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Author SHA1 Message Date
Ian Romanick
2b77d8afa7 nir/loop_unroll: Always unroll loops that iterate at most once 
Two carchase compute shaders (shader-db) and two Fallout 4 fragment
shaders (fossil-db) were helped.  Based on the NIR of the shaders, all
four had structures like

    for (i = 0; i < 1; i++) {
        ...

	for (...) {
            ...
	}
    }

All HSW+ platforms had similar results. (Ice Lake shown)
total loops in shared programs: 6033 -> 6031 (-0.03%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2
HURT: 0

All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 143692018 -> 143692006 (-0.0%)
SENDs in all programs: 6947154 -> 6947154 (+0.0%)
Loops in all programs: 38285 -> 38283 (-0.0%)
Cycles in all programs: 8434822225 -> 8434476815 (-0.0%)
Spills in all programs: 191665 -> 191665 (+0.0%)
Fills in all programs: 298822 -> 298822 (+0.0%)

In the presense of loop unrolling like this, the change in cycles is not
accurate.

v2: Rearrange the logic in the if-condition to read a little better.
Suggested by Tim.

Closes: #5089
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit ae99ea6f4d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13366>
 2021-10-20 20:40:57 +01:00
Eric Engestrom
f774768d17 .pick_status.json: Mark 7a2e40df5e as denominated 2021-10-20 20:40:57 +01:00
Eric Engestrom
1cf264d89d .pick_status.json: Update to 86b3d8c66c 2021-10-20 20:40:41 +01:00
Eric Engestrom
2dc6aa567f VERSION: bump for 21.3.0-rc1 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
mesa-21.3.0-rc1 		2021-10-13 20:59:03 +01:00
Kenneth Graunke
02435f1294 iris: Require a 4K alignment for extra clear color BOs. 
Apparently, we've been requiring a 4K alignment for internally allocated
clear color addresses to work around some unknown issues.  There's a
comment to that effect in iris_resource_create_with_modifiers().

When importing a dmabuf and tacking on an additional clear color BO, we
only required an alignment of 1.  This wasn't a problem for a long time
because all BO allocations were naturally aligned to the 4K page size.

However, once we enabled suballocation, we were able to allocate "BOs"
at 256B granularity, making this no longer 4K aligned.  Increase the
alignment requirement to 4K to match the behavior of our normal
allocations and also our previous behavior.

Fixes Piglit's ext_image_dma_buf_import-intel-modifiers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5482
Fixes: ce2e2296ab ("iris: Suballocate BO using the Gallium pb_slab mechanism")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13326>
21.3-branchpoint 		2021-10-13 18:46:03 +00:00
Caio Marcelo de Oliveira Filho
94e07058ee intel/compiler: Remove unused ret declaration 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
 2021-10-13 17:24:29 +00:00
Caio Marcelo de Oliveira Filho
bd2cc4b916 intel/compiler: Convert test_eu_compact to use gtest 
Be consistent with the other test suites in intel/compiler.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>
 2021-10-13 17:24:29 +00:00
Mike Blumenkrantz
420e33f551 radv: move alpha_adjust into conditional during vertex input updating 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
 2021-10-13 17:03:26 +00:00
Mike Blumenkrantz
1b8bdecf6e radv: add a mask of bound descriptor buffers for dynamic vertex input 
unnecessarily dereferencing the vertex buffer info array here causes a
ton of cpu overhead due to bad cache locality, so just use a mask to
avoid loading X more cachelines into memory unnecessarily

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
 2021-10-13 17:03:26 +00:00
Mike Blumenkrantz
eda5634e25 radv: pre-calc "simple" dynamic vertex input values 
when the shader pipeline is known to not require any of the more complex
calculations, those calculations can be excluded from the dynamic update
code

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
 2021-10-13 17:03:26 +00:00
Mike Blumenkrantz
c335a4d70e radv: dynamically calculate misaligned_mask for dynamic vertex input 
this avoids incurring overhead at draw time, instead shifting it to vertex
binding commands

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
 2021-10-13 17:03:26 +00:00
Mike Blumenkrantz
90d9c8dc62 radv: don't use invalid stride for triggering vertex state change 
NULL here means this was regular CmdBindVertexBuffers, so the stride
cannot be used

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>
 2021-10-13 17:03:26 +00:00
Adam Jackson
27054f737a egl/dri: Enable FP16 for EGL_EXT_platform_device 
Why is this not the same code as EGL_MESA_platform_surfaceless.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13182>
 2021-10-13 16:36:27 +00:00
Adam Jackson
ea038747df dri: Remove the allow_fp16_configs option, always allow them 
There's no danger of accidentally using these, the default pixel format
is integer and if you want float you need to have explicitly asked for
it in eglChooseConfig.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13182>
 2021-10-13 16:36:27 +00:00
Adam Jackson
b01fe97a39 wsi/x11: Fetch and discard the SYNC extension info 
Since we're not checking for this, xcb has to do it for us the first
time we call xcb_sync_destroy_fence, which puts a blocking round-trip in
the swapchain destroy path for no reason. Check for the extension so we
have the extension's opcode cached when we need it.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13339>
 2021-10-13 16:11:11 +00:00
Lone_Wolf
ebfbb42e0e clover: TargetRegistry.h was moved to another folder 
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13290>
 2021-10-13 15:41:49 +00:00
Emma Anholt
cdc009f5aa Revert "ci: Add osmesa to Windows GitLab CI" 
This reverts commit 90faabc0ee.  It has been
flaky and producing timeouts.  (See
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/14634204 for an example)

Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13318>
 2021-10-13 15:01:52 +00:00
Lionel Landwerlin
9fb2c84768 isl: only bump the min row pitch for display when not specified 
If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3a4517f41 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
 2021-10-13 14:46:49 +00:00
Lionel Landwerlin
47ff6767ea anv: fill correct surface state for lowered storage image 
Small typo/copy-paste.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c0093c4668 ("anv: Flip around the way we reason about storage image lowering")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13332>
 2021-10-13 14:33:14 +00:00
Bas Nieuwenhuizen
fd8210f27e radv: Try to do a better job of dealing with L2 coherent images. 
Only try to invalidate L2 if we actually hit one of the incoherent images.

Note we may actually insert some extra flushes at the end of a command
buffer so that we may asume the caches are clean the start of the next
command buffer. However, on average I think that case is uncommon
enough that being able to make assumptions at the start of a cmdbuffer
is beneficial. Especially since MSAA is somewhat rare in more recent
games.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
 2021-10-13 14:07:05 +00:00
Bas Nieuwenhuizen
64b237436a radv: Add hooks after in-renderpass meta operations. 
So that we can mark the rendertargets dirty.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
 2021-10-13 14:07:05 +00:00
Bas Nieuwenhuizen
3de7ba13f5 radv: Document cache coherency rules. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
 2021-10-13 14:07:05 +00:00
Hyunjun Ko
30b4911031 turnip: enable strictLines 
Now we can enable strictLines as we set rectangular lines by default.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
 2021-10-13 12:18:01 +00:00
Hyunjun Ko
542211676c turnip: enable VK_EXT_line_rasterization 
By default line mode is VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
when lineRasterizationMode is VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
and primtype is line - we enable bresenham line mode.

We have to disable MSAA when bresenham lines are used, this is
a hardware limitation and spec allows it:

  "When Bresenham lines are being rasterized, sample locations may
   all be treated as being at the pixel center (this may affect
   attribute and depth interpolation)."

This forces us to re-emit msaa state when line mode is changed.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
 2021-10-13 12:18:01 +00:00
Hyunjun Ko
88afceacf0 freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL 
This bit seems like the control for line mode of rastrization.

That can be simply figured out by comparing
dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines,
dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and
dEQP-VK.rasterization.primitives.no_stipple.lines.

For opengl, the value of bresenham lines mode, which is 0, is set
by default and the value of rectangular mode, which is 0x1, is set
when multi-sampled.

For vulkan, the bresenham lines are enabled when lineRasterizationMode is
VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while
the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
that seems to be default.

If both multi-sampled and bresenham-lines are used when primitive type is
line, the bit is to be set as 0 and makes msaa disabled.

Note that this is only tested on a6xx, but I guess it's likely the same
for a5xx.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
 2021-10-13 12:18:01 +00:00
Tapani Pälli
d729038c07 anv: use vk_object_zalloc for wsi fences created 
Otherwise we hit assert in vk_object_base_assert_valid when attemping to
create handle from anv_fence with unknown base type.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13330>
 2021-10-13 11:59:17 +00:00
Emma Anholt
4721352f97 radeonsi: Fix leak of screen->perfcounters. 
A refactor dropped one of the frees.

Fixes: 380ac28891 ("ac: import performance counters from RadeonSI")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13322>
 2021-10-13 11:01:19 +00:00
Yipeng Chen (Jasber)
33484a327e radeonsi: do not use staging texture for APU 
This is to fix serious performance drop of texture_upload/
texture_resue relative items in chromeos glbench test.
Staging texture is not efficient for CPU uploading.

Signed-off-by: Jasber Chen <yipeng.chen@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13306>
 2021-10-13 10:45:04 +00:00
Marek Olšák
80efe661d7 radeonsi: simplify write_psize code in si_get_vs_out_cntl 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
 2021-10-13 10:28:14 +00:00
Marek Olšák
824d9bed4f radeonsi: simplify how VS_OUT_CCDIST is set 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
 2021-10-13 10:28:14 +00:00
Arvind Yadav
8f9945a75b radeonsi: remove the use of PKT3_CONTEXT_REG_RMW 
This patch is to to remove PKT3_CONTEXT_REG_RMW from radeonsi.
and avoid multiple command buffer(PM4 packet)creation for R_02881C_PA_CL_VS_OUT_CNTL.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
 2021-10-13 10:28:14 +00:00
Timur Kristóf
411c081e97 drirc: Apply radv_invariant_geom workaround to World War Z games. 
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5433
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
 2021-10-13 08:55:33 +00:00
Timur Kristóf
bbce747a0d drirc: Apply radv_invariant_geom workaround to Resident Evil Village. 
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5071
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
 2021-10-13 08:55:33 +00:00
Timur Kristóf
574c6612ae drirc: Fix indentation. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13312>
 2021-10-13 08:55:33 +00:00
Marek Olšák
84d0f54e75 ac/surface: enable better display DCC for chips newer than Yellow Carp 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
 2021-10-13 06:20:13 +00:00
Marek Olšák
a18a7626a2 ac/surface: disallow display DCC for big resolutions 
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
 2021-10-13 06:20:13 +00:00
Marek Olšák
1a8df6f1be ac/surface: always use suboptimal display DCC with DRM <= 3.43.0 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13214>
 2021-10-13 06:20:13 +00:00
Tapani Pälli
840c79fc9b anv/android: fix parameters given for vk_common_QueueSubmit 
Common queue submit expects pWaitDstStageMask to be set per each
semaphore (as per Vulkan spec) and crashes if these are not given
properly.

This fixes crashes seen when running vulkan apps on Android.

v2: change the VkPipelineStageFlags given (Lionel)

Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13305>
 2021-10-13 06:00:56 +00:00
Kyle Brenneman
e28ce12afa Remove the shebang from eglFunctionList.py. 
eglFunctionList.py isn't executed directly, so it doesn't need a shebang
line.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13130>
 2021-10-13 05:34:27 +00:00
Kyle Brenneman
06309e0f26 Add copyright comments to the GLVND-related files. 
A few of the GLVND-related files were missing a copyright comment at the
top. Copy the same MIT license text from gen_egl_dispatch.py et. al.

https://gitlab.freedesktop.org/mesa/mesa/-/issues/5267

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13130>
 2021-10-13 05:34:27 +00:00
Rhys Perry
d9c7a17542 radv: enable VK_EXT_vertex_input_dynamic_state 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4768
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
d3c0cbbc84 radv: implement VK_EXT_vertex_input_dynamic_state 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
d45958f82e aco: implement VS input loads with prologs 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
f4ea2d7887 aco: implement aco_compile_vs_prolog 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
f6f6f18e55 radv: add pre-compiled vertex shader prologs for common states 
This lets us pre-compile a prolog and avoid a hash table lookup during
command buffer recording, most of the time.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
80841196b2 radv: implement dynamic vertex input state using vertex shader prologs 
This doesn't actually use the functionality or implement prolog
compilation yet.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
2b8d88ed91 radv: move VS specific input SGPRs first 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
a1069b8bd4 radv: add segregated fit shader memory allocator 
Way faster than the previous one, especially with a large number of
shaders.

This doesn't have much of an effect right now, but the previous allocator
was expensive compared to the cost of compiling vertex shader prologs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
404752bfb2 radv: add radv_shader_variant_get_va and radv_find_shader_variant helpers 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Rhys Perry
d1f09419b4 radv: add radv_translate_vertex_format() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00