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763 Commits

Author SHA1 Message Date
Dave Airlie
5591651b9e vulkan/video: fix vui encoding 
This is a single bit field.

Fixes: d46162981a ("vulkan/video: add h264 headers encode")
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Tested-by: Bernhard C. Schrenk <clemy@clemy.org>
Reviewed-by: Bernhard C. Schrenk <clemy@clemy.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30968>
(cherry picked from commit af425a63f7)
 2024-09-05 12:54:35 -07:00
Samuel Pitoiset
6460525c7a radv: fix emitting DGC indirect draws with drawid/base_instance 
This fixes test_execute_indirect_state_vbo_offsets, a new vkd3d-proton
test.

The drawid/base_instance bits were cleared by mistake.

Fixes: e59a16bbb8 ("radv: use an indirect draw when IBO isn't updated as part of DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30971>
(cherry picked from commit 8873382703)
 2024-09-05 12:54:35 -07:00
Dylan Baker
2a9a45784c .pick_status.json: Update to 4aa1259eb4 2024-09-05 12:54:35 -07:00
Jordan Justen
68dd5f4860 intel/dev: Update hwconfig => max_threads_per_psd for Xe2 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30887>
(cherry picked from commit 3e4f73b3a0)
 2024-08-30 12:27:39 +02:00
Valentine Burley
41ae715026 tu: Fix VK_EXT_extended_dynamic_state3 feature 
Don't claim to support extendedDynamicState3SampleLocationsEnable on pre-A650 GPUs,
which can't advertise VK_EXT_sample_locations.

Fixes dEQP-VK.info.device_mandatory_features on A6xx Gen 1 and Gen 2.

Fixes: 84726da2f4 ("tu: Implement extendedDynamicState3SampleLocationsEnable")
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30730>
(cherry picked from commit 98d52cf292)
 2024-08-30 12:27:22 +02:00
Lionel Landwerlin
6121239034 iris: fix utrace compute end timestamp reads on Gfx20 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30923>
(cherry picked from commit 91b3ae71d7)
 2024-08-30 12:25:10 +02:00
Lionel Landwerlin
56d048a4ac anv: fix utrace compute timestamp reads on Gfx20 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30923>
(cherry picked from commit 14d772d678)
 2024-08-30 12:23:41 +02:00
Job Noorman
7291e2fb08 ir3: fix recognizing const/imm registers as a0 
Fixes: 72bb4d79dc ("ir3/legalize: handle scalar ALU WAR hazards for a0.x")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30611>
(cherry picked from commit 7cc24aa506)
 2024-08-30 12:20:16 +02:00
Roland Scheidegger
2950194ea6 llvmpipe: Fix type mismatch when storing residency info 
The storage allocated was always the same for both the ordinary texture
result data as well as the residency info. However, the former can be
float vector, whereas the latter is always int vector.
At least some llvm versions/builds will assert on this mismatch when
storing the data.
While here, also cut unnecessary zero initialization (lp_build_alloca()
already explicitly does this).

Fixes: 6168317b84 (lavapipe: Implement shaderResourceResidency)

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30878>
(cherry picked from commit 9b717596b2)
 2024-08-30 12:13:38 +02:00
Eric Engestrom
8b277994be .pick_status.json: Update to 3e4f73b3a0 2024-08-30 12:11:20 +02:00
Rohan Garg
ff6d97f84a anv: prefetch samplers when dispatching compute shaders 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30922>
(cherry picked from commit 32f606486f)
 2024-08-29 18:42:37 +02:00
Konstantin Seurer
be036a778a nir/opt_loop: Fix handling else-breaks in merge_terminators 
If both breaks are in the else branch, we have to use iand.

Fixes: 9995f33 ("nir: add merge loop terminators optimisation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11726
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30850>
(cherry picked from commit 0fc3c52e43)
 2024-08-29 18:42:37 +02:00
Tapani Pälli
8390fe9932 anv: set correct miplevel for anv_image_hiz_op 
Fixes: 5efecc9782 ("anv: Enable HiZ on multi-LOD depth buffers.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11787
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30892>
(cherry picked from commit 44e1cf2748)
 2024-08-29 18:42:37 +02:00
Faith Ekstrand
a98bd06d98 nvk: Hash minSampleShading in nvk_hash_graphics_state() 
We put minSampleShading in the nvk_shader and [de]serialize that to/from
the binary so it also needs to go in the hash.  We could also plumb the
pipeline state through to the deserialize callback but that's quite a
stretch and this literally only affects minSampleShading which is a
rarely used feature.

Fixes: 813b253939 ("nvk: Switch to shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30914>
(cherry picked from commit 5f402f3aae)
 2024-08-29 18:42:36 +02:00
Faith Ekstrand
b336bc37e6 vulkan/pipeline: Handle VIEW_INDEX_FROM_DEVICE_INDEX_BIT 
The rehash we're doing here is a bit of a hack but it's a back-portable
hack.  We'll fix it properly in following commits.

Fixes: 9308e8d90d ("vulkan: Add generic graphics and compute VkPipeline implementations")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30876>
(cherry picked from commit c0191b20de)
 2024-08-29 18:42:36 +02:00
Iván Briano
c3cdff396e nir: add pass to convert ViewIndex to DeviceIndex 
Used to implement VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30329>
(cherry picked from commit 7fce39484e)
 2024-08-29 18:42:36 +02:00
Eric Engestrom
467e26382d .pick_status.json: Mark 033818fdd9 as denominated 2024-08-29 17:34:13 +02:00
Eric Engestrom
972eabb37e .pick_status.json: Mark 4888d39f29 as denominated 2024-08-29 17:34:08 +02:00
Eric Engestrom
369c1fd495 etnaviv/ci: fix gc2000_piglit test timeout 
Setting it to the same value as (or higher than) the job timeout
effectively bypasses the safety mechanism.

Let's change it to `job timeout - 5min`.

Fixes: f39ffc6911 ("ci/etnaviv: Get the gc2000_piglit manual job mostly working.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
(cherry picked from commit b978d3eb54)
 2024-08-29 17:32:38 +02:00
Eric Engestrom
b4f0699dfb v3dv/ci: fix test timeout for v3dv-rpi5-vk-full:arm64 
It was set to 170min, which made sense when the job timeout was 3h, but
then 4bb564f40d ("broadcom/ci: add more jobs to test with rpi5")
lowered the job timeout to 2h without lowering the test timeout to match.

Fixes: 4bb564f40d ("broadcom/ci: add more jobs to test with rpi5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
(cherry picked from commit aac9c74a83)
 2024-08-29 16:49:41 +02:00
Kenneth Graunke
a7b7b8753a intel/brw: Fix extract_imm for subregion reads of 64-bit immediates 
We could be trying to extract a D/UD from a Q/UQ, for example.  We were
ignoring the top 32-bits, which is incorrect.

Fixes: 580e1c592d ("intel/brw: Introduce a new SSA-based copy propagation pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30884>
(cherry picked from commit da395e6985)
 2024-08-29 16:30:16 +02:00
Kenneth Graunke
139398f124 intel/brw: Drop misguided sign extension attempts in extract_imm() 
This function never expands a type - it only narrows it.  As such, we
don't need to ever sign extend to fill additional new bits.  I think
this code was left over from earlier versions of my optimization pass
that was buggy and trying to handle cases it should not have.

Fixes: 580e1c592d ("intel/brw: Introduce a new SSA-based copy propagation pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30884>
(cherry picked from commit 51c85e0363)
 2024-08-29 16:30:13 +02:00
Jesse Natalie
b558fb259e d3d12: Don't use a vertex re-ordering GS for line primitives 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30903>
(cherry picked from commit dac44e02f7)
 2024-08-29 16:29:25 +02:00
Eric Engestrom
25482678a6 .pick_status.json: Update to 51e05c2844 2024-08-29 16:29:23 +02:00
David Heidelberg
e79cfc71d2 bin/gen_release_notes: adjust checksums section 
We currently provide SHA256 and SHA512, differenciated by length.

Cc: mesa-stable
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30897>
(cherry picked from commit 83b74bfc6d)
 2024-08-28 20:33:17 +02:00
Eric Engestrom
debaa0b5f6 .pick_status.json: Update to 64ca0fd2f2 2024-08-28 20:33:17 +02:00
Rhys Perry
be09c4aeb3 aco: preserve bitsets after a lane mask is written 
fossil-db (navi31):
Totals from 4840 (6.10% of 79395) affected shaders:
Instrs: 13733449 -> 13761177 (+0.20%); split: -0.00%, +0.21%
CodeSize: 71997868 -> 72102520 (+0.15%); split: -0.00%, +0.15%
Latency: 128385177 -> 128408780 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 21105847 -> 21109475 (+0.02%); split: -0.00%, +0.02%
VALU: 7741209 -> 7741210 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
(cherry picked from commit 11262a01ce)
 2024-08-28 20:33:17 +02:00
Rhys Perry
121e202516 aco: check SALU writing lanemask later for VALUMaskWriteHazard 
This should be done after reads are checked and
sgpr_read_by_valu_as_lanemask_then_wr_by_salu is reset. The old version
also skipped checking the reads if the write check passed.

fossil-db (navi31):
Totals from 193 (0.24% of 79395) affected shaders:
Instrs: 3212435 -> 3212735 (+0.01%)
CodeSize: 16462868 -> 16463848 (+0.01%); split: -0.00%, +0.01%
Latency: 19492377 -> 19492462 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 4419705 -> 4419718 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
(cherry picked from commit 61e73c2323)
 2024-08-28 20:33:17 +02:00
Rhys Perry
7508807d52 aco: don't consider sa_sdst=0 before SALU write to fix VALUMaskWriteHazard 
LLVM does but that's probably a bug.

fossil-db (navi31):
Totals from 311 (0.39% of 79395) affected shaders:
Instrs: 380453 -> 381075 (+0.16%)
CodeSize: 1961012 -> 1964744 (+0.19%)
Latency: 4799095 -> 4800313 (+0.03%)
InvThroughput: 958358 -> 958904 (+0.06%)
VALU: 242322 -> 242633 (+0.13%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
(cherry picked from commit b1ba7d1b99)
 2024-08-28 20:33:17 +02:00
Rhys Perry
79ff5008c7 aco: also consider VALU reads for VALUMaskWriteHazard 
fossil-db (navi31):
Totals from 9776 (12.31% of 79395) affected shaders:
Instrs: 19348258 -> 19383680 (+0.18%); split: -0.00%, +0.19%
CodeSize: 101223460 -> 101366964 (+0.14%); split: -0.01%, +0.15%
Latency: 172853115 -> 172866070 (+0.01%); split: -0.01%, +0.01%
InvThroughput: 27590468 -> 27592390 (+0.01%); split: -0.00%, +0.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11550
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11436
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11337
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11738
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11741
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
(cherry picked from commit 8f5ee70d85)
 2024-08-28 20:33:17 +02:00
Rhys Perry
e0e7bfadee aco: ignore exec and literals when mitigating VALUMaskWriteHazard 
LLVM ignores exec and literals don't seem to work in some cases.

fossil-db (navi31):
Totals from 2676 (3.37% of 79395) affected shaders:
Instrs: 10638979 -> 10646019 (+0.07%); split: -0.00%, +0.07%
CodeSize: 55929640 -> 55959416 (+0.05%); split: -0.00%, +0.06%
Latency: 107707408 -> 107712893 (+0.01%); split: -0.00%, +0.01%
InvThroughput: 18119843 -> 18120442 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Backport-to: 24.1
Backport-to: 24.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
(cherry picked from commit ee648326d9)
 2024-08-28 20:33:17 +02:00
Lionel Landwerlin
cbee9e7a88 brw: switch mesh/task URB fence prior to EOT to GPU 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30849>
(cherry picked from commit 93fba40389)
 2024-08-28 15:52:41 +02:00
Yiwei Zhang
c6187962a2 venus: workaround cacheline overflush issue on Intel JSL 
We observed that Venus on ANV on JSL platform has some cacheline flush
issue. The overflush shows up as:
1. There're 2 threads venus bliting the feedback buffers suballocated
   from the same backing device memory, back to back.
2. On thread A, flushing the feedback buffer for cpu read is placed
   behind flushing a shader storage buffer for cpu read.
3. On thread B, flushing a different feedback buffer with the same
   backing device memory (different offset bound to) can kick the
   feedback buffer flush in (2) earlier than it should be flushed.
4. As a result, CPU polling thread for thread B results would see venus
   feedback buffer update earlier than shader storage buffer results
   being updated, breaking Venus sync primitives optimization.

During investigation, a solid workaround for JSL platform is to force
Venus to align up to 128 bytes for feedback buffer suballocation while
the default is at 64 bytes.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30879>
(cherry picked from commit 7941d705c3)
 2024-08-28 15:31:32 +02:00
bbhtt
83e71e0ebd pipe_loader_drm: Fix virtgpu_drm header path 
Fixes: 2ea4a59ab7 ("loader: Add better
support for virtgpu nctx driver loading")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30673>
(cherry picked from commit 284ad7da39)
 2024-08-28 15:31:31 +02:00
Eric Engestrom
da70827656 vc4: Add missing libvc4_neon build dependencies 
Duplicates the libvc4 dependencies.

Fixes: ebcb4c2156 ("meson: Enable VC4's NEON assembly support.")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Co-authored-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30819>
(cherry picked from commit fda6f8638a)
 2024-08-28 15:31:25 +02:00
Sviatoslav Peleshko
dcfb085a6a anv: Add full subgroups WA for the shaders with barriers in Breaking Limit 
When barriers are used in invalid shaders with non-uniform control flow
we might get a hang. Forcing 32-wide group can help by making it more
probable that barrier instruction is executed by at least one channel
in each thread, and thus hang will be avoided. This shouldn't affect
Xe2+, where active-thread-only barriers are used anyway.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11497
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
(cherry picked from commit 7e52b67801)
 2024-08-28 15:31:23 +02:00
Sviatoslav Peleshko
97fdcffb0c anv: Release correct BO in anv_cmd_buffer_set_ray_query_buffer 
If p_atomic_cmpxchg doesn't set the ray_query_shadow_bos[bucket] to new_bo
allocated by this thread, it returns the bucket BO allocated by the other
thread and we use it. But due to a mistake, we also release that BO, not
the candidate just allocated by this thread and never used again.

Fixes: 5d3e4193 ("anv: enable ray queries")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
(cherry picked from commit 1904fe1186)
 2024-08-28 14:26:48 +02:00
Sviatoslav Peleshko
f6432697e7 brw,elk: Fix opening flags on dumping shader binaries 
Truncation is needed for overwriting correctly in cases when old file is
bigger than the one we want to dump (e.g. when the old one was edited
inplace). Also, creation permissions are way too broad.

Fixes: 4f41c44d ("intel/compiler: Add variable to dump binaries of all compiled shaders")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
(cherry picked from commit 09122e2be0)
 2024-08-28 14:26:47 +02:00
Eric Engestrom
a24002fc1a .pick_status.json: Update to 7392e3306e 2024-08-28 14:26:41 +02:00
David Rosca
afb9e01454 frontends/va: Fix leaks with multiple coded buffer segments 
The buffers can be reused, so we must only allocate added segments
and free unused segments.

Fixes: be4287c3aa ("pipe: Extend get_feedback with additional metadata")
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30779>
(cherry picked from commit 1ebff2220d)
 2024-08-27 09:25:38 +02:00
Lionel Landwerlin
7d7a9cce41 nir/divergence: add missing load_constant_base_ptr 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30712>
(cherry picked from commit 2158fe2ae2)
 2024-08-27 09:25:15 +02:00
Faith Ekstrand
56a5cf145e nil,nvk: Disable modifiers for B10G11R11_UFLOAT and E5B9G9R9_UFLOAT 
The CTS tests fail due to precision issues (arguably a CTS bug) but it
also doesn't make a lot of sense to advertise modifiers on them at all.

Fixes: cd428e01d7 ("nvk: Advertise VK_EXT_image_drm_format_modifier")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30861>
(cherry picked from commit b78a691ce2)
 2024-08-27 09:08:38 +02:00
Lionel Landwerlin
c64ba9c8d3 anv: always use workaround_address, not workaround_bo 
The workaround BO has some debug information at the beginning. The
workaround address is placed after that.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30844>
(cherry picked from commit d8ec8acede)
 2024-08-27 09:08:29 +02:00
Dave Airlie
87ea4ab7d2 llvmpipe: make sure to duplicate the fd handle before giving out 
This handle is given to the user to close, so make sure to dup it
first.

Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30839>
(cherry picked from commit 4bf257a18f)
 2024-08-27 09:08:28 +02:00
Dave Airlie
6cd669911e llvmpipe: handle stride properly on lvp udmabuf imports 
The import data comes in via the fd import, but we need to make
sure to store the row stride value here.

Fixes: c44d65a467 ("lp: only map dt buffer on import from dmabuf")
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30839>
(cherry picked from commit 521dc42e6c)
 2024-08-27 09:08:27 +02:00
Mike Blumenkrantz
631732e3df dril: add zink stub 
ironically this was the only driver left out

Fixes: 3de62b2f9a ("gallium/dril: Compatibility stub for the legacy DRI loader interface")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30851>
(cherry picked from commit 786be05df3)
 2024-08-27 09:08:26 +02:00
Valentine Burley
6acc836b91 llvmpipe: Only use udmabuf with libdrm 
It's possible to have the linux/udmabuf.h header but not libdrm in some setups, like under Termux.

Fixes: 112063a060 ("llvmpipe: Only use udmabuf if header is found")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30853>
(cherry picked from commit 4cfaf10c10)
 2024-08-27 09:08:25 +02:00
Lionel Landwerlin
5eb0a7d809 anv: explicitly disable BT pool allocations at device init 
The default state doesn't seem well defined (or kernel driver bug
maybe?). Let's just set it to disabled on platforms where we're not
using it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Found-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30841>
(cherry picked from commit 1f9c40a8d1)
 2024-08-27 09:08:24 +02:00
Dave Airlie
591cfcaf79 radv/video: fix reporting video format props for encode. 
When encode isn't enabled, refuse the image usage, also use
the correct error on the decode check.

Fixes: 05cd42417f ("radv/video: enable video encoding behind perftest flag")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30838>
(cherry picked from commit 68cd36d9b4)
 2024-08-27 09:08:23 +02:00
David Heidelberg
71812c26ea etnaviv: build dependency for the etnaviv tests 
Resolves failures as:
... -o src/etnaviv/isa/tests/etnaviv_disasm.p/disasm.cpp.o -c ../src/etnaviv/isa/tests/disasm.cpp
In file included from ../src/etnaviv/isa/tests/disasm.cpp:12:
../src/etnaviv/isa/asm.h:15:10: fatal error: etnaviv/isa/enums.h: No such file or directory
   15 | #include "etnaviv/isa/enums.h"
      |          ^~~~~~~~~~~~~~~~~~~~~

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11740
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30829>
(cherry picked from commit 8f8a51ac5c)
 2024-08-27 09:08:23 +02:00