When updating an AFBC-packed resource, the size of the resulting
texture data can change while the BO and modifier stay the same. We
still need to update the texture descriptor in that situation so
that the size is properly reported. Having a smaller size than the
real one might cause artifacts as the GPU doesn't want to read past
the reported size.
A future (more foolproof) fix might involve having a hash key to
track the size of all slices independently, but this patch still
improves the situation and make sure we don't hit a relatively
common issue when using `PAN_MESA_DEBUG=forcepack`.
Fixes: bc55d150a9 ("panfrost: Add support for AFBC packing")
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 30825140d0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
A next patch will emit more instructions in video and copy queues
for Gfx 200 and newer but the current code only creates anv_async_submit
if device has aux_map.
Instead we can always create anv_async_submit and only submit it to
hardware if any instruction was emited.
Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit b8f93bfd38)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Last VGT stages (VS, TES or GS) can always be used with a null FS when
nextStage is non-zero. Like if a VS is created with nextStage=TCS, it's
also allowed to draw without binding a CTS (ie. nextStage=None is always
a valid case).
Because we don't want to compile two variants for NONE and FRAGMENT,
let's compile only the FRAGMENT one when necessary.
Fixes new CTS coverage, see https://gerrit.khronos.org/c/vk-gl-cts/+/15976.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 0223f0f54d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
With the introduction of the slab allocator, most of our small
allocations now hit that rather than directly hitting the bucket
cache. Those now show up as 2MB slab allocations from the cache's
perspective. So, we don't need quite as many buckets. (Note that
only allocations in IRIS_MEMZONE_OTHER are suballocated today.)
Previously, we had 55 buckets, going from 4KB to 112MB, with sizes
N, N+1/4, N+1/2, N+3/4 for a series of power-of-two N's.
This patch prunes it down to 25 buckets:
- 4K-4MB => power-of-two sizes only
- 6MB => a one-off bucket to reduce waste between 4MB and 8MB
- 8MB+ => the usual N, N+1/4, N+1/2, N+3/4 system
- 64MB => the largest bucket size
In particular, this eliminates the 1.75MB, 2.5MB, 3MB, 3.5MB, and 7MB
buckets in favor of multiples of 2MB. Allocating multiples of 2MB is
preferable because it allows the kernel to allocate 64KB pages rather
than being stuck using inefficient 4K pages. And, the amount of waste
from bumping to the next multiple of 2MB isn't huge in that range of
sizes. We also eliminate buckets larger than 64MB because they're
rarely used, and also the amount of waste from rounding up to the
80/96/112MB buckets can get pretty large.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 0b6693a3a1 ("iris: Align fresh BO allocations to 2MB in size")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10219
(cherry picked from commit d85d6ad2a5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
It's allowed to place OpExecuteCallableKHR in a SPIR-V, even if the RT
pipeline doesn't contain any callable shaders. Unreal hits this case and
crashes. We can assume the intrinsic never gets executed, so we can
simply remove it.
Cc: mesa-stable
(cherry picked from commit 0c02a7e8e8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
The current assertion fails as soon as a MAD with src0 and src2 being
immediate is detected.
The assertion was supposted to catch, "If it's ADD3, only one of src0
and src2 can be immediate." The detect this, the opcode test should have
been !=.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: c1c09e3c4a ("brw/emit: Add correct 3-source instruction assertions for each platform")
(cherry picked from commit c52ce6157f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Some callers of brw_constant_fold_instruction depend on the result being
a MOV of immediate when progress is made. Previously `MUL dst:D src0:D
1:D` would be converted to `MOV dst:D src0:D`. There was also no
handling for `MUL dst:D imm0:D imm1:D`.
This could cause problems if one of the immedate values was -1. The
existing code would convert this to a `MOV dst:D imm0:D` and set the
negate flag on src0. That is not correct.
v2: Fix the is_negative_one case handling of the non-negative-one
source. Add a comment explaining the assertion. Both suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 2cc1575a31 ("brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic")
(cherry picked from commit 25de9dcd76)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Some callers of brw_constant_fold_instruction depend on the result being
a MOV of immediate when progress is made. Previously `ADD dst:D src0:D
0:D` would be converted to `MOV dst:D src0:D`. There was also no
handling for `ADD dst:D imm0:D imm1:D`.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 2cc1575a31 ("brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic")
(cherry picked from commit 086e83ccd9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
In this case, num_sources is bigger than this->sources, so if we loop
up to num_sources (instead of this->sources) we'll end up reading past
the end of old_src[]. Only copy up to what we originally had.
This was found by code inspection, I'm not aware of any applications
failing due to the lack of this patch.
Fixes: d9e737212d ("intel/brw: Add a src array for the common case in fs_inst")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit d4a54d4f92)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Rather than checking hwconfig items when using them, wait until after
devinfo has been fully initialized. This includes having workarounds
implemented.
We can then check if the hwconfig data and final Mesa initialization
agree. If the match fails, we need to investigate if Mesa or the
hwconfig data is wrong.
This code becomes a no-op when not on a release build.
Fixes: a4c5bfd34c ("intel/dev: Use hwconfig for urb min/max entry values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12141
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 1027b071f9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Unscissored glClearColor is using i915_fill_blit().
Clearing can be done with the 1 byte formats
GL_ALPHA, GL_LUMINANCE or GL_INTENSITY.
Routine i915_fill_blit() is called with a rgba-mask containing
1 byte, but it is handling this as a 2-byte color.
This fix adds the needed 1 byte setup to both
i915_fill_blit() and i915_copy_blit().
It solves 1 piglit-test concerning arb_clear_texture-base-formats
and 15 tests concerning fbo-clear-formats.
No regression is shown at other piglit-tests.
Cc: mesa-stable
Signed-off-by: GKraats <vd.kraats@hccnet.nl>
(cherry picked from commit bed66430ab)
Conflicts:
src/gallium/drivers/i915/ci/i915-g33-fails.txt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
VRS rates should only be preserved for clears, otherwise the HTILE
buffer should be cleared completely.
This fixes some failures/flakes in CI.
Fixes: 8197d744f5 ("radv: Do not overwrite VRS rates when doing fast clears")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8b755840fc)
Conflicts:
src/amd/vulkan/meta/radv_meta_clear.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
The override used for the immed encoding in #cat3-src-const-or-immed
used a pattern which isn't supported in overrides by isaspec. The
pattern in the base bitset (10) was too strict for immediates since it
didn't allow the most significant bit to be 1.
Fix this by making the base pattern 1 and adding an assert for the next
bit to be 0 in the non-immed case.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 1c6c200c0d ("ir3: add newly found shlg.b16 instruction")
(cherry picked from commit 943f666b69)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
When a timestamped present is not used (MAILBOX or the very first present),
it's possible that the very last queued present ID won't complete in finite time.
Similar to frame callback based workaround, apply a timeout to present
waits when they target the very last submitted presentID.
Only apply the workaround when we're not guaranteed forward progress.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Derek Foreman <derek.foreman@collabora.com>
(cherry picked from commit c3becade15)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
