fran/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
204,852 Commits 63 Branches 889 Tags
bisect-temp
Commit Graph

204852 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Caleb Callaway
92170f6fc1 iris: ISP invalidate at end of compute batches 
We're now re-emitting push constants at the
start of compute batches, so we can avoid the
overhead of restoring them.

CC: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35873>
(cherry picked from commit 6f38d58db3)
 2025-07-15 16:19:55 +02:00
Caleb Callaway
1c2c5559de iris: re-emit push constants at compute batch start 
Per Ken Graunke, corruption issues with push
constants for render batches on Gen12 graphics
have been observed and worked around by re-emitting
push constants at the start of the batch buffer.
We're seeing similar issues with compute batches,
so we'll apply the same work-around.

Fixes corruption reported in Blender on ADL/RPL

CC: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35873>
(cherry picked from commit 8fd008a45f)
 2025-07-15 16:19:55 +02:00
Yiwei Zhang
9f4368e394 anv: avoid leaking private binding for aliased wsi image 
Aliased wsi image has to share the same private binding with the
original wsi image for memory consistency. If the private binding
exists, it needs to be released before being overridden.

Fixes: d85a9d658f ("anv/image: Call into WSI to create swapchain images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35893>
(cherry picked from commit b21e62b71a)
 2025-07-15 16:19:55 +02:00
Mary Guillemard
5c71a3db0f pan/genxml: Fix wrong size for compute size workgroup 
Fix annoying warnings when decoding CSF.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 486c341769 ("panfrost: Add architecture description XML for v10")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35909>
(cherry picked from commit a3272cd0ce)
 2025-07-15 16:19:55 +02:00
Erik Faye-Lund
094e9e4e83 st/pbo: use sized nir-types for download-path 
The Midgard compiler only deals with sized NIR types for image loads and
stores. Since we already have nir_get_nir_type_for_glsl_base_type()
which can provide us with the corresponding sized type, let's just use
that, and drop the extra table.

This fixes the following piglits on Mali-T760:
- spec/ext_texture_compression_s3tc/getteximage-targets 2d s3tc
- spec/ext_texture_compression_s3tc/getteximage-targets cube s3tc

Fixes: 9123ee0f18 ("st/mesa/pbo: Set src type on image_store")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35882>
(cherry picked from commit 96d124092f)
 2025-07-15 16:19:55 +02:00
Samuel Pitoiset
e04ac3f94a ac/surface: select a different swizzle mode for ASTC formats on GFX12 
It seems only 4KiB swizzle works fine with ASTC.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34877>
(cherry picked from commit 2af3ef9305)
 2025-07-15 16:19:55 +02:00
José Roberto de Souza
635ba76fbf anv: Do not emit batch_emit_fast_color_dummy_blit() for video engine 
Wa_16018063123 don't apply to video engine also video engine don't
support XY_FAST_COLOR_BLT.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Fixes: ec43c20182 ("anv: implement dummy blit for Wa_16018063123")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit 926e6a94ad)
 2025-07-15 16:19:55 +02:00
José Roberto de Souza
74c88f22ae anv: Flush before invalidate aux map in copy and video engines 
BSpec: 43904
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit 4618a99a4c)
 2025-07-15 16:19:55 +02:00
José Roberto de Souza
c2461e75b5 anv: Read the correct register for aux table invalidation when in GPGPU mode in render engine 
For 3D or GPGPU modes the same render engine should be used, CCS
register should only be used when using compute engine.

Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
(cherry picked from commit e68f81eaf6)
 2025-07-15 16:19:55 +02:00
Faith Ekstrand
4c3edecfab nak: Surface handles are not allowed to be rZ 
The chances of this happening are near zero with the way we do surface
ops today but I have seen it in the wild and this is apparently a rule.
The hardware throws an illegal instruction encoding if it sees 255.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35895>
(cherry picked from commit 19bee26056)
 2025-07-15 16:19:55 +02:00
Samuel Pitoiset
f8cc14aabd ac/surface: use align with NPOT for estimating surface size 
ac_estimate_size() triggers an assertion because the block size isn't
aligned to a power of two for ASTC formats.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35879>
(cherry picked from commit cb6f2d9409)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
aa5c66fdd0 freedreno/ci: fix a750-piglit-cl rules 
Fixes: 5b3f7de99f ("ci/freedreno: Introduce OpenCL testing for Adreno 618, 660, and 750")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35888>
(cherry picked from commit 32fe81a02b)
 2025-07-15 16:19:54 +02:00
Mike Blumenkrantz
416ad99090 aux/trace: always finish dumping draw/dispatch calls before triggering them 
this avoids deadlocks

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35769>
(cherry picked from commit f946167e30)
 2025-07-15 16:19:54 +02:00
Samuel Pitoiset
579385e32b radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5 
This looks like a hw bug on GFX10.3-GFX11.5 because RB+ seems to only
work as expected when all channels (RGBA) are written. With that format,
RGB channels must be all set or unset but setting the A channel is
legal so far.

This will reduce rendering performance with that format but it's the
less intrusive solution for now. This might be revisited in the near
future, also with more VKCTS coverage.

This has been tested and verified on GFX10.3 (NAVI21) and GFX11
(NAVI31) and GFX12 (NAVI48), unfortunately I don't have GFX11.5 but
let's assume it's broken there too.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13371
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 10ef9c6a80)
 2025-07-15 16:19:54 +02:00
Samuel Pitoiset
3eaf0a6489 radv: stop disabling the alpha optimization with E5B9G9R9 and RB+ 
This old workaround was added due to test failures with VKCTS but it
turns out the tests were broken. Color writemask for E5B9G9R9 must be
all RGB or none and some tests are testing various RGB channels which
is illegal.

See https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/5821.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 7017b25d6a)
 2025-07-15 16:19:54 +02:00
Caio Oliveira
bfb578f2ca brw: Use the right width in brw_nir_apply_key for BS shaders 
Fixes: 23c7142cd6 ("anv: disable SIMD16 for RT shaders")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35798>
(cherry picked from commit c733f07378)
 2025-07-15 16:19:54 +02:00
Rhys Perry
fe59e9ffdf aco/ra: fix repeated compact_linear_vgprs() in get_reg() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b7738de4f9 ("aco/ra: rework linear VGPR allocation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13431
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35838>
(cherry picked from commit dce1d4ad4c)
 2025-07-15 16:19:54 +02:00
Boris Brezillon
4c94de4044 panvk: Lower maxImageDimension{2D,3D,Cube} to match the HW caps 
Maximum texture dimension is 2^16, but we're limited by the 32-bit
fields that are used to pass strides/sizes in various descriptors.
Assuming RGBA32_FLOAT is the biggest format we support, that gives us a
16k-1 image size for 2D and cube map, and 512 for 3D.

Change our GetPhysicalDeviceImageFormatProperties2() implementation so
that smaller formats can still advertise bigger image sizes.

Fixes: d5ed77800e ("panvk: Fix GetPhysicalDeviceProperties2() to report accurate info")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35555>
(cherry picked from commit e25a91d919)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
e6b9543668 meson: only run symbols-check if nm is available 
And drop the redundant check from symbols-check.py, which was actually
masking all kinds of issues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 4be493862d)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
313130c431 bin/symbols-check: document new platform symbols exported since symbols-check was broken 
The `pthread_mutexattr_*` symbols probably shouldn't be exported, but
let's fix that later so that we can at least get symbols-check to run
again ASAP.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit f350803fb3)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
a2bc0d2079 bin/symbols-check: sort platform symbols 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit f06fff8148)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
21c1e4f371 bin/symbols-check: ignore version of platform symbols 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 3d9b76db8e)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
fc37fbb555 bin/symbols-check: ignore nm lines that don't have a symbol name 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit 5672230c19)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
643d542143 bin/symbols-check: fix fields length condition before accessing fields 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35891>
(cherry picked from commit e626636e90)
 2025-07-15 16:19:54 +02:00
Yiwei Zhang
b67b5cbec2 meson: drop vdrm from virgl and venus 
Currently neither virgl nor venus uses vdrm. One big blocker is neither
of them has adopted drm_syncobj yet.

Fixes: 1a6fc7006a ("meson: split subdir for virtio/vdrm and virtio/vulkan")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35933>
(cherry picked from commit 60eebe964d)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
da0f67c5d0 meson: split subdir for virtio/vdrm and virtio/vulkan 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35723>
(cherry picked from commit 1a6fc7006a)
 2025-07-15 16:19:54 +02:00
Eric Engestrom
0968cd5859 virtio: move inc_virtio up one folder 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35723>
(cherry picked from commit 6f8c4a7ce1)
 2025-07-15 16:19:53 +02:00
Eric Engestrom
faaa6f1480 .pick_status.json: Mark 485b520cf2 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
a6671662ef .pick_status.json: Mark 0a581e7408 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
12cc9a4d7b .pick_status.json: Mark 94f42bb201 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
cd1d798ab0 .pick_status.json: Mark 2f5ff9788a as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
18f347d364 .pick_status.json: Mark 6ad0b59cc8 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
24db8ef2a8 .pick_status.json: Mark 85e4a19ed1 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
030d2daa14 .pick_status.json: Mark abe23e1cd0 as denominated 2025-07-15 16:19:53 +02:00
Eric Engestrom
c62c2a5510 .pick_status.json: Update to 37ae4df3e4 2025-07-15 16:19:49 +02:00
Eric Engestrom
8a3d5aed64 docs: add sha sum for 25.1.5 2025-07-02 17:57:21 +02:00
Eric Engestrom
fe77ae26db VERSION: bump for 25.1.5 mesa-25.1.5 2025-07-02 17:46:17 +02:00
Eric Engestrom
1bf5e50bb2 docs: add release notes for 25.1.5 2025-07-02 17:46:17 +02:00
Rob Clark
1a85ddb514 rusticl: Fix work group size validation 
For each dimension, we `threads *= lws`.. which is still zero if threads
is initialized to zero.

Fixes: eca4f0f632 ("rusticl/kernel: check that local size on dispatch doesn't exceed limits")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35864>
(cherry picked from commit 6bc47e65d7)
 2025-07-02 16:55:02 +02:00
Rob Clark
9b3b65d7c3 freedreno/a6xx: Fix thread calc for dummy kernels 
If a kernel uses no regs, max_reg will be -1.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35864>
(cherry picked from commit c417b83f19)
 2025-07-02 16:55:02 +02:00
Boris Brezillon
d861a7b498 pan/layout: Fix size_B calculation for AFBC(3D) 
Right now the headers are not counted when we calculate the total slice
size of an AFBC(3D) image. Fix that by special-casing size_B
initialization for AFBC.

I couldn't get back to the original commit introducing this mistakes,
so I'm flagging for backport instead of adding a proper Fixes tag.

Backport-to: 25.1
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35555>
(cherry picked from commit 1389a23708)
 2025-07-02 16:19:33 +02:00
Iván Briano
61761d49d5 anv: move view_usage check to before setting the protected bit on it 
Otherwise the comparison will always be false for protected content.

Also remove extra setting of the protected bit that was happening later.

Fixes: 8d9cc6aa23 ("anv: properly flag image/imageviews for ISL protection")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35870>
(cherry picked from commit 5b58b838fe)
 2025-07-02 16:19:33 +02:00
Rhys Perry
27d61a6fd2 aco: update ctx.block when inserting discard block 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13432
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35833>
(cherry picked from commit 21c4400278)
 2025-07-02 16:19:32 +02:00
Jose Maria Casanova Crespo
09915f11a4 v3d: fix support for no buffer object bound 
Piglit arb_texture_buffer_object-render-no-bo was generating
gpu resets because the uniform stream was missing the last
Fragment Shader uniform. So it was reading instead of the last
fragment shader uniform the first uniform of the vertex shader.

And using that unrelated VS uniform as the sampler address where
the texture should be read.

So now if a buffer object is not bound for a texture buffer object
we write the texture state base address to 0 (NULL) so the default
texture state is used.

So only is needed to set the 4 lower bits of the tmu_p0 with
the bit-mask of word enables.

Fixes: bb8285c258 ("v3d: add support for no buffer object bound")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35847>
(cherry picked from commit 0f8c681c5c)
 2025-07-02 16:19:32 +02:00
Timothy Arceri
2ae8d0362b dri: fix __DRI_IMAGE_FORMAT* to PIPE_FORMAT* mappings 
As per the old comment:

"These formats correspond to the similarly named MESA_FORMAT_*
 tokens, except in the native endian of the CPU.  For example, on
 little endian __DRI_IMAGE_FORMAT_XRGB8888 corresponds to
 MESA_FORMAT_XRGB8888, but MESA_FORMAT_XRGB8888_REV on big endian."

Fixes: 7e10601786 ("dri: Redeclare __DRI_IMAGE_FORMAT_* as PIPE_FORMAT_*")
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35814>
(cherry picked from commit 2ca46c7a7a)
 2025-07-02 16:19:32 +02:00
Faith Ekstrand
b2186f35a1 nak: I/O offsets are unsigned when combined with RZ 
Fixes dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.samplers_16384

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35843>
(cherry picked from commit 3853f72f52)
 2025-07-02 16:19:32 +02:00
Alyssa Rosenzweig
8bcc9c9a04 asahi: flush around XFB 
this is required by the spec. fixes
gles-3.0-transform-feedback-uniform-buffer-object.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Backport-to: 25.1
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35802>
(cherry picked from commit 03a5b7f25c)
 2025-07-02 16:19:32 +02:00
Jesse Natalie
fe9d475e34 dzn: Roll up initialization failure in dzn_meta_init 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13416
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35748>
(cherry picked from commit 7f4ae75903)
 2025-07-02 16:19:32 +02:00
Rhys Perry
a20567eead nir/lower_bit_size: fix bitz/bitnz 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 6585209cdd ("nir/lower_bit_size: mask bitz/bitnz src1 like shifts")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35770>
(cherry picked from commit 08859cbe50)
 2025-07-02 16:19:32 +02:00
Faith Ekstrand
dd65919d84 nak: Tell NIR to lower invalid implicit LODs 
I think NVIDIA hardware more or less does this for us for free but it's
nice to have NIR make sure.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35795>
(cherry picked from commit c6ad70551b)
 2025-07-02 16:19:32 +02:00