fran/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
174,371 Commits 63 Branches 889 Tags
zink-stablefix
Commit Graph

174371 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Yonggang Luo
1ed7a1282c mapi: Merge get_static_proc_address into _glapi_get_proc_address 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23879>
 2023-06-29 01:36:09 +00:00
Yonggang Luo
e3b93887eb mapi: Style fixes in glapi/glapi_getproc.c 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23879>
 2023-06-29 01:36:09 +00:00
Yonggang Luo
a63b7a03a1 util: sizeof bucket are always 32bit width, use align instead align64 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:31 +00:00
Yonggang Luo
b7a0d34f89 util: Do not use align64 over unsigned int in register_allocate.c 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:31 +00:00
Yonggang Luo
4d7c969dd8 util: Replace the usage of redundant u_align_u32 with align and remove u_align_u32 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:30 +00:00
Yonggang Luo
7ac83b0961 util: Getting align and align64 consistence with ALIGN 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:30 +00:00
Yonggang Luo
b45fb614a4 util: use uint32_t instead of unsigned in bitscan.h 
uint32_t is more exact than unsigned for these functions

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:30 +00:00
Yonggang Luo
3aa929ca46 util: Add function util_is_power_of_two_nonzero64 in bitscan.h 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
 2023-06-29 00:45:30 +00:00
Donald Robson
3fc727b346 pvr: Rename rogue_fw.xml -> rogue_kmd_stream.xml. 
The UMD does not care if firmware is used, and the current name isn't
very informative either.

Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Matt Coster
70f86b25a1 pvr: Rename transfer 3D heap to transfer frag heap 
This better matches the naming throughout the rest of the driver.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Sarah Walker
a76818e525 pvr: Merge main and extension command streams 
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Sarah Walker
8d3e8c3ad9 pvr: Rename heap reserved area to static data carveout 
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Sarah Walker
b0a45fc618 pvr: use pvr_csb_pack() to setup CR_FB_CDC_ZLS 
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Sarah Walker
e714b35301 pvr: Fragment register fb_cdc_zls is feature dependent 
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
 2023-06-28 22:26:07 +00:00
Prodea Alexandru-Liviu
5acbadddb4 microsoft/clc: Don't build compiler test if build-tests is false 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8161

Cc: mesa-stable

Reviewed-by: Eric Engestrom <eric@igalia.com>

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23890>
 2023-06-28 22:09:13 +00:00
Sil Vilerino
1b7bf9a4f4 d3d12: Fix usage of D3D12_VIDEO_ENCODER_RATE_CONTROL_FLAG, was using D3D12_VIDEO_ENCODER_SUPPORT_FLAG wrongly instead 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
 2023-06-28 21:48:38 +00:00
Sil Vilerino
ed0087d75e d3d12: Only set reduced_tx_set when supported by D3D12 caps (no libva caps for reduced_tx_set to map to) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
 2023-06-28 21:48:38 +00:00
Sil Vilerino
6de9402fa8 d3d12: Correct tx_mode_support reporting as specified in libva spec 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
 2023-06-28 21:48:38 +00:00
Yonggang Luo
75ac852253 compiler: set alignment=1 by default for handling empty struct/interface in glsl_types.cpp 
When there is no elements in struct/interface, the alignment of it should be 1 instead of 0.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23841>
 2023-06-28 21:16:05 +00:00
Joshua Ashton
68b9ad0ba7 radv: Do not enable robustness for push constants with robustBufferAccess2 
There is no spec text requiring this behaviour, it is only for buffers.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23885>
 2023-06-28 20:49:30 +00:00
Caio Oliveira
f4c2025e2c nir/print: Print more representations in load_const 
In addition to the hexadecimal and float (when applicable), print the
signed and unsigned representations.  Representations may be omitted based
on information about the value:

- If gather types has unambiguous information, we use it;
- Float is omitted for 8 bit values;
- Signed decimal is omitted for positive values;
- Unsigned decimal is omitted for small values (representation is same as hex);

Note for now the "terse form" that appear in SSA uses is unchaged.

Based on a patch by Mike Blumenkrantz.

Examples:

```
// Just used as float. Omitted decimals.
vec4 32 ssa_81 = load_const (0x3f800000, 0x3f800000, 0x3e4ccccd, 0x3f800000) = (1.000000, 1.000000, 0.200000, 1.000000)
vec1 32 ssa_28 = load_const (0x3e4ccccd = 0.200000)

// Just a small integer. Omitted float and decimal.
vec1 32 ssa_45 = load_const (0x00000001)

// Larger positive integers. Omitted float.
vec1 32 ssa_39 = load_const (0x00002000 = 8192)
vec1 32 ssa_30 = load_const (0x000000ff = 255)
vec1 32 ssa_28 = load_const (0x00000010 = 16)

// Integers with negative values.
load_const (0xff = -1 = 255)
load_const (0xff80 = -128 = 65408)
load_const (0xffff = -1 = 65535)

// Same value, in the first case we know is used as an integer.
load_const (0xffffffe0 = -32 = 4294967264)
load_const (0xffffffe0 = -nan = -32 = 4294967264)
```

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
a185736a42 nir/print: Use src_type when printing consts in SSA uses 
If the src_type is not available, untie by looking at the results from
nir_gather_ssa_types(). If that is ambiguous, just pick uint.

Now in print_const_from_load() when the type is invalid, print the full
constant form (with both padded hex and float); when the passed type
is valid, print the terse form based on it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
5d15f4ef28 nir: Extract logic to get dest and srcs types from intrinsic 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
7de530d3df nir: Make a const-friendly way to get the offset_src and arrayed_io_src from intrinsic 
The existing helper returns a `nir_src *` so expects a non-const instr.

We plan to use this function in queries that don't modify the shader, so
create (and use internally) a variant that returns the index instead.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
8f64415af7 nir/print: Make NIR_DEBUG=print_consts behavior the default 
Now there's a NIR_DEBUG=print_no_inline_consts to omit them.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
260a9167db nir/print: Improve NIR_PRINT=print_consts by using nir_gather_ssa_types() 
The two representations are *always* used for `load_const`, but when
inlining the value as SSA source, use just a single terse
representation.

The choice between integer or float is based on the result of
nir_gather_ssa_types(), with a bias for integer when in doubt.

Also remove extra comment `/* */` syntax since the value is already
enclosed by parenthesis.

---

For illustration, here's some instructions from crucible test
func.shader.averageRounded.uint64_t with NIR_DEBUG=print_consts:

BEFORE:

```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 /*(0xfffffffc = -nan)*/
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 /*(0x00000002 = 0.000000)*/, ssa_25 /*(0x00000024 = 0.000000)*/) (access=0, align_mul=1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 /*(0x00000002 = 0.000000)*/
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 /*(0x00000007 = 0.000000)*/
vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 /*(0x7b000808 = 664776890994587263929995856502063104.000000)*/, ssa_30
```

AFTER:

```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 (0xfffffffc)
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 (0x2), ssa_25 (0x24)) (access=0, align_mul=1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 (0x2)
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 (0x7)
vec1 32 con ssa_31 = load_const (0x7b000808 = 664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 (0x7b000808), ssa_30
```

and some instructions from crucible test func.gs.basic with NIR_DEBUG=print_consts,
now showing float representation being selected:

BEFORE:

```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 /*(0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)*/
```

AFTER:

```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 (0.200000, 0.200000, 0.000000, 0.000000)
```

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Caio Oliveira
3cfdab8f92 nir: Allow nir_gather_ssa_types() to ignore regs instead of assert 
If we infer a type for a reg, just ignore and keep going.  This will allow
to use this pass even when registers are present.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
 2023-06-28 20:17:18 +00:00
Konstantin Seurer
1e2f647fbb radv/rt: Hash stages using radv_hash_shaders 
The hash also depends on the radv_pipeline_key as well as the flags. The
pipeline layout will also play a role when we implement inline
descriptor sets and push constants.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Konstantin Seurer
de1092e256 radv/rt: Fix caching non-recursive stages 
The hash used for insertion is calculated in a different way than the
hash used for lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Konstantin Seurer
c9a5cac4ff util: Do not include immintrin.h in half_float.h 
The files included are extremely large and hurt compile time of
everything that inludes half_float.h directly or indirectly.

Compile time of a fresh RADV build:
before 32.477s 32.661s 32.625s
after  25.116s 24.928s 25.114s

v2: Include xmmintrin instead (Marek Olšák)
after  25.552s 25.811s 25.678s

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23871>
 2023-06-28 18:56:20 +00:00
Eric Engestrom
189c7d6ff1 amd/ci: add another dEQP-VK.multiview.renderpass2.multisample.* flake 
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/44557372

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23910>
 2023-06-28 18:32:10 +00:00
Kiskae
e67337bebf vulkan/wsi: check for dri3 buffer initialization failure 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8427
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lina Versace <linyaa@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23081>
 2023-06-28 14:45:01 +00:00
Dmitry Baryshkov
0e51f2de88 freedreno/registers: add bitfield for DSI wide bus enablement 
Add a bitfield controlling wide bus enablement for DPU<->DSI interface.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23829>
 2023-06-28 14:17:06 +00:00
Erik Faye-Lund
bbcda63564 draw/i915: move hwfmt array to i915 specific struct 
There's no point in bloating the vertex_info struct everywhere with
information that's only used by i915 in a single place. Let's explicitly
store the hwinfo when needed, instead of piggy-backing on vertex_info.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23851>
 2023-06-28 13:42:44 +00:00
Samuel Pitoiset
3f7ea95bc9 radv: inline more values in radv_emit_fb_ds_state() 
These are no longer adjusted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Samuel Pitoiset
5010ab8fff radv: stop emitting TILE_SURFACE_ENABLE for the ZRANGE_PRECISION workaround 
The only case that matters is when the fb is emitted, but HTILE is
already disabled there using DB_RENDER_CONTROL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Yonggang Luo
f8a2047387 d3d12: Fixes unused-variable compile error 
The compile error message is:
../../src/gallium/drivers/d3d12/d3d12_video_screen.cpp:481:70: error: unused variable ‘sliceData’ [-Werror=unused-variable]
  481 |    D3D12_VIDEO_ENCODER_PICTURE_CONTROL_SUBREGIONS_LAYOUT_DATA_SLICES sliceData = { };
      |                                                                      ^~~~~~~~~
cc1plus: all warnings being treated as errors

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23900>
 2023-06-28 12:04:56 +00:00
Karmjit Mahil
4096bd8d85 pvr: Setup ZLS depth and stencil load/store separately 
Previously the code assumed that you could only have depth-stencil
attachments so no stencil only or depth only, for ZLS load/stores.
This isn't true as we can have stencil only attachments so the
ZLS depth and stencil store/load enable have to be set separately.

Other ZLSCTL setup has also been adjusted for separate depth-stencil.
E.g. the z{load,store}format, and {load,store}twiddled.

Co-Authored-By: Soroush Kashani <soroush.kashani@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23830>
 2023-06-28 11:14:10 +00:00
Alejandro Piñeiro
59518b6dc6 v3dv: add a linear images to buffer copy codepath 
Called copy_image_to_buffer_texel_buffer, that reuses
copy_image_linear_texel_buffer, by setting up a image destination from
the buffer destination.

This fixes new ycbcr tests added recently (1.3.6.0) like:
dEQP-VK.ycbcr.copy.*.*.*buffer*

that were failing due lack of a codepath handling them.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23864>
 2023-06-28 12:55:16 +02:00
Alejandro Piñeiro
74fd2b9dd7 v3dv: refactor copy_image_to_buffer_blit 
In order to have common code to create a image from a buffer, that we
plan to use later on a new codepath.

This refactor adds three new methods:
 * One that gathers all the info required to create the structures and
   implement the operation
 * One that creates the image from the buffer, based on that info
 * One that creates a BlitRegion from that info

This seems like too much splitting, but we needed to do it in this
way, because we can't ensure that future uses of this common code
would use a BlitRegion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23864>
 2023-06-28 12:54:57 +02:00
Samuel Pitoiset
7b8c6cedcf radv: allow NV_device_generated_commands with RADV_DEBUG=noibs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
277b2afd70 radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs 
This contains some preliminary work to be able to execute DGC cmdbuf
on the compute queue because IB2 doesn't exist.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
82c60b41e9 radv/amdgpu: add more small helpers for managing CS 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Sil Vilerino
86785130d1 CI/windows: Update headers and Agility redist to 1.711.3-preview 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23811>
 2023-06-27 23:16:37 +00:00
Sil Vilerino
64da736286 d3d12: AV1 Encode 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23811>
 2023-06-27 23:16:37 +00:00
Sil Vilerino
314871d57b frontends/va: Extend AV1 Encode params 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23811>
 2023-06-27 23:16:37 +00:00
Alyssa Rosenzweig
190b1fdc64 nir: Convert to nir_foreach_function_impl 
Done by hand at each call site but going very quickly with funny Vim motions and
common regexes. This is a very common idiom in NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23807>
 2023-06-27 22:44:04 +00:00
Alyssa Rosenzweig
19daa9283c nir: Add nir_foreach_function_impl helper 
Most users of nir_foreach_function actually want the nir_function_impl, not the
nir_function, and want to skip empty functions (though some graphics-specific
passes sometimes fail to do that part). Add a nir_foreach_function_impl macro
to make that case more ergonomic.

   nir_foreach_function_impl(impl, shader) {
      ...
      foo(impl)
   }

is equivalent to:

   nir_foreach_function(func, shader) {
      if (func->impl) {
         ...
         foo(func->impl);
      }
   }

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23807>
 2023-06-27 22:44:04 +00:00
Karol Herbst
a8044110bf docs/rusticl: add Enabling section 
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23859>
 2023-06-27 22:35:13 +00:00
Karol Herbst
e2263a645c docs/rusticl: mark building section as such 
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23859>
 2023-06-27 22:35:13 +00:00