Commit Graph

101804 Commits

Author SHA1 Message Date
Marek Olšák
9a1363427e radeonsi: always prefetch later shaders after the draw packet
so that the draw is started as soon as possible.

v2: only prefetch the API VS and VBO descriptors

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
e4b7974ec7 radeonsi: emit shader pointers before cache flushes & waits
This code was written with the constant engine in mind.
We can simplify it now.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
82799c5035 radeonsi/gfx9: don't use the workaround for gather4 + stencil
it doesn't seem to be needed.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
1372ccfe6f radeonsi: disable TC-compat HTILE on Tonga and Iceland
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
afe0bd2c55 radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabled
just pass the flag that indicates it.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
29a09e1d38 radeonsi: don't flush HTILE if there is no HTILE clear
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
5fb31a1734 radeonsi: merge 2 identical if statements in si_clear
and other cleanups

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
8a28679987 radeonsi: don't do GFX-specific texture decompression for compute
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
307bccc6df radeonsi: simplify generating the renderer string
HAVE_LLVM > 0 is a tautology.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Marek Olšák
a3b785be4d winsys/amdgpu: allow local BOs on APUs
Local BOs ignore BO priorities, and we don't need those on APUs.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-04-13 12:31:04 -04:00
Juan A. Suarez Romero
b37b35a5d2 getteximage: assume texture image is empty for non defined levels
Current code is returning an INVALID_OPERATION when trying to use
getTextureImage() on a level that has not been explicitly defined.

That is, we define a mipmapped Texture2D with 3 levels, and try to use
GetTextureImage() for the 4th levels, and INVALID_OPERATION is returned.

Nevertheless, such case is not listed as an error in OpenGL 4.6 spec,
section 8.11.4 ("Texture Image Queries"), where all the case errors for
this function are defined. So it seems this is a valid operation.

On the other hand, in section 8.22 ("Texture State and Proxy State") it
states:

  "Each initial texture image is null. It has zero width, height, and
   depth, internal format RGBA, or R8 for buffer textures, component
   sizes set to zero and component types set to NONE, the compressed
   flag set to FALSE, a zero compressed size, and the bound buffer
   object name is zero."

We can assume that we are reading this initialized empty image when
calling GetTextureImage() with a non defined level.

With this assumption, we will reach one of the other error cases defined
for the functions. In the end this means that we would end up returning
INVALID_VALUE to the caller.

This fixes arb_get_texture_sub_image piglit tests.

v2: just return INVALID_VALUE if there is no defined level (Iago)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-04-13 17:47:37 +02:00
Juan A. Suarez Romero
8d411eb6b3 gettextureimage: verify cube map is complete
According to OpenGL 4.6 spec, section 8.11.4 ("Texture Image Queries"),
relative to errors for GetTexImage, GetTextureImage, and GetnTexImage:

  "An INVALID_OPERATION error is generated by GetTextureImage if the
   effective target is TEXTURE_CUBE_MAP or TEXTURE_CUBE_MAP_ARRAY, and
   the texture object is not cube complete or cube array complete,
   respectively."

This fixes arb_get_texture_sub_image piglit tests.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-04-13 17:47:27 +02:00
Juan A. Suarez Romero
42891dbaa1 gettextsubimage: verify zoffset and depth are correct
According to OpenGL 4.6 spec, section 8.11.4 ("Texture Image Queries"),
relative to errors for GetTextureSubImage() function:

  "An INVALID_VALUE error is generated if the effective target is
   TEXTURE_1D and either yoffset is not zero, or height is not one.

   An INVALID_VALUE error is generated if the effective target is
   TEXTURE_1D, TEXTURE_1D_ARRAY, TEXTURE_2D or TEXTURE_RECTANGLE, and
   either zoffset is not zero, or depth is not one."

The commit fixes the check for height and depth.

This fixes arb_get_texture_sub_image piglit tests.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-04-13 17:47:27 +02:00
Timothy Arceri
a63e69f5f0 mesa: free debug messages when destroying the debug state
Fixes: 04a8baad37 "mesa: refactor _mesa_PopDebugGroup and _mesa_free_errors_data"

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98281
2018-04-13 22:20:48 +10:00
Timothy Arceri
c500ab2735 mesa: fix x86 builds
Fixes: 43d66c8c2d "mesa: include mtypes.h less"
2018-04-13 22:13:46 +10:00
Marek Olšák
e961824ba8 Fix make check 2018-04-12 20:03:13 -04:00
Marek Olšák
6d6b1b3890 Fix scons build 2018-04-12 19:55:01 -04:00
Marek Olšák
43d66c8c2d mesa: include mtypes.h less
- remove mtypes.h from most header files
- add main/menums.h for often used definitions
- remove main/core.h

v2: fix radv build

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-12 19:31:30 -04:00
Marek Olšák
57f4268da4 mesa: include dispatch.h less
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-12 19:31:28 -04:00
Bas Nieuwenhuizen
6ff98dbf7c radv: Implement VK_EXT_vertex_attribute_divisor.
Pretty straight forward, just pass the divisors through the shader
key and then do a LLVM divide.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-12 22:57:23 +02:00
Bas Nieuwenhuizen
7eff8d7d35 ac/surface: Allow S swizzle for displayable surfaces.
For dcn1 && < 64 bpp displayable surfaces, addrlib only accepts
S swizzles.

At the same time addrlib prefers D swizzles is allowed, so we can
just allow S swizzles as fallback.

Fixes: b64b712558 "ac/surface/gfx9: request desired micro tile mode explicitly"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-12 21:24:55 +02:00
Eric Anholt
7bc77dbb00 broadcom/vc5: Fix a stray '`' in a comment. 2018-04-12 11:20:50 -07:00
Eric Anholt
b225cdcecc broadcom/vc5: Update the UABI for in/out syncobjs
This is the ABI I'm hoping to stabilize for merging the driver.  seqnos
are eliminated, which allows for the GPU scheduler to task-switch between
DRM fds even after submission to the kernel.  In/out sync objects are
introduced, to allow the Android fencing extension (not yet implemented,
but should be trivial), and to also allow the driver to tell the kernel to
not start a bin until a previous render is complete.
2018-04-12 11:20:50 -07:00
Eric Anholt
d9c525ed22 broadcom/vc5: Drop the finished_seqno optimization.
With the DRM scheduler changes, I'm about to remove all seqnos from the
UABI.
2018-04-12 11:20:50 -07:00
Eric Anholt
aedfd8ede4 broadcom/vc5: Drop the throttling code.
Since I'll be using the DRM scheduler, we won't run into the problem of a
runaway client starving other clients of GPU time.
2018-04-12 11:20:50 -07:00
Eric Anholt
dd9c476165 broadcom/vc5: Move flush_last_load into load_general, like for stores.
This should avoid mistakes with not flushing as we change the series of
loads.  Already, it fixes a hopefully unreachable case where we were
emitting just the TILE_COORDINATES and not the dummy store that needs to
go with it.
2018-04-12 11:20:50 -07:00
Eric Anholt
6a21a582fb broadcom/vc5: Rename read_but_not_cleared to loads_pending.
This is a more obvious name for what the variable means, and matches what
it's called for stores.
2018-04-12 11:20:50 -07:00
Eric Anholt
b946218c48 broadcom/vc5: Refactor the implicit coords/stores_pending logic.
Since I just fixed a bug due to forgetting to do these right, do it once
in the helper func.
2018-04-12 11:20:50 -07:00
Eric Anholt
ec60559f97 broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.
Fixes a simulator assertion failure in
KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
2018-04-12 11:20:50 -07:00
Eric Anholt
8f2999120d broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.
This was dying in the simulator on
GTF-GLES3.gtf.GL3Tests.packed_depth_stencil.packed_depth_stencil_blit.
We'll need to do basically the same thing as Z32F/S8 does in the MSAA
Z24S8 case.
2018-04-12 11:20:50 -07:00
Eric Anholt
7553cbfc9d broadcom/vc5: Fix MSAA depth/stencil size setup.
The v3dX(get_internal_type_bpp_for_output_format)() call only handles
color output formats (which overlap in enum numbers with depth output
formats), so for depth we just need to take the normal cpp times the
number of samples.
2018-04-12 11:20:50 -07:00
Leo Liu
fa328456e8 st/va: add VP9 config to enable profile2
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
dac0024b58 radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
f1277dabbc radeon/vcn: add VP9 profile2 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
e8724bd1e3 vl: add VP9 profile2 support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
d9a31341ec st/va: add VP9 config to enable profile0
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
ef52ba8aa0 st/va: parse VP9 uncompressed frame header
To get some of UVD required parameters.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
bf0f5fe929 st/va: add slice parameter handling for VP9
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
05176fe65e st/va: add picture parameter handling for VP9
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
9ff83d13e5 st/va: add handles for VP9 buffers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
30438fbf46 st/va: add VP9 picture to context
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
0f373a65e5 radeonsi: cap VP9 support to progressive buffer
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
6adaf6de6d radeonsi: cap VP9 support to Raven
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
905368669d radeon/vcn: add VP9 context buffer
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
e2ce7c0a62 radeon/vcn: get VP9 msg buffer
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
6000bdb75b radeon/vcn: fill probability table to prob buffers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
93c0f3cc13 radeon/vcn: add VP9 message buffer interface
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:13 -04:00
Leo Liu
caaecf3d3b radeon/vcn: add VP9 prob table buffer
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:12 -04:00
Leo Liu
b628ea039f vl: add VP9 probability tables
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:12 -04:00
Leo Liu
eb22785bd8 radeon/vcn: add VP9 dpb buffer size
The current FW has restricted the size to the worse case,
and the new dynamic dpb buffer support is on the way from
firmware side, we will change accordingly.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12 11:15:12 -04:00