Samuel Pitoiset
ae4628d3d6
radv: do not program COMPUTE_MAX_WAVE_ID (GDS register) on GFX6
...
Ported from RadeonSI c2359797samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26867 >
2024-01-09 16:31:30 +00:00
Mike Blumenkrantz
ec656e1984
lavapipe: maint6
...
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26881 >
2024-01-09 15:24:12 +00:00
Mike Blumenkrantz
89a7ee7393
lavapipe: maint6 descriptor stuff
...
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26881 >
2024-01-09 15:24:12 +00:00
Mike Blumenkrantz
6c83b9f219
vk/cmd_queue: fix up indentation a little
...
still kinda fucked
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26881 >
2024-01-09 15:24:12 +00:00
Mike Blumenkrantz
e977a2368b
vk/cmd_queue: generate maint6 functions
...
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26881 >
2024-01-09 15:24:12 +00:00
Mike Blumenkrantz
2439982eac
vk/cmd_queue: stop using explicit casts
...
this just ends up being broken for complex types anyway
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26881 >
2024-01-09 15:24:12 +00:00
José Roberto de Souza
ad158b0bee
anv: Call anv_measure_submit() before anv_cmd_buffer_chain_command_buffers()
...
Otherwise the measurement instructions will be placed after the
MI_BATCH_BUFFER_START calling the next cmd_buffer.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
José Roberto de Souza
d37414d8a4
anv: Fix anv_measure_start/stop_snapshot() over copy or video engine
...
Those engines don't have PIPE_CONTROL so we can't do
ANV_TIMESTAMP_CAPTURE_AT_CS_STALL but we can support measurement
by changing the capture type to ANV_TIMESTAMP_CAPTURE_TOP/END_OF_PIPE
Right now this issue is only reproduced in Xe KMD without setting
any special parameters(other than INTEL_MEASURE) because Xe KMD allows
the usage of copy engine while i915 can't due TRTT restrictions.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
José Roberto de Souza
b8d48ebc93
anv: Add missing anv_measure_submit() calls in Xe KMD backend
...
Without this intel_measure don't work with Xe KMD.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
José Roberto de Souza
a0f7820fe8
anv: Simply companion_rcs handling
...
Here dropping is_companion_rcs_cmd_buffer parameter of a few functions
that don't need this information, it just need the right
anv_cmd_buffer for each case.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
José Roberto de Souza
428a179865
anv: Drop useless STATIC_ASSERT in anv_physical_device_init_queue_families()
...
assert(family_count <= ANV_MAX_QUEUE_FAMILIES) already takes care
of STATIC_ASSERT without need of updates.
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
José Roberto de Souza
0997766069
anv: Increase ANV_MAX_QUEUE_FAMILIES
...
If ANV_VIDEO_DECODE, ANV_VIDEO_DECODE and INTEL_COPY_CLASS are enabled
it is possible to have 5 different queues, so here increasing
ANV_MAX_QUEUE_FAMILIES.
Fixes: 17b8b2cffdjose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
José Roberto de Souza
0c42c79edf
utils/u_debug: Fix parse of "all,<something else>
...
If debug string is something like "all,file=..." the all case would
never be executed, this can be fixed by comparing up to strlen("all").
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
Erik Faye-Lund
a63f3fbdae
mesa: check for float-format support
...
Surprisingly enough, EXT_color_buffer_float doesn't make RGB32F
color-renderable, but EXT_color_buffer_half_float *does* make
RGB16F color-renderable...
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26870 >
2024-01-09 13:45:38 +00:00
Erik Faye-Lund
c75b882de4
mesa/main: require EXT_color_buffer_float for ES 3.2
...
OpenGL ES 3.2 makes FP16 and FP32 textures color-renderable, so this is
effectively a requirement.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26870 >
2024-01-09 13:45:38 +00:00
Erik Faye-Lund
782fb8966b
mesa: actually check for EXT_color_buffer_float support
...
EXT_color_buffer_float makes both 16 and 32 bit floating-point texture
formats color-renderable. We can't just unconditionally report that, we
need to check for support.
The RGB formats are a bit special under this extension, because it's not
specified as color-renderable. However, because the RGBA formats *are*
specified as color-renderable, and the state-tracker can emulate the RGB
formats with the RGBA ones, we don't need to test for that here.
While we're at it, move EXT_color_buffer_half_float to its correct
sorted position.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26870 >
2024-01-09 13:45:38 +00:00
Erik Faye-Lund
5f995f5e34
mesa/st: do not check for emulated format
...
The state-tracker can emulate this format with the alpha version, so we
don't actually need the X version in addition...
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26870 >
2024-01-09 13:45:38 +00:00
Erik Faye-Lund
ee8ac6a7a2
mesa/st: do not require render-target support for texture-only exts
...
These extensions only enable texturing support for these formats, so we
don't need to require them to be renderable.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26870 >
2024-01-09 13:45:38 +00:00
Iago Toral Quiroga
5c42d6c62f
v3dv: implement VK_EXT_shader_demote_to_helper_invocation
...
Demoting means that we don't execute any writes to memory but
otherwise the invocation continues to execute. Particularly,
subgroup operations and derivatives must work.
Our implementation of discard does exactly this by using
setmsf to prevent writes for the affected invocations, the
only difference for us is that with discard/terminate we
want to be more careful with emitting quad loads for tmu
operations, since the invocations are not supposed to be
running any more and load offsets may not be valid, but with
demote the invocations are not terminated and thus we should
emit memory reads for them to ensure quad operations and
derivatives from invocations that have not been demoted still
work.
Since we use the sample mask to implement demotes we can't tell
whether a particular helper invocation was originally such
(gl_HelperInvocation in GLSL) or was later demoted
(OpIsHelperInvocationEXT added with SPV_EXT_demote_to_helper_invocation),
so we use nir_lower_is_helper_invocation to take care of this.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26949 >
2024-01-09 13:22:37 +00:00
Konstantin Seurer
658ce711d5
radv/rt: Lower ray payloads to registers
...
This should allow for cross stage optimizations and it reduces latency
caused by scratch access.
Totals from 44 (9.69% of 454) affected shaders:
MaxWaves: 432 -> 436 (+0.93%)
Instrs: 2740662 -> 1610327 (-41.24%); split: -41.24%, +0.00%
CodeSize: 14616932 -> 8573620 (-41.34%)
VGPRs: 4880 -> 4816 (-1.31%)
SpillSGPRs: 464 -> 294 (-36.64%)
Latency: 18548886 -> 11465281 (-38.19%); split: -38.19%, +0.00%
InvThroughput: 5195964 -> 3066729 (-40.98%); split: -40.98%, +0.00%
VClause: 99672 -> 55611 (-44.21%)
SClause: 65827 -> 38697 (-41.21%)
Copies: 231231 -> 137676 (-40.46%); split: -40.47%, +0.01%
Branches: 111379 -> 65865 (-40.86%); split: -40.87%, +0.00%
PreSGPRs: 3854 -> 3812 (-1.09%); split: -1.19%, +0.10%
PreVGPRs: 4518 -> 4439 (-1.75%); split: -1.84%, +0.09%
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26431 >
2024-01-09 13:02:11 +00:00
Sviatoslav Peleshko
8e6d28f473
intel/tools/tests: Add i965_asm tests for gfx12 and gfx12.5
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b87fc2125e
intel/tools/tests: Unbreak i965_asm tests
...
Currently it's searching for test cases in the nonexistent folders, and
because there are none, tests always pass. Point the script onto the
correct ones. And while we're at it, add a check to make sure this
situation won't repeat in the future.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bb2083a57c
intel/tools/tests: Fix sends indirect argument in gfx9 test
...
Currently it's in the wrong format. It was fixed in disasm in
98aab272sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98d2461424
intel/tools/i965_asm: Don't set src0 for break and while on gfx12
...
This effectively implements same changes as were done to codegen in
bafc9515sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
db4d58fe31
intel/tools/i965_asm: Add dp4a and add3 instructions
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
88fcd305be
intel/tools/i965_asm: Implement gfx12 and gfx12.5 send/sendc
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
bc46cc7807
intel/tools/i965_asm: Allow src0 and src2 of ternary instructions to be imm
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
8eaa0db13f
intel/tools/i965_asm: Don't override flag reg from cond modifier
...
Both predication and conditional modifier use the same flag, but in
assembly it's specified only once. If the instruction already has a
flag from predication we should not override it with zeroes.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
f96e08f34d
intel/tools/i965_asm: Allow neg and abs modifiers on accumulator register
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
98665e024f
intel/tools/i965_asm: Handle sync instruction
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
9dd3a6f86f
intel/tools/i965_asm: Handle HF immediates
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
0c41a8f5d6
intel/tools/i965_asm: Add SWSB handling
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
cfb34dc695
intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
dbf6f0291a
intel/fs: Set group 0 for Wa_14010017096 MOV instruction
...
We always set exec size to 16 for this MOV, but the execution group remains
from the previous emitted instruction. This can cause emitting a group
which violates PRM restriction for ChanOff: "The execution size (ExecSize)
must be a factor of the chosen offset."
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
173a991405
intel/disasm: Print src1_len correctly depending on ExDesc type
...
There are two "Src1.Length" with different formats in "send" description
in the PRMs. One is part of ExMsgDesc, is relevant for LSC SFIDs, and
exists if [ExDesc.IsReg]==false. The other is just a 5-bit immediate,
is relevant for other SFIDs too, and exists if ([ExDesc.IsReg]==true)
AND ([ExBSO]==true).
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
b5c0b90402
intel/compiler: Set flag reg to 0 when disabling predication
...
Having the reg set with predication disabled shouldn't cause any problems
during the execution. But when decompiling such instruction the flag won't
be shown in the output, so the recompiling will cause
functionally-identical but binary-different code. Fixing this makes
disasm/asm testing easier.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
a129e136de
intel/disasm: Print half-float values instead of placeholder
...
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:52 +00:00
Sviatoslav Peleshko
4f41c44df2
intel/compiler: Add variable to dump binaries of all compiled shaders
...
This can be useful for testing i965_disasm and i965_asm by comparing
bin -> asm -> bin results.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25657 >
2024-01-09 11:35:51 +00:00
Alejandro Piñeiro
54e2e44f99
broadcom/compiler: remove one superfluous call to nir_opt_undef
...
v3d_optimize_nir is calling nir_opt_undef twice. As it is inside the
usual "do {..} while (progress);" loop, is not needed to call it
twice.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26928 >
2024-01-09 12:02:36 +01:00
Italo Nicola
a60c52e5f8
panfrost: expose support for EXT_copy_image
...
This was held back by the issue fixed in the previous patch. Let's
enable it again!
There's a bunch of failures due to a bug in Piglit, where undefined
behavior gets invoked. Let's just mark them as expected failures for now
and move on.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
17a62ff993
panfrost: legalize afbc before blitting
...
If we legalize AFBC late, we end up in a situation while we might need
to do a blit while inside a previous blit operation, but u_blitter
state isn't saved recursively, and that leads to crashes.
This patch solves this issue by splitting panfrost_blit into two
functions and legalizing AFBC early.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
5027b5aa28
gallium: stop calling resource_copy_region for multisampled copy_image
...
The hook explicitly says it's not supposed to be called for nr_samples > 1.
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Italo Nicola
c6a7d0ead2
panfrost: fix untracked dependency when converting resource modifier
...
Signed-off-by: Italo Nicola <italonicola@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Erik Faye-Lund
3e1708ea40
panfrost: document ci failure
...
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24942 >
2024-01-09 09:21:29 +00:00
Konstantin Seurer
2e4951d3fb
radv: Remove the BVH depth heuristics
...
It only helps Quake II RTX and hurts everything else.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26481 >
2024-01-09 09:00:24 +00:00
Konstantin Seurer
719619c477
radv: Use PLOC for TLAS builds
...
Improves control performance by about 1%.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26481 >
2024-01-09 09:00:24 +00:00
Dave Airlie
71bd479a7f
radv: don't emit cp dma packets on video rings.
...
Only emit this on the gfx/ace rings.
Fixes hangs with CTS on video decode with navi3x.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26945 >
2024-01-09 07:39:52 +00:00
Sergi Blanch Torne
5cee5578f7
Revert "ci: disable Collabora's LAVA lab for maintance"
...
This reverts commit 11b707de0esergi.blanch.torne@collabora.com >
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26900 >
2024-01-09 07:54:30 +01:00
Caio Oliveira
dc2170f32b
ci: Add Werror=misleading-indentation to debian-clang
...
Due to some issues with GCC and this warning in very long files, we
disabled it when compiling NIR. Unfortunately by design Meson doesn't
allow us to set flags per source file.
The warning is still enabled in clang. but it is less commonly
used during development. To avoid missing catching those warnings,
add -Werror=misleading-indentation to the GitLab CI debian-clang build.
See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25315 for
more context. This patch is a transcription of what Eric Engestrom
suggested, except only targetting C flags (since we only disable them
for C in NIR build).
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Reviewed-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26938 >
2024-01-09 05:56:16 +00:00
Karol Herbst
6024bbed3c
rusticl/llvm: do not include spirv-tools/linker.hpp
...
This was left by mistake as we do not cache the linked output.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10404
Fixes: 299f949775kherbst@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26943 >
2024-01-09 05:12:53 +00:00
