Commit Graph

183869 Commits

Author SHA1 Message Date
Dave Airlie
15e6d8b8d2 egl/dri2: don't bind dri2 for zink
I'm not sure why zink would want dri2 here instead of kopper,
I'm sure it's some side effect of something else, let zink
use the kopper paths.

This fixes:
dEQP-GL45-ES3.info.vendor
on zink on nvk with GL cts using EGL.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Fixes: 12a47b84b7 ("egl/dri2: trigger drawable invalidation from surface queries for zink")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28707>
(cherry picked from commit 223aedfa5d)
2024-04-21 22:21:51 +02:00
Mike Blumenkrantz
431c00e39d lavapipe: clamp 32bit query results to low 32 bits rather than MIN
this should be more consistent with hardware driver behavior

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28671>
(cherry picked from commit ede4e4aae3)
2024-04-21 22:21:51 +02:00
Mike Blumenkrantz
62cba397d1 llvmpipe: clamp 32bit query results to low 32 bits rather than MIN
this should be more consistent with hardware driver behavior

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28671>
(cherry picked from commit 129bebd519)
2024-04-21 22:21:51 +02:00
Patrick Lerda
052f4952f2 r300: fix r300_draw_elements() behavior
Indeed, the pointer processed by r300_upload_index_buffer() was not the right one.
This is the reason why "deqp-gles2 --deqp-case=dEQP-GLES2.functional.draw.draw_elements.indices.user_ptr.index_byte"
was failing (the logs are below). This change corrects this issue and makes the related deqp tests work properly.

This change considers that r300_upload_index_buffer() sets indexBuffer to NULL. The indexBuffer resource
should be properly freed once the buffer is processed. This is required to avoid another refcnt imbalance
(another kind of memory leak).

==9962==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200000721f at pc 0x7fd57b54a9a0 bp 0x7fffd2c39290 sp 0x7fffd2c38a40
READ of size 30 at 0x60200000721f thread T0
    #0 0x7fd57b54a99f in __interceptor_memcpy (/usr/lib64/libasan.so.6.0.0+0x3c99f)
    #1 0x7fd570d10528 in u_upload_data ../src/gallium/auxiliary/util/u_upload_mgr.c:333
    #2 0x7fd57114142b in r300_upload_index_buffer ../src/gallium/drivers/r300/r300_screen_buffer.c:44
    #3 0x7fd57113943c in r300_draw_elements ../src/gallium/drivers/r300/r300_render.c:632
    #4 0x7fd57113bbc4 in r300_draw_vbo ../src/gallium/drivers/r300/r300_render.c:840
    #5 0x7fd570d212e2 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1487
    #6 0x7fd56fceb873 in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:1709
    #7 0x7fd56fcf28c5 in _mesa_DrawElementsBaseVertex ../src/mesa/main/draw.c:1852

Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28523>
(cherry picked from commit 2b6993cb71)
2024-04-21 22:21:51 +02:00
nyanmisaka
c4b6f6b450 radeonsi/uvd_enc: update to use correct padding size
Update padding size calculation to use cropping.
Original method could result in 0 padding, which
generated unnessary noise in the encoding result.

Cc: mesa-stable
Fixes: mesa/mesa#9196

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28369>
(cherry picked from commit 7d00b759f3)
2024-04-21 22:21:51 +02:00
Sagar Ghuge
8b496ec0ab anv: Use appropriate argument format for indirect draw
If index is specified we can use the DRAWINDEXED otherwise we can simply
use DRAW argument format.

v2: (Rohan & Lionel)
- Fix the aligned_stride check

Fixes: 6d4f43f0d6 ("anv: Emit EXECUTE_INDIRECT_DRAW when available")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28658>
(cherry picked from commit 0aa632b519)
2024-04-21 22:21:51 +02:00
Georg Lehmann
2a82433d7b aco: use v1 definition for v_interp_p1lv_f16
The result of the first interpolation step is always fp32.

Fixes: 1647e098e9 ("aco: implement 16-bit interp")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28435>
(cherry picked from commit 893ee883fe)
2024-04-21 22:21:51 +02:00
Mike Blumenkrantz
bc76037811 zink: block LA formats with srgb
this doesn't work correctly

fixes #7218

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28674>
(cherry picked from commit 934188c3ca)
2024-04-21 22:21:51 +02:00
Jonathan Gray
dc3a8b54b8 intel/dev: 0x7d45 is mtl-u not mtl-h
Ref: https://ark.intel.com/content/www/us/en/ark/products/237327/intel-core-ultra-7-processor-155u-12m-cache-up-to-4-80-ghz.html
Ref: Core Ultra Processor Datasheet, Doc. No.: 792044, Rev.: 002
Fixes: 48ff68820e ("intel/dev: Enable MTL PCI ids")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27973>
(cherry picked from commit 094a0a2ccb)
2024-04-21 22:21:51 +02:00
Sagar Ghuge
e01f71ad46 anv: Fix typo in DestinationAlphaBlendFactor value
Workaround states that if Destination Alpha Blend
Factor==BLENDFACTOR_ZERO, instead use BLENDFACTOR_CONST_ALPHA with the
constant alpha set to 0.

We had typo while setting the DestinationAlphaBlendFactor, use
BLENDFACTOR_CONST_ALPHA instead of BLENDFACTOR_CONST_COLOR.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28640>
(cherry picked from commit 7cc604ed1b)
2024-04-21 22:21:51 +02:00
Mike Blumenkrantz
658e39802c lavapipe: don't clamp index buffer size for null index buffer draws
this should execute however many draws the user is trying to execute

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28656>
(cherry picked from commit a5a2bd2969)
2024-04-21 22:21:50 +02:00
Jonathan Gray
9376ec8dcd intel/dev: update DG2 device names
Ref: 864f42116c/shared/source/dll/devices/devices_base.inl (L53)
Fixes: 98f3d072b4 ("intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28643>
(cherry picked from commit fef9ad6f66)
2024-04-21 22:21:50 +02:00
Jonathan Gray
c73b6da5b3 intel/dev: update DG2 device names
Ref: https://ark.intel.com/content/www/us/en/ark/products/237549/intel-arc-a380e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237552/intel-arc-a310e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237550/intel-arc-a370e-graphics.html
Ref: https://ark.intel.com/content/www/us/en/ark/products/237551/intel-arc-a350e-graphics.html
Ref: 864f42116c/shared/source/dll/devices/devices_base.inl (L49)
Fixes: c74a578c54 ("intel/dev: Add 0x56ba-0x56bd DG2 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28643>
(cherry picked from commit a02d8c811d)
2024-04-21 22:21:50 +02:00
Eric Engestrom
d731bfcd54 .pick_status.json: Update to 2bb102f020 2024-04-21 22:21:50 +02:00
Yonggang Luo
b255492acb compiler/spirv: vtn_add_printf_string support for handling OpBitcast
specifically, it's handling
         %48 = OpBitcast %_ptr_UniformConstant_uchar %_str
         %49 = OpBitcast %_ptr_UniformConstant_uchar %_str_1

; SPIR-V
; Version: 1.4
; Generator: Khronos SPIR-V Tools Linker; 0
; Bound: 53
; Schema: 0
               OpCapability Addresses
               OpCapability Kernel
               OpCapability Int64
               OpCapability Int8
          %1 = OpExtInstImport "OpenCL.std"
               OpMemoryModel Physical64 OpenCL
               OpEntryPoint Kernel %2 "main_test" %_str %_str_1
          %5 = OpString "kernel_arg_type.main_test.float*,uint*,"
          %6 = OpString "kernel_arg_type_qual.main_test.,,"
               OpSource OpenCL_C 102000
               OpName %_str ".str"
               OpName %_str_1 ".str.1"
               OpName %main_test "main_test"
               OpName %src "src"
               OpName %dest "dest"
               OpName %entry "entry"
               OpName %src_addr "src.addr"
               OpName %dest_addr "dest.addr"
               OpName %arrayidx "arrayidx"
               OpName %call "call"
               OpName %src_0 "src"
               OpName %dest_0 "dest"
               OpModuleProcessed "Linked by SPIR-V Tools Linker"
               OpDecorate %_str Constant
               OpDecorate %_str Alignment 1
               OpDecorate %_str_1 Constant
               OpDecorate %_str_1 Alignment 1
               OpDecorate %src Alignment 4
               OpDecorate %dest Alignment 4
               OpDecorate %src_addr Alignment 8
               OpDecorate %dest_addr Alignment 8
               OpDecorate %src_0 Alignment 4
               OpDecorate %dest_0 Alignment 4
      %ulong = OpTypeInt 64 0
      %uchar = OpTypeInt 8 0
       %uint = OpTypeInt 32 0
    %ulong_7 = OpConstant %ulong 7
   %uchar_37 = OpConstant %uchar 37
  %uchar_115 = OpConstant %uchar 115
   %uchar_58 = OpConstant %uchar 58
   %uchar_32 = OpConstant %uchar 32
  %uchar_102 = OpConstant %uchar 102
    %uchar_0 = OpConstant %uchar 0
    %ulong_5 = OpConstant %ulong 5
   %uchar_84 = OpConstant %uchar 84
  %uchar_101 = OpConstant %uchar 101
  %uchar_116 = OpConstant %uchar 116
    %ulong_0 = OpConstant %ulong 0
%_arr_uchar_ulong_7 = OpTypeArray %uchar %ulong_7
%_ptr_UniformConstant__arr_uchar_ulong_7 = OpTypePointer UniformConstant %_arr_uchar_ulong_7
%_arr_uchar_ulong_5 = OpTypeArray %uchar %ulong_5
%_ptr_UniformConstant__arr_uchar_ulong_5 = OpTypePointer UniformConstant %_arr_uchar_ulong_5
       %void = OpTypeVoid
      %float = OpTypeFloat 32
%_ptr_CrossWorkgroup_float = OpTypePointer CrossWorkgroup %float
%_ptr_CrossWorkgroup_uint = OpTypePointer CrossWorkgroup %uint
         %40 = OpTypeFunction %void %_ptr_CrossWorkgroup_float %_ptr_CrossWorkgroup_uint
%_ptr_Function__ptr_CrossWorkgroup_float = OpTypePointer Function %_ptr_CrossWorkgroup_float
%_ptr_Function__ptr_CrossWorkgroup_uint = OpTypePointer Function %_ptr_CrossWorkgroup_uint
%_ptr_UniformConstant_uchar = OpTypePointer UniformConstant %uchar
         %44 = OpConstantComposite %_arr_uchar_ulong_7 %uchar_37 %uchar_115 %uchar_58 %uchar_32 %uchar_37 %uchar_102 %uchar_0
       %_str = OpVariable %_ptr_UniformConstant__arr_uchar_ulong_7 UniformConstant %44
         %45 = OpConstantComposite %_arr_uchar_ulong_5 %uchar_84 %uchar_101 %uchar_115 %uchar_116 %uchar_0
     %_str_1 = OpVariable %_ptr_UniformConstant__arr_uchar_ulong_5 UniformConstant %45
  %main_test = OpFunction %void DontInline %40
        %src = OpFunctionParameter %_ptr_CrossWorkgroup_float
       %dest = OpFunctionParameter %_ptr_CrossWorkgroup_uint
      %entry = OpLabel
   %src_addr = OpVariable %_ptr_Function__ptr_CrossWorkgroup_float Function
  %dest_addr = OpVariable %_ptr_Function__ptr_CrossWorkgroup_uint Function
               OpStore %src_addr %src Aligned 8
               OpStore %dest_addr %dest Aligned 8
         %46 = OpLoad %_ptr_CrossWorkgroup_float %src_addr Aligned 8
   %arrayidx = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_float %46 %ulong_0
         %47 = OpLoad %float %arrayidx Aligned 4
         %48 = OpBitcast %_ptr_UniformConstant_uchar %_str
         %49 = OpBitcast %_ptr_UniformConstant_uchar %_str_1
       %call = OpExtInst %uint %1 printf %48 %49 %47
         %50 = OpLoad %_ptr_CrossWorkgroup_uint %dest_addr Aligned 8
               OpStore %50 %call Aligned 4
               OpReturn
               OpFunctionEnd
          %2 = OpFunction %void DontInline %40
      %src_0 = OpFunctionParameter %_ptr_CrossWorkgroup_float
     %dest_0 = OpFunctionParameter %_ptr_CrossWorkgroup_uint
         %51 = OpLabel
         %52 = OpFunctionCall %void %main_test %src_0 %dest_0
               OpReturn
               OpFunctionEnd

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26775>
(cherry picked from commit 616c0cd067)
2024-04-21 22:01:10 +02:00
Eric Engestrom
976b75c8c5 docs: add sha256sum for 24.0.5 2024-04-10 21:28:48 +01:00
Eric Engestrom
7737614720 VERSION: bump for 24.0.5 mesa-24.0.5 2024-04-10 21:17:49 +01:00
Eric Engestrom
4de817cee2 docs: add release notes for 24.0.5 2024-04-10 21:17:45 +01:00
José Roberto de Souza
066c61c748 intel: Enable Xe KMD support by default
Xe KMD landed on drm-next, uAPI is now stable and we can remove
the build time parameter to enable support to it but platforms
older than Lunar lake will have experimental support with Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20418>
(cherry picked from commit 31920cb60c)
2024-04-10 21:12:05 +01:00
David Heidelberg
cbbf9d781b r600: add license information to the sfn_shader_gs.h
Fixes: 79ca456b48 ("r600/sfn: rewrite NIR backend")
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28395>
(cherry picked from commit fd3d125343)
2024-04-09 22:08:43 +01:00
David Heidelberg
4a33e47af5 r600: add license info to the r600_opcodes.h
Fixes: a3a94554f5 ("r600g: split opcodes out and add wrapper around usage.")
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28395>
(cherry picked from commit 722e5bf46f)
2024-04-09 22:08:42 +01:00
David Heidelberg
df4f6b5491 r600: add license header to r600_formats.h
The header was missing after the definitions were moved.

Fixes: 82114ac02a ("r600g: switch to a common formats.h file since they are in different regs")

Acked-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28395>
(cherry picked from commit 0020dd85ee)
2024-04-09 22:08:42 +01:00
Axel Davy
b1087acbcb frontend/nine: Reset should EndScene
This was reported by some users.

Cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28232>
(cherry picked from commit c6468f6547)
2024-04-09 22:08:41 +01:00
Axel Davy
7bf97678dd frontend/nine: Fix destruction race
As we were checking the bind count after decreasing the ref count,
we could hit a situation where the worker thread decreases the bind count
just after the ref count is decreased, but before the bind count is checked
which would lead to both threads calling the resource dtor.

Cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28232>
(cherry picked from commit d6044cf857)
2024-04-09 22:08:40 +01:00
Axel Davy
63873590d8 frontend/nine: Fix missing light flag check
The constants for ff lights use the VIEW matrix,
thus we must update them if the matrix is dirty.

Cc: mesa-stable

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28232>
(cherry picked from commit b4a14c7ebf)
2024-04-09 22:08:39 +01:00
Axel Davy
64b0629062 frontend/nine: Fix programmable vs check
Checking if context->vs is set is not
equivalent to checking programmable vs

Cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28232>
(cherry picked from commit d3cec6cdf1)
2024-04-09 22:08:39 +01:00
Axel Davy
e1c686778a frontend/nine: Fix ff ps key
The stage index, rather than the
texture coord index was used.

Cc: mesa-stable
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28232>
(cherry picked from commit 9063d554f3)
2024-04-09 22:08:38 +01:00
Konstantin Seurer
ad2594ead4 nir/serialize: Encode data for temporaries
the location has to be preserved when lowering them to scratch using
nir_lower_vars_to_explicit_types and nir_lower_explicit_io.

cc: mesa-stable

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28187>
(cherry picked from commit edc8e011eb)
2024-04-09 22:08:37 +01:00
Paul Gofman
b573f69885 driconf: add a workaround for Joe Danger
CC: mesa-stable
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28439>
(cherry picked from commit 27dba224d3)
2024-04-09 22:08:36 +01:00
Paul Gofman
b351969fa2 driconf: add a workaround for Joe Danger 2
CC: mesa-stable
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28439>
(cherry picked from commit 2abb72f512)
2024-04-09 22:08:35 +01:00
Paul Gofman
50669655ed glsl: allow out arrays in #110 with allow_glsl_120_subset_in_110
CC: mesa-stable
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28439>
(cherry picked from commit bd189dbd77)
2024-04-09 22:08:35 +01:00
Paulo Zanoni
dac8689fc3 anv, iris: add missing CS_STALL bit for GPGPU texture invalidation
The BSpec page "Flush Types" (46213) says the following about the Tex
Invalidate bit:

  "Requires stall bit ([20] of DW) set for all GPGPU Workloads."

For newer platforms, this is documented in the description of the
texture invalidation bit in the PIPE_CONTROL page (56551):

  "CS Stall bit in PIPE_CONTROL command must be always set for GPGPU
   workloads when Texture Cache Invalidation Enable bit is set"

Iris had it only for GFX_VER 9 and 11, while Anv had it missing for
everything.

Please notice that this patch includes a revert of 397e728ef4.

Fixes: 397e728ef4 ("iris: Drop GPGPU Tex Invalidate restriction for TGL+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28608>
(cherry picked from commit cf7e1f3817)
2024-04-09 22:08:34 +01:00
Zack Rusin
c73e830dc9 svga: Fix instanced draw detection
The new GTK+ GL renderer is extensively using instanced rendering. SVGA
driver was incorrectly detecting the instanced draws by only checking
whether the instance count was greater than 1. Base instance has to
be also checked to make sure that the draw correctly offsets the vertex
buffer.

Fix instanced draw detection by checking both the instance count and
the base instance. Fixes the new GTK+ 4 GL renderer.

Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
Fixes: ccb4ea5a43 ("svga: Add GL4.1(compatibility profile) support in svga driver")
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28616>
(cherry picked from commit 955444e068)
2024-04-09 22:08:33 +01:00
Lucas Stach
5eb9128a52 etnaviv: rs: take src dimensions into account when increasing height alignment
When trying to increase the height alignment to unlock multi-pipe resolve for
better performance we need to be careful to not overstep the source dimensions
as this would cause the blit to be rejected.

Do so and also rearrange the code a bit to make it more obvious what is being
done.

Fixes: 797454edfc ("etnaviv: rs: fix blits with insufficient alignment for dual pipe operation")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28598>
(cherry picked from commit 2964812aac)
2024-04-09 22:08:32 +01:00
Lionel Landwerlin
a6aa5d30d7 isl: set NullPageCoherencyEnable for depth/stencil sparse surfaces
Not setting this bits, it seems we get incorrect depth values (i.e
not zero) for null depth/stencil tiles.

Fixes vkd3d-proton's test_sparse_depth_stencil_rendering

CTS doesn´t seem to exercise any depth/stencil format.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28611>
(cherry picked from commit 2dd321963f)
2024-04-09 22:08:31 +01:00
Lionel Landwerlin
b3a65a1881 anv: mark descriptors & pipeline dirty after blorp compute
All of those are used by blorp, we need to reemit it when doing the
next compute dispatch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 37fca614b8 ("anv/blorp: Split blorp_exec into a render and compute")
Fixes: 6823ffe70e ("anv: try to keep the pipeline in GPGPU mode when buffer transfer ops")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10972
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28617>
(cherry picked from commit c3d30d9e65)
2024-04-09 22:08:29 +01:00
Faith Ekstrand
60c8db6cd1 nvk: Add a _pad field to nvk_fs_key
Fixes: ae17145882 ("nak: Rewrite nir_intrinsic_load_sample_pos...")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28615>
(cherry picked from commit 987cbaee2a)
2024-04-09 22:05:38 +01:00
Eric R. Smith
3e9ac50d37 gallium: handle copy_image of depth textures
copy_image calls blit now for multisampled images, including
depth. But blit explicitly uses only PIPE_MASK_RGBA, so it is
incapable of copying depth buffers.

This patch checks the destination format and uses PIPE_MASK_ZS if
it is a depth or stencil. Ideally we would simply use PIPE_MASK_RGBAZS
always, but not all drivers actually handle getting this mask
(they probably should, but that's another story).

The change to copy_image was in 5027b5aa2, so in some sense this
patch "fixes" that. In fact though the issue wasn't in the copy_image
change, it was always latent in blit().

Fixes: 5027b5aa28 ("gallium: stop calling resource_copy_region for multisampled copy_image")
Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28585>
(cherry picked from commit 0cb852050d)
2024-04-09 22:05:37 +01:00
Lionel Landwerlin
6dab9b4a6d anv: add missing data flush out of L3 for transform feedback writes
Fixes zink's piglit.spec.arb_shader_image_load_store.host-mem-barrier on TGL

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28492>
(cherry picked from commit fe36cf6cad)
2024-04-09 22:05:35 +01:00
Jesse Natalie
45904c576d glsl: Use a stable attr sort for VS in / FS out
This is a perpetual bug that hits Windows. In the MSVC CRT, qsort
is unstable, where the glibc qsort is stable. So apps run fine on
Windows IHV drivers, and on Linux Mesa drivers, and only break down
when running on Windows Mesa drivers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10922
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28586>
(cherry picked from commit acbf3ad1fb)
2024-04-09 22:05:34 +01:00
Eric Engestrom
1971a267bc .pick_status.json: Update to 2c1cb65949 2024-04-09 22:05:24 +01:00
David Heidelberg
5681b3604a ci/amd: drop old PIGLIT_REPLAY_DESCRIPTION_FILE surpassed by PIGLIT_TRACES_FILE
This got probably accidentally in, as Eric MR changing this was just
before this change got in.

Fixes: 16af090908 ("ci/lava: separate HW definitions from SW")
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28600>
(cherry picked from commit 5b69cbb80a)
2024-04-09 22:00:22 +01:00
José Roberto de Souza
0d608f1b5b anv: Create protected engine context when i915 supports vm control
When has_vm_control is supported it takes a different code path and
creates one context per engine and in this code path we were not
setting the protected context flag.

The lack of this is not causing any test to fail in our CI but it is
better do what we are supposed to do.

Fixes: fd40134487 ("anv: allow protected GEM context creation")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28299>
(cherry picked from commit 77c004f7ca)
2024-04-09 22:00:20 +01:00
Samuel Pitoiset
a5d4638ed5 radv: make sure the heap budget is less than or equal to the heap size
Reported by Hans-Kristian.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28575>
(cherry picked from commit 14ba56718f)
2024-04-09 22:00:19 +01:00
Jordan Justen
0deacc982b intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs
Ref: bspec 44477
Backport-to: 24.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28584>
(cherry picked from commit 98f3d072b4)
2024-04-09 22:00:13 +01:00
Lionel Landwerlin
955d6229c1 anv: update protection fault property
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 794b0496e9 ("anv: enable protected memory")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
(cherry picked from commit 9b0f028c7e)
2024-04-09 21:59:21 +01:00
Lionel Landwerlin
9e225ce531 anv: disable generated draws in protected command buffers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 794b0496e9 ("anv: enable protected memory")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
(cherry picked from commit d2e490dc4d)
2024-04-09 21:58:41 +01:00
Lionel Landwerlin
3935eb328f anv: disable protected content around surface state copies
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 794b0496e9 ("anv: enable protected memory")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
(cherry picked from commit 034a1cdb58)
2024-04-09 21:55:58 +01:00
Lionel Landwerlin
f144f32686 anv: fix protected memory allocations
Using the wrong flag field...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5f2c77a10a ("anv: handle protected memory allocation")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
(cherry picked from commit 07bf480856)
2024-04-09 21:50:41 +01:00
Mike Blumenkrantz
5e02f105d0 nir/texcoord_replace: fix scalarized io handling
if a texcoord load only loads some components, only those components
should be replaced

cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28463>
(cherry picked from commit 0851c30d16)
2024-04-09 21:45:10 +01:00