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Author SHA1 Message Date
Eric Engestrom
418e19a6ff .pick_status.json: Update to 4660ee1dea 2024-04-25 16:16:21 +02:00
Eric Engestrom
b0de5e98f0 VERSION: bump for 24.1.0-rc1 mesa-24.1.0-rc1 2024-04-24 22:28:09 +02:00
Marek Olšák
c3fc214a98 radeonsi: implement user_data_amd for 5, 6, and 7 components correctly 
NIR can't handle those component counts, so we have to split it into 2
SGPR vectors where each has max 4 components.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
24.1-branchpoint 		2024-04-24 19:17:10 +00:00
Marek Olšák
882ee264a6 radeonsi: use ip_type in debug code instead of hardcoding GFX 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
e7000c02e4 radeonsi: always run nir_opt_16bit_tex_image 
It optimizes constants in srcs to 16 bits.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
18bcdbb634 radeonsi: only expose 8 EQAA samples due to shader limitations 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
256cc77f84 radeonsi: don't add whether NIR is used into the shader key 
This is from when we had TGSI and NIR was a debug option.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
e5c8f0781c radeonsi: make clear_render_target clear DCC directly instead of via pipe->clear() 
This extracts the relevant parts from si_fast_clear.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
eccaba9dfa radeonsi: enable fast FB clears for conditional rendering 
They use compute shaders, which always support the render condition.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
9a47fbecd7 radeonsi: don't flush CB and DB if there have been no draw calls 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
f0160443a2 radeonsi: don't flush CB in si_launch_grid_internal_images if not needed 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
708f57e681 radeonsi: don't use si_get_flush_flags() for flushing images 
si_make_{CB/DB}_shader_coherent are more correct.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
38f74d6277 radeonsi: disable VRS flat shading for selected 8xMSAA and thick tiling cases 
for better slow clear performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
86131c25a1 radeonsi/gfx11: implement DCC clear to "single" for fast non-0/1 clears 
If the clear color isn't 0 or 1, we used a slow clear. This adds a new
DCC clear where the DCC buffer is cleared to a special value and the clear
color is stored at the beginning of each 256B block in the image.

It can be very fast, but it's not always faster than a slow clear.
There is a heuristic that determines whether this new fast clear is
better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
10ec468983 radeonsi: don't call resource_copy_region in pipe->blit 
It's slower because it forces preservation of NaNs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
26a5955821 radeonsi: change allow_flat_shading to make it a single condition 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
494cad56c4 radeonsi: remove si_use_compute_copy_for_float_formats 
Gfx blits preserve NaNs now, so this is no longer needed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
18b7b2c806 radeonsi: use simpler UINT fallback formats for draw-based resource_copy_region 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
8235d3aa19 radeonsi: preserve NaNs in draw-based resource_copy_region 
Gfx copies are faster sometimes, so they should be able to copy anything.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
a03df53d3b radeonsi: move blitter clear_render_target impl into si_gfx_clear_render_target 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
82e63db91f radeonsi: move blitter resource_copy_region implementation to si_gfx_copy_image 
for a new performance test.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
e94813204a radeonsi: allow input NIR to use descriptors in image opcodes 
Skip lowering because there is nothing to lower.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
30fab15f39 radeonsi: don't expose samples_identical and don't lower FMASK if it's disabled 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
dab4295cd5 radeonsi: fix initialization of occlusion query buffers for disabled RBs 
GFX9+ should assume the enabled RB results are packed (no holes).
Same as PAL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
aad2302cf5 radeonsi: move TCS epilog key bits to the key->ge.opt section 
Since the TCS epilog is no more, this is required to apply those bits
to monolithic shaders.

tessfactors_are_def_in_all_invocs was unused.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
d29d215df7 radeonsi: check has_stable_pstate in the winsys 
so that we don't duplicate the condition everywhere

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
a094339d64 radeonsi: add the radeonsi_optimize_io option into the shader cache key 
otherwise the options would be ignored if the shader cache had already
cached the same shader with the option inverted.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
3630c11c3b radeonsi: use the same nir_lower_subgroups_options as RADV 
Some FREE calls are removed because nir_options is always NULL there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
adde1dbae5 radeonsi/gfx11: enable DCC fast clears for 8-bit and 16-bit formats 
They seem to work fine.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
d478693dc6 radeonsi/gfx11: don't prefetch constants in binaries into the instruction cache 
Only prefetch shader instructions. There will be more GFX versions
in that list.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
71ae7b85ed radeonsi/ci: update gfx11 failures 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:10 +00:00
Marek Olšák
665df08af4 ac/surface: constify and reindent NIR meta address-from-coord function params 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:09 +00:00
Marek Olšák
cce1aa4766 ac/llvm: always trim components of texture instructions, trim DMASK 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:09 +00:00
Marek Olšák
83a601d420 ac/llvm: fix assertions for texture instructions with 16-bit LOD bias 
A16 dictates the type.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
 2024-04-24 19:17:09 +00:00
José Roberto de Souza
708b0a7c23 intel/dev: Read GFX IP version during runtime 
Starting from MTL there is registers in HW to read the IP version of
graphics, media and display IPs, those registers are called GMD.

IPs can be used in any combination to form a SOC/platform and each IP
has it own stepping/revision, making complex to track each IP stepping
using just PCI revision.

Since MTL will be supported by default by i915 KMD that don't have
a uAPI fetch IP versions, this feature will only be supported in LNL
and newer that are backed by Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26908>
 2024-04-24 18:06:04 +00:00
José Roberto de Souza
4d3fee0b40 intel: Sync xe_drm.h 
Sync xe_drm.h with 31ced035ecde ("drm/xe/uapi: Restore flags VM_BIND_FLAG_READONLY and VM_BIND_FLAG_IMMEDIATE").

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26908>
 2024-04-24 18:06:04 +00:00
Tomeu Vizoso
a78e98f18e etnaviv/nn: Keep track of the sign bit when decrementing to zero 
To avoid underflow.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
9bac40b796 etnaviv/nn: Don't shortcut ZRL bits calculation 
In some (probably malformed) cases, even weights BOs for strided or depthwise
convolutions can become bigger when using ZRL compression.

To avoid running out of space in the BO, play safe and calculate the
actual optimum ZRL bit count. This does slow compilation for quite a
bit, though (2x slower for MobileNetV1).

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
d46e68c89a etnaviv/nn: Enable image cache 
By using the on-chip SRAM to cache the input image we can save some more
bandwidth and increase the utilization of the NN cores, with the
following improvements:

MobileNetV1: 9.991ms -> 6.2ms
SSDLite MobileDet: 27ms -> 24.3ms

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
d6045ca502 etnaviv/nn: Move unused field to its right place in the struct 
The blob sets it in some cases, but doesn't seem to make any difference.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
c75b512673 etnaviv/nn: Fix calculation of remaining out channels 
We were wrongly counting the remaining number of output channels in the
last superblock, when the former isn't divisible by the latter.

MobileNetV1: 9.991ms -> 9.991ms
SSDLite MobileDet: 32.692ms -> 27ms

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
baebd6f43d etnaviv/nn: Ensure tile_y is > 0 
A zero tile dimension doesn't make sense.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
Tomeu Vizoso
e70ea63a17 teflon: Enable convolutions with number of output channels not divisible by 8 
This was an old restriction during initial development which isn't
needed any more, and gives us a speed bump.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
 2024-04-24 17:47:44 +00:00
José Roberto de Souza
b143823727 intel/tools: Parse INSTDONE registers in Xe KMD error dump 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28722>
 2024-04-24 17:07:50 +00:00
José Roberto de Souza
c221ba6f75 intel/decoder: Add intel_print_group_custom_spacing() 
This function has 2 additional parameters to set spacing before
printing register group dword or individual registers.

intel_print_group() is keept with the same spacing as before so no
changes on decoder output is expected here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28722>
 2024-04-24 17:07:50 +00:00
José Roberto de Souza
94deb24e2b intel/tools/aubinator_error_decode: Move definition of option_color to header 
Xe parser will also need to use the option_color parameter.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28722>
 2024-04-24 17:07:50 +00:00
Rohan Garg
7e5628749c anv: use u_foreach_bit to iterate over the the view mask like we do for transition_clear_color 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28629>
 2024-04-24 16:42:07 +00:00
Rohan Garg
5efecc9782 anv: Enable HiZ on multi-LOD depth buffers. 
Initial work by Rafael Antognolli <rafael.antognolli@intel.com>

Reworks
 - Rebase to main
 - Emit the right hiz op for higher mip levels when transitioning the
   depth buffer

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28629>
 2024-04-24 16:42:06 +00:00
Martin Roukala (né Peres)
599e8bf921 ci/valve: remove the traces runner 
This script is severely outdated and has had no use in literal years.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28902>
 2024-04-24 15:46:32 +00:00
Martin Roukala (né Peres)
a589225827 ci/b2c: allow setting the DTB to be used 
This will be used by upcoming new CI jobs.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28902>
 2024-04-24 15:46:32 +00:00