docs: Add release notes for the 9.2.4 release.

In preparation for the 9.2.4 release.

Android.common.mk

@@ -35,7 +35,7 @@ LOCAL_C_INCLUDES += \
 
 # define ANDROID_VERSION (e.g., 4.0.x => 0x0400)
 LOCAL_CFLAGS += \
-	-DPACKAGE_VERSION=\"9.2.0-devel\" \
+	-DPACKAGE_VERSION=\"9.2.4\" \
 	-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\" \
 	-DANDROID_VERSION=0x0$(MESA_ANDROID_MAJOR_VERSION)0$(MESA_ANDROID_MINOR_VERSION)
 

Makefile.am

@@ -50,6 +50,7 @@ EXTRA_FILES = \
 	bin/install-sh					\
 	bin/ltmain.sh					\
 	bin/missing					\
+	bin/test-driver					\
 	bin/ylwrap					\
 	src/glsl/glsl_parser.cpp			\
 	src/glsl/glsl_parser.h				\
@@ -57,12 +58,6 @@ EXTRA_FILES = \
 	src/glsl/glcpp/glcpp-lex.c			\
 	src/glsl/glcpp/glcpp-parse.c			\
 	src/glsl/glcpp/glcpp-parse.h			\
-	src/mesa/main/api_exec_es1.c			\
-	src/mesa/main/api_exec_es1_dispatch.h		\
-	src/mesa/main/api_exec_es1_remap_helper.h	\
-	src/mesa/main/api_exec_es2.c			\
-	src/mesa/main/api_exec_es2_dispatch.h		\
-	src/mesa/main/api_exec_es2_remap_helper.h	\
 	src/mesa/program/lex.yy.c			\
 	src/mesa/program/program_parse.tab.c		\
 	src/mesa/program/program_parse.tab.h		\

SConstruct

@@ -70,7 +70,7 @@ if env['gles']:
 # Environment setup
 
 env.Append(CPPDEFINES = [
-    ('PACKAGE_VERSION', '\\"9.2.0-devel\\"'),
+    ('PACKAGE_VERSION', '\\"9.2.4\\"'),
     ('PACKAGE_BUGREPORT', '\\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\\"'),
 ])
 

bin/.cherry-ignore

@@ -0,0 +1,17 @@
+# Already cherry picked without -x
+d8ac987f6ab228df1a478b36c3d889992754374f glsl: Disallow uniform block layout qualifiers on non-uniform block vars.
+
+# The bug fixed by this patch does not exist in 9.2.  Discussed with Marek and
+# Brian Paul on the mesa-stable mailing list.
+89a665eb5fa176f68223bf54a472d6a0567c3546 draw: fix segfaults with aaline and aapoint stages disabled
+
+# Previously cherry picked (patch originally appeared twice on master with a
+# revert in between)
+4e5eb8ba25054ede4798fa424e6f32b23aba0f98 i965/vec4: Only zero out unused message components when there are any.
+
+# Backported as 7ab2b8c4c4607817c91946dcba943b29f1bd1895 but without "cherry
+# picked from" in commit message
+360a141f24a9d00891665b7fedb77ffb116944ca wayland: Don't rely on static variable for identifying wl_drm buffers
+
+# Code being fixed is not present in 9.2
+f278d49c4bcfedbda10cb224cb251e3755e88288 i965: Do not set bilinear_filter flag in case of multisample blits

bin/get-pick-list.sh

@@ -14,7 +14,7 @@ git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
 	sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
 
 # Grep for commits that were marked as a candidate for the stable tree.
-git log --reverse --pretty=%H -i --grep='^[[:space:]]*NOTE: .*[Cc]andidate' HEAD..origin/master |\
+git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate.*9\.2\|CC:.*9\.2.*mesa-stable\)' HEAD..origin/master |\
 while read sha
 do
 	# Check to see whether the patch is on the ignore list.

configure.ac

@@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output
 m4_divert_once([HELP_END], [
 See docs/autoconf.html for more details on the options for Mesa.])
 
-AC_INIT([Mesa], [9.2.0-devel],
+AC_INIT([Mesa], [9.2.4],
     [https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa])
 AC_CONFIG_AUX_DIR([bin])
 AC_CONFIG_MACRO_DIR([m4])
@@ -579,6 +579,11 @@ AC_ARG_ENABLE([osmesa],
         [enable OSMesa library @<:@default=disabled@:>@])],
     [enable_osmesa="$enableval"],
     [enable_osmesa=no])
+AC_ARG_ENABLE([gallium-osmesa],
+    [AS_HELP_STRING([--enable-gallium-osmesa],
+        [enable Gallium implementation of the OSMesa library @<:@default=disabled@:>@])],
+    [enable_gallium_osmesa="$enableval"],
+    [enable_gallium_osmesa=no])
 AC_ARG_ENABLE([egl],
     [AS_HELP_STRING([--disable-egl],
         [disable EGL library @<:@default=enabled@:>@])],
@@ -769,7 +774,13 @@ if test "x$enable_dri" = xyes; then
     GALLIUM_STATE_TRACKERS_DIRS="dri $GALLIUM_STATE_TRACKERS_DIRS"
 fi
 
-if test "x$enable_osmesa" = xyes; then
+if test "x$enable_gallium_osmesa" = xyes; then
+    if test -z "$with_gallium_drivers"; then
+        AC_MSG_ERROR([Cannot enable gallium_osmesa without Gallium])
+    fi
+    if test "x$enable_osmesa" = xyes; then
+        AC_MSG_ERROR([Cannot enable both classic and Gallium OSMesa implementations])
+    fi
     GALLIUM_STATE_TRACKERS_DIRS="osmesa $GALLIUM_STATE_TRACKERS_DIRS"
     GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS osmesa"
 fi
@@ -1135,7 +1146,7 @@ x16|x32)
     ;;
 esac
 
-if test "x$enable_osmesa" = xyes; then
+if test "x$enable_osmesa" = xyes -o "x$enable_gallium_osmesa" = xyes; then
     # only link libraries with osmesa if shared
     if test "$enable_static" = no; then
         OSMESA_LIB_DEPS="-lm $PTHREAD_LIBS $SELINUX_LIBS $DLOPEN_LIBS"
@@ -1914,8 +1925,8 @@ AM_CONDITIONAL(NEED_GALLIUM_SOFTPIPE_DRIVER, test "x$HAVE_GALLIUM_SVGA" = xyes -
                                                   "x$HAVE_GALLIUM_I915" = xyes -o \
                                                   "x$HAVE_GALLIUM_SOFTPIPE" = xyes)
 AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test "x$HAVE_GALLIUM_I915" = xyes -o \
-                                                  "x$HAVE_GALLIUM_SOFTPIPE" = xyes -a \
-                                                  "x$MESA_LLVM" = x1)
+                                                  "x$HAVE_GALLIUM_SOFTPIPE" = xyes \
+                                                  && test "x$MESA_LLVM" = x1)
 
 if test "x$enable_gallium_loader" = xyes; then
     GALLIUM_WINSYS_DIRS="$GALLIUM_WINSYS_DIRS sw/null"
@@ -1962,9 +1973,11 @@ AC_SUBST([ELF_LIB])
 
 AM_CONDITIONAL(NEED_LIBPROGRAM, test "x$with_gallium_drivers" != x -o \
                                      "x$enable_xlib_glx" = xyes -o \
-                                     "x$enable_osmesa" = xyes)
+                                     "x$enable_osmesa" = xyes -o \
+                                     "x$enable_gallium_osmesa" = xyes)
 AM_CONDITIONAL(HAVE_X11_DRIVER, test "x$enable_xlib_glx" = xyes)
 AM_CONDITIONAL(HAVE_OSMESA, test "x$enable_osmesa" = xyes)
+AM_CONDITIONAL(HAVE_GALLIUM_OSMESA, test "x$enable_gallium_osmesa" = xyes)
 
 AM_CONDITIONAL(HAVE_X86_ASM, echo "$DEFINES" | grep 'X86_ASM' >/dev/null 2>&1)
 AM_CONDITIONAL(HAVE_X86_64_ASM, echo "$DEFINES" | grep 'X86_64_ASM' >/dev/null 2>&1)
@@ -2053,6 +2066,7 @@ AC_CONFIG_FILES([Makefile
 		src/gallium/targets/gbm/Makefile
 		src/gallium/targets/opencl/Makefile
 		src/gallium/targets/osmesa/Makefile
+		src/gallium/targets/osmesa/osmesa.pc
 		src/gallium/targets/pipe-loader/Makefile
 		src/gallium/targets/libgl-xlib/Makefile
 		src/gallium/targets/vdpau-nouveau/Makefile
@@ -2151,11 +2165,17 @@ echo "        OpenVG:          $enable_openvg"
 
 dnl Driver info
 echo ""
-if test "x$enable_osmesa" != xno; then
+case "x$enable_osmesa$enable_gallium_osmesa" in
+xnoyes)
+        echo "        OSMesa:          lib$OSMESA_LIB (Gallium)"
+        ;;
+xyesno)
         echo "        OSMesa:          lib$OSMESA_LIB"
-else
+        ;;
+xnono)
         echo "        OSMesa:          no"
-fi
+        ;;
+esac
 
 if test "x$enable_dri" != xno; then
         # cleanup the drivers var

docs/index.html

@@ -16,6 +16,12 @@
 
 <h1>News</h1>
 
+<h2>August 1, 2013</h2>
+<p>
+<a href="relnotes/9.1.6.html">Mesa 9.1.6</a> is released.
+This is a bug fix release.
+</p>
+
 <h2>July 17, 2013</h2>
 <p>
 <a href="relnotes/9.1.5.html">Mesa 9.1.5</a> is released.

docs/relnotes.html

@@ -22,6 +22,7 @@ The release notes summarize what's new or changed in each Mesa release.
 
 <ul>
 <li><a href="relnotes/9.2.html">9.2 release notes</a>
+<li><a href="relnotes/9.1.6.html">9.1.6 release notes</a>
 <li><a href="relnotes/9.1.5.html">9.1.5 release notes</a>
 <li><a href="relnotes/9.1.4.html">9.1.4 release notes</a>
 <li><a href="relnotes/9.1.3.html">9.1.3 release notes</a>

docs/relnotes/9.1.5.html

@@ -30,7 +30,9 @@ because GL_ARB_compatibility is not supported.
 
 <h2>MD5 checksums</h2>
 <pre>
-TBD
+4ed2af5943141a85a21869053a2fc2eb  MesaLib-9.1.5.tar.bz2
+47181066acf3231d74e027b2033f9455  MesaLib-9.1.5.tar.gz
+4c9c6615bd99215325250f87ed34058f  MesaLib-9.1.5.zip
 </pre>
 
 <h2>New features</h2>

docs/relnotes/9.1.6.html

@@ -0,0 +1,168 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.6 Release Notes / August 1, 2013</h1>
+
+<p>
+Mesa 9.1.6 is a bug fix release which fixes bugs found since the 9.1.5 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+443a2a352667294b53d56cb1a74114e9  MesaLib-9.1.6.tar.bz2
+08d3069cccd6821e5f33e0840bca0718  MesaLib-9.1.6.tar.gz
+90aa7a6d9878cdbfcb055312f356d6b9  MesaLib-9.1.6.zip
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47824">Bug 47824</a> - osmesa using --enable-shared-glapi depends on libgl</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62362">Bug 62362</a> - Crash when using Wayland EGL platform</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63435">Bug 63435</a> - [Regression since 9.0] Flickering in EGL OpenGL full-screen window with swap interval 1</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64087">Bug 64087</a> - Webgl conformance shader-with-non-reserved-words crash when mesa is compiled without --enable-debug</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64330">Bug 64330</a> - WebGL snake demo crash in loop_analysis.cpp:506: bool is_loop_terminator(ir_if*): assertion „inst != __null“ failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=65236">Bug 65236</a> - [i965] Rendering artifacts in VDrift/GL2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66558">Bug 66558</a> - RS690: 3D artifacts when playing SuperTuxKart</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66847">Bug 66847</a> - compilation broken with llvm 3.3</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66850">Bug 66850</a> - glGenerateMipmap crashes when using GL_TEXTURE_2D_ARRAY with compressed internal format</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66921">Bug 66921</a> - [r300g] Heroes of Newerth: HiZ related corruption</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67283">Bug 67283</a> - VDPAU doesn't work on hybrid laptop through DRI_PRIME</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.1.5..mesa-9.1.6
+</pre>
+
+<p>Andreas Boll (1):</p>
+<ul>
+  <li>configure.ac: Require llvm-3.2 for r600g/radeonsi llvm backends</li>
+</ul>
+
+<p>Brian Paul (4):</p>
+<ul>
+  <li>mesa: handle 2D texture arrays in get_tex_rgba_compressed()</li>
+  <li>meta: handle 2D texture arrays in decompress_texture_image()</li>
+  <li>mesa: implement mipmap generation for compressed 2D array textures</li>
+  <li>mesa: improve free() cleanup in generate_mipmap_compressed()</li>
+</ul>
+
+<p>Carl Worth (7):</p>
+<ul>
+  <li>docs: Add 9.1.5 release md5sums</li>
+  <li>Merge 'origin/9.1' into stable</li>
+  <li>cherry-ignore: Drop 13 patches from the pick list</li>
+  <li>get-pick-list.sh: Include commits mentionining "CC: mesa-stable..." in pick list</li>
+  <li>get-pick-list: Allow for non-whitespace between "CC:" and "mesa-stable"</li>
+  <li>get-pick-list: Ignore commits which CC mesa-stable unless they say "9.1"</li>
+  <li>Bump version to 9.1.6</li>
+</ul>
+
+<p>Chris Forbes (5):</p>
+<ul>
+  <li>i965/Gen4: Zero extra coordinates for ir_tex</li>
+  <li>i965/vs: Fix flaky texture swizzling</li>
+  <li>i965/vs: set up sampler state pointer for Gen4/5.</li>
+  <li>i965/vs: Put lod parameter in the correct place for Gen4</li>
+  <li>i965/vs: Gen4/5: enable front colors if back colors are written</li>
+</ul>
+
+<p>Christoph Bumiller (1):</p>
+<ul>
+  <li>nv50,nvc0: s/uint16/uint32 for constant buffer offset</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>gallium/vl: add prime support</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>egl: Restore "bogus" DRI2 invalidate event code.</li>
+</ul>
+
+<p>Jeremy Huddleston Sequoia (1):</p>
+<ul>
+  <li>Apple: glFlush() is not needed with CGLFlushDrawable()</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>glsl: Classify "layout" like other identifiers.</li>
+</ul>
+
+<p>Kristian Høgsberg (1):</p>
+<ul>
+  <li>egl-wayland: Fix left-over wl_display_roundtrip() usage</li>
+</ul>
+
+<p>Maarten Lankhorst (2):</p>
+<ul>
+  <li>osmesa: link against static libglapi library too to get the gl exports</li>
+  <li>nvc0: force use of correct firmware file</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>r300g/swtcl: fix geometry corruption by uploading indices to a buffer</li>
+  <li>r300g/swtcl: fix a lockup in MSAA resolve</li>
+  <li>Revert "r300g: allow HiZ with a 16-bit zbuffer"</li>
+  <li>r600g: increase array size for shader inputs and outputs</li>
+</ul>
+
+<p>Matt Turner (2):</p>
+<ul>
+  <li>i965: NULL check prog on shader compilation failure.</li>
+  <li>i965/vs: Print error if vertex shader fails to compile.</li>
+</ul>
+
+<p>Paul Berry (1):</p>
+<ul>
+  <li>glsl: Handle empty if statement encountered during loop analysis.</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/9.2.1.html

@@ -0,0 +1,206 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.2.1 Release Notes / (October 4, 2013)</h1>
+
+<p>
+Mesa 9.2.1 is a bug fix release which fixes bugs found since the 9.2 release.
+</p>
+<p>
+Mesa 9.2 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+e6cdfa84dfddd86e3d36ec7ff4b6478a  MesaLib-9.2.1.tar.gz
+dd4c82667d9c19c28a553b12eba3f8a0  MesaLib-9.2.1.tar.bz2
+d9af0f5607f7d275793d293057ca9ac6  MesaLib-9.2.1.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66779">Bug 66779</a> - Use of uninitialized stack variable with brw_search_cache()</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68233">Bug 68233</a> - Valgrind errors in mesa</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68250">Bug 68250</a> - Automatic mipmap generation with texture compression produces borders that fade to black</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68637">Bug 68637</a> - [Bisected IVB/HSW]Unigine demo crash</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68753">Bug 68753</a> - [regression bisected] GLSL ES: structs members can't have precision qualifiers anymore in 9.2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=69525">Bug 69525</a> - [GM45, bisected] Piglit tex-shadow2drect fails</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.2..mesa-9.2.1
+</pre>
+
+
+<p>Alex Deucher (1):</p>
+<ul>
+  <li>radeon/winsys: pad IBs to a multiple of 8 DWs</li>
+</ul>
+
+<p>Andreas Boll (1):</p>
+<ul>
+  <li>os: First check for __GLIBC__ and then for PIPE_OS_BSD</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>glsl: Allow precision qualifiers for sampler types</li>
+</ul>
+
+<p>Brian Paul (2):</p>
+<ul>
+  <li>docs: minor fixes for 9.2 release notes</li>
+  <li>mesa: check for bufSize &gt; 0 in _mesa_GetSynciv()</li>
+</ul>
+
+<p>Carl Worth (3):</p>
+<ul>
+  <li>cherry-ignore: Ignore a commit which appeared twice on master</li>
+  <li>Use -Bsymbolic when linking libEGL.so</li>
+  <li>mesa: Bump version to 9.2.1</li>
+</ul>
+
+<p>Chris Forbes (3):</p>
+<ul>
+  <li>i965/fs: Gen4: Zero out extra coordinates when using shadow compare</li>
+  <li>i965: Fix cube array coordinate normalization</li>
+  <li>i965: fix bogus swizzle in brw_cubemap_normalize</li>
+</ul>
+
+<p>Christoph Bumiller (2):</p>
+<ul>
+  <li>nvc0/ir: add f32 long immediate cannot saturate</li>
+  <li>nvc0: delete compute object on screen destruction</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>st/mesa: don't dereference stObj-&gt;pt if NULL</li>
+</ul>
+
+<p>Dominik Behr (1):</p>
+<ul>
+  <li>glsl: propagate max_array_access through function calls</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>nouveau: initialise the nouveau_transfer maps</li>
+</ul>
+
+<p>Eric Anholt (4):</p>
+<ul>
+  <li>mesa: Rip out more extension checking from texformat.c.</li>
+  <li>mesa: Don't choose S3TC for generic compression if we can't compress.</li>
+  <li>i965/gen4: Fix fragment program rectangle texture shadow compares.</li>
+  <li>i965: Reenable glBitmap() after the sRGB winsys enabling.</li>
+</ul>
+
+<p>Ian Romanick (7):</p>
+<ul>
+  <li>docs: Add 9.2 release md5sums</li>
+  <li>Add .cherry-ignore file</li>
+  <li>mesa: Note that 89a665e should not be picked</li>
+  <li>glsl: Reallow precision qualifiers on structure members</li>
+  <li>mesa: Support GL_MAX_VERTEX_OUTPUT_COMPONENTS query with ES3</li>
+  <li>mesa: Remove all traces of GL_OES_matrix_get</li>
+  <li>mesa: Don't return any data for GL_SHADER_BINARY_FORMATS</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+  <li>nv30: find first unused texcoord rather than bailing if first is used</li>
+  <li>nv30: fix inconsistent setting of push-&gt;user_priv</li>
+</ul>
+
+<p>Joakim Sindholt (1):</p>
+<ul>
+  <li>nvc0: fix blitctx memory leak</li>
+</ul>
+
+<p>Johannes Obermayr (1):</p>
+<ul>
+  <li>st/gbm: Add $(WAYLAND_CFLAGS) for HAVE_EGL_PLATFORM_WAYLAND.</li>
+</ul>
+
+<p>Kenneth Graunke (5):</p>
+<ul>
+  <li>i965/vs: Detect GRF sources in split_virtual_grfs send-from-GRF code.</li>
+  <li>i965/fs: Detect GRF sources in split_virtual_grfs send-from-GRF code.</li>
+  <li>i965/vec4: Only zero out unused message components when there are any.</li>
+  <li>i965: Fix brw_vs_prog_data_compare to actually check field members.</li>
+  <li>meta: Set correct viewport and projection in decompress_texture_image.</li>
+</ul>
+
+<p>Maarten Lankhorst (2):</p>
+<ul>
+  <li>st/dri: do not create a new context for msaa copy</li>
+  <li>nvc0: restore viewport after blit</li>
+</ul>
+
+<p>Marek Olšák (2):</p>
+<ul>
+  <li>r600g: fix constant buffer cache flushing</li>
+  <li>r600g: fix texture buffer object cache flushing</li>
+</ul>
+
+<p>Paul Berry (1):</p>
+<ul>
+  <li>i965: Initialize inout_offset parameter to brw_search_cache().</li>
+</ul>
+
+<p>Rico Schüller (1):</p>
+<ul>
+  <li>glx: Initialize OpenGL version to 1.0</li>
+</ul>
+
+<p>Tiziano Bacocco (1):</p>
+<ul>
+  <li>nvc0/ir: fix use after free in texture barrier insertion pass</li>
+</ul>
+
+<p>Torsten Duwe (1):</p>
+<ul>
+  <li>wayland-egl.pc requires wayland-client.pc.</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/9.2.2.html

@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.2.2 Release Notes / (October 18, 2013)</h1>
+
+<p>
+Mesa 9.2.2 is a bug fix release which fixes bugs found since the 9.2.1 release.
+</p>
+<p>
+Mesa 9.2 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+df801a975045150790e10e2ccf32193f  MesaLib-9.2.2.tar.gz
+20887f8020db7d1736a01ae9cd5d8c38  MesaLib-9.2.2.tar.bz2
+1676f4f1b157c838d077dadd31ba6c84  MesaLib-9.2.2.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=69449">Bug 69449</a> - Valgrind error in program_resource_visitor::recursion</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=70411">Bug 70411</a> - glInvalidateFramebuffer fails with GL_INVALID_ENUM</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.2.1..mesa-9.2.2
+</pre>
+
+<p>Brian Paul (3):</p>
+<ul>
+  <li>docs: add missing &lt;pre&gt; tag</li>
+  <li>svga: fix incorrect memcpy src in svga_buffer_upload_piecewise()</li>
+  <li>mesa: consolidate cube width=height error checking</li>
+</ul>
+
+<p>Carl Worth (3):</p>
+<ul>
+  <li>docs: Add md5sums for 9.2.1 release</li>
+  <li>Bump version to 9.2.2</li>
+</ul>
+
+<p>Constantin Baranov (1):</p>
+<ul>
+  <li>mesa: Add missing switch break in invalidate_framebuffer_storage()</li>
+</ul>
+
+<p>Eric Anholt (3):</p>
+<ul>
+  <li>i965: Don't forget the cube map padding on gen5+.</li>
+  <li>mesa: Fix compiler warnings when ALIGN's alignment is "1 &lt;&lt; value".</li>
+  <li>i965: Fix 3D texture layout by more literally copying from the spec.</li>
+</ul>
+
+<p>Francisco Jerez (1):</p>
+<ul>
+  <li>glsl: Fix usage of the wrong union member in program_resource_visitor::recursion.</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>radeonsi: Use 'SI' as the LLVM processor for CIK on LLVM &lt;= 3.3</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/9.2.3.html

@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.2.3 Release Notes / (November 13, 2013)</h1>
+
+<p>
+Mesa 9.2.3 is a bug fix release which fixes bugs found since the 9.2.2 release.
+</p>
+<p>
+Mesa 9.2 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+66e9a33a414f801e1c33398bf627d56b  MesaLib-9.2.3.tar.gz
+f56b6beb556e4b9072814419f7c554e3  MesaLib-9.2.3.tar.bz2
+ed852dab576faac237ac4298bf55d0a1  MesaLib-9.2.3.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=69437">Bug 69437</a> - Composite Bypass no longer works</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.2.2..mesa-9.2.3
+</pre>
+
+<p>Brian Paul (2):</p>
+<ul>
+  <li>st/mesa: move out of memory check in st_draw_vbo()</li>
+  <li>osmesa: fix broken triangle/line drawing when using float color buffer</li>
+</ul>
+
+<p>Carl Worth (7):</p>
+<ul>
+  <li>Remove error when calling glGenQueries/glDeleteQueries while a query is active</li>
+  <li>Bump version to 9.2.3</li>
+</ul>
+
+<p>Daniel Vetter (1):</p>
+<ul>
+  <li>i965: CS writes/reads should use I915_GEM_INSTRUCTION</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>i965: Fix texture buffer rendering after a whole buffer replacement.</li>
+</ul>
+
+<p>Kenneth Graunke (6):</p>
+<ul>
+  <li>i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.</li>
+  <li>i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE.</li>
+  <li>i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.</li>
+  <li>i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.</li>
+  <li>i965: Also emit HIER_DEPTH and STENCIL packets when disabling depth.</li>
+  <li>i965: Also emit HiZ and Stencil packets when disabling depth on Gen6.</li>
+</ul>
+
+<p>Kristian Høgsberg (1):</p>
+<ul>
+  <li>wayland: Don't rely on static variable for identifying wl_drm buffers</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>radeonsi: fix blitting the last 2 mipmap levels of compressed textures</li>
+</ul>
+
+<p>Petr Sebor (1):</p>
+<ul>
+  <li>meta: enable vertex attributes in the context of the newly created array object</li>
+</ul>
+
+<p>Scott Graham (1):</p>
+<ul>
+  <li>mesa: fixes for MSVC 2013</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/9.2.4.html

@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.2.4 Release Notes / (November 27, 2013)</h1>
+
+<p>
+Mesa 9.2.4 is a bug fix release which fixes bugs found since the 9.2.3 release.
+</p>
+<p>
+Mesa 9.2 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53077">Bug 53077</a> - [IVB] Output error with msaa when both of framebuffer and source color's alpha are not 1</li>
+
+<li>Fix freedreno to compile with recent libdrm.</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.2.3..mesa-9.2.4
+</pre>
+
+<p>Brian Paul (1):</p>
+<ul>
+  <li>st/mesa: fix GL_FEEDBACK mode inverted Y coordinate bug</li>
+</ul>
+
+<p>Paul Berry (2):</p>
+<ul>
+  <li>i965: Fix vertical alignment for multisampled buffers.</li>
+  <li>glsl: Fix lowering of direct assignment in lower_clip_distance.</li>
+</ul>
+
+<p>Rob Clark (17):</p>
+<ul>
+  <li>freedreno/a3xx: fix color inversion on mem-&gt;gmem restore</li>
+  <li>freedreno/a3xx: fix viewport on gmem-&gt;mem resolve</li>
+  <li>freedreno: add debug option to disable scissor optimization</li>
+  <li>freedreno: update register headers</li>
+  <li>freedreno/a3xx: some texture fixes</li>
+  <li>freedreno/a3xx/compiler: fix CMP</li>
+  <li>freedreno/a3xx/compiler: handle saturate on dst</li>
+  <li>freedreno/a3xx/compiler: use max_reg rather than file_count</li>
+  <li>freedreno/a3xx/compiler: cat4 cannot use const reg as src</li>
+  <li>freedreno: fix segfault when no color buffer bound</li>
+  <li>freedreno/a3xx/compiler: make compiler errors more useful</li>
+  <li>freedreno/a3xx/compiler: bit of re-arrange/cleanup</li>
+  <li>freedreno/a3xx/compiler: fix SGT/SLT/etc</li>
+  <li>freedreno/a3xx: don't leak so much</li>
+  <li>freedreno/a3xx/compiler: better const handling</li>
+  <li>freedreno/a3xx/compiler: handle sync flags better</li>
+  <li>freedreno: updates for msm drm/kms driver</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>mesa: enable GL_TEXTURE_LOD_BIAS set/get</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/9.2.html

@@ -14,7 +14,7 @@
 <iframe src="../contents.html"></iframe>
 <div class="content">
 
-<h1>Mesa 9.2 Release Notes / (date TBD)</h1>
+<h1>Mesa 9.2 Release Notes / (August 27, 2013)</h1>
 
 <p>
 Mesa 9.2 is a new development release.
@@ -33,7 +33,9 @@ because GL_ARB_compatibility is not supported.
 
 <h2>MD5 checksums</h2>
 <pre>
-tbd
+4f93c6475ec656fc1f7b93aeffc9b6c4  MesaLib-9.2.0.tar.gz
+4185b6aae890bc62a964f4b24cc1aca8  MesaLib-9.2.0.tar.bz2
+3bc5339bc98b9c37777ffd14e3a8eca4  MesaLib-9.2.0.zip
 </pre>
 
 
@@ -44,21 +46,166 @@ Note: some of the new features are only available with certain drivers.
 </p>
 
 <ul>
+<li>GL_ARB_shading_language_420pack in all drivers that support GLSL 1.30.</li>
 <li>GL_ARB_texture_buffer_range</li>
 <li>GL_ARB_texture_multisample</li>
 <li>GL_ARB_texture_storage_multisample</li>
 <li>GL_ARB_texture_query_lod</li>
-<li>Enable GL_ARB_texture_storage on radeon, r200, and nouveau</li>
+<li>GL_ARB_texture_storage on radeon, r200, and nouveau</li>
+<li>GL_EXT_discard_framebuffer in all OpenGL ES (all versions) drivers</li>
+<li>GL_EXT_framebuffer_multisample_blit_scaled on i965</li>
 <li>Added new freedreno gallium driver</li>
 <li>OSMesa interface for gallium llvmpipe/softpipe drivers</li>
 <li>Gallium Heads-Up Display (HUD) feature for performance monitoring</li>
+<li>Added support for UVD (2.2 and 3.0) video decoding on r600g and radeonsi through VDPAU (requires Kernel 3.10 or later)</li>
 </ul>
 
 
 <h2>Bug fixes</h2>
 
-<p>TBD -- This list is likely incomplete.</p>
+<p>Attempts have been made to <b>not</b> include bugs fixed in previous 9.1
+releases or bugs that were regressions during 9.2 development. This list is
+likely incomplete.</p>
 
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=41787">Bug 41787</a> - [llvmpipe] stencil broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44618">Bug 44618</a> - Cross-compilation broken by glsl builtin_compiler</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=46632">Bug 46632</a> - Make the alignment checks for the readpixel blit fastpath a bit more lenient</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47116">Bug 47116</a> - Enemy territory freezes with rs880 and commit fbebd431ec4e2e461a0cbcd5f3a04a000b8f6bbf</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47248">Bug 47248</a> - autogen missing dependency on flex and bison, causes infinite loop in glsl build</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=48694">Bug 48694</a> - radeonsi_pipe.c:322:7: error: ‘PIPE_CAP_DUAL_SOURCE_BLEND’ undeclared</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=50655">Bug 50655</a> - [r600g][RV670 HD3870] Ioquake games causes GPU lockup (waiting for 0x00003039 last fence id 0x00003030)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=51471">Bug 51471</a> - [965gm] Corrupted graphics in corners of screen with pixel shaders enabled</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=51782">Bug 51782</a> - mesa-8.0.3: fails to compile against uclibc</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54240">Bug 54240</a> - [swrast] piglit fbo-generatemipmap-filtering regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=55503">Bug 55503</a> - Constant vertex attributes broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=55783">Bug 55783</a> - glEnable(GL_FRAMEBUFFER_SRGB) has no effect on the backbuffer</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=55825">Bug 55825</a> - [Bisected i965]Oglc max_values(advanced.fragmentProgram.GL_MAX_PROGRAM_ALU_INSTRUCTIONS_ARB)  causes OOM-killer</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=56920">Bug 56920</a> - [sandybridge][uxa] graphics very glitchy and always flickering</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57753">Bug 57753</a> - leak in loop_analysis</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57875">Bug 57875</a> - Second Life viewer bad rendering with git-ec83535</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58666">Bug 58666</a> - rv670 + llvm = errors.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58680">Bug 58680</a> - [IVB] Graphical glitches in 0 A.D</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58872">Bug 58872</a> - Mac OS X configure: error: Couldn't find clock_gettime</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59322">Bug 59322</a> - r300g MSAA breaks Half-Life 2 in Wine</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59364">Bug 59364</a> - [bisected] Mesa build fails: clientattrib.c:33:22: fatal error: indirect.h: No such file or directory</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59439">Bug 59439</a> - glCopyPixels generates no fragments (occlusion_query_meta_fragments test fails)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59440">Bug 59440</a> - glBitmap generates no fragments (occlusion_query_meta_fragments test fails)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59494">Bug 59494</a> - [Bisected]Piglit glean_depthStencil fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59592">Bug 59592</a> - Radeon HD 5670: reproducable GPU lockups with htile enabled</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59648">Bug 59648</a> - [SNB/IVB/HSW Bisected]Piglit spec/ARB_uniform_buffer/object_layout-std140-base-size-and-alignment fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59701">Bug 59701</a> - lp_test_arit fails on non-sse41 capable machines, breaking make check</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59737">Bug 59737</a> - [bisected] 0d108116bd80b757fb01a84a9f1946ef870b57b8 breaks osmesa when cross compiling</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59740">Bug 59740</a> - [i965 Bisected]Oglc api-error(negative.glEvalMesh) fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59851">Bug 59851</a> - AC_ARG_WITH misusage leading to mesa configure failure</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59873">Bug 59873</a> - [swrast] piglit ext_framebuffer_multisample-interpolation 0 centroid-edges regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59876">Bug 59876</a> - glGetTexLevelParameteriv broken for indirect rendering</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60038">Bug 60038</a> - [osmesa] [git] building 32-bit mesa on 64 bit fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60047">Bug 60047</a> - [softpipe] piglit masked-clear regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60052">Bug 60052</a> - [Bisected]Piglit glx_extension_string_sanity fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60082">Bug 60082</a> - [  FAILED  ] DispatchSanity_test.GL31_CORE</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60086">Bug 60086</a> - Wayland platform backend crashes if there's no back buffer during dri2_swap_buffers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60098">Bug 60098</a> - [softpipe] Unexpected PIPE_CAP 78 query</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60172">Bug 60172</a> - Planeshift: triangles where grass would be</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60200">Bug 60200</a> - radeon_bo with virtual address referencing mismatch</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60212">Bug 60212</a> - [Bisected] Weston black output</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60524">Bug 60524</a> - [softpipe] piglit depthstencil-render-miplevels 146 s=z24_s8 regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60527">Bug 60527</a> - [softpipe] fbo-stencil GL_DEPTH24_STENCIL8 clear regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60633">Bug 60633</a> - EXT_texture_sRGB does not work in game The Cave on IvyBridge</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60737">Bug 60737</a> - In GLSL ES, a missing FS precision qualifier does not generate an error</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60866">Bug 60866</a> - GLSL performance issues for uniform buffer objects</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61036">Bug 61036</a> - Shader fails to build in LLVMpipe, aborts program</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61200">Bug 61200</a> - insufficient linking of libxatracker.so</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61635">Bug 61635</a> - glVertexAttribPointer(id, GL_UNSIGNED_BYTE, GL_FALSE,...) does not work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62466">Bug 62466</a> - r600g hyperz lockups with KSP 0.19</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62669">Bug 62669</a> - HyperZ freeze when playing PrBoom-Plus demo with lots of monsters</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62721">Bug 62721</a> - GPU lockup in Minecraft 1.5.1 with HyperZ</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62830">Bug 62830</a> - [i965 bisected] Wrong Lightning on Freespace 2 SCP (patch attached)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63124">Bug 63124</a> - [r600g] HyperZ lockup on REDWOOD in Half Life 2 Deathmatch</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63702">Bug 63702</a> - tiling2d in radeon trash vdpau UVD textures</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64935">Bug 64935</a> - [swrast] s_texfetch.c:1335: set_fetch_functions: Assertion `texImage-&gt;FetchTexel' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64959">Bug 64959</a> - Cannot build against EGL without X11</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=65112">Bug 65112</a> - glcpp hangs parsing line continuations</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=65958">Bug 65958</a> - GPU Lockup on Trinity 7500G</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66450">Bug 66450</a> - JUNIPER UVD accelerated  playback of MPEG 1/2 streams does not work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66606">Bug 66606</a> - [i965 bisected]GLBenchmark 2.5.1/2.7.0 sometimes render error with gnome-session enabling SNA</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66713">Bug 66713</a> - Team Fortress 2 crashes with r600-sb on HD4850</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67354">Bug 67354</a> - glsl_parser.cpp is broken with bison 3.0</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67548">Bug 67548</a> - glGetAttribLocation seems to be broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67927">Bug 67927</a> - R600_DEBUG=sb: Celestia show 2 earths, one wrongly rendered</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67934">Bug 67934</a> - [SNB/IVB/HSW 9.2 Bisected]Ogles2conform/GL2Tests/glUniform/glUniform.test fails with gnome-session enable compositing</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68162">Bug 68162</a> - [radeonsi] texture rendering is broken in Source-Engine games</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68195">Bug 68195</a> - piglit tests vs-struct-pad and fs-struct-pad both fail</li>
+
+</ul>
 
 <h2>Changes</h2>
 
@@ -70,7 +217,8 @@ Note: some of the new features are only available with certain drivers.
 the (unsupported) GDI driver.</li>
 <li>GL_EXT_separate_shader_objects has been removed from all Gallium drivers,
     because it disallows a critical GLSL shader optimization.
-    GL_ARB_separate_shader_objects doesn't have this issue.
+    GL_ARB_separate_shader_objects doesn't have this issue.</li>
+<li>i965 Gen6+ requires Kernel 3.6 or later. (92d2f5a)</li>
 </ul>
 
 </div>

include/c99/stdbool.h

@@ -35,7 +35,8 @@
 #define bool    _Bool
 
 /* For compilers that don't have the builtin _Bool type. */
-#if defined(_MSC_VER) || (__STDC_VERSION__ < 199901L && __GNUC__ < 3)
+#if (defined(_MSC_VER) && _MSC_VER < 1800) || \
+    (defined __GNUC__&& __STDC_VERSION__ < 199901L && __GNUC__ < 3)
 typedef unsigned char _Bool;
 #endif
 

src/Makefile.am

@@ -29,6 +29,10 @@ if HAVE_DRI_GLX
 SUBDIRS += glx
 endif
 
+if HAVE_EGL_PLATFORM_WAYLAND
+SUBDIRS += egl/wayland
+endif
+
 if HAVE_GBM
 SUBDIRS += gbm
 endif

src/egl/Makefile.am

@@ -21,8 +21,4 @@
 
 SUBDIRS=
 
-if HAVE_EGL_PLATFORM_WAYLAND
-SUBDIRS += wayland
-endif
-
 SUBDIRS += drivers main

src/egl/drivers/dri2/Makefile.am

@@ -28,6 +28,7 @@ AM_CFLAGS = \
 	-I$(top_srcdir)/src/egl/wayland/wayland-drm \
 	-I$(top_builddir)/src/egl/wayland/wayland-drm \
 	$(DEFINES) \
+	$(VISIBILITY_CFLAGS) \
 	$(LIBDRM_CFLAGS) \
 	$(LIBUDEV_CFLAGS) \
 	$(LIBKMS_CFLAGS) \

src/egl/drivers/dri2/egl_dri2.c

@@ -1203,7 +1203,7 @@ dri2_create_image_wayland_wl_buffer(_EGLDisplay *disp, _EGLContext *ctx,
    EGLint err;
    int32_t plane;
 
-   if (!wayland_buffer_is_drm(&buffer->buffer))
+   if (!wayland_buffer_is_drm(dri2_dpy->wl_server_drm, &buffer->buffer))
        return NULL;
 
    err = _eglParseImageAttribList(&attrs, disp, attr_list);
@@ -1585,6 +1585,11 @@ dri2_bind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *disp,
    if (!dri2_dpy->wl_server_drm)
 	   return EGL_FALSE;
 
+#ifdef HAVE_DRM_PLATFORM
+   if (dri2_dpy->gbm_dri)
+      dri2_dpy->gbm_dri->wl_drm = dri2_dpy->wl_server_drm;
+#endif
+
    return EGL_TRUE;
 }
 
@@ -1611,9 +1616,10 @@ dri2_query_wayland_buffer_wl(_EGLDriver *drv, _EGLDisplay *disp,
                              EGLint attribute, EGLint *value)
 {
    struct wl_drm_buffer *buffer = (struct wl_drm_buffer *) _buffer;
+   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
    const struct wl_drm_components_descriptor *format;
 
-   if (!wayland_buffer_is_drm(&buffer->buffer))
+   if (!wayland_buffer_is_drm(dri2_dpy->wl_server_drm, &buffer->buffer))
       return EGL_FALSE;
 
    format = buffer->driver_format;

src/egl/drivers/dri2/platform_x11.c

@@ -743,6 +743,20 @@ dri2_swap_buffers_msc(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw,
       free(reply);
    }
 
+   /* Since we aren't watching for the server's invalidate events like we're
+    * supposed to (due to XCB providing no mechanism for filtering the events
+    * the way xlib does), and SwapBuffers is a common cause of invalidate
+    * events, just shove one down to the driver, even though we haven't told
+    * the driver that we're the kind of loader that provides reliable
+    * invalidate events.  This causes the driver to request buffers again at
+    * its next draw, so that we get the correct buffers if a pageflip
+    * happened.  The driver should still be using the viewport hack to catch
+    * window resizes.
+    */
+   if (dri2_dpy->flush &&
+       dri2_dpy->flush->base.version >= 3 && dri2_dpy->flush->invalidate)
+      (*dri2_dpy->flush->invalidate)(dri2_surf->dri_drawable);
+
    return swap_count;
 }
 

src/egl/drivers/glx/Makefile.am

@@ -22,6 +22,7 @@
 AM_CFLAGS = \
 	-I$(top_srcdir)/include \
 	-I$(top_srcdir)/src/egl/main \
+	$(VISIBILITY_CFLAGS) \
 	$(X11_CFLAGS) \
 	$(DEFINES)
 

src/egl/main/Makefile.am

@@ -29,6 +29,7 @@ AM_CFLAGS = \
 	-I$(top_srcdir)/include \
 	-I$(top_srcdir)/src/gbm/main \
 	$(DEFINES) \
+	$(VISIBILITY_CFLAGS) \
 	$(EGL_CFLAGS) \
 	-D_EGL_NATIVE_PLATFORM=$(EGL_NATIVE_PLATFORM) \
 	-D_EGL_DRIVER_SEARCH_DIR=\"$(EGL_DRIVER_INSTALL_DIR)\" \
@@ -74,7 +75,7 @@ libEGL_la_SOURCES = \
 
 libEGL_la_LIBADD = \
 	$(EGL_LIB_DEPS)
-libEGL_la_LDFLAGS = -version-number 1:0 -no-undefined
+libEGL_la_LDFLAGS = -Wl,-Bsymbolic -version-number 1:0 -no-undefined
 
 if HAVE_EGL_PLATFORM_X11
 AM_CFLAGS += -DHAVE_X11_PLATFORM

src/egl/wayland/wayland-drm/Makefile.am

@@ -1,6 +1,7 @@
 AM_CFLAGS = -I$(top_srcdir)/src/egl/main \
 	    -I$(top_srcdir)/include \
 	    $(DEFINES) \
+	    $(VISIBILITY_CFLAGS) \
 	    $(WAYLAND_CFLAGS) 
 
 noinst_LTLIBRARIES = libwayland-drm.la

src/egl/wayland/wayland-drm/wayland-drm.c

@@ -45,6 +45,7 @@ struct wl_drm {
         uint32_t flags;
 
 	struct wayland_drm_callbacks *callbacks;
+        struct wl_buffer_interface buffer_interface;
 };
 
 static void
@@ -63,10 +64,6 @@ buffer_destroy(struct wl_client *client, struct wl_resource *resource)
 	wl_resource_destroy(resource);
 }
 
-const static struct wl_buffer_interface drm_buffer_interface = {
-	buffer_destroy
-};
-
 static void
 create_buffer(struct wl_client *client, struct wl_resource *resource,
               uint32_t id, uint32_t name, int fd,
@@ -107,7 +104,7 @@ create_buffer(struct wl_client *client, struct wl_resource *resource,
 	buffer->buffer.resource.object.id = id;
 	buffer->buffer.resource.object.interface = &wl_buffer_interface;
 	buffer->buffer.resource.object.implementation =
-		(void (**)(void)) &drm_buffer_interface;
+		(void (**)(void)) &drm->buffer_interface;
 	buffer->buffer.resource.data = buffer;
 
 	buffer->buffer.resource.destroy = destroy_buffer;
@@ -246,6 +243,7 @@ wayland_drm_init(struct wl_display *display, char *device_name,
 	drm->callbacks = callbacks;
 	drm->user_data = user_data;
         drm->flags = flags;
+        drm->buffer_interface.destroy = buffer_destroy;
 
 	wl_display_add_global(display, &wl_drm_interface, drm, bind_drm);
 
@@ -263,10 +261,10 @@ wayland_drm_uninit(struct wl_drm *drm)
 }
 
 int
-wayland_buffer_is_drm(struct wl_buffer *buffer)
+wayland_buffer_is_drm(struct wl_drm *drm, struct wl_buffer *buffer)
 {
 	return buffer->resource.object.implementation == 
-		(void (**)(void)) &drm_buffer_interface;
+		(void (**)(void)) &drm->buffer_interface;
 }
 
 uint32_t

src/egl/wayland/wayland-drm/wayland-drm.h

@@ -99,7 +99,7 @@ void
 wayland_drm_uninit(struct wl_drm *drm);
 
 int
-wayland_buffer_is_drm(struct wl_buffer *buffer);
+wayland_buffer_is_drm(struct wl_drm *drm, struct wl_buffer *buffer);
 
 uint32_t
 wayland_drm_buffer_get_format(struct wl_buffer *buffer_base);

src/egl/wayland/wayland-egl/Makefile.am

@@ -2,6 +2,7 @@ pkgconfigdir = $(libdir)/pkgconfig
 pkgconfig_DATA = wayland-egl.pc
 
 AM_CFLAGS = $(DEFINES) \
+	    $(VISIBILITY_CFLAGS) \
 	    $(WAYLAND_CFLAGS)
 
 lib_LTLIBRARIES = libwayland-egl.la

src/egl/wayland/wayland-egl/wayland-egl.pc.in

@@ -6,5 +6,6 @@ includedir=@includedir@
 Name: wayland-egl
 Description: Mesa wayland-egl library
 Version: @VERSION@
+Requires: wayland-client
 Libs: -L${libdir} -lwayland-egl
 Cflags: -I${includedir}

src/gallium/auxiliary/Makefile.am

@@ -38,13 +38,17 @@ libgallium_la_SOURCES += \
 endif
 
 indices/u_indices_gen.c: $(srcdir)/indices/u_indices_gen.py
+	$(MKDIR_P) indices
 	$(AM_V_GEN) $(PYTHON2) $< > $@
 
 indices/u_unfilled_gen.c: $(srcdir)/indices/u_unfilled_gen.py
+	$(MKDIR_P) indices
 	$(AM_V_GEN) $(PYTHON2) $< > $@
 
 util/u_format_srgb.c: $(srcdir)/util/u_format_srgb.py
+	$(MKDIR_P) util
 	$(AM_V_GEN) $(PYTHON2) $< > $@
 
 util/u_format_table.c: $(srcdir)/util/u_format_table.py $(srcdir)/util/u_format_pack.py $(srcdir)/util/u_format_parse.py $(srcdir)/util/u_format.csv
+	$(MKDIR_P) util
 	$(AM_V_GEN) $(PYTHON2) $(srcdir)/util/u_format_table.py $(srcdir)/util/u_format.csv > $@

src/gallium/auxiliary/draw/draw_context.c

@@ -58,7 +58,7 @@ draw_get_option_use_llvm(void)
 
 #ifdef PIPE_ARCH_X86
       util_cpu_detect();
-      /* require SSE2 due to LLVM PR6960. */
+      /* require SSE2 due to LLVM PR6960. XXX Might be fixed by now? */
       if (!util_cpu_caps.has_sse2)
          value = FALSE;
 #endif
@@ -78,6 +78,9 @@ draw_create_context(struct pipe_context *pipe, boolean try_llvm)
    if (draw == NULL)
       goto err_out;
 
+   /* we need correct cpu caps for disabling denorms in draw_vbo() */
+   util_cpu_detect();
+
 #if HAVE_LLVM
    if (try_llvm && draw_get_option_use_llvm()) {
       draw->llvm = draw_llvm_create(draw);

src/gallium/auxiliary/os/os_process.c

@@ -32,10 +32,10 @@
 
 #if defined(PIPE_SUBSYSTEM_WINDOWS_USER)
 #  include <windows.h>
-#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
-#  include <stdlib.h>
 #elif defined(__GLIBC__)
 #  include <errno.h>
+#elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
+#  include <stdlib.h>
 #else
 #warning unexpected platform in os_process.c
 #endif
@@ -68,11 +68,11 @@ os_get_process_name(char *procname, size_t size)
 
    name = lpProcessName;
 
+#elif defined(__GLIBC__)
+   name = program_invocation_short_name;
 #elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
    /* *BSD and OS X */
    name = getprogname();
-#elif defined(__GLIBC__)
-   name = program_invocation_short_name;
 #else
 #warning unexpected platform in os_process.c
    return FALSE;

src/gallium/auxiliary/postprocess/postprocess.h

@@ -77,6 +77,14 @@ void pp_debug(const char *, ...);
 struct program *pp_init_prog(struct pp_queue_t *, struct pipe_context *pipe,
                              struct cso_context *);
 void pp_init_fbos(struct pp_queue_t *, unsigned int, unsigned int);
+void pp_blit(struct pipe_context *pipe,
+             struct pipe_resource *src_tex,
+             int srcX0, int srcY0,
+             int srcX1, int srcY1,
+             int srcZ0,
+             struct pipe_surface *dst,
+             int dstX0, int dstY0,
+             int dstX1, int dstY1);
 
 /* The filters */
 

src/gallium/auxiliary/postprocess/pp_init.c

@@ -31,7 +31,6 @@
 
 #include "pipe/p_screen.h"
 #include "util/u_inlines.h"
-#include "util/u_blit.h"
 #include "util/u_math.h"
 #include "util/u_debug.h"
 #include "util/u_memory.h"
@@ -111,13 +110,6 @@ pp_init(struct pipe_context *pipe, const unsigned int *enabled,
       }
    }
 
-   ppq->p->blitctx = util_create_blit(ppq->p->pipe, cso);
-
-   if (ppq->p->blitctx == NULL) {
-      pp_debug("Unable to create a blit context.\n");
-      goto error;
-   }
-
    ppq->n_filters = curpos;
    ppq->n_tmp = (curpos > 2 ? 2 : 1);
    ppq->n_inner_tmp = tmp_req;
@@ -180,11 +172,6 @@ pp_free(struct pp_queue_t *ppq)
    pp_free_fbos(ppq);
 
    if (ppq && ppq->p) {
-      /* Only destroy created contexts. */
-      if (ppq->p->blitctx) {
-         util_destroy_blit(ppq->p->blitctx);
-      }
-
       if (ppq->p->pipe && ppq->filters && ppq->shaders) {
          for (i = 0; i < ppq->n_filters; i++) {
             unsigned int filter = ppq->filters[i];

src/gallium/auxiliary/postprocess/pp_mlaa.c

@@ -43,7 +43,6 @@
 #include "postprocess/postprocess.h"
 #include "postprocess/pp_mlaa.h"
 #include "postprocess/pp_filters.h"
-#include "util/u_blit.h"
 #include "util/u_box.h"
 #include "util/u_sampler.h"
 #include "util/u_inlines.h"
@@ -191,10 +190,9 @@ pp_jimenezmlaa_run(struct pp_queue_t *ppq, struct pipe_resource *in,
    pp_filter_set_fb(p);
 
    /* Blit the input to the output */
-   util_blit_pixels(p->blitctx, in, 0, 0, 0,
-                    w, h, 0, p->framebuffer.cbufs[0],
-                    0, 0, w, h, 0, PIPE_TEX_MIPFILTER_NEAREST,
-                    TGSI_WRITEMASK_XYZW, 0);
+   pp_blit(p->pipe, in, 0, 0,
+           w, h, 0, p->framebuffer.cbufs[0],
+           0, 0, w, h);
 
    u_sampler_view_default_template(&v_tmp, in, in->format);
    arr[0] = p->pipe->create_sampler_view(p->pipe, in, &v_tmp);

src/gallium/auxiliary/postprocess/pp_program.h

@@ -56,8 +56,6 @@ struct program
    struct pipe_resource *vbuf;
    struct pipe_surface surf;
    struct pipe_sampler_view *view;
-
-   struct blit_state *blitctx;
 };
 
 

src/gallium/auxiliary/postprocess/pp_run.c

@@ -28,12 +28,50 @@
 #include "postprocess.h"
 
 #include "postprocess/pp_filters.h"
-#include "util/u_blit.h"
 #include "util/u_inlines.h"
 #include "util/u_sampler.h"
 
 #include "tgsi/tgsi_parse.h"
 
+void
+pp_blit(struct pipe_context *pipe,
+        struct pipe_resource *src_tex,
+        int srcX0, int srcY0,
+        int srcX1, int srcY1,
+        int srcZ0,
+        struct pipe_surface *dst,
+        int dstX0, int dstY0,
+        int dstX1, int dstY1)
+{
+   struct pipe_blit_info blit;
+
+   memset(&blit, 0, sizeof(blit));
+
+   blit.src.resource = src_tex;
+   blit.src.level = 0;
+   blit.src.format = src_tex->format;
+   blit.src.box.x = srcX0;
+   blit.src.box.y = srcY0;
+   blit.src.box.z = srcZ0;
+   blit.src.box.width = srcX1 - srcX0;
+   blit.src.box.height = srcY1 - srcY0;
+   blit.src.box.depth = 1;
+
+   blit.dst.resource = dst->texture;
+   blit.dst.level = dst->u.tex.level;
+   blit.dst.format = dst->format;
+   blit.dst.box.x = dstX0;
+   blit.dst.box.y = dstY0;
+   blit.dst.box.z = 0;
+   blit.dst.box.width = dstX1 - dstX0;
+   blit.dst.box.height = dstY1 - dstY0;
+   blit.dst.box.depth = 1;
+
+   blit.mask = PIPE_MASK_RGBA;
+
+   pipe->blit(pipe, &blit);
+}
+
 /**
 *	Main run function of the PP queue. Called on swapbuffers/flush.
 *
@@ -66,10 +104,10 @@ pp_run(struct pp_queue_t *ppq, struct pipe_resource *in,
       unsigned int w = ppq->p->framebuffer.width;
       unsigned int h = ppq->p->framebuffer.height;
 
-      util_blit_pixels(ppq->p->blitctx, in, 0, 0, 0,
-                       w, h, 0, ppq->tmps[0],
-                       0, 0, w, h, 0, PIPE_TEX_MIPFILTER_NEAREST,
-                       TGSI_WRITEMASK_XYZW, 0);
+
+      pp_blit(ppq->p->pipe, in, 0, 0,
+              w, h, 0, ppq->tmps[0],
+              0, 0, w, h);
 
       in = ppq->tmp[0];
    }
@@ -218,8 +256,8 @@ pp_tgsi_to_state(struct pipe_context *pipe, const char *text, bool isvs,
       return NULL;
    }
 
-   if (tgsi_text_translate(text, tokens, Elements(tokens)) == FALSE) {
-      pp_debug("Failed to translate %s\n", name);
+   if (tgsi_text_translate(text, tokens, PP_MAX_TOKENS) == FALSE) {
+      _debug_printf("pp: Failed to translate a shader for %s\n", name);
       return NULL;
    }
 

src/gallium/auxiliary/util/u_format_s3tc.c

@@ -111,7 +111,6 @@ util_format_s3tc_init(void)
    util_dl_proc fetch_2d_texel_rgba_dxt3;
    util_dl_proc fetch_2d_texel_rgba_dxt5;
    util_dl_proc tx_compress_dxtn;
-   char *force_s3tc_enable;
 
    if (!first_time)
       return;
@@ -122,15 +121,8 @@ util_format_s3tc_init(void)
 
    library = util_dl_open(DXTN_LIBNAME);
    if (!library) {
-      if ((force_s3tc_enable = getenv("force_s3tc_enable")) &&
-          !strcmp(force_s3tc_enable, "true")) {
-         debug_printf("couldn't open " DXTN_LIBNAME ", enabling DXTn due to "
-            "force_s3tc_enable=true environment variable\n");
-         util_format_s3tc_enabled = TRUE;
-      } else {
-         debug_printf("couldn't open " DXTN_LIBNAME ", software DXTn "
-            "compression/decompression unavailable\n");
-      }
+      debug_printf("couldn't open " DXTN_LIBNAME ", software DXTn "
+                   "compression/decompression unavailable\n");
       return;
    }
 

src/gallium/auxiliary/vl/vl_winsys_dri.c

@@ -32,8 +32,10 @@
 #include <fcntl.h>
 
 #include <X11/Xlib-xcb.h>
+#include <X11/extensions/dri2tokens.h>
 #include <xcb/dri2.h>
 #include <xf86drm.h>
+#include <errno.h>
 
 #include "pipe/p_screen.h"
 #include "pipe/p_context.h"
@@ -305,6 +307,7 @@ vl_screen_create(Display *display, int screen)
    xcb_generic_error_t *error = NULL;
    char *device_name;
    int fd, device_name_length;
+   unsigned int driverType;
 
    drm_magic_t magic;
 
@@ -332,7 +335,22 @@ vl_screen_create(Display *display, int screen)
    s = xcb_setup_roots_iterator(xcb_get_setup(scrn->conn));
    while (screen--)
 	xcb_screen_next(&s);
-   connect_cookie = xcb_dri2_connect_unchecked(scrn->conn, s.data->root, XCB_DRI2_DRIVER_TYPE_DRI);
+   driverType = XCB_DRI2_DRIVER_TYPE_DRI;
+#ifdef DRI2DriverPrimeShift
+   {
+      char *prime = getenv("DRI_PRIME");
+      if (prime) {
+         unsigned int primeid;
+         errno = 0;
+         primeid = strtoul(prime, NULL, 0);
+         if (errno == 0)
+            driverType |=
+               ((primeid & DRI2DriverPrimeMask) << DRI2DriverPrimeShift);
+      }
+   }
+#endif
+
+   connect_cookie = xcb_dri2_connect_unchecked(scrn->conn, s.data->root, driverType);
    connect = xcb_dri2_connect_reply(scrn->conn, connect_cookie, NULL);
    if (connect == NULL || connect->driver_name_length + connect->device_name_length == 0)
       goto free_screen;

src/gallium/docs/source/screen.rst

@@ -168,6 +168,8 @@ The integer capabilities:
   since they are linked) a driver can support. Returning 0 is equivalent
   to returning 1 because every driver has to support at least a single
   viewport/scissor combination.  
+* ''PIPE_CAP_ENDIANNESS``:: The endianness of the device.  Either
+  PIPE_ENDIAN_BIG or PIPE_ENDIAN_LITTLE.
 
 
 .. _pipe_capf:

src/gallium/drivers/freedreno/a2xx/a2xx.xml.h

@@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx.xml                (  30127 bytes, from 2013-05-05 18:29:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -236,56 +238,6 @@ enum sq_tex_filter {
 
 #define REG_A2XX_CP_PFP_UCODE_DATA				0x000000c1
 
-#define REG_A2XX_CP_RB_BASE					0x000001c0
-
-#define REG_A2XX_CP_RB_CNTL					0x000001c1
-
-#define REG_A2XX_CP_RB_RPTR_ADDR				0x000001c3
-
-#define REG_A2XX_CP_RB_RPTR					0x000001c4
-
-#define REG_A2XX_CP_RB_WPTR					0x000001c5
-
-#define REG_A2XX_CP_RB_WPTR_DELAY				0x000001c6
-
-#define REG_A2XX_CP_RB_RPTR_WR					0x000001c7
-
-#define REG_A2XX_CP_RB_WPTR_BASE				0x000001c8
-
-#define REG_A2XX_CP_QUEUE_THRESHOLDS				0x000001d5
-
-#define REG_A2XX_SCRATCH_UMSK					0x000001dc
-
-#define REG_A2XX_SCRATCH_ADDR					0x000001dd
-
-#define REG_A2XX_CP_STATE_DEBUG_INDEX				0x000001ec
-
-#define REG_A2XX_CP_STATE_DEBUG_DATA				0x000001ed
-
-#define REG_A2XX_CP_INT_CNTL					0x000001f2
-
-#define REG_A2XX_CP_INT_STATUS					0x000001f3
-
-#define REG_A2XX_CP_INT_ACK					0x000001f4
-
-#define REG_A2XX_CP_ME_CNTL					0x000001f6
-
-#define REG_A2XX_CP_ME_STATUS					0x000001f7
-
-#define REG_A2XX_CP_ME_RAM_WADDR				0x000001f8
-
-#define REG_A2XX_CP_ME_RAM_RADDR				0x000001f9
-
-#define REG_A2XX_CP_ME_RAM_DATA					0x000001fa
-
-#define REG_A2XX_CP_DEBUG					0x000001fc
-
-#define REG_A2XX_CP_CSQ_RB_STAT					0x000001fd
-
-#define REG_A2XX_CP_CSQ_IB1_STAT				0x000001fe
-
-#define REG_A2XX_CP_CSQ_IB2_STAT				0x000001ff
-
 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT			0x00000395
 
 #define REG_A2XX_RBBM_PERFCOUNTER1_LO				0x00000397
@@ -338,11 +290,32 @@ enum sq_tex_filter {
 
 #define REG_A2XX_CP_STAT					0x0000047f
 
-#define REG_A2XX_SCRATCH_REG0					0x00000578
-
-#define REG_A2XX_SCRATCH_REG2					0x0000057a
-
 #define REG_A2XX_RBBM_STATUS					0x000005d0
+#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK			0x0000001f
+#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT			0
+static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
+{
+	return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
+}
+#define A2XX_RBBM_STATUS_TC_BUSY				0x00000020
+#define A2XX_RBBM_STATUS_HIRQ_PENDING				0x00000100
+#define A2XX_RBBM_STATUS_CPRQ_PENDING				0x00000200
+#define A2XX_RBBM_STATUS_CFRQ_PENDING				0x00000400
+#define A2XX_RBBM_STATUS_PFRQ_PENDING				0x00000800
+#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA			0x00001000
+#define A2XX_RBBM_STATUS_RBBM_WU_BUSY				0x00004000
+#define A2XX_RBBM_STATUS_CP_NRT_BUSY				0x00010000
+#define A2XX_RBBM_STATUS_MH_BUSY				0x00040000
+#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY			0x00080000
+#define A2XX_RBBM_STATUS_SX_BUSY				0x00200000
+#define A2XX_RBBM_STATUS_TPC_BUSY				0x00400000
+#define A2XX_RBBM_STATUS_SC_CNTX_BUSY				0x01000000
+#define A2XX_RBBM_STATUS_PA_BUSY				0x02000000
+#define A2XX_RBBM_STATUS_VGT_BUSY				0x04000000
+#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY				0x08000000
+#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY				0x10000000
+#define A2XX_RBBM_STATUS_RB_CNTX_BUSY				0x40000000
+#define A2XX_RBBM_STATUS_GUI_ACTIVE				0x80000000
 
 #define REG_A2XX_A220_VSC_BIN_SIZE				0x00000c01
 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK			0x0000001f
@@ -358,13 +331,13 @@ static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
 }
 
-#define REG_A2XX_VSC_PIPE(i0)				       (0x00000c06 + 0x3*(i0))
+static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 
-#define REG_A2XX_VSC_PIPE_CONFIG(i0)			       (0x00000c06 + 0x3*(i0))
+static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 
-#define REG_A2XX_VSC_PIPE_DATA_ADDRESS(i0)		       (0x00000c07 + 0x3*(i0))
+static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
 
-#define REG_A2XX_VSC_PIPE_DATA_LENGTH(i0)		       (0x00000c08 + 0x3*(i0))
+static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
 
 #define REG_A2XX_PC_DEBUG_CNTL					0x00000c38
 

src/gallium/drivers/freedreno/a2xx/fd2_emit.c

@@ -137,7 +137,7 @@ emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
 	OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
 
 	OUT_RING(ring, sampler->tex0 | view->tex0);
-	OUT_RELOC(ring, view->tex_resource->bo, 0, view->fmt);
+	OUT_RELOC(ring, view->tex_resource->bo, 0, view->fmt, 0);
 	OUT_RING(ring, view->tex2);
 	OUT_RING(ring, sampler->tex3 | view->tex3);
 	OUT_RING(ring, sampler->tex4);
@@ -171,7 +171,7 @@ fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val,
 	OUT_RING(ring, (0x1 << 16) | (val & 0xffff));
 	for (i = 0; i < n; i++) {
 		struct fd_resource *rsc = fd_resource(vbufs[i].prsc);
-		OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3);
+		OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0);
 		OUT_RING (ring, vbufs[i].size);
 	}
 }

src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

@@ -70,7 +70,7 @@ emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t base,
 	OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 	OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 	OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
-	OUT_RELOC(ring, rsc->bo, 0, 0);         /* RB_COPY_DEST_BASE */
+	OUT_RELOCW(ring, rsc->bo, 0, 0, 0);     /* RB_COPY_DEST_BASE */
 	OUT_RING(ring, rsc->pitch >> 5);        /* RB_COPY_DEST_PITCH */
 	OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
 			A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
@@ -199,7 +199,7 @@ emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t base,
 			A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
 			A2XX_SQ_TEX_0_PITCH(rsc->pitch));
 	OUT_RELOC(ring, rsc->bo, 0,
-			fd2_pipe2surface(psurf->format) | 0x800);
+			fd2_pipe2surface(psurf->format) | 0x800, 0);
 	OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
 			A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
 	OUT_RING(ring, 0x01000000 | // XXX
@@ -241,7 +241,7 @@ fd2_emit_tile_mem2gmem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 	y0 = ((float)yoff) / ((float)pfb->height);
 	y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 	OUT_PKT3(ring, CP_MEM_WRITE, 9);
-	OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0);
+	OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
 	OUT_RING(ring, fui(x0));
 	OUT_RING(ring, fui(y0));
 	OUT_RING(ring, fui(x1));
@@ -337,7 +337,7 @@ fd2_emit_tile_init(struct fd_context *ctx)
 	struct fd_ringbuffer *ring = ctx->ring;
 	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	enum pipe_format format = pfb->cbufs[0]->format;
+	enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 	uint32_t reg;
 
 	OUT_PKT3(ring, CP_SET_CONSTANT, 4);
@@ -358,7 +358,7 @@ fd2_emit_tile_prep(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 {
 	struct fd_ringbuffer *ring = ctx->ring;
 	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	enum pipe_format format = pfb->cbufs[0]->format;
+	enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 
 	OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 	OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
@@ -379,7 +379,7 @@ fd2_emit_tile_renderprep(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 {
 	struct fd_ringbuffer *ring = ctx->ring;
 	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	enum pipe_format format = pfb->cbufs[0]->format;
+	enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 
 	OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 	OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));

src/gallium/drivers/freedreno/a3xx/a3xx.xml.h

@@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml                (  42578 bytes, from 2013-06-02 13:10:46)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -130,6 +132,13 @@ enum a3xx_tex_fmt {
 	TFMT_NORM_USHORT_5551 = 6,
 	TFMT_NORM_USHORT_4444 = 7,
 	TFMT_NORM_UINT_X8Z24 = 10,
+	TFMT_NORM_UINT_NV12_UV_TILED = 17,
+	TFMT_NORM_UINT_NV12_Y_TILED = 19,
+	TFMT_NORM_UINT_NV12_UV = 21,
+	TFMT_NORM_UINT_NV12_Y = 23,
+	TFMT_NORM_UINT_I420_Y = 24,
+	TFMT_NORM_UINT_I420_U = 26,
+	TFMT_NORM_UINT_I420_V = 27,
 	TFMT_NORM_UINT_2_10_10_10 = 41,
 	TFMT_NORM_UINT_A8 = 44,
 	TFMT_NORM_UINT_L8_A8 = 47,
@@ -207,6 +216,37 @@ enum a3xx_tex_swiz {
 	A3XX_TEX_ONE = 5,
 };
 
+enum a3xx_tex_type {
+	A3XX_TEX_1D = 0,
+	A3XX_TEX_2D = 1,
+	A3XX_TEX_CUBE = 2,
+	A3XX_TEX_3D = 3,
+};
+
+#define A3XX_INT0_RBBM_GPU_IDLE					0x00000001
+#define A3XX_INT0_RBBM_AHB_ERROR				0x00000002
+#define A3XX_INT0_RBBM_REG_TIMEOUT				0x00000004
+#define A3XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
+#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
+#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00000020
+#define A3XX_INT0_VFD_ERROR					0x00000040
+#define A3XX_INT0_CP_SW_INT					0x00000080
+#define A3XX_INT0_CP_T0_PACKET_IN_IB				0x00000100
+#define A3XX_INT0_CP_OPCODE_ERROR				0x00000200
+#define A3XX_INT0_CP_RESERVED_BIT_ERROR				0x00000400
+#define A3XX_INT0_CP_HW_FAULT					0x00000800
+#define A3XX_INT0_CP_DMA					0x00001000
+#define A3XX_INT0_CP_IB2_INT					0x00002000
+#define A3XX_INT0_CP_IB1_INT					0x00004000
+#define A3XX_INT0_CP_RB_INT					0x00008000
+#define A3XX_INT0_CP_REG_PROTECT_FAULT				0x00010000
+#define A3XX_INT0_CP_RB_DONE_TS					0x00020000
+#define A3XX_INT0_CP_VS_DONE_TS					0x00040000
+#define A3XX_INT0_CP_PS_DONE_TS					0x00080000
+#define A3XX_INT0_CACHE_FLUSH_TS				0x00100000
+#define A3XX_INT0_CP_AHB_ERROR_HALT				0x00200000
+#define A3XX_INT0_MISC_HANG_DETECT				0x01000000
+#define A3XX_INT0_UCHE_OOB_ACCESS				0x02000000
 #define REG_A3XX_RBBM_HW_VERSION				0x00000000
 
 #define REG_A3XX_RBBM_HW_RELEASE				0x00000001
@@ -230,6 +270,27 @@ enum a3xx_tex_swiz {
 #define REG_A3XX_RBBM_GPR0_CTL					0x0000002e
 
 #define REG_A3XX_RBBM_STATUS					0x00000030
+#define A3XX_RBBM_STATUS_HI_BUSY				0x00000001
+#define A3XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
+#define A3XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
+#define A3XX_RBBM_STATUS_CP_NRT_BUSY				0x00004000
+#define A3XX_RBBM_STATUS_VBIF_BUSY				0x00008000
+#define A3XX_RBBM_STATUS_TSE_BUSY				0x00010000
+#define A3XX_RBBM_STATUS_RAS_BUSY				0x00020000
+#define A3XX_RBBM_STATUS_RB_BUSY				0x00040000
+#define A3XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
+#define A3XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
+#define A3XX_RBBM_STATUS_VFD_BUSY				0x00200000
+#define A3XX_RBBM_STATUS_VPC_BUSY				0x00400000
+#define A3XX_RBBM_STATUS_UCHE_BUSY				0x00800000
+#define A3XX_RBBM_STATUS_SP_BUSY				0x01000000
+#define A3XX_RBBM_STATUS_TPL1_BUSY				0x02000000
+#define A3XX_RBBM_STATUS_MARB_BUSY				0x04000000
+#define A3XX_RBBM_STATUS_VSC_BUSY				0x08000000
+#define A3XX_RBBM_STATUS_ARB_BUSY				0x10000000
+#define A3XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
+#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC				0x40000000
+#define A3XX_RBBM_STATUS_GPU_BUSY				0x80000000
 
 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL			0x00000033
 
@@ -251,20 +312,202 @@ enum a3xx_tex_swiz {
 
 #define REG_A3XX_RBBM_PERFCTR_CTL				0x00000080
 
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0				0x00000081
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1				0x00000082
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000084
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000085
+
+#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT			0x00000086
+
+#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT			0x00000087
+
 #define REG_A3XX_RBBM_GPU_BUSY_MASKED				0x00000088
 
+#define REG_A3XX_RBBM_PERFCTR_CP_0_LO				0x00000090
+
+#define REG_A3XX_RBBM_PERFCTR_CP_0_HI				0x00000091
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO				0x00000092
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI				0x00000093
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO				0x00000094
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI				0x00000095
+
+#define REG_A3XX_RBBM_PERFCTR_PC_0_LO				0x00000096
+
+#define REG_A3XX_RBBM_PERFCTR_PC_0_HI				0x00000097
+
+#define REG_A3XX_RBBM_PERFCTR_PC_1_LO				0x00000098
+
+#define REG_A3XX_RBBM_PERFCTR_PC_1_HI				0x00000099
+
+#define REG_A3XX_RBBM_PERFCTR_PC_2_LO				0x0000009a
+
+#define REG_A3XX_RBBM_PERFCTR_PC_2_HI				0x0000009b
+
+#define REG_A3XX_RBBM_PERFCTR_PC_3_LO				0x0000009c
+
+#define REG_A3XX_RBBM_PERFCTR_PC_3_HI				0x0000009d
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO				0x0000009e
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI				0x0000009f
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO				0x000000a0
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI				0x000000a1
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO				0x000000a2
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI				0x000000a3
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO				0x000000a4
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI				0x000000a5
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO				0x000000a6
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI				0x000000a7
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO				0x000000a8
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI				0x000000a9
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO				0x000000aa
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI				0x000000ab
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO				0x000000ac
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI				0x000000ad
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO				0x000000ae
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI				0x000000af
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO				0x000000b0
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI				0x000000b1
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO				0x000000b2
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI				0x000000b3
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO				0x000000b4
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI				0x000000b5
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO				0x000000b6
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI				0x000000b7
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO				0x000000b8
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI				0x000000b9
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO				0x000000ba
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI				0x000000bb
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO				0x000000bc
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI				0x000000bd
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO				0x000000be
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI				0x000000bf
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO				0x000000c0
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI				0x000000c1
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO				0x000000c2
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI				0x000000c3
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO				0x000000c4
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI				0x000000c5
+
+#define REG_A3XX_RBBM_PERFCTR_TP_0_LO				0x000000c6
+
+#define REG_A3XX_RBBM_PERFCTR_TP_0_HI				0x000000c7
+
+#define REG_A3XX_RBBM_PERFCTR_TP_1_LO				0x000000c8
+
+#define REG_A3XX_RBBM_PERFCTR_TP_1_HI				0x000000c9
+
+#define REG_A3XX_RBBM_PERFCTR_TP_2_LO				0x000000ca
+
+#define REG_A3XX_RBBM_PERFCTR_TP_2_HI				0x000000cb
+
+#define REG_A3XX_RBBM_PERFCTR_TP_3_LO				0x000000cc
+
+#define REG_A3XX_RBBM_PERFCTR_TP_3_HI				0x000000cd
+
+#define REG_A3XX_RBBM_PERFCTR_TP_4_LO				0x000000ce
+
+#define REG_A3XX_RBBM_PERFCTR_TP_4_HI				0x000000cf
+
+#define REG_A3XX_RBBM_PERFCTR_TP_5_LO				0x000000d0
+
+#define REG_A3XX_RBBM_PERFCTR_TP_5_HI				0x000000d1
+
+#define REG_A3XX_RBBM_PERFCTR_SP_0_LO				0x000000d2
+
+#define REG_A3XX_RBBM_PERFCTR_SP_0_HI				0x000000d3
+
+#define REG_A3XX_RBBM_PERFCTR_SP_1_LO				0x000000d4
+
+#define REG_A3XX_RBBM_PERFCTR_SP_1_HI				0x000000d5
+
+#define REG_A3XX_RBBM_PERFCTR_SP_2_LO				0x000000d6
+
+#define REG_A3XX_RBBM_PERFCTR_SP_2_HI				0x000000d7
+
+#define REG_A3XX_RBBM_PERFCTR_SP_3_LO				0x000000d8
+
+#define REG_A3XX_RBBM_PERFCTR_SP_3_HI				0x000000d9
+
+#define REG_A3XX_RBBM_PERFCTR_SP_4_LO				0x000000da
+
+#define REG_A3XX_RBBM_PERFCTR_SP_4_HI				0x000000db
+
+#define REG_A3XX_RBBM_PERFCTR_SP_5_LO				0x000000dc
+
+#define REG_A3XX_RBBM_PERFCTR_SP_5_HI				0x000000dd
+
+#define REG_A3XX_RBBM_PERFCTR_SP_6_LO				0x000000de
+
+#define REG_A3XX_RBBM_PERFCTR_SP_6_HI				0x000000df
+
 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO				0x000000e0
 
 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI				0x000000e1
 
+#define REG_A3XX_RBBM_PERFCTR_RB_0_LO				0x000000e2
+
+#define REG_A3XX_RBBM_PERFCTR_RB_0_HI				0x000000e3
+
+#define REG_A3XX_RBBM_PERFCTR_RB_1_LO				0x000000e4
+
+#define REG_A3XX_RBBM_PERFCTR_RB_1_HI				0x000000e5
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO				0x000000ea
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI				0x000000eb
+
 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO				0x000000ec
 
 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI				0x000000ed
 
 #define REG_A3XX_RBBM_RBBM_CTL					0x00000100
 
-#define REG_A3XX_RBBM_RBBM_CTL					0x00000100
-
 #define REG_A3XX_RBBM_DEBUG_BUS_CTL				0x00000111
 
 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS			0x00000112
@@ -287,22 +530,20 @@ enum a3xx_tex_swiz {
 
 #define REG_A3XX_CP_MEQ_DATA					0x000001db
 
+#define REG_A3XX_CP_PERFCOUNTER_SELECT				0x00000445
+
 #define REG_A3XX_CP_HW_FAULT					0x0000045c
 
 #define REG_A3XX_CP_PROTECT_CTRL				0x0000045e
 
 #define REG_A3XX_CP_PROTECT_STATUS				0x0000045f
 
-#define REG_A3XX_CP_PROTECT(i0)				       (0x00000460 + 0x1*(i0))
+static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 
-#define REG_A3XX_CP_PROTECT_REG(i0)			       (0x00000460 + 0x1*(i0))
+static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 
 #define REG_A3XX_CP_AHB_FAULT					0x0000054d
 
-#define REG_A3XX_CP_SCRATCH_REG2				0x0000057a
-
-#define REG_A3XX_CP_SCRATCH_REG3				0x0000057b
-
 #define REG_A3XX_GRAS_CL_CLIP_CNTL				0x00002040
 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER			0x00001000
 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
@@ -528,9 +769,9 @@ static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
 
 #define REG_A3XX_UNKNOWN_20C3					0x000020c3
 
-#define REG_A3XX_RB_MRT(i0)				       (0x000020c4 + 0x4*(i0))
+static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
 
-#define REG_A3XX_RB_MRT_CONTROL(i0)			       (0x000020c4 + 0x4*(i0))
+static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
 #define A3XX_RB_MRT_CONTROL_BLEND				0x00000010
 #define A3XX_RB_MRT_CONTROL_BLEND2				0x00000020
@@ -553,7 +794,7 @@ static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
 	return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
 }
 
-#define REG_A3XX_RB_MRT_BUF_INFO(i0)			       (0x000020c5 + 0x4*(i0))
+static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x0000003f
 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
@@ -579,7 +820,7 @@ static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
 	return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
 }
 
-#define REG_A3XX_RB_MRT_BUF_BASE(i0)			       (0x000020c6 + 0x4*(i0))
+static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK		0xfffffff0
 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT		4
 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
@@ -587,7 +828,7 @@ static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
 	return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
 }
 
-#define REG_A3XX_RB_MRT_BLEND_CONTROL(i0)		       (0x000020c7 + 0x4*(i0))
+static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
@@ -627,12 +868,60 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE			0x20000000
 
 #define REG_A3XX_RB_BLEND_RED					0x000020e4
+#define A3XX_RB_BLEND_RED_UINT__MASK				0x000000ff
+#define A3XX_RB_BLEND_RED_UINT__SHIFT				0
+static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
+{
+	return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
+}
+#define A3XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
+#define A3XX_RB_BLEND_RED_FLOAT__SHIFT				16
+static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
+{
+	return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
+}
 
 #define REG_A3XX_RB_BLEND_GREEN					0x000020e5
+#define A3XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
+#define A3XX_RB_BLEND_GREEN_UINT__SHIFT				0
+static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
+{
+	return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
+}
+#define A3XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
+#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT			16
+static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
+{
+	return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
+}
 
 #define REG_A3XX_RB_BLEND_BLUE					0x000020e6
+#define A3XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
+#define A3XX_RB_BLEND_BLUE_UINT__SHIFT				0
+static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
+{
+	return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
+}
+#define A3XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
+#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT				16
+static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
+{
+	return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
+}
 
 #define REG_A3XX_RB_BLEND_ALPHA					0x000020e7
+#define A3XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
+#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT				0
+static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
+{
+	return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
+}
+#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
+#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16
+static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
+{
+	return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
+}
 
 #define REG_A3XX_UNKNOWN_20E8					0x000020e8
 
@@ -1063,9 +1352,9 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
 
 #define REG_A3XX_VFD_INDEX_OFFSET				0x00002245
 
-#define REG_A3XX_VFD_FETCH(i0)				       (0x00002246 + 0x2*(i0))
+static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
 
-#define REG_A3XX_VFD_FETCH_INSTR_0(i0)			       (0x00002246 + 0x2*(i0))
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT			0
 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
@@ -1092,11 +1381,11 @@ static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
 	return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
 }
 
-#define REG_A3XX_VFD_FETCH_INSTR_1(i0)			       (0x00002247 + 0x2*(i0))
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
 
-#define REG_A3XX_VFD_DECODE(i0)				       (0x00002266 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
 
-#define REG_A3XX_VFD_DECODE_INSTR(i0)			       (0x00002266 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT			0
 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
@@ -1173,13 +1462,13 @@ static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
 	return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
 }
 
-#define REG_A3XX_VPC_VARYING_INTERP(i0)			       (0x00002282 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
 
-#define REG_A3XX_VPC_VARYING_INTERP_MODE(i0)		       (0x00002282 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
 
-#define REG_A3XX_VPC_VARYING_PS_REPL(i0)		       (0x00002286 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
 
-#define REG_A3XX_VPC_VARYING_PS_REPL_MODE(i0)		       (0x00002286 + 0x1*(i0))
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
 
 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0			0x0000228a
 
@@ -1293,9 +1582,9 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
 	return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
 }
 
-#define REG_A3XX_SP_VS_OUT(i0)				       (0x000022c7 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
 
-#define REG_A3XX_SP_VS_OUT_REG(i0)			       (0x000022c7 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK			0x000001ff
 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
@@ -1321,9 +1610,9 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
 	return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
 }
 
-#define REG_A3XX_SP_VS_VPC_DST(i0)			       (0x000022d0 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
 
-#define REG_A3XX_SP_VS_VPC_DST_REG(i0)			       (0x000022d0 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
@@ -1480,9 +1769,9 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 
 #define REG_A3XX_SP_FS_OUTPUT_REG				0x000022ec
 
-#define REG_A3XX_SP_FS_MRT(i0)				       (0x000022f0 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
 
-#define REG_A3XX_SP_FS_MRT_REG(i0)			       (0x000022f0 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
 #define A3XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT				0
 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
@@ -1491,9 +1780,9 @@ static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
 }
 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION			0x00000100
 
-#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0)			       (0x000022f4 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
 
-#define REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i0)		       (0x000022f4 + 0x1*(i0))
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK		0x0000003f
 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT		0
 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
@@ -1607,9 +1896,9 @@ static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 
 #define REG_A3XX_VSC_SIZE_ADDRESS				0x00000c02
 
-#define REG_A3XX_VSC_PIPE(i0)				       (0x00000c06 + 0x3*(i0))
+static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 
-#define REG_A3XX_VSC_PIPE_CONFIG(i0)			       (0x00000c06 + 0x3*(i0))
+static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 #define A3XX_VSC_PIPE_CONFIG_X__MASK				0x000003ff
 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT				0
 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
@@ -1635,26 +1924,46 @@ static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
 	return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
 }
 
-#define REG_A3XX_VSC_PIPE_DATA_ADDRESS(i0)		       (0x00000c07 + 0x3*(i0))
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
 
-#define REG_A3XX_VSC_PIPE_DATA_LENGTH(i0)		       (0x00000c08 + 0x3*(i0))
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
 
 #define REG_A3XX_UNKNOWN_0C3D					0x00000c3d
 
+#define REG_A3XX_PC_PERFCOUNTER0_SELECT				0x00000c48
+
+#define REG_A3XX_PC_PERFCOUNTER1_SELECT				0x00000c49
+
+#define REG_A3XX_PC_PERFCOUNTER2_SELECT				0x00000c4a
+
+#define REG_A3XX_PC_PERFCOUNTER3_SELECT				0x00000c4b
+
 #define REG_A3XX_UNKNOWN_0C81					0x00000c81
 
-#define REG_A3XX_GRAS_CL_USER_PLANE(i0)			       (0x00000ca0 + 0x4*(i0))
+#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT			0x00000c88
 
-#define REG_A3XX_GRAS_CL_USER_PLANE_X(i0)		       (0x00000ca0 + 0x4*(i0))
+#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT			0x00000c89
 
-#define REG_A3XX_GRAS_CL_USER_PLANE_Y(i0)		       (0x00000ca1 + 0x4*(i0))
+#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT			0x00000c8a
 
-#define REG_A3XX_GRAS_CL_USER_PLANE_Z(i0)		       (0x00000ca2 + 0x4*(i0))
+#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT			0x00000c8b
 
-#define REG_A3XX_GRAS_CL_USER_PLANE_W(i0)		       (0x00000ca3 + 0x4*(i0))
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
 
 #define REG_A3XX_RB_GMEM_BASE_ADDR				0x00000cc0
 
+#define REG_A3XX_RB_PERFCOUNTER0_SELECT				0x00000cc6
+
+#define REG_A3XX_RB_PERFCOUNTER1_SELECT				0x00000cc7
+
 #define REG_A3XX_RB_WINDOW_SIZE					0x00000ce0
 #define A3XX_RB_WINDOW_SIZE_WIDTH__MASK				0x00003fff
 #define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT			0
@@ -1669,18 +1978,46 @@ static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val)
 	return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK;
 }
 
-#define REG_A3XX_UNKNOWN_0E00					0x00000e00
+#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT			0x00000e00
+
+#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT			0x00000e01
+
+#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT			0x00000e02
+
+#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT			0x00000e03
+
+#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT			0x00000e04
+
+#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT			0x00000e05
 
 #define REG_A3XX_UNKNOWN_0E43					0x00000e43
 
 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT			0x00000e44
 
+#define REG_A3XX_VFD_PERFCOUNTER1_SELECT			0x00000e45
+
 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL				0x00000e61
 
 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ				0x00000e62
 
+#define REG_A3XX_VPC_PERFCOUNTER0_SELECT			0x00000e64
+
+#define REG_A3XX_VPC_PERFCOUNTER1_SELECT			0x00000e65
+
 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG			0x00000e82
 
+#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT			0x00000e84
+
+#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT			0x00000e85
+
+#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT			0x00000e86
+
+#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT			0x00000e87
+
+#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT			0x00000e88
+
+#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT			0x00000e89
+
 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG			0x00000ea0
 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK		0x0fffffff
 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT		0
@@ -1724,6 +2061,18 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
 
 #define REG_A3XX_UNKNOWN_0F03					0x00000f03
 
+#define REG_A3XX_TP_PERFCOUNTER0_SELECT				0x00000f04
+
+#define REG_A3XX_TP_PERFCOUNTER1_SELECT				0x00000f05
+
+#define REG_A3XX_TP_PERFCOUNTER2_SELECT				0x00000f06
+
+#define REG_A3XX_TP_PERFCOUNTER3_SELECT				0x00000f07
+
+#define REG_A3XX_TP_PERFCOUNTER4_SELECT				0x00000f08
+
+#define REG_A3XX_TP_PERFCOUNTER5_SELECT				0x00000f09
+
 #define REG_A3XX_TEX_SAMP_0					0x00000000
 #define A3XX_TEX_SAMP_0_XY_MAG__MASK				0x0000000c
 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT				2
@@ -1791,6 +2140,12 @@ static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
 {
 	return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
 }
+#define A3XX_TEX_CONST_0_TYPE__MASK				0xc0000000
+#define A3XX_TEX_CONST_0_TYPE__SHIFT				30
+static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
+{
+	return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
+}
 
 #define REG_A3XX_TEX_CONST_1					0x00000001
 #define A3XX_TEX_CONST_1_HEIGHT__MASK				0x00003fff

src/gallium/drivers/freedreno/a3xx/fd3_compiler.c

@@ -62,10 +62,16 @@ static unsigned regmask_idx(struct ir3_register *reg)
 	return num;
 }
 
-static void regmask_set(regmask_t regmask, struct ir3_register *reg)
+static void regmask_set(regmask_t regmask, struct ir3_register *reg,
+		unsigned wrmask)
 {
-	unsigned idx = regmask_idx(reg);
-	regmask[idx / 8] |= 1 << (idx % 8);
+	unsigned i;
+	for (i = 0; i < 4; i++) {
+		if (wrmask & (1 << i)) {
+			unsigned idx = regmask_idx(reg) + i;
+			regmask[idx / 8] |= 1 << (idx % 8);
+		}
+	}
 }
 
 static unsigned regmask_get(regmask_t regmask, struct ir3_register *reg)
@@ -91,6 +97,7 @@ struct fd3_compile_context {
 
 	unsigned next_inloc;
 	unsigned num_internal_temps;
+	struct tgsi_src_register internal_temps[6];
 
 	/* track registers which need to synchronize w/ "complex alu" cat3
 	 * instruction pipeline:
@@ -128,9 +135,16 @@ struct fd3_compile_context {
 	 * up the vector operation
 	 */
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 };
 
+
+static void vectorize(struct fd3_compile_context *ctx,
+		struct ir3_instruction *instr, struct tgsi_dst_register *dst,
+		int nsrcs, ...);
+static void create_mov(struct fd3_compile_context *ctx,
+		struct tgsi_dst_register *dst, struct tgsi_src_register *src);
+
 static unsigned
 compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
 		const struct tgsi_token *tokens)
@@ -154,19 +168,19 @@ compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
 	/* Immediates go after constants: */
 	ctx->base_reg[TGSI_FILE_CONSTANT]  = 0;
 	ctx->base_reg[TGSI_FILE_IMMEDIATE] =
-			ctx->info.file_count[TGSI_FILE_CONSTANT];
+			ctx->info.file_max[TGSI_FILE_CONSTANT] + 1;
 
 	/* Temporaries after outputs after inputs: */
 	ctx->base_reg[TGSI_FILE_INPUT]     = 0;
 	ctx->base_reg[TGSI_FILE_OUTPUT]    =
-			ctx->info.file_count[TGSI_FILE_INPUT];
+			ctx->info.file_max[TGSI_FILE_INPUT] + 1;
 	ctx->base_reg[TGSI_FILE_TEMPORARY] =
-			ctx->info.file_count[TGSI_FILE_INPUT] +
-			ctx->info.file_count[TGSI_FILE_OUTPUT];
+			ctx->info.file_max[TGSI_FILE_INPUT] + 1 +
+			ctx->info.file_max[TGSI_FILE_OUTPUT] + 1;
 
 	so->first_immediate = ctx->base_reg[TGSI_FILE_IMMEDIATE];
-	ctx->immediate_idx = 4 * (ctx->info.file_count[TGSI_FILE_CONSTANT] +
-			ctx->info.file_count[TGSI_FILE_IMMEDIATE]);
+	ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_CONSTANT] + 1 +
+			ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
 
 	ret = tgsi_parse_init(&ctx->parser, tokens);
 	if (ret != TGSI_PARSE_OK)
@@ -177,6 +191,21 @@ compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
 	return ret;
 }
 
+static void
+compile_error(struct fd3_compile_context *ctx, const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	_debug_vprintf(format, ap);
+	va_end(ap);
+	tgsi_dump(ctx->tokens, 0);
+	assert(0);
+}
+
+#define compile_assert(ctx, cond) do { \
+		if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
+	} while (0)
+
 static void
 compile_free(struct fd3_compile_context *ctx)
 {
@@ -193,6 +222,24 @@ struct instr_translater {
 	unsigned arg;
 };
 
+static unsigned
+src_flags(struct fd3_compile_context *ctx, struct ir3_register *reg)
+{
+	unsigned flags = 0;
+
+	if (regmask_get(ctx->needs_ss, reg)) {
+		flags |= IR3_INSTR_SS;
+		memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
+	}
+
+	if (regmask_get(ctx->needs_sy, reg)) {
+		flags |= IR3_INSTR_SY;
+		memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
+	}
+
+	return flags;
+}
+
 static struct ir3_register *
 add_dst_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 		const struct tgsi_dst_register *dst, unsigned chan)
@@ -205,9 +252,8 @@ add_dst_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 		num = dst->Index + ctx->base_reg[dst->File];
 		break;
 	default:
-		DBG("unsupported dst register file: %s",
+		compile_error(ctx, "unsupported dst register file: %s\n",
 			tgsi_file_name(dst->File));
-		assert(0);
 		break;
 	}
 
@@ -234,14 +280,17 @@ add_src_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 		flags |= IR3_REG_CONST;
 		num = src->Index + ctx->base_reg[src->File];
 		break;
+	case TGSI_FILE_OUTPUT:
+		/* NOTE: we should only end up w/ OUTPUT file for things like
+		 * clamp()'ing saturated dst instructions
+		 */
 	case TGSI_FILE_INPUT:
 	case TGSI_FILE_TEMPORARY:
 		num = src->Index + ctx->base_reg[src->File];
 		break;
 	default:
-		DBG("unsupported src register file: %s",
+		compile_error(ctx, "unsupported src register file: %s\n",
 			tgsi_file_name(src->File));
-		assert(0);
 		break;
 	}
 
@@ -254,15 +303,7 @@ add_src_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 
 	reg = ir3_reg_create(instr, regid(num, chan), flags);
 
-	if (regmask_get(ctx->needs_ss, reg)) {
-		instr->flags |= IR3_INSTR_SS;
-		memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
-	}
-
-	if (regmask_get(ctx->needs_sy, reg)) {
-		instr->flags |= IR3_INSTR_SY;
-		memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
-	}
+	instr->flags |= src_flags(ctx, reg);
 
 	return reg;
 }
@@ -285,11 +326,11 @@ src_from_dst(struct tgsi_src_register *src, struct tgsi_dst_register *dst)
 /* Get internal-temp src/dst to use for a sequence of instructions
  * generated by a single TGSI op.
  */
-static void
+static struct tgsi_src_register *
 get_internal_temp(struct fd3_compile_context *ctx,
-		struct tgsi_dst_register *tmp_dst,
-		struct tgsi_src_register *tmp_src)
+		struct tgsi_dst_register *tmp_dst)
 {
+	struct tgsi_src_register *tmp_src;
 	int n;
 
 	tmp_dst->File      = TGSI_FILE_TEMPORARY;
@@ -299,23 +340,78 @@ get_internal_temp(struct fd3_compile_context *ctx,
 
 	/* assign next temporary: */
 	n = ctx->num_internal_temps++;
+	compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
+	tmp_src = &ctx->internal_temps[n];
 
-	tmp_dst->Index = ctx->info.file_count[TGSI_FILE_TEMPORARY] + n;
+	tmp_dst->Index = ctx->info.file_max[TGSI_FILE_TEMPORARY] + n + 1;
 
 	src_from_dst(tmp_src, tmp_dst);
+
+	return tmp_src;
 }
 
 /* same as get_internal_temp, but w/ src.xxxx (for instructions that
  * replicate their results)
  */
-static void
+static struct tgsi_src_register *
 get_internal_temp_repl(struct fd3_compile_context *ctx,
-		struct tgsi_dst_register *tmp_dst,
-		struct tgsi_src_register *tmp_src)
+		struct tgsi_dst_register *tmp_dst)
 {
-	get_internal_temp(ctx, tmp_dst, tmp_src);
+	struct tgsi_src_register *tmp_src =
+			get_internal_temp(ctx, tmp_dst);
 	tmp_src->SwizzleX = tmp_src->SwizzleY =
 		tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
+	return tmp_src;
+}
+
+static inline bool
+is_const(struct tgsi_src_register *src)
+{
+	return (src->File == TGSI_FILE_CONSTANT) ||
+			(src->File == TGSI_FILE_IMMEDIATE);
+}
+
+static type_t
+get_ftype(struct fd3_compile_context *ctx)
+{
+	return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
+}
+
+static type_t
+get_utype(struct fd3_compile_context *ctx)
+{
+	return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
+}
+
+static unsigned
+src_swiz(struct tgsi_src_register *src, int chan)
+{
+	switch (chan) {
+	case 0: return src->SwizzleX;
+	case 1: return src->SwizzleY;
+	case 2: return src->SwizzleZ;
+	case 3: return src->SwizzleW;
+	}
+	assert(0);
+	return 0;
+}
+
+/* for instructions that cannot take a const register as src, if needed
+ * generate a move to temporary gpr:
+ */
+static struct tgsi_src_register *
+get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
+{
+	struct tgsi_dst_register tmp_dst;
+	struct tgsi_src_register *tmp_src;
+
+	compile_assert(ctx, is_const(src));
+
+	tmp_src = get_internal_temp(ctx, &tmp_dst);
+
+	create_mov(ctx, &tmp_dst, src);
+
+	return tmp_src;
 }
 
 static void
@@ -365,30 +461,11 @@ get_immediate(struct fd3_compile_context *ctx,
 	reg->SwizzleW  = swiz2tgsi[swiz];
 }
 
-static type_t
-get_type(struct fd3_compile_context *ctx)
-{
-	return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
-}
-
-static unsigned
-src_swiz(struct tgsi_src_register *src, int chan)
-{
-	switch (chan) {
-	case 0: return src->SwizzleX;
-	case 1: return src->SwizzleY;
-	case 2: return src->SwizzleZ;
-	case 3: return src->SwizzleW;
-	}
-	assert(0);
-	return 0;
-}
-
 static void
 create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
 		struct tgsi_src_register *src)
 {
-	type_t type_mov = get_type(ctx);
+	type_t type_mov = get_ftype(ctx);
 	unsigned i;
 
 	for (i = 0; i < 4; i++) {
@@ -404,7 +481,35 @@ create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
 			ir3_instr_create(ctx->ir, 0, OPC_NOP);
 		}
 	}
+}
 
+static void
+create_clamp(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
+		struct tgsi_src_register *minval, struct tgsi_src_register *maxval)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_src_register src;
+
+	src_from_dst(&src, dst);
+
+	instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
+	vectorize(ctx, instr, dst, 2, &src, 0, minval, 0);
+
+	instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
+	vectorize(ctx, instr, dst, 2, &src, 0, maxval, 0);
+}
+
+static void
+create_clamp_imm(struct fd3_compile_context *ctx,
+		struct tgsi_dst_register *dst,
+		uint32_t minval, uint32_t maxval)
+{
+	struct tgsi_src_register minconst, maxconst;
+
+	get_immediate(ctx, &minconst, minval);
+	get_immediate(ctx, &maxconst, maxval);
+
+	create_clamp(ctx, dst, &minconst, &maxconst);
 }
 
 static struct tgsi_dst_register *
@@ -415,7 +520,7 @@ get_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst)
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		struct tgsi_src_register *src = &inst->Src[i].Register;
 		if ((src->File == dst->File) && (src->Index == dst->Index)) {
-			get_internal_temp(ctx, &ctx->tmp_dst, &ctx->tmp_src);
+			ctx->tmp_src = get_internal_temp(ctx, &ctx->tmp_dst);
 			ctx->tmp_dst.WriteMask = dst->WriteMask;
 			dst = &ctx->tmp_dst;
 			break;
@@ -430,7 +535,7 @@ put_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst,
 {
 	/* if necessary, add mov back into original dst: */
 	if (dst != &inst->Dst[0].Register) {
-		create_mov(ctx, &inst->Dst[0].Register, &ctx->tmp_src);
+		create_mov(ctx, &inst->Dst[0].Register, ctx->tmp_src);
 	}
 }
 
@@ -478,6 +583,7 @@ vectorize(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
 				cur->regs[j+1]->num =
 					regid(cur->regs[j+1]->num >> 2,
 						src_swiz(src, i));
+				cur->flags |= src_flags(ctx, cur->regs[j+1]);
 			}
 			va_end(ap);
 		}
@@ -496,6 +602,15 @@ vectorize(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
  * native instructions:
  */
 
+static inline void
+get_swiz(unsigned *swiz, struct tgsi_src_register *src)
+{
+	swiz[0] = src->SwizzleX;
+	swiz[1] = src->SwizzleY;
+	swiz[2] = src->SwizzleZ;
+	swiz[3] = src->SwizzleW;
+}
+
 static void
 trans_dotp(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
@@ -503,39 +618,35 @@ trans_dotp(const struct instr_translater *t,
 {
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 	struct tgsi_dst_register *dst  = &inst->Dst[0].Register;
 	struct tgsi_src_register *src0 = &inst->Src[0].Register;
 	struct tgsi_src_register *src1 = &inst->Src[1].Register;
-	unsigned swiz0[] = { src0->SwizzleX, src0->SwizzleY, src0->SwizzleZ, src0->SwizzleW };
-	unsigned swiz1[] = { src1->SwizzleX, src1->SwizzleY, src1->SwizzleZ, src1->SwizzleW };
+	unsigned swiz0[4];
+	unsigned swiz1[4];
 	opc_t opc_mad    = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
 	unsigned n = t->arg;     /* number of components */
-	unsigned i;
+	unsigned i, swapped = 0;
 
-	get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
+	tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
 
-	/* Blob compiler never seems to use a const in src1 position for
-	 * mad.*, although there does seem (according to disassembler
-	 * hidden in libllvm-a3xx.so) to be a bit to indicate that src1
-	 * is a const.  Not sure if this is a hw bug, or simply that the
-	 * disassembler lies.
+	/* in particular, can't handle const for src1 for cat3/mad:
 	 */
-	if ((src1->File == TGSI_FILE_IMMEDIATE) ||
-			(src1->File == TGSI_FILE_CONSTANT)) {
-
-		/* the mov to tmp unswizzles src1, so now we have tmp.xyzw:
-		 */
-		for (i = 0; i < 4; i++)
-			swiz1[i] = i;
-
-		/* the first mul.f will clobber tmp.x, but that is ok
-		 * because after that point we no longer need tmp.x:
-		 */
-		create_mov(ctx, &tmp_dst, src1);
-		src1 = &tmp_src;
+	if (is_const(src1)) {
+		if (!is_const(src0)) {
+			struct tgsi_src_register *tmp;
+			tmp = src0;
+			src0 = src1;
+			src1 = tmp;
+			swapped = 1;
+		} else {
+			src0 = get_unconst(ctx, src0);
+		}
 	}
 
+	get_swiz(swiz0, src0);
+	get_swiz(swiz1, src1);
+
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	add_dst_reg(ctx, instr, &tmp_dst, 0);
 	add_src_reg(ctx, instr, src0, swiz0[0]);
@@ -548,29 +659,27 @@ trans_dotp(const struct instr_translater *t,
 		add_dst_reg(ctx, instr, &tmp_dst, 0);
 		add_src_reg(ctx, instr, src0, swiz0[i]);
 		add_src_reg(ctx, instr, src1, swiz1[i]);
-		add_src_reg(ctx, instr, &tmp_src, 0);
+		add_src_reg(ctx, instr, tmp_src, 0);
 	}
 
 	/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
 	if (t->tgsi_opc == TGSI_OPCODE_DPH) {
-		ir3_instr_create(ctx->ir, 0, OPC_NOP);
+		ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
 
 		instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
 		add_dst_reg(ctx, instr, &tmp_dst, 0);
-		add_src_reg(ctx, instr, src1, swiz1[i]);
-		add_src_reg(ctx, instr, &tmp_src, 0);
+		if (swapped)
+			add_src_reg(ctx, instr, src0, swiz0[i]);
+		else
+			add_src_reg(ctx, instr, src1, swiz1[i]);
+		add_src_reg(ctx, instr, tmp_src, 0);
 
 		n++;
 	}
 
-	ir3_instr_create(ctx->ir, 0, OPC_NOP);
+	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 2;
 
-	/* pad out to multiple of 4 scalar instructions: */
-	for (i = 2 * n; i % 4; i++) {
-		ir3_instr_create(ctx->ir, 0, OPC_NOP);
-	}
-
-	create_mov(ctx, dst, &tmp_src);
+	create_mov(ctx, dst, tmp_src);
 }
 
 /* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
@@ -581,37 +690,39 @@ trans_lrp(const struct instr_translater *t,
 {
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst1, tmp_dst2;
-	struct tgsi_src_register tmp_src1, tmp_src2;
+	struct tgsi_src_register *tmp_src1, *tmp_src2;
 	struct tgsi_src_register tmp_const;
+	struct tgsi_src_register *src0 = &inst->Src[0].Register;
+	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 
-	get_internal_temp(ctx, &tmp_dst1, &tmp_src1);
-	get_internal_temp(ctx, &tmp_dst2, &tmp_src2);
+	if (is_const(src0) && is_const(src1))
+		src0 = get_unconst(ctx, src0);
+
+	tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
+	tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
 
 	get_immediate(ctx, &tmp_const, fui(1.0));
 
 	/* tmp1 = (a * b) */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
-	vectorize(ctx, instr, &tmp_dst1, 2,
-			&inst->Src[0].Register, 0,
-			&inst->Src[1].Register, 0);
+	vectorize(ctx, instr, &tmp_dst1, 2, src0, 0, src1, 0);
 
 	/* tmp2 = (1 - a) */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
-	vectorize(ctx, instr, &tmp_dst2, 2,
-			&tmp_const, 0,
-			&inst->Src[0].Register, IR3_REG_NEGATE);
+	vectorize(ctx, instr, &tmp_dst2, 2, &tmp_const, 0,
+			src0, IR3_REG_NEGATE);
 
 	/* tmp2 = tmp2 * c */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	vectorize(ctx, instr, &tmp_dst2, 2,
-			&tmp_src2, 0,
+			tmp_src2, 0,
 			&inst->Src[2].Register, 0);
 
 	/* dst = tmp1 + tmp2 */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
 	vectorize(ctx, instr, &inst->Dst[0].Register, 2,
-			&tmp_src1, 0,
-			&tmp_src2, 0);
+			tmp_src1, 0,
+			tmp_src2, 0);
 }
 
 /* FRC(x) = x - FLOOR(x) */
@@ -622,9 +733,9 @@ trans_frac(const struct instr_translater *t,
 {
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 
-	get_internal_temp(ctx, &tmp_dst, &tmp_src);
+	tmp_src = get_internal_temp(ctx, &tmp_dst);
 
 	/* tmp = FLOOR(x) */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_FLOOR_F);
@@ -635,7 +746,7 @@ trans_frac(const struct instr_translater *t,
 	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
 	vectorize(ctx, instr, &inst->Dst[0].Register, 2,
 			&inst->Src[0].Register, 0,
-			&tmp_src, IR3_REG_NEGATE);
+			tmp_src, IR3_REG_NEGATE);
 }
 
 /* POW(a,b) = EXP2(b * LOG2(a)) */
@@ -647,24 +758,24 @@ trans_pow(const struct instr_translater *t,
 	struct ir3_instruction *instr;
 	struct ir3_register *r;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
+	struct tgsi_src_register *tmp_src;
 	struct tgsi_dst_register *dst  = &inst->Dst[0].Register;
 	struct tgsi_src_register *src0 = &inst->Src[0].Register;
 	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 
-	get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
+	tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
 
 	/* log2 Rtmp, Rsrc0 */
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
 	instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
 	r = add_dst_reg(ctx, instr, &tmp_dst, 0);
 	add_src_reg(ctx, instr, src0, src0->SwizzleX);
-	regmask_set(ctx->needs_ss, r);
+	regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
 
 	/* mul.f Rtmp, Rtmp, Rsrc1 */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
 	add_dst_reg(ctx, instr, &tmp_dst, 0);
-	add_src_reg(ctx, instr, &tmp_src, 0);
+	add_src_reg(ctx, instr, tmp_src, 0);
 	add_src_reg(ctx, instr, src1, src1->SwizzleX);
 
 	/* blob compiler seems to ensure there are at least 6 instructions
@@ -676,10 +787,10 @@ trans_pow(const struct instr_translater *t,
 	/* exp2 Rdst, Rtmp */
 	instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
 	r = add_dst_reg(ctx, instr, &tmp_dst, 0);
-	add_src_reg(ctx, instr, &tmp_src, 0);
-	regmask_set(ctx->needs_ss, r);
+	add_src_reg(ctx, instr, tmp_src, 0);
+	regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
 
-	create_mov(ctx, dst, &tmp_src);
+	create_mov(ctx, dst, tmp_src);
 }
 
 /* texture fetch/sample instructions: */
@@ -690,8 +801,6 @@ trans_samp(const struct instr_translater *t,
 {
 	struct ir3_register *r;
 	struct ir3_instruction *instr;
-	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
 	struct tgsi_src_register *coord = &inst->Src[0].Register;
 	struct tgsi_src_register *samp  = &inst->Src[1].Register;
 	unsigned tex = inst->Texture.Texture;
@@ -711,7 +820,7 @@ trans_samp(const struct instr_translater *t,
 		flags |= IR3_INSTR_P;
 		break;
 	default:
-		assert(0);
+		compile_assert(ctx, 0);
 		break;
 	}
 
@@ -726,10 +835,13 @@ trans_samp(const struct instr_translater *t,
 	 */
 	for (i = 1; (i < 4) && (order[i] >= 0); i++) {
 		if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i])) {
-			type_t type_mov = get_type(ctx);
+			struct tgsi_dst_register tmp_dst;
+			struct tgsi_src_register *tmp_src;
+
+			type_t type_mov = get_ftype(ctx);
 
 			/* need to move things around: */
-			get_internal_temp(ctx, &tmp_dst, &tmp_src);
+			tmp_src = get_internal_temp(ctx, &tmp_dst);
 
 			for (j = 0; (j < 4) && (order[j] >= 0); j++) {
 				instr = ir3_instr_create(ctx->ir, 1, 0);
@@ -740,7 +852,7 @@ trans_samp(const struct instr_translater *t,
 						src_swiz(coord, order[j]));
 			}
 
-			coord = &tmp_src;
+			coord = tmp_src;
 
 			if (j < 4)
 				ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 4 - j - 1;
@@ -750,7 +862,7 @@ trans_samp(const struct instr_translater *t,
 	}
 
 	instr = ir3_instr_create(ctx->ir, 5, t->opc);
-	instr->cat5.type = get_type(ctx);
+	instr->cat5.type = get_ftype(ctx);
 	instr->cat5.samp = samp->Index;
 	instr->cat5.tex  = samp->Index;
 	instr->flags |= flags;
@@ -760,10 +872,42 @@ trans_samp(const struct instr_translater *t,
 
 	add_src_reg(ctx, instr, coord, coord->SwizzleX);
 
-	regmask_set(ctx->needs_sy, r);
+	regmask_set(ctx->needs_sy, r, r->wrmask);
 }
 
-/* CMP(a,b,c) = (a < 0) ? b : c */
+/*
+ * SEQ(a,b) = (a == b) ? 1.0 : 0.0
+ *   cmps.f.eq tmp0, b, a
+ *   cov.u16f16 dst, tmp0
+ *
+ * SNE(a,b) = (a != b) ? 1.0 : 0.0
+ *   cmps.f.eq tmp0, b, a
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * SGE(a,b) = (a >= b) ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, a, b
+ *   cov.u16f16 dst, tmp0
+ *
+ * SLE(a,b) = (a <= b) ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, b, a
+ *   cov.u16f16 dst, tmp0
+ *
+ * SGT(a,b) = (a > b)  ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, b, a
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * SLT(a,b) = (a < b)  ? 1.0 : 0.0
+ *   cmps.f.ge tmp0, a, b
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * CMP(a,b,c) = (a < 0.0) ? b : c
+ *   cmps.f.ge tmp0, a, {0.0}
+ *   add.s tmp0, tmp0, -1
+ *   sel.f16 dst, c, tmp0, b
+ */
 static void
 trans_cmp(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
@@ -771,35 +915,94 @@ trans_cmp(const struct instr_translater *t,
 {
 	struct ir3_instruction *instr;
 	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
-	struct tgsi_src_register constval;
-	/* final instruction uses original src1 and src2, so we need get_dst() */
+	struct tgsi_src_register *tmp_src;
+	struct tgsi_src_register constval0, constval1;
+	/* final instruction for CMP() uses orig src1 and src2: */
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *a0, *a1;
+	unsigned condition;
 
-	get_internal_temp(ctx, &tmp_dst, &tmp_src);
+	tmp_src = get_internal_temp(ctx, &tmp_dst);
 
-	/* cmps.f.ge tmp, src0, 0.0 */
+	switch (t->tgsi_opc) {
+	case TGSI_OPCODE_SEQ:
+	case TGSI_OPCODE_SNE:
+		a0 = &inst->Src[1].Register;  /* b */
+		a1 = &inst->Src[0].Register;  /* a */
+		condition = IR3_COND_EQ;
+		break;
+	case TGSI_OPCODE_SGE:
+	case TGSI_OPCODE_SLT:
+		a0 = &inst->Src[0].Register;  /* a */
+		a1 = &inst->Src[1].Register;  /* b */
+		condition = IR3_COND_GE;
+		break;
+	case TGSI_OPCODE_SLE:
+	case TGSI_OPCODE_SGT:
+		a0 = &inst->Src[1].Register;  /* b */
+		a1 = &inst->Src[0].Register;  /* a */
+		condition = IR3_COND_GE;
+		break;
+	case TGSI_OPCODE_CMP:
+		get_immediate(ctx, &constval0, fui(0.0));
+		a0 = &inst->Src[0].Register;  /* a */
+		a1 = &constval0;              /* {0.0} */
+		condition = IR3_COND_GE;
+		break;
+	default:
+		compile_assert(ctx, 0);
+		return;
+	}
+
+	if (is_const(a0) && is_const(a1))
+		a0 = get_unconst(ctx, a0);
+
+	/* cmps.f.ge tmp, a0, a1 */
 	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
-	instr->cat2.condition = IR3_COND_GE;
-	get_immediate(ctx, &constval, fui(0.0));
-	vectorize(ctx, instr, &tmp_dst, 2,
-			&inst->Src[0].Register, 0,
-			&constval, 0);
+	instr->cat2.condition = condition;
+	vectorize(ctx, instr, &tmp_dst, 2, a0, 0, a1, 0);
 
-	/* add.s tmp, tmp, -1 */
-	instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
-	instr->repeat = 3;
-	add_dst_reg(ctx, instr, &tmp_dst, 0);
-	add_src_reg(ctx, instr, &tmp_src, 0);
-	ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
+	switch (t->tgsi_opc) {
+	case TGSI_OPCODE_SEQ:
+	case TGSI_OPCODE_SGE:
+	case TGSI_OPCODE_SLE:
+		/* cov.u16f16 dst, tmp0 */
+		instr = ir3_instr_create(ctx->ir, 1, 0);
+		instr->cat1.src_type = get_utype(ctx);
+		instr->cat1.dst_type = get_ftype(ctx);
+		vectorize(ctx, instr, dst, 1, tmp_src, 0);
+		break;
+	case TGSI_OPCODE_SNE:
+	case TGSI_OPCODE_SGT:
+	case TGSI_OPCODE_SLT:
+	case TGSI_OPCODE_CMP:
+		/* add.s tmp, tmp, -1 */
+		instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
+		instr->repeat = 3;
+		add_dst_reg(ctx, instr, &tmp_dst, 0);
+		add_src_reg(ctx, instr, tmp_src, 0)->flags |= IR3_REG_R;
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
 
-	/* sel.{f32,f16} dst, src2, tmp, src1 */
-	instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
-			OPC_SEL_F16 : OPC_SEL_F32);
-	vectorize(ctx, instr, &inst->Dst[0].Register, 3,
-			&inst->Src[2].Register, 0,
-			&tmp_src, 0,
-			&inst->Src[1].Register, 0);
+		if (t->tgsi_opc == TGSI_OPCODE_CMP) {
+			/* sel.{f32,f16} dst, src2, tmp, src1 */
+			instr = ir3_instr_create(ctx->ir, 3,
+					ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
+			vectorize(ctx, instr, dst, 3,
+					&inst->Src[2].Register, 0,
+					tmp_src, 0,
+					&inst->Src[1].Register, 0);
+		} else {
+			get_immediate(ctx, &constval0, fui(0.0));
+			get_immediate(ctx, &constval1, fui(1.0));
+			/* sel.{f32,f16} dst, {0.0}, tmp0, {1.0} */
+			instr = ir3_instr_create(ctx->ir, 3,
+					ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
+			vectorize(ctx, instr, dst, 3,
+					&constval0, 0, tmp_src, 0, &constval1, 0);
+		}
+
+		break;
+	}
 
 	put_dst(ctx, inst, dst);
 }
@@ -858,10 +1061,13 @@ trans_if(const struct instr_translater *t,
 
 	get_immediate(ctx, &constval, fui(0.0));
 
+	if (is_const(src))
+		src = get_unconst(ctx, src);
+
 	instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
 	ir3_reg_create(instr, regid(REG_P0, 0), 0);
-	add_src_reg(ctx, instr, &constval, constval.SwizzleX);
 	add_src_reg(ctx, instr, src, src->SwizzleX);
+	add_src_reg(ctx, instr, &constval, constval.SwizzleX);
 	instr->cat2.condition = IR3_COND_EQ;
 
 	instr = ir3_instr_create(ctx->ir, 0, OPC_BR);
@@ -939,16 +1145,12 @@ instr_cat2(const struct instr_translater *t,
 		struct tgsi_full_instruction *inst)
 {
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src0 = &inst->Src[0].Register;
+	struct tgsi_src_register *src1 = &inst->Src[1].Register;
 	struct ir3_instruction *instr;
 	unsigned src0_flags = 0;
 
-	instr = ir3_instr_create(ctx->ir, 2, t->opc);
-
 	switch (t->tgsi_opc) {
-	case TGSI_OPCODE_SLT:
-	case TGSI_OPCODE_SGE:
-		instr->cat2.condition = t->arg;
-		break;
 	case TGSI_OPCODE_ABS:
 		src0_flags = IR3_REG_ABS;
 		break;
@@ -970,48 +1172,65 @@ instr_cat2(const struct instr_translater *t,
 	case OPC_SETRM:
 	case OPC_CBITS_B:
 		/* these only have one src reg */
-		vectorize(ctx, instr, dst, 1,
-				&inst->Src[0].Register, src0_flags);
+		instr = ir3_instr_create(ctx->ir, 2, t->opc);
+		vectorize(ctx, instr, dst, 1, src0, src0_flags);
 		break;
 	default:
-		vectorize(ctx, instr, dst, 2,
-				&inst->Src[0].Register, src0_flags,
-				&inst->Src[1].Register, 0);
+		if (is_const(src0) && is_const(src1))
+			src0 = get_unconst(ctx, src0);
+
+		instr = ir3_instr_create(ctx->ir, 2, t->opc);
+		vectorize(ctx, instr, dst, 2, src0, src0_flags, src1, 0);
 		break;
 	}
 
 	put_dst(ctx, inst, dst);
 }
 
+static bool is_mad(opc_t opc)
+{
+	switch (opc) {
+	case OPC_MAD_U16:
+	case OPC_MADSH_U16:
+	case OPC_MAD_S16:
+	case OPC_MADSH_M16:
+	case OPC_MAD_U24:
+	case OPC_MAD_S24:
+	case OPC_MAD_F16:
+	case OPC_MAD_F32:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static void
 instr_cat3(const struct instr_translater *t,
 		struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
 {
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src0 = &inst->Src[0].Register;
 	struct tgsi_src_register *src1 = &inst->Src[1].Register;
-	struct tgsi_dst_register tmp_dst;
-	struct tgsi_src_register tmp_src;
 	struct ir3_instruction *instr;
 
-	/* Blob compiler never seems to use a const in src1 position..
-	 * although there does seem (according to disassembler hidden
-	 * in libllvm-a3xx.so) to be a bit to indicate that src1 is a
-	 * const.  Not sure if this is a hw bug, or simply that the
-	 * disassembler lies.
+	/* in particular, can't handle const for src1 for cat3..
+	 * for mad, we can swap first two src's if needed:
 	 */
-	if ((src1->File == TGSI_FILE_CONSTANT) ||
-			(src1->File == TGSI_FILE_IMMEDIATE)) {
-		get_internal_temp(ctx, &tmp_dst, &tmp_src);
-		create_mov(ctx, &tmp_dst, src1);
-		src1 = &tmp_src;
+	if (is_const(src1)) {
+		if (is_mad(t->opc) && !is_const(src0)) {
+			struct tgsi_src_register *tmp;
+			tmp = src0;
+			src0 = src1;
+			src1 = tmp;
+		} else {
+			src0 = get_unconst(ctx, src0);
+		}
 	}
 
 	instr = ir3_instr_create(ctx->ir, 3,
 			ctx->so->half_precision ? t->hopc : t->opc);
-	vectorize(ctx, instr, dst, 3,
-			&inst->Src[0].Register, 0,
-			src1, 0,
+	vectorize(ctx, instr, dst, 3, src0, 0, src1, 0,
 			&inst->Src[2].Register, 0);
 	put_dst(ctx, inst, dst);
 }
@@ -1022,15 +1241,20 @@ instr_cat4(const struct instr_translater *t,
 		struct tgsi_full_instruction *inst)
 {
 	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src = &inst->Src[0].Register;
 	struct ir3_instruction *instr;
 
+	/* seems like blob compiler avoids const as src.. */
+	if (is_const(src))
+		src = get_unconst(ctx, src);
+
 	ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
 	instr = ir3_instr_create(ctx->ir, 4, t->opc);
 
-	vectorize(ctx, instr, dst, 1,
-			&inst->Src[0].Register, 0);
+	vectorize(ctx, instr, dst, 1, src, 0);
 
-	regmask_set(ctx->needs_ss, instr->regs[0]);
+	regmask_set(ctx->needs_ss, instr->regs[0],
+			inst->Dst[0].Register.WriteMask);
 
 	put_dst(ctx, inst, dst);
 }
@@ -1051,12 +1275,11 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
 	INSTR(DPH,          trans_dotp, .arg = 3),   /* almost like DP3 */
 	INSTR(MIN,          instr_cat2, .opc = OPC_MIN_F),
 	INSTR(MAX,          instr_cat2, .opc = OPC_MAX_F),
-	INSTR(SLT,          instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_LT),
-	INSTR(SGE,          instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_GE),
 	INSTR(MAD,          instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
 	INSTR(LRP,          trans_lrp),
 	INSTR(FRC,          trans_frac),
 	INSTR(FLR,          instr_cat2, .opc = OPC_FLOOR_F),
+	INSTR(ARL,          instr_cat2, .opc = OPC_FLOOR_F),
 	INSTR(EX2,          instr_cat4, .opc = OPC_EXP2),
 	INSTR(LG2,          instr_cat4, .opc = OPC_LOG2),
 	INSTR(POW,          trans_pow),
@@ -1065,6 +1288,12 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
 	INSTR(SIN,          instr_cat4, .opc = OPC_COS),
 	INSTR(TEX,          trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX),
 	INSTR(TXP,          trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP),
+	INSTR(SGT,          trans_cmp),
+	INSTR(SLT,          trans_cmp),
+	INSTR(SGE,          trans_cmp),
+	INSTR(SLE,          trans_cmp),
+	INSTR(SNE,          trans_cmp),
+	INSTR(SEQ,          trans_cmp),
 	INSTR(CMP,          trans_cmp),
 	INSTR(IF,           trans_if),
 	INSTR(ELSE,         trans_else),
@@ -1132,7 +1361,7 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 	unsigned name = decl->Semantic.Name;
 	unsigned i;
 
-	assert(decl->Declaration.Semantic);  // TODO is this ever not true?
+	compile_assert(ctx, decl->Declaration.Semantic);  // TODO is this ever not true?
 
 	DBG("decl out[%d] -> r%d", name, decl->Range.First + base);   // XXX
 
@@ -1152,9 +1381,8 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 				so->outputs[so->outputs_count++].regid = regid(i + base, 0);
 			break;
 		default:
-			DBG("unknown VS semantic name: %s",
+			compile_error(ctx, "unknown VS semantic name: %s\n",
 					tgsi_semantic_names[name]);
-			assert(0);
 		}
 	} else {
 		switch (name) {
@@ -1162,9 +1390,8 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 			so->color_regid = regid(decl->Range.First + base, 0);
 			break;
 		default:
-			DBG("unknown VS semantic name: %s",
+			compile_error(ctx, "unknown VS semantic name: %s\n",
 					tgsi_semantic_names[name]);
-			assert(0);
 		}
 	}
 }
@@ -1223,10 +1450,19 @@ compile_instructions(struct fd3_compile_context *ctx)
 				t->fxn(t, ctx, inst);
 				ctx->num_internal_temps = 0;
 			} else {
-				debug_printf("unknown TGSI opc: %s\n",
+				compile_error(ctx, "unknown TGSI opc: %s\n",
 						tgsi_get_opcode_name(opc));
-				tgsi_dump(ctx->tokens, 0);
-				assert(0);
+			}
+
+			switch (inst->Instruction.Saturate) {
+			case TGSI_SAT_ZERO_ONE:
+				create_clamp_imm(ctx, &inst->Dst[0].Register,
+						fui(0.0), fui(1.0));
+				break;
+			case TGSI_SAT_MINUS_PLUS_ONE:
+				create_clamp_imm(ctx, &inst->Dst[0].Register,
+						fui(-1.0), fui(1.0));
+				break;
 			}
 
 			break;
@@ -1253,6 +1489,8 @@ fd3_compile_shader(struct fd3_shader_stateobj *so,
 
 	so->ir = ir3_shader_create();
 
+	assert(so->ir);
+
 	so->color_regid = regid(63,0);
 	so->pos_regid   = regid(63,0);
 	so->psize_regid = regid(63,0);

src/gallium/drivers/freedreno/a3xx/fd3_context.c

@@ -40,7 +40,18 @@
 static void
 fd3_context_destroy(struct pipe_context *pctx)
 {
+	struct fd3_context *fd3_ctx = fd3_context(fd_context(pctx));
+
 	fd3_prog_fini(pctx);
+
+	fd_bo_del(fd3_ctx->vs_pvt_mem);
+	fd_bo_del(fd3_ctx->fs_pvt_mem);
+	fd_bo_del(fd3_ctx->vsc_size_mem);
+	fd_bo_del(fd3_ctx->vsc_pipe_mem);
+
+	pipe_resource_reference(&fd3_ctx->solid_vbuf, NULL);
+	pipe_resource_reference(&fd3_ctx->blit_texcoord_vbuf, NULL);
+
 	fd_context_destroy(pctx);
 }
 

src/gallium/drivers/freedreno/a3xx/fd3_emit.c

@@ -81,7 +81,7 @@ fd3_emit_constant(struct fd_ringbuffer *ring,
 	if (prsc) {
 		struct fd_bo *bo = fd_resource(prsc)->bo;
 		OUT_RELOC(ring, bo, offset,
-				CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
+				CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
 	} else {
 		OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 				CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
@@ -212,7 +212,7 @@ emit_textures(struct fd_ringbuffer *ring,
 	for (i = 0; i < tex->num_textures; i++) {
 		struct fd3_pipe_sampler_view *view =
 				fd3_pipe_sampler_view(tex->textures[i]);
-		OUT_RELOC(ring, view->tex_resource->bo, 0, 0);
+		OUT_RELOC(ring, view->tex_resource->bo, 0, 0, 0);
 		/* I think each entry is a ptr to mipmap level.. for now, just
 		 * pad w/ null's until I get around to actually implementing
 		 * mipmap support..
@@ -279,9 +279,9 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf
 			CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 	OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(psurf->format)) |
 			0x40000000 | // XXX
-			fd3_tex_swiz(psurf->format,  PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_GREEN,
-					PIPE_SWIZZLE_RED, PIPE_SWIZZLE_ALPHA));
-	OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(fd3_pipe2fetchsize(psurf->format)) |
+			fd3_tex_swiz(psurf->format,  PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
+					PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
+	OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
 			A3XX_TEX_CONST_1_WIDTH(psurf->width) |
 			A3XX_TEX_CONST_1_HEIGHT(psurf->height));
 	OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc->pitch * rsc->cpp) |
@@ -296,7 +296,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf
 			CP_LOAD_STATE_0_NUM_UNIT(1));
 	OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 			CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
-	OUT_RELOC(ring, rsc->bo, 0, 0);
+	OUT_RELOC(ring, rsc->bo, 0, 0, 0);
 }
 
 void
@@ -322,7 +322,7 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 				COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
 				A3XX_VFD_FETCH_INSTR_0_INDEXCODE(i) |
 				A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
-		OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0);
+		OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 0, 0);
 
 		OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(i), 1);
 		OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
@@ -481,12 +481,12 @@ fd3_emit_restore(struct fd_context *ctx)
 
 	OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_CTRL_REG, 3);
 	OUT_RING(ring, 0x08000001);                  /* SP_VS_PVT_MEM_CTRL_REG */
-	OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0, 0);  /* SP_VS_PVT_MEM_ADDR_REG */
+	OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
 	OUT_RING(ring, 0x00000000);                  /* SP_VS_PVT_MEM_SIZE_REG */
 
 	OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_CTRL_REG, 3);
 	OUT_RING(ring, 0x08000001);                  /* SP_FS_PVT_MEM_CTRL_REG */
-	OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0, 0);  /* SP_FS_PVT_MEM_ADDR_REG */
+	OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
 	OUT_RING(ring, 0x00000000);                  /* SP_FS_PVT_MEM_SIZE_REG */
 
 	OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
@@ -536,8 +536,8 @@ fd3_emit_restore(struct fd_context *ctx)
 	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
 	OUT_RING(ring, 0x00000001);        /* UNKNOWN_0C3D */
 
-	OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E00, 1);
-	OUT_RING(ring, 0x00000000);        /* UNKNOWN_0E00 */
+	OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
+	OUT_RING(ring, 0x00000000);        /* HLSQ_PERFCOUNTER0_SELECT */
 
 	OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
 	OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
@@ -549,7 +549,7 @@ fd3_emit_restore(struct fd_context *ctx)
 	OUT_RING(ring, 0x00000001);        /* UCHE_CACHE_MODE_CONTROL_REG */
 
 	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
-	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0); /* VSC_SIZE_ADDRESS */
+	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 
 	OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 	OUT_RING(ring, 0x00000000);                  /* GRAS_CL_CLIP_CNTL */

src/gallium/drivers/freedreno/a3xx/fd3_gmem.c

@@ -89,7 +89,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 		if (bin_w || (i >= nr_bufs)) {
 			OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
 		} else {
-			OUT_RELOCS(ring, res->bo, 0, 0, -1);
+			OUT_RELOCW(ring, res->bo, 0, 0, -1);
 		}
 
 		OUT_PKT0(ring, REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i), 1);
@@ -116,7 +116,7 @@ emit_gmem2mem_surf(struct fd_ringbuffer *ring,
 	OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 			A3XX_RB_COPY_CONTROL_MODE(mode) |
 			A3XX_RB_COPY_CONTROL_GMEM_BASE(base));
-	OUT_RELOCS(ring, rsc->bo, 0, 0, -1);    /* RB_COPY_DEST_BASE */
+	OUT_RELOCW(ring, rsc->bo, 0, 0, -1);    /* RB_COPY_DEST_BASE */
 	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(rsc->pitch * rsc->cpp));
 	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 			A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(psurf->format)) |
@@ -168,6 +168,14 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 	OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
 	OUT_RING(ring, 0x00000000);   /* GRAS_CL_CLIP_CNTL */
 
+	OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height/2.0 - 0.5));
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height/2.0));
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
+	OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+
 	OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
 	OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 			A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE);
@@ -206,8 +214,12 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 		}, 1);
 
 	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
-		uint32_t base = depth_base(&ctx->gmem) *
-				fd_resource(pfb->cbufs[0]->texture)->cpp;
+		uint32_t base = 0;
+		if (pfb->cbufs[0]) {
+			struct fd_resource *rsc =
+					fd_resource(pfb->cbufs[0]->texture);
+			base = depth_base(&ctx->gmem) * rsc->cpp;
+		}
 		emit_gmem2mem_surf(ring, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 	}
 
@@ -260,7 +272,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 	y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 
 	OUT_PKT3(ring, CP_MEM_WRITE, 5);
-	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0);
+	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 	OUT_RING(ring, fui(x0));
 	OUT_RING(ring, fui(y0));
 	OUT_RING(ring, fui(x1));
@@ -383,7 +395,7 @@ update_vsc_pipe(struct fd_context *ctx)
 			A3XX_VSC_PIPE_CONFIG_Y(0) |
 			A3XX_VSC_PIPE_CONFIG_W(gmem->nbins_x) |
 			A3XX_VSC_PIPE_CONFIG_H(gmem->nbins_y));
-	OUT_RELOC(ring, bo, 0, 0);              /* VSC_PIPE[0].DATA_ADDRESS */
+	OUT_RELOC(ring, bo, 0, 0, 0);           /* VSC_PIPE[0].DATA_ADDRESS */
 	OUT_RING(ring, fd_bo_size(bo) - 32);    /* VSC_PIPE[0].DATA_LENGTH */
 
 	for (i = 1; i < 8; i++) {
@@ -402,8 +414,11 @@ static void
 fd3_emit_sysmem_prep(struct fd_context *ctx)
 {
 	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	struct fd_resource *rsc = fd_resource(pfb->cbufs[0]->texture);
 	struct fd_ringbuffer *ring = ctx->ring;
+	uint32_t pitch = 0;
+
+	if (pfb->cbufs[0])
+		pitch = fd_resource(pfb->cbufs[0]->texture)->pitch;
 
 	fd3_emit_restore(ctx);
 
@@ -414,7 +429,7 @@ fd3_emit_sysmem_prep(struct fd_context *ctx)
 	emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
 
 	fd3_emit_rbrc_tile_state(ring,
-			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(rsc->pitch));
+			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(pitch));
 
 	/* setup scissor/offset for current tile: */
 	OUT_PKT0(ring, REG_A3XX_PA_SC_WINDOW_OFFSET, 1);

src/gallium/drivers/freedreno/a3xx/fd3_program.c

@@ -249,7 +249,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
 	 */
 	for (i = 0; i < 6; i++) {
 		OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER0_SELECT, 1);
-		OUT_RING(ring, 0x00000000);    /* SP_PERFCOUNTER4_SELECT */
+		OUT_RING(ring, 0x00000000);    /* SP_PERFCOUNTER0_SELECT */
 
 		OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER4_SELECT, 1);
 		OUT_RING(ring, 0x00000000);    /* SP_PERFCOUNTER4_SELECT */
@@ -320,7 +320,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
 	OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 	OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 			A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
-	OUT_RELOC(ring, vp->bo, 0, 0);    /* SP_VS_OBJ_START_REG */
+	OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 #endif
 
 	OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
@@ -345,7 +345,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
 	OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 	OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 			A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(128 - fp->instrlen));
-	OUT_RELOC(ring, fp->bo, 0, 0);    /* SP_FS_OBJ_START_REG */
+	OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 #endif
 
 	OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);

src/gallium/drivers/freedreno/a3xx/fd3_texture.c

@@ -87,6 +87,7 @@ fd3_sampler_state_create(struct pipe_context *pctx,
 	so->base = *cso;
 
 	so->texsamp0 =
+			COND(!cso->normalized_coords, A3XX_TEX_SAMP_0_UNNORM_COORDS) |
 			A3XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter)) |
 			A3XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter)) |
 			A3XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s)) |
@@ -97,6 +98,28 @@ fd3_sampler_state_create(struct pipe_context *pctx,
 	return so;
 }
 
+static enum a3xx_tex_type
+tex_type(unsigned target)
+{
+	switch (target) {
+	default:
+		assert(0);
+	case PIPE_BUFFER:
+	case PIPE_TEXTURE_1D:
+	case PIPE_TEXTURE_1D_ARRAY:
+		return A3XX_TEX_1D;
+	case PIPE_TEXTURE_RECT:
+	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_2D_ARRAY:
+		return A3XX_TEX_2D;
+	case PIPE_TEXTURE_3D:
+		return A3XX_TEX_3D;
+	case PIPE_TEXTURE_CUBE:
+	case PIPE_TEXTURE_CUBE_ARRAY:
+		return A3XX_TEX_CUBE;
+	}
+}
+
 static struct pipe_sampler_view *
 fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 		const struct pipe_sampler_view *cso)
@@ -116,7 +139,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	so->tex_resource =  rsc;
 
 	so->texconst0 =
-			0x40000000 | /* ??? */
+			A3XX_TEX_CONST_0_TYPE(tex_type(prsc->target)) |
 			A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(cso->format)) |
 			fd3_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
 						cso->swizzle_b, cso->swizzle_a);

src/gallium/drivers/freedreno/a3xx/fd3_util.c

@@ -306,10 +306,11 @@ fd3_pipe2swap(enum pipe_format format)
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
 	case PIPE_FORMAT_B8G8R8X8_UNORM:
 		return WXYZ;
+
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
 	case PIPE_FORMAT_Z24X8_UNORM:
 	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
-		return WZYX;
-
 	default:
 		return WZYX;
 	}

src/gallium/drivers/freedreno/a3xx/ir-a3xx.h

@@ -166,8 +166,7 @@ struct ir3_instruction {
 	};
 };
 
-/* this is just large to cope w/ the large test *.asm: */
-#define MAX_INSTRS 10240
+#define MAX_INSTRS 1024
 
 struct ir3_shader {
 	unsigned instrs_count;

src/gallium/drivers/freedreno/adreno_common.xml.h

@@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml                (  42578 bytes, from 2013-06-02 13:10:46)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -113,5 +115,318 @@ enum adreno_rb_depth_format {
 	DEPTHX_24_8 = 1,
 };
 
+enum adreno_mmu_clnt_beh {
+	BEH_NEVR = 0,
+	BEH_TRAN_RNG = 1,
+	BEH_TRAN_FLT = 2,
+};
+
+#define REG_AXXX_MH_MMU_CONFIG					0x00000040
+#define AXXX_MH_MMU_CONFIG_MMU_ENABLE				0x00000001
+#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE			0x00000002
+#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK		0x00000030
+#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT		4
+static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK		0x000000c0
+#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT		6
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK		0x00000300
+#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT		8
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK		0x00000c00
+#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT		10
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK		0x00003000
+#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT		12
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK		0x0000c000
+#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT		14
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK		0x00030000
+#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT		16
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK		0x000c0000
+#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT		18
+static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK		0x00300000
+#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT		20
+static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK		0x00c00000
+#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT		22
+static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK		0x03000000
+#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT		24
+static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+	return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
+}
+
+#define REG_AXXX_MH_MMU_VA_RANGE				0x00000041
+
+#define REG_AXXX_MH_MMU_PT_BASE					0x00000042
+
+#define REG_AXXX_MH_MMU_PAGE_FAULT				0x00000043
+
+#define REG_AXXX_MH_MMU_TRAN_ERROR				0x00000044
+
+#define REG_AXXX_MH_MMU_INVALIDATE				0x00000045
+
+#define REG_AXXX_MH_MMU_MPU_BASE				0x00000046
+
+#define REG_AXXX_MH_MMU_MPU_END					0x00000047
+
+#define REG_AXXX_CP_RB_BASE					0x000001c0
+
+#define REG_AXXX_CP_RB_CNTL					0x000001c1
+#define AXXX_CP_RB_CNTL_BUFSZ__MASK				0x0000003f
+#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT				0
+static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
+{
+	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
+}
+#define AXXX_CP_RB_CNTL_BLKSZ__MASK				0x00003f00
+#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT				8
+static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
+{
+	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
+}
+#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK				0x00030000
+#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT				16
+static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
+{
+	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
+}
+#define AXXX_CP_RB_CNTL_POLL_EN					0x00100000
+#define AXXX_CP_RB_CNTL_NO_UPDATE				0x08000000
+#define AXXX_CP_RB_CNTL_RPTR_WR_EN				0x80000000
+
+#define REG_AXXX_CP_RB_RPTR_ADDR				0x000001c3
+#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK				0x00000003
+#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT			0
+static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
+{
+	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
+}
+#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK				0xfffffffc
+#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT			2
+static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
+{
+	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
+}
+
+#define REG_AXXX_CP_RB_RPTR					0x000001c4
+
+#define REG_AXXX_CP_RB_WPTR					0x000001c5
+
+#define REG_AXXX_CP_RB_WPTR_DELAY				0x000001c6
+
+#define REG_AXXX_CP_RB_RPTR_WR					0x000001c7
+
+#define REG_AXXX_CP_RB_WPTR_BASE				0x000001c8
+
+#define REG_AXXX_CP_QUEUE_THRESHOLDS				0x000001d5
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK		0x0000000f
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT		0
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
+{
+	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
+}
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK		0x00000f00
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT		8
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
+{
+	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
+}
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK		0x000f0000
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT		16
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
+{
+	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
+}
+
+#define REG_AXXX_CP_MEQ_THRESHOLDS				0x000001d6
+
+#define REG_AXXX_CP_CSQ_AVAIL					0x000001d7
+#define AXXX_CP_CSQ_AVAIL_RING__MASK				0x0000007f
+#define AXXX_CP_CSQ_AVAIL_RING__SHIFT				0
+static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
+}
+#define AXXX_CP_CSQ_AVAIL_IB1__MASK				0x00007f00
+#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT				8
+static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
+}
+#define AXXX_CP_CSQ_AVAIL_IB2__MASK				0x007f0000
+#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT				16
+static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
+}
+
+#define REG_AXXX_CP_STQ_AVAIL					0x000001d8
+#define AXXX_CP_STQ_AVAIL_ST__MASK				0x0000007f
+#define AXXX_CP_STQ_AVAIL_ST__SHIFT				0
+static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
+{
+	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
+}
+
+#define REG_AXXX_CP_MEQ_AVAIL					0x000001d9
+#define AXXX_CP_MEQ_AVAIL_MEQ__MASK				0x0000001f
+#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT				0
+static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
+{
+	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
+}
+
+#define REG_AXXX_SCRATCH_UMSK					0x000001dc
+#define AXXX_SCRATCH_UMSK_UMSK__MASK				0x000000ff
+#define AXXX_SCRATCH_UMSK_UMSK__SHIFT				0
+static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
+{
+	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
+}
+#define AXXX_SCRATCH_UMSK_SWAP__MASK				0x00030000
+#define AXXX_SCRATCH_UMSK_SWAP__SHIFT				16
+static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
+{
+	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
+}
+
+#define REG_AXXX_SCRATCH_ADDR					0x000001dd
+
+#define REG_AXXX_CP_ME_RDADDR					0x000001ea
+
+#define REG_AXXX_CP_STATE_DEBUG_INDEX				0x000001ec
+
+#define REG_AXXX_CP_STATE_DEBUG_DATA				0x000001ed
+
+#define REG_AXXX_CP_INT_CNTL					0x000001f2
+
+#define REG_AXXX_CP_INT_STATUS					0x000001f3
+
+#define REG_AXXX_CP_INT_ACK					0x000001f4
+
+#define REG_AXXX_CP_ME_CNTL					0x000001f6
+
+#define REG_AXXX_CP_ME_STATUS					0x000001f7
+
+#define REG_AXXX_CP_ME_RAM_WADDR				0x000001f8
+
+#define REG_AXXX_CP_ME_RAM_RADDR				0x000001f9
+
+#define REG_AXXX_CP_ME_RAM_DATA					0x000001fa
+
+#define REG_AXXX_CP_DEBUG					0x000001fc
+#define AXXX_CP_DEBUG_PREDICATE_DISABLE				0x00800000
+#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE			0x01000000
+#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE			0x02000000
+#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS			0x04000000
+#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE			0x08000000
+#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE			0x10000000
+#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL			0x40000000
+#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE			0x80000000
+
+#define REG_AXXX_CP_CSQ_RB_STAT					0x000001fd
+#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK				0x0000007f
+#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT				0
+static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK				0x007f0000
+#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT				16
+static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_CSQ_IB1_STAT				0x000001fe
+#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK				0x0000007f
+#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT			0
+static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK				0x007f0000
+#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT			16
+static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_CSQ_IB2_STAT				0x000001ff
+#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK				0x0000007f
+#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT			0
+static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK				0x007f0000
+#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT			16
+static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
+{
+	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_SCRATCH_REG0				0x00000578
+
+#define REG_AXXX_CP_SCRATCH_REG1				0x00000579
+
+#define REG_AXXX_CP_SCRATCH_REG2				0x0000057a
+
+#define REG_AXXX_CP_SCRATCH_REG3				0x0000057b
+
+#define REG_AXXX_CP_SCRATCH_REG4				0x0000057c
+
+#define REG_AXXX_CP_SCRATCH_REG5				0x0000057d
+
+#define REG_AXXX_CP_SCRATCH_REG6				0x0000057e
+
+#define REG_AXXX_CP_SCRATCH_REG7				0x0000057f
+
+#define REG_AXXX_CP_ME_CF_EVENT_SRC				0x0000060a
+
+#define REG_AXXX_CP_ME_CF_EVENT_ADDR				0x0000060b
+
+#define REG_AXXX_CP_ME_CF_EVENT_DATA				0x0000060c
+
+#define REG_AXXX_CP_ME_NRT_ADDR					0x0000060d
+
+#define REG_AXXX_CP_ME_NRT_DATA					0x0000060e
+
 
 #endif /* ADRENO_COMMON_XML */

src/gallium/drivers/freedreno/adreno_pm4.xml.h

@@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml                (  42578 bytes, from 2013-06-02 13:10:46)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

src/gallium/drivers/freedreno/freedreno_context.c

@@ -86,7 +86,8 @@ fd_context_render(struct pipe_context *pctx)
 	ctx->gmem_reason = 0;
 	ctx->num_draws = 0;
 
-	fd_resource(pfb->cbufs[0]->texture)->dirty = false;
+	if (pfb->cbufs[0])
+		fd_resource(pfb->cbufs[0]->texture)->dirty = false;
 	if (pfb->zsbuf)
 		fd_resource(pfb->zsbuf->texture)->dirty = false;
 }

src/gallium/drivers/freedreno/freedreno_draw.c

@@ -104,7 +104,7 @@ fd_draw_emit(struct fd_context *ctx, const struct pipe_draw_info *info)
 			src_sel, idx_type, IGNORE_VISIBILITY));
 	OUT_RING(ring, info->count);       /* NumIndices */
 	if (info->indexed) {
-		OUT_RELOC(ring, idx_bo, idx_offset, 0);
+		OUT_RELOC(ring, idx_bo, idx_offset, 0, 0);
 		OUT_RING (ring, idx_size);
 	}
 }
@@ -193,8 +193,8 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
 	}
 
 	DBG("%x depth=%f, stencil=%u (%s/%s)", buffers, depth, stencil,
-			util_format_name(pfb->cbufs[0]->format),
-			pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
+		util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
+		util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 
 	ctx->clear(ctx, buffers, color, depth, stencil);
 

src/gallium/drivers/freedreno/freedreno_gmem.c

@@ -71,12 +71,16 @@ calculate_tiles(struct fd_context *ctx)
 {
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
 	struct pipe_scissor_state *scissor = &ctx->max_scissor;
-	uint32_t cpp = util_format_get_blocksize(ctx->framebuffer.cbufs[0]->format);
+	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 	uint32_t gmem_size = ctx->screen->gmemsize_bytes;
 	uint32_t minx, miny, width, height;
 	uint32_t nbins_x = 1, nbins_y = 1;
 	uint32_t bin_w, bin_h;
 	uint32_t max_width = 992;
+	uint32_t cpp = 4;
+
+	if (pfb->cbufs[0])
+		cpp = util_format_get_blocksize(pfb->cbufs[0]->format);
 
 	if ((gmem->cpp == cpp) &&
 			!memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
@@ -84,10 +88,17 @@ calculate_tiles(struct fd_context *ctx)
 		return;
 	}
 
-	minx = scissor->minx & ~31; /* round down to multiple of 32 */
-	miny = scissor->miny & ~31;
-	width = scissor->maxx - minx;
-	height = scissor->maxy - miny;
+	if (fd_mesa_debug & FD_DBG_DSCIS) {
+		minx = 0;
+		miny = 0;
+		width = pfb->width;
+		height = pfb->height;
+	} else {
+		minx = scissor->minx & ~31; /* round down to multiple of 32 */
+		miny = scissor->miny & ~31;
+		width = scissor->maxx - minx;
+		height = scissor->maxy - miny;
+	}
 
 // TODO we probably could optimize this a bit if we know that
 // Z or stencil is not enabled for any of the draw calls..
@@ -132,9 +143,7 @@ static void
 render_tiles(struct fd_context *ctx)
 {
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	uint32_t i, yoff = 0;
-
-	yoff= gmem->miny;
+	uint32_t i, yoff = gmem->miny;
 
 	ctx->emit_tile_init(ctx);
 
@@ -143,13 +152,13 @@ render_tiles(struct fd_context *ctx)
 		uint32_t bh = gmem->bin_h;
 
 		/* clip bin height: */
-		bh = MIN2(bh, gmem->height - yoff);
+		bh = MIN2(bh, gmem->miny + gmem->height - yoff);
 
 		for (j = 0; j < gmem->nbins_x; j++) {
 			uint32_t bw = gmem->bin_w;
 
 			/* clip bin width: */
-			bw = MIN2(bw, gmem->width - xoff);
+			bw = MIN2(bw, gmem->minx + gmem->width - xoff);
 
 			DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
 					bh, yoff, bw, xoff);
@@ -205,15 +214,15 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 
 	if (sysmem) {
 		DBG("rendering sysmem (%s/%s)",
-			util_format_name(pfb->cbufs[0]->format),
-			pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
+			util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
+			util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 		render_sysmem(ctx);
 	} else {
 		struct fd_gmem_stateobj *gmem = &ctx->gmem;
-		DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
-			util_format_name(pfb->cbufs[0]->format),
-			pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
 		calculate_tiles(ctx);
+		DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
+			util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
+			util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 		render_tiles(ctx);
 	}
 
@@ -225,7 +234,8 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 
 	/* update timestamps on render targets: */
 	timestamp = fd_ringbuffer_timestamp(ctx->ring);
-	fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
+	if (pfb->cbufs[0])
+		fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
 	if (pfb->zsbuf)
 		fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
 

src/gallium/drivers/freedreno/freedreno_resource.c

@@ -59,6 +59,9 @@ fd_resource_transfer_unmap(struct pipe_context *pctx,
 		struct pipe_transfer *ptrans)
 {
 	struct fd_context *ctx = fd_context(pctx);
+	struct fd_resource *rsc = fd_resource(ptrans->resource);
+	if (!(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED))
+		fd_bo_cpu_fini(rsc->bo);
 	pipe_resource_reference(&ptrans->resource, NULL);
 	util_slab_free(&ctx->transfer_pool, ptrans);
 }
@@ -74,12 +77,13 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 	struct fd_resource *rsc = fd_resource(prsc);
 	struct pipe_transfer *ptrans = util_slab_alloc(&ctx->transfer_pool);
 	enum pipe_format format = prsc->format;
+	uint32_t op = 0;
 	char *buf;
 
 	if (!ptrans)
 		return NULL;
 
-	/* util_slap_alloc() doesn't zero: */
+	/* util_slab_alloc() doesn't zero: */
 	memset(ptrans, 0, sizeof(*ptrans));
 
 	pipe_resource_reference(&ptrans->resource, prsc);
@@ -90,7 +94,8 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 	ptrans->layer_stride = ptrans->stride;
 
 	/* some state trackers (at least XA) don't do this.. */
-	fd_resource_transfer_flush_region(pctx, ptrans, box);
+	if (!(usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
+		fd_resource_transfer_flush_region(pctx, ptrans, box);
 
 	buf = fd_bo_map(rsc->bo);
 	if (!buf) {
@@ -98,6 +103,15 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 		return NULL;
 	}
 
+	if (usage & PIPE_TRANSFER_READ)
+		op |= DRM_FREEDRENO_PREP_READ;
+
+	if (usage & PIPE_TRANSFER_WRITE)
+		op |= DRM_FREEDRENO_PREP_WRITE;
+
+	if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED))
+		fd_bo_cpu_prep(rsc->bo, ctx->screen->pipe, op);
+
 	*pptrans = ptrans;
 
 	return buf +

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -60,6 +60,7 @@ static const struct debug_named_value debug_options[] = {
 		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
 		{"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
 		{"dgmem",     FD_DBG_DGMEM,  "Mark all state dirty after GMEM tile pass"},
+		{"dscis",     FD_DBG_DSCIS,  "Disable scissor optimization"},
 		DEBUG_NAMED_VALUE_END
 };
 
@@ -227,6 +228,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXEL_OFFSET:
 		return 7;
 
+	case PIPE_CAP_ENDIANNESS:
+		return PIPE_ENDIAN_LITTLE;
+
 	default:
 		DBG("unknown param %d", param);
 		return 0;

src/gallium/drivers/freedreno/freedreno_state.c

@@ -120,7 +120,7 @@ fd_set_framebuffer_state(struct pipe_context *pctx,
 	unsigned i;
 
 	DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx->needs_flush,
-			cso->cbufs[0], cso->zsbuf);
+			framebuffer->cbufs[0], framebuffer->zsbuf);
 
 	fd_context_render(pctx);
 

src/gallium/drivers/freedreno/freedreno_util.h

@@ -33,8 +33,10 @@
 #include <freedreno_ringbuffer.h>
 
 #include "pipe/p_format.h"
+#include "pipe/p_state.h"
 #include "util/u_debug.h"
 #include "util/u_math.h"
+#include "util/u_half.h"
 
 #include "adreno_common.xml.h"
 #include "adreno_pm4.xml.h"
@@ -47,10 +49,11 @@ enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
 enum adreno_stencil_op fd_stencil_op(unsigned op);
 
 
-#define FD_DBG_MSGS   0x1
-#define FD_DBG_DISASM 0x2
-#define FD_DBG_DCLEAR 0x4
-#define FD_DBG_DGMEM  0x8
+#define FD_DBG_MSGS     0x01
+#define FD_DBG_DISASM   0x02
+#define FD_DBG_DCLEAR   0x04
+#define FD_DBG_DGMEM    0x08
+#define FD_DBG_DSCIS    0x10
 extern int fd_mesa_debug;
 
 #define DBG(fmt, ...) \
@@ -77,6 +80,15 @@ static inline uint32_t DRAW(enum pc_di_primtype prim_type,
 			(1                 << 14);
 }
 
+
+static inline enum pipe_format
+pipe_surface_format(struct pipe_surface *psurf)
+{
+	if (!psurf)
+		return PIPE_FORMAT_NONE;
+	return psurf->format;
+}
+
 #define LOG_DWORDS 0
 
 
@@ -92,25 +104,36 @@ OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
 
 static inline void
 OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
-		uint32_t offset, uint32_t or)
-{
-	if (LOG_DWORDS) {
-		DBG("ring[%p]: OUT_RELOC  %04x:  %p+%u", ring,
-				(uint32_t)(ring->cur - ring->last_start), bo, offset);
-	}
-	fd_ringbuffer_emit_reloc(ring, bo, offset, or);
-}
-
-/* shifted reloc: */
-static inline void
-OUT_RELOCS(struct fd_ringbuffer *ring, struct fd_bo *bo,
 		uint32_t offset, uint32_t or, int32_t shift)
 {
 	if (LOG_DWORDS) {
-		DBG("ring[%p]: OUT_RELOCS  %04x:  %p+%u << %d", ring,
+		DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
 				(uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
 	}
-	fd_ringbuffer_emit_reloc_shift(ring, bo, offset, or, shift);
+	fd_ringbuffer_reloc(ring, &(struct fd_reloc){
+		.bo = bo,
+		.flags = FD_RELOC_READ,
+		.offset = offset,
+		.or = or,
+		.shift = shift,
+	});
+}
+
+static inline void
+OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
+		uint32_t offset, uint32_t or, int32_t shift)
+{
+	if (LOG_DWORDS) {
+		DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
+				(uint32_t)(ring->cur - ring->last_start), bo, offset, shift);
+	}
+	fd_ringbuffer_reloc(ring, &(struct fd_reloc){
+		.bo = bo,
+		.flags = FD_RELOC_READ | FD_RELOC_WRITE,
+		.offset = offset,
+		.or = or,
+		.shift = shift,
+	});
 }
 
 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
@@ -143,7 +166,7 @@ OUT_IB(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
 		struct fd_ringmarker *end)
 {
 	OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
-	fd_ringbuffer_emit_reloc_ring(ring, start);
+	fd_ringbuffer_emit_reloc_ring(ring, start, end);
 	OUT_RING(ring, fd_ringmarker_dwords(start, end));
 }
 

src/gallium/drivers/i915/i915_screen.c

@@ -263,6 +263,8 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
       return 0;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_LITTLE;
 
    default:
       debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);

src/gallium/drivers/ilo/ilo_screen.c

@@ -421,6 +421,8 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 1 << 27;
    case PIPE_CAP_MAX_VIEWPORTS:
       return ILO_MAX_VIEWPORTS;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_LITTLE;
 
    default:
       return 0;

src/gallium/drivers/llvmpipe/lp_bld_depth.c

@@ -836,7 +836,7 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
    LLVMValueRef stencil_vals = NULL;
    LLVMValueRef z_bitmask = NULL, stencil_shift = NULL;
    LLVMValueRef z_pass = NULL, s_pass_mask = NULL;
-   LLVMValueRef orig_mask = lp_build_mask_value(mask);
+   LLVMValueRef current_mask = lp_build_mask_value(mask);
    LLVMValueRef front_facing = NULL;
    boolean have_z, have_s;
 
@@ -984,7 +984,7 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
 
       /* apply stencil-fail operator */
       {
-         LLVMValueRef s_fail_mask = lp_build_andnot(&s_bld, orig_mask, s_pass_mask);
+         LLVMValueRef s_fail_mask = lp_build_andnot(&s_bld, current_mask, s_pass_mask);
          stencil_vals = lp_build_stencil_op(&s_bld, stencil, S_FAIL_OP,
                                             stencil_refs, stencil_vals,
                                             s_fail_mask, front_facing);
@@ -1032,6 +1032,11 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
       /* compare src Z to dst Z, returning 'pass' mask */
       z_pass = lp_build_cmp(&z_bld, depth->func, z_src, z_dst);
 
+      /* mask off bits that failed stencil test */
+      if (s_pass_mask) {
+         current_mask = LLVMBuildAnd(builder, current_mask, s_pass_mask, "");
+      }
+
       if (!stencil[0].enabled) {
          /* We can potentially skip all remaining operations here, but only
           * if stencil is disabled because we still need to update the stencil
@@ -1041,25 +1046,19 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
 
          if (do_branch) {
             lp_build_mask_check(mask);
-            do_branch = FALSE;
          }
       }
 
       if (depth->writemask) {
-         LLVMValueRef zselectmask;
+         LLVMValueRef z_pass_mask;
 
          /* mask off bits that failed Z test */
-         zselectmask = LLVMBuildAnd(builder, orig_mask, z_pass, "");
-
-         /* mask off bits that failed stencil test */
-         if (s_pass_mask) {
-            zselectmask = LLVMBuildAnd(builder, zselectmask, s_pass_mask, "");
-         }
+         z_pass_mask = LLVMBuildAnd(builder, current_mask, z_pass, "");
 
          /* Mix the old and new Z buffer values.
           * z_dst[i] = zselectmask[i] ? z_src[i] : z_dst[i]
           */
-         z_dst = lp_build_select(&z_bld, zselectmask, z_src, z_dst);
+         z_dst = lp_build_select(&z_bld, z_pass_mask, z_src, z_dst);
       }
 
       if (stencil[0].enabled) {
@@ -1067,13 +1066,13 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
          LLVMValueRef z_fail_mask, z_pass_mask;
 
          /* apply Z-fail operator */
-         z_fail_mask = lp_build_andnot(&s_bld, orig_mask, z_pass);
+         z_fail_mask = lp_build_andnot(&s_bld, current_mask, z_pass);
          stencil_vals = lp_build_stencil_op(&s_bld, stencil, Z_FAIL_OP,
                                             stencil_refs, stencil_vals,
                                             z_fail_mask, front_facing);
 
          /* apply Z-pass operator */
-         z_pass_mask = LLVMBuildAnd(builder, orig_mask, z_pass, "");
+         z_pass_mask = LLVMBuildAnd(builder, current_mask, z_pass, "");
          stencil_vals = lp_build_stencil_op(&s_bld, stencil, Z_PASS_OP,
                                             stencil_refs, stencil_vals,
                                             z_pass_mask, front_facing);
@@ -1083,7 +1082,7 @@ lp_build_depth_stencil_test(struct gallivm_state *gallivm,
       /* No depth test: apply Z-pass operator to stencil buffer values which
        * passed the stencil test.
        */
-      s_pass_mask = LLVMBuildAnd(builder, orig_mask, s_pass_mask, "");
+      s_pass_mask = LLVMBuildAnd(builder, current_mask, s_pass_mask, "");
       stencil_vals = lp_build_stencil_op(&s_bld, stencil, Z_PASS_OP,
                                          stencil_refs, stencil_vals,
                                          s_pass_mask, front_facing);

src/gallium/drivers/llvmpipe/lp_screen.c

@@ -231,6 +231,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 0;
    case PIPE_CAP_MAX_VIEWPORTS:
       return PIPE_MAX_VIEWPORTS;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_NATIVE;
    }
    /* should only get here on unhandled cases */
    debug_printf("Unexpected PIPE_CAP %d query\n", param);

src/gallium/drivers/nouveau/nouveau_buffer.c

@@ -289,6 +289,7 @@ nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf)
    tx.base.box.x = 0;
    tx.base.box.width = buf->base.width0;
    tx.bo = NULL;
+   tx.map = NULL;
 
    if (!buf->data)
       if (!nouveau_buffer_malloc(buf))
@@ -690,6 +691,7 @@ nouveau_buffer_migrate(struct nouveau_context *nv,
       tx.base.box.x = 0;
       tx.base.box.width = buf->base.width0;
       tx.bo = NULL;
+      tx.map = NULL;
       if (!nouveau_transfer_staging(nv, &tx, FALSE))
          return FALSE;
       nouveau_transfer_write(nv, &tx, 0, tx.base.box.width);

src/gallium/drivers/nv30/nv30_context.c

@@ -208,7 +208,7 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv)
    /*XXX: *cough* per-context pushbufs */
    push = screen->base.pushbuf;
    nv30->base.pushbuf = push;
-   nv30->base.pushbuf->user_priv = push->user_priv; /* hack at validate time */
+   nv30->base.pushbuf->user_priv = &nv30->bufctx; /* hack at validate time */
    nv30->base.pushbuf->rsvd_kick = 16; /* hack in screen before first space */
    nv30->base.pushbuf->kick_notify = nv30_context_kick_notify;
 

src/gallium/drivers/nv30/nv30_format.c

@@ -111,9 +111,6 @@ nv30_format_info_table[PIPE_FORMAT_COUNT] = {
    _(R16G16_SNORM        , __V_),
    _(R16G16B16_SNORM     , __V_),
    _(R16G16B16A16_SNORM  , __V_),
-   _(R8_USCALED          , __V_),
-   _(R8G8_USCALED        , __V_),
-   _(R8G8B8_USCALED      , __V_),
    _(R8G8B8A8_USCALED    , __V_),
    _(R16_FLOAT           , __V_),
    _(R16G16_FLOAT        , __V_), //S_V_),
@@ -160,9 +157,6 @@ nv30_vtxfmt_table[PIPE_FORMAT_COUNT] = {
    _(R8G8_UNORM          , U8_UNORM   , 2),
    _(R8G8B8_UNORM        , U8_UNORM   , 3),
    _(R8G8B8A8_UNORM      , U8_UNORM   , 4),
-   _(R8_USCALED          , U8_USCALED , 1),
-   _(R8G8_USCALED        , U8_USCALED , 2),
-   _(R8G8B8_USCALED      , U8_USCALED , 3),
    _(R8G8B8A8_USCALED    , U8_USCALED , 4),
    _(R16_SNORM           , V16_SNORM  , 1),
    _(R16G16_SNORM        , V16_SNORM  , 2),

src/gallium/drivers/nv30/nv30_screen.c

@@ -113,6 +113,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_BARRIER:
    case PIPE_CAP_SEAMLESS_CUBE_MAP:
    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+   case PIPE_CAP_CUBE_MAP_ARRAY:
    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
@@ -130,6 +131,8 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
       return 1;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_LITTLE;
    default:
       debug_printf("unknown param %d\n", param);
       return 0;

src/gallium/drivers/nv30/nv30_vbo.c

@@ -40,13 +40,15 @@ nv30_emit_vtxattr(struct nv30_context *nv30, struct pipe_vertex_buffer *vb,
    const unsigned nc = util_format_get_nr_components(ve->src_format);
    struct nouveau_pushbuf *push = nv30->base.pushbuf;
    struct nv04_resource *res = nv04_resource(vb->buffer);
+   const struct util_format_description *desc =
+      util_format_description(ve->src_format);
    const void *data;
    float v[4];
 
    data = nouveau_resource_map_offset(&nv30->base, res, vb->buffer_offset +
                                       ve->src_offset, NOUVEAU_BO_RD);
 
-   util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
+   desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
 
    switch (nc) {
    case 4:

src/gallium/drivers/nv30/nvfx_fragprog.c

@@ -976,9 +976,8 @@ nvfx_fragprog_assign_generic(struct nv30_context *nvfx, struct nvfx_fpc *fpc,
             fpc->r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw);
             return TRUE;
          }
-         return FALSE;
       }
-      return TRUE;
+      return FALSE;
    default:
       return TRUE;
    }

src/gallium/drivers/nv50/nv50_screen.c

@@ -189,6 +189,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return 0;
    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_LITTLE;
    default:
       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
       return 0;

src/gallium/drivers/nv50/nv50_stateobj.h

@@ -40,7 +40,7 @@ struct nv50_constbuf {
       const uint8_t *data;
    } u;
    uint32_t size; /* max 65536 */
-   uint16_t offset;
+   uint32_t offset;
    boolean user; /* should only be TRUE if u.data is valid and non-NULL */
 };
 

src/gallium/drivers/nv50/nv50_vbo.c

@@ -140,10 +140,20 @@ nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
    float v[4];
    const unsigned nc = util_format_get_nr_components(ve->src_format);
+   const struct util_format_description *desc =
+      util_format_description(ve->src_format);
 
    assert(vb->user_buffer);
 
-   util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
+   if (desc->channel[0].pure_integer) {
+      if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
+         desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
+      } else {
+         desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
+      }
+   } else {
+      desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
+   }
 
    switch (nc) {
    case 4:

src/gallium/drivers/nv50/nv84_video.c

@@ -624,17 +624,13 @@ nv84_video_buffer_create(struct pipe_context *pipe,
    union nouveau_bo_config cfg;
    unsigned bo_size;
 
-   if (getenv("XVMC_VL"))
+   if (getenv("XVMC_VL") || template->buffer_format != PIPE_FORMAT_NV12)
       return vl_video_buffer_create(pipe, template);
 
    if (!template->interlaced) {
       debug_printf("Require interlaced video buffers\n");
       return NULL;
    }
-   if (template->buffer_format != PIPE_FORMAT_NV12) {
-      debug_printf("Must use NV12 format\n");
-      return NULL;
-   }
    if (template->chroma_format != PIPE_VIDEO_CHROMA_FORMAT_420) {
       debug_printf("Must use 4:2:0 format\n");
       return NULL;

src/gallium/drivers/nv50/nv84_video_bsp.c

@@ -136,12 +136,11 @@ nv84_decoder_bsp(struct nv84_decoder *dec,
    params.iseqparm.chroma_format_idc = 1;
 
    params.iseqparm.pic_width_in_mbs_minus1 = mb(dec->base.width) - 1;
-   if (desc->field_pic_flag)
+   if (desc->field_pic_flag || desc->mb_adaptive_frame_field_flag)
       params.iseqparm.pic_height_in_map_units_minus1 = mb_half(dec->base.height) - 1;
    else
       params.iseqparm.pic_height_in_map_units_minus1 = mb(dec->base.height) - 1;
 
-   /* TODO: interlaced still doesn't work, maybe due to ref frame management. */
    if (desc->bottom_field_flag)
       params.ipicparm.curr_pic_order_cnt = desc->field_order_cnt[1];
    else

src/gallium/drivers/nv50/nv84_video_vp.c

@@ -39,10 +39,10 @@ struct h264_iparm1 {
    uint32_t h1; // 1fc
    uint32_t h2; // 200
    uint32_t h3; // 204
-   uint32_t unk208;
-   uint32_t field_pic_flag;
-   uint32_t format;
-   uint32_t unk214;
+   uint32_t mb_adaptive_frame_field_flag; // 208
+   uint32_t field_pic_flag; // 20c
+   uint32_t format; // 210
+   uint32_t unk214; // 214
 };
 
 struct h264_iparm2 {
@@ -56,7 +56,7 @@ struct h264_iparm2 {
    uint32_t h2; // 1c
    uint32_t h3; // 20
    uint32_t unk24;
-   uint32_t unk28;
+   uint32_t mb_adaptive_frame_field_flag; // 28
    uint32_t top; // 2c
    uint32_t bottom; // 30
    uint32_t is_reference; // 34
@@ -100,6 +100,7 @@ nv84_decoder_vp_h264(struct nv84_decoder *dec,
    param1.height = param1.h2 = height;
    param1.h1 = param1.h3 = align(height, 32);
    param1.format = 0x3231564e; /* 'NV12' */
+   param1.mb_adaptive_frame_field_flag = desc->mb_adaptive_frame_field_flag;
    param1.field_pic_flag = desc->field_pic_flag;
 
    param2.width = width;
@@ -115,6 +116,7 @@ nv84_decoder_vp_h264(struct nv84_decoder *dec,
       param2.top = desc->bottom_field_flag ? 2 : 1;
       param2.bottom = desc->bottom_field_flag;
    }
+   param2.mb_adaptive_frame_field_flag = desc->mb_adaptive_frame_field_flag;
    param2.is_reference = desc->is_reference;
 
    PUSH_SPACE(push, 5 + 16 + 3 + 2 + 6 + (is_ref ? 2 : 0) + 3 + 2 + 4 + 2);

src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp

@@ -441,6 +441,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
          if (i->op == OP_TEXBAR) {
             if (i->subOp >= max) {
                delete_Instruction(prog, i);
+               i = NULL;
             } else {
                max = i->subOp;
                if (prev && prev->op == OP_TEXBAR && prev->subOp >= max) {
@@ -452,7 +453,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
          if (isTextureOp(i->op)) {
             max++;
          }
-         if (!i->isNop())
+         if (i && !i->isNop())
             prev = i;
       }
    }

src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp

@@ -337,6 +337,11 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
          // (except if we implement more constraints)
          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
             return false;
+      } else
+      if (i->op == OP_ADD && i->sType == TYPE_F32) {
+         // add f32 LIMM cannot saturate
+         if (i->saturate && (reg.data.u32 & 0xfff))
+            return false;
       }
    }
 
@@ -431,6 +436,13 @@ TargetNVC0::isSatSupported(const Instruction *insn) const
    if (insn->dType == TYPE_U32)
       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
 
+   // add f32 LIMM cannot saturate
+   if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
+      if (insn->getSrc(1)->asImm() &&
+          insn->getSrc(1)->reg.data.u32 & 0xfff)
+         return false;
+   }
+
    return insn->dType == TYPE_F32;
 }
 

src/gallium/drivers/nvc0/nvc0_context.c

@@ -111,6 +111,7 @@ nvc0_destroy(struct pipe_context *pipe)
    nouveau_pushbuf_kick(nvc0->base.pushbuf, nvc0->base.pushbuf->channel);
 
    nvc0_context_unreference_resources(nvc0);
+   nvc0_blitctx_destroy(nvc0);
 
 #ifdef NVC0_WITH_DRAW_MODULE
    draw_destroy(nvc0->draw);

src/gallium/drivers/nvc0/nvc0_context.h

@@ -96,6 +96,7 @@
 struct nvc0_blitctx;
 
 boolean nvc0_blitctx_create(struct nvc0_context *);
+void nvc0_blitctx_destroy(struct nvc0_context *);
 
 struct nvc0_context {
    struct nouveau_context base;
@@ -197,6 +198,7 @@ struct nvc0_context {
    struct pipe_surface *surfaces[2][NVC0_MAX_SURFACE_SLOTS];
    uint16_t surfaces_dirty[2];
    uint16_t surfaces_valid[2];
+   uint32_t vport_int[2];
 
    struct util_dynarray global_residents;
 

src/gallium/drivers/nvc0/nvc0_screen.c

@@ -179,6 +179,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return 1;
    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
+   case PIPE_CAP_ENDIANNESS:
+      return PIPE_ENDIAN_LITTLE;
    default:
       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
       return 0;
@@ -369,6 +371,7 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
    nouveau_object_del(&screen->eng3d);
    nouveau_object_del(&screen->eng2d);
    nouveau_object_del(&screen->m2mf);
+   nouveau_object_del(&screen->compute);
 
    nouveau_screen_fini(&screen->base);
 
@@ -510,6 +513,7 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
    }
 
    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
+   size  = align(size, 0x8000);
    size *= screen->mp_count;
 
    size = align(size, 1 << 17);

src/gallium/drivers/nvc0/nvc0_state_validate.c

@@ -245,9 +245,11 @@ nvc0_validate_viewport(struct nvc0_context *nvc0)
     zmin = vp->translate[2] - fabsf(vp->scale[2]);
     zmax = vp->translate[2] + fabsf(vp->scale[2]);
 
+    nvc0->vport_int[0] = (w << 16) | x;
+    nvc0->vport_int[1] = (h << 16) | y;
     BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
-    PUSH_DATA (push, (w << 16) | x);
-    PUSH_DATA (push, (h << 16) | y);
+    PUSH_DATA (push, nvc0->vport_int[0]);
+    PUSH_DATA (push, nvc0->vport_int[1]);
     BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
     PUSH_DATAf(push, zmin);
     PUSH_DATAf(push, zmax);

src/gallium/drivers/nvc0/nvc0_stateobj.h

@@ -38,7 +38,7 @@ struct nvc0_constbuf {
       const void *data;
    } u;
    uint32_t size;
-   uint16_t offset;
+   uint32_t offset;
    boolean user; /* should only be TRUE if u.data is valid and non-NULL */
 };
 

src/gallium/drivers/nvc0/nvc0_surface.c

@@ -948,8 +948,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    /* restore viewport */
 
    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
-   PUSH_DATA (push, nvc0->framebuffer.width << 16);
-   PUSH_DATA (push, nvc0->framebuffer.height << 16);
+   PUSH_DATA (push, nvc0->vport_int[0]);
+   PUSH_DATA (push, nvc0->vport_int[1]);
    IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 }
 
@@ -1246,6 +1246,13 @@ nvc0_blitctx_create(struct nvc0_context *nvc0)
    return TRUE;
 }
 
+void
+nvc0_blitctx_destroy(struct nvc0_context *nvc0)
+{
+   if (nvc0->blit)
+      FREE(nvc0->blit);
+}
+
 void
 nvc0_init_surface_functions(struct nvc0_context *nvc0)
 {

src/gallium/drivers/nvc0/nvc0_video.c

@@ -153,7 +153,7 @@ static void nvc0_video_getpath(enum pipe_video_profile profile, char *path)
          break;
       }
       case PIPE_VIDEO_CODEC_VC1: {
-         sprintf(path, "/lib/firmware/nouveau/vuc-vc1-%u", profile - PIPE_VIDEO_PROFILE_VC1_SIMPLE);
+         sprintf(path, "/lib/firmware/nouveau/vuc-vc1-0");
          break;
       }
       case PIPE_VIDEO_CODEC_MPEG4_AVC: {

src/gallium/drivers/nvc0/nve4_compute.c

@@ -78,11 +78,11 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
     */
    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
-   PUSH_DATA (push, screen->tls->size / screen->mp_count);
+   PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
    PUSH_DATA (push, 0xff);
    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
-   PUSH_DATA (push, screen->tls->size / screen->mp_count);
+   PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
    PUSH_DATA (push, 0xff);
 
    /* Unified address space ? Who needs that ? Certainly not OpenCL.

src/gallium/drivers/r300/Makefile.am

@@ -18,7 +18,8 @@ AM_CFLAGS = \
 	$(RADEON_CFLAGS)
 
 r300_compiler_tests_LDADD = libr300.la libr300-helper.la \
-	$(top_builddir)/src/gallium/auxiliary/libgallium.la
+	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
+	$(GALLIUM_DRI_LIB_DEPS)
 r300_compiler_tests_CPPFLAGS = \
 	-I$(top_srcdir)/src/gallium/drivers/r300/compiler
 r300_compiler_tests_SOURCES = \

src/gallium/drivers/r300/compiler/tests/radeon_compiler_optimize_tests.c

@@ -80,7 +80,7 @@ static void test_runner_rc_optimize(struct test_result * result)
 
 unsigned radeon_compiler_optimize_run_tests()
 {
-	struct test tests[] = {
+	static struct test tests[] = {
 		{"rc_optimize() => peephole_mul_omod()", test_runner_rc_optimize},
 		{NULL, NULL}
 	};

src/gallium/drivers/r300/compiler/tests/radeon_compiler_regalloc_tests.c

@@ -91,8 +91,8 @@ static void tex_1d_swizzle(struct test_result *result)
 
 unsigned radeon_compiler_regalloc_run_tests()
 {
-	struct test tests[] = {
-		{"rc_pair_regalloc() => TEX 1D Swizzle - r300", tex_1d_swizzle},
+	static struct test tests[] = {
+		{"rc_pair_regalloc() => TEX 1D Swizzle - r300", tex_1d_swizzle },
 		{NULL, NULL}
 	};
 	return run_tests(tests);

src/gallium/drivers/r300/compiler/tests/radeon_compiler_util_tests.c

@@ -96,7 +96,7 @@ static void test_runner_rc_inst_can_use_presub(struct test_result * result)
 
 unsigned radeon_compiler_util_run_tests()
 {
-	struct test tests[] = {
+	static struct test tests[] = {
 		{"rc_inst_can_use_presub()", test_runner_rc_inst_can_use_presub},
 		{NULL, NULL}
 	};

src/gallium/drivers/r300/r300_screen.c

@@ -104,7 +104,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
         case PIPE_CAP_USER_INDEX_BUFFERS:
         case PIPE_CAP_USER_CONSTANT_BUFFERS:
-        case PIPE_CAP_DEPTH_CLIP_DISABLE: /* XXX implemented, but breaks Regnum Online */
         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
             return 1;
 
@@ -138,6 +137,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
         case PIPE_CAP_INDEP_BLEND_ENABLE:
         case PIPE_CAP_INDEP_BLEND_FUNC:
+        case PIPE_CAP_DEPTH_CLIP_DISABLE:
         case PIPE_CAP_SHADER_STENCIL_EXPORT:
         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
         case PIPE_CAP_TGSI_INSTANCEID:
@@ -190,6 +190,8 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         /* Render targets. */
         case PIPE_CAP_MAX_RENDER_TARGETS:
             return 4;
+	case PIPE_CAP_ENDIANNESS:
+            return PIPE_ENDIAN_LITTLE;
     }
     return 0;
 }

src/gallium/drivers/r300/r300_state.c

@@ -1333,8 +1333,7 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
 
     if (r300_screen(pipe->screen)->caps.has_tcl) {
        vap_clip_cntl = (state->clip_plane_enable & 63) |
-                       R300_PS_UCP_MODE_CLIP_AS_TRIFAN |
-                       (state->depth_clip ? 0 : R300_CLIP_DISABLE);
+                       R300_PS_UCP_MODE_CLIP_AS_TRIFAN;
     } else {
        vap_clip_cntl = R300_CLIP_DISABLE;
     }

src/gallium/drivers/r600/r600_hw_context.c

@@ -236,14 +236,21 @@ void r600_flush_emit(struct r600_context *rctx)
 	}
 
 	if (rctx->flags & R600_CONTEXT_INV_CONST_CACHE) {
-		cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1);
+		/* Direct constant addressing uses the shader cache.
+		 * Indirect contant addressing uses the vertex cache. */
+		cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
+				 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
+							 : S_0085F0_TC_ACTION_ENA(1));
 	}
 	if (rctx->flags & R600_CONTEXT_INV_VERTEX_CACHE) {
 		cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
 							: S_0085F0_TC_ACTION_ENA(1);
 	}
 	if (rctx->flags & R600_CONTEXT_INV_TEX_CACHE) {
-		cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
+		/* Textures use the texture cache.
+		 * Texture buffer objects use the vertex cache. */
+		cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
+				 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0);
 	}
 
 	/* Don't use the DB CP COHER logic on r6xx.

src/gallium/drivers/r600/r600_pipe.c

@@ -679,6 +679,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
 	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 		return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
+	case PIPE_CAP_ENDIANNESS:
+		return PIPE_ENDIAN_LITTLE;
 	}
 	return 0;
 }

src/gallium/drivers/r600/sb/sb_sched.cpp

@@ -1490,7 +1490,8 @@ unsigned post_scheduler::try_add_instruction(node *n) {
 
 		// FIXME workaround for some problems with MULADD in trans slot on r700,
 		// (is it really needed on r600?)
-		if (a->bc.op == ALU_OP3_MULADD && !ctx.is_egcm()) {
+		if ((a->bc.op == ALU_OP3_MULADD || a->bc.op == ALU_OP3_MULADD_IEEE) &&
+				!ctx.is_egcm()) {
 			allowed_slots &= 0x0F;
 		}
 

src/gallium/drivers/radeon/radeon_llvm_emit.c

@@ -124,7 +124,7 @@ unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_llvm_binary *binary,
 	r = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile, &err,
 								 &out_buffer);
 	if (r) {
-		fprintf(stderr, err);
+		fprintf(stderr, "%s", err);
 		FREE(err);
 		return 1;
 	}

src/gallium/drivers/radeonsi/r600_blit.c

@@ -322,6 +322,21 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
 	rtex->surface.level[0].npix_y = util_format_get_nblocksy(orig->format, orig->npix0_y);
 	rtex->surface.level[level].npix_x = util_format_get_nblocksx(orig->format, orig->npix_x);
 	rtex->surface.level[level].npix_y = util_format_get_nblocksy(orig->format, orig->npix_y);
+
+	/* By dividing the dimensions by 4, we effectively decrement
+	 * last_level by 2, therefore the last 2 mipmap levels disappear and
+	 * aren't blittable. Note that the last 3 mipmap levels (4x4, 2x2,
+	 * 1x1) have equal slice sizes, which is an important assumption
+	 * for this to work.
+	 *
+	 * In order to make the last 2 mipmap levels blittable, we have to
+	 * add the slice size of the last mipmap level to the texture
+	 * address, so that even though the hw thinks it reads last_level-2,
+	 * it will actually read last_level-1, and if we add the slice size*2,
+	 * it will read last_level. That's how this workaround works.
+	 */
+	if (level > rtex->resource.b.b.last_level-2)
+		rtex->mipmap_shift = level - (rtex->resource.b.b.last_level-2);
 }
 
 static void r600_change_format(struct pipe_resource *tex,
@@ -355,6 +370,7 @@ static void r600_reset_blittable_to_orig(struct pipe_resource *tex,
 	rtex->surface.level[0].npix_y = orig->npix0_y;
 	rtex->surface.level[level].npix_x = orig->npix_x;
 	rtex->surface.level[level].npix_y = orig->npix_y;
+	rtex->mipmap_shift = 0;
 }
 
 static void r600_resource_copy_region(struct pipe_context *ctx,

src/gallium/drivers/radeonsi/r600_resource.h

@@ -53,6 +53,8 @@ struct r600_resource_texture {
 	struct r600_resource_texture	*flushed_depth_texture;
 	boolean				is_flushing_texture;
 	struct radeon_surface		surface;
+
+	unsigned mipmap_shift;
 };
 
 struct r600_surface {

src/gallium/drivers/radeonsi/radeonsi_pipe.c

@@ -298,11 +298,15 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
 		case CHIP_PITCAIRN: return "pitcairn";
 		case CHIP_VERDE: return "verde";
 		case CHIP_OLAND: return "oland";
+#if HAVE_LLVM <= 0x0303
+		default: return "SI";
+#else
 		case CHIP_HAINAN: return "hainan";
 		case CHIP_BONAIRE: return "bonaire";
 		case CHIP_KABINI: return "kabini";
 		case CHIP_KAVERI: return "kaveri";
 		default: return "";
+#endif
 	}
 }
 
@@ -440,6 +444,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
 	case PIPE_CAP_MAX_TEXEL_OFFSET:
 		return 7;
+	case PIPE_CAP_ENDIANNESS:
+		return PIPE_ENDIAN_LITTLE;
 	}
 	return 0;
 }

src/gallium/drivers/radeonsi/radeonsi_shader.c

@@ -198,6 +198,8 @@ static void declare_input_fs(
 	struct si_shader *shader = &si_shader_ctx->shader->shader;
 	struct lp_build_context * base =
 				&si_shader_ctx->radeon_bld.soa.bld_base.base;
+	struct lp_build_context *uint =
+				&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
 	struct gallivm_state * gallivm = base->gallivm;
 	LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
 	LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
@@ -341,6 +343,22 @@ static void declare_input_fs(
 		}
 
 		shader->ninterp++;
+	} else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
+		LLVMValueRef args[4];
+
+		args[0] = uint->zero;
+		args[1] = attr_number;
+		args[2] = params;
+		args[3] = interp_param;
+		si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
+			build_intrinsic(base->gallivm->builder, intr_name,
+						input_type, args, args[3] ? 4 : 3,
+						LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+		si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
+		si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
+			lp_build_const_float(gallivm, 0.0f);
+		si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
+			lp_build_const_float(gallivm, 1.0f);
 	} else {
 		for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 			LLVMValueRef args[4];
@@ -562,12 +580,11 @@ static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
 }
 
 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
-				    unsigned index)
+				    LLVMValueRef (*pos)[9], unsigned index)
 {
 	struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
 	struct lp_build_context *base = &bld_base->base;
 	struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
-	LLVMValueRef args[9];
 	unsigned reg_index;
 	unsigned chan;
 	unsigned const_chan;
@@ -582,6 +599,8 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
 	}
 
 	for (reg_index = 0; reg_index < 2; reg_index ++) {
+		LLVMValueRef *args = pos[2 + reg_index];
+
 		args[5] =
 		args[6] =
 		args[7] =
@@ -612,10 +631,6 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
 		args[3] = lp_build_const_int32(base->gallivm,
 					       V_008DFC_SQ_EXP_POS + 2 + reg_index);
 		args[4] = uint->zero;
-		lp_build_intrinsic(base->gallivm->builder,
-				   "llvm.SI.export",
-				   LLVMVoidTypeInContext(base->gallivm->context),
-				   args, 9);
 	}
 }
 
@@ -630,17 +645,18 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 	struct tgsi_parse_context *parse = &si_shader_ctx->parse;
 	LLVMValueRef args[9];
 	LLVMValueRef last_args[9] = { 0 };
+	LLVMValueRef pos_args[4][9] = { { 0 } };
 	unsigned semantic_name;
 	unsigned color_count = 0;
 	unsigned param_count = 0;
 	int depth_index = -1, stencil_index = -1;
+	int i;
 
 	while (!tgsi_parse_end_of_tokens(parse)) {
 		struct tgsi_full_declaration *d =
 					&parse->FullToken.FullDeclaration;
 		unsigned target;
 		unsigned index;
-		int i;
 
 		tgsi_parse_token(parse);
 
@@ -716,7 +732,7 @@ handle_semantic:
 				target = V_008DFC_SQ_EXP_POS + 2 + d->Semantic.Index;
 				break;
 			case TGSI_SEMANTIC_CLIPVERTEX:
-				si_llvm_emit_clipvertex(bld_base, index);
+				si_llvm_emit_clipvertex(bld_base, pos_args, index);
 				shader->clip_dist_write = 0xFF;
 				continue;
 			case TGSI_SEMANTIC_FOG:
@@ -734,9 +750,13 @@ handle_semantic:
 
 			si_llvm_init_export_args(bld_base, d, index, target, args);
 
-			if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
-			    (semantic_name == TGSI_SEMANTIC_POSITION) :
-			    (semantic_name == TGSI_SEMANTIC_COLOR)) {
+			if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
+			    target >= V_008DFC_SQ_EXP_POS &&
+			    target <= (V_008DFC_SQ_EXP_POS + 3)) {
+				memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
+				       args, sizeof(args));
+			} else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT &&
+				   semantic_name == TGSI_SEMANTIC_COLOR) {
 				if (last_args[0]) {
 					lp_build_intrinsic(base->gallivm->builder,
 							   "llvm.SI.export",
@@ -784,7 +804,10 @@ handle_semantic:
 			args[7] =
 			args[8] =
 			args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
-			mask |= 0x2;
+			/* Only setting the stencil component bit (0x2) here
+			 * breaks some stencil piglit tests
+			 */
+			mask |= 0x3;
 
 			if (depth_index < 0)
 				args[5] = args[6];
@@ -806,66 +829,87 @@ handle_semantic:
 			memcpy(last_args, args, sizeof(args));
 	}
 
-	if (!last_args[0]) {
-		assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
+	if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+		unsigned pos_idx = 0;
 
-		/* Specify which components to enable */
-		last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
+		for (i = 0; i < 4; i++)
+			if (pos_args[i][0])
+				shader->nr_pos_exports++;
 
-		/* Specify the target we are exporting */
-		last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+		for (i = 0; i < 4; i++) {
+			if (!pos_args[i][0])
+				continue;
 
-		/* Set COMPR flag to zero to export data as 32-bit */
-		last_args[4] = uint->zero;
-
-		/* dummy bits */
-		last_args[5]= uint->zero;
-		last_args[6]= uint->zero;
-		last_args[7]= uint->zero;
-		last_args[8]= uint->zero;
-
-		si_shader_ctx->shader->spi_shader_col_format |=
-			V_028714_SPI_SHADER_32_ABGR;
-		si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
-	}
-
-	/* Specify whether the EXEC mask represents the valid mask */
-	last_args[1] = lp_build_const_int32(base->gallivm,
-					    si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
-
-	if (shader->fs_write_all && shader->nr_cbufs > 1) {
-		int i;
-
-		/* Specify that this is not yet the last export */
-		last_args[2] = lp_build_const_int32(base->gallivm, 0);
-
-		for (i = 1; i < shader->nr_cbufs; i++) {
 			/* Specify the target we are exporting */
-			last_args[3] = lp_build_const_int32(base->gallivm,
-							    V_008DFC_SQ_EXP_MRT + i);
+			pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
+
+			if (pos_idx == shader->nr_pos_exports)
+				/* Specify that this is the last export */
+				pos_args[i][2] = uint->one;
 
 			lp_build_intrinsic(base->gallivm->builder,
 					   "llvm.SI.export",
 					   LLVMVoidTypeInContext(base->gallivm->context),
-					   last_args, 9);
+					   pos_args[i], 9);
+		}
+	} else {
+		if (!last_args[0]) {
+			/* Specify which components to enable */
+			last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
+
+			/* Specify the target we are exporting */
+			last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+
+			/* Set COMPR flag to zero to export data as 32-bit */
+			last_args[4] = uint->zero;
+
+			/* dummy bits */
+			last_args[5]= uint->zero;
+			last_args[6]= uint->zero;
+			last_args[7]= uint->zero;
+			last_args[8]= uint->zero;
 
 			si_shader_ctx->shader->spi_shader_col_format |=
-				si_shader_ctx->shader->spi_shader_col_format << 4;
-			si_shader_ctx->shader->cb_shader_mask |=
-				si_shader_ctx->shader->cb_shader_mask << 4;
+				V_028714_SPI_SHADER_32_ABGR;
+			si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
 		}
 
-		last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+		/* Specify whether the EXEC mask represents the valid mask */
+		last_args[1] = uint->one;
+
+		if (shader->fs_write_all && shader->nr_cbufs > 1) {
+			int i;
+
+			/* Specify that this is not yet the last export */
+			last_args[2] = lp_build_const_int32(base->gallivm, 0);
+
+			for (i = 1; i < shader->nr_cbufs; i++) {
+				/* Specify the target we are exporting */
+				last_args[3] = lp_build_const_int32(base->gallivm,
+								    V_008DFC_SQ_EXP_MRT + i);
+
+				lp_build_intrinsic(base->gallivm->builder,
+						   "llvm.SI.export",
+						   LLVMVoidTypeInContext(base->gallivm->context),
+						   last_args, 9);
+
+				si_shader_ctx->shader->spi_shader_col_format |=
+					si_shader_ctx->shader->spi_shader_col_format << 4;
+				si_shader_ctx->shader->cb_shader_mask |=
+					si_shader_ctx->shader->cb_shader_mask << 4;
+			}
+
+			last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+		}
+
+		/* Specify that this is the last export */
+		last_args[2] = lp_build_const_int32(base->gallivm, 1);
+
+		lp_build_intrinsic(base->gallivm->builder,
+				   "llvm.SI.export",
+				   LLVMVoidTypeInContext(base->gallivm->context),
+				   last_args, 9);
 	}
-
-	/* Specify that this is the last export */
-	last_args[2] = lp_build_const_int32(base->gallivm, 1);
-
-	lp_build_intrinsic(base->gallivm->builder,
-			   "llvm.SI.export",
-			   LLVMVoidTypeInContext(base->gallivm->context),
-			   last_args, 9);
-
 /* XXX: Look up what this function does */
 /*		ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
 }