android: enlarge cache_resources

The functions are already defined in the latest bionic.

CleanSpec.mk

@@ -0,0 +1,49 @@
+# Copyright (C) 2013 The Android-x86 Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# If you don't need to do a full clean build but would like to touch
+# a file or delete some intermediate files, add a clean step to the end
+# of the list.  These steps will only be run once, if they haven't been
+# run before.
+#
+# E.g.:
+#     $(call add-clean-step, touch -c external/sqlite/sqlite3.h)
+#     $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/STATIC_LIBRARIES/libz_intermediates)
+#
+# Always use "touch -c" and "rm -f" or "rm -rf" to gracefully deal with
+# files that are missing or have been moved.
+#
+# Use $(PRODUCT_OUT) to get to the "out/target/product/blah/" directory.
+# Use $(OUT_DIR) to refer to the "out" directory.
+#
+# If you need to re-do something that's already mentioned, just copy
+# the command and add it to the bottom of the list.  E.g., if a change
+# that you made last week required touching a file and a change you
+# made today requires touching the same file, just copy the old
+# touch step and add it to the end of the list.
+#
+# ************************************************
+# NEWER CLEAN STEPS MUST BE AT THE END OF THE LIST
+# ************************************************
+
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/STATIC_LIBRARIES/libmesa_*_intermediates)
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/libdrm_*intermediates)
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/i9?5_dri_intermediates)
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/libglapi_intermediates)
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/gralloc.drm_intermediates)
+$(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/libgralloc_drm_intermediates)
+$(call add-clean-step, rm -rf $(OUT_DIR)/host/$(HOST_OS)-$(HOST_ARCH)/obj/EXECUTABLES/mesa_*_intermediates)
+$(call add-clean-step, rm -rf $(OUT_DIR)/host/$(HOST_OS)-$(HOST_ARCH)/obj/EXECUTABLES/glsl_compiler_intermediates)
+$(call add-clean-step, rm -rf $(OUT_DIR)/host/$(HOST_OS)-$(HOST_ARCH)/obj/STATIC_LIBRARIES/libmesa_glsl_utils_intermediates)

include/GL/internal/dri_interface.h

@@ -983,6 +983,7 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_YUV410	0x39565559
 #define __DRI_IMAGE_FOURCC_YUV411	0x31315559
 #define __DRI_IMAGE_FOURCC_YUV420	0x32315559
+#define __DRI_IMAGE_FOURCC_YVU420	0x32315659
 #define __DRI_IMAGE_FOURCC_YUV422	0x36315559
 #define __DRI_IMAGE_FOURCC_YUV444	0x34325559
 #define __DRI_IMAGE_FOURCC_NV12		0x3231564e

src/egl/drivers/dri2/platform_android.c

@@ -38,6 +38,7 @@
 #include <xf86drm.h>
 #include <i915_drm.h>
 #include <radeon_drm.h>
+#include <gralloc_drm.h>
 
 #include "egl_dri2.h"
 #include "gralloc_drm.h"
@@ -56,9 +57,9 @@ get_format_bpp(int native)
    case HAL_PIXEL_FORMAT_RGB_888:
       bpp = 3;
       break;
+   case HAL_PIXEL_FORMAT_DRM_NV12:
+   case HAL_PIXEL_FORMAT_YV12:
    case HAL_PIXEL_FORMAT_RGB_565:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       bpp = 2;
       break;
    default:
@@ -339,6 +340,7 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
    struct dri2_egl_image *dri2_img;
    int name;
+   uint32_t offsets[3], strides[3], handles[3], tmp;
    EGLint format;
 
    if (ctx != NULL) {
@@ -367,6 +369,12 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
 
    /* see the table in droid_add_configs_for_visuals */
    switch (buf->format) {
+   case HAL_PIXEL_FORMAT_DRM_NV12:
+       format = __DRI_IMAGE_FOURCC_NV12;
+       break;
+   case HAL_PIXEL_FORMAT_YV12:
+      format = __DRI_IMAGE_FOURCC_YVU420;
+      break;
    case HAL_PIXEL_FORMAT_BGRA_8888:
       format = __DRI_IMAGE_FORMAT_ARGB8888;
       break;
@@ -380,8 +388,6 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
       format = __DRI_IMAGE_FORMAT_XBGR8888;
       break;
    case HAL_PIXEL_FORMAT_RGB_888:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       /* unsupported */
    default:
       _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", buf->format);
@@ -400,6 +406,11 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
       return NULL;
    }
 
+   switch (format) {
+   case __DRI_IMAGE_FORMAT_ARGB8888:
+   case __DRI_IMAGE_FORMAT_RGB565:
+   case __DRI_IMAGE_FORMAT_ABGR8888:
+   case __DRI_IMAGE_FORMAT_XBGR8888:
        dri2_img->dri_image =
           dri2_dpy->image->createImageFromName(dri2_dpy->dri_screen,
                            buf->width,
@@ -408,6 +419,57 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
                            name,
                            buf->stride,
                            dri2_img);
+       break;
+   case __DRI_IMAGE_FOURCC_YVU420:
+       offsets[0] = offsets[1] = offsets[2] = 0;
+       strides[0] = strides[1] = strides[2] = 0;
+
+       gralloc_drm_resolve_format(buf->handle, &strides[0], &offsets[0],
+                                  &handles[0]);
+
+       /* u anv v are given in wrong order than what we need here thus this:*/
+       tmp = offsets[1];
+       offsets[1] = offsets[2];
+       offsets[2] = tmp;
+       tmp = strides[1];
+       strides[1] = strides[2];
+       strides[2] = tmp;
+
+       dri2_img->dri_image =
+          dri2_dpy->image->createImageFromNames(dri2_dpy->dri_screen,
+                           buf->width,
+                           buf->height,
+                           format,
+                           &name, 1,
+                           (int*)strides,
+                           (int*)offsets,
+                           dri2_img);
+       break;
+   case __DRI_IMAGE_FOURCC_NV12:
+       offsets[0] = offsets[1] = offsets[2] = 0;
+       strides[0] = strides[1] = strides[2] = 0;
+
+       gralloc_drm_resolve_format(buf->handle, &strides[0], &offsets[0],
+                                  &handles[0]);
+
+
+       dri2_img->dri_image =
+          dri2_dpy->image->createImageFromNames(dri2_dpy->dri_screen,
+                        buf->width,
+                        buf->height,
+                        format,
+                        &name, 1,
+                        (int*)strides,
+                        (int*)offsets,
+                        dri2_img);
+       break;
+   default:
+       /* We should never arrive here */
+      _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x",
+              buf->format);
+      break;
+   }
+
    if (!dri2_img->dri_image) {
       free(dri2_img);
       _eglError(EGL_BAD_ALLOC, "droid_create_image_mesa_drm");

src/egl/drivers/dri2/platform_x11.c

@@ -212,7 +212,7 @@ dri2_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
 			dri2_surf->drawable, s.data->root,
 			dri2_surf->base.Width, dri2_surf->base.Height);
    } else {
-      dri2_surf->drawable = window;
+      dri2_surf->drawable = (xcb_drawable_t)window;
    }
 
    if (dri2_dpy->dri2) {
@@ -836,10 +836,10 @@ dri2_copy_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf,
    (*dri2_dpy->flush->flush)(dri2_surf->dri_drawable);
 
    gc = xcb_generate_id(dri2_dpy->conn);
-   xcb_create_gc(dri2_dpy->conn, gc, target, 0, NULL);
+   xcb_create_gc(dri2_dpy->conn, gc, (xcb_drawable_t)target, 0, NULL);
    xcb_copy_area(dri2_dpy->conn,
 		  dri2_surf->drawable,
-		  target,
+		  (xcb_drawable_t)target,
 		  gc,
 		  0, 0,
 		  0, 0,

src/egl/main/Android.mk

@@ -121,11 +121,13 @@ endif
 # r300g/r600g/radeonsi
 ifneq ($(filter r300g r600g radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_winsys_radeon
+LOCAL_SHARED_LIBRARIES += libdrm_radeon
 ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r300
 endif
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
-gallium_DRIVERS += libmesa_pipe_r600
+gallium_DRIVERS += libmesa_pipe_r600 libmesa_pipe_radeon
+LOCAL_SHARED_LIBRARIES += libstlport
 endif
 ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_radeonsi

src/gallium/Android.mk

@@ -61,7 +61,7 @@ ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/r300
 endif
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
-SUBDIRS += drivers/r600
+SUBDIRS += drivers/r600 drivers/radeon
 endif
 ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/radeonsi

src/gallium/auxiliary/translate/translate.c

@@ -39,7 +39,7 @@ struct translate *translate_create( const struct translate_key *key )
    struct translate *translate = NULL;
 
 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
-   translate = translate_sse2_create( key );
+   /*translate = translate_sse2_create( key );*/
    if (translate)
       return translate;
 #else

src/gallium/auxiliary/util/u_math.h

@@ -136,30 +136,6 @@ roundf(float x)
 #endif /* _MSC_VER */
 
 
-#ifdef PIPE_OS_ANDROID
-
-static INLINE
-double log2(double d)
-{
-   return log(d) * (1.0 / M_LN2);
-}
-
-/* workaround a conflict with main/imports.h */
-#ifdef log2f
-#undef log2f
-#endif
-
-static INLINE
-float log2f(float f)
-{
-   return logf(f) * (float) (1.0 / M_LN2);
-}
-
-#endif
-
-
-
-
 #define POW2_TABLE_SIZE_LOG2 9
 #define POW2_TABLE_SIZE (1 << POW2_TABLE_SIZE_LOG2)
 #define POW2_TABLE_OFFSET (POW2_TABLE_SIZE/2)

src/gallium/drivers/r300/r300_chipset.c

@@ -35,6 +35,11 @@
 
 static void r300_apply_hyperz_blacklist(struct r300_capabilities* caps)
 {
+#ifdef ANDROID
+    extern const char *__progname;
+    const char *arg = strrchr(__progname, '/');
+    const char *program_invocation_short_name = arg ? arg + 1 : __progname;
+#endif
     static const char *list[] = {
         "X",    /* the DDX or indirect rendering */
         "Xorg", /* (alternative name) */

src/gallium/drivers/r600/Android.mk

@@ -28,11 +28,12 @@ include $(LOCAL_PATH)/Makefile.sources
 
 include $(CLEAR_VARS)
 
-LOCAL_SRC_FILES := $(C_SOURCES)
+LOCAL_SRC_FILES := $(C_SOURCES) $(CXX_SOURCES)
 
-LOCAL_C_INCLUDES :=
+LOCAL_C_INCLUDES := $(DRM_TOP)
 
 LOCAL_MODULE := libmesa_pipe_r600
 
+include external/stlport/libstlport.mk
 include $(GALLIUM_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)

src/gallium/drivers/r600/sb/sb_bc.h

@@ -846,7 +846,7 @@ public:
 	unsigned ndw() { return bc.size(); }
 
 	void write_data(uint32_t* dst) {
-		memcpy(dst, bc.data(), 4 * bc.size());
+		std::copy(bc.begin(), bc.end(), dst);
 	}
 
 	void align(unsigned a) {
@@ -870,7 +870,7 @@ public:
 	}
 
 	unsigned get_pos() { return pos; }
-	uint32_t *data() { return bc.data(); }
+	uint32_t *data() { return &bc[0]; }
 
 	bytecode & operator <<(uint32_t v) {
 		if (pos == ndw()) {

src/gallium/drivers/r600/sb/sb_ra_init.cpp

@@ -680,7 +680,7 @@ void ra_split::split_vec(vvec &vv, vvec &v1, vvec &v2, bool allow_swz) {
 
 			value *t;
 			vvec::iterator F =
-					allow_swz ? find(v2.begin(), v2.end(), o) : v2.end();
+					allow_swz ? std::find(v2.begin(), v2.end(), o) : v2.end();
 
 			if (F != v2.end()) {
 				t = *(v1.begin() + (F - v2.begin()));

src/gallium/drivers/r600/sb/sb_valtable.cpp

@@ -207,7 +207,7 @@ void value_table::get_values(vvec& v) {
 
 	for(vt_table::iterator I = hashtable.begin(), E = hashtable.end();
 			I != E; ++I) {
-		T = copy(I->begin(), I->end(), T);
+		T = std::copy(I->begin(), I->end(), T);
 	}
 }
 
@@ -368,7 +368,7 @@ inline bool sb_bitset::set_chk(unsigned id, bool bit) {
 }
 
 void sb_bitset::clear() {
-	memset(data.data(), 0, sizeof(basetype) * data.size());
+	std::fill(data.begin(), data.end(), 0);
 }
 
 void sb_bitset::resize(unsigned size) {

src/gallium/drivers/radeon/Android.mk

@@ -0,0 +1,38 @@
+# Mesa 3-D graphics library
+#
+# Copyright (C) 2010-2011 Chia-I Wu <olvaffe@gmail.com>
+# Copyright (C) 2010-2011 LunarG Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := $(C_SOURCES)
+
+LOCAL_C_INCLUDES := $(DRM_TOP)
+
+LOCAL_MODULE := libmesa_pipe_radeon
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

src/gallium/state_trackers/egl/android/native_android.cpp

@@ -98,8 +98,8 @@ struct android_surface {
       int height;
       int format;
    } cache_key;
-   void *cache_handles[2];
-   struct pipe_resource *cache_resources[2];
+   void *cache_handles[4];
+   struct pipe_resource *cache_resources[4];
 };
 
 struct android_config {
@@ -147,10 +147,6 @@ get_pipe_format(int native)
    case HAL_PIXEL_FORMAT_BGRA_8888:
       fmt = PIPE_FORMAT_B8G8R8A8_UNORM;
       break;
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-      /* fmt = PIPE_FORMAT_A1B5G5R5_UNORM; */
-   case HAL_PIXEL_FORMAT_RGBA_4444:
-      /* fmt = PIPE_FORMAT_A4B4G4R4_UNORM; */
    default:
       ALOGE("unsupported native format 0x%x", native);
       fmt = PIPE_FORMAT_NONE;

src/gallium/targets/egl-static/egl.c

@@ -40,6 +40,8 @@
 #include "egl_pipe.h"
 #include "egl_st.h"
 
+#include <cutils/properties.h>
+
 static struct egl_g3d_loader egl_g3d_loader;
 
 static struct st_module {
@@ -231,12 +233,15 @@ static struct pipe_screen *
 create_drm_screen(const char *name, int fd)
 {
    struct pipe_screen *screen;
+   char value[PROPERTY_VALUE_MAX];
 
    if (!name) {
       name = drm_fd_get_screen_name(fd);
       if (!name)
          return NULL;
    }
+   if (!property_get("debug.mesa.driver", value, NULL))
+       property_set("debug.mesa.driver", name);
 
    screen = egl_pipe_create_drm_screen(name, fd);
    if (screen)

src/gallium/winsys/radeon/drm/radeon_winsys.h

@@ -41,7 +41,7 @@
  */
 
 #include "pipebuffer/pb_buffer.h"
-#include "libdrm/radeon_surface.h"
+#include "radeon/radeon_surface.h"
 
 #define RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
 

src/gbm/backends/dri/gbm_dri.c

@@ -547,6 +547,15 @@ gbm_dri_bo_create(struct gbm_device *gbm,
    case GBM_FORMAT_ABGR8888:
       dri_format = __DRI_IMAGE_FORMAT_ABGR8888;
       break;
+   case GBM_FORMAT_YUV420:
+      dri_format = __DRI_IMAGE_FOURCC_YUV420;
+      break;
+   case GBM_FORMAT_YVU420:
+      dri_format = __DRI_IMAGE_FOURCC_YVU420;
+      break;
+   case GBM_FORMAT_NV12:
+      dri_format = __DRI_IMAGE_FOURCC_NV12;
+      break;
    default:
       return NULL;
    }

src/glsl/Android.mk

@@ -39,12 +39,12 @@ LOCAL_SRC_FILES := \
 	$(LIBGLSL_FILES)
 
 LOCAL_C_INCLUDES := \
-	external/astl/include \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/mesa
 
 LOCAL_MODULE := libmesa_glsl
 
+include external/stlport/libstlport.mk
 include $(LOCAL_PATH)/Android.gen.mk
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)

src/glsl/ast_to_hir.cpp

@@ -94,6 +94,24 @@ _mesa_ast_to_hir(exec_list *instructions, struct _mesa_glsl_parse_state *state)
    detect_conflicting_assignments(state, instructions);
 
    state->toplevel_ir = NULL;
+
+   /* Move all of the variable declarations to the front of the IR list, and
+    * reverse the order.  This has the (intended!) side effect that vertex
+    * shader inputs and fragment shader outputs will appear in the IR in the
+    * same order that they appeared in the shader code.  This results in the
+    * locations being assigned in the declared order.  Many (arguably buggy)
+    * applications depend on this behavior, and it matches what nearly all
+    * other drivers do.
+    */
+   foreach_list_safe(node, instructions) {
+      ir_variable *const var = ((ir_instruction *) node)->as_variable();
+
+      if (var == NULL)
+         continue;
+
+      var->remove();
+      instructions->push_head(var);
+   }
 }
 
 

src/glsl/link_uniforms.cpp

@@ -739,6 +739,20 @@ link_assign_uniform_locations(struct gl_shader_program *prog)
              sizeof(prog->_LinkedShaders[i]->SamplerTargets));
    }
 
+   /* Determine the size of the largest uniform array queryable via
+    * glGetUniformLocation.  Using this as the location scale guarantees that
+    * there is enough "room" for the array index to be stored in the low order
+    * part of the uniform location.  It also makes the locations be more
+    * tightly packed.
+    */
+   unsigned max_array_size = 1;
+   for (unsigned i = 0; i < num_user_uniforms; i++) {
+      if (uniforms[i].array_elements > max_array_size)
+         max_array_size = uniforms[i].array_elements;
+   }
+
+   prog->UniformLocationBaseScale = max_array_size;
+
 #ifndef NDEBUG
    for (unsigned i = 0; i < num_user_uniforms; i++) {
       assert(uniforms[i].storage != NULL);

src/mesa/Android.libmesa_dricore.mk

@@ -52,6 +52,10 @@ endif # MESA_ENABLE_ASM
 LOCAL_CFLAGS := \
    $(patsubst %,-DFEATURE_%=1,$(MESA_ENABLED_APIS))
 
+ifneq ($(strip $(MESA_VERSION_STRING_EXTRA)),)
+    LOCAL_CFLAGS += -DMESA_VERSION_STRING_EXTRA="\"$(MESA_VERSION_STRING_EXTRA)\""
+endif
+
 LOCAL_C_INCLUDES := \
 	$(call intermediates-dir-for STATIC_LIBRARIES,libmesa_program,,) \
 	$(MESA_TOP)/src/mapi \

src/mesa/drivers/dri/i915/Android.mk

@@ -42,7 +42,7 @@ LOCAL_C_INCLUDES := \
 	$(DRM_TOP)/intel
 
 LOCAL_SRC_FILES := \
-	$(i915_C_FILES)
+	$(i915_FILES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := \
 	$(MESA_DRI_WHOLE_STATIC_LIBRARIES)

src/mesa/drivers/dri/i915/i830_texstate.c

@@ -335,6 +335,7 @@ i830UpdateTextureState(struct intel_context *intel)
       case TEXTURE_1D_BIT:
       case TEXTURE_2D_BIT:
       case TEXTURE_CUBE_BIT:
+      case TEXTURE_EXTERNAL_BIT:
          ok = i830_update_tex_unit(intel, i, TEXCOORDS_ARE_NORMAL);
          break;
       case TEXTURE_RECT_BIT:

src/mesa/drivers/dri/i915/i915_context.c

@@ -107,6 +107,7 @@ intel_init_texture_formats(struct gl_context *ctx)
    ctx->TextureFormatSupported[MESA_FORMAT_ARGB4444] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_ARGB1555] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_RGB565] = true;
+   ctx->TextureFormatSupported[MESA_FORMAT_RGBX8888_REV] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_L8] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_A8] = true;
    ctx->TextureFormatSupported[MESA_FORMAT_I8] = true;

src/mesa/drivers/dri/i915/i915_fragprog.c

@@ -258,6 +258,8 @@ translate_tex_src_target(struct i915_fragment_program *p, GLubyte bit)
       return D0_SAMPLE_TYPE_VOLUME;
    case TEXTURE_CUBE_INDEX:
       return D0_SAMPLE_TYPE_CUBE;
+   case TEXTURE_EXTERNAL_INDEX:
+      return D0_SAMPLE_TYPE_2D;
    default:
       i915_program_error(p, "TexSrcBit: %d", bit);
       return 0;

src/mesa/drivers/dri/i915/i915_state.c

@@ -788,6 +788,7 @@ i915Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
 
    switch (cap) {
    case GL_TEXTURE_2D:
+   case GL_TEXTURE_EXTERNAL_OES:
       break;
 
    case GL_LIGHTING:

src/mesa/drivers/dri/i915/i915_tex_layout.c

@@ -236,6 +236,7 @@ i915_miptree_layout(struct intel_mipmap_tree * mt)
       break;
    case GL_TEXTURE_1D:
    case GL_TEXTURE_2D:
+   case GL_TEXTURE_EXTERNAL_OES:
    case GL_TEXTURE_RECTANGLE_ARB:
       i915_miptree_layout_2d(mt);
       break;
@@ -468,6 +469,7 @@ i945_miptree_layout(struct intel_mipmap_tree * mt)
       break;
    case GL_TEXTURE_1D:
    case GL_TEXTURE_2D:
+   case GL_TEXTURE_EXTERNAL_OES:
    case GL_TEXTURE_RECTANGLE_ARB:
       i945_miptree_layout_2d(mt);
       break;

src/mesa/drivers/dri/i915/i915_texstate.c

@@ -61,6 +61,8 @@ translate_texture_format(gl_format mesa_format, GLenum DepthMode)
       return MAPSURF_32BIT | MT_32BIT_ARGB8888;
    case MESA_FORMAT_XRGB8888:
       return MAPSURF_32BIT | MT_32BIT_XRGB8888;
+   case MESA_FORMAT_RGBX8888_REV:
+      return MAPSURF_32BIT | MT_32BIT_XBGR8888;
    case MESA_FORMAT_RGBA8888_REV:
       return MAPSURF_32BIT | MT_32BIT_ABGR8888;
    case MESA_FORMAT_YCBCR_REV:
@@ -422,6 +424,7 @@ i915UpdateTextureState(struct intel_context *intel)
       case TEXTURE_2D_BIT:
       case TEXTURE_CUBE_BIT:
       case TEXTURE_3D_BIT:
+      case TEXTURE_EXTERNAL_BIT:
          ok = i915_update_tex_unit(intel, i, SS3_NORMALIZED_COORDS);
          break;
       case TEXTURE_RECT_BIT:

src/mesa/drivers/dri/i915/i915_vtbl.c

@@ -551,6 +551,7 @@ static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 {
    [MESA_FORMAT_ARGB8888] = DV_PF_8888,
    [MESA_FORMAT_XRGB8888] = DV_PF_8888,
+   [MESA_FORMAT_RGBX8888_REV] = DV_PF_8888,
    [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
    [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
    [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,

src/mesa/drivers/dri/i965/Makefile.sources

@@ -60,6 +60,7 @@ i965_FILES = \
 	brw_fs_live_variables.cpp \
 	brw_fs_reg_allocate.cpp \
 	brw_fs_vector_splitting.cpp \
+	brw_fs_ext_texture.cpp \
 	brw_fs_visitor.cpp \
 	brw_gs.c \
 	brw_gs_emit.c \

src/mesa/drivers/dri/i965/brw_clear.c

@@ -128,6 +128,14 @@ brw_fast_clear_depth(struct gl_context *ctx)
       return false;
    }
 
+   /* check that colorbuffer depth equals to depthbuffer depth on IVB */
+   if(intel->gen == 7) {
+      struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
+      if (rb && _mesa_get_format_bytes(rb->Format) !=
+                _mesa_get_format_bytes(intel_rb_format(depth_irb)))
+         return false;
+   }
+
    uint32_t depth_clear_value;
    switch (mt->format) {
    case MESA_FORMAT_Z32_FLOAT_X24S8:

src/mesa/drivers/dri/i965/brw_context.h

@@ -263,19 +263,52 @@ static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type)
    return ss_type & 0xFFFF;
 }
 
+/** Number of texture sampler units */
+#define BRW_MAX_TEX_UNIT 16
+
 /** Subclass of Mesa vertex program */
 struct brw_vertex_program {
    struct gl_vertex_program program;
    GLuint id;
+   /** See equivalent member of 'brw_fragment_program' for details */
+   uint32_t sampler_to_surf_state_start[BRW_MAX_TEX_UNIT];
 };
 
+static inline uint32_t brw_surf_index_vs_texture(
+   const struct brw_vertex_program *vp, unsigned sampler)
+{
+   return vp->sampler_to_surf_state_start[sampler];
+}
 
 /** Subclass of Mesa fragment program */
 struct brw_fragment_program {
    struct gl_fragment_program program;
    GLuint id;  /**< serial no. to identify frag progs, never re-used */
+
+   /**
+    * Relation assigning shader samplers with a region in the HW surface state
+    * binding table. This used to be explicit one-sampler-one-surface-relation.
+    * However, in order to support image-external-textures a sampler
+    * representing, for example, multi-planar YUV texture may require up to
+    * three HW surfaces, one for each of the components/planes (Y, U and V). The
+    * actual number of HW surfaces associated with a sampler can be deduced from
+    * the format/layout of the texture image - here one simply stores the
+    * starting index.
+    * This relation can be set after linking but must in place before WM FS
+    * emission (one needs to know the surface state indices when generating the
+    * sampling commands). In addition, this relation must be accessible just
+    * before the actual execution of the shader is kicked off. (The contents of
+    * the surface state binding table itself are updated at that point).
+    */
+   uint32_t sampler_to_surf_state_start[BRW_MAX_TEX_UNIT];
 };
 
+static inline uint32_t brw_surf_index_texture(
+   const struct brw_fragment_program *fp, unsigned sampler)
+{
+   return fp->sampler_to_surf_state_start[sampler];
+}
+
 struct brw_shader {
    struct gl_shader base;
 
@@ -482,9 +515,6 @@ struct brw_vs_prog_data {
    bool uses_vertexid;
 };
 
-/** Number of texture sampler units */
-#define BRW_MAX_TEX_UNIT 16
-
 /** Max number of render targets in a shader */
 #define BRW_MAX_DRAW_BUFFERS 8
 

src/mesa/drivers/dri/i965/brw_fs.h

@@ -184,6 +184,7 @@ public:
    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint32_t texture_offset; /**< Texture offset bitfield */
    int sampler;
+   int surf_index_offset;
    int target; /**< MRT target. */
    bool eot;
    bool header_present;
@@ -349,6 +350,7 @@ public:
    fs_reg *emit_general_interpolation(ir_variable *ir);
    void emit_interpolation_setup_gen4();
    void emit_interpolation_setup_gen6();
+   bool emit_texture_external(ir_texture *ir, fs_reg& coordinate, int sampler);
    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
                            bool is_rect, int sampler, int texunit);
    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,

src/mesa/drivers/dri/i965/brw_fs_emit.cpp

@@ -492,7 +492,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
 	      retype(dst, BRW_REGISTER_TYPE_UW),
 	      inst->base_mrf,
 	      src,
-              SURF_INDEX_TEXTURE(inst->sampler),
+              brw_surf_index_texture((const struct brw_fragment_program*)fp,
+                 inst->sampler) + inst->surf_index_offset,
 	      inst->sampler,
 	      msg_type,
 	      rlen,

src/mesa/drivers/dri/i965/brw_fs_ext_texture.cpp

@@ -0,0 +1,274 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Topi Pohjolainen <topi.pohjolainen@intel.com>
+ *
+ */
+
+/** @file brw_fs_ext_texture.cpp
+ *
+ * This file implements the generation of FS LIR for converting YUV samples into
+ * RGB as part of single GLSL texture sampling instruction. The implementation
+ * follows the one found in "brw_wm_fp.c::precalc_tex()".
+ *
+ *   B = 1.164(Y - 16)                  + 2.018(U - 128)
+ *   G = 1.164(Y - 16) - 0.813(V - 128) - 0.391(U - 128)
+ *   R = 1.164(Y - 16) + 1.596(V - 128)
+ * 
+ * Implementation in 'brw_wm_fp.c':
+ *
+ * Need to emit YUV texture conversions by hand. Probably need to do this here
+ * - the alternative is in execution unit emisson time , but the conversion
+ * requires allocating a temporary variable which one doesn't have the facility
+ * to do that late in the compilation.
+ * 
+ * CONST C0 = { -.0625, -.5, -.5, 1.164 }
+ * CONST C1 = { 1.596, -0.813, 2.018, -.391 }
+ * YUV     = TEX ...
+ * YUV.xyz = ADD YUV,     C0
+ * YUV.x   = MUL YUV.x,   C0.w
+ * RGB.xyz = MAD YUV.zzy, C1,   YUV.x
+ * RGB.y   = MAD YUV.y,   C1.w, RGB.y
+ */
+extern "C" {
+
+#include <sys/types.h>
+
+#include "main/macros.h"
+#include "brw_context.h"
+}
+#include "brw_shader.h"
+#include "brw_fs.h"
+
+struct fs_reg_const_float4 : public fs_reg {
+   fs_reg_const_float4(fs_visitor *v, float f1, float f2, float f3, float f4) :
+      fs_reg(v, glsl_type::vec4_type)
+   {
+      fs_reg tmp = *this;
+
+      v->emit(BRW_OPCODE_MOV, tmp, fs_reg(f1));
+      ++tmp.reg_offset;
+      v->emit(BRW_OPCODE_MOV, tmp, fs_reg(f2));
+      ++tmp.reg_offset;
+      v->emit(BRW_OPCODE_MOV, tmp, fs_reg(f3));
+      ++tmp.reg_offset;
+      v->emit(BRW_OPCODE_MOV, tmp, fs_reg(f4));
+   }
+};
+
+static fs_reg
+add_mul_yuv_c0(fs_visitor *v, const fs_reg& yuv)
+{
+   /**
+    * Whereas original uses 16/256 = .0625, 128/256 = .5, here one uses the
+    * divider of 255 corresponding to the range [0,255]. The multiplier of 1.164
+    * in turn corresponds to treating Y-components being in the range of
+    * [16,235] (219 steps).
+    */
+   fs_reg_const_float4 c0(v, -16.0f/255, -128.0f/255, -128.0f/255, 255.0/219);
+   fs_reg res(v, glsl_type::vec4_type);
+   fs_reg tmp_res(res);
+   fs_reg tmp_yuv(yuv);
+
+   /* YUV.xyz = ADD YUV, C0 */
+   for (unsigned i = 0; i < 3; ++i) {
+      v->emit(BRW_OPCODE_ADD, tmp_res, tmp_yuv, c0);
+      tmp_yuv.reg_offset++;
+      c0.reg_offset++;
+      tmp_res.reg_offset++;
+   }
+
+   /* YUV.x = MUL YUV.x, C0.w */
+   tmp_res.reg_offset = 0;
+   v->emit(BRW_OPCODE_MUL, tmp_res, tmp_res, c0);
+
+   return res;
+}
+
+static fs_reg
+mad_yuv_c1(fs_visitor *v, const fs_reg& yuv)
+{
+   /**
+    * The multipliers are result of treating V- and U-components having range
+    * of [16,240] (224 steps).
+    */
+   fs_reg_const_float4 c1(v, 1.402 * 255.0 / 224, -0.714 * 255.0 / 224,
+                             1.772 * 255.0 / 224, -0.344 * 255.0 / 224);
+   fs_reg res(v, glsl_type::vec4_type);
+   fs_reg tmp_res(res);
+   fs_reg tmp_uv(yuv);
+   fs_reg tmp_y(yuv);
+
+   /* RGB.x = MAD YUV.x, C1.x, YUV.z */
+   tmp_uv.reg_offset = 2;
+   v->emit(BRW_OPCODE_MAD, tmp_res, tmp_y, c1, tmp_uv);
+   c1.reg_offset++;
+   tmp_res.reg_offset++;
+
+   /* RGB.y = MAD YUV.x, C1.y, YUV.z */
+   v->emit(BRW_OPCODE_MAD, tmp_res, tmp_y, c1, tmp_uv);
+   c1.reg_offset++;
+   tmp_res.reg_offset++;
+
+   /* RGB.z = MAD YUV.x, C1.z, YUV.y */
+   tmp_uv.reg_offset = 1;
+   v->emit(BRW_OPCODE_MAD, tmp_res, tmp_y, c1, tmp_uv);
+   c1.reg_offset++;
+
+   /* RGB.y = MAD RGB.y, C1.w, YUV.y */
+   tmp_res.reg_offset = 1;
+   v->emit(BRW_OPCODE_MAD, tmp_res, tmp_res, c1, tmp_uv);
+
+   /* Specification says that alpha is to be set to 255 if not available */
+   tmp_res.reg_offset = 3;
+   v->emit(BRW_OPCODE_MOV, tmp_res, fs_reg(1.0f));
+
+   return res;
+}
+
+static const struct intel_texture_image *
+resolve_tex_img(const struct gl_context *ctx, const GLbitfield *used, int unit)
+{
+   if (!(used[unit] & (1 << TEXTURE_EXTERNAL_INDEX)))
+      return 0;
+
+   const struct gl_texture_object *obj =
+      ctx->Texture.Unit[unit].CurrentTex[TEXTURE_EXTERNAL_INDEX];
+
+   if (!obj)
+      return 0;
+
+   return (const struct intel_texture_image *)obj->Image[0][obj->BaseLevel];
+}
+
+static fs_inst *
+emit_texture_gen(fs_visitor *visitor, ir_texture *ir, int gen,
+		 fs_reg& dst, fs_reg& coord, int sampler,
+		 int surf_index_offset)
+{
+   fs_reg shadow_c;
+   fs_reg lod;
+   fs_reg lod2;
+   fs_inst *inst;
+
+   if (gen >= 7) {
+      inst = visitor->emit_texture_gen7(ir, dst, coord, shadow_c, lod, lod2, 0);
+   } else if (gen >= 5) {
+      inst = visitor->emit_texture_gen5(ir, dst, coord, shadow_c, lod, lod2, 0);
+   } else {
+      inst = visitor->emit_texture_gen4(ir, dst, coord, shadow_c, lod, lod2);
+   }
+
+   /* The header is set up by generate_tex() when necessary. */
+   inst->src[0] = reg_undef;
+   inst->sampler = sampler;
+   inst->surf_index_offset = surf_index_offset;
+
+   return inst;
+}
+
+static void
+yuv420_chroma(fs_visitor *v, ir_texture *ir, int gen, fs_reg& yuv,
+              fs_reg& coord, int sampler,
+              unsigned chroma_src_i, unsigned chroma_dst_i)
+{
+   fs_reg tmp_yuv_dst(yuv);
+   fs_reg c = fs_reg(v, glsl_type::vec4_type);
+
+   emit_texture_gen(v, ir, gen, c, coord, sampler, chroma_src_i);
+
+   tmp_yuv_dst.reg_offset += chroma_dst_i;
+   v->emit(BRW_OPCODE_MOV, tmp_yuv_dst, c);
+}
+
+static void
+nv12_chroma(fs_visitor *v, ir_texture *ir, int gen, fs_reg& yuv,
+            fs_reg& coord, int sampler)
+{
+   fs_reg tmp_yuv_dst(yuv);
+   fs_reg uv = fs_reg(v, glsl_type::vec4_type);
+
+   emit_texture_gen(v, ir, gen, uv, coord, sampler, 1);
+
+   tmp_yuv_dst.reg_offset++;
+   v->emit(BRW_OPCODE_MOV, tmp_yuv_dst, uv);
+
+   tmp_yuv_dst.reg_offset++;
+   uv.reg_offset++;
+   v->emit(BRW_OPCODE_MOV, tmp_yuv_dst, uv);
+}
+
+/* Consider the YUV format in question and fetch the different components from
+ * single plane in case of packed formats or from separate planes in case of
+ * planar formats.
+ * The components are then packed into one register allowing one to use the same
+ * conversion logic independent on the component layout in the texture being
+ * sampled. Naturally one could write texture format aware converters and
+ * possibly improve the performance by reducing the amount of instructions. Here
+ * things are, however, rather kept simple.
+ */
+bool
+fs_visitor::emit_texture_external(ir_texture *ir, fs_reg& coordinate,
+				  int sampler)
+{
+   const struct intel_texture_image *img = resolve_tex_img(ctx,
+                                              fp->Base.TexturesUsed,
+                                              fp->Base.SamplerUnits[sampler]);
+
+   if (img && !img->ext_format)
+      return false;
+
+   /**
+    * "Sampling an external texture which is not associated with any EGLImage
+    *  sibling will return a sample value of (0,0,0,1)." 
+    */
+   if (!img) {
+      swizzle_result(ir, fs_reg_const_float4(this, 0, 0, 0, 1), sampler);
+      return true;
+   }
+
+   fs_reg yuv = fs_reg(this, glsl_type::vec4_type);
+   emit_texture_gen(this, ir, intel->gen, yuv, coordinate, sampler, 0);
+
+   switch (img->ext_format->fourcc) {
+   case __DRI_IMAGE_FOURCC_YUV420:
+      yuv420_chroma(this, ir, intel->gen, yuv, coordinate, sampler, 1, 1);
+      yuv420_chroma(this, ir, intel->gen, yuv, coordinate, sampler, 2, 2);
+      break;
+   case __DRI_IMAGE_FOURCC_YVU420:
+      yuv420_chroma(this, ir, intel->gen, yuv, coordinate, sampler, 1, 2);
+      yuv420_chroma(this, ir, intel->gen, yuv, coordinate, sampler, 2, 1);
+      break;
+   case __DRI_IMAGE_FOURCC_NV12:
+      nv12_chroma(this, ir, intel->gen, yuv, coordinate, sampler);
+      break;
+   default:
+      return false;
+   }
+
+   fs_reg rgb = mad_yuv_c1(this, add_mul_yuv_c0(this, yuv));
+
+   swizzle_result(ir, rgb, sampler);
+
+   return true;
+}

src/mesa/drivers/dri/i965/brw_fs_visitor.cpp

@@ -1440,6 +1440,11 @@ fs_visitor::visit(ir_texture *ir)
                                     sampler, texunit);
    }
 
+   if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_EXTERNAL &&
+      emit_texture_external(ir, coordinate, sampler)) {
+      return;
+   }
+
    fs_reg shadow_comparitor;
    if (ir->shadow_comparitor) {
       ir->shadow_comparitor->accept(this);

src/mesa/drivers/dri/i965/brw_program.c

@@ -40,6 +40,7 @@
 #include "glsl/ralloc.h"
 
 #include "brw_context.h"
+#include "brw_state.h"
 #include "brw_wm.h"
 
 static unsigned
@@ -135,6 +136,7 @@ brwProgramStringNotify(struct gl_context *ctx,
       if (newFP == curFP)
 	 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
       newFP->id = get_new_program_id(brw->intel.intelScreen);
+      brw_clear_cache(brw, &brw->cache);
    }
    else if (target == GL_VERTEX_PROGRAM_ARB) {
       struct gl_vertex_program *vprog = (struct gl_vertex_program *) prog;
@@ -206,6 +208,14 @@ brw_get_scratch_bo(struct intel_context *intel,
    }
 }
 
+static void
+brwSamplerUniformChange(struct gl_context *ctx,
+	GLenum target, struct gl_program *prog)
+{
+	brwProgramStringNotify(ctx, target, prog);
+}
+
+
 void brwInitFragProgFuncs( struct dd_function_table *functions )
 {
    assert(functions->ProgramStringNotify == _tnl_program_string); 
@@ -215,6 +225,7 @@ void brwInitFragProgFuncs( struct dd_function_table *functions )
    functions->DeleteProgram = brwDeleteProgram;
    functions->IsProgramNative = brwIsProgramNative;
    functions->ProgramStringNotify = brwProgramStringNotify;
+   functions->SamplerUniformChange = brwSamplerUniformChange;
 
    functions->NewShader = brw_new_shader;
    functions->NewShaderProgram = brw_new_shader_program;

src/mesa/drivers/dri/i965/brw_program.h

@@ -40,6 +40,12 @@ struct brw_sampler_prog_key_data {
     */
    uint16_t yuvtex_mask;
    uint16_t yuvtex_swap_mask; /**< UV swaped */
+
+   /**
+    * Format of the sampled texture when it is of the type image
+    * external and needs special sampling/conversion.
+    */
+   const struct intel_image_format *ext_format;
 };
 
 void brw_populate_sampler_prog_key_data(struct gl_context *ctx,

src/mesa/drivers/dri/i965/brw_state.h

@@ -152,6 +152,7 @@ bool brw_search_cache(struct brw_cache *cache,
 		      const void *key,
 		      GLuint key_size,
 		      uint32_t *inout_offset, void *out_aux);
+void brw_clear_cache(struct brw_context *brw, struct brw_cache *cache);
 void brw_state_cache_check_size( struct brw_context *brw );
 
 void brw_init_caches( struct brw_context *brw );

src/mesa/drivers/dri/i965/brw_state_cache.c

@@ -348,7 +348,7 @@ brw_init_caches(struct brw_context *brw)
    cache->aux_free[BRW_WM_PROG] = brw_wm_prog_data_free;
 }
 
-static void
+void
 brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
 {
    struct intel_context *intel = &brw->intel;

src/mesa/drivers/dri/i965/brw_vs.c

@@ -209,7 +209,6 @@ brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
    return true;
 }
 
-
 bool
 brw_vs_prog_data_compare(const void *in_a, const void *in_b,
                          int aux_size, const void *in_key)
@@ -231,6 +230,29 @@ brw_vs_prog_data_compare(const void *in_a, const void *in_b,
    return true;
 }
 
+static bool brw_vs_surf_setup(GLbitfield samplers,
+                              const GLubyte *samplers_units,
+                              const GLbitfield *textures_used,
+                              const struct gl_texture_unit *units,
+                              uint32_t *sampler_to_surf_state_start)
+{
+   unsigned num_samplers = _mesa_fls(samplers);
+   unsigned surf_index = 0;
+
+   for (unsigned s = 0; s < num_samplers; s++) {
+      if (samplers & (1 << s)) {
+         sampler_to_surf_state_start[s] = SURF_INDEX_VS_TEXTURE(surf_index);
+         surf_index += resolve_hw_surf_num(units, textures_used,
+                          samplers_units[s]);
+
+         if (surf_index > SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT))
+            return false;
+      }
+   }
+
+   return true;
+}
+
 static bool
 do_vs_prog(struct brw_context *brw,
 	   struct gl_shader_program *prog,
@@ -307,6 +329,13 @@ do_vs_prog(struct brw_context *brw,
 			       true);
    }
 
+   if (!brw_vs_surf_setup(c.vp->program.Base.SamplersUsed,
+			 c.vp->program.Base.SamplerUnits,
+			 c.vp->program.Base.TexturesUsed,
+			 brw->intel.ctx.Texture.Unit,
+			 c.vp->sampler_to_surf_state_start))
+      return false;
+
    /* Emit GEN4 code.
     */
    program = brw_vs_emit(brw, prog, &c, &prog_data, mem_ctx, &program_size);

src/mesa/drivers/dri/i965/brw_wm.c

@@ -130,6 +130,29 @@ brw_wm_prog_data_free(const void *in_prog_data)
    ralloc_free((void *)prog_data->pull_param);
 }
 
+static bool brw_wm_fs_surf_setup(GLbitfield samplers,
+                                 const GLubyte *samplers_units,
+                                 const GLbitfield *textures_used,
+                                 const struct gl_texture_unit *units,
+                                 uint32_t *sampler_to_surf_state_start)
+{
+   unsigned num_samplers = _mesa_fls(samplers);
+   unsigned surf_index = 0;
+
+   for (unsigned s = 0; s < num_samplers; s++) {
+      if (samplers & (1 << s)) {
+         sampler_to_surf_state_start[s] = SURF_INDEX_TEXTURE(surf_index);
+         surf_index += resolve_hw_surf_num(units, textures_used,
+	                  samplers_units[s]);
+
+         if (surf_index > SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT))
+            return false;
+      }
+   }
+
+   return true;
+}
+
 /**
  * All Mesa program -> GPU code generation goes through this function.
  * Depending on the instructions used (i.e. flow control instructions)
@@ -172,6 +195,13 @@ bool do_wm_prog(struct brw_context *brw,
       brw_compute_barycentric_interp_modes(brw, c->key.flat_shade,
                                            &fp->program);
 
+   if (!brw_wm_fs_surf_setup(fp->program.Base.SamplersUsed,
+                             fp->program.Base.SamplerUnits,
+                             fp->program.Base.TexturesUsed,
+                             brw->intel.ctx.Texture.Unit,
+                             fp->sampler_to_surf_state_start))
+      return false;
+
    program = brw_wm_fs_emit(brw, c, &fp->program, prog, &program_size);
    if (program == NULL)
       return false;
@@ -343,6 +373,13 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
 	    if (sampler->WrapR == GL_CLAMP)
 	       key->gl_clamp_mask[2] |= 1 << s;
 	 }
+
+         if (unit->_Current->Target == GL_TEXTURE_EXTERNAL_OES) {
+            const struct intel_texture_image *intel_img =
+               (const struct intel_texture_image *)img;
+
+            key->ext_format = intel_img->ext_format;
+         }
       }
    }
 }

src/mesa/drivers/dri/i965/brw_wm_surface_state.c

@@ -949,56 +949,37 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
 }
 
 static void
-brw_update_texture_surface(struct gl_context *ctx,
-                           unsigned unit,
-                           uint32_t *binding_table,
-                           unsigned surf_index)
+brw_update_texture_component(struct brw_context *brw,
+                             uint32_t *binding_table_slot,
+                             const struct intel_mipmap_tree *mt,
+                             unsigned width, unsigned height,
+                             unsigned depth, unsigned stride,
+                             GLuint target, GLuint tex_format,
+                             uint32_t offset, uint32_t levels,
+                             uint32_t first_level)
 {
-   struct intel_context *intel = intel_context(ctx);
-   struct brw_context *brw = brw_context(ctx);
-   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
-   struct intel_texture_object *intelObj = intel_texture_object(tObj);
-   struct intel_mipmap_tree *mt = intelObj->mt;
-   struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
-   struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-   uint32_t *surf;
-   int width, height, depth;
    uint32_t tile_x, tile_y;
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    6 * 4, 32, binding_table_slot);
 
-   if (tObj->Target == GL_TEXTURE_BUFFER) {
-      brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
-      return;
-   }
-
-   intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
-
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  6 * 4, 32, &binding_table[surf_index]);
-
-   surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
+   surf[0] = (target << BRW_SURFACE_TYPE_SHIFT |
 	      BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 	      BRW_SURFACE_CUBEFACE_ENABLES |
-	      (translate_tex_format(intel,
-                                    mt->format,
-				    firstImage->InternalFormat,
-				    tObj->DepthMode,
-				    sampler->sRGBDecode) <<
-	       BRW_SURFACE_FORMAT_SHIFT));
+	      (tex_format << BRW_SURFACE_FORMAT_SHIFT));
 
-   surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
-   surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
+   surf[1] = mt->region->bo->offset + offset;
+   surf[1] += intel_miptree_get_tile_offsets(mt, first_level, 0,
                                              &tile_x, &tile_y);
 
-   surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
+   surf[2] = (levels << BRW_SURFACE_LOD_SHIFT |
 	      (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 	      (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 
-   surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
+   surf[3] = (brw_get_surface_tiling_bits(mt->region->tiling) |
 	      (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
-	      (intelObj->mt->region->pitch - 1) <<
-	      BRW_SURFACE_PITCH_SHIFT);
+	      (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
 
-   surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
+   surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
 
    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
    /* Note that the low bits of these fields are missing, so
@@ -1012,12 +993,80 @@ brw_update_texture_surface(struct gl_context *ctx,
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   binding_table[surf_index] + 4,
-			   intelObj->mt->region->bo,
-                           surf[1] - intelObj->mt->region->bo->offset,
+                           *binding_table_slot + 4,
+                           mt->region->bo,
+                           surf[1] - mt->region->bo->offset,
                            I915_GEM_DOMAIN_SAMPLER, 0);
 }
 
+static void
+brw_update_ext_texture_surface(struct brw_context *brw,
+                               uint32_t *binding_table_slots,
+                               const struct intel_texture_image *intel_img)
+{
+   unsigned i;
+   const struct intel_region *region = intel_img->mt->region;
+   const struct intel_image_format *f = intel_img->ext_format;
+
+   for (i = 0; i < f->nplanes; ++i) {
+      int format = BRW_SURFACEFORMAT_R8_UNORM;
+      int index = f->planes[i].buffer_index;
+
+      if (f->planes[i].dri_format == __DRI_IMAGE_FORMAT_GR88)
+         format = BRW_SURFACEFORMAT_R8G8_UNORM;
+
+      brw_update_texture_component(brw, binding_table_slots + i,
+         intel_img->mt,
+         region->width >> f->planes[i].width_shift,
+         region->height >> f->planes[i].height_shift,
+         intel_img->base.Base.Depth,
+         intel_img->ext_strides[index],
+         BRW_SURFACE_2D,
+         format,
+         intel_img->ext_offsets[index],
+         0 /*levels*/,
+         0 /*first_level*/);
+   }
+}
+
+static void
+brw_update_texture_surface(struct gl_context *ctx,
+                           unsigned unit,
+                           uint32_t *binding_table,
+                           unsigned surf_index)
+{
+   struct brw_context *brw = brw_context(ctx);
+   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
+   struct intel_texture_object *intelObj = intel_texture_object(tObj);
+   struct intel_mipmap_tree *mt = intelObj->mt;
+   struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
+   const struct intel_texture_image *intel_img =
+      (const struct intel_texture_image *)firstImage;
+   struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+   int width, height, depth;
+
+   if (tObj->Target == GL_TEXTURE_BUFFER) {
+      brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
+      return;
+   }
+   else if (tObj->Target == GL_TEXTURE_EXTERNAL_OES && intel_img->ext_format) {
+      brw_update_ext_texture_surface(brw, binding_table + surf_index,
+                                     intel_img); 
+      return;
+   }
+
+   intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
+
+   brw_update_texture_component(brw, binding_table + surf_index,
+      mt, width, height, depth, mt->region->pitch,
+      translate_tex_target(tObj->Target),
+      translate_tex_format(intel_context(ctx), mt->format,
+         firstImage->InternalFormat, tObj->DepthMode, sampler->sRGBDecode),
+      mt->offset,
+      intelObj->_MaxLevel - tObj->BaseLevel,
+      firstImage->Level);
+}
+
 /**
  * Create the constant buffer surface.  Vertex/fragment shader constants will be
  * read from this buffer with Data Port Read instructions/messages.
@@ -1479,9 +1528,6 @@ brw_update_texture_surfaces(struct brw_context *brw)
    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
 
    for (unsigned s = 0; s < num_samplers; s++) {
-      brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
-      brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
-
       if (vs->SamplersUsed & (1 << s)) {
          const unsigned unit = vs->SamplerUnits[s];
 
@@ -1489,7 +1535,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
             intel->vtbl.update_texture_surface(ctx, unit,
                brw->vs.surf_offset,
-                                               SURF_INDEX_VS_TEXTURE(s));
+               brw_surf_index_vs_texture(
+                  (const struct brw_vertex_program *)brw->vertex_program,
+                  s));
          }
       }
 
@@ -1500,7 +1548,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
             intel->vtbl.update_texture_surface(ctx, unit,
                brw->wm.surf_offset,
-                                               SURF_INDEX_TEXTURE(s));
+               brw_surf_index_texture(
+                  (const struct brw_fragment_program *)brw->fragment_program,
+                  s));
          }
       }
    }

src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

@@ -282,6 +282,103 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,
    gen7_check_surface_setup(surf, false /* is_render_target */);
 }
 
+static void
+gen7_update_texture_component(struct brw_context *brw,
+                              uint32_t *binding_table_slot,
+                              const struct intel_mipmap_tree *mt,
+                              unsigned width, unsigned height,
+                              unsigned depth, unsigned stride,
+                              GLenum target, GLuint tex_format,
+                              uint32_t offset, GLuint first_level,
+                              uint32_t levels, int swizzle)
+{
+   uint32_t tile_x, tile_y;
+   const struct intel_region *region = mt->region;
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    8 * 4, 32, binding_table_slot);
+   memset(surf, 0, 8 * 4);
+
+   surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
+             tex_format << BRW_SURFACE_FORMAT_SHIFT |
+             gen7_surface_tiling_mode(region->tiling) |
+             BRW_SURFACE_CUBEFACE_ENABLES;
+
+   if (mt->align_h == 4)
+      surf[0] |= GEN7_SURFACE_VALIGN_4;
+   if (mt->align_w == 8)
+      surf[0] |= GEN7_SURFACE_HALIGN_8;
+
+   if (depth > 1 && target != GL_TEXTURE_3D)
+      surf[0] |= GEN7_SURFACE_IS_ARRAY;
+
+   if (mt->array_spacing_lod0)
+      surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
+
+   surf[1] = mt->region->bo->offset + offset;
+   surf[1] += intel_miptree_get_tile_offsets(mt, first_level, 0,
+                                             &tile_x, &tile_y);
+
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
+   surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (stride - 1);
+
+   surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
+   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
+              (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+              /* mip count */
+              levels);
+
+   if (brw->intel.is_haswell) {
+      surf[7] =
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
+   }
+
+   /* Emit relocation to surface contents */
+   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+                           *binding_table_slot + 4,
+                           mt->region->bo,
+                           surf[1] - mt->region->bo->offset,
+                           I915_GEM_DOMAIN_SAMPLER, 0);
+
+   gen7_check_surface_setup(surf, false /* is_render_target */);
+}
+
+static void
+gen7_update_ext_texture_surface(struct brw_context *brw,
+                                uint32_t *binding_table_slots,
+                                const struct intel_texture_image *intel_img)
+{
+   unsigned i;
+   const struct intel_region *region = intel_img->mt->region;
+   const struct intel_image_format *f = intel_img->ext_format;
+
+   for (i = 0; i < f->nplanes; ++i) {
+      int format = BRW_SURFACEFORMAT_R8_UNORM;
+      int index = f->planes[i].buffer_index;
+
+      if (f->planes[i].dri_format == __DRI_IMAGE_FORMAT_GR88)
+         format = BRW_SURFACEFORMAT_R8G8_UNORM;
+
+      gen7_update_texture_component(brw, binding_table_slots + i,
+         intel_img->mt,
+         region->width >> f->planes[i].width_shift,
+         region->height >> f->planes[i].height_shift,
+         intel_img->base.Base.Depth, intel_img->ext_strides[index],
+         GL_TEXTURE_EXTERNAL_OES,
+         format,
+         intel_img->ext_offsets[index],
+         0, 0, 0);
+   }
+}
+
 static void
 gen7_update_texture_surface(struct gl_context *ctx,
                             unsigned unit,
@@ -294,63 +391,29 @@ gen7_update_texture_surface(struct gl_context *ctx,
    struct intel_texture_object *intelObj = intel_texture_object(tObj);
    struct intel_mipmap_tree *mt = intelObj->mt;
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
+   const struct intel_texture_image *intel_img =
+      (const struct intel_texture_image *)firstImage;
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    int width, height, depth;
-   uint32_t tile_x, tile_y;
+   int swizzle = 0;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
       return;
    }
+   else if (tObj->Target == GL_TEXTURE_EXTERNAL_OES && intel_img->ext_format) {
+      gen7_update_ext_texture_surface(brw, binding_table + surf_index,
+                                      intel_img);
+      return;
+   }
+
+
+   /* We don't support MSAA for textures. */
+   assert(!mt->array_spacing_lod0);
+   assert(mt->num_samples <= 1);
 
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
-   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                                    8 * 4, 32, &binding_table[surf_index]);
-   memset(surf, 0, 8 * 4);
-
-   uint32_t tex_format = translate_tex_format(intel,
-                                              mt->format,
-                                              firstImage->InternalFormat,
-                                              tObj->DepthMode,
-                                              sampler->sRGBDecode);
-
-   surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
-             tex_format << BRW_SURFACE_FORMAT_SHIFT |
-             gen7_surface_tiling_mode(mt->region->tiling) |
-             BRW_SURFACE_CUBEFACE_ENABLES;
-
-   if (mt->align_h == 4)
-      surf[0] |= GEN7_SURFACE_VALIGN_4;
-   if (mt->align_w == 8)
-      surf[0] |= GEN7_SURFACE_HALIGN_8;
-
-   if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
-      surf[0] |= GEN7_SURFACE_IS_ARRAY;
-
-   if (mt->array_spacing_lod0)
-      surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
-
-   surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
-   surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
-                                             &tile_x, &tile_y);
-
-   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
-   surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
-             ((intelObj->mt->region->pitch) - 1);
-
-   surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
-
-   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
-   /* Note that the low bits of these fields are missing, so
-    * there's the possibility of getting in trouble.
-    */
-   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
-              (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
-              /* mip count */
-              (intelObj->_MaxLevel - tObj->BaseLevel));
-
    if (intel->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
        * texturing functions that return a float, as our code generation always
@@ -360,24 +423,17 @@ gen7_update_texture_surface(struct gl_context *ctx,
          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 
-      const int swizzle = unlikely(alpha_depth)
-         ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
-
-      surf[7] =
-         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
-         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
-         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
-         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
+      swizzle =
+         unlikely(alpha_depth) ? SWIZZLE_XYZW :
+         brw_get_texture_swizzle(ctx, tObj);
    }
 
-   /* Emit relocation to surface contents */
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   binding_table[surf_index] + 4,
-			   intelObj->mt->region->bo,
-                           surf[1] - intelObj->mt->region->bo->offset,
-			   I915_GEM_DOMAIN_SAMPLER, 0);
-
-   gen7_check_surface_setup(surf, false /* is_render_target */);
+   gen7_update_texture_component(brw, binding_table + surf_index,
+      mt, width, height, depth, mt->region->pitch, tObj->Target,
+      translate_tex_format(intel, mt->format, firstImage->InternalFormat,
+         tObj->DepthMode, sampler->sRGBDecode),
+      mt->offset, firstImage->Level,
+      intelObj->_MaxLevel - tObj->BaseLevel, swizzle);
 }
 
 /**

src/mesa/drivers/dri/intel/intel_extensions.c

@@ -83,7 +83,9 @@ intelInitExtensions(struct gl_context *ctx)
    ctx->Extensions.NV_texture_rectangle = true;
    ctx->Extensions.TDFX_texture_compression_FXT1 = true;
    ctx->Extensions.OES_EGL_image = true;
+   ctx->Extensions.OES_EGL_image_external = true;
    ctx->Extensions.OES_draw_texture = true;
+   ctx->Extensions.OES_EGL_image_external = true;
 
    if (intel->gen >= 6)
       ctx->Const.GLSLVersion = 140;
@@ -181,6 +183,7 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.EXT_texture_compression_s3tc = true;
 
    ctx->Extensions.ANGLE_texture_compression_dxt = true;
+   ctx->Extensions.EXT_texture_compression_s3tc = true;
 
    if (intel->gen >= 4) {
       ctx->Extensions.NV_primitive_restart = true;

src/mesa/drivers/dri/intel/intel_regions.c

@@ -43,6 +43,7 @@
 #include <errno.h>
 
 #include "main/hash.h"
+#include "main/macros.h"
 #include "intel_context.h"
 #include "intel_regions.h"
 #include "intel_blit.h"
@@ -158,6 +159,69 @@ intel_region_alloc(struct intel_screen *screen,
    return region;
 }
 
+/**
+ * The region is allocated in a way that it can be accessed by the sampling
+ * engine as it is (width aligned by four and height by two). Also the plane
+ * offsets are on page boundary in order to allow them to be further used as
+ * images on their own.
+ */
+struct intel_region *
+intel_region_planar_alloc(struct intel_screen *screen,
+			  int fourcc, GLuint width, GLuint height,
+			  uint32_t *strides, uint32_t *offsets)
+{
+   drm_intel_bo *buffer;
+   struct intel_region *region;
+   unsigned total;
+
+   /* For now one supports only formats with 2x2 subsampled UV-planes */
+   if (height % 2 || width % 2)
+      return NULL;
+
+   strides[0] = ALIGN(width, 4);
+   offsets[0] = 0;
+
+   total = strides[0] * ALIGN(height, 2);
+
+   switch (fourcc) {
+   case __DRI_IMAGE_FOURCC_YUV420:
+   case __DRI_IMAGE_FOURCC_YVU420:
+      strides[1] = ALIGN(width / 2, 4);
+      offsets[1] = ALIGN(total, 4096);
+
+      total = offsets[1] + strides[1] * ALIGN(height / 2, 2);
+      strides[2] = ALIGN(width / 2, 4);
+
+      offsets[2] = ALIGN(total, 4096);
+      total = offsets[2] + strides[2] * ALIGN(height / 2, 2);
+      break;
+   case __DRI_IMAGE_FOURCC_NV12:
+      strides[1] = ALIGN(width, 4);
+      offsets[1] = ALIGN(total, 4096);
+
+      total = offsets[1] + strides[1] * ALIGN(height / 2, 2);
+
+      strides[2] = 0;
+      offsets[2] = 0;
+      break;
+   default:
+      return NULL;
+   }
+
+   buffer = drm_intel_bo_alloc(screen->bufmgr, "region", total, 0);
+   if (buffer == NULL)
+      return NULL;
+
+   region = intel_region_alloc_internal(screen, 1, width, height,
+                                        width, I915_TILING_NONE, buffer);
+   if (region == NULL) {
+      drm_intel_bo_unreference(buffer);
+      return NULL;
+   }
+
+   return region;
+}
+
 bool
 intel_region_flink(struct intel_region *region, uint32_t *name)
 {
@@ -283,7 +347,7 @@ intel_region_release(struct intel_region **region_handle)
  * untiled, the masks are set to 0.
  */
 void
-intel_region_get_tile_masks(struct intel_region *region,
+intel_region_get_tile_masks(const struct intel_region *region,
                             uint32_t *mask_x, uint32_t *mask_y,
                             bool map_stencil_as_y_tiled)
 {

src/mesa/drivers/dri/intel/intel_regions.h

@@ -81,6 +81,12 @@ struct intel_region *intel_region_alloc(struct intel_screen *screen,
                                         GLuint height,
 					bool expect_accelerated_upload);
 
+struct intel_region *intel_region_planar_alloc(struct intel_screen *screen,
+					       int fourcc,
+					       GLuint width, GLuint height,
+					       uint32_t *strides,
+					       uint32_t *offsets);
+
 struct intel_region *
 intel_region_alloc_for_handle(struct intel_screen *screen,
 			      GLuint cpp,
@@ -104,7 +110,7 @@ void intel_region_release(struct intel_region **ib);
 void intel_recreate_static_regions(struct intel_context *intel);
 
 void
-intel_region_get_tile_masks(struct intel_region *region,
+intel_region_get_tile_masks(const struct intel_region *region,
                             uint32_t *mask_x, uint32_t *mask_y,
                             bool map_stencil_as_y_tiled);
 

src/mesa/drivers/dri/intel/intel_screen.c

@@ -210,6 +210,11 @@ static struct intel_image_format intel_image_formats[] = {
        { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
        { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
 
+   { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+     { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+       { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
+       { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
    { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
      { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
        { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
@@ -241,6 +246,21 @@ static struct intel_image_format intel_image_formats[] = {
        { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } }
 };
 
+static struct intel_image_format *
+intel_image_format_lookup(int fourcc)
+{
+   struct intel_image_format *f = 0;
+
+   for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
+      if (intel_image_formats[i].fourcc == fourcc) {
+	 f = &intel_image_formats[i];
+	 break;
+      }
+   }
+
+   return f;
+}
+
 static __DRIimage *
 intel_allocate_image(int dri_format, void *loaderPrivate)
 {
@@ -275,6 +295,12 @@ intel_allocate_image(int dri_format, void *loaderPrivate)
     case __DRI_IMAGE_FORMAT_GR88:
        image->format = MESA_FORMAT_GR88;
        break;
+    case __DRI_IMAGE_FOURCC_YUV420:
+    case __DRI_IMAGE_FOURCC_YVU420:
+    case __DRI_IMAGE_FOURCC_NV12:
+       image->format = MESA_FORMAT_R8;
+       image->planar_format = intel_image_format_lookup(dri_format);
+       break;
     case __DRI_IMAGE_FORMAT_NONE:
        image->format = MESA_FORMAT_NONE;
        break;
@@ -502,9 +528,18 @@ intel_create_image(__DRIscreen *screen,
    if (image == NULL)
       return NULL;
 
+   if (format == __DRI_IMAGE_FOURCC_YUV420 ||
+       format == __DRI_IMAGE_FOURCC_YVU420 ||
+       format == __DRI_IMAGE_FOURCC_NV12) {
+      image->region =
+         intel_region_planar_alloc(intelScreen, format, width, height,
+	 			   image->strides, image->offsets);
+   } else {
       cpp = _mesa_get_format_bytes(image->format);
       image->region =
          intel_region_alloc(intelScreen, tiling, cpp, width, height, true);
+   }
+
    if (image->region == NULL) {
       free(image);
       return NULL;
@@ -608,17 +643,12 @@ intel_create_image_from_names(__DRIscreen *screen,
     if (screen == NULL || names == NULL || num_names != 1)
         return NULL;
 
-    for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
-        if (intel_image_formats[i].fourcc == fourcc) {
-           f = &intel_image_formats[i];
-        }
-    }
-
+    f = intel_image_format_lookup(fourcc);
     if (f == NULL)
         return NULL;
 
     image = intel_create_image_from_name(screen, width, height,
-                                         __DRI_IMAGE_FORMAT_NONE,
+                                         __DRI_IMAGE_FORMAT_R8,
                                          names[0], strides[0],
                                          loaderPrivate);
 

src/mesa/drivers/dri/intel/intel_tex_image.c

@@ -388,6 +388,27 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
                                   image->format, image->offset,
                                   image->width,  image->height,
                                   image->tile_x, image->tile_y);
+
+   if (image->planar_format) {
+      struct intel_texture_image *intel_image = intel_texture_image(texImage);
+      const struct intel_image_format *f = image->planar_format;
+      unsigned i, index;
+
+      /* Check for sampling support here - shader compile time is too late. */
+      if (f->fourcc != __DRI_IMAGE_FOURCC_YUV420 &&
+          f->fourcc != __DRI_IMAGE_FOURCC_YVU420 &&
+          f->fourcc != __DRI_IMAGE_FOURCC_NV12) {
+         _mesa_error(ctx, GL_INVALID_OPERATION, __func__);
+         return;
+      }
+      
+      intel_image->ext_format = f;
+      for (i = 0; i < f->nplanes; i++) {
+         index = f->planes[i].buffer_index;
+         intel_image->ext_offsets[index] = image->offsets[index];
+         intel_image->ext_strides[index] = image->strides[index];
+      }
+   }
 }
 
 void

src/mesa/drivers/dri/intel/intel_tex_obj.h

@@ -29,6 +29,7 @@
 #define _INTEL_TEX_OBJ_H
 
 #include "swrast/s_context.h"
+#include "intel_regions.h"
 
 
 struct intel_texture_object
@@ -71,8 +72,44 @@ struct intel_texture_image
     * Else there is no image data.
     */
    struct intel_mipmap_tree *mt;
+
+   /* If ext_format != NULL, the image represents an external buffer. Depending
+    * on the format the details for the individual components of planar formats
+    * (such as NV12) are set in ext_strides and ext_offsets.
+    */
+   const struct intel_image_format *ext_format;
+   uint32_t ext_strides[3];
+   uint32_t ext_offsets[3];
 };
 
+/** Use specifically the format of the first image as this is set directly based
+ *  on the format of "__DRIimage" representing the external surface:
+ *  (see intel_image_target_texture_2d() and intel_set_texture_image_region()).
+ */
+static INLINE unsigned
+resolve_hw_surf_num(const struct gl_texture_unit *units, const GLbitfield *used,
+                    unsigned unit)
+{
+   const struct intel_texture_image *intel_img;
+   const struct gl_texture_object *tex_obj;
+
+   /** Only external textures may require more than one surface */
+   if (!(used[unit] & (1 << TEXTURE_EXTERNAL_INDEX)))
+      return 1;
+
+   tex_obj = units[unit].CurrentTex[TEXTURE_EXTERNAL_INDEX];
+   assert(tex_obj->Target == GL_TEXTURE_EXTERNAL_OES);
+
+   intel_img = (const struct intel_texture_image *)
+      tex_obj->Image[0][tex_obj->BaseLevel];
+
+   /** Assume one surface as no images are bound yet */
+   if (!intel_img)
+      return 1;
+
+   return intel_img->ext_format ? intel_img->ext_format->nplanes : 1;
+}
+
 static INLINE struct intel_texture_object *
 intel_texture_object(struct gl_texture_object *obj)
 {

src/mesa/main/extensions.c

@@ -143,7 +143,7 @@ static const struct extension extension_table[] = {
    { "GL_ARB_texture_float",                       o(ARB_texture_float),                       GL,             2004 },
    { "GL_ARB_texture_mirrored_repeat",             o(dummy_true),                              GLL,            2001 },
    { "GL_ARB_texture_multisample",                 o(ARB_texture_multisample),                 GL,             2009 },
-   { "GL_ARB_texture_non_power_of_two",            o(ARB_texture_non_power_of_two),            GL,             2003 },
+   { "GL_ARB_texture_non_power_of_two",            o(ARB_texture_non_power_of_two),            GL | ES1,       2003 },
    { "GL_ARB_texture_query_lod",                   o(ARB_texture_query_lod),                   GL,             2009 },
    { "GL_ARB_texture_rectangle",                   o(NV_texture_rectangle),                    GL,             2004 },
    { "GL_ARB_texture_rgb10_a2ui",                  o(ARB_texture_rgb10_a2ui),                  GL,             2009 },
@@ -212,7 +212,7 @@ static const struct extension extension_table[] = {
    { "GL_ANGLE_texture_compression_dxt5",          o(ANGLE_texture_compression_dxt),           GL | ES1 | ES2, 2011 },
    { "GL_EXT_texture_compression_latc",            o(EXT_texture_compression_latc),            GL,             2006 },
    { "GL_EXT_texture_compression_rgtc",            o(ARB_texture_compression_rgtc),            GL,             2004 },
-   { "GL_EXT_texture_compression_s3tc",            o(EXT_texture_compression_s3tc),            GL,             2000 },
+   { "GL_EXT_texture_compression_s3tc",            o(EXT_texture_compression_s3tc),            GL | ES1 | ES2, 2000 },
    { "GL_EXT_texture_cube_map",                    o(ARB_texture_cube_map),                    GLL,            2001 },
    { "GL_EXT_texture_edge_clamp",                  o(dummy_true),                              GLL,            1997 },
    { "GL_EXT_texture_env_add",                     o(dummy_true),                              GLL,            1999 },
@@ -291,6 +291,7 @@ static const struct extension extension_table[] = {
    { "GL_AMD_vertex_shader_layer",                 o(AMD_vertex_shader_layer),                 GL,             2012 },
    { "GL_APPLE_object_purgeable",                  o(APPLE_object_purgeable),                  GL,             2006 },
    { "GL_APPLE_packed_pixels",                     o(dummy_true),                              GLL,            2002 },
+   { "GL_APPLE_texture_2D_limited_npot",           o(ARB_texture_non_power_of_two),                 ES1,       2011 },
    { "GL_APPLE_texture_max_level",                 o(dummy_true),                                   ES1 | ES2, 2009 },
    { "GL_APPLE_vertex_array_object",               o(dummy_true),                              GLL,            2002 },
    { "GL_ATI_blend_equation_separate",             o(EXT_blend_equation_separate),             GL,             2003 },

src/mesa/main/mtypes.h

@@ -2332,6 +2332,21 @@ struct gl_shader_program
    struct gl_uniform_block *UniformBlocks;
    unsigned NumUniformBlocks;
 
+   /**
+    * Scale factor for the uniform base location
+    *
+    * This is used to generate locations (returned by \c glGetUniformLocation)
+    * of uniforms.  The base location of the uniform is multiplied by this
+    * value, and the array index is added.
+    *
+    * \note
+    * Must be >= 1.
+    *
+    * \sa
+    * _mesa_uniform_merge_location_offset, _mesa_uniform_split_location_offset
+    */
+   unsigned UniformLocationBaseScale;
+
    /**
     * Indices into the _LinkedShaders's UniformBlocks[] array for each stage
     * they're used in, or -1.

src/mesa/main/shaderobj.c

@@ -283,6 +283,7 @@ _mesa_clear_shader_program_data(struct gl_context *ctx,
       ralloc_free(shProg->UniformStorage);
       shProg->NumUserUniformStorage = 0;
       shProg->UniformStorage = NULL;
+      shProg->UniformLocationBaseScale = 0;
    }
 
    if (shProg->UniformHash) {

src/mesa/main/uniform_query.cpp

@@ -235,7 +235,7 @@ validate_uniform_parameters(struct gl_context *ctx,
       return false;
    }
 
-   _mesa_uniform_split_location_offset(location, loc, array_index);
+   _mesa_uniform_split_location_offset(shProg, location, loc, array_index);
 
    if (*loc >= shProg->NumUserUniformStorage) {
       _mesa_error(ctx, GL_INVALID_OPERATION, "%s(location=%d)",

src/mesa/main/uniforms.c

@@ -538,7 +538,7 @@ _mesa_GetUniformLocation(GLhandleARB programObj, const GLcharARB *name)
    if (shProg->UniformStorage[index].block_index != -1)
       return -1;
 
-   return _mesa_uniform_merge_location_offset(index, offset);
+   return _mesa_uniform_merge_location_offset(shProg, index, offset);
 }
 
 GLuint GLAPIENTRY

src/mesa/main/uniforms.h

@@ -269,20 +269,24 @@ struct gl_builtin_uniform_desc {
  * Combine the uniform's base location and the offset
  */
 static inline GLint
-_mesa_uniform_merge_location_offset(unsigned base_location, unsigned offset)
+_mesa_uniform_merge_location_offset(const struct gl_shader_program *prog,
+                                    unsigned base_location, unsigned offset)
 {
-   return (base_location << 16) | offset;
+   assert(prog->UniformLocationBaseScale >= 0);
+   assert(offset < prog->UniformLocationBaseScale);
+   return (base_location * prog->UniformLocationBaseScale) + offset;
 }
 
 /**
  * Separate the uniform base location and parameter offset
  */
 static inline void
-_mesa_uniform_split_location_offset(GLint location, unsigned *base_location,
+_mesa_uniform_split_location_offset(const struct gl_shader_program *prog,
+                                    GLint location, unsigned *base_location,
 				    unsigned *offset)
 {
-   *offset = location & 0xffff;
-   *base_location = location >> 16;
+   *offset = location % prog->UniformLocationBaseScale;
+   *base_location = location / prog->UniformLocationBaseScale;
 }
 /*@}*/
 

src/mesa/main/version.c

@@ -101,6 +101,9 @@ create_version_string(struct gl_context *ctx, const char *prefix)
    if (ctx->VersionString) {
       _mesa_snprintf(ctx->VersionString, max,
 		     "%s%u.%u%s Mesa " PACKAGE_VERSION
+#ifdef MESA_VERSION_STRING_EXTRA
+		     " " MESA_VERSION_STRING_EXTRA
+#endif
 #ifdef MESA_GIT_SHA1
 		     " (" MESA_GIT_SHA1 ")"
 #endif

src/mesa/state_tracker/st_glsl_to_tgsi.cpp

@@ -3096,7 +3096,7 @@ set_uniform_initializer(struct gl_context *ctx, void *mem_ctx,
         	"Couldn't find uniform for initializer %s\n", name);
       return;
    }
-   int loc = _mesa_uniform_merge_location_offset(index, offset);
+   int loc = _mesa_uniform_merge_location_offset(shader_program, index, offset);
 
    for (unsigned int i = 0; i < (type->is_array() ? type->length : 1); i++) {
       ir_constant *element;