docs: Add mesa 18.1.7 docs

bump version for 18.1.7 release
r600/eg: rework atomic counter emission with flushes
2018-08-23 09:39:20 -07:00 · 2018-08-23 09:34:54 -07:00 · 2018-08-22 08:46:19 -07:00 · 2018-08-22 08:46:00 -07:00 · 2018-08-21 08:25:00 -07:00 · 2018-08-21 08:23:16 -07:00
21 changed files with 223 additions and 61 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-18.1.6
+18.1.7
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -56,3 +56,18 @@ ccbe33af5b086f4b488ac7ca8a8a45ebc9ac189c
 f2c0d310d6efe560de8192ab468ba02d50c9ac1e
 50a8713d4f90a6c70a23f9f5871420371df283a7
 1561e4984eb03d6946d19b820b83a96bbbd83b98
+66e12451ac4e4e1c05a48b2cd2b0d3186f779f20
+73b342c7a52a93d283799800824311639f372de0
+71d5b2fbf83061a1319141d26942771e8c75ff2b
+011a811652c74dcc9f56506ebb6075e4bdfe6ef9
+f3a78a9da01218df0067b24b52204a4e5f01bc69
+f9e8456c39136aa41f85f82758a00e5aa2aab334
+0aacb5eab6120aa1410966d23101e16eea3fbcd7
+a4a104fc81e93555899050efac23c3cd6ba762ab
+24ee53231da84a1be5ec08abebe8a2ff6aa019ca
+4c43ec461de4f122d5d6566361d064c816e4ef69
+
+# These have more than one fixes tag and generate a warning
+#
+24839663a40257e0468406d72c48d431b5ae2bd4
+6ff1c479968819b93c46d24bd898e89ce14ac401
--- a/docs/relnotes/18.1.6.html
+++ b/docs/relnotes/18.1.6.html
@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+580e03328ffefe1fd43b19ab7669f20d931601a1c0a4c0f8b9c65d6e81a06df3  mesa-18.1.6.tar.gz
+bb7ce759069801804fcfb8152da3457f76cd7b4e0096e4870ff5adcb5c894289  mesa-18.1.6.tar.xz
 </pre>


--- a/docs/relnotes/18.1.7.html
+++ b/docs/relnotes/18.1.7.html
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.7 Release Notes / August 24 2018</h1>
+
+<p>
+Mesa 18.1.7 is a bug fix release which fixes bugs found since the 18.1.6 release.
+</p>
+<p>
+Mesa 18.1.7 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105975">Bug 105975</a> - i965 always reports 0 viewport subpixel bits</li>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107098">Bug 107098</a> - Segfault after munmap(kms_sw_dt-&gt;ro_mapped)</li>
+</ul>
+
+<h2>Changes</h2>
+<p>Alexander Tsoy (1):</p>
+<ul>
+  <li>meson: fix build for egl platform_x11 without dri3 and gbm</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+  <li>radv: Fix missing Android platform define.</li>
+</ul>
+
+<p>Danylo Piliaiev (1):</p>
+<ul>
+  <li>i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>r600/eg: rework atomic counter emission with flushes</li>
+</ul>
+
+<p>Dylan Baker (7):</p>
+<ul>
+  <li>docs: Add sha256 sums for 18.1.6</li>
+  <li>cherry-ignore: Add additional 18.2 only patches</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: Add a couple of patches with &gt; 1 fixes tags</li>
+  <li>cherry-ignore: more 18.2 patches</li>
+  <li>bump version for 18.1.7 release</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>intel: Switch the order of the 2x MSAA sample positions</li>
+  <li>anv/lower_ycbcr: Use the binding array size for bounds checks</li>
+</ul>
+
+<p>Ray Strode (1):</p>
+<ul>
+  <li>gallium/winsys/kms: don't unmap what wasn't mapped</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+  <li>radv/winsys: fix creating the BO list for virtual buffers</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>radv: add Doom workaround</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -104,7 +104,7 @@ VULKAN_LIB_DEPS += \
 endif

 if HAVE_PLATFORM_ANDROID
-AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
+AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR
 AM_CFLAGS += $(ANDROID_CFLAGS)
 VULKAN_LIB_DEPS += $(ANDROID_LIBS)
 VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -432,6 +432,9 @@ radv_handle_per_app_options(struct radv_instance *instance,
 		 * and it gives few more FPS.
 		 */
 		instance->perftest_flags |= RADV_PERFTEST_SISCHED;
+	} else if (!strcmp(name, "DOOM_VFR")) {
+		/* Work around a Doom VFR game bug */
+		instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
 	}
 }

--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -692,7 +692,7 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 			if (!cs->num_buffers)
 				continue;

-			if (unique_bo_count == 0) {
+			if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
 				memcpy(handles, cs->handles, cs->num_buffers * sizeof(amdgpu_bo_handle));
 				memcpy(priorities, cs->priorities, cs->num_buffers * sizeof(uint8_t));
 				unique_bo_count = cs->num_buffers;
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -99,6 +99,7 @@ endif

 if with_platform_x11
  files_egl += files('drivers/dri2/platform_x11.c')
+  incs_for_egl += inc_loader
  if with_dri3
    files_egl += files('drivers/dri2/platform_x11_dri3.c')
    link_for_egl += libloader_dri3_helper
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -715,7 +715,6 @@ static void compute_emit_cs(struct r600_context *rctx,
 		rctx->cmd_buf_is_compute = true;
 	}

-	r600_need_cs_space(rctx, 0, true);
 	if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI) {
 		r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty);
 		current = rctx->cs_shader_state.shader->sel->current;
@@ -742,16 +741,22 @@ static void compute_emit_cs(struct r600_context *rctx,
 		}
 		rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0;
 		rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
+
+		evergreen_emit_atomic_buffer_setup_count(rctx, current, combined_atomics, &atomic_used_mask);
+		r600_need_cs_space(rctx, 0, true, util_bitcount(atomic_used_mask));
+
 		if (need_buf_const) {
 			eg_setup_buffer_constants(rctx, PIPE_SHADER_COMPUTE);
 		}
 		r600_update_driver_const_buffers(rctx, true);

-		if (evergreen_emit_atomic_buffer_setup(rctx, current, combined_atomics, &atomic_used_mask)) {
+		evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, atomic_used_mask);
+		if (atomic_used_mask) {
 			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 			radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
 		}
-	}
+	} else
+		r600_need_cs_space(rctx, 0, true, 0);

 	/* Initialize all the compute-related registers.
 	 *
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -111,7 +111,7 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,

 		r600_need_cs_space(rctx,
 				   10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) +
-				   R600_MAX_PFP_SYNC_ME_DWORDS, FALSE);
+				   R600_MAX_PFP_SYNC_ME_DWORDS, FALSE, 0);

 		/* Flush the caches for the first copy only. */
 		if (rctx->b.flags) {
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3978,7 +3978,6 @@ static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,

 		if (!buffers || !buffers[idx].buffer) {
 			pipe_resource_reference(&abuf->buffer, NULL);
-			astate->enabled_mask &= ~(1 << i);
 			continue;
 		}
 		buf = &buffers[idx];
@@ -3986,7 +3985,6 @@ static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
 		pipe_resource_reference(&abuf->buffer, buf->buffer);
 		abuf->buffer_offset = buf->buffer_offset;
 		abuf->buffer_size = buf->buffer_size;
-		astate->enabled_mask |= (1 << i);
 	}
 }

@@ -4816,20 +4814,15 @@ static void cayman_write_count_to_gds(struct r600_context *rctx,
 	radeon_emit(cs, reloc);
 }

-bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
-					struct r600_pipe_shader *cs_shader,
-					struct r600_shader_atomic *combined_atomics,
-					uint8_t *atomic_used_mask_p)
+void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
+					      struct r600_pipe_shader *cs_shader,
+					      struct r600_shader_atomic *combined_atomics,
+					      uint8_t *atomic_used_mask_p)
 {
-	struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
-	unsigned pkt_flags = 0;
 	uint8_t atomic_used_mask = 0;
 	int i, j, k;
 	bool is_compute = cs_shader ? true : false;

-	if (is_compute)
-		pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
-
 	for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
 		uint8_t num_atomic_stage;
 		struct r600_pipe_shader *pshader;
@@ -4862,8 +4855,25 @@ bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
 			}
 		}
 	}
+	*atomic_used_mask_p = atomic_used_mask;
+}
+
+void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
+					bool is_compute,
+					struct r600_shader_atomic *combined_atomics,
+					uint8_t atomic_used_mask)
+{
+	struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
+	unsigned pkt_flags = 0;
+	uint32_t mask;
+
+	if (is_compute)
+		pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
+
+	mask = atomic_used_mask;
+	if (!mask)
+		return;

-	uint32_t mask = atomic_used_mask;
 	while (mask) {
 		unsigned atomic_index = u_bit_scan(&mask);
 		struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
@@ -4875,8 +4885,6 @@ bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
 		else
 			evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
 	}
-	*atomic_used_mask_p = atomic_used_mask;
-	return true;
 }

 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
@@ -4888,7 +4896,7 @@ void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
 	struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
 	uint32_t pkt_flags = 0;
 	uint32_t event = EVENT_TYPE_PS_DONE;
-	uint32_t mask = astate->enabled_mask;
+	uint32_t mask;
 	uint64_t dst_offset;
 	unsigned reloc;

--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -31,7 +31,7 @@


 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
-			boolean count_draw_in)
+			boolean count_draw_in, unsigned num_atomics)
 {
 	/* Flush the DMA IB if it's not empty. */
 	if (radeon_emitted(ctx->b.dma.cs, 0))
@@ -61,6 +61,9 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 		num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
 	}

+	/* add atomic counters, 8 pre + 8 post per counter + 16 post if any counters */
+	num_dw += (num_atomics * 16) + (num_atomics ? 16 : 0);
+
 	/* Count in r600_suspend_queries. */
 	num_dw += ctx->b.num_cs_dw_queries_suspend;

@@ -526,7 +529,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,

 		r600_need_cs_space(rctx,
 				   10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) +
-				   3 + R600_MAX_PFP_SYNC_ME_DWORDS, FALSE);
+				   3 + R600_MAX_PFP_SYNC_ME_DWORDS, FALSE, 0);

 		/* Flush the caches for the first copy only. */
 		if (rctx->b.flags) {
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -446,8 +446,6 @@ struct r600_shader_state {
 };

 struct r600_atomic_buffer_state {
-	uint32_t enabled_mask;
-	uint32_t dirty_mask;
 	struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
 };

@@ -771,7 +769,7 @@ void r600_context_gfx_flush(void *context, unsigned flags,
 			    struct pipe_fence_handle **fence);
 void r600_begin_new_cs(struct r600_context *ctx);
 void r600_flush_emit(struct r600_context *ctx);
-void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in, unsigned num_atomics);
 void r600_emit_pfp_sync_me(struct r600_context *rctx);
 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 			     struct pipe_resource *dst, uint64_t dst_offset,
@@ -1065,10 +1063,14 @@ void r600_delete_shader_selector(struct pipe_context *ctx,
 				 struct r600_pipe_shader_selector *sel);

 struct r600_shader_atomic;
-bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
-					struct r600_pipe_shader *cs_shader,
+void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
+					      struct r600_pipe_shader *cs_shader,
+					      struct r600_shader_atomic *combined_atomics,
+					      uint8_t *atomic_used_mask_p);
+void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
+					bool is_compute,
 					struct r600_shader_atomic *combined_atomics,
-					uint8_t *atomic_used_mask_p);
+					uint8_t atomic_used_mask);
 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
 				       bool is_compute,
 				       struct r600_shader_atomic *combined_atomics,
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2083,8 +2083,9 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		: (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
 		: info->mode;

-	if (rctx->b.chip_class >= EVERGREEN)
-		evergreen_emit_atomic_buffer_setup(rctx, NULL, combined_atomics, &atomic_used_mask);
+	if (rctx->b.chip_class >= EVERGREEN) {
+		evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask);
+	}

 	if (index_size) {
 		index_offset += info->start * index_size;
@@ -2170,7 +2171,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		evergreen_setup_tess_constants(rctx, info, &num_patches);

 	/* Emit states. */
-	r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE);
+	r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE, util_bitcount(atomic_used_mask));
 	r600_flush_emit(rctx);

 	mask = rctx->dirty_atoms;
@@ -2178,6 +2179,10 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
 	}

+	if (rctx->b.chip_class >= EVERGREEN) {
+		evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask);
+	}
+		
 	if (rctx->b.chip_class == CAYMAN) {
 		/* Copied from radeonsi. */
 		unsigned primgroup_size = 128; /* recommended without a GS */
@@ -3282,7 +3287,7 @@ static void r600_set_active_query_state(struct pipe_context *ctx, boolean enable
 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
                                   bool include_draw_vbo)
 {
-	r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
+	r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo, 0);
 }

 /* keep this at the end of this file, please */
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -176,6 +176,8 @@ kms_sw_displaytarget_create(struct sw_winsys *ws,

   list_inithead(&kms_sw_dt->planes);
   kms_sw_dt->ref_count = 1;
+   kms_sw_dt->mapped = MAP_FAILED;
+   kms_sw_dt->ro_mapped = MAP_FAILED;

   kms_sw_dt->format = format;

@@ -262,7 +264,7 @@ kms_sw_displaytarget_map(struct sw_winsys *ws,

   prot = (flags == PIPE_TRANSFER_READ) ? PROT_READ : (PROT_READ | PROT_WRITE);
   void **ptr = (flags == PIPE_TRANSFER_READ) ? &kms_sw_dt->ro_mapped : &kms_sw_dt->mapped;
-   if (!*ptr) {
+   if (*ptr == MAP_FAILED) {
      void *tmp = mmap(0, kms_sw_dt->size, prot, MAP_SHARED,
                       kms_sw->fd, map_req.offset);
      if (tmp == MAP_FAILED)
@@ -332,6 +334,8 @@ kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys *kms_sw, int fd,
      FREE(kms_sw_dt);
      return NULL;
   }
+   kms_sw_dt->mapped = MAP_FAILED;
+   kms_sw_dt->ro_mapped = MAP_FAILED;
   kms_sw_dt->size = lseek_ret;
   kms_sw_dt->ref_count = 1;
   kms_sw_dt->handle = handle;
@@ -368,10 +372,14 @@ kms_sw_displaytarget_unmap(struct sw_winsys *ws,
   DEBUG_PRINT("KMS-DEBUG: unmapped buffer %u (was %p)\n", kms_sw_dt->handle, kms_sw_dt->mapped);
   DEBUG_PRINT("KMS-DEBUG: unmapped buffer %u (was %p)\n", kms_sw_dt->handle, kms_sw_dt->ro_mapped);

-   munmap(kms_sw_dt->mapped, kms_sw_dt->size);
-   kms_sw_dt->mapped = NULL;
-   munmap(kms_sw_dt->ro_mapped, kms_sw_dt->size);
-   kms_sw_dt->ro_mapped = NULL;
+   if (kms_sw_dt->mapped != MAP_FAILED) {
+      munmap(kms_sw_dt->mapped, kms_sw_dt->size);
+      kms_sw_dt->mapped = MAP_FAILED;
+   }
+   if (kms_sw_dt->ro_mapped != MAP_FAILED) {
+      munmap(kms_sw_dt->ro_mapped, kms_sw_dt->size);
+      kms_sw_dt->ro_mapped = MAP_FAILED;
+   }
 }

 static struct sw_displaytarget *
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -798,6 +798,14 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
       * grid of samples with in a pixel. Sample number layout shows the
       * rectangular grid of samples roughly corresponding to the real sample
       * locations with in a pixel.
+       *
+       * In the case of 2x MSAA, the layout of sample indices is reversed from
+       * the layout of sample numbers:
+       *
+       * sample index layout :  ---------    sample number layout :  ---------
+       *                        | 0 | 1 |                            | 1 | 0 |
+       *                        ---------                            ---------
+       *
       * In case of 4x MSAA, layout of sample indices matches the layout of
       * sample numbers:
       *           ---------
@@ -841,7 +849,9 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
                                            key->x_scale * key->y_scale));
      sample = nir_f2i32(b, sample);

-      if (tex_samples == 8) {
+      if (tex_samples == 2) {
+         sample = nir_isub(b, nir_imm_int(b, 1), sample);
+      } else if (tex_samples == 8) {
         sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
                                       nir_ishl(b, sample, nir_imm_int(b, 2))),
                           nir_imm_int(b, 0xf));
--- a/src/intel/common/gen_sample_positions.h
+++ b/src/intel/common/gen_sample_positions.h
@@ -42,10 +42,10 @@ prefix##0YOffset   = 0.5;
 * c   1
 */
 #define GEN_SAMPLE_POS_2X(prefix) \
-prefix##0XOffset   = 0.25; \
-prefix##0YOffset   = 0.25; \
-prefix##1XOffset   = 0.75; \
-prefix##1YOffset   = 0.75;
+prefix##0XOffset   = 0.75; \
+prefix##0YOffset   = 0.75; \
+prefix##1XOffset   = 0.25; \
+prefix##1YOffset   = 0.25;

 /**
 * Sample positions:
--- a/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
+++ b/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
@@ -337,18 +337,16 @@ try_lower_tex_ycbcr(struct anv_pipeline_layout *layout,
   if (binding->immutable_samplers == NULL)
      return false;

-   unsigned texture_index = tex->texture_index;
+   assert(tex->texture_index == 0);
+   unsigned array_index = 0;
   if (tex->texture->deref.child) {
      assert(tex->texture->deref.child->deref_type == nir_deref_type_array);
      nir_deref_array *deref_array = nir_deref_as_array(tex->texture->deref.child);
      if (deref_array->deref_array_type != nir_deref_array_type_direct)
         return false;
-      size_t hw_binding_size =
-         anv_descriptor_set_binding_layout_get_hw_size(binding);
-      texture_index += MIN2(deref_array->base_offset, hw_binding_size - 1);
+      array_index = MIN2(deref_array->base_offset, binding->array_size - 1);
   }
-   const struct anv_sampler *sampler =
-      binding->immutable_samplers[texture_index];
+   const struct anv_sampler *sampler = binding->immutable_samplers[array_index];

   if (sampler->conversion == NULL)
      return false;
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -688,7 +688,7 @@ brw_initialize_context_constants(struct brw_context *brw)
   /* ARB_viewport_array, OES_viewport_array */
   if (devinfo->gen >= 6) {
      ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS;
-      ctx->Const.ViewportSubpixelBits = 0;
+      ctx->Const.ViewportSubpixelBits = 8;

      /* Cast to float before negating because MaxViewportWidth is unsigned.
       */
--- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
+++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
@@ -38,13 +38,13 @@
 /**
 * 1x MSAA has a single sample at the center: (0.5, 0.5) -> (0x8, 0x8).
 *
- * 2x MSAA sample positions are (0.25, 0.25) and (0.75, 0.75):
+ * 2x MSAA sample positions are (0.75, 0.75) and (0.25, 0.25):
 *   4 c
- * 4 0
- * c   1
+ * 4 1
+ * c   0
 */
 static const uint32_t
-brw_multisample_positions_1x_2x = 0x0088cc44;
+brw_multisample_positions_1x_2x = 0x008844cc;

 /**
 * Sample positions:
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -68,10 +68,10 @@ gen6_get_sample_position(struct gl_context *ctx,
 * index layout in case of 2X and 4x MSAA, but they are different in
 * case of 8X MSAA.
 *
- * 2X MSAA sample index / number layout
- *           ---------
- *           | 0 | 1 |
- *           ---------
+ * 8X MSAA sample index layout    8x MSAA sample number layout
+ *           ---------                      ---------
+ *           | 0 | 1 |                      | 1 | 0 |
+ *           ---------                      ---------
 *
 * 4X MSAA sample index / number layout
 *           ---------
@@ -107,7 +107,7 @@ gen6_get_sample_position(struct gl_context *ctx,
 void
 gen6_set_sample_maps(struct gl_context *ctx)
 {
-   uint8_t map_2x[2] = {0, 1};
+   uint8_t map_2x[2] = {1, 0};
   uint8_t map_4x[4] = {0, 1, 2, 3};
   uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
   uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
Author	SHA1	Message	Date
Dylan Baker	ab384a10ce	docs: Add mesa 18.1.7 docs	2018-08-23 09:39:20 -07:00
Dylan Baker	9c5b4ca2f3	bump version for 18.1.7 release	2018-08-23 09:34:54 -07:00
Dave Airlie	97ecabee2d	r600/eg: rework atomic counter emission with flushes With the current code, we didn't do the space checks prior to atomic counter setup emission, but we also didn't add atomic counters to the space check so we could get a flush later as well. These flushes would be bad, and lead to problems with parallel tests. We have to ensure the atomic counter copy in, draw emits and counter copy out are kept in the same command submission unit. This reworks the code to drop some useless masks, make the counting separate to the emits, and make the space checker handle atomic counter space. [airlied: want this in 18.2] Fixes: `06993e4ee` (r600: add support for hw atomic counters. (v3)) (cherry picked from commit `32529e6084`)	2018-08-22 08:46:19 -07:00
Dylan Baker	cafb53fe4d	cherry-ignore: more 18.2 patches	2018-08-22 08:46:00 -07:00
Danylo Piliaiev	3268ca90f0	i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+ We use floating-points for viewport bounds so VIEWPORT_SUBPIXEL_BITS should reflect this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105975 Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit `25ec806eb2`)	2018-08-21 08:25:00 -07:00
Dylan Baker	fb927b9a64	cherry-ignore: Add a couple of patches with > 1 fixes tags	2018-08-21 08:23:16 -07:00
Jason Ekstrand	5a90cc132b	anv/lower_ycbcr: Use the binding array size for bounds checks Because lower_ycbcr gets called before apply_pipeline_layout, the indices are all logical and the binding layout HW size is actually too big for the bounds check. We should just use the regular logical array size instead. Fixes: `f3e91e78a3` "anv: add nir lowering pass for ycbcr textures" Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit `320dacb0a0`)	2018-08-20 09:11:10 -07:00
Ray Strode	33acfb0780	gallium/winsys/kms: don't unmap what wasn't mapped At the moment, depending on pipe transfer flags, the dumb buffer map address can end up at either kms_sw_dt->ro_mapped or kms_sw_dt->mapped. When it's time to unmap the dumb buffer, both locations get unmapped, even though one is probably initialized to 0. That leads to the code segment getting unmapped at runtime and crashes when trying to call into unrelated code. This commit addresses the problem by using MAP_FAILED instead of NULL for ro_mapped and mapped when the dumb buffer is unmapped, and only unmapping mapped addresses at unmap time. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107098 Signed-off-by: Ray Strode <rstrode@redhat.com> Fixes: `d891f28df9` ("gallium/winsys/kms: Fix possible leak in map/unmap.") Cc: Lepton Wu <lepton@chromium.org> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `9baff597ce`)	2018-08-20 08:26:14 -07:00
Dylan Baker	7b7fbee00a	cherry-ignore: Add more 18.2 patches	2018-08-20 08:25:50 -07:00
Samuel Pitoiset	fe63541a70	radv/winsys: fix creating the BO list for virtual buffers When the number of unique BO is 0, we optimize the list creation by copying all buffers of the current CS directly into it. But this is only valid if the CS doesn't have virtual buffers, otherwise they are not added and hw might report VM faults. This fixes VM faults with: dEQP-VK.sparse_resources.image_sparse_binding.2d.rgba8ui.1024_128_1 CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit `d27e1584ce`)	2018-08-20 08:25:34 -07:00
Dylan Baker	b33a2fa911	cherry-ignore: Add more 18.2 patches	2018-08-16 14:24:37 -07:00
Timothy Arceri	0936b87324	radv: add Doom workaround Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit `f0a8accb0d`) Conflicts resolved by Dylan Conflicts: src/amd/vulkan/radv_device.c	2018-08-16 14:23:48 -07:00
Alexander Tsoy	8143fefa10	meson: fix build for egl platform_x11 without dri3 and gbm Compiling EGL's platform_x11 without dri3 and gbm yields this compile failure: platform_x11 needs inc_loader: ../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal error: loader.h: No such file or directory #include "loader.h" ^~~~~~~~~~ Fixes: `108d257a16` ("meson: build libEGL") Bugzilla: https://bugs.gentoo.org/663534 Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit `9a96bf0ecd`)	2018-08-16 14:22:42 -07:00
Dylan Baker	cf7f783f35	cherry-ignore: Add additional 18.2 only patches	2018-08-15 09:06:09 -07:00
Bas Nieuwenhuizen	ee595b275c	radv: Fix missing Android platform define. CC: <mesa-stable@lists.freedesktop.org> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit `bf33ca7512`) Conflicts resolved by Dylan Conflicts: src/amd/vulkan/Android.mk There is no android.mk support in 18.1 for radv, so only apply the parts for autotools android builds, which can be used by android implementations not using android.mk files	2018-08-15 09:01:03 -07:00
Jason Ekstrand	1f06f0e850	intel: Switch the order of the 2x MSAA sample positions The Vulkan 1.1.82 spec flipped the order to better match D3D. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (cherry picked from commit `a9f7bcfdf9`)	2018-08-13 10:08:44 -07:00
Dylan Baker	3f2388e21a	docs: Add sha256 sums for 18.1.6	2018-08-13 09:56:25 -07:00
@@ -1 +1 @@
 .1.6
 .1.7