Add release notes for the 10.5.3 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

Makefile.am

@@ -21,7 +21,7 @@
 
 SUBDIRS = src
 
-DISTCHECK_CONFIGURE_FLAGS = \
+AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-dri3 \
 	--enable-gallium-tests \
 	--enable-gbm \
@@ -49,6 +49,7 @@ noinst_HEADERS =					\
 	include/c99					\
 	include/c11					\
 	include/D3D9					\
+	include/VG					\
 	include/HaikuGL					\
 	include/pci_ids
 

VERSION

@@ -1 +1 @@
-10.5.0-devel
+10.5.3

bin/.cherry-ignore

@@ -0,0 +1,26 @@
+# Cherry-picked without -x
+# nir: resolve nir.h dependency list (fix make distcheck)
+556fc4b84df99a1cd4b18c11fb16f7854a948b2a 
+
+# nir: add missing header to the sources list
+72e602905dd9d86450a936d5a22bf21758844b38
+
+# configure: rework wayland_scanner handling(fix make distcheck)
+153539bd9d4445b504110958306f00632222f840
+
+# auxiliary/vl: bring back the VL code for the dri targets
+c39dbfdd0f764b1aaa7319b4694e7335692993dd
+
+# mesa: rename format_info.c to format_info.h
+3f6c28f2a976e35128b7a4a513cfa60af00301e1
+# mesa: fix dependency tracking of generated sources
+d22391cb165af4ed2f9a9e5d6233072a432cc969
+# mesa: drop Makefile from get_hash.h dependency list
+2c0f72d5389a9838cc4fbf4cc4f4291aa56c7845
+# mapi: fix *glapi dependency tracking
+fe5fddd7e2df74233a2a02ae021418485f39d11c
+# xmlpool: make sure we ship options.h
+8d8ca64c28170ec7e9ffa01638bcf8fd30a96088
+
+# The optimisations mentioned are not available in 10.5
+627c68308683abbd6e563a09af6013a33938a790 i965/fs: in MAD optimizations, switch last argument to be immediate

configure.ac

@@ -9,7 +9,6 @@ dnl Copyright © 2009-2014 Jon TURNEY
 dnl Copyright © 2011-2012 Benjamin Franzke
 dnl Copyright © 2008-2014 David Airlie
 dnl Copyright © 2009-2013 Brian Paul
-dnl Copyright © 2003-2007 Keith Packard, Daniel Stone
 dnl
 dnl Permission is hereby granted, free of charge, to any person obtaining a
 dnl copy of this software and associated documentation files (the "Software"),
@@ -79,6 +78,7 @@ XCBDRI2_REQUIRED=1.8
 XCBGLX_REQUIRED=1.8.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
+PYTHON_MAKO_REQUIRED=0.3.4
 
 dnl Check for progs
 AC_PROG_CPP
@@ -114,7 +114,19 @@ if test "x$INDENT" != "xcat"; then
     fi
 fi
 
-AX_CHECK_PYTHON_MAKO_MODULE(0.3.4)
+AX_CHECK_PYTHON_MAKO_MODULE($PYTHON_MAKO_REQUIRED)
+
+if test -z "$PYTHON2"; then
+    if test ! -f "$srcdir/src/util/format_srgb.c"; then
+        AC_MSG_ERROR([Python not found - unable to generate sources])
+    fi
+else
+    if test "x$acv_mako_found" = xno; then
+        if test ! -f "$srcdir/src/mesa/main/format_unpack.c"; then
+            AC_MSG_ERROR([Python mako module v$PYTHON_MAKO_REQUIRED or higher not found])
+        fi
+    fi
+fi
 
 AC_PROG_INSTALL
 
@@ -935,144 +947,6 @@ fi
 
 AC_SUBST([MESA_LLVM])
 
-# SHA1 hashing
-AC_ARG_WITH([sha1],
-        [AS_HELP_STRING([--with-sha1=libc|libmd|libnettle|libgcrypt|libcrypto|libsha1|CommonCrypto|CryptoAPI],
-        [choose SHA1 implementation])])
-case "x$with_sha1" in
-x | xlibc | xlibmd | xlibnettle | xlibgcrypt | xlibcrypto | xlibsha1 | xCommonCrypto | xCryptoAPI)
-  ;;
-*)
-        AC_MSG_ERROR([Illegal value for --with-sha1: $with_sha1])
-esac
-
-AC_CHECK_FUNC([SHA1Init], [HAVE_SHA1_IN_LIBC=yes])
-if test "x$with_sha1" = x && test "x$HAVE_SHA1_IN_LIBC" = xyes; then
-	with_sha1=libc
-fi
-if test "x$with_sha1" = xlibc && test "x$HAVE_SHA1_IN_LIBC" != xyes; then
-	AC_MSG_ERROR([sha1 in libc requested but not found])
-fi
-if test "x$with_sha1" = xlibc; then
-	AC_DEFINE([HAVE_SHA1_IN_LIBC], [1],
-		[Use libc SHA1 functions])
-	SHA1_LIBS=""
-fi
-AC_CHECK_FUNC([CC_SHA1_Init], [HAVE_SHA1_IN_COMMONCRYPTO=yes])
-if test "x$with_sha1" = x && test "x$HAVE_SHA1_IN_COMMONCRYPTO" = xyes; then
-	with_sha1=CommonCrypto
-fi
-if test "x$with_sha1" = xCommonCrypto && test "x$HAVE_SHA1_IN_COMMONCRYPTO" != xyes; then
-	AC_MSG_ERROR([CommonCrypto requested but not found])
-fi
-if test "x$with_sha1" = xCommonCrypto; then
-	AC_DEFINE([HAVE_SHA1_IN_COMMONCRYPTO], [1],
-		[Use CommonCrypto SHA1 functions])
-	SHA1_LIBS=""
-fi
-dnl stdcall functions cannot be tested with AC_CHECK_LIB
-AC_CHECK_HEADER([wincrypt.h], [HAVE_SHA1_IN_CRYPTOAPI=yes], [], [#include <windows.h>])
-if test "x$with_sha1" = x && test "x$HAVE_SHA1_IN_CRYPTOAPI" = xyes; then
-	with_sha1=CryptoAPI
-fi
-if test "x$with_sha1" = xCryptoAPI && test "x$HAVE_SHA1_IN_CRYPTOAPI" != xyes; then
-	AC_MSG_ERROR([CryptoAPI requested but not found])
-fi
-if test "x$with_sha1" = xCryptoAPI; then
-	AC_DEFINE([HAVE_SHA1_IN_CRYPTOAPI], [1],
-		[Use CryptoAPI SHA1 functions])
-	SHA1_LIBS=""
-fi
-AC_CHECK_LIB([md], [SHA1Init], [HAVE_LIBMD=yes])
-if test "x$with_sha1" = x && test "x$HAVE_LIBMD" = xyes; then
-	with_sha1=libmd
-fi
-if test "x$with_sha1" = xlibmd && test "x$HAVE_LIBMD" != xyes; then
-	AC_MSG_ERROR([libmd requested but not found])
-fi
-if test "x$with_sha1" = xlibmd; then
-	AC_DEFINE([HAVE_SHA1_IN_LIBMD], [1],
-	          [Use libmd SHA1 functions])
-	SHA1_LIBS=-lmd
-fi
-PKG_CHECK_MODULES([LIBSHA1], [libsha1], [HAVE_LIBSHA1=yes], [HAVE_LIBSHA1=no])
-if test "x$with_sha1" = x && test "x$HAVE_LIBSHA1" = xyes; then
-   with_sha1=libsha1
-fi
-if test "x$with_sha1" = xlibsha1 && test "x$HAVE_LIBSHA1" != xyes; then
-	AC_MSG_ERROR([libsha1 requested but not found])
-fi
-if test "x$with_sha1" = xlibsha1; then
-	AC_DEFINE([HAVE_SHA1_IN_LIBSHA1], [1],
-	          [Use libsha1 for SHA1])
-	SHA1_LIBS=-lsha1
-fi
-AC_CHECK_LIB([nettle], [nettle_sha1_init], [HAVE_LIBNETTLE=yes])
-if test "x$with_sha1" = x && test "x$HAVE_LIBNETTLE" = xyes; then
-	with_sha1=libnettle
-fi
-if test "x$with_sha1" = xlibnettle && test "x$HAVE_LIBNETTLE" != xyes; then
-	AC_MSG_ERROR([libnettle requested but not found])
-fi
-if test "x$with_sha1" = xlibnettle; then
-	AC_DEFINE([HAVE_SHA1_IN_LIBNETTLE], [1],
-	          [Use libnettle SHA1 functions])
-	SHA1_LIBS=-lnettle
-fi
-AC_CHECK_LIB([gcrypt], [gcry_md_open], [HAVE_LIBGCRYPT=yes])
-if test "x$with_sha1" = x && test "x$HAVE_LIBGCRYPT" = xyes; then
-	with_sha1=libgcrypt
-fi
-if test "x$with_sha1" = xlibgcrypt && test "x$HAVE_LIBGCRYPT" != xyes; then
-	AC_MSG_ERROR([libgcrypt requested but not found])
-fi
-if test "x$with_sha1" = xlibgcrypt; then
-	AC_DEFINE([HAVE_SHA1_IN_LIBGCRYPT], [1],
-	          [Use libgcrypt SHA1 functions])
-	SHA1_LIBS=-lgcrypt
-fi
-# We don't need all of the OpenSSL libraries, just libcrypto
-AC_CHECK_LIB([crypto], [SHA1_Init], [HAVE_LIBCRYPTO=yes])
-PKG_CHECK_MODULES([OPENSSL], [openssl], [HAVE_OPENSSL_PKC=yes],
-                  [HAVE_OPENSSL_PKC=no])
-if test "x$HAVE_LIBCRYPTO" = xyes || test "x$HAVE_OPENSSL_PKC" = xyes; then
-	if test "x$with_sha1" = x; then
-		with_sha1=libcrypto
-	fi
-else
-	if test "x$with_sha1" = xlibcrypto; then
-		AC_MSG_ERROR([OpenSSL libcrypto requested but not found])
-	fi
-fi
-if test "x$with_sha1" = xlibcrypto; then
-	if test "x$HAVE_LIBCRYPTO" = xyes; then
-		SHA1_LIBS=-lcrypto
-	else
-		SHA1_LIBS="$OPENSSL_LIBS"
-		SHA1_CFLAGS="$OPENSSL_CFLAGS"
-	fi
-fi
-AC_MSG_CHECKING([for SHA1 implementation])
-AC_MSG_RESULT([$with_sha1])
-AC_SUBST(SHA1_LIBS)
-AC_SUBST(SHA1_CFLAGS)
-
-# Allow user to configure out the shader-cache feature
-AC_ARG_ENABLE([shader-cache],
-    AS_HELP_STRING([--disable-shader-cache], [Disable binary shader cache]),
-    [enable_shader_cache="$enableval"],
-    [if test "x$with_sha1" != "x"; then
-        enable_shader_cache=yes
-     else
-        enable_shader_cache=no
-     fi])
-if test "x$with_sha1" = "x"; then
-    if test "x$enable_shader_cache" = "xyes"; then
-        AC_MSG_ERROR([Cannot enable shader cache (no SHA-1 implementation found)])
-    fi
-fi
-AM_CONDITIONAL([ENABLE_SHADER_CACHE], [test x$enable_shader_cache = xyes])
-
 # Check for libdrm
 PKG_CHECK_MODULES([LIBDRM], [libdrm >= $LIBDRM_REQUIRED],
                   [have_libdrm=yes], [have_libdrm=no])
@@ -1572,14 +1446,23 @@ if test -n "$with_gallium_drivers" -a "x$with_gallium_drivers" != xswrast; then
     fi
 fi
 
+if test "x$enable_dri" = xyes -o \
+        "x$enable_xvmc" = xyes -o \
+        "x$enable_vdpau" = xyes -o \
+        "x$enable_omx" = xyes -o \
+        "x$enable_va" = xyes; then
+    need_gallium_vl=yes
+fi
+AM_CONDITIONAL(NEED_GALLIUM_VL, test "x$need_gallium_vl" = xyes)
+
 if test "x$enable_xvmc" = xyes -o \
         "x$enable_vdpau" = xyes -o \
         "x$enable_omx" = xyes -o \
         "x$enable_va" = xyes; then
     PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED])
-    need_gallium_vl=yes
+    need_gallium_vl_winsys=yes
 fi
-AM_CONDITIONAL(NEED_GALLIUM_VL, test "x$need_gallium_vl" = xyes)
+AM_CONDITIONAL(NEED_GALLIUM_VL_WINSYS, test "x$need_gallium_vl_winsys" = xyes)
 
 if test "x$enable_xvmc" = xyes; then
     PKG_CHECK_MODULES([XVMC], [xvmc >= $XVMC_REQUIRED])
@@ -1730,6 +1613,13 @@ if test "x$with_egl_platforms" != "x" -a "x$enable_egl" != xyes; then
     AC_MSG_ERROR([cannot build egl state tracker without EGL library])
 fi
 
+PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland_scanner],
+        WAYLAND_SCANNER=`$PKG_CONFIG --variable=wayland_scanner wayland_scanner`,
+        WAYLAND_SCANNER='')
+if test "x$WAYLAND_SCANNER" = x; then
+    AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner])
+fi
+
 # Do per-EGL platform setups and checks
 egl_platforms=`IFS=', '; echo $with_egl_platforms`
 for plat in $egl_platforms; do
@@ -1737,9 +1627,9 @@ for plat in $egl_platforms; do
 	wayland)
 		PKG_CHECK_MODULES([WAYLAND], [wayland-client >= $WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED])
 
-                WAYLAND_PREFIX=`$PKG_CONFIG --variable=prefix wayland-client`
+		if test "x$WAYLAND_SCANNER" = x; then
-                AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner],,
+			AC_MSG_ERROR([wayland-scanner is needed to compile the wayland egl platform])
-                             [${WAYLAND_PREFIX}/bin$PATH_SEPARATOR$PATH])
+		fi
 		;;
 
 	x11)
@@ -1770,7 +1660,7 @@ done
 # libEGL wants to default to the first platform specified in
 # ./configure.  parse that here.
 if test "x$egl_platforms" != "x"; then
-    FIRST_PLATFORM_CAPS=`echo $egl_platforms | sed 's| .*||' | tr 'a-z' 'A-Z'`
+    FIRST_PLATFORM_CAPS=`echo $egl_platforms | sed 's| .*||' | tr '[[a-z]]' '[[A-Z]]'`
     EGL_NATIVE_PLATFORM="_EGL_PLATFORM_$FIRST_PLATFORM_CAPS"
 else
     EGL_NATIVE_PLATFORM="_EGL_INVALID_PLATFORM"
@@ -2513,12 +2403,6 @@ else
     echo "        Gallium:         no"
 fi
 
-dnl Shader cache
-echo ""
-echo "        Shader cache:    $enable_shader_cache"
-if test "x$enable_shader_cache" = "xyes"; then
-    echo "        With SHA1 from:  $with_sha1"
-fi
 
 dnl Libraries
 echo ""

docs/relnotes/10.5.0.html

@@ -14,7 +14,7 @@
 <iframe src="../contents.html"></iframe>
 <div class="content">
 
-<h1>Mesa 10.5.0 Release Notes / TBD</h1>
+<h1>Mesa 10.5.0 Release Notes / March 06, 2015</h1>
 
 <p>
 Mesa 10.5.0 is a new development release.
@@ -31,9 +31,10 @@ because compatibility contexts are not supported.
 </p>
 
 
-<h2>MD5 checksums</h2>
+<h2>SHA256 checksums</h2>
 <pre>
-TBD.
+2bb6e2e982ee4d8264d52d638c2a4e3f8a164190336d72d4e34ae1304d87ed91  mesa-10.5.0.tar.gz
+d7ca9f9044bbdd674377e3eebceef1fae339c8817b9aa435c2053e4fea44e5d3  mesa-10.5.0.tar.xz
 </pre>
 
 
@@ -55,7 +56,150 @@ Note: some of the new features are only available with certain drivers.
 
 <h2>Bug fixes</h2>
 
-TBD.
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=10370">Bug 10370</a> - Incorrect pixels read back if draw bitmap texture through Display list</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45348">Bug 45348</a> - [swrast] piglit fbo-drawbuffers-arbfp regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60879">Bug 60879</a> - [radeonsi] X11 can't start with acceleration enabled</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=67672">Bug 67672</a> - [llvmpipe] lp_test_arit fails on old CPUs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=77544">Bug 77544</a> - i965: Try to use LINE instructions to perform MAD with immediate arguments</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78770">Bug 78770</a> - [SNB bisected]Webglc conformance/textures/texture-size-limit.html fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80568">Bug 80568</a> - [gen4] GPU Crash During Google Chrome Operation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82477">Bug 82477</a> - [softpipe] piglit fp-long-alu regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82585">Bug 82585</a> - geometry shader with optional out variable segfaults</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82991">Bug 82991</a> - Inverted bumpmap in webgl applications</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83463">Bug 83463</a> - [swrast] piglit glsl-vs-clamp-1 regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83500">Bug 83500</a> - si_dma_copy_tile causes GPU hangs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83510">Bug 83510</a> - Graphical glitches in Unreal Engine 4</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83908">Bug 83908</a> - [i965] Incorrect icon colors in Steam Big Picture</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=84212">Bug 84212</a> - [BSW]ES3-CTS.shaders.loops.do_while_dynamic_iterations.vector_counter_vertex fails and causes GPU hang</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=84651">Bug 84651</a> - Distorted graphics or black window when running Battle.net app on Intel hardware via wine</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=84777">Bug 84777</a> - [BSW]Piglit spec_glsl-1.50_execution_geometry-basic fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85367">Bug 85367</a> - [gen4] GPU hang in glmark-es2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85467">Bug 85467</a> - [llvmpipe] piglit gl-1.0-dlist-beginend failure with llvm-3.6.0svn</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85529">Bug 85529</a> - Surfaces not drawn in Unvanquished</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85647">Bug 85647</a> - Random radeonsi crashes with mesa 10.3.x</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85696">Bug 85696</a> - r600g+nine: Bioshock shader failure after 7b1c0cbc90d456384b0950ad21faa3c61a6b43ff</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86089">Bug 86089</a> - [r600g][mesa 10.4.0-dev] shader failure - r600_sb::bc_finalizer::cf_peephole() when starting Second Life</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86618">Bug 86618</a> - [NV96] neg modifiers not working in MIN and MAX operations</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86760">Bug 86760</a> - mesa doesn't build: recipe for target 'r600_llvm.lo' failed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86764">Bug 86764</a> - [SNB+ Bisected]Piglit glean/pointSprite fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86788">Bug 86788</a> - (bisected) 32bit UrbanTerror 4.1 timedemo sse4.1 segfault...</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86811">Bug 86811</a> - [BDW/BSW Bisected]Piglit spec_arb_shading_language_packing_execution_built-in-functions_vs-unpackSnorm4x8 fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86837">Bug 86837</a> - kodi segfault since auxiliary/vl: rework the build of the VL code</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86939">Bug 86939</a> - test_vf_float_conversions.cpp:63:12: error: expected primary-expression before ‘union’</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86944">Bug 86944</a> - glsl_parser_extras.cpp&quot;, line 1455: Error: Badly formed expression. (Oracle Studio)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86958">Bug 86958</a> - lp_bld_misc.cpp:503:40: error: no matching function for call to ‘llvm::EngineBuilder::setMCJITMemoryManager(ShaderMemoryManager*&amp;)’</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86969">Bug 86969</a> - _drm_intel_gem_bo_references() function takes half the CPU with Witcher2 game</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87076">Bug 87076</a> - Dead Island needs allow_glsl_extension_directive_midshader</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87516">Bug 87516</a> - glProgramBinary violates spec</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87619">Bug 87619</a> - Changes to state such as render targets change fragment shader without marking it dirty.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87658">Bug 87658</a> - [llvmpipe] SEGV in sse2_has_daz on ancient Pentium4-M</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87694">Bug 87694</a> - [SNB] Crash in brw_begin_transform_feedback</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87886">Bug 87886</a> - constant fps drops with Intel and Radeon</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87887">Bug 87887</a> - [i965 Bisected]ES2-CTS.gtf.GL.cos.cos_float_vert_xvary fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87913">Bug 87913</a> - CPU cacheline size of 0 can be returned by CPUID leaf 0x80000006 in some virtual machines</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88079">Bug 88079</a> - dEQP-GLES3.functional.fbo.completeness.renderable.renderbuffer.color0 tests fail due to enabling of GL_RGB and GL_RGBA</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88170">Bug 88170</a> - 32 bits opengl apps crash with latest llvm 3.6 git / mesa git / radeonsi</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88219">Bug 88219</a> - include/c11/threads_posix.h:197: undefined reference to `pthread_mutex_lock'</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88227">Bug 88227</a> - Radeonsi: High GTT usage in Prison Architect large map</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88248">Bug 88248</a> - Calling glClear while there is an occlusion query in progress messes up the results</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88335">Bug 88335</a> - format_pack.c:9567:22: error: expected ')'</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88385">Bug 88385</a> - [SNB+ Bisected]Ogles3conform ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels core dumped</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88467">Bug 88467</a> - nir.c:140: error: ‘nir_src’ has no member named ‘ssa’</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88478">Bug 88478</a> - #error &quot;&lt;malloc.h&gt; has been replaced by &lt;stdlib.h&gt;&quot;</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88519">Bug 88519</a> - sha1.c:210:22: error: 'grcy_md_hd_t' undeclared (first use in this function)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88523">Bug 88523</a> - sha1.c:37: error: 'SHA1_CTX' undeclared (first use in this function)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88561">Bug 88561</a> - [radeonsi][regression,bisected] Depth test/buffer issues in Portal</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88658">Bug 88658</a> - (bisected) Slow video playback on Kabini</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88662">Bug 88662</a> - unaligned access to gl_dlist_node</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88783">Bug 88783</a> - FTBFS: Clover: src/gallium/state_trackers/clover/llvm/invocation.cpp:335:49: error: no matching function for call to 'llvm::TargetLibraryInfo::TargetLibraryInfo(llvm::Triple)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88792">Bug 88792</a> - [BDW/BSW Bisected]Piglit spec_ARB_pixel_buffer_object_pbo-read-argb8888 fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88806">Bug 88806</a> - nir/nir_constant_expressions.c:2754:15: error: controlling expression type 'unsigned int' not compatible with any generic association type</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88841">Bug 88841</a> - [SNB/IVB/HSW/BDW Bisected]Piglit spec_EGL_NOK_texture_from_pixmap_basic fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88852">Bug 88852</a> - macros.h(181) : error C2143: syntax error : missing '{' before 'enum [tag]'</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88905">Bug 88905</a> - [SNB+ Bisected]Ogles3conform ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88930">Bug 88930</a> - [osmesa] osbuffer-&gt;textures should be indexed by attachment type</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88962">Bug 88962</a> - [osmesa] Crash on postprocessing if z buffer is NULL</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89032">Bug 89032</a> - [BDW/BSW/SKL Bisected]Piglit spec_OpenGL_1.1_infinite-spot-light fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89037">Bug 89037</a> - [SKL]Piglit spec_EXT_texture_array_copyteximage_1D_ARRAY_samples=2 sporadically causes GPU hang</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89068">Bug 89068</a> - glTexImage2D regression by texstore_rgba switch to _mesa_format_convert</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89069">Bug 89069</a> - Lack of grass in The Talos Principle on radeonsi (native\wine\nine)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89180">Bug 89180</a> - [IVB regression] Rendering issues in Mass Effect through VMware Workstation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86330">Bug 86330</a> - lp_bld_debug.cpp:112: multiple definition of `raw_debug_ostream::write_impl(char const*, unsigned long)'</li>
+
+</ul>
+
 
 <h2>Changes</h2>
 

docs/relnotes/10.5.1.html

@@ -0,0 +1,217 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.5.1 Release Notes / March 13, 2015</h1>
+
+<p>
+Mesa 10.5.1 is a bug fix release which fixes bugs found since the 10.5.0 release.
+</p>
+<p>
+Mesa 10.5.1 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+b5b6256a6d46023e16a675257fd11a0f94d7b3e60a76cf112952da3d0fef8e9b  mesa-10.5.1.tar.gz
+ffc51943d15c6812ee7611d053d8980a683fbd6a4986cff567b12cc66637d679  mesa-10.5.1.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79202">Bug 79202</a> - valgrind errors in glsl-fs-uniform-array-loop-unroll.shader_test; random code generation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=84613">Bug 84613</a> - [G965, bisected] piglit regressions : glslparsertest.glsl2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86747">Bug 86747</a> - Noise in Football Manager 2014 textures</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86974">Bug 86974</a> - INTEL_DEBUG=shader_time always asserts in fs_generator::generate_code() when Mesa is built with --enable-debug (= with asserts)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88246">Bug 88246</a> - Commit 2881b12 causes 43 DrawElements test regressions</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88793">Bug 88793</a> - [BDW/BSW Bisected]Piglit/shaders_glsl-max-varyings fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88883">Bug 88883</a> - ir-a2xx.c: variable changed in assert statement</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88885">Bug 88885</a> - Transform feedback uses incorrect interleaving if a previous draw did not write gl_Position</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89095">Bug 89095</a> - [SNB/IVB/BYT Bisected]Webglc conformance/glsl/functions/glsl-function-mix-float.html fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89156">Bug 89156</a> - r300g: GL_COMPRESSED_RED_RGTC1 / ATI1N support broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89224">Bug 89224</a> - Incorrect rendering of Unigine Valley running in VM on VMware Workstation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89292">Bug 89292</a> - [regression,bisected] incomplete screenshots in some cases</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89311">Bug 89311</a> - [regression, bisected] dEQP: Added entry points for glCompressedTextureSubImage*D.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89312">Bug 89312</a> - [regression, bisected] main: Added entry points for CopyTextureSubImage*D. (d6b7c40cecfe01)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89315">Bug 89315</a> - [HSW, regression, bisected] i965/fs: Emit MAD instructions when possible.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89317">Bug 89317</a> - [HSW, regression, bisected] i965: Add LINTERP/CINTERP to can_do_cmod() (d91390634)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89416">Bug 89416</a> - UE4Editor crash after load project</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89430">Bug 89430</a> - [g965][bisected] arb_copy_image-targets gl_texture* tests fail</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Andrey Sudnik (1):</p>
+<ul>
+  <li>i965/vec4: Don't lose the saturate modifier in copy propagation.</li>
+</ul>
+
+<p>Chris Forbes (1):</p>
+<ul>
+  <li>i965/gs: Check newly-generated GS-out VUE map against correct stage</li>
+</ul>
+
+<p>Daniel Stone (1):</p>
+<ul>
+  <li>egl: Take alpha bits into account when selecting GBM formats</li>
+</ul>
+
+<p>Emil Velikov (5):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.5.0 release</li>
+  <li>egl/main: no longer export internal function</li>
+  <li>cherry-ignore: ignore a few more commits picked without -x</li>
+  <li>mapi: fix commit 90411b56f6bc817e229d8801ac0adad6d4e3fb7a</li>
+  <li>Update version to 10.5.1</li>
+</ul>
+
+<p>Frank Henigman (1):</p>
+<ul>
+  <li>intel: fix EGLImage renderbuffer _BaseFormat</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>i965: Fix out-of-bounds accesses into pull_constant_loc array</li>
+</ul>
+
+<p>Ian Romanick (1):</p>
+<ul>
+  <li>i965/fs/nir: Use emit_math for nir_op_fpow</li>
+</ul>
+
+<p>Ilia Mirkin (3):</p>
+<ul>
+  <li>freedreno: move fb state copy after checking for size change</li>
+  <li>freedreno/ir3: fix array count returned by TXQ</li>
+  <li>freedreno/ir3: get the # of miplevels from getinfo</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>meta/TexSubImage: Stash everything other than PIXEL_TRANSFER/store in meta_begin</li>
+  <li>main/base_tex_format: Properly handle STENCIL_INDEX1/4/16</li>
+</ul>
+
+<p>Kenneth Graunke (8):</p>
+<ul>
+  <li>i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.</li>
+  <li>glsl: Mark array access when copying to a temporary for the ?: operator.</li>
+  <li>i965/fs: Set force_writemask_all on shader_time instructions.</li>
+  <li>i965/fs: Set smear on shader_time diff register.</li>
+  <li>i965/fs: Make emit_shader_time_write return rather than emit.</li>
+  <li>i965/fs: Make get_timestamp() pass back the MOV rather than emitting it.</li>
+  <li>i965/fs: Make emit_shader_time_end() insert before EOT.</li>
+  <li>i965/fs: Don't issue FB writes for bound but unwritten color targets.</li>
+</ul>
+
+<p>Laura Ekstrand (2):</p>
+<ul>
+  <li>main: Fix target checking for CompressedTexSubImage*D.</li>
+  <li>main: Fix target checking for CopyTexSubImage*D.</li>
+</ul>
+
+<p>Marc-Andre Lureau (1):</p>
+<ul>
+  <li>gallium/auxiliary/indices: fix start param</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>r300g: fix RGTC1 and LATC1 SNORM formats</li>
+  <li>r300g: fix a crash when resolving into an sRGB texture</li>
+  <li>r300g: fix sRGB-&gt;sRGB blits</li>
+</ul>
+
+<p>Matt Turner (12):</p>
+<ul>
+  <li>i965/vec4: Fix implementation of i2b.</li>
+  <li>mesa: Indent break statements and add a missing one.</li>
+  <li>mesa: Free memory allocated for luminance in readpixels.</li>
+  <li>mesa: Correct backwards NULL check.</li>
+  <li>i965: Consider scratch writes to have side effects.</li>
+  <li>i965/fs: Don't use backend_visitor::instructions after creating the CFG.</li>
+  <li>r300g: Use PATH_MAX instead of limiting ourselves to 100 chars.</li>
+  <li>r300g: Check return value of snprintf().</li>
+  <li>i965/fs: Don't propagate cmod to inst with different type.</li>
+  <li>i965: Tell intel_get_memcpy() which direction the memcpy() is going.</li>
+  <li>Revert SHA1 additions.</li>
+  <li>i965: Avoid applying negate to wrong MAD source.</li>
+</ul>
+
+<p>Neil Roberts (4):</p>
+<ul>
+  <li>meta: In pbo_{Get,}TexSubImage don't repeatedly rebind the source tex</li>
+  <li>Revert "common: Fix PBOs for 1D_ARRAY."</li>
+  <li>meta: Allow GL_UN/PACK_IMAGE_HEIGHT in _mesa_meta_pbo_Get/TexSubImage</li>
+  <li>meta: Fix the y offset for 1D_ARRAY in _mesa_meta_pbo_TexSubImage</li>
+</ul>
+
+<p>Rob Clark (11):</p>
+<ul>
+  <li>freedreno/ir3: fix silly typo for binning pass shaders</li>
+  <li>freedreno/a2xx: fix increment in assert</li>
+  <li>freedreno/a4xx: bit of cleanup</li>
+  <li>freedreno: update generated headers</li>
+  <li>freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properly</li>
+  <li>freedreno: update generated headers</li>
+  <li>freedreno/a4xx: aniso filtering</li>
+  <li>freedreno/ir3: fix up cat6 instruction encodings</li>
+  <li>freedreno/ir3: add support for memory (cat6) instructions</li>
+  <li>freedreno/ir3: handle flat bypass for a4xx</li>
+  <li>freedreno/ir3: fix failed assert in grouping</li>
+</ul>
+
+<p>Stefan Dösinger (1):</p>
+<ul>
+  <li>r300g: Fix the ATI1N swizzle (RGTC1 and LATC1)</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/10.5.2.html

@@ -0,0 +1,130 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.5.2 Release Notes / March 28, 2015</h1>
+
+<p>
+Mesa 10.5.2 is a bug fix release which fixes bugs found since the 10.5.1 release.
+</p>
+<p>
+Mesa 10.5.2 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+755220e160a9f22fda0dffd47746f997b6e196d03f8edc390df7793aecaaa541  mesa-10.5.2.tar.gz
+2f4b6fb77c3e7d6f861558d0884a3073f575e1e673dad8d1b0624e78e9c4dd44  mesa-10.5.2.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=88534">Bug 88534</a> - include/c11/threads_posix.h PTHREAD_MUTEX_RECURSIVE_NP not defined</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89328">Bug 89328</a> - python required to build Mesa release tarballs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89530">Bug 89530</a> - FTBFS in loader: missing fstat</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89590">Bug 89590</a> - Crash in glLinkProgram with shaders with multiple constant arrays</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89680">Bug 89680</a> - Hard link exist in Mesa 10.5.1 sources</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>glsl: Generate link error for non-matching gl_FragCoord redeclarations</li>
+</ul>
+
+<p>Emil Velikov (7):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.5.1 release</li>
+  <li>automake: add missing egl files to the tarball</li>
+  <li>st/egl: don't ship the dri2.c link at the tarball</li>
+  <li>loader: include &lt;sys/stat.h&gt; for non-sysfs builds</li>
+  <li>auxiliary/os: fix the android build - s/drm_munmap/os_munmap/</li>
+  <li>cherry-ignore: add commit non applicable for 10.5</li>
+  <li>Update version to 10.5.2</li>
+</ul>
+
+<p>Felix Janda (1):</p>
+<ul>
+  <li>c11/threads: Use PTHREAD_MUTEX_RECURSIVE by default</li>
+</ul>
+
+<p>Francisco Jerez (1):</p>
+<ul>
+  <li>i965: Set nr_params to the number of uniform components in the VS/GS path.</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+  <li>freedreno/a3xx: use the same layer size for all slices</li>
+  <li>freedreno: fix slice pitch calculations</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>radeonsi: increase coords array size for radeon_llvm_emit_prepare_cube_coords</li>
+</ul>
+
+<p>Mario Kleiner (2):</p>
+<ul>
+  <li>glx: Handle out-of-sequence swap completion events correctly. (v2)</li>
+  <li>mapi: Make private copies of name strings provided by client.</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+  <li>freedreno: update generated headers</li>
+</ul>
+
+<p>Samuel Iglesias Gonsalvez (2):</p>
+<ul>
+  <li>glsl: optimize (0 cmp x + y) into (-x cmp y).</li>
+  <li>configure: Introduce new output variable to ax_check_python_mako_module.m4</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>glsl: fix names in lower_constant_arrays_to_uniforms</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>clover: Return 0 as storage size for local kernel args that are not set v2</li>
+</ul>
+
+
+</div>
+</body>
+</html>

docs/relnotes/10.5.3.html

@@ -0,0 +1,124 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.5.3 Release Notes / April 12, 2015</h1>
+
+<p>
+Mesa 10.5.3 is a bug fix release which fixes bugs found since the 10.5.2 release.
+</p>
+<p>
+Mesa 10.5.3 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83962">Bug 83962</a> - [HSW/BYT]Piglit spec_ARB_gpu_shader5_arb_gpu_shader5-emitstreamvertex_nodraw fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89679">Bug 89679</a> - [NV50] Portal/Half-Life 2 will not start (native Steam)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89746">Bug 89746</a> - Mesa and LLVM 3.6+ break opengl for genymotion</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89754">Bug 89754</a> - vertexAttrib fails WebGL Conformance test with mesa drivers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89758">Bug 89758</a> - pow WebGL Conformance test with mesa drivers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89759">Bug 89759</a> - WebGL OGL ES GLSL conformance test with mesa drivers fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89905">Bug 89905</a> - scons build broken on 10.5.2 due to activated vega st</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>st_glsl_to_tgsi: only do mov copy propagation on temps (v2)</li>
+</ul>
+
+<p>Emil Velikov (5):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.5.2 release</li>
+  <li>xmlpool: don't forget to ship the MOS</li>
+  <li>configure.ac: error out if python/mako is not found when required</li>
+  <li>dist: add the VG depedencies into the tarball</li>
+  <li>Update version to 10.5.3</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>i965: Do not render primitives in non-zero streams then TF is disabled</li>
+</ul>
+
+<p>Ilia Mirkin (7):</p>
+<ul>
+  <li>st/mesa: update arrays when the current attrib has been updated</li>
+  <li>nv50/ir: take postFactor into account when doing peephole optimizations</li>
+  <li>nv50/ir/gk110: fix offset flag position for TXD opcode</li>
+  <li>freedreno/a3xx: fix 3d texture layout</li>
+  <li>freedreno/a3xx: point size should not be divided by 2</li>
+  <li>nv50: allocate more offset space for occlusion queries</li>
+  <li>nv50,nvc0: limit the y-tiling of 3d textures to the first level's tiling</li>
+</ul>
+
+<p>Kenneth Graunke (2):</p>
+<ul>
+  <li>i965: Fix instanced geometry shaders on Gen8+.</li>
+  <li>i965: Add forgotten multi-stream code to Gen8 SOL state.</li>
+</ul>
+
+<p>Marcin Ślusarz (1):</p>
+<ul>
+  <li>nouveau: synchronize "scratch runout" destruction with the command stream</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeonsi: Cache LLVMTargetMachineRef in context instead of in screen</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>clover: Return CL_BUILD_ERROR for CL_PROGRAM_BUILD_STATUS when compilation fails v2</li>
+</ul>
+
+<p>Ville Syrjälä (1):</p>
+<ul>
+  <li>i965: Fix URB size for CHV</li>
+</ul>
+
+
+</div>
+</body>
+</html>

include/c11/threads_posix.h

@@ -177,13 +177,8 @@ mtx_init(mtx_t *mtx, int type)
       && type != (mtx_try|mtx_recursive))
         return thrd_error;
     pthread_mutexattr_init(&attr);
-    if ((type & mtx_recursive) != 0) {
+    if ((type & mtx_recursive) != 0)
-#if defined(__linux__) || defined(__linux)
-        pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE_NP);
-#else
         pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE);
-#endif
-    }
     pthread_mutex_init(mtx, &attr);
     pthread_mutexattr_destroy(&attr);
     return thrd_success;

install-lib-links.mk

@@ -3,9 +3,9 @@
 
 if BUILD_SHARED
 if HAVE_COMPAT_SYMLINKS
-all-local : .libs/install-mesa-links
+all-local : .install-mesa-links
 
-.libs/install-mesa-links : $(lib_LTLIBRARIES)
+.install-mesa-links : $(lib_LTLIBRARIES)
 	$(AM_V_GEN)$(MKDIR_P) $(top_builddir)/$(LIB_DIR);	\
 	for f in $(join $(addsuffix .libs/,$(dir $(lib_LTLIBRARIES))),$(notdir $(lib_LTLIBRARIES:%.la=%.$(LIB_EXT)*))); do \
 		if test -h .libs/$$f; then			\
@@ -19,6 +19,7 @@ clean-local:
 	for f in $(notdir $(lib_LTLIBRARIES:%.la=.libs/%.$(LIB_EXT)*)); do \
 		$(RM) $(top_builddir)/$(LIB_DIR)/$$f;	\
 	done;
+	$(RM) .install-mesa-links
 
 endif
 endif

m4/ax_check_python_mako_module.m4

@@ -54,8 +54,10 @@ else:
     " | $PYTHON2 -
 
     if test $? -ne 0 ; then
-       AC_MSG_ERROR(mako $1 or later is required.)
+       AC_MSG_RESULT(no)
+       AC_SUBST(acv_mako_found, 'no')
     else
-        AC_MSG_RESULT(yes)
+       AC_MSG_RESULT(yes)
+       AC_SUBST(acv_mako_found, 'yes')
     fi
 ])

src/Makefile.am

@@ -53,7 +53,10 @@ if HAVE_GALLIUM
 SUBDIRS += gallium
 endif
 
-EXTRA_DIST = egl/docs getopt hgl SConscript
+EXTRA_DIST = \
+	egl/drivers/haiku \
+	egl/docs \
+	getopt hgl SConscript
 
 AM_CPPFLAGS = \
 	-I$(top_srcdir)/include/ \

src/egl/drivers/dri2/Makefile.am

@@ -64,3 +64,5 @@ if HAVE_EGL_PLATFORM_DRM
 libegl_dri2_la_SOURCES += platform_drm.c
 AM_CFLAGS += -DHAVE_DRM_PLATFORM
 endif
+
+EXTRA_DIST = SConscript

src/egl/drivers/dri2/egl_dri2.c

@@ -534,7 +534,7 @@ dri2_setup_screen(_EGLDisplay *disp)
          disp->Extensions.KHR_gl_texture_2D_image = EGL_TRUE;
          disp->Extensions.KHR_gl_texture_cubemap_image = EGL_TRUE;
       }
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
       if (dri2_dpy->image->base.version >= 8 &&
           dri2_dpy->image->createImageFromDmaBufs) {
          disp->Extensions.EXT_image_dma_buf_import = EGL_TRUE;
@@ -1335,7 +1335,7 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, _EGLContext *ctx,
    return dri2_create_image_from_dri(disp, dri_image);
 }
 
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
 static _EGLImage *
 dri2_create_image_mesa_drm_buffer(_EGLDisplay *disp, _EGLContext *ctx,
 				  EGLClientBuffer buffer, const EGLint *attr_list)
@@ -1571,7 +1571,7 @@ dri2_create_wayland_buffer_from_image(_EGLDriver *drv, _EGLDisplay *dpy,
    return dri2_dpy->vtbl->create_wayland_buffer_from_image(drv, dpy, img);
 }
 
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
 static EGLBoolean
 dri2_check_dma_buf_attribs(const _EGLImageAttribs *attrs)
 {
@@ -1821,7 +1821,7 @@ dri2_create_image_khr(_EGLDriver *drv, _EGLDisplay *disp,
       return dri2_create_image_khr_texture(disp, ctx, target, buffer, attr_list);
    case EGL_GL_RENDERBUFFER_KHR:
       return dri2_create_image_khr_renderbuffer(disp, ctx, buffer, attr_list);
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
    case EGL_DRM_BUFFER_MESA:
       return dri2_create_image_mesa_drm_buffer(disp, ctx, buffer, attr_list);
 #endif
@@ -1829,7 +1829,7 @@ dri2_create_image_khr(_EGLDriver *drv, _EGLDisplay *disp,
    case EGL_WAYLAND_BUFFER_WL:
       return dri2_create_image_wayland_wl_buffer(disp, ctx, buffer, attr_list);
 #endif
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
    case EGL_LINUX_DMA_BUF_EXT:
       return dri2_create_image_dma_buf(disp, ctx, buffer, attr_list);
 #endif
@@ -1853,7 +1853,7 @@ dri2_destroy_image_khr(_EGLDriver *drv, _EGLDisplay *disp, _EGLImage *image)
    return EGL_TRUE;
 }
 
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
 static _EGLImage *
 dri2_create_drm_image_mesa(_EGLDriver *drv, _EGLDisplay *disp,
 			   const EGLint *attr_list)
@@ -2215,7 +2215,7 @@ _eglBuiltInDriverDRI2(const char *args)
    dri2_drv->base.API.CreateImageKHR = dri2_create_image;
    dri2_drv->base.API.DestroyImageKHR = dri2_destroy_image_khr;
    dri2_drv->base.API.CreateWaylandBufferFromImageWL = dri2_create_wayland_buffer_from_image;
-#ifdef HAVE_DRM_PLATFORM
+#ifdef HAVE_LIBDRM
    dri2_drv->base.API.CreateDRMImageMESA = dri2_create_drm_image_mesa;
    dri2_drv->base.API.ExportDRMImageMESA = dri2_export_drm_image_mesa;
 #endif

src/egl/drivers/dri2/platform_drm.c

@@ -668,15 +668,21 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
 
    for (i = 0; dri2_dpy->driver_configs[i]; i++) {
       EGLint format, attr_list[3];
-      unsigned int mask;
+      unsigned int red, alpha;
 
       dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[i],
-                                       __DRI_ATTRIB_RED_MASK, &mask);
+                                       __DRI_ATTRIB_RED_MASK, &red);
-      if (mask == 0x3ff00000)
+      dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[i],
+                                       __DRI_ATTRIB_ALPHA_MASK, &alpha);
+      if (red == 0x3ff00000 && alpha == 0x00000000)
          format = GBM_FORMAT_XRGB2101010;
-      else if (mask == 0x00ff0000)
+      else if (red == 0x3ff00000 && alpha == 0xc0000000)
+         format = GBM_FORMAT_ARGB2101010;
+      else if (red == 0x00ff0000 && alpha == 0x00000000)
          format = GBM_FORMAT_XRGB8888;
-      else if (mask == 0xf800)
+      else if (red == 0x00ff0000 && alpha == 0xff000000)
+         format = GBM_FORMAT_ARGB8888;
+      else if (red == 0xf800)
          format = GBM_FORMAT_RGB565;
       else
          continue;

src/egl/drivers/dri2/platform_wayland.c

@@ -292,6 +292,26 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
    struct dri2_egl_display *dri2_dpy =
       dri2_egl_display(dri2_surf->base.Resource.Display);
    int i;
+   unsigned int dri_image_format;
+
+   /* currently supports three WL DRM formats,
+    * WL_DRM_FORMAT_ARGB8888, WL_DRM_FORMAT_XRGB8888,
+    * and WL_DRM_FORMAT_RGB565
+    */
+   switch (dri2_surf->format) {
+   case WL_DRM_FORMAT_ARGB8888:
+      dri_image_format = __DRI_IMAGE_FORMAT_ARGB8888;
+      break;
+   case WL_DRM_FORMAT_XRGB8888:
+      dri_image_format = __DRI_IMAGE_FORMAT_XRGB8888;
+      break;
+   case WL_DRM_FORMAT_RGB565:
+      dri_image_format = __DRI_IMAGE_FORMAT_RGB565;
+      break;
+   default:
+      /* format is not supported */
+      return -1;
+   }
 
    /* We always want to throttle to some event (either a frame callback or
     * a sync request) after the commit so that we can be sure the
@@ -322,7 +342,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
          dri2_dpy->image->createImage(dri2_dpy->dri_screen,
                                       dri2_surf->base.Width,
                                       dri2_surf->base.Height,
-                                      __DRI_IMAGE_FORMAT_ARGB8888,
+                                      dri_image_format,
                                       __DRI_IMAGE_USE_SHARE,
                                       NULL);
       dri2_surf->back->age = 0;
@@ -462,11 +482,26 @@ dri2_wl_get_buffers(__DRIdrawable * driDrawable,
                     unsigned int *attachments, int count,
                     int *out_count, void *loaderPrivate)
 {
+   struct dri2_egl_surface *dri2_surf = loaderPrivate;
    unsigned int *attachments_with_format;
    __DRIbuffer *buffer;
-   const unsigned int format = 32;
+   unsigned int bpp;
+
    int i;
 
+   switch (dri2_surf->format) {
+   case WL_DRM_FORMAT_ARGB8888:
+   case WL_DRM_FORMAT_XRGB8888:
+      bpp = 32;
+      break;
+   case WL_DRM_FORMAT_RGB565:
+      bpp = 16;
+      break;
+   default:
+      /* format is not supported */
+      return NULL;
+   }
+
    attachments_with_format = calloc(count, 2 * sizeof(unsigned int));
    if (!attachments_with_format) {
       *out_count = 0;
@@ -475,7 +510,7 @@ dri2_wl_get_buffers(__DRIdrawable * driDrawable,
 
    for (i = 0; i < count; ++i) {
       attachments_with_format[2*i] = attachments[i];
-      attachments_with_format[2*i + 1] = format;
+      attachments_with_format[2*i + 1] = bpp;
    }
 
    buffer =

src/egl/main/eglarray.h

@@ -49,7 +49,7 @@ extern _EGLArray *
 _eglCreateArray(const char *name, EGLint init_size);
 
 
-PUBLIC void
+extern void
 _eglDestroyArray(_EGLArray *array, void (*free_cb)(void *));
 
 
@@ -65,7 +65,7 @@ void *
 _eglFindArray(_EGLArray *array, void *elem);
 
 
-PUBLIC EGLint
+extern EGLint
 _eglFilterArray(_EGLArray *array, void **data, EGLint size,
                 _EGLArrayForEach filter, void *filter_data);
 

src/egl/main/eglconfig.c

@@ -75,7 +75,7 @@ _eglInitConfig(_EGLConfig *conf, _EGLDisplay *dpy, EGLint id)
  *
  * Note that we just save the ptr to the config (we don't copy the config).
  */
-PUBLIC EGLConfig
+EGLConfig
 _eglLinkConfig(_EGLConfig *conf)
 {
    _EGLDisplay *dpy = conf->Display;

src/egl/main/eglconfig.h

@@ -162,11 +162,11 @@ _eglGetConfigKey(const _EGLConfig *conf, EGLint key)
 }
 
 
-PUBLIC void
+extern void
 _eglInitConfig(_EGLConfig *config, _EGLDisplay *dpy, EGLint id);
 
 
-PUBLIC EGLConfig
+extern EGLConfig
 _eglLinkConfig(_EGLConfig *conf);
 
 
@@ -184,25 +184,25 @@ _eglGetConfigHandle(_EGLConfig *conf)
 }
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglValidateConfig(const _EGLConfig *conf, EGLBoolean for_matching);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglMatchConfig(const _EGLConfig *conf, const _EGLConfig *criteria);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglParseConfigAttribList(_EGLConfig *conf, _EGLDisplay *dpy,
                           const EGLint *attrib_list);
 
 
-PUBLIC EGLint
+extern EGLint
 _eglCompareConfigs(const _EGLConfig *conf1, const _EGLConfig *conf2,
                    const _EGLConfig *criteria, EGLBoolean compare_id);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglFilterConfigArray(_EGLArray *array, EGLConfig *configs,
                       EGLint config_size, EGLint *num_configs,
                       EGLBoolean (*match)(const _EGLConfig *, void *),

src/egl/main/eglcontext.h

@@ -63,7 +63,7 @@ struct _egl_context
 };
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglInitContext(_EGLContext *ctx, _EGLDisplay *dpy,
                 _EGLConfig *config, const EGLint *attrib_list);
 
@@ -72,7 +72,7 @@ extern EGLBoolean
 _eglQueryContext(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx, EGLint attribute, EGLint *value);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglBindContext(_EGLContext *ctx, _EGLSurface *draw, _EGLSurface *read,
                 _EGLContext **old_ctx,
                 _EGLSurface **old_draw, _EGLSurface **old_read);

src/egl/main/eglcurrent.c

@@ -242,7 +242,7 @@ _eglIsCurrentThreadDummy(void)
 /**
  * Return the currently bound context of the given API, or NULL.
  */
-PUBLIC _EGLContext *
+_EGLContext *
 _eglGetAPIContext(EGLenum api)
 {
    _EGLThreadInfo *t = _eglGetCurrentThread();

src/egl/main/eglcurrent.h

@@ -90,7 +90,7 @@ _eglConvertApiFromIndex(EGLint idx)
 }
 
 
-PUBLIC _EGLThreadInfo *
+extern _EGLThreadInfo *
 _eglGetCurrentThread(void);
 
 
@@ -102,15 +102,15 @@ extern EGLBoolean
 _eglIsCurrentThreadDummy(void);
 
 
-PUBLIC _EGLContext *
+extern _EGLContext *
 _eglGetAPIContext(EGLenum api);
 
 
-PUBLIC _EGLContext *
+extern _EGLContext *
 _eglGetCurrentContext(void);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglError(EGLint errCode, const char *msg);
 
 

src/egl/main/egldisplay.h

@@ -177,11 +177,11 @@ extern _EGLDisplay *
 _eglFindDisplay(_EGLPlatformType plat, void *plat_dpy);
 
 
-PUBLIC void
+extern void
 _eglReleaseDisplayResources(_EGLDriver *drv, _EGLDisplay *dpy);
 
 
-PUBLIC void
+extern void
 _eglCleanupDisplay(_EGLDisplay *disp);
 
 
@@ -189,7 +189,7 @@ extern EGLBoolean
 _eglCheckDisplayHandle(EGLDisplay dpy);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglCheckResource(void *res, _EGLResourceType type, _EGLDisplay *dpy);
 
 
@@ -221,11 +221,11 @@ extern void
 _eglInitResource(_EGLResource *res, EGLint size, _EGLDisplay *dpy);
 
 
-PUBLIC void
+extern void
 _eglGetResource(_EGLResource *res);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglPutResource(_EGLResource *res);
 
 

src/egl/main/egldriver.h

@@ -96,7 +96,7 @@ extern _EGLDriver *
 _eglBuiltInDriverGLX(const char *args);
 
 
-PUBLIC _EGLDriver *
+extern _EGLDriver *
 _eglMain(const char *args);
 
 
@@ -113,11 +113,11 @@ _eglUnloadDrivers(void);
 
 
 /* defined in eglfallbacks.c */
-PUBLIC void
+extern void
 _eglInitDriverFallbacks(_EGLDriver *drv);
 
 
-PUBLIC void
+extern void
 _eglSearchPathForEach(EGLBoolean (*callback)(const char *, size_t, void *),
                       void *callback_data);
 

src/egl/main/eglimage.h

@@ -80,12 +80,12 @@ struct _egl_image
 };
 
 
-PUBLIC EGLint
+extern EGLint
 _eglParseImageAttribList(_EGLImageAttribs *attrs, _EGLDisplay *dpy,
                          const EGLint *attrib_list);
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglInitImage(_EGLImage *img, _EGLDisplay *dpy);
 
 

src/egl/main/egllog.h

@@ -43,15 +43,15 @@
 typedef void (*_EGLLogProc)(EGLint level, const char *msg);
 
 
-PUBLIC void
+extern void
 _eglSetLogProc(_EGLLogProc logger);
 
 
-PUBLIC void
+extern void
 _eglSetLogLevel(EGLint level);
 
 
-PUBLIC void
+extern void
 _eglLog(EGLint level, const char *fmtStr, ...);
 
 

src/egl/main/eglscreen.h

@@ -67,11 +67,11 @@ struct _egl_screen
 };
 
 
-PUBLIC void
+extern void
 _eglInitScreen(_EGLScreen *screen, _EGLDisplay *dpy, EGLint num_modes);
 
 
-PUBLIC EGLScreenMESA
+extern EGLScreenMESA
 _eglLinkScreen(_EGLScreen *screen);
 
 

src/egl/main/eglsurface.h

@@ -78,7 +78,7 @@ struct _egl_surface
 };
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglInitSurface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
                 _EGLConfig *config, const EGLint *attrib_list);
 
@@ -91,10 +91,10 @@ extern EGLBoolean
 _eglSurfaceAttrib(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf, EGLint attribute, EGLint value);
 
 
-PUBLIC extern EGLBoolean
+extern EGLBoolean
 _eglBindTexImage(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf, EGLint buffer);
 
-PUBLIC extern EGLBoolean
+extern EGLBoolean
 _eglReleaseTexImage(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf, EGLint buffer);
 
 

src/egl/main/eglsync.h

@@ -48,7 +48,7 @@ struct _egl_sync
 };
 
 
-PUBLIC EGLBoolean
+extern EGLBoolean
 _eglInitSync(_EGLSync *sync, _EGLDisplay *dpy, EGLenum type,
              const EGLint *attrib_list);
 

src/gallium/auxiliary/Makefile.am

@@ -53,24 +53,40 @@ libgalliumvl_stub_la_SOURCES = \
 
 if NEED_GALLIUM_VL
 
-noinst_LTLIBRARIES += libgalliumvl.la
+COMMON_VL_CFLAGS = \
-
-libgalliumvl_la_CFLAGS = \
 	$(AM_CFLAGS) \
 	$(VL_CFLAGS) \
+	$(DRI2PROTO_CFLAGS) \
 	$(LIBDRM_CFLAGS) \
 	$(GALLIUM_PIPE_LOADER_DEFINES) \
 	-DPIPE_SEARCH_DIR=\"$(libdir)/gallium-pipe\"
 
 if HAVE_GALLIUM_STATIC_TARGETS
-libgalliumvl_la_CFLAGS += \
+COMMON_VL_CFLAGS += \
 	-DGALLIUM_STATIC_TARGETS=1
 
 endif # HAVE_GALLIUM_STATIC_TARGETS
 
+noinst_LTLIBRARIES += libgalliumvl.la
+
+libgalliumvl_la_CFLAGS = \
+	$(COMMON_VL_CFLAGS)
+
 libgalliumvl_la_SOURCES = \
 	$(VL_SOURCES)
 
+if NEED_GALLIUM_VL_WINSYS
+
+noinst_LTLIBRARIES += libgalliumvlwinsys.la
+
+libgalliumvlwinsys_la_CFLAGS = \
+	$(COMMON_VL_CFLAGS)
+
+libgalliumvlwinsys_la_SOURCES = \
+	$(VL_WINSYS_SOURCES)
+
+endif
+
 endif
 
 EXTRA_DIST = \

src/gallium/auxiliary/Makefile.sources

@@ -334,10 +334,13 @@ VL_SOURCES := \
 	vl/vl_video_buffer.h \
 	vl/vl_vlc.h \
 	vl/vl_winsys.h \
-	vl/vl_winsys_dri.c \
 	vl/vl_zscan.c \
 	vl/vl_zscan.h
 
+# XXX: Nuke this as our dri targets no longer depend on VL.
+VL_WINSYS_SOURCES := \
+	vl/vl_winsys_dri.c
+
 VL_STUB_SOURCES := \
 	vl/vl_stubs.c
 

src/gallium/auxiliary/indices/u_indices_gen.py

@@ -193,7 +193,7 @@ def lineloop(intype, outtype, inpv, outpv):
     print '  for (i = start, j = 0; j < nr - 2; j+=2, i++) { '
     do_line( intype, outtype, 'out+j',  'i', 'i+1', inpv, outpv );
     print '   }'
-    do_line( intype, outtype, 'out+j',  'i', '0', inpv, outpv );
+    do_line( intype, outtype, 'out+j',  'i', 'start', inpv, outpv );
     postamble()
 
 def tris(intype, outtype, inpv, outpv):
@@ -218,7 +218,7 @@ def tristrip(intype, outtype, inpv, outpv):
 def trifan(intype, outtype, inpv, outpv):
     preamble(intype, outtype, inpv, outpv, prim='trifan')
     print '  for (i = start, j = 0; j < nr; j+=3, i++) { '
-    do_tri( intype, outtype, 'out+j',  '0', 'i+1', 'i+2', inpv, outpv );
+    do_tri( intype, outtype, 'out+j',  'start', 'i+1', 'i+2', inpv, outpv );
     print '   }'
     postamble()
 
@@ -228,9 +228,9 @@ def polygon(intype, outtype, inpv, outpv):
     preamble(intype, outtype, inpv, outpv, prim='polygon')
     print '  for (i = start, j = 0; j < nr; j+=3, i++) { '
     if inpv == FIRST:
-        do_tri( intype, outtype, 'out+j',  '0', 'i+1', 'i+2', inpv, outpv );
+        do_tri( intype, outtype, 'out+j',  'start', 'i+1', 'i+2', inpv, outpv );
     else:
-        do_tri( intype, outtype, 'out+j',  'i+1', 'i+2', '0', inpv, outpv );
+        do_tri( intype, outtype, 'out+j',  'i+1', 'i+2', 'start', inpv, outpv );
     print '   }'
     postamble()
 

src/gallium/auxiliary/os/os_misc.c

@@ -118,7 +118,7 @@ os_get_total_physical_memory(uint64_t *size)
    *size = phys_pages * page_size;
    return (phys_pages > 0 && page_size > 0);
 #elif defined(PIPE_OS_APPLE) || defined(PIPE_OS_BSD)
-   size_t len = sizeof(size);
+   size_t len = sizeof(*size);
    int mib[2];
 
    mib[0] = CTL_HW;
@@ -134,7 +134,7 @@ os_get_total_physical_memory(uint64_t *size)
 #error Unsupported *BSD
 #endif
 
-   return (sysctl(mib, 2, &size, &len, NULL, 0) == 0);
+   return (sysctl(mib, 2, size, &len, NULL, 0) == 0);
 #elif defined(PIPE_OS_HAIKU)
    system_info info;
    status_t ret;

src/gallium/auxiliary/os/os_mman.h

@@ -70,8 +70,8 @@ static INLINE void *os_mmap(void *addr, size_t length, int prot, int flags,
    return __mmap2(addr, length, prot, flags, fd, (size_t) (offset >> 12));
 }
 
-#  define drm_munmap(addr, length) \
+#  define os_munmap(addr, length) \
-              munmap(addr, length)
+             munmap(addr, length)
 
 #else
 /* assume large file support exists */

src/gallium/drivers/freedreno/a2xx/a2xx.xml.h

@@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51270 bytes, from 2015-01-18 23:05:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

src/gallium/drivers/freedreno/a2xx/ir-a2xx.c

@@ -439,7 +439,8 @@ static int instr_emit_alu(struct ir2_instruction *instr, uint32_t *dwords,
 		assert(sdst_reg->flags == dst_reg->flags);
 
 		if (src3_reg) {
-			assert(src3_reg == instr->regs[reg++]);
+			assert(src3_reg == instr->regs[reg]);
+			reg++;
 		} else {
 			src3_reg = instr->regs[reg++];
 		}

src/gallium/drivers/freedreno/a3xx/a3xx.xml.h

@@ -13,10 +13,10 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51270 bytes, from 2015-01-18 23:05:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -130,6 +130,10 @@ enum a3xx_tex_fmt {
 	TFMT_I420_Y = 24,
 	TFMT_I420_U = 26,
 	TFMT_I420_V = 27,
+	TFMT_ATC_RGB = 32,
+	TFMT_ATC_RGBA_EXPLICIT = 33,
+	TFMT_ETC1 = 34,
+	TFMT_ATC_RGBA_INTERPOLATED = 35,
 	TFMT_DXT1 = 36,
 	TFMT_DXT3 = 37,
 	TFMT_DXT5 = 38,
@@ -854,6 +858,12 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va
 {
 	return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
 }
+#define A3XX_RB_MODE_CONTROL_MRT__MASK				0x00003000
+#define A3XX_RB_MODE_CONTROL_MRT__SHIFT				12
+static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
+{
+	return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
+}
 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE		0x00008000
 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE		0x00010000
 
@@ -2107,6 +2117,12 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1			0x000022e9
 
 #define REG_A3XX_SP_FS_OUTPUT_REG				0x000022ec
+#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK				0x00000003
+#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
+static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+	return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT		8
@@ -2661,7 +2677,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
 }
 
 #define REG_A3XX_TEX_CONST_3					0x00000003
-#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x0000000f
+#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x00001fff
 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT			0
 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
 {

src/gallium/drivers/freedreno/a3xx/fd3_program.c

@@ -365,7 +365,10 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
 				COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 		OUT_RING(ring, 0x00000000);
 	} else {
-		uint32_t vinterp[4] = {0}, flatshade[2] = {0};
+		uint32_t vinterp[4], flatshade[2];
+
+		memset(vinterp, 0, sizeof(vinterp));
+		memset(flatshade, 0, sizeof(flatshade));
 
 		/* figure out VARYING_INTERP / FLAT_SHAD register values: */
 		for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {

src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c

@@ -50,7 +50,7 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
 
 	if (cso->point_size_per_vertex) {
 		psize_min = util_get_min_point_size(cso);
-		psize_max = 8192;
+		psize_max = 4092;
 	} else {
 		/* Force the point size to be as if the vertex output was disabled. */
 		psize_min = cso->point_size;
@@ -67,9 +67,9 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
 */
 	so->gras_cl_clip_cntl = A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER; /* ??? */
 	so->gras_su_point_minmax =
-			A3XX_GRAS_SU_POINT_MINMAX_MIN(psize_min/2) |
+			A3XX_GRAS_SU_POINT_MINMAX_MIN(psize_min) |
-			A3XX_GRAS_SU_POINT_MINMAX_MAX(psize_max/2);
+			A3XX_GRAS_SU_POINT_MINMAX_MAX(psize_max);
-	so->gras_su_point_size   = A3XX_GRAS_SU_POINT_SIZE(cso->point_size/2);
+	so->gras_su_point_size   = A3XX_GRAS_SU_POINT_SIZE(cso->point_size);
 	so->gras_su_poly_offset_scale =
 			A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(cso->offset_scale);
 	so->gras_su_poly_offset_offset =

src/gallium/drivers/freedreno/a3xx/fd3_texture.c

@@ -212,6 +212,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	struct fd_resource *rsc = fd_resource(prsc);
 	unsigned lvl = cso->u.tex.first_level;
 	unsigned miplevels = cso->u.tex.last_level - lvl;
+	uint32_t sz2 = 0;
 
 	if (!so)
 		return NULL;
@@ -252,8 +253,10 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	case PIPE_TEXTURE_3D:
 		so->texconst3 =
 				A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->depth0, lvl)) |
-				A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[0].size0) |
+				A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[lvl].size0);
-				A3XX_TEX_CONST_3_LAYERSZ2(rsc->slices[0].size0);
+		while (lvl < cso->u.tex.last_level && sz2 != rsc->slices[lvl+1].size0)
+			sz2 = rsc->slices[++lvl].size0;
+		so->texconst3 |= A3XX_TEX_CONST_3_LAYERSZ2(sz2);
 		break;
 	default:
 		so->texconst3 = 0x00000000;

src/gallium/drivers/freedreno/a4xx/a4xx.xml.h

@@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51270 bytes, from 2015-01-18 23:05:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -150,6 +150,7 @@ enum a4xx_depth_format {
 enum a4xx_tex_filter {
 	A4XX_TEX_NEAREST = 0,
 	A4XX_TEX_LINEAR = 1,
+	A4XX_TEX_ANISO = 2,
 };
 
 enum a4xx_tex_clamp {
@@ -159,6 +160,14 @@ enum a4xx_tex_clamp {
 	A4XX_TEX_CLAMP_NONE = 3,
 };
 
+enum a4xx_tex_aniso {
+	A4XX_TEX_ANISO_1 = 0,
+	A4XX_TEX_ANISO_2 = 1,
+	A4XX_TEX_ANISO_4 = 2,
+	A4XX_TEX_ANISO_8 = 3,
+	A4XX_TEX_ANISO_16 = 4,
+};
+
 enum a4xx_tex_swiz {
 	A4XX_TEX_X = 0,
 	A4XX_TEX_Y = 1,
@@ -936,6 +945,10 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
 
 #define REG_A4XX_CP_IB2_BUFSZ					0x00000209
 
+#define REG_A4XX_CP_ME_NRT_ADDR					0x0000020c
+
+#define REG_A4XX_CP_ME_NRT_DATA					0x0000020d
+
 #define REG_A4XX_CP_ME_RB_DONE_DATA				0x00000217
 
 #define REG_A4XX_CP_QUEUE_THRESH2				0x00000219
@@ -946,9 +959,9 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
 
 #define REG_A4XX_CP_ROQ_DATA					0x0000021d
 
-#define REG_A4XX_CP_MEQ_ADDR 					0x0000021e
+#define REG_A4XX_CP_MEQ_ADDR					0x0000021e
 
-#define REG_A4XX_CP_MEQ_DATA 					0x0000021f
+#define REG_A4XX_CP_MEQ_DATA					0x0000021f
 
 #define REG_A4XX_CP_MERCIU_ADDR					0x00000220
 
@@ -1424,6 +1437,10 @@ static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0
 
 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7				0x00000e4a
 
+#define REG_A4XX_VGT_CL_INITIATOR				0x000021d0
+
+#define REG_A4XX_VGT_EVENT_INITIATOR				0x000021d9
+
 #define REG_A4XX_VFD_CONTROL_0					0x00002200
 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK			0x000000ff
 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT			0
@@ -2041,7 +2058,12 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 #define REG_A4XX_PC_BIN_BASE					0x000021c0
 
 #define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4
-#define A4XX_PC_PRIM_VTX_CNTL_VAROUT				0x00000001
+#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK			0x0000000f
+#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT			0
+static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
+{
+	return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
+}
 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000
 
@@ -2166,6 +2188,12 @@ static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
 {
 	return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
 }
+#define A4XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
+#define A4XX_TEX_SAMP_0_ANISO__SHIFT				14
+static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
+{
+	return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
+}
 
 #define REG_A4XX_TEX_SAMP_1					0x00000001
 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e

src/gallium/drivers/freedreno/a4xx/fd4_draw.c

@@ -100,6 +100,9 @@ fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 		if (last_key->alpha != key->alpha)
 			ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 
+		if (last_key->rasterflat != key->rasterflat)
+			ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
+
 		fd4_ctx->last_key = *key;
 	}
 }
@@ -118,6 +121,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 			.binning_pass = true,
 			.color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 			.alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
+			.rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 			// TODO set .half_precision based on render target format,
 			// ie. float16 and smaller use half, float32 use full..
 			.half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
@@ -130,7 +134,6 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 			.fsaturate_r = fd4_ctx->fsaturate_r,
 		},
 		.format = fd4_emit_format(pfb->cbufs[0]),
-		.rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 	};
 	unsigned dirty;
 

src/gallium/drivers/freedreno/a4xx/fd4_emit.c

@@ -425,13 +425,9 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
 		OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
 		OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
-	}
 
-	if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
-		uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
-				->gras_cl_clip_cntl;
 		OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
-		OUT_RING(ring, val);
+		OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
 	}
 
 	/* NOTE: since primitive_restart is not actually part of any
@@ -444,7 +440,12 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 				->pc_prim_vtx_cntl;
 
 		val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
-		val |= COND(fp->total_in > 0, A4XX_PC_PRIM_VTX_CNTL_VAROUT);
+		if (fp->total_in > 0) {
+			uint32_t varout = align(fp->total_in, 16) / 16;
+			if (varout > 1)
+				varout = align(varout, 2);
+			val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
+		}
 
 		OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 		OUT_RING(ring, val);

src/gallium/drivers/freedreno/a4xx/fd4_emit.h

@@ -55,7 +55,6 @@ struct fd4_emit {
 	struct ir3_shader_key key;
 	enum a4xx_color_fmt format;
 	uint32_t dirty;
-	bool rasterflat;
 
 	/* cached to avoid repeated lookups of same variants: */
 	struct ir3_shader_variant *vp, *fp;

src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

@@ -375,7 +375,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 
 	OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 	OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
-			A4XX_PC_PRIM_VTX_CNTL_VAROUT);
+			A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
 
 	OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 	OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
@@ -436,13 +436,6 @@ fd4_emit_sysmem_prep(struct fd_context *ctx)
 {
 	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 	struct fd_ringbuffer *ring = ctx->ring;
-	uint32_t pitch = 0;
-
-	if (pfb->cbufs[0]) {
-		struct pipe_surface *psurf = pfb->cbufs[0];
-		unsigned lvl = psurf->u.tex.level;
-		pitch = fd_resource(psurf->texture)->slices[lvl].pitch;
-	}
 
 	fd4_emit_restore(ctx);
 

src/gallium/drivers/freedreno/a4xx/fd4_program.c

@@ -420,8 +420,28 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
 				COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
 		OUT_RING(ring, 0x00000000);
 	} else {
-		uint32_t vinterp[8] = {0}, flatshade[2] = {0};
+		uint32_t vinterp[8], flatshade[2];
 
+		memset(vinterp, 0, sizeof(vinterp));
+		memset(flatshade, 0, sizeof(flatshade));
+
+		/* TODO: looks like we need to do int varyings in the frag
+		 * shader on a4xx (no flatshad reg?):
+		 *
+		 *    (sy)(ss)nop
+		 *    (sy)ldlv.u32 r0.x,l[r0.x], 1
+		 *    ldlv.u32 r0.y,l[r0.x+1], 1
+		 *    (ss)bary.f (ei)r63.x, 0, r0.x
+		 *    (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
+		 *    (rpt5)nop
+		 *    sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
+		 *
+		 * for now, don't set FLAT on vinterp[], since that
+		 * at least works well enough for pure float impl (ie.
+		 * pre glsl130).. we'll have to do a bit more work to
+		 * handle this properly:
+		 */
+#if 0
 		/* figure out VARYING_INTERP / FLAT_SHAD register values: */
 		for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
 			uint32_t interp = s[FS].v->inputs[j].interpolate;
@@ -443,25 +463,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
 				}
 			}
 		}
-
+#endif
-		/* HACK: looks like we need to do int varyings in the frag
-		 * shader on a4xx (no flatshad reg?):
-		 *
-		 *    (sy)(ss)nop
-		 *    (sy)ldlv.u32 r0.x,l[r0.x], 1
-		 *    ldlv.u32 r0.y,l[r0.x+1], 1
-		 *    (ss)bary.f (ei)r63.x, 0, r0.x
-		 *    (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
-		 *    (rpt5)nop
-		 *    sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
-		 *
-		 * for now, don't set FLAT on vinterp[], since that
-		 * at least works well enough for pure float impl (ie.
-		 * pre glsl130).. we'll have to do a bit more work to
-		 * handle this properly:
-		 */
-		for (i = 0; i < ARRAY_SIZE(vinterp); i++)
-			vinterp[i] = 0;
 
 		OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
 		OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |

src/gallium/drivers/freedreno/a4xx/fd4_texture.c

@@ -68,13 +68,13 @@ tex_clamp(unsigned wrap)
 }
 
 static enum a4xx_tex_filter
-tex_filter(unsigned filter)
+tex_filter(unsigned filter, bool aniso)
 {
 	switch (filter) {
 	case PIPE_TEX_FILTER_NEAREST:
 		return A4XX_TEX_NEAREST;
 	case PIPE_TEX_FILTER_LINEAR:
-		return A4XX_TEX_LINEAR;
+		return aniso ? A4XX_TEX_ANISO : A4XX_TEX_LINEAR;
 	default:
 		DBG("invalid filter: %u", filter);
 		return 0;
@@ -86,6 +86,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 		const struct pipe_sampler_state *cso)
 {
 	struct fd4_sampler_stateobj *so = CALLOC_STRUCT(fd4_sampler_stateobj);
+	unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
 	bool miplinear = false;
 
 	if (!so)
@@ -98,8 +99,9 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 
 	so->texsamp0 =
 		COND(miplinear, A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
-		A4XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter)) |
+		A4XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
-		A4XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter)) |
+		A4XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
+		A4XX_TEX_SAMP_0_ANISO(aniso) |
 		A4XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s)) |
 		A4XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t)) |
 		A4XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r));

src/gallium/drivers/freedreno/adreno_common.xml.h

@@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51270 bytes, from 2015-01-18 23:05:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

src/gallium/drivers/freedreno/adreno_pm4.xml.h

@@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51270 bytes, from 2015-01-18 23:05:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

src/gallium/drivers/freedreno/freedreno_resource.c

@@ -213,9 +213,22 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment)
 	for (level = 0; level <= prsc->last_level; level++) {
 		struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
 
-		slice->pitch = align(width, 32);
+		slice->pitch = width = align(width, 32);
 		slice->offset = size;
-		slice->size0 = align(slice->pitch * height * rsc->cpp, alignment);
+		/* 1d array and 2d array textures must all have the same layer size
+		 * for each miplevel on a3xx. 3d textures can have different layer
+		 * sizes for high levels, but the hw auto-sizer is buggy (or at least
+		 * different than what this code does), so as soon as the layer size
+		 * range gets into range, we stop reducing it.
+		 */
+		if (prsc->target == PIPE_TEXTURE_3D && (
+					level == 1 ||
+					(level > 1 && rsc->slices[level - 1].size0 > 0xf000)))
+			slice->size0 = align(slice->pitch * height * rsc->cpp, alignment);
+		else if (level == 0 || rsc->layer_first || alignment == 1)
+			slice->size0 = align(slice->pitch * height * rsc->cpp, alignment);
+		else
+			slice->size0 = rsc->slices[level - 1].size0;
 
 		size += slice->size0 * depth * layers_in_level;
 

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -314,7 +314,7 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 	case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 	case PIPE_CAPF_MAX_POINT_WIDTH:
 	case PIPE_CAPF_MAX_POINT_WIDTH_AA:
-		return 8192.0f;
+		return 4092.0f;
 	case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 		return 16.0f;
 	case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:

src/gallium/drivers/freedreno/freedreno_state.c

@@ -123,12 +123,12 @@ fd_set_framebuffer_state(struct pipe_context *pctx,
 
 	fd_context_render(pctx);
 
-	util_copy_framebuffer_state(cso, framebuffer);
-
 	if ((cso->width != framebuffer->width) ||
 			(cso->height != framebuffer->height))
 		ctx->needs_rb_fbd = true;
 
+	util_copy_framebuffer_state(cso, framebuffer);
+
 	ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
 
 	ctx->disabled_scissor.minx = 0;

src/gallium/drivers/freedreno/ir3/disasm-a3xx.c

@@ -448,117 +448,114 @@ static void print_instr_cat5(instr_t *instr)
 	}
 }
 
-static int32_t u2i(uint32_t val, int nbits)
-{
-	return ((val >> (nbits-1)) * ~((1 << nbits) - 1)) | val;
-}
-
 static void print_instr_cat6(instr_t *instr)
 {
 	instr_cat6_t *cat6 = &instr->cat6;
+	char sd = 0, ss = 0;  /* dst/src address space */
+	bool full = type_size(cat6->type) == 32;
+	bool nodst = false;
 
 	printf(".%s ", type[cat6->type]);
 
 	switch (cat6->opc) {
+	case OPC_STG:
+		sd = 'g';
+		break;
+	case OPC_STP:
+		sd = 'p';
+		break;
+	case OPC_STL:
+	case OPC_STLW:
+		sd = 'l';
+		break;
+
 	case OPC_LDG:
+		ss = 'g';
+		break;
 	case OPC_LDP:
+		ss = 'p';
+		break;
 	case OPC_LDL:
 	case OPC_LDLW:
 	case OPC_LDLV:
-		/* load instructions: */
+		ss = 'l';
-		print_reg_dst((reg_t)(cat6->a.dst), type_size(cat6->type) == 32, false);
-		printf(",");
-		switch (cat6->opc) {
-		case OPC_LDG:
-			printf("g");
-			break;
-		case OPC_LDP:
-			printf("p");
-			break;
-		case OPC_LDL:
-		case OPC_LDLW:
-		case OPC_LDLV:
-			printf("l");
-			break;
-		}
-		printf("[");
-		print_reg_src((reg_t)(cat6->a.src), true,
-				false, false, false, false, false, false);
-		if (cat6->a.off)
-			printf("%+d", cat6->a.off);
-		printf("]");
 		break;
-	case OPC_PREFETCH:
-		/* similar to load instructions: */
-		printf("g[");
-		print_reg_src((reg_t)(cat6->a.src), true,
-				false, false, false, false, false, false);
-		if (cat6->a.off)
-			printf("%+d", cat6->a.off);
-		printf("]");
-		break;
-	case OPC_STG:
-	case OPC_STP:
-	case OPC_STL:
-	case OPC_STLW:
-		/* store instructions: */
-		switch (cat6->opc) {
-		case OPC_STG:
-			printf("g");
-			break;
-		case OPC_STP:
-			printf("p");
-			break;
-		case OPC_STL:
-		case OPC_STLW:
-			printf("l");
-			break;
-		}
-		printf("[");
-		print_reg_dst((reg_t)(cat6->b.dst), true, false);
-		if (cat6->b.off || cat6->b.off_hi)
-			printf("%+d", u2i((cat6->b.off_hi << 8) | cat6->b.off, 13));
-		printf("]");
-		printf(",");
-		print_reg_src((reg_t)(cat6->b.src), type_size(cat6->type) == 32,
-				false, false, false, false, false, false);
 
+	case OPC_L2G:
+		ss = 'l';
+		sd = 'g';
 		break;
+
+	case OPC_G2L:
+		ss = 'g';
+		sd = 'l';
+		break;
+
+	case OPC_PREFETCH:
+		ss = 'g';
+		nodst = true;
+		break;
+
 	case OPC_STI:
-		/* sti has same encoding as other store instructions, but
+		full = false;  // XXX or inverts??
-		 * slightly different syntax:
-		 */
-		print_reg_dst((reg_t)(cat6->b.dst), false /* XXX is it always half? */, false);
-		if (cat6->b.off || cat6->b.off_hi)
-			printf("%+d", u2i((cat6->b.off_hi << 8) | cat6->b.off, 13));
-		printf(",");
-		print_reg_src((reg_t)(cat6->b.src), type_size(cat6->type) == 32,
-				false, false, false, false, false, false);
 		break;
 	}
 
-	printf(", %d", cat6->iim_val);
+	if (cat6->has_off) {
+		if (!nodst) {
+			if (sd)
+				printf("%c[", sd);
+			print_reg_dst((reg_t)(cat6->a.dst), full, false);
+			if (sd)
+				printf("]");
+			printf(", ");
+		}
+		if (ss)
+			printf("%c[", ss);
+		print_reg_src((reg_t)(cat6->a.src1), true,
+				false, false, cat6->a.src1_im, false, false, false);
+		printf("%+d", cat6->a.off);
+		if (ss)
+			printf("]");
+		printf(", ");
+		print_reg_src((reg_t)(cat6->a.src2), full,
+				false, false, cat6->a.src2_im, false, false, false);
+	} else {
+		if (!nodst) {
+			if (sd)
+				printf("%c[", sd);
+			print_reg_dst((reg_t)(cat6->b.dst), full, false);
+			if (sd)
+				printf("]");
+			printf(", ");
+		}
+		if (ss)
+			printf("%c[", ss);
+		print_reg_src((reg_t)(cat6->b.src1), true,
+				false, false, cat6->b.src1_im, false, false, false);
+		if (ss)
+			printf("]");
+		printf(", ");
+		print_reg_src((reg_t)(cat6->b.src2), full,
+				false, false, cat6->b.src2_im, false, false, false);
+	}
 
 	if (debug & PRINT_VERBOSE) {
 		switch (cat6->opc) {
 		case OPC_LDG:
 		case OPC_LDP:
 			/* load instructions: */
-			if (cat6->a.dummy1|cat6->a.dummy2|cat6->a.dummy3)
+			if (cat6->a.dummy2|cat6->a.dummy3)
-				printf("\t{6: %x,%x,%x}", cat6->a.dummy1, cat6->a.dummy2, cat6->a.dummy3);
+				printf("\t{6: %x,%x}", cat6->a.dummy2, cat6->a.dummy3);
-			if ((cat6->a.must_be_one1 != 1) || (cat6->a.must_be_one2 != 1))
-				printf("{?? %d,%d ??}", cat6->a.must_be_one1, cat6->a.must_be_one2);
 			break;
 		case OPC_STG:
 		case OPC_STP:
 		case OPC_STI:
 			/* store instructions: */
-			if (cat6->b.dummy1|cat6->b.dummy2)
+			if (cat6->b.dummy2|cat6->b.dummy2)
-				printf("\t{6: %x,%x}", cat6->b.dummy1, cat6->b.dummy2);
+				printf("\t{6: %x,%x}", cat6->b.dummy2, cat6->b.dummy3);
-			if ((cat6->b.must_be_one1 != 1) || (cat6->b.must_be_one2 != 1) ||
+			if (cat6->b.ignore0)
-					(cat6->b.must_be_zero1 != 0))
+				printf("\t{?? %x}", cat6->b.ignore0);
-				printf("{?? %d,%d,%d ??}", cat6->b.must_be_one1, cat6->b.must_be_one2,
-						cat6->b.must_be_zero1);
 			break;
 		}
 	}

src/gallium/drivers/freedreno/ir3/instr-a3xx.h

@@ -572,15 +572,15 @@ typedef struct PACKED {
 	uint32_t opc_cat  : 3;
 } instr_cat5_t;
 
-/* used for load instructions: */
+/* [src1 + off], src2: */
 typedef struct PACKED {
 	/* dword0: */
-	uint32_t must_be_one1 : 1;
+	uint32_t mustbe1  : 1;
-	int16_t  off      : 13;
+	int32_t  off      : 13;
-	uint32_t src      : 8;
+	uint32_t src1     : 8;
-	uint32_t dummy1   : 1;
+	uint32_t src1_im  : 1;
-	uint32_t must_be_one2 : 1;
+	uint32_t src2_im  : 1;
-	int32_t  iim_val  : 8;
+	uint32_t src2     : 8;
 
 	/* dword1: */
 	uint32_t dst      : 8;
@@ -593,35 +593,38 @@ typedef struct PACKED {
 	uint32_t opc_cat  : 3;
 } instr_cat6a_t;
 
-/* used for store instructions: */
+/* [src1], src2: */
 typedef struct PACKED {
 	/* dword0: */
-	uint32_t must_be_zero1 : 1;
+	uint32_t mustbe0  : 1;
-	uint32_t src      : 8;
+	uint32_t src1     : 8;
-	uint32_t off_hi   : 5;   /* high bits of 'off'... ugly! */
+	uint32_t ignore0  : 13;
-	uint32_t dummy1   : 9;
+	uint32_t src1_im  : 1;
-	uint32_t must_be_one1 : 1;
+	uint32_t src2_im  : 1;
-	int32_t  iim_val  : 8;
+	uint32_t src2     : 8;
 
 	/* dword1: */
-	uint16_t off      : 8;
-	uint32_t must_be_one2 : 1;
 	uint32_t dst      : 8;
+	uint32_t dummy2   : 9;
 	uint32_t type     : 3;
-	uint32_t dummy2   : 2;
+	uint32_t dummy3   : 2;
 	uint32_t opc      : 5;
 	uint32_t jmp_tgt  : 1;
 	uint32_t sync     : 1;
 	uint32_t opc_cat  : 3;
 } instr_cat6b_t;
 
+/* I think some of the other cat6 instructions use additional
+ * sub-encodings..
+ */
+
 typedef union PACKED {
 	instr_cat6a_t a;
 	instr_cat6b_t b;
 	struct PACKED {
 		/* dword0: */
-		uint32_t pad1     : 24;
+		uint32_t has_off  : 1;
-		int32_t  iim_val  : 8;
+		uint32_t pad1     : 31;
 
 		/* dword1: */
 		uint32_t pad2     : 17;

src/gallium/drivers/freedreno/ir3/ir3.c

@@ -113,6 +113,8 @@ static uint32_t reg(struct ir3_register *reg, struct ir3_info *info,
 
 		if (reg->flags & IR3_REG_CONST) {
 			info->max_const = MAX2(info->max_const, max);
+		} else if (val.num == 63) {
+			/* ignore writes to dummy register r63.x */
 		} else if ((max != REG_A0) && (max != REG_P0)) {
 			if (reg->flags & IR3_REG_HALF) {
 				info->max_half_reg = MAX2(info->max_half_reg, max);
@@ -474,58 +476,40 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 static int emit_cat6(struct ir3_instruction *instr, void *ptr,
 		struct ir3_info *info)
 {
-	struct ir3_register *dst = instr->regs[0];
+	struct ir3_register *dst  = instr->regs[0];
-	struct ir3_register *src = instr->regs[1];
+	struct ir3_register *src1 = instr->regs[1];
+	struct ir3_register *src2 = (instr->regs_count >= 3) ? instr->regs[2] : NULL;
 	instr_cat6_t *cat6 = ptr;
 
-	iassert(instr->regs_count == 2);
+	iassert(instr->regs_count >= 2);
 
-	switch (instr->opc) {
+	if (instr->cat6.offset) {
-	/* load instructions: */
-	case OPC_LDG:
-	case OPC_LDP:
-	case OPC_LDL:
-	case OPC_LDLW:
-	case OPC_LDLV:
-	case OPC_PREFETCH: {
 		instr_cat6a_t *cat6a = ptr;
 
-		iassert(!((dst->flags ^ type_flags(instr->cat6.type)) & IR3_REG_HALF));
+		cat6->has_off = true;
 
-		cat6a->must_be_one1  = 1;
-		cat6a->must_be_one2  = 1;
-		cat6a->off = instr->cat6.offset;
-		cat6a->src = reg(src, info, instr->repeat, 0);
 		cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
-		break;
+		cat6a->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
-	}
+		cat6a->src1_im = !!(src1->flags & IR3_REG_IMMED);
-	/* store instructions: */
+		if (src2) {
-	case OPC_STG:
+			cat6a->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
-	case OPC_STP:
+			cat6a->src2_im = !!(src2->flags & IR3_REG_IMMED);
-	case OPC_STL:
+		}
-	case OPC_STLW:
+		cat6a->off = instr->cat6.offset;
-	case OPC_STI: {
+	} else {
 		instr_cat6b_t *cat6b = ptr;
-		uint32_t src_flags = type_flags(instr->cat6.type);
-		uint32_t dst_flags = (instr->opc == OPC_STI) ? IR3_REG_HALF : 0;
 
-		iassert(!((src->flags ^ src_flags) & IR3_REG_HALF));
+		cat6->has_off = false;
 
-		cat6b->must_be_one1  = 1;
+		cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
-		cat6b->must_be_one2  = 1;
+		cat6b->src1 = reg(src1, info, instr->repeat, IR3_REG_IMMED);
-		cat6b->src    = reg(src, info, instr->repeat, src_flags);
+		cat6b->src1_im = !!(src1->flags & IR3_REG_IMMED);
-		cat6b->off_hi = instr->cat6.offset >> 8;
+		if (src2) {
-		cat6b->off    = instr->cat6.offset;
+			cat6b->src2 = reg(src2, info, instr->repeat, IR3_REG_IMMED);
-		cat6b->dst    = reg(dst, info, instr->repeat, IR3_REG_R | dst_flags);
+			cat6b->src2_im = !!(src2->flags & IR3_REG_IMMED);
-
+		}
-		break;
-	}
-	default:
-		// TODO
-		break;
 	}
 
-	cat6->iim_val  = instr->cat6.iim_val;
 	cat6->type     = instr->cat6.type;
 	cat6->opc      = instr->opc;
 	cat6->jmp_tgt  = !!(instr->flags & IR3_INSTR_JP);

src/gallium/drivers/freedreno/ir3/ir3.h

@@ -420,8 +420,19 @@ static inline bool is_tex(struct ir3_instruction *instr)
 	return (instr->category == 5);
 }
 
+static inline bool is_mem(struct ir3_instruction *instr)
+{
+	return (instr->category == 6);
+}
+
 static inline bool is_input(struct ir3_instruction *instr)
 {
+	/* in some cases, ldlv is used to fetch varying without
+	 * interpolation.. fortunately inloc is the first src
+	 * register in either case
+	 */
+	if (is_mem(instr) && (instr->opc == OPC_LDLV))
+		return true;
 	return (instr->category == 2) && (instr->opc == OPC_BARY_F);
 }
 

src/gallium/drivers/freedreno/ir3/ir3_compiler.c

@@ -102,6 +102,11 @@ struct ir3_compile_context {
 	/* for calculating input/output positions/linkages: */
 	unsigned next_inloc;
 
+	/* a4xx (at least patchlevel 0) cannot seem to flat-interpolate
+	 * so we need to use ldlv.u32 to load the varying directly:
+	 */
+	bool flat_bypass;
+
 	unsigned num_internal_temps;
 	struct tgsi_src_register internal_temps[8];
 
@@ -198,9 +203,13 @@ compile_init(struct ir3_compile_context *ctx, struct ir3_shader_variant *so,
 	} else if (ir3_shader_gpuid(so->shader) >= 400) {
 		/* a4xx seems to have *no* sam.p */
 		lconfig.lower_TXP = ~0;  /* lower all txp */
+		/* need special handling for "flat" */
+		ctx->flat_bypass = true;
 	} else {
 		/* a3xx just needs to avoid sam.p for 3d tex */
 		lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
+		/* no special handling for "flat" */
+		ctx->flat_bypass = false;
 	}
 
 	ctx->tokens = tgsi_transform_lowering(&lconfig, tokens, &ctx->info);
@@ -1537,6 +1546,7 @@ trans_txq(const struct instr_translater *t,
 	struct tgsi_dst_register *dst = &inst->Dst[0].Register;
 	struct tgsi_src_register *level = &inst->Src[0].Register;
 	struct tgsi_src_register *samp = &inst->Src[1].Register;
+	const struct target_info *tgt = &tex_targets[inst->Texture.Texture];
 	struct tex_info tinf;
 
 	memset(&tinf, 0, sizeof(tinf));
@@ -1550,8 +1560,67 @@ trans_txq(const struct instr_translater *t,
 	instr->cat5.tex  = samp->Index;
 	instr->flags |= tinf.flags;
 
-	add_dst_reg_wrmask(ctx, instr, dst, 0, dst->WriteMask);
+	if (tgt->array && (dst->WriteMask & (1 << tgt->dims))) {
-	add_src_reg_wrmask(ctx, instr, level, level->SwizzleX, 0x1);
+		/* Array size actually ends up in .w rather than .z. This doesn't
+		 * matter for miplevel 0, but for higher mips the value in z is
+		 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
+		 * returned, which means that we have to add 1 to it for arrays.
+		 */
+		struct tgsi_dst_register tmp_dst;
+		struct tgsi_src_register *tmp_src;
+		type_t type_mov = get_utype(ctx);
+
+		tmp_src = get_internal_temp(ctx, &tmp_dst);
+		add_dst_reg_wrmask(ctx, instr, &tmp_dst, 0,
+						   dst->WriteMask | TGSI_WRITEMASK_W);
+		add_src_reg_wrmask(ctx, instr, level, level->SwizzleX, 0x1);
+
+		if (dst->WriteMask & TGSI_WRITEMASK_X) {
+			instr = instr_create(ctx, 1, 0);
+			instr->cat1.src_type = type_mov;
+			instr->cat1.dst_type = type_mov;
+			add_dst_reg(ctx, instr, dst, 0);
+			add_src_reg(ctx, instr, tmp_src, src_swiz(tmp_src, 0));
+		}
+
+		if (tgt->dims == 2) {
+			if (dst->WriteMask & TGSI_WRITEMASK_Y) {
+				instr = instr_create(ctx, 1, 0);
+				instr->cat1.src_type = type_mov;
+				instr->cat1.dst_type = type_mov;
+				add_dst_reg(ctx, instr, dst, 1);
+				add_src_reg(ctx, instr, tmp_src, src_swiz(tmp_src, 1));
+			}
+		}
+
+		instr = instr_create(ctx, 2, OPC_ADD_U);
+		add_dst_reg(ctx, instr, dst, tgt->dims);
+		add_src_reg(ctx, instr, tmp_src, src_swiz(tmp_src, 3));
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = 1;
+	} else {
+		add_dst_reg_wrmask(ctx, instr, dst, 0, dst->WriteMask);
+		add_src_reg_wrmask(ctx, instr, level, level->SwizzleX, 0x1);
+	}
+
+	if (dst->WriteMask & TGSI_WRITEMASK_W) {
+		/* The # of levels comes from getinfo.z. We need to add 1 to it, since
+		 * the value in TEX_CONST_0 is zero-based.
+		 */
+		struct tgsi_dst_register tmp_dst;
+		struct tgsi_src_register *tmp_src;
+
+		tmp_src = get_internal_temp(ctx, &tmp_dst);
+		instr = instr_create(ctx, 5, OPC_GETINFO);
+		instr->cat5.type = get_utype(ctx);
+		instr->cat5.samp = samp->Index;
+		instr->cat5.tex  = samp->Index;
+		add_dst_reg_wrmask(ctx, instr, &tmp_dst, 0, TGSI_WRITEMASK_Z);
+
+		instr = instr_create(ctx, 2, OPC_ADD_U);
+		add_dst_reg(ctx, instr, dst, 3);
+		add_src_reg(ctx, instr, tmp_src, src_swiz(tmp_src, 2));
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = 1;
+	}
 }
 
 /* DDX/DDY */
@@ -2718,11 +2787,23 @@ decl_semantic(const struct tgsi_declaration_semantic *sem)
 
 static struct ir3_instruction *
 decl_in_frag_bary(struct ir3_compile_context *ctx, unsigned regid,
-		unsigned j, unsigned inloc)
+		unsigned j, unsigned inloc, bool use_ldlv)
 {
 	struct ir3_instruction *instr;
 	struct ir3_register *src;
 
+	if (use_ldlv) {
+		/* ldlv.u32 dst, l[#inloc], 1 */
+		instr = instr_create(ctx, 6, OPC_LDLV);
+		instr->cat6.type = TYPE_U32;
+		instr->cat6.iim_val = 1;
+		ir3_reg_create(instr, regid, 0);   /* dummy dst */
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = inloc;
+		ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = 1;
+
+		return instr;
+	}
+
 	/* bary.f dst, #inloc, r0.x */
 	instr = instr_create(ctx, 2, OPC_BARY_F);
 	ir3_reg_create(instr, regid, 0);   /* dummy dst */
@@ -2916,9 +2997,31 @@ decl_in(struct ir3_compile_context *ctx, struct tgsi_full_declaration *decl)
 					so->frag_face = true;
 					instr = decl_in_frag_face(ctx, r + j, j);
 				} else {
+					bool use_ldlv = false;
+
+					/* I don't believe it is valid to not have Interp
+					 * on a normal frag shader input, and various parts
+					 * that that handle flat/smooth shading make this
+					 * assumption as well.
+					 */
+					compile_assert(ctx, decl->Declaration.Interpolate);
+
+					if (ctx->flat_bypass) {
+						switch (decl->Interp.Interpolate) {
+						case TGSI_INTERPOLATE_COLOR:
+							if (!ctx->so->key.rasterflat)
+								break;
+							/* fallthrough */
+						case TGSI_INTERPOLATE_CONSTANT:
+							use_ldlv = true;
+							break;
+						}
+					}
+
 					so->inputs[n].bary = true;
+
 					instr = decl_in_frag_bary(ctx, r + j, j,
-							so->inputs[n].inloc + j - 8);
+							so->inputs[n].inloc + j - 8, use_ldlv);
 				}
 			} else {
 				instr = create_input(ctx->block, NULL, (i * 4) + j);
@@ -3220,7 +3323,7 @@ ir3_compile_shader(struct ir3_shader_variant *so,
 	if (key.binning_pass) {
 		for (i = 0, j = 0; i < so->outputs_count; i++) {
 			unsigned name = sem2name(so->outputs[i].semantic);
-			unsigned idx = sem2name(so->outputs[i].semantic);
+			unsigned idx = sem2idx(so->outputs[i].semantic);
 
 			/* throw away everything but first position/psize */
 			if ((idx == 0) && ((name == TGSI_SEMANTIC_POSITION) ||

src/gallium/drivers/freedreno/ir3/ir3_depth.c

@@ -67,7 +67,7 @@ int ir3_delayslots(struct ir3_instruction *assigner,
 		return 6;
 
 	/* handled via sync flags: */
-	if (is_sfu(assigner) || is_tex(assigner))
+	if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner))
 		return 0;
 
 	/* assigner must be alu: */

src/gallium/drivers/freedreno/ir3/ir3_group.c

@@ -50,50 +50,7 @@ static bool check_stop(struct ir3_instruction *instr)
 	return false;
 }
 
-/* bleh.. we need to do the same group_n() thing for both inputs/outputs
+static struct ir3_instruction * create_mov(struct ir3_instruction *instr)
- * (where we have a simple instr[] array), and fanin nodes (where we have
- * an extra indirection via reg->instr).
- */
-struct group_ops {
-	struct ir3_instruction *(*get)(void *arr, int idx);
-	void (*set)(void *arr, int idx, struct ir3_instruction *instr);
-};
-
-static struct ir3_instruction *arr_get(void *arr, int idx)
-{
-	return ((struct ir3_instruction **)arr)[idx];
-}
-static void arr_set_out(void *arr, int idx, struct ir3_instruction *instr)
-{
-	((struct ir3_instruction **)arr)[idx] = instr;
-}
-static void arr_set_in(void *arr, int idx, struct ir3_instruction *instr)
-{
-	debug_printf("cannot insert mov before input!\n");
-	debug_assert(0);
-}
-static struct group_ops arr_ops_out = { arr_get, arr_set_out };
-static struct group_ops arr_ops_in = { arr_get, arr_set_in };
-
-static struct ir3_instruction *instr_get(void *arr, int idx)
-{
-	return ssa(((struct ir3_instruction *)arr)->regs[idx+1]);
-}
-static void instr_set(void *arr, int idx, struct ir3_instruction *instr)
-{
-	((struct ir3_instruction *)arr)->regs[idx+1]->instr = instr;
-}
-static struct group_ops instr_ops = { instr_get, instr_set };
-
-
-
-static bool conflicts(struct ir3_instruction *a, struct ir3_instruction *b)
-{
-	return (a && b) && (a != b);
-}
-
-static struct ir3_instruction *
-create_mov(struct ir3_instruction *instr)
 {
 	struct ir3_instruction *mov;
 
@@ -106,6 +63,67 @@ create_mov(struct ir3_instruction *instr)
 	return mov;
 }
 
+/* bleh.. we need to do the same group_n() thing for both inputs/outputs
+ * (where we have a simple instr[] array), and fanin nodes (where we have
+ * an extra indirection via reg->instr).
+ */
+struct group_ops {
+	struct ir3_instruction *(*get)(void *arr, int idx);
+	void (*insert_mov)(void *arr, int idx, struct ir3_instruction *instr);
+};
+
+static struct ir3_instruction *arr_get(void *arr, int idx)
+{
+	return ((struct ir3_instruction **)arr)[idx];
+}
+static void arr_insert_mov_out(void *arr, int idx, struct ir3_instruction *instr)
+{
+	((struct ir3_instruction **)arr)[idx] = create_mov(instr);
+}
+static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr)
+{
+	/* so, we can't insert a mov in front of a meta:in.. and the downstream
+	 * instruction already has a pointer to 'instr'.  So we cheat a bit and
+	 * morph the meta:in instruction into a mov and insert a new meta:in
+	 * in front.
+	 */
+	struct ir3_instruction *in;
+
+	debug_assert(instr->regs_count == 1);
+
+	in = ir3_instr_create(instr->block, -1, OPC_META_INPUT);
+	in->inout.block = instr->block;
+	ir3_reg_create(in, instr->regs[0]->num, 0);
+
+	/* create src reg for meta:in and fixup to now be a mov: */
+	ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in;
+	instr->category = 1;
+	instr->opc = 0;
+	instr->cat1.src_type = TYPE_F32;
+	instr->cat1.dst_type = TYPE_F32;
+
+	((struct ir3_instruction **)arr)[idx] = in;
+}
+static struct group_ops arr_ops_out = { arr_get, arr_insert_mov_out };
+static struct group_ops arr_ops_in = { arr_get, arr_insert_mov_in };
+
+static struct ir3_instruction *instr_get(void *arr, int idx)
+{
+	return ssa(((struct ir3_instruction *)arr)->regs[idx+1]);
+}
+static void instr_insert_mov(void *arr, int idx, struct ir3_instruction *instr)
+{
+	((struct ir3_instruction *)arr)->regs[idx+1]->instr = create_mov(instr);
+}
+static struct group_ops instr_ops = { instr_get, instr_insert_mov };
+
+
+
+static bool conflicts(struct ir3_instruction *a, struct ir3_instruction *b)
+{
+	return (a && b) && (a != b);
+}
+
 static void group_n(struct group_ops *ops, void *arr, unsigned n)
 {
 	unsigned i, j;
@@ -135,8 +153,7 @@ restart:
 					conflict = true;
 
 			if (conflict) {
-				instr = create_mov(instr);
+				ops->insert_mov(arr, i, instr);
-				ops->set(arr, i, instr);
 				/* inserting the mov may have caused a conflict
 				 * against the previous:
 				 */

src/gallium/drivers/freedreno/ir3/ir3_legalize.c

@@ -168,6 +168,8 @@ static void legalize(struct ir3_legalize_ctx *ctx)
 			 */
 			ctx->has_samp = true;
 			regmask_set(&needs_sy, n->regs[0]);
+		} else if (is_mem(n)) {
+			regmask_set(&needs_sy, n->regs[0]);
 		}
 
 		/* both tex/sfu appear to not always immediately consume
@@ -185,8 +187,44 @@ static void legalize(struct ir3_legalize_ctx *ctx)
 			last_input = n;
 	}
 
-	if (last_input)
+	if (last_input) {
+		/* special hack.. if using ldlv to bypass interpolation,
+		 * we need to insert a dummy bary.f on which we can set
+		 * the (ei) flag:
+		 */
+		if (is_mem(last_input) && (last_input->opc == OPC_LDLV)) {
+			int i, cnt;
+
+			/* note that ir3_instr_create() inserts into
+			 * shader->instrs[] and increments the count..
+			 * so we need to bump up the cnt initially (to
+			 * avoid it clobbering the last real instr) and
+			 * restore it after.
+			 */
+			cnt = ++shader->instrs_count;
+
+			/* inserting instructions would be a bit nicer if list.. */
+			for (i = cnt - 2; i >= 0; i--) {
+				if (shader->instrs[i] == last_input) {
+
+					/* (ss)bary.f (ei)r63.x, 0, r0.x */
+					last_input = ir3_instr_create(block, 2, OPC_BARY_F);
+					last_input->flags |= IR3_INSTR_SS;
+					ir3_reg_create(last_input, regid(63, 0), 0);
+					ir3_reg_create(last_input, 0, IR3_REG_IMMED)->iim_val = 0;
+					ir3_reg_create(last_input, regid(0, 0), 0);
+
+					shader->instrs[i + 1] = last_input;
+
+					break;
+				}
+				shader->instrs[i + 1] = shader->instrs[i];
+			}
+
+			shader->instrs_count = cnt;
+		}
 		last_input->regs[0]->flags |= IR3_REG_EI;
+	}
 
 	if (last_rel)
 		last_rel->flags |= IR3_INSTR_UL;

src/gallium/drivers/freedreno/ir3/ir3_shader.c

@@ -246,6 +246,7 @@ ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
 		key.color_two_side = false;
 		key.half_precision = false;
 		key.alpha = false;
+		key.rasterflat = false;
 		if (key.has_per_samp) {
 			key.fsaturate_s = 0;
 			key.fsaturate_t = 0;

src/gallium/drivers/freedreno/ir3/ir3_shader.h

@@ -77,6 +77,10 @@ struct ir3_shader_key {
 			 * let's start with this and see how it goes:
 			 */
 			unsigned alpha : 1;
+			/* used when shader needs to handle flat varyings (a4xx),
+			 * for TGSI_INTERPOLATE_COLOR:
+			 */
+			unsigned rasterflat : 1;
 		};
 		uint32_t global;
 	};

src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp

@@ -1116,6 +1116,7 @@ CodeEmitterGK110::emitTEX(const TexInstruction *i)
    if (i->tex.useOffsets == 1) {
       switch (i->op) {
       case OP_TXF: code[1] |= 0x200; break;
+      case OP_TXD: code[1] |= 0x00400000; break;
       default: code[1] |= 0x800; break;
       }
    }

src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

@@ -422,7 +422,9 @@ ConstantFolding::expr(Instruction *i,
             b->data.f32 = 0.0f;
       }
       switch (i->dType) {
-      case TYPE_F32: res.data.f32 = a->data.f32 * b->data.f32; break;
+      case TYPE_F32:
+         res.data.f32 = a->data.f32 * b->data.f32 * exp2f(i->postFactor);
+         break;
       case TYPE_F64: res.data.f64 = a->data.f64 * b->data.f64; break;
       case TYPE_S32:
          if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
@@ -550,6 +552,7 @@ ConstantFolding::expr(Instruction *i,
 
    i->src(0).mod = Modifier(0);
    i->src(1).mod = Modifier(0);
+   i->postFactor = 0;
 
    i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), res.data.u32));
    i->setSrc(1, NULL);
@@ -653,7 +656,7 @@ ConstantFolding::tryCollapseChainedMULs(Instruction *mul2,
    Instruction *insn;
    Instruction *mul1 = NULL; // mul1 before mul2
    int e = 0;
-   float f = imm2.reg.data.f32;
+   float f = imm2.reg.data.f32 * exp2f(mul2->postFactor);
    ImmediateValue imm1;
 
    assert(mul2->op == OP_MUL && mul2->dType == TYPE_F32);
@@ -753,9 +756,10 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
          i->op = OP_MOV;
          i->setSrc(0, new_ImmediateValue(prog, 0u));
          i->src(0).mod = Modifier(0);
+         i->postFactor = 0;
          i->setSrc(1, NULL);
       } else
-      if (imm0.isInteger(1) || imm0.isInteger(-1)) {
+      if (!i->postFactor && (imm0.isInteger(1) || imm0.isInteger(-1))) {
          if (imm0.isNegative())
             i->src(t).mod = i->src(t).mod ^ Modifier(NV50_IR_MOD_NEG);
          i->op = i->src(t).mod.getOp();
@@ -768,7 +772,7 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
             i->src(0).mod = 0;
          i->setSrc(1, NULL);
       } else
-      if (imm0.isInteger(2) || imm0.isInteger(-2)) {
+      if (!i->postFactor && (imm0.isInteger(2) || imm0.isInteger(-2))) {
          if (imm0.isNegative())
             i->src(t).mod = i->src(t).mod ^ Modifier(NV50_IR_MOD_NEG);
          i->op = OP_ADD;

src/gallium/drivers/nouveau/nouveau_buffer.c

@@ -846,17 +846,28 @@ nouveau_scratch_bo_alloc(struct nouveau_context *nv, struct nouveau_bo **pbo,
                          4096, size, NULL, pbo);
 }
 
+static void
+nouveau_scratch_unref_bos(void *d)
+{
+   struct runout *b = d;
+   int i;
+
+   for (i = 0; i < b->nr; ++i)
+      nouveau_bo_ref(NULL, &b->bo[i]);
+
+   FREE(b);
+}
+
 void
 nouveau_scratch_runout_release(struct nouveau_context *nv)
 {
-   if (!nv->scratch.nr_runout)
+   if (!nv->scratch.runout)
+      return;
+
+   if (!nouveau_fence_work(nv->screen->fence.current, nouveau_scratch_unref_bos,
+         nv->scratch.runout))
       return;
-   do {
-      --nv->scratch.nr_runout;
-      nouveau_bo_ref(NULL, &nv->scratch.runout[nv->scratch.nr_runout]);
-   } while (nv->scratch.nr_runout);
 
-   FREE(nv->scratch.runout);
    nv->scratch.end = 0;
    nv->scratch.runout = NULL;
 }
@@ -868,21 +879,26 @@ static INLINE boolean
 nouveau_scratch_runout(struct nouveau_context *nv, unsigned size)
 {
    int ret;
-   const unsigned n = nv->scratch.nr_runout++;
+   unsigned n;
 
-   nv->scratch.runout = REALLOC(nv->scratch.runout,
+   if (nv->scratch.runout)
-                                (n + 0) * sizeof(*nv->scratch.runout),
+      n = nv->scratch.runout->nr;
-                                (n + 1) * sizeof(*nv->scratch.runout));
+   else
-   nv->scratch.runout[n] = NULL;
+      n = 0;
+   nv->scratch.runout = REALLOC(nv->scratch.runout, n == 0 ? 0 :
+                                (sizeof(*nv->scratch.runout) + (n + 0) * sizeof(void *)),
+                                 sizeof(*nv->scratch.runout) + (n + 1) * sizeof(void *));
+   nv->scratch.runout->nr = n + 1;
+   nv->scratch.runout->bo[n] = NULL;
 
-   ret = nouveau_scratch_bo_alloc(nv, &nv->scratch.runout[n], size);
+   ret = nouveau_scratch_bo_alloc(nv, &nv->scratch.runout->bo[n], size);
    if (!ret) {
-      ret = nouveau_bo_map(nv->scratch.runout[n], 0, NULL);
+      ret = nouveau_bo_map(nv->scratch.runout->bo[n], 0, NULL);
       if (ret)
-         nouveau_bo_ref(NULL, &nv->scratch.runout[--nv->scratch.nr_runout]);
+         nouveau_bo_ref(NULL, &nv->scratch.runout->bo[--nv->scratch.runout->nr]);
    }
    if (!ret) {
-      nv->scratch.current = nv->scratch.runout[n];
+      nv->scratch.current = nv->scratch.runout->bo[n];
       nv->scratch.offset = 0;
       nv->scratch.end = size;
       nv->scratch.map = nv->scratch.current->map;

src/gallium/drivers/nouveau/nouveau_context.h

@@ -40,8 +40,10 @@ struct nouveau_context {
       unsigned end;
       struct nouveau_bo *bo[NOUVEAU_MAX_SCRATCH_BUFS];
       struct nouveau_bo *current;
-      struct nouveau_bo **runout;
+      struct runout {
-      unsigned nr_runout;
+         unsigned nr;
+         struct nouveau_bo *bo[0];
+      } *runout;
       unsigned bo_size;
    } scratch;
 
@@ -71,7 +73,7 @@ static INLINE void
 nouveau_scratch_done(struct nouveau_context *nv)
 {
    nv->scratch.wrap = nv->scratch.id;
-   if (unlikely(nv->scratch.nr_runout))
+   if (unlikely(nv->scratch.runout))
       nouveau_scratch_runout_release(nv);
 }
 

src/gallium/drivers/nouveau/nv50/nv50_miptree.c

@@ -29,7 +29,8 @@
 #include "nv50/nv50_resource.h"
 
 uint32_t
-nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz)
+nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz,
+                                 boolean is_3d)
 {
    uint32_t tile_mode = 0x000;
 
@@ -41,7 +42,7 @@ nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz)
    else
    if (ny >  8) tile_mode = 0x010; /* height 16 tiles */
 
-   if (nz == 1)
+   if (!is_3d)
       return tile_mode;
    else
       if (tile_mode > 0x020)
@@ -52,14 +53,15 @@ nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz)
    if (nz > 8) return tile_mode | 0x400; /* depth 16 tiles */
    if (nz > 4) return tile_mode | 0x300; /* depth 8 tiles */
    if (nz > 2) return tile_mode | 0x200; /* depth 4 tiles */
+   if (nz > 1) return tile_mode | 0x100; /* depth 2 tiles */
 
-   return tile_mode | 0x100;
+   return tile_mode;
 }
 
 static uint32_t
-nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz)
+nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, boolean is_3d)
 {
-   return nv50_tex_choose_tile_dims_helper(nx, ny * 2, nz);
+   return nv50_tex_choose_tile_dims_helper(nx, ny * 2, nz, is_3d);
 }
 
 static uint32_t
@@ -304,7 +306,7 @@ nv50_miptree_init_layout_tiled(struct nv50_miptree *mt)
 
       lvl->offset = mt->total_size;
 
-      lvl->tile_mode = nv50_tex_choose_tile_dims(nbx, nby, d);
+      lvl->tile_mode = nv50_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
 
       tsx = NV50_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
       tsy = NV50_TILE_SIZE_Y(lvl->tile_mode);

src/gallium/drivers/nouveau/nv50/nv50_query.c

@@ -41,7 +41,7 @@ struct nv50_query {
    uint32_t sequence;
    struct nouveau_bo *bo;
    uint32_t base;
-   uint32_t offset; /* base + i * 16 */
+   uint32_t offset; /* base + i * 32 */
    boolean ready;
    boolean flushed;
    boolean is64bit;
@@ -116,8 +116,8 @@ nv50_query_create(struct pipe_context *pipe, unsigned type, unsigned index)
    q->type = type;
 
    if (q->type == PIPE_QUERY_OCCLUSION_COUNTER) {
-      q->offset -= 16;
+      q->offset -= 32;
-      q->data -= 16 / sizeof(*q->data); /* we advance before query_begin ! */
+      q->data -= 32 / sizeof(*q->data); /* we advance before query_begin ! */
    }
 
    return (struct pipe_query *)q;
@@ -150,8 +150,8 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
     * initialized it to TRUE.
     */
    if (q->type == PIPE_QUERY_OCCLUSION_COUNTER) {
-      q->offset += 16;
+      q->offset += 32;
-      q->data += 16 / sizeof(*q->data);
+      q->data += 32 / sizeof(*q->data);
       if (q->offset - q->base == NV50_QUERY_ALLOC_SPACE)
          nv50_query_allocate(nv50, q, NV50_QUERY_ALLOC_SPACE);
 

src/gallium/drivers/nouveau/nv50/nv50_resource.h

@@ -34,7 +34,8 @@ nv50_screen_init_resource_functions(struct pipe_screen *pscreen);
 #endif /* __NVC0_RESOURCE_H__ */
 
 uint32_t
-nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz);
+nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz,
+                                 boolean is_3d);
 
 struct nv50_miptree_level {
    uint32_t offset;

src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c

@@ -29,9 +29,9 @@
 #include "nvc0/nvc0_resource.h"
 
 static uint32_t
-nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz)
+nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz, boolean is_3d)
 {
-   return nv50_tex_choose_tile_dims_helper(nx, ny, nz);
+   return nv50_tex_choose_tile_dims_helper(nx, ny, nz, is_3d);
 }
 
 static uint32_t
@@ -211,7 +211,7 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
 
       lvl->offset = mt->total_size;
 
-      lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d);
+      lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
 
       tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
       tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);

src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c

@@ -252,7 +252,12 @@ nvc0_tfb_validate(struct nvc0_context *nvc0)
 
    for (b = 0; b < nvc0->num_tfbbufs; ++b) {
       struct nvc0_so_target *targ = nvc0_so_target(nvc0->tfbbuf[b]);
-      struct nv04_resource *buf = nv04_resource(targ->pipe.buffer);
+      struct nv04_resource *buf;
+
+      if (!targ) {
+         IMMED_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 0);
+         continue;
+      }
 
       if (tfb)
          targ->stride = tfb->stride[b];
@@ -260,6 +265,8 @@ nvc0_tfb_validate(struct nvc0_context *nvc0)
       if (!(nvc0->tfbbuf_dirty & (1 << b)))
          continue;
 
+      buf = nv04_resource(targ->pipe.buffer);
+
       if (!targ->clean)
          nvc0_query_fifo_wait(push, targ->pq);
       BEGIN_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 5);

src/gallium/drivers/nouveau/nvc0/nvc0_state.c

@@ -1089,9 +1089,11 @@ nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
       pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
    }
    for (; i < nvc0->num_tfbbufs; ++i) {
-      nvc0->tfbbuf_dirty |= 1 << i;
+      if (nvc0->tfbbuf[i]) {
-      nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
+         nvc0->tfbbuf_dirty |= 1 << i;
-      pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
+         nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
+         pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
+      }
    }
    nvc0->num_tfbbufs = num_targets;
 

src/gallium/drivers/nouveau/nvc0/nvc0_surface.c

@@ -1401,11 +1401,14 @@ nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
       } else
       if (!nv50_2d_src_format_faithful(info->src.format)) {
          if (!util_format_is_luminance(info->src.format)) {
+            if (!nv50_2d_dst_format_ops_supported(info->dst.format))
+               eng3d = TRUE;
+            else
             if (util_format_is_intensity(info->src.format))
                eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
             else
-            if (!nv50_2d_dst_format_ops_supported(info->dst.format))
+            if (util_format_is_alpha(info->src.format))
-               eng3d = TRUE;
+               eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
             else
                eng3d = !nv50_2d_format_supported(info->src.format);
          }

src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c

@@ -28,6 +28,7 @@
  */
 
 #include <errno.h>
+#include <limits.h>
 #include <regex.h>
 #include <stdlib.h>
 #include <stdio.h>
@@ -528,7 +529,6 @@ void init_compiler(
 }
 
 #define MAX_LINE_LENGTH 100
-#define MAX_PATH_LENGTH 100
 
 unsigned load_program(
 	struct radeon_compiler *c,
@@ -536,14 +536,19 @@ unsigned load_program(
 	const char *filename)
 {
 	char line[MAX_LINE_LENGTH];
-	char path[MAX_PATH_LENGTH];
+	char path[PATH_MAX];
 	FILE *file;
 	unsigned *count;
 	char **string_store;
 	unsigned i = 0;
+	int n;
 
 	memset(line, 0, sizeof(line));
-	snprintf(path, MAX_PATH_LENGTH, TEST_PATH "/%s", filename);
+	n = snprintf(path, PATH_MAX, TEST_PATH "/%s", filename);
+	if (n < 0 || n >= PATH_MAX) {
+		return 0;
+	}
+
 	file = fopen(path, "r");
 	if (!file) {
 		return 0;

src/gallium/drivers/r300/r300_blit.c

@@ -803,6 +803,15 @@ static void r300_blit(struct pipe_context *pipe,
         (struct pipe_framebuffer_state*)r300->fb_state.state;
     struct pipe_blit_info info = *blit;
 
+    /* The driver supports sRGB textures but not framebuffers. Blitting
+     * from sRGB to sRGB should be the same as blitting from linear
+     * to linear, so use that, This avoids incorrect linearization.
+     */
+    if (util_format_is_srgb(info.src.format)) {
+      info.src.format = util_format_linear(info.src.format);
+      info.dst.format = util_format_linear(info.dst.format);
+    }
+
     /* MSAA resolve. */
     if (info.src.resource->nr_samples > 1 &&
         !util_format_is_depth_or_stencil(info.src.resource->format)) {

src/gallium/drivers/r300/r300_fs.c

@@ -170,24 +170,10 @@ static void get_external_state(
         }
 
         state->unit[i].non_normalized_coords = !s->state.normalized_coords;
-        state->unit[i].convert_unorm_to_snorm =
+        state->unit[i].convert_unorm_to_snorm = 0;
-                v->base.format == PIPE_FORMAT_RGTC1_SNORM ||
-                v->base.format == PIPE_FORMAT_LATC1_SNORM;
 
         /* Pass texture swizzling to the compiler, some lowering passes need it. */
-        if (v->base.format == PIPE_FORMAT_RGTC1_SNORM ||
+        if (state->unit[i].compare_mode_enabled) {
-            v->base.format == PIPE_FORMAT_LATC1_SNORM) {
-            unsigned char swizzle[4];
-
-            util_format_compose_swizzles(
-                            util_format_description(v->base.format)->swizzle,
-                            v->swizzle,
-                            swizzle);
-
-            state->unit[i].texture_swizzle =
-                    RC_MAKE_SWIZZLE(swizzle[0], swizzle[1],
-                                    swizzle[2], swizzle[3]);
-        } else if (state->unit[i].compare_mode_enabled) {
             state->unit[i].texture_swizzle =
                 RC_MAKE_SWIZZLE(v->swizzle[0], v->swizzle[1],
                                 v->swizzle[2], v->swizzle[3]);

src/gallium/drivers/r300/r300_texture.c

@@ -169,20 +169,21 @@ uint32_t r300_translate_texformat(enum pipe_format format,
 
     /* Add swizzling. */
     /* The RGTC1_SNORM and LATC1_SNORM swizzle is done in the shader. */
-    if (format != PIPE_FORMAT_RGTC1_SNORM &&
+    if (util_format_is_compressed(format) &&
+        dxtc_swizzle &&
+        format != PIPE_FORMAT_RGTC2_UNORM &&
+        format != PIPE_FORMAT_RGTC2_SNORM &&
+        format != PIPE_FORMAT_LATC2_UNORM &&
+        format != PIPE_FORMAT_LATC2_SNORM &&
+        format != PIPE_FORMAT_RGTC1_UNORM &&
+        format != PIPE_FORMAT_RGTC1_SNORM &&
+        format != PIPE_FORMAT_LATC1_UNORM &&
         format != PIPE_FORMAT_LATC1_SNORM) {
-        if (util_format_is_compressed(format) &&
+        result |= r300_get_swizzle_combined(desc->swizzle, swizzle_view,
-            dxtc_swizzle &&
+                                            TRUE);
-            format != PIPE_FORMAT_RGTC2_UNORM &&
+    } else {
-            format != PIPE_FORMAT_RGTC2_SNORM &&
+        result |= r300_get_swizzle_combined(desc->swizzle, swizzle_view,
-            format != PIPE_FORMAT_LATC2_UNORM &&
+                                            FALSE);
-            format != PIPE_FORMAT_LATC2_SNORM) {
-            result |= r300_get_swizzle_combined(desc->swizzle, swizzle_view,
-                                                TRUE);
-        } else {
-            result |= r300_get_swizzle_combined(desc->swizzle, swizzle_view,
-                                                FALSE);
-        }
     }
 
     /* S3TC formats. */
@@ -213,6 +214,7 @@ uint32_t r300_translate_texformat(enum pipe_format format,
         switch (format) {
             case PIPE_FORMAT_RGTC1_SNORM:
             case PIPE_FORMAT_LATC1_SNORM:
+                result |= sign_bit[0];
             case PIPE_FORMAT_LATC1_UNORM:
             case PIPE_FORMAT_RGTC1_UNORM:
                 return R500_TX_FORMAT_ATI1N | result;
@@ -936,14 +938,16 @@ static void r300_texture_setup_fb_state(struct r300_surface *surf)
         surf->pitch_zmask = tex->tex.zmask_stride_in_pixels[level];
         surf->pitch_hiz = tex->tex.hiz_stride_in_pixels[level];
     } else {
+        enum pipe_format format = util_format_linear(surf->base.format);
+
         surf->pitch =
                 stride |
-                r300_translate_colorformat(surf->base.format) |
+                r300_translate_colorformat(format) |
                 R300_COLOR_TILE(tex->tex.macrotile[level]) |
                 R300_COLOR_MICROTILE(tex->tex.microtile);
-        surf->format = r300_translate_out_fmt(surf->base.format);
+        surf->format = r300_translate_out_fmt(format);
         surf->colormask_swizzle =
-            r300_translate_colormask_swizzle(surf->base.format);
+            r300_translate_colormask_swizzle(format);
         surf->pitch_cmask = tex->tex.cmask_stride_in_pixels;
     }
 }

src/gallium/drivers/r600/sb/sb_sched.cpp

@@ -266,7 +266,7 @@ bool rp_gpr_tracker::try_reserve(alu_node* n) {
 
 	for (i = 0; i < nsrc; ++i) {
 		value *v = n->src[i];
-		if (v->is_readonly()) {
+		if (v->is_readonly() || v->is_undef()) {
 			const_count++;
 			if (trans && const_count == 3)
 				break;
@@ -295,7 +295,7 @@ bool rp_gpr_tracker::try_reserve(alu_node* n) {
 	if (need_unreserve && i--) {
 		do {
 			value *v = n->src[i];
-			if (!v->is_readonly()) {
+			if (!v->is_readonly() && !v->is_undef()) {
 			if (i == 1 && opt)
 				continue;
 			unreserve(bs_cycle(trans, bs, i), n->bc.src[i].sel,

src/gallium/drivers/radeon/radeon_llvm_emit.c

@@ -80,10 +80,6 @@ void radeon_llvm_shader_type(LLVMValueRef F, unsigned type)
 	sprintf(Str, "%1d", llvm_type);
 
 	LLVMAddTargetDependentFunctionAttr(F, "ShaderType", Str);
-
-	if (type != TGSI_PROCESSOR_COMPUTE) {
-		LLVMAddTargetDependentFunctionAttr(F, "unsafe-fp-math", "true");
-	}
 }
 
 static void init_r600_target()

src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c

@@ -748,7 +748,7 @@ static void txp_fetch_args(
 	const struct tgsi_full_instruction * inst = emit_data->inst;
 	LLVMValueRef src_w;
 	unsigned chan;
-	LLVMValueRef coords[4];
+	LLVMValueRef coords[5];
 
 	emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 	src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);

src/gallium/drivers/radeonsi/si_compute.c

@@ -130,7 +130,8 @@ static void *si_create_compute_state(
 	        for (i = 0; i < program->num_kernels; i++) {
 		        LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
                                                         code, header->num_bytes);
-			si_compile_llvm(sctx->screen, &program->kernels[i], mod);
+			si_compile_llvm(sctx->screen, &program->kernels[i], sctx->tm,
+					mod);
 			LLVMDisposeModule(mod);
 		}
 	}

src/gallium/drivers/radeonsi/si_pipe.c

@@ -69,6 +69,11 @@ static void si_destroy_context(struct pipe_context *context)
 	si_pm4_cleanup(sctx);
 
 	r600_common_context_cleanup(&sctx->b);
+
+#if HAVE_LLVM >= 0x0306
+	LLVMDisposeTargetMachine(sctx->tm);
+#endif
+
 	FREE(sctx);
 }
 
@@ -77,6 +82,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
 	struct si_context *sctx = CALLOC_STRUCT(si_context);
 	struct si_screen* sscreen = (struct si_screen *)screen;
 	struct radeon_winsys *ws = sscreen->b.ws;
+	LLVMTargetRef r600_target;
+#if HAVE_LLVM >= 0x0306
+	const char *triple = "amdgcn--";
+#else
+	const char *triple = "r600--";
+#endif
 	int shader, i;
 
 	if (sctx == NULL)
@@ -167,6 +178,17 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
 	 */
 	sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
 
+#if HAVE_LLVM >= 0x0306
+	/* Initialize LLVM TargetMachine */
+	r600_target = radeon_llvm_get_r600_target(triple);
+	sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
+					   r600_get_llvm_processor_name(sscreen->b.family),
+					   "+DumpCode,+vgpr-spilling",
+					   LLVMCodeGenLevelDefault,
+					   LLVMRelocDefault,
+					   LLVMCodeModelDefault);
+#endif
+
 	return &sctx->b.b;
 fail:
 	si_destroy_context(&sctx->b.b);
@@ -435,12 +457,6 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 	if (!sscreen->b.ws->unref(sscreen->b.ws))
 		return;
 
-#if HAVE_LLVM >= 0x0306
-	// r600_destroy_common_screen() frees sscreen, so we need to make
-	// sure to dispose the TargetMachine before we call it.
-	LLVMDisposeTargetMachine(sscreen->tm);
-#endif
-
 	r600_destroy_common_screen(&sscreen->b);
 }
 
@@ -498,12 +514,7 @@ static bool si_initialize_pipe_config(struct si_screen *sscreen)
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 {
 	struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
-	LLVMTargetRef r600_target;
+
-#if HAVE_LLVM >= 0x0306
-	const char *triple = "amdgcn--";
-#else
-	const char *triple = "r600--";
-#endif
 	if (sscreen == NULL) {
 		return NULL;
 	}
@@ -531,13 +542,5 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 	/* Create the auxiliary context. This must be done last. */
 	sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
 
-#if HAVE_LLVM >= 0x0306
-	/* Initialize LLVM TargetMachine */
-	r600_target = radeon_llvm_get_r600_target(triple);
-	sscreen->tm = LLVMCreateTargetMachine(r600_target, triple,
-				r600_get_llvm_processor_name(sscreen->b.family),
-				"+DumpCode,+vgpr-spilling", LLVMCodeGenLevelDefault, LLVMRelocDefault,
-				LLVMCodeModelDefault);
-#endif
 	return &sscreen->b.b;
 }

src/gallium/drivers/radeonsi/si_pipe.h

@@ -83,7 +83,6 @@ struct si_compute;
 
 struct si_screen {
 	struct r600_common_screen	b;
-	LLVMTargetMachineRef		tm;
 };
 
 struct si_sampler_view {
@@ -200,6 +199,8 @@ struct si_context {
 	struct pipe_resource	*esgs_ring;
 	struct pipe_resource	*gsvs_ring;
 
+	LLVMTargetMachineRef		tm;
+
 	/* SI state handling */
 	union si_state	queued;
 	union si_state	emitted;

src/gallium/drivers/radeonsi/si_shader.c

@@ -72,6 +72,7 @@ struct si_shader_context
 	int param_streamout_offset[4];
 	int param_vertex_id;
 	int param_instance_id;
+	LLVMTargetMachineRef tm;
 	LLVMValueRef const_md;
 	LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
 	LLVMValueRef ddxy_lds;
@@ -1520,7 +1521,7 @@ static void tex_fetch_args(
 	const struct tgsi_full_instruction * inst = emit_data->inst;
 	unsigned opcode = inst->Instruction.Opcode;
 	unsigned target = inst->Texture.Texture;
-	LLVMValueRef coords[4];
+	LLVMValueRef coords[5];
 	LLVMValueRef address[16];
 	int ref_pos;
 	unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
@@ -2638,13 +2639,13 @@ int si_shader_binary_read(struct si_screen *sscreen,
 }
 
 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
-							LLVMModuleRef mod)
+		    LLVMTargetMachineRef tm, LLVMModuleRef mod)
 {
 	int r = 0;
 	bool dump = r600_can_dump_shader(&sscreen->b,
 			shader->selector ? shader->selector->tokens : NULL);
 	r = radeon_llvm_compile(mod, &shader->binary,
-		r600_get_llvm_processor_name(sscreen->b.family), dump, sscreen->tm);
+		r600_get_llvm_processor_name(sscreen->b.family), dump, tm);
 
 	if (r) {
 		return r;
@@ -2732,7 +2733,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 		fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
 
 	r = si_compile_llvm(sscreen, si_shader_ctx->shader,
-			    bld_base->base.gallivm->module);
+			    si_shader_ctx->tm, bld_base->base.gallivm->module);
 
 	radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
 
@@ -2740,7 +2741,45 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 	return r;
 }
 
-int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
+static void si_dump_key(unsigned shader, union si_shader_key *key)
+{
+	int i;
+
+	fprintf(stderr, "SHADER KEY\n");
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		fprintf(stderr, "  instance_divisors = {");
+		for (i = 0; i < Elements(key->vs.instance_divisors); i++)
+			fprintf(stderr, !i ? "%u" : ", %u",
+				key->vs.instance_divisors[i]);
+		fprintf(stderr, "}\n");
+
+		if (key->vs.as_es)
+			fprintf(stderr, "  gs_used_inputs = 0x%"PRIx64"\n",
+				key->vs.gs_used_inputs);
+		fprintf(stderr, "  as_es = %u\n", key->vs.as_es);
+		break;
+
+	case PIPE_SHADER_GEOMETRY:
+		break;
+
+	case PIPE_SHADER_FRAGMENT:
+		fprintf(stderr, "  export_16bpc = 0x%X\n", key->ps.export_16bpc);
+		fprintf(stderr, "  last_cbuf = %u\n", key->ps.last_cbuf);
+		fprintf(stderr, "  color_two_side = %u\n", key->ps.color_two_side);
+		fprintf(stderr, "  alpha_func = %u\n", key->ps.alpha_func);
+		fprintf(stderr, "  alpha_to_one = %u\n", key->ps.alpha_to_one);
+		fprintf(stderr, "  poly_stipple = %u\n", key->ps.poly_stipple);
+		break;
+
+	default:
+		assert(0);
+	}
+}
+
+int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
+		     struct si_shader *shader)
 {
 	struct si_shader_selector *sel = shader->selector;
 	struct tgsi_token *tokens = sel->tokens;
@@ -2812,6 +2851,7 @@ int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
 	si_shader_ctx.shader = shader;
 	si_shader_ctx.type = tgsi_get_processor_type(tokens);
 	si_shader_ctx.screen = sscreen;
+	si_shader_ctx.tm = tm;
 
 	switch (si_shader_ctx.type) {
 	case TGSI_PROCESSOR_VERTEX:
@@ -2867,7 +2907,7 @@ int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
 	radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
 
 	mod = bld_base->base.gallivm->module;
-	r = si_compile_llvm(sscreen, shader, mod);
+	r = si_compile_llvm(sscreen, shader, tm, mod);
 	if (r) {
 		fprintf(stderr, "LLVM failed to compile shader\n");
 		goto out;

src/gallium/drivers/radeonsi/si_shader.h

@@ -181,9 +181,10 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 }
 
 /* radeonsi_shader.c */
-int si_shader_create(struct si_screen *sscreen, struct si_shader *shader);
+int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
+		     struct si_shader *shader);
 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
-		    LLVMModuleRef mod);
+		    LLVMTargetMachineRef tm, LLVMModuleRef mod);
 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader);
 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,

src/gallium/drivers/radeonsi/si_state.c

@@ -735,12 +735,16 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
  */
 static void si_update_dsa_stencil_ref(struct si_context *sctx)
 {
-	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+	struct si_pm4_state *pm4;
 	struct pipe_stencil_ref *ref = &sctx->stencil_ref;
-        struct si_state_dsa *dsa = sctx->queued.named.dsa;
+	struct si_state_dsa *dsa = sctx->queued.named.dsa;
 
-        if (pm4 == NULL)
+	if (!dsa)
-                return;
+		return;
+
+	pm4 = CALLOC_STRUCT(si_pm4_state);
+	if (pm4 == NULL)
+		return;
 
 	si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
 		       S_028430_STENCILTESTVAL(ref->ref_value[0]) |

src/gallium/drivers/radeonsi/si_state_draw.c

@@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
 {
 	struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
 	uint32_t cp_coher_cntl = 0;
-	uint32_t sqc_caches = 0;
 	uint32_t compute =
 		PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
 
 	/* SI has a bug that it always flushes ICACHE and KCACHE if either
-	 * bit is set. An alternative way is to write SQC_CACHES. */
+	 * bit is set. An alternative way is to write SQC_CACHES, but that
-	if (sctx->chip_class == SI &&
+	 * doesn't seem to work reliably. Since the bug doesn't affect
-	    sctx->flags & BOTH_ICACHE_KCACHE &&
+	 * correctness (it only does more work than necessary) and
-	    (sctx->flags & BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
+	 * the performance impact is likely negligible, there is no plan
-		sqc_caches =
+	 * to fix it.
-			S_008C08_INST_INVALIDATE(!!(sctx->flags & SI_CONTEXT_INV_ICACHE)) |
+	 */
-			S_008C08_DATA_INVALIDATE(!!(sctx->flags & SI_CONTEXT_INV_KCACHE));
+
-	} else {
+	if (sctx->flags & SI_CONTEXT_INV_ICACHE)
-		if (sctx->flags & SI_CONTEXT_INV_ICACHE)
+		cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
-			cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
+	if (sctx->flags & SI_CONTEXT_INV_KCACHE)
-		if (sctx->flags & SI_CONTEXT_INV_KCACHE)
+		cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
-			cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
-	}
 
 	if (sctx->flags & SI_CONTEXT_INV_TC_L1)
 		cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
@@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
 	 * It looks like SURFACE_SYNC flushes caches immediately and doesn't
 	 * wait for any engines. This should be last.
 	 */
-	if (sqc_caches) {
-		r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
-		cs->buf[cs->cdw-3] |= compute; /* set the compute bit in the header */
-	}
 	if (cp_coher_cntl) {
 		if (sctx->chip_class >= CIK) {
 			radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);

src/gallium/drivers/radeonsi/si_state_shaders.c

@@ -398,6 +398,7 @@ static INLINE void si_shader_selector_key(struct pipe_context *ctx,
 static int si_shader_select(struct pipe_context *ctx,
 			    struct si_shader_selector *sel)
 {
+	struct si_context *sctx = (struct si_context *)ctx;
 	union si_shader_key key;
 	struct si_shader * shader = NULL;
 	int r;
@@ -437,7 +438,8 @@ static int si_shader_select(struct pipe_context *ctx,
 
 		shader->next_variant = sel->current;
 		sel->current = shader;
-		r = si_shader_create((struct si_screen*)ctx->screen, shader);
+		r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
+				     shader);
 		if (unlikely(r)) {
 			R600_ERR("Failed to build shader variant (type=%u) %d\n",
 				 sel->type, r);
@@ -661,9 +663,11 @@ bcolor:
 			}
 		}
 
-		if (j == vsinfo->num_outputs) {
+		if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
-			/* No corresponding output found, load defaults into input */
+			/* No corresponding output found, load defaults into input.
-			tmp |= S_028644_OFFSET(0x20);
+			 * Don't set any other bits.
+			 * (FLAT_SHADE=1 completely changes behavior) */
+			tmp = S_028644_OFFSET(0x20);
 		}
 
 		si_pm4_set_reg(pm4,

src/gallium/state_trackers/clover/core/kernel.hpp

@@ -175,7 +175,7 @@ namespace clover {
          virtual void unbind(exec_context &ctx);
 
       private:
-         size_t _storage;
+         size_t _storage = 0;
       };
 
       class constant_argument : public argument {

src/gallium/state_trackers/clover/core/program.cpp

@@ -90,6 +90,8 @@ cl_build_status
 program::build_status(const device &dev) const {
    if (_binaries.count(&dev))
       return CL_BUILD_SUCCESS;
+   else if (_logs.count(&dev))
+      return CL_BUILD_ERROR;
    else
       return CL_BUILD_NONE;
 }

src/gallium/state_trackers/egl/Makefile.sources

@@ -52,6 +52,5 @@ x11_FILES := \
 	x11/native_ximage.c
 
 x11_drm_FILES := \
-	x11/dri2.c \
 	x11/x11_screen.c \
 	x11/x11_screen.h

src/gallium/state_trackers/egl/SConscript

@@ -39,7 +39,8 @@ else:
             '#/src/mapi',
         ])
         sources.append(env.ParseSourceList('Makefile.sources', 'x11_FILES'))
-        if env['drm']:
+        if env['drm'] and False:
+            # XXX: Disabled as we're don't generate the x11/dri2.c symlink at buildtime.
             env.Append(CPPDEFINES = ['GLX_DIRECT_RENDERING'])
             sources.append(env.ParseSourceList('Makefile.sources', 'x11_drm_FILES'))
     if env['drm'] and False:

src/gallium/state_trackers/egl/x11/dri2.c

@@ -1 +0,0 @@
-../../../../glx/dri2.c

src/gallium/state_trackers/omx/vid_dec_h264.c

@@ -706,6 +706,11 @@ static void slice_header(vid_dec_PrivateType *priv, struct vl_rbsp *rbsp,
       if (pic_order_cnt_lsb != priv->codec_data.h264.pic_order_cnt_lsb)
          vid_dec_h264_EndFrame(priv);
 
+      if (IdrPicFlag) {
+         priv->codec_data.h264.pic_order_cnt_msb = 0;
+         priv->codec_data.h264.pic_order_cnt_lsb = 0;
+      }
+
       if ((pic_order_cnt_lsb < priv->codec_data.h264.pic_order_cnt_lsb) &&
           (priv->codec_data.h264.pic_order_cnt_lsb - pic_order_cnt_lsb) >= (max_pic_order_cnt_lsb / 2))
          pic_order_cnt_msb = priv->codec_data.h264.pic_order_cnt_msb + max_pic_order_cnt_lsb;

src/gallium/targets/dri/Makefile.am

@@ -44,7 +44,7 @@ gallium_dri_la_LIBADD = \
 	$(top_builddir)/src/mesa/drivers/dri/common/libdricommon.la \
 	$(top_builddir)/src/mesa/drivers/dri/common/libmegadriver_stub.la \
 	$(top_builddir)/src/gallium/state_trackers/dri/libdri.la \
-	$(top_builddir)/src/gallium/auxiliary/libgalliumvl_stub.la \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvl.la \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/gallium/drivers/galahad/libgalahad.la \
 	$(top_builddir)/src/gallium/drivers/noop/libnoop.la \

src/gallium/targets/omx/Makefile.am

@@ -24,6 +24,7 @@ endif # HAVE_LD_VERSION_SCRIPT
 
 libomx_mesa_la_LIBADD = \
 	$(top_builddir)/src/gallium/state_trackers/omx/libomxtracker.la \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvlwinsys.la \
 	$(top_builddir)/src/gallium/auxiliary/libgalliumvl.la \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/util/libmesautil.la \

src/gallium/targets/pipe-loader/Makefile.am

@@ -46,6 +46,11 @@ PIPE_LIBS += \
 	$(top_builddir)/src/gallium/auxiliary/libgalliumvl_stub.la
 endif
 
+if NEED_GALLIUM_VL_WINSYS
+PIPE_LIBS+= \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvlwinsys.la
+endif
+
 PIPE_LIBS += \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/util/libmesautil.la \

src/gallium/targets/va/Makefile.am

@@ -25,6 +25,7 @@ endif # HAVE_LD_VERSION_SCRIPT
 # NOTE: gallium_drv_video does not use(link against) libva
 gallium_drv_video_la_LIBADD = \
 	$(top_builddir)/src/gallium/state_trackers/va/libvatracker.la \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvlwinsys.la \
 	$(top_builddir)/src/gallium/auxiliary/libgalliumvl.la \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/util/libmesautil.la \

src/gallium/targets/vdpau/Makefile.am

@@ -30,6 +30,7 @@ endif # HAVE_LD_DYNAMIC_LIST
 # NOTE: libvdpau_gallium does not use(link against) libvdpau
 libvdpau_gallium_la_LIBADD = \
 	$(top_builddir)/src/gallium/state_trackers/vdpau/libvdpautracker.la \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvlwinsys.la \
 	$(top_builddir)/src/gallium/auxiliary/libgalliumvl.la \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/util/libmesautil.la \

src/gallium/targets/xvmc/Makefile.am

@@ -24,6 +24,7 @@ endif # HAVE_LD_VERSION_SCRIPT
 
 libXvMCgallium_la_LIBADD = \
 	$(top_builddir)/src/gallium/state_trackers/xvmc/libxvmctracker.la \
+	$(top_builddir)/src/gallium/auxiliary/libgalliumvlwinsys.la \
 	$(top_builddir)/src/gallium/auxiliary/libgalliumvl.la \
 	$(top_builddir)/src/gallium/auxiliary/libgallium.la \
 	$(top_builddir)/src/util/libmesautil.la \