763 Commits

Author SHA1 Message Date
Rob Clark
575259eb26 freedreno: Fix tile-per-pipe debug overrides
Fixes: 0f3c12c0ab ("freedreno: add env var to override tiles-per-pipe")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31857>
(cherry picked from commit 42446052d4)
2024-11-02 18:41:25 +01:00
Patrick Lerda
782225e1da r600: fix sfn_nir_legalize_image_load_store cubearray behavior
This change fixes the calculation of the number of cubemap
images which requires a 6x multiplier.

This commit is inspired from nir_lower_robust_access and fixes
at least the following tests on cayman:
spec/arb_shader_image_load_store/layer/imagecubearray/layered binding test: fail pass
spec/arb_shader_image_load_store/max-size/imagecubearray max size test/8x8x2046x1: fail pass

Fixes: 27f5157777 ("r600/sfn: Add lowering pass to legalize image access")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31626>
(cherry picked from commit 5c63d7a916)
2024-11-02 18:17:23 +01:00
Mike Blumenkrantz
2db348fdb0 zink: stop leaking precompiled generated tcs
this may have been created during precompile when using shader objects

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27705>
(cherry picked from commit 01608a4067)
2024-11-02 18:17:22 +01:00
Samuel Pitoiset
092a85a7c2 radv: add missing L2 non-coherent image case for mipmaps with DCC/HTILE on GFX11
According to PAL, an image with DCC/HTILE and mipmaps isn't coherent
with L2 when the mip level is in the metadata mip-tail region.

This fix isn't super optimal because the driver should rely on the
subresource range to determine if the mip level is in the mip-tail,
but it's easier to backport. Upcoming commits will optimize that.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11939
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31920>
(cherry picked from commit b23cc8c1d3)
2024-11-02 18:17:21 +01:00
David Rosca
85cfa40dcc radeonsi/vcn: Enable VCN4 AV1 encode WA
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31889>
(cherry picked from commit c9ade8c3b5)
2024-11-02 18:17:21 +01:00
Paulo Zanoni
904c9d6464 brw: add a NOP in between WHILE instructions on LNL
This is a workaround that is still in progress, see HSD 22020521218.
If we don't have these NOPs we may see rendering corruption or even
GPU hangs.

While we still don't fully understand the issue from the hardware
point of view, let's have this workaround so we can pass CTS and move
things forward. If we need to change this later, we can. Besides, the
impact is minimal. Shaderdb/fossilize report no changes for this
patch.

On our Blackops trace, the lack of this patch causes corruption in fog
rendering (rectangles where fog was supposed to be shown don't show
the fog).

On dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters, without
this patch we get a GPU hang.

Backport-to: 24.2
Testcase: dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11813
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31331>
(cherry picked from commit 5ca883505e)
2024-11-02 18:17:19 +01:00
Lionel Landwerlin
6531617cad anv: avoid L3 fabric flush in pipeline barriers
This bit is not needed for barriers and appears to trigger a
performance regression. So leave it for just for AUX-TT
flushing/invalidation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e3814dee1a ("anv: add plumbing/support for L3 fabric flush")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12090
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31915>
(cherry picked from commit cb224370b6)
2024-11-02 18:17:18 +01:00
Rob Clark
d480ca55aa util/primconvert: Avoid OoB with improbable draws
Detect when the temporary index buffer cannot be generated due to too
large primitive count, and simply drop the draw on the floor.

Fixes a webgl reachable asan/crash.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12092
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31914>
(cherry picked from commit 98ff271c5a)
2024-11-02 18:17:17 +01:00
Timur Kristóf
9d0da8765a radv: Flush L2 cache for non-L2-coherent images in EndCommandBuffer.
This fixes a CTS hang on Hawaii.

We previously only did a CB/DB flush,
but that doesn't include a L2 cache flush.
Also fix the comment that said this is for GFX9+.

Fixes: 7c62f6fa01
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31906>
(cherry picked from commit 96b95c8427)
2024-11-02 18:17:16 +01:00
Connor Abbott
f583d6f7ba ir3: Fix detection of nontrivial continues
We may still need to insert a continue block even if there is only one
backedge, in a situation like:

for (...) {
   if (...) continue;
   foo();
   break;
}

We want foo() to be executed before reconverging. This is important for
the BVH encoding kernel, which launches an invocation for each node in
the tree and does a preorder traversal:

while (true) {
   if (!ready[node]) continue;
   encode();
   for (child node)
      ready[child] = true;
   break;
}

For the first few nodes, which will be in the same wave, we need
encode() for the root node to be called first, then its children spin
until ready, then the children call encode(), and so on. This can only
work if the children that aren't ready yet are parked while the parent
executes encode(), which requires the continue block.

This is also required because divergence analysis will assume that
uniform values written before the continue are still uniform after it,
which isn't the case now and causes an RA validation failure with Godot.

Fixes: 0fa93fb662 ("ir3: Fix convergence behavior for loops with continues")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31905>
(cherry picked from commit d3533716f9)
2024-11-02 18:17:15 +01:00
Eric Engestrom
e33b700954 .pick_status.json: Update to ab1479ae6a 2024-11-02 11:26:20 +01:00
Alyssa Rosenzweig
2e61c87e90 asahi: fix no16 flag
regressed when shuffling code for hk.

Fixes: 3cb8c1de81 ("asahi: get debug in common")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31908>
(cherry picked from commit 773dd89fde)
2024-10-30 18:56:40 +01:00
Samuel Pitoiset
274f429664 radv: fix wrong index in radv_skip_graphics_pipeline_compile()
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12089
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31901>
(cherry picked from commit fc0545e6a7)
2024-10-30 18:56:40 +01:00
Lu Yao
4da954852c ac/radeonsi: compute htile for tile mode RADEON_SURF_MODE_1D on GFX6-8
Computing 'htile_size/meta_size' is allowed for RADEON_SURF_MODE_1D when
RADEON_SURF_TC_COMPATIBLE_HTILE isn't set.
Lacking of computing causes performance degradation in some scenarios.

Fixes: d4d9ec55c5 ("radeonsi: implement TC-compatible HTILE")
Signed-off-by: Lu Yao <yaolu@kylinos.cn>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31617>
(cherry picked from commit 0442a6c292)
2024-10-30 18:56:40 +01:00
YaoBing Xiao
859bf9a4f2 vulkan/x11: use xcb_connection_has_error to check for failue
xcb_connectxx() always returns a non-NULL pointer to a
xcb_connection_t, even on failure.

cc: mesa-stable

Signed-off-by: YaoBing Xiao <xiaoyaobing@uniontech.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31812>
(cherry picked from commit b63dfcc172)
2024-10-30 18:56:40 +01:00
Eric Engestrom
056e7c7909 .pick_status.json: Update to c245609b64 2024-10-30 17:20:10 +01:00
Daniel Schürmann
03aadd157d aco: Respect addressible SGPR limit in VS prologs
On Tonga, the effective SGPR limit is 96, including VCC.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31859>
(cherry picked from commit 10958d04d5)
2024-10-28 16:20:12 +01:00
Samuel Pitoiset
6a593de60c radv: fix considering NGG culling for depth-only rendering
When the FS is unknown, this can happen with fast-link GPL or unlinked
ESO, rely on the number of VS/TES outputs which should be a good
approximation of the number of PS inputs.

This fixes a (huge?) performance regression from May 2023 because
for depth-only rendering, the FS is NULL and NGG culling wasn't
considered at all.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31830>
(cherry picked from commit 8e4d1965bd)
2024-10-28 16:20:11 +01:00
Job Noorman
c99c1ba27b ir3: fix physical edges of predicated branches
The algorithm for adding extra physical edges works by finding edges
that jump over reconvergence points. Since predicated branches don't
introduce reconvergence points, we wouldn't add a physical edge from the
true block to the false block. However, this physical edge is still
needed as control flow does fall though here. This patch fixes this by
manually adding the physical edge so that we don't need to insert a
reconvergence point for it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 39088571f0 ("ir3: add support for predication")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31733>
(cherry picked from commit 19c560da04)
2024-10-28 16:20:10 +01:00
Rob Clark
742e2ddb4b freedreno/ir3: Do not propagate away a widening move
A narrowing move from const is just emulated CONSTANT_DEMOTION_ENABLE so
we can permit it.  But not the inverse.

Cc: mesa-stable
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
(cherry picked from commit 63a5803433)
2024-10-28 16:20:09 +01:00
Ian Romanick
f0cb1eb414 brw/copy: Don't remove instructions w/ conditional modifier
Fixes: 9e750f00c3 ("intel/brw: Make opt_copy_propagation_defs clean up its own trash")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
(cherry picked from commit 8329c04521)
2024-10-28 16:20:08 +01:00
Dmitry Osipenko
ffbb9de588 util/mesa-db: Fix crash on compacting empty DB
Fix mesa_db_compact() segfaulting if compacted DB is empty. This crash
happens on writing cache entry that is bigger than DB's size limit and
when DB is empty, which can be triggered by setting DB size to a small
value.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 5ec424c6be)
2024-10-28 16:20:07 +01:00
Dmitry Osipenko
1421945edd util/mesa-db: Open DB files during access time
Open DB files when DB is accessed and close them afterwards to reduce
number of FDs used by multi-part DB cache.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 7b40d32187)
2024-10-28 16:20:06 +01:00
Dmitry Osipenko
64bc227b49 util/mesa-db-multipart: Open one cache part at a time
Open one cache DB part at a time for a multi-part cache to reduce number
of FDs used by the cache. Previously multi-part DB cache instance was
consuming 100 FDs, now it's 2 and cache files are opened when cache
is read or written instead of opening them at the init time.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 2a9378a0f9)
2024-10-28 16:17:57 +01:00
Dmitry Osipenko
823397fe55 util/mesa-db: Fix missing O_CLOEXEC
Use O_CLOEXEC flag for opened cache DB files to not leak cache FDs when
process forks.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 6a2f5cb556)
2024-10-28 16:17:57 +01:00
Michel Dänzer
e7dc5d6466 util/mesa-db: Make mesa_db_lock robust against signals
flock may be interrupted by a signal, in which case it returns with
EINTR error. In this case we need to retry until it returns success
or another error.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 13c44abaac)
2024-10-28 16:17:56 +01:00
Rob Clark
c2cf1cc556 nir/lower_amul: Fix ASAN error
We shouldn't assume the bindings are sparse when we allocate an array
indexed on the binding.  See, for example:

  dEQP-GLES31.functional.program_interface_query.buffer_variable.random.55

Fixes: 2e833b16bc ("nir/lower_amul: Use num_ubos/ssbos instead of recomputing it.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
(cherry picked from commit 7f63fa34da)
2024-10-28 16:17:55 +01:00
Rob Clark
ed61c273e6 freedreno/ir3: Create UBO variables for driver-UBOs
Some nir passes, like lower_amul, expect to have varibles declared for
things that are accessed via load_ubo().

Fixes: 76e417ca59 ("turnip,ir3/a750: Implement consts loading via preamble")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
(cherry picked from commit e548f90edb)
2024-10-28 16:17:54 +01:00
Jocelyn Falempe
a6f534107a gbm/dri: Fix color format for big endian.
Using wayland on s390x has all the colors wrong.
Mesa reports using GBM_FORMAT_XRGB8888 but inside the buffer, the
colors are in GBM_FORMAT_BGRX8888 order.
This patch fixes it for common formats, and also introduced BGRX8888
which is the default on big endian.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit b24d4f0c86)
2024-10-28 16:16:33 +01:00
Jocelyn Falempe
325ee5941d gbm/dri: Use PIPE_FORMAT_* instead of using __DRI_IMAGE_*
__DRI_IMAGE formats are not well defined for big endian.
This patch has no functionnal change and prepare the work to better support
big endian.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit 3814dee11a)
2024-10-28 16:16:02 +01:00
Jocelyn Falempe
10e69d7843 loader: Fix typo in __DRI_IMAGE_FORMAT_XBGR16161616 definition
The X and A format are inverted by mistake.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit c6d7ab7c1f)
2024-10-28 16:13:48 +01:00
Rhys Perry
e311640911 nir/algebraic: fix shfr optimization with zero src2
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 08903bbe89 ("nir: add mqsad_4x8, shfr and nir_opt_mqsad")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31808>
(cherry picked from commit 8efc765a3d)
2024-10-28 16:13:47 +01:00
Rhys Perry
5ad7003957 nir: fix shfr constant folding with zero src2
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 08903bbe89 ("nir: add mqsad_4x8, shfr and nir_opt_mqsad")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31808>
(cherry picked from commit b2abd3bdba)
2024-10-28 16:13:46 +01:00
Samuel Pitoiset
1701837c16 radv: fix emitting NGG culling state for ESO
It's possible to enable NGG culling with ESO if shaders are linked, or
if the VS doesn't need a prolog or if TES is used. This wasn't
supposed to be enabled but I think it worked just by luck because the
user SGPR value was probably zero and NGGC was disabled at draw time.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31829>
(cherry picked from commit 62efebfd70)
2024-10-28 16:13:45 +01:00
Patrick Lerda
0837800452 r600: fix spec ext_packed_depth_stencil getteximage
This very test was working until the commit 4da147a02b
("mesa: remove fallback for GL_DEPTH_STENCIL"). Indeed this
commit lets the driver handles this path and this was
failing on evergreen r600.

The test was processed through r600_blit() which loads the
fragment shader util_make_fs_blit_zs(). This fragment shader
loads two textures the stencil and depth. The texture depth
was processed properly but the other texture was generating
incorrect values. This issue, which seems to be related to
the hardware configuration, disappears when the underlying
surface is allocated using a width multiple of 32.

This change was tested on cayman and palm with the normal test:
"piglit/bin/ext_packed_depth_stencil-getteximage -auto -fb" and
the test was modified to test all the relevant width and height
values. The gpu rv770 was not affected by this issue. Here is
the result:
spec/ext_packed_depth_stencil/getteximage: fail pass

Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31757>
(cherry picked from commit d19e2597ce)
2024-10-28 16:13:45 +01:00
Georg Lehmann
b7f428a3c0 radv: don't use v_mqsad_u32_u8 on gfx7
According to tests on hawaii, v_mqsad_u32_u8 always uses saturating accumulation
while v_msad_u8 truncates. GFX8+ can control this with the VOP3 clamp bit,
on older hardware that's not supported.

We want truncation for the NIR opcode.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12062
Fixes: c3c138b10f ("radv: optimize msad_4x8 to mqsad_4x8")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31809>
(cherry picked from commit 54fa55a3f7)
2024-10-28 16:13:44 +01:00
Connor Abbott
e94468c7e6 tu: Don't invalidate CS state for 3D blits
We don't dirty the CS state, so if a 3D blit comes between binding a
compute pipeline and executing a dispatch then we won't re-emit the
pipeline and invalidating CS state causes immediates emitted via
CP_LOAD_STATE to disappear. Fixes
dEQP-VK.binding_model.descriptor_buffer.ycbcr_sampler.compute_comp.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
(cherry picked from commit 048afdd438)
2024-10-28 16:13:43 +01:00
Connor Abbott
d48aac9e19 freedreno: Add compute constlen quirk for X1-85
This GPU seems to have half the compute constlen of other a7xx GPUs,
because there are sporadic hangs in dEQP-VK.robustness.robustness2.* and
other tests unless we limit the constlen. This does *not* happen on
SM8550-HDK, so it does seem to be specific to the GPU in x1e laptops.

Fixes: b0d22461b9 ("freedreno: Enable the X1-85")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
(cherry picked from commit 3c8190e8b2)
2024-10-28 16:08:48 +01:00
Connor Abbott
655cdbd649 ir3: Increase compute const size on a7xx
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30995>
(cherry picked from commit 5879eaac18)
2024-10-28 16:08:21 +01:00
Valentine Burley
6293074106 freedreno/devices: Unify magic_regs for A740 and A32
The only difference was RB_UNKNOWN_8E01 being set to 0x0 or 0x00000000.
Their raw_magic_regs however are different.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31328>
(cherry picked from commit dde6acceb5)
2024-10-28 16:08:21 +01:00
Yao Zi
c282a40403 panvk: Link with --build-id explicitly
panvk provides driver UUID generated from build id of the dynamic
library, but ld_args_build_id isn't used during linking. This leads to
broken drivers when building mesa with a toolchain defaults to
--no-build-id. Let's specify the flag explicitly.

Fixes: 8ea2931ed1 ("panvk: Generate proper device and driver UUIDs")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31654>
(cherry picked from commit 5ffc5ba8ef)
2024-10-28 16:01:33 +01:00
Adam Jackson
09167a3e0b glx: Fix the GLX_EXT_swap_control_tear drawable attributes
GLX_SWAP_INTERVAL_EXT is always positive, GLX_LATE_SWAPS_TEAR_EXT is how
you tell whether the drawable is set to do it. This aligns us with the
spec and NVIDIA's GLX.

Closes: mesa/mesa#10193
Fixes: 5e9e457383 glx/dri3: Implement GLX_EXT_swap_control_tear
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31655>
(cherry picked from commit 858eb18952)
2024-10-28 16:01:33 +01:00
Danylo Piliaiev
4d166e1edb util/vma: Fix util_vma_heap_get_max_free_continuous_size calculation
It was based on misunderstanding of how holes are sorted, they are
sorted by address and not by size.

Fixes: df3ba95a24
("util/vma: Add function to get max continuous free size")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31722>
(cherry picked from commit 3209a97c5c)
2024-10-28 15:59:22 +01:00
Jordan Justen
34aff5d279 intel/dev: Use hwconfig for urb min/max entry values
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit a4c5bfd34c)
2024-10-28 15:59:16 +01:00
Jordan Justen
3da8b46eba intel/dev: Allow specifying a version when to always use hwconfig
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit 7b86da0ccd)
2024-10-28 15:59:15 +01:00
Jordan Justen
f878028d18 intel/dev: Simplify DEVINFO_HWCONFIG_KV by adding should_apply_hwconfig_item()
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit a71702d342)
2024-10-28 15:59:14 +01:00
Jordan Justen
e25c4095e5 intel/dev: Rework DEVINFO_HWCONFIG; add DEVINFO_HWCONFIG_KV macro
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit b4df9658f5)
2024-10-28 15:59:13 +01:00
Samuel Pitoiset
fc21133c03 radv: fix initializing the HTILE buffer on transfer queue
When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
(cherry picked from commit be81c8b8db)
2024-10-28 15:59:12 +01:00
Sviatoslav Peleshko
308c6b9069 intel/brw/gfx9: Implement WaClearArfDependenciesBeforeEot
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11928
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31746>
(cherry picked from commit 2a4efe21c5)
2024-10-28 15:58:59 +01:00
Frank Binns
0c158e6741 pvr: ensure stencil clear value fits TA_STATE_ISPA.sref field
If the stencil clear value was larger than the maximum supported by the hardware
(255) then it would end up corrupting other fields in TA_STATE_ISPA. The Vulkan
1.0.266 spec says for VkClearDepthStencilValue:

  "stencil is the clear value for the stencil aspect of the depth/stencil
   attachment. It is a 32-bit integer value which is converted to the
   attachment’s format by taking the appropriate number of LSBs."

As such, mask the clear value when packing TA_STATE_ISPA.

Fixes a number of GLES tests, including:
  dEQP-GLES2.functional.depth_stencil_clear.*stencil_scissored*
  dEQP-GLES2.functional.fragment_ops.stencil.*
  dEQP-GLES3.functional.depth_stencil_clear.*stencil_scissored*
  dEQP-GLES3.functional.fragment_ops.stencil.*

Fixes: 821c6b9342 ("pvr: Implement depth/stencil/depth+stencil attachment...")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 1612255de6)
2024-10-28 15:49:42 +01:00