Commit Graph

204305 Commits

Author SHA1 Message Date
Samuel Pitoiset
a327bc677a radv: configure COVERAGE_TO_SHADER_SELECT only if conservative rast is enabled
When conservative rasterization isn't enabled, FullyCoveredEXT is
expected to return 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
2025-04-08 08:42:17 +00:00
Samuel Pitoiset
6e9782b39c radv: emit conservative raster mode as part of the MSAA state
From the hw perspective, it's more like a MSAA state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
2025-04-08 08:42:17 +00:00
Samuel Pitoiset
ed744b5c68 radv: move emitting raster and depth/stencil state slightly earlier
To avoid a redundant chekc if no dynamic states are dirtied.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
2025-04-08 08:42:17 +00:00
Lars-Ivar Hesselberg Simonsen
37595775a0 panvk: Add barrier for interleaved ZS copy cmds
When executing CopyBufferToImage or CopyImage with multiple regions of
both depth and stencil aspects targeting an interleaved depth stencil
image, we must split the regions into one copy-command for each aspect
and add a barrier between them to avoid a write-after-write race.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 5067921349 ("panvk: Switch to vk_meta")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34384>
2025-04-08 08:08:35 +00:00
Samuel Pitoiset
ef9e7cb3f5 radv: add before/after draw functions for DGC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
2025-04-08 08:15:05 +02:00
Samuel Pitoiset
d2da54e6f3 radv: apply the workaround for buggy HiZ/HiS on GFX12 for DGC
Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
2025-04-08 08:15:04 +02:00
Samuel Pitoiset
6388db03c8 radv: add a workaround for buggy HiZ/HiS on GFX12
HiZ/HiS is buggy and can cause random GPU hangs when stencil is enabled.
There are basically two alternatives but RADV follows RadeonSI and emit
a dummy RELEASE_MEM packet after every draw which should workaround the
issue and maintain performance.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12944
Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
2025-04-08 08:09:13 +02:00
Samuel Pitoiset
11b6d2ba60 radv: determine if HiZ/HiS is enabled earlier on GFX12
To lower CPU overhead of the hardware workaround.

Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
2025-04-08 08:03:11 +02:00
Faith Ekstrand
2ff22de626 nak: Use suld.b on Kepler if we have a format
This works on all GPU generations but we don't actually need it since we
have formatted image loads on everything Maxwell+.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34336>
2025-04-08 04:06:45 +00:00
Faith Ekstrand
6aa2c152b8 nak,nir: Add an image_load_raw_nv intrinsic
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34336>
2025-04-08 04:06:45 +00:00
Faith Ekstrand
e7843720c2 nak: Add support for suld/st.b
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34336>
2025-04-08 04:06:45 +00:00
Faith Ekstrand
3d9185f17e nak: Add a ChannelMask type
We use this for tex and image ops instead of a u8.  This lets us assert
some variants up-front as well as pretty print them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34336>
2025-04-08 04:06:45 +00:00
Lars-Ivar Hesselberg Simonsen
c2570055d5 vulkan/wsi/wayland: Avoid duplicate colorspace entry
The colorspace SRGB_NONLINEAR could be added twice when querying
available formats, leading to duplicate entries and VulkanCTS WSI test
failures.

Fixes: 789507c99c ("vulkan/wsi: implement the Wayland color management protocol")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34410>
2025-04-07 23:55:25 +00:00
Faith Ekstrand
436f175187 intel/compiler: Use nir_split_conversions()
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34266>
2025-04-07 17:45:21 -05:00
Caio Oliveira
bf9ad36f2d brw: Properly handle cooperative matrices created with constants
Expand constant sources to cover the region read by DPAS, and also
use NULL register as accumulator when possible.

Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34373>
2025-04-07 14:27:43 -07:00
Mel Henning
16e3e0d93b nvk: Support blackwell in max_warps_per_mp_for_sm
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34161>
2025-04-07 20:28:48 +00:00
Mel Henning
f2aac0f96a nvk: SET_PS_{REGISTER,WARP}_WATERMARKS
Brings Baldur's Gate 3 from 32 to 35 fps on the character creator. (+9%)
Brings Horizon Zero Dawn from 7098 to 7872 points in its bencmark. (+11%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34161>
2025-04-07 20:28:48 +00:00
Marek Olšák
39d2a1e773 radeonsi: add a VOP3P swizzle requirement for 16-bit packed math
Otherwise ACO fails an assertion.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:23 +00:00
Marek Olšák
15b0198d7f radeonsi: lower load/store bit sizes before load/store vectorization
to match RADV and also to reduce code size by -2.33% in 178 affected shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:23 +00:00
Marek Olšák
5e5b04cb27 radeonsi/ci: don't run GTF tests (they have been removed from glcts)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
5039feb192 radeonsi/ci: update gfx11 failures
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
a4b71e5b2d radeonsi: expose 16-bit NIR types for ALU, MEM, and LDS (no inputs/outputs)
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
58f3d6fa20 radeonsi: always use ACO callbacks to scalarize/vectorize 16-bit ALU
This fixes 16-bit ALU with LLVM.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
a82705911e radeonsi: work around a primitive restart bug on gfx10-10.3
Using the GE instead of the VGT register has no effect because it's
the same value. SQ_NON_EVENT is the fix.

Discovered by Samuel Pitoiset.

Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
e4a30b7241 ac/surface: remove 64K_2D modifier with 64B max compressed blocks for gfx12
It has no use and is slower.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
27d5be13c6 ac/nir/cull: always do frustum culling, skip only small prim culling
Only small prim culling uses the viewport state, so only that must be
disabled when there are multiple viewports.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
0f97dc707d ac/nir/cull: rename skip_viewport_culling -> skip_viewport_state_culling
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
bc27ad8064 ac: define physical VGPRs for fake hw overrides
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Alyssa Rosenzweig
e5097a7c9d glsl_to_nir: upcast array indices
array indices need to match the pointer size, otherwise we fail NIR assertions.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6075
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Marek Olšák
1d5c42528b nir/opt_algebraic: lower 16-bit imul_high & umul_high
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
2025-04-07 19:44:22 +00:00
Mike Blumenkrantz
b14c8128bf tu: check for valid descriptor set when binding descriptors
these pointers can be null, and they are checked as null in
pipeline layout creation, but here if the pointer is null it will crash

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34412>
2025-04-07 18:49:10 +00:00
Sergi Blanch Torne
3ef0eac21c Uprev Piglit to ebdf60e0d4b0dc23e79373cb923fdee023eb3b2b
68658566da...ebdf60e0d4

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34378>
2025-04-07 18:16:00 +00:00
Collabora's Gfx CI Team
fcf19bf335 Uprev ANGLE to 3818d37d5e94317f01810053b8f28c1f1e8b98e6
1b34d2a18a...3818d37d5e

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34378>
2025-04-07 18:16:00 +00:00
Ian Romanick
f33faa4648 brw/nir: Allow b2f(not(X)) optimization on Gfx12.5+
Since there are no type conversions, no restrictions are violated.

No shader-db or fossil-db changes on any Gfx12 or older Intel
platforms.

shader-db:

Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown)
total instructions in shared programs: 16956077 -> 16944933 (-0.07%)
instructions in affected programs: 1957573 -> 1946429 (-0.57%)
helped: 4629 / HURT: 35

total cycles in shared programs: 915668518 -> 915684808 (<.01%)
cycles in affected programs: 341925598 -> 341941888 (<.01%)
helped: 3040 / HURT: 1305
helped stats (abs) min: 2 max: 23034 x̄: 205.36 x̃: 16
helped stats (rel) min: <.01% max: 41.21% x̄: 1.28% x̃: 0.48%
HURT stats (abs)   min: 2 max: 68820 x̄: 490.88 x̃: 22
HURT stats (rel)   min: <.01% max: 103.69% x̄: 2.29% x̃: 0.37%
95% mean confidence interval for cycles value: -50.28 57.78
95% mean confidence interval for cycles %-change: -0.35% -0.07%
Inconclusive result (value mean confidence interval includes 0).

LOST:   40
GAINED: 42

fossil-db:

Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown)
Totals:
Instrs: 209828027 -> 209790349 (-0.02%); split: -0.03%, +0.01%
Cycle count: 30504938008 -> 30514045408 (+0.03%); split: -0.06%, +0.09%
Spill count: 512182 -> 512168 (-0.00%)
Fill count: 623432 -> 623426 (-0.00%); split: -0.00%, +0.00%
Max live registers: 65465029 -> 65464959 (-0.00%)

Totals from 57895 (8.19% of 706589) affected shaders:
Instrs: 50144907 -> 50107229 (-0.08%); split: -0.11%, +0.03%
Cycle count: 7549692606 -> 7558800006 (+0.12%); split: -0.25%, +0.37%
Spill count: 58834 -> 58820 (-0.02%)
Fill count: 102324 -> 102318 (-0.01%); split: -0.01%, +0.01%
Max live registers: 9129045 -> 9128975 (-0.00%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33931>
2025-04-07 17:42:05 +00:00
Ian Romanick
853ead2073 brw/nir: Optimize b2f(not(X)) using logical operations instead of arithmetic
Funny story... this is how regular b2f was implemented before Curro
implmented the `MOV dst:F -src:D` method 9 years ago (see
3ee2daf23d).

Eliminating the type conversion in the arithmetic operation enables the
next commit.

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33931>
2025-04-07 17:42:05 +00:00
Ian Romanick
3d23496fd9 brw/copy: Copy prop -X into Y&1
This commit prevents code quality regressions in the next
commit. Without this, some fragment shaders in Batman: Arkham Origins
have code like:

    shr(8)          g51<1>UW        g1.28<1,8,0>UB  0x76543210V
    ...
    and(8)          g52<1>UD        ~g51<8,8,1>UW   0x0001UW
    ...
    add(8)          g56<1>D         -g52<8,8,1>D    1D

transformed to

    shr(8)          g51<1>UW        g1.28<1,8,0>UB  0x76543210V
    ...
    and(8)          g52<1>UD        ~g51<8,8,1>UW   0x0001UW
    ...
    mov(8)          g56<1>D         -g52<8,8,1>D
    ...
    and(8)          g57<1>UD        ~g56<8,8,1>D    0x00000001UD

Propagating through the negation allows the added MOV to be deleted.

shader-db:

All Intel platforms had simlar results. (Lunar Lake shown)
total instructions in shared programs: 16968020 -> 16968019 (<.01%)
instructions in affected programs: 281 -> 280 (-0.36%)
helped: 1 / HURT: 0

total cycles in shared programs: 914598850 -> 914598832 (<.01%)
cycles in affected programs: 5398 -> 5380 (-0.33%)
helped: 1 / HURT: 0

A single Blender vertex shader was affected.

fossil-db:

Lunar Lake, Tiger Lake, Ice Lake, and Skylake had similar results. (Lunar Lake shown)
Totals:
Instrs: 209894650 -> 209894651 (+0.00%)
Cycle count: 30545958586 -> 30545952860 (-0.00%)

Totals from 2 (0.00% of 706657) affected shaders:
Instrs: 3582 -> 3583 (+0.03%)
Cycle count: 1875100 -> 1869374 (-0.31%)

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Subgroup size: 9906400 -> 9906416 (+0.00%)

Totals from 2 (0.00% of 805770) affected shaders:
Subgroup size: 16 -> 32 (+100.00%)

Two compute shaders in Hogwarts Legacy were affected.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33931>
2025-04-07 17:42:05 +00:00
Ian Romanick
e82464e6e0 brw/copy: Refactor source modifier type checking
This simplifies the next commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33931>
2025-04-07 17:42:05 +00:00
Ian Romanick
dee49f4206 brw/algebraic: Optimize derivative of convergent value
This is mostly defensive. If a convergent value ever ended up as a
source of a DDX or DDY, the eu_emit code will ignore the stride. This
will result in bad code being generated.

No shader-db or fossil-db changes on any Intel platform.

v2: DDX and DDY will always be float, but brw_imm_for_type only works
with integer types.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Ken
Fixes: d5d7ae22ae ("brw/nir: Fix up handling of sources that might be convergent vectors")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33007>
2025-04-07 17:16:34 +00:00
Ian Romanick
5656682344 brw/nir: Eliminate default parameter to get_nir_src
The vast majority of the callers want channel = 0. During the
development process, using this default parameter value saved a lot of
pain in rebasing. However, it seems to be more trouble than it's worth.

Issue #12464 occurred because LNL was merged while this code was in
review. As a result, one caller of get_nir_src that wanted channel = -1
was not inspected closely, and it got the default channel = 0 instead.

To prevent this happening in the future (with possible branches still
yet to be merged, for example), remove the default parameter. This will
force the inspection of any callers that don't have an explicit channel
parameter. Hopefully that will prevent more problems.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33007>
2025-04-07 17:16:34 +00:00
Ian Romanick
38b58e286f brw/nir: Fix source handling of nir_intrinsic_load_barycentric_at_offset
The source of nir_intrinsic_load_barycentric_at_offset is a vector, so
-1 should be passed to get_nir_src. This is also done for texture
sampling intrinsics.

I skimmed the other user of get_nir_src, and I believe they are
correct. This one was just missed as LNL support landed an many, many
rebases of the original MR occurred.

v2: Fix another get_nir_src call. Suggested by Lionel.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: d5d7ae22ae ("brw/nir: Fix up handling of sources that might be convergent vectors")
Closes: #12464
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33007>
2025-04-07 17:16:34 +00:00
Eric R. Smith
739da17f6e panfrost,lima: use index size in panfrost minmax_cache
Bifrost keeps a cache of information about buffers being
used as indices. Unfortunately, it was not keeping information
about the size of the indices (probably because this rarely
changes). If a program deliberately re-interprets the indices
as a different type (e.g. UNSIGNED_INT instead of UNSIGNED_SHORT)
then we will use incorrect values from the cache. This actually
showed up in a test program we were running.

Fix by saving the index size in the cache key.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34011>
2025-04-07 16:53:22 +00:00
Patrick Lerda
6fab29d37e r600: implement EXT_window_rectangles
This is a backport of 0ca8294ece ("radeonsi:
implement EXT_window_rectangles")

This change was tested and passes the piglit tests (20/20)
on rv770, palm and cayman.

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34295>
2025-04-07 16:31:21 +00:00
Ashley Smith
c1ce2dcc66 pan/bi: Enable ARB_shader_clock extension support
Introduces GCLK instruction to read the system timer/counter. Currently
only counter is supported.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34342>
2025-04-07 15:58:45 +00:00
Patrick Lerda
f0c0997277 r600: fix textures with swizzles limited to zero and one
This issue seems to be specific to textureGather() which could
fail when processing some surfaces. These surfaces are configured
with non-standard one and zero swizzles. The gpu doesn't support
this very specific setup with all the possible hardware formats.
This change selects a compatible configuration when this is
possible.

This change was tested on palm, barts and cayman. This change
fixes the 216 remaining arb_texture_gather tests:
spec/arb_texture_gather/texturegather/.*-zero-.*: fail pass
spec/arb_texture_gather/texturegather/.*-one-.*: fail pass
spec/arb_texture_gather/texturegatheroffset/.*-zero-.*: fail pass
spec/arb_texture_gather/texturegatheroffset/.*-one-.*: fail pass

Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34293>
2025-04-07 15:38:44 +00:00
Samuel Pitoiset
e3c3fa8b9a radv: add a fuction to emit the VRS surface on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00
Samuel Pitoiset
00354f0a74 radv: do not emit the VRS surface VA when it's not enabled
This shouldn't be necessary because VRS_SURFACE_ENABLE is the toggle
bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00
Samuel Pitoiset
9b11caee40 radv: stop emitting CB_FDCC_CONTROL to zero on GFX11-GFX11.5
It's already emitted by the CLEAR_STATE packet on these GPUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00
Samuel Pitoiset
17e5fd856f radv: split null framebuffer state emission for GFX12
For consistency with color/ds states emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00
Samuel Pitoiset
c608a601bf radv: split framebuffer depth/stencil state emission for GFX12
It's also really simpler on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00
Samuel Pitoiset
d5eb1f6833 radv: split framebuffer color state emission for GFX12
It's really simpler on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
2025-04-07 15:09:18 +00:00