Compare commits

...

6082 Commits

Author SHA1 Message Date
Eric Engestrom
7de17e2520 VERSION: bump to 20.1.0 release
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-05-27 23:47:01 +02:00
Eric Engestrom
10f7779c54 docs: Add release notes for 20.1.0
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-05-27 23:47:01 +02:00
Samuel Pitoiset
9b7290d15c radv: update the list of allowed Android extensions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 8c6350d2bb)
2020-05-27 21:54:17 +02:00
Samuel Pitoiset
54db67ecb8 radv: handle different Vulkan API versions correctly
Loosely based on ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 021270cb31)
2020-05-27 21:54:17 +02:00
Danylo Piliaiev
e81c43540c intel/fs: Work around dual-source blending hangs in combination with SIMD16
It was found that dual-source blending hangs with SIMD16 dispatch in some
specific but unknown situation. Which in the wild happen when rgba
anti-aliasing is enabled for fonts.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5037>
(cherry picked from commit 296c04d78c)
2020-05-27 21:54:17 +02:00
Erik Faye-Lund
d043d24654 zink: use general-layout when blitting to/from same resource
This avoids a validator warning when for instance generating mipmaps.

Fixes: d2bb63c8d4 ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5199>
(cherry picked from commit dd2bd68fa6)
2020-05-27 21:54:17 +02:00
Timothy Arceri
e5301cfeef glsl: fix slow linking of uniforms in the nir linker
Currently the nir linker resizes the amount of storage needed to hold
uniform information on the fly while linking. As shaders can contain
thousands of uniforms this can be very slow. For example some Godot
shaders can take 30 seconds to compile on some machines.

In this change we count the amount of storage needed before we start
processing the uniforms. This is what the GLSL IR linker does also.

Fixes: 95f555a93a ("st/glsl_to_nir: make use of nir linker for linking uniforms")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2996

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5137>
(cherry picked from commit f1acf492de)
2020-05-27 21:54:17 +02:00
Timothy Arceri
bcab0cc6d8 glsl: stop cascading errors if process_parameters() fails
Generally we do not completely stop compilation as soon as we see an error,
instead we continue on to attemp to find any futher errors.

This means we shouldn't be checking state->error to see if any error has
happened during the compilation process, doing so was causing
process_parameters() to fail on completely valid functions if there was
any error found in the shader previously. This then caused the valid
functions not to be found because the paramlist was considered empty,
resulting in the compiler spewing out misleading error messages.

Here we simply add the IR error value to the param list when we have
an issue with processing a parameter, this leads to much better error
messaging.

Fixes: 53e4159eaa ("glsl: stop processing function parameters if error happened")

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5205>
(cherry picked from commit f6214750eb)
2020-05-27 21:54:17 +02:00
Vinson Lee
f9c4314d35 freedreno: Add missing va_end.
Fix warning reported by Coverity Scan.

Missing varargs init or cleanup (VARARGS)
missing_va_end: va_end was not called for ap.

Fixes: a0ca1462f3 ("freedreno: add logging infrastructure")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5221>
(cherry picked from commit 755c040060)
2020-05-27 21:54:17 +02:00
Rob Clark
9b3aa87227 freedreno: clear last_fence after resource tracking
The resource tracking in the clear/draw_vbo/blit paths could itself
trigger a flush.  Which would update last_fence.  So we need to clear
last_fence *after* all the dependency tracking.

Fixes: ddb7fadaf8 ("freedreno: avoid no-op flushes by re-using last-fence")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2992
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5188>
(cherry picked from commit 8728c42031)
2020-05-27 21:54:17 +02:00
Rhys Perry
f2dd854bfe nir: fix lowering to scratch with boolean access
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 18ed82b084
   ('nir: Add a pass for selectively lowering variables to scratch space')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5214>
(cherry picked from commit 8e2009c448)
2020-05-27 21:54:17 +02:00
Gert Wollny
ca0e70927d r600: Fix duplicated subexpression in r600_asm.c
Fixes: 4422ce1b04
    r600: force new CF with TEX only if any texture value is written

Closes #3012

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5187>
(cherry picked from commit 901793d558)
2020-05-27 21:54:17 +02:00
Vinson Lee
2e817d95e6 r600/sfn: Use correct setter method.
Fix warning reported by Coverity Scan.

Useless call (USELESS_CALL)
side_effect_free: Calling v->pin_to_channel() is only useful for its
return value, which is ignored.

Fixes: 5d10e3ec60 ("r600/nir: Pin interpolation results to channel")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5197>
(cherry picked from commit 1241f8cb4c)
2020-05-27 21:54:17 +02:00
Bas Nieuwenhuizen
cf7dffbaae radv: Implement vkGetSwapchainGrallocUsage2ANDROID.
This was implemented in version 6 of the VK_ANDROID_native_buffer
extension and we only implement version 5. However, the Android
Vulkan loader only checks whether vkGetInstanceProcAddr for the
function is not NULL.

This all went wrong when we switched to the layer code from ANV.
Because the function may now be different per device, it adds fallback
functions that dispatch to the dispatch table. So if we didn't implement
the function we still returned a pointer to the dispatch function,
which made the Android Vulkan loader believe it was supported.

Dispatch functions:
d555794f30/src/amd/vulkan/radv_entrypoints_gen.py (L328)

Fixes: d555794f30 "radv: update entrypoints generation from ANV"
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2936
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5198>
(cherry picked from commit be784cc77b)
2020-05-27 21:54:17 +02:00
Bas Nieuwenhuizen
5dabdf3eef radv: Do not close fd -1 when NULL-winsys creation fails.
Fixes: cd6ec2b1ab "radv: implement a dummy winsys for creating devices without AMDGPU"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5181>
(cherry picked from commit a51ab5f956)
2020-05-27 21:54:17 +02:00
Bas Nieuwenhuizen
9f86183f50 radv: Handle failing to create .cache dir.
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5181>
(cherry picked from commit cd61f5234d)
2020-05-27 21:54:17 +02:00
Bas Nieuwenhuizen
167d4a5993 radv/winsys: Remove extra sizeof multiply.
The pointer is already uint64_t*, so the sizeof was too much ...

Fixes: eeff7e1154 "radv: Add userspace fence buffer per context."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5181>
(cherry picked from commit 906435fb0e)
2020-05-27 21:54:17 +02:00
Vinson Lee
f6412c24b3 r600/sfn: Initialize VertexStageExportForGS m_num_clip_dist member variable.
Fix warning reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_num_clip_dist is not
initialized in this constructor nor in any functions that it calls.

Fixes: f7df2c57a2 ("r600/sfn: extract class to handle the VS export to different stages")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5180>
(cherry picked from commit 73c0f60d8c)
2020-05-27 21:54:16 +02:00
Icecream95
57f400b013 panfrost: Fix background showing when using discard
This fixes problems in a number of games, including SuperTuxKart,
OpenMW and RVGL.

v2: Use MALI_READS_ZS | 0x20 instead of MALI_WRITES_Z to match with
the blob. Keep using 0x400 | 0x20 when depth is disabled.

Closes: #2620
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
(cherry picked from commit 0dd24b381c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5193>
2020-05-27 21:54:16 +02:00
Eric Engestrom
1fa0c121c8 tree-wide: fix deprecated GitLab URLs
They will stop working in the next GitLab release, so let's update them
ASAP to make sure things are propagated to everyone by then.

See:
https://about.gitlab.com/releases/2020/05/06/gitlab-com-13-0-breaking-changes/#removal-of-deprecated-project-paths

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5111>
(cherry picked from commit 444138d6d9)
2020-05-27 21:54:16 +02:00
Kristian H. Kristensen
0931bf60fd freedreno: Use the right amount of &'s
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5176>
(cherry picked from commit 5f365affc9)
2020-05-27 21:54:16 +02:00
Hanno Böck
cb5d60b7d9 Properly check mmap return value
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5150>
(cherry picked from commit be71e2fd08)
2020-05-27 21:54:16 +02:00
Jason Ekstrand
8cb8c7f0f1 nir/copy_prop_vars: Record progress in more places
Fixes: 96c32d7776 "nir/copy_prop_vars: handle load/store of vector..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
(cherry picked from commit f0e075ce6e)
2020-05-27 21:54:16 +02:00
Jason Ekstrand
cebdf2700f nir/opt_deref: Report progress if we remove a deref
Fixes: a1c688517d "nir/opt_deref: Properly optimize ptr_as_array..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
(cherry picked from commit db6d9cdf06)
2020-05-27 21:54:15 +02:00
Jason Ekstrand
f9ecf907e4 nir/lower_double_ops: Rework the if (progress) tree
Fixes: d7d35a9522 "nir/lower_doubles: Use the new NIR lowering..."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5170>
(cherry picked from commit 111b0a6699)
2020-05-27 21:54:15 +02:00
Danylo Piliaiev
c10e0616ed mesa: Fix double-lock of Shared->FrameBuffers and usage of wrong mutex
Fixes: 7534c536ca
Fixes: 8cfb3e4ee5
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3024
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5160>
(cherry picked from commit 4025583123)
2020-05-27 21:54:15 +02:00
Pierre-Eric Pelloux-Prayer
1a6c365774 amd/addrlib: fix forgotten char -> enum conversions
clang warning:
  result of comparison of constant 115 with expression of type
  'const enum Dim' is always false

Fixes: e3e704c7e7 ("amd/addrlib: Use enum instead of sparse chars to identify dimensions")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
(cherry picked from commit dddd91eef3)
2020-05-27 21:54:15 +02:00
Danylo Piliaiev
511d89f0ad meson: Disable GCC's dead store elimination for memory zeroing custom new
Some classes use custom new operator which zeroes memory, however gcc does
aggressive dead-store elimination which threats all writes to the memory
before the constructor as "dead stores".

For now we disable this optimization.

The new operators in question are declared via:
 DECLARE_RZALLOC_CXX_OPERATORS
 DECLARE_LINEAR_ZALLOC_CXX_OPERATORS

The issue was found with lto builds, however there is no guarantee that
it didn't happen with ordinary ones.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2977
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1358
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5104>
(cherry picked from commit 5500a2b7fc)
2020-05-27 21:54:15 +02:00
Dave Airlie
fc0124c711 llvmpipe: compute shaders work better with all the threads.
I got to benchmarking some vulkan compute benchmark and wondered
why my CPUs weren't being saturated, helps if you actually wake up
all the threads in the threadpool.

Fixes: 1b24e3ba75 (llvmpipe: add compute threadpool + mutex)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5138>
(cherry picked from commit 22554e1fbc)
2020-05-27 21:54:15 +02:00
Nataraj Deshpande
a6dc18e874 dri_util: Update internal_format to GL_RGB8 for MESA_FORMAT_R8G8B8X8_UNORM
The commit helps to resolve GL_INVALID_OPERATION error returned
during CTS test when Android format RGBX8888 fallback to RGBA8888
and then set color with glTexSubImage2D(format=GL_RGB).

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:
 #SingleLayer_ColorTest_GpuSampledImageCanBeSampled_R8G8B8X8_UNORM

Cc: <mesa-stable@lists.freedesktop.org>
Fixes: bf576772ab ("dri_util: add driImageFormatToSizedInternalGLFormat function")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5034>
(cherry picked from commit 02a1f95386)
2020-05-27 21:54:15 +02:00
Andrii Simiklit
2303be5ff1 i965/vec4: Ignore swizzle of VGRF for use by var_range_end()
Issue description from Matt's commit e7c376ad:
 "var_range_end(v, n) loops over the n components of variable number v and
  finds the maximum value, giving the last use of any component of v.
  Therefore it expects v to correspond to the variable associated with the
  .x channel of the VGRF.

  var_from_reg() however returns the variable for the first channel of the
  VGRF, post-swizzle.

  So, if the last register had a swizzle with y, z, or w in the swizzle
  component, we would read out of bounds. For any other register, we would
  read liveness information from the next register.

  The fix is to convert the src_reg to a dst_reg in order to call the
  dst_reg version of var_from_reg() that doesn't consider the swizzle."

Closes: #3003
Fixes: 48dfb30f ('intel/compiler: Move all live interval analysis results into vec4_live_variables')
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4941>
(cherry picked from commit d1b7462849)
2020-05-27 21:54:15 +02:00
D Scott Phillips
a366c3f548 anv/gen11+: Disable object level preemption
An unknown issue is causing vs push constants to become corrupted
during object-level preemption. For now, restrict to command
buffer level preemption to avoid rendering corruption.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5110>
(cherry picked from commit 81201e4617)
2020-05-27 21:54:15 +02:00
Eric Engestrom
ad8cd753a1 .pick_status.json: Update to a91306677c 2020-05-27 21:54:10 +02:00
Eric Engestrom
d41ccffb63 VERSION: bump to 20.1.0-rc4
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-05-20 20:56:43 +02:00
Dylan Baker
6328352ae6 tests: Make tests aware of meson test wrapper
Meson 0.55.0 will set the MESON_EXE_WRAPPER environment variable to the
joined version of that wrapper if it is needed. Our tests that take
compiled targets as arguments can use that information to run cross
built binaries, or if there isn't a wrapper and we get an ENOEXEC, we
can skip the tests gracefully.

We try to use mesonlib.split_args, which handles windows arguments
better than python's builtin shlex module, but fall back to that if the
meson module isn't available for some reason.

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5103>
(cherry picked from commit 5580322486)
2020-05-20 20:55:20 +02:00
Icecream95
a18df71c67 panfrost: Enable PIPE_CAP_VERTEX_COLOR_UNCLAMPED
This tells Mesa to clamp vertex colours in the vertex shader.

This improves rendering in a number of games such as Extreme Tux
Racer and H-Craft Championships.

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5075>
(cherry picked from commit faf28b83fd)
2020-05-20 20:55:20 +02:00
Rhys Perry
6b7e48f160 nir/opt_if: run opt_peel_loop_initial_if after all other optimizations
Fixes dEQP-VK.graphicsfuzz.loops-ifs-continues-call with RADV.

opt_if_loop_terminator can cause this optimization or
opt_if_simplification to be run on the non-SSA code.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 52c8bc0130 ('nir: make opt_if_loop_terminator() less strict')
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2943
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4757>
(cherry picked from commit 50bead32b1)
2020-05-20 20:55:20 +02:00
Emmanuel Gil Peyrot
5049d8518e Expose EGL_KHR_platform_* when EXT is supported
On EGL 1.4, one had to check for the existence of EGL_EXT_platform_base
before querying the eglGetPlatformDisplayEXT() and
eglCreatePlatformWindowSurfaceEXT() symbols, to then use them if the
EGL_EXT_platform_* extension for the given platform was exposed.

Since EGL 1.5, the platform functionality was made core, which means we
can obtain the symbols unconditionally, but we can't know the EGL
version before having created a display, at which point we've already
done a platform selection by passing an EGLNativeDisplay.  The
EGL_KHR_platform_* extensions thus are used by clients to know whether
it's safe or not to dlsym() the EGL 1.5 symbols.

This commit adds those extensions when the given platform is enabled.

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5052>
(cherry picked from commit a3fb064e00)
2020-05-20 20:55:20 +02:00
Gert Wollny
1edaba5f4a r600/sfn: Fix printing vertex fetch instruction flags
Fixes: f718ac6268
    r600/sfn: Add a basic nir shader backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5085>
(cherry picked from commit 32305c0959)
2020-05-20 20:55:20 +02:00
Michel Dänzer
b5a7d4b68b Revert "gallium/gallivm: fix compilation issues with llvm 11"
This reverts commit e2a7436dd1.

The corresponding LLVM changes were reverted.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2983

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5087>
(cherry picked from commit 667126cc82)
2020-05-20 20:55:20 +02:00
Michel Dänzer
b195f77730 Revert "ac,radeonsi: fix compilations issues with LLVM 11"
This reverts commit 42b1696ef6.

The corresponding LLVM changes were reverted.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5087>
(cherry picked from commit 2a6811f0f9)
2020-05-20 20:55:19 +02:00
Jason Ekstrand
6e5158ff60 anv:gpu_memcpy: Emit 3DSTATE_VF_INDEXING on Gen8+
If this gets run right after something which uses
VK_VERTEX_INPUT_RATE_INSTANCE on its first vertex binding, we could end
up in serious trouble.

Fixes: 3d9747780b "anv: Add a helper for doing buffer copies with..."

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5090>
(cherry picked from commit 164aed6c81)
2020-05-20 20:55:19 +02:00
Christopher Egert
d358af0503 radv: use util_float_to_half_rtz
Since commit 8b8af6d398 there is a
performance regression in dirt 4 on picasso APUs.

The game ends up feeding a large value into this which overflows on the
conversion to 16bit float. With the old implementation (which now lives
in util_float_to_half_rtz) it would be clamped to inf-1, while the new
one returns inf. This causes a performance hit somehow at some point
down the line.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 8b8af6d398 "gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl."
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5062>
(cherry picked from commit 78615dcca1)
2020-05-20 20:55:19 +02:00
Joshua Ashton
fa18ad0f64 radeonsi: Use TRUNC_COORD on samplers
The default behaviour (0) is: "round-nearest-even to n.6 and drop fraction when point sampling" whereas the OpenGL spec simply wants us to floor it (1) "truncate when point sampling".
See 8.14.2 in the OpenGL spec:

https://www.khronos.org/registry/OpenGL/specs/gl/glspec46.core.pdf

The Direct3D spec also mandates this (https://microsoft.github.io/DirectX-Specs/d3d/archive/D3D11_3_FunctionalSpec.htm#7.18.7%20Point%20Sample%20Addressing)

On WineD3D:
This fixes some point-sampling texture precision issues in some Direct3D 9 titles such as Guild Wars 2 and htoL#NiQ: The Firefly Diary that are not present on other vendors.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3953>
(cherry picked from commit d573d1d825)
2020-05-20 20:55:19 +02:00
Marek Olšák
04ff61811d radeonsi: don't expose 16xAA on chips with 1 RB due to an occlusion query issue
Only Stoney and Raven2 are affected.

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5047>
(cherry picked from commit f80d653d70)
2020-05-20 20:55:19 +02:00
Lucas Stach
4dac0c36a4 etnaviv: retarget transfer to render resource when necessary
If we have a separate render resource, it may contain more up-to-date
data than what is available in the base resource, so we need to retarget
the transfer to this resource. As the most likely reason for the
existence of the render resource is a multi-tiled render layout we need
to allow this transfer to go through the resolve/blit copy path, as we
can't de-/tile those layouts in software.

Fixes: b962776530 (etnaviv: rework compatible render base)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5051>
(cherry picked from commit 9d1821adf0)
2020-05-20 20:55:19 +02:00
Erik Faye-Lund
8142a52255 zink: implement i2b1
This shuold really have been implemented before starting to use these,
but I guess I missed them.

Fixes a crash when starting a game in Warzone 2100.

Fixes: 7f6a491eec ("zink: lower b2b to b2i")
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5053>
(cherry picked from commit 09ac0350fd)
2020-05-20 20:55:19 +02:00
Bas Nieuwenhuizen
5a6f40fd34 radv: Provide a better error for permission issues with priorities.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4816>
(cherry picked from commit 9e3c6a7ba7)
2020-05-20 20:55:19 +02:00
Ian Romanick
a6c55b1a5b anv/tests: Don't rely on assert or changing NDEBUG in tests
This is the last part of the fix for #2903.

v2: Add test_common.h.

Fixes: f7c56475d2 ("anv/tests: compile to something sensible in release builds")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
(cherry picked from commit f4638cfdad)
2020-05-20 20:55:19 +02:00
Danylo Piliaiev
a31c646aee anv: Fix deadlock in anv_timelines_wait
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2945
Fixes: 34f32a6d66
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5005>
(cherry picked from commit 06b6c687e2)
2020-05-20 20:55:19 +02:00
Danylo Piliaiev
493eaebc99 anv: Translate relative timeout to absolute when calling anv_timelines_wait
Fixes: 34f32a6d66
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5025>
(cherry picked from commit 15dd7933bc)
2020-05-20 20:55:19 +02:00
Jan Palus
906c933e12 targets/opencl: fix build against LLVM>=10 with Polly support
see https://bugs.llvm.org/show_bug.cgi?id=44870

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4511>
(cherry picked from commit a1b69d101a)
2020-05-20 20:55:18 +02:00
Eric Engestrom
178156b3e5 post_version.py: stop adding release candidates to the index and relnotes
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2870
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4929>
(cherry picked from commit 445e559e35)
2020-05-20 20:55:18 +02:00
Eric Engestrom
afdd3037b4 post_version.py: invert is_point into is_first_release to make its purpose clearer
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4929>
(cherry picked from commit ae26149e2e)
2020-05-20 20:55:18 +02:00
Eric Engestrom
ab0eed45b1 post_version.py: fix branch name construction for release candidates
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2870
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4929>
(cherry picked from commit 5fba85bcb8)
2020-05-20 20:55:18 +02:00
Eric Engestrom
404180c500 .pick_status.json: Update to 5a6beb6a24 2020-05-20 20:55:13 +02:00
Eric Engestrom
c49fbacd94 VERSION: bump to 20.1.0-rc3
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-05-13 19:14:21 +02:00
Andres Gomez
ed872abd56 gitlab-ci: correct tracie behavior with replay errors
[dump_trace_images] Info: Dumping trace /tmp/tracie.test.ap5pshYcsg/traces-db/trace1/magenta.testtrace... ERROR
[dump_trace_images] Debug: === Failure log start ===
invalid literal for int() with base 16: 'in'
[dump_trace_images] Debug: === Failure log end ===
[check_image] Trace /tmp/tracie.test.ap5pshYcsg/traces-db/trace1/magenta.testtrace couldn't be replayed. See above logs for more information.
Traceback (most recent call last):
  File "/tmp/tracie.test.ap5pshYcsg/tracie.py", line 176, in <module>
    main()
  File "/tmp/tracie.test.ap5pshYcsg/tracie.py", line 164, in main
    ok, result = gitlab_check_trace(project_url, commit_id, args.device_name, trace, expectation)
TypeError: cannot unpack non-iterable bool object

Fixes: efbbf8bb81 ("tracie: Print results in a machine readable format")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4839>
(cherry picked from commit a6beb051af)
2020-05-13 14:44:57 +02:00
Andres Gomez
d1e3c0b430 gitlab-ci: create always the "results" directory with tracie
Otherwise, we will fail when the traces description file doesn't
contain any checksum for the specified device.

Fixes: efbbf8bb81 ("tracie: Print results in a machine readable format")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4839>
(cherry picked from commit 8546d1dd78)
2020-05-13 14:44:56 +02:00
Marek Vasut
97e2965b07 etnaviv: Disable seamless cube map on GC880
The GC880 on iMX6DL indicates in it's minorFeatures2 register that it
does support SEAMLESS_CUBE_MAP, however when the TE.SAMPLER_CONFIG1
VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP bit is set on GC880 on iMX6DL,
the result is corrupted image. In particular, the following ~112 dEQPs
are affected and fail:

  dEQP-GLES2.functional.texture.filtering.cube.*

This only happens on MX6DL GC880, MX6Q GC2000 and STM32MP1 GC400(GCnano)
do not report the minorFeatures2 SEAMLESS_CUBE_MAP bit and ignore the
TE_SAMPLER_CONFIG1 VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP bit (note
that ss->seamless_cube_map is unconditionally set by mesa at times even
PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE returns 0), so there is no visible
problem and there are no failing dEQP tests on the GC2000 and GCnano.

This might imply that the minorFeatures2 SEAMLESS_CUBE_MAP has some
different meaning on GC880 or the SEAMLESS_CUBE_MAP behaves differently
on the GC880.

This patch does not set the SEAMLESS_CUBE_MAP bit on hardware which does
not indicate support for seamless cube map and on GC880, which results
in reduction in failed dEQPs: 635 to 186 on GC880, 274 to 270 on GC2000
and no change on GC400(GCnano).

Fixes: 8dd26fa2f0 ("etnaviv: support GL_ARB_seamless_cubemap_per_texture")
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4865>
(cherry picked from commit 2b535ac61b)
2020-05-13 14:44:54 +02:00
Rob Clark
8b409a429f freedreno/ir3: fix indirect cb0 load_ubo lowering
We can no longer assume that `state->ranges[0]` is block 0.  It *often*
is, but when we encounter a "real" ubo that we lower to `load_uniform`
before a block 0 `load_ubo`, it could end up another entry in the table.
Resulting in the second pass after gathering ubo ranges, not finding a
valid range.  Which results in a `load_ubo` for a thing that is not
actually a ubo making it's way into ir3 frontend.  Resulting in grabbing
what we think is a ubo address out of some unrelated const register, and
trying to dereference that.  Which as you can imagine, fails in amusing
ways.

Fixes: fc850080ee ("ir3: Rewrite UBO push analysis to support bindless")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4954>
(cherry picked from commit d69f6fd852)
2020-05-13 14:44:53 +02:00
Arcady Goldmints-Orlov
fef7d3c73e intel/compiler: fix alignment assert in nir_emit_intrinsic
Fixes: c643979228 (intel/fs: Choose memory message type based on bit size)
Fixes: dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i8vec2

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5000>
(cherry picked from commit 95fd950d35)
2020-05-13 14:44:52 +02:00
Samuel Pitoiset
67c3c06541 radv: limit the Vulkan version to 1.1 for Android
Vulkan 1.2 seems rejected. This hardcodes the Android version to
1.1.107.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2936
Fixes: 7f5462e349 ("radv: enable Vulkan 1.2")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4985>
(cherry picked from commit 69430921fc)
2020-05-13 14:44:51 +02:00
Gert Wollny
464bbd6aaa r600: Fix nir compiler options, i.e. don't lower IO to temps for TESS
Also fix alignments and add umad24 and umul24 options.

Fixes: 6747a984f5
    r600: Enable tesselation for NIR

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4982>
(cherry picked from commit 50eabb7035)
2020-05-13 14:44:49 +02:00
Axel Davy
5c0738f967 gallium/util: Fix leak in the live shader cache
When the nir backend is used, the create_shader
call is supposed to release state->ir.nir.
When the cache hits, create_shader is not called,
thus state->ir.nir should be freed.

There is nothing to be done for the TGSI case as the
tokens release is done by the caller.

This fixes a leak noticed in:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/2931

Fixes: 4bb919b0b8

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4980>
(cherry picked from commit 47bfc799da)
2020-05-13 14:44:48 +02:00
Ian Romanick
750a0125df nir/algebraic: Optimize ushr of pack_half, not ishr
When a = -1.0, pack_half_2x16(vec2(0x0000, 0xBC00)) will produce
0xBC000000.  The ishr will produce 0xFFFFBC00.  The replacement
pack_half_2x16(vec2(0xBC00, 0x0000)) will produce 0x0000BC00.

Fixes: 1f72857739 ("nir/algebraic: add some half packing optimizations")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4515>
(cherry picked from commit a2bf41ec65)
2020-05-13 14:44:44 +02:00
Samuel Pitoiset
fa01a9397f aco: fix 64-bit trunc with negative exponents on GFX6
v_frexp_exp returns the exponent as an unsigned value.

Also, v_ashr returns either 0 or -1 depending on the sign of the
source operand, but what we want is only the sign bit.

Fixes a bunch of recent dEQP-VK.glsl.builtin.precision_double.* tests.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4921>
(cherry picked from commit 3fba0a7a6f)
2020-05-13 14:44:42 +02:00
Eric Engestrom
c4b59dbe81 .pick_status.json: Update to c1c0cf7a66 2020-05-13 14:44:38 +02:00
Jordan Justen
2ab0496842 docs/relnotes/new_features.txt: Add RKL to 20.1 release notes
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2020-05-10 16:33:45 -07:00
Jordan Justen
c75ab0a241 intel/dev: Add device info for RKL
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>
(cherry picked from commit 45c33313e6)
2020-05-11 00:22:20 +02:00
Jordan Justen
7d5074f4a6 intel/dev: Split .num_subslices out of GEN12_FEATURES macro
The .num_subslices field makes it problematic to reuse the
GEN12_FEATURES macro in other macros.

This also fixes the number of L3 banks for tgl gt1, except that this
was already fixed by Jason (dynamically) in:

86f67952d3 ("intel/devinfo: Compute the correct L3$ size for Gen12")

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by : Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4955>
(cherry picked from commit 54996ad492)
2020-05-10 23:21:22 +02:00
Qiang Yu
096e06c56a panfrost: don't always build bifrost_compiler
src/panfrost/shared is shared with lima driver, build
bifrost_compiler for lima driver is meaningless and
get link error when only lima driver is enabled.

So only build bifrost_compiler when configued with:
  meson -Dtools=panfrost

Fixes: ec2a59cd7a "panfrost: Move non-Gallium files outside of Gallium"
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4960>
(cherry picked from commit 07b0fbea92)
2020-05-10 23:20:04 +02:00
Eric Engestrom
1e3e805b0c .pick_status.json: Update to 56f955e485 2020-05-10 23:20:02 +02:00
Arcady Goldmints-Orlov
c22388ed7e anv: increase minUniformBufferOffsetAlignment to 64
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4904>
(cherry picked from commit a0de2e0090)

squashed with its fix:

anv: fix alignments for uniform buffers

We were not consistent with minimums reported in the physical device
properties.

Fixes a few CTS tests :
   dEQP-VK.memory.requirements.dedicated_allocation.buffer.regular
   dEQP-VK.memory.requirements.extended.buffer.regular
   dEQP-VK.memory.requirements.core.buffer.regular

v2: Use define for the limit

v3: Rename define

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a0de2e0090 ("anv: increase minUniformBufferOffsetAlignment to 64")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4940>
(cherry picked from commit 8bcfce2fcd)
2020-05-08 18:31:42 +02:00
Blaž Tomažič
be882b566b radeonsi: Fix omitted flush when moving suballocated texture
Fixes: 5e805cc74b "radeonsi: flush the context after resource_copy_region for buffer exports"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4925>
(cherry picked from commit 808eb20186)
2020-05-08 18:27:00 +02:00
pal1000
38f1cf4335 util: Make process_test path compatible with mingw native toolchains
v2: Make sure we require winepath when using mingw crosscompilers

v3: Also take into account mingw clang toolchains

Acked-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>

Fixes: f8f14130 ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2788
CC: "20.1" <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4731>
(cherry picked from commit 772b15ad32)
2020-05-08 18:27:00 +02:00
Daniel Schürmann
dd42e82586 aco: either copy-propagate or inline create_vector operands
Don't do both at the same time as it breaks DCE

Fixes: 2dc550202e ('aco: copy-propagate p_create_vector copies of vectors')
Fixes: dEQP-VK.glsl.builtin.precision_double.ldexp.compute.scalar on GFX6-GFX7

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4922>
(cherry picked from commit 37e89e3027)
2020-05-08 18:27:00 +02:00
Lionel Landwerlin
a603ee96b3 anv: don't expose VK_INTEL_performance_query without kernel support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Acked-by: Timothy Strelchun <timothy.strelchun@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4937>
(cherry picked from commit 4f17e9eef6)
2020-05-08 18:27:00 +02:00
Erik Faye-Lund
4628e95920 util/os_memory: never use os_memory_debug.h
This is currently broken hard, because this code is being used in more
places that it used to be, and fixing that is prohibitively hard right
now.

This is far from ideal, as it leaves the same inconsistency in the
EMBEDDED_DEVICE code-path. But that only used by VMWare, so it's
probably better if they fix it, as they know their requirements better
than we do.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2911
Fixes: 76f79db3f5 ("util: stop including files from mesa/main")
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4919>
(cherry picked from commit 7ba2333cc1)
2020-05-08 18:26:59 +02:00
Jose Maria Casanova Crespo
77e06f9d4b v3d: Include supported DXT formats to enable s3tc/dxt extensions
DXT1_RGBA and sRGB variants of DXT[135] formats are enabled as
valid format on V3D.

Once all S3TC formats supported by V3C are enabled the following
extensions become exposed by gallium.

    * GL_ANGLE_texture_compression_dxt3
    * GL_ANGLE_texture_compression_dxt5,
    * GL_EXT_texture_compression_dxt1
    * GL_EXT_texture_compression_s3tc
    * GL_S3_s3tc
    * GL_EXT_texture_compression_s3tc_srgb

This enables 206 passing piglit test related to gl_compressed.*s3tc_dxt

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
(cherry picked from commit 905edc376d)
2020-05-08 18:26:59 +02:00
Jose Maria Casanova Crespo
f060438be0 v3d: Fix swizzle in DXT3 and DXT5 formats
Swizzles were ignoring the W component of the format DXT3_RGBA and
DXT5_RGBA.

This fixes 15 piglit tests:

spec/!opengl 1.1/copyteximage 2d
spec/!opengl 1.2/copyteximage 3d
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba npot
spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgba, swizzled, border color only
spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgba, border color only
spec/arb_texture_cube_map/copyteximage cube
spec/arb_texture_cube_map/copyteximage cube samples=2
spec/arb_texture_cube_map/copyteximage cube samples=4
spec/arb_texture_rectangle/copyteximage rect
spec/arb_texture_rectangle/copyteximage rect samples=2
spec/arb_texture_rectangle/copyteximage rect samples=4
spec/ext_texture_array/copyteximage 2d_array
spec/ext_texture_array/copyteximage 2d_array samples=2
spec/ext_texture_array/copyteximage 2d_array samples=4

Fixes: 469bbd8387 "broadcom/vc5: Move the formats table to per-V3D-version compile."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
(cherry picked from commit e3ecf48dda)
2020-05-08 18:26:59 +02:00
Pierre Moreau
1dfbdca81d clover/nir: Check the result of spirv_to_nir
Fixes: deb04adf2a ("clover: add support for passing kernels as nir to the driver")
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4901>
(cherry picked from commit 38bbfd3a57)
2020-05-08 18:26:59 +02:00
Eric Engestrom
a5d3bc88f4 .pick_status.json: Update to 772b15ad32 2020-05-08 18:26:50 +02:00
Eric Engestrom
e658e900bb VERSION: bump to 20.1.0-rc2
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-05-06 21:49:41 +02:00
Marek Olšák
f7d67c99a6 radeonsi: fix compilation of monolithic PS
This was totally broken. Monolithic PS is only used if FBFETCH or
interpolateAtSample are used.

When the PS prolog was built, it overwrote ctx->main_fn.

Discovered by @eefano.

Fixes: 8832a88434 "radeonsi: move PS LLVM code into si_shader_llvm_ps.c"
Closes: #2814

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4918>
(cherry picked from commit 29da521280)
2020-05-06 19:32:39 +02:00
Danylo Piliaiev
b896c506b8 i965: Fix out-of-bounds access to brw_stage_state::surf_offset
../src/mesa/drivers/dri/i965/brw_wm_surface_state.c:1378:32: runtime error: index 3503345872 out of bounds for type 'uint32_t [149]'

brw_assign_common_binding_table_offsets has the following comment:
 "Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 unused but also make sure that addition of small offsets to them will
 trigger some of our asserts that surface indices are < BRW_MAX_SURFACES."

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4350>
(cherry picked from commit 784358bd6e)
2020-05-06 19:32:28 +02:00
Samuel Pitoiset
fa1739113b radv: don't report error with other vendor DRM devices
Enumeration should just skip unsupported DRM devices.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
(cherry picked from commit 8d993c9d2c)
2020-05-06 19:32:28 +02:00
Samuel Pitoiset
d4c1cb59c2 radv: report INITIALIZATION_FAILED when the amdgpu winsys init failed
The driver should be capable if it reaches the winsys initialization.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
(cherry picked from commit f03abd5041)
2020-05-06 19:32:28 +02:00
Erik Faye-Lund
1ed51096ac zink: lower b2b to b2i
Zink requires 1-bit booleans, but this requirement was missed before
b2b1s started getting automatically inserted. Let's lower these away, to
avoid piglit regressions.

Fixes the following piglits:
- shaders@glsl-vs-if-bool
- spec@!opengl 2.0@vertex-program-two-side

Fixes: c217ee8d35 ("nir: Insert b2b1s around booleans in nir_lower_to")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2902
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4903>
(cherry picked from commit 7f6a491eec)
2020-05-06 19:32:28 +02:00
Dave Airlie
a36b7d8c97 llvmpipo/nir: free compute shader NIR
I forgot this in the last round.

Fixes: 18f896e55d (llvmpipe: add initial nir support)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4899>
(cherry picked from commit 870b6a6050)
2020-05-06 19:32:28 +02:00
Dave Airlie
ebb656bfb3 draw/tess: free tessellation control shader i/o memory.
Fixes: 0d02a7b8ca (draw: add main tessellation code)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4899>
(cherry picked from commit d1ad1be35a)
2020-05-06 19:32:28 +02:00
Rhys Perry
b4e46da708 nir: add missing group_memory_barrier handling
Totals from 2 (0.00% of 127638) affected shaders:
VGPRs: 164 -> 168 (+2.44%)
CodeSize: 18420 -> 18756 (+1.82%)
Instrs: 3658 -> 3700 (+1.15%)
Cycles: 82912 -> 83080 (+0.20%)
VMEM: 70 -> 69 (-1.43%)
PreVGPRs: 155 -> 168 (+8.39%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
CC: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4889>
(cherry picked from commit a46aa3dc2e)
2020-05-06 19:32:28 +02:00
Pierre-Eric Pelloux-Prayer
f2a012f987 radeonsi: don't print gs_copy_shader stats for shaderdb
Fixes: dbc86fa3de ("radeonsi: dump shader stats when hitting the live cache")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
(cherry picked from commit 547e81655a)
2020-05-06 19:32:28 +02:00
Pierre-Eric Pelloux-Prayer
a25234047f driconf: add force_integer_tex_nearest option
And enable it for "GRID Autosport" and "DIRT: Showdown" games.

CC: 20.1 <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1258
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
(cherry picked from commit 403eb507f5)
2020-05-06 19:32:28 +02:00
Pierre-Eric Pelloux-Prayer
ae44a916ec mesa: add gl_coontext::ForceIntegerTexNearest
Some applications incorrectly use GL_LINEAR* values for integers texture.
copyimage.c already implemented a tolerance for such app in prepare_target_err.

This commit adds a boolean that will treat GL_LINEAR* filters as
GL_NEAREST for integer textures.

CC: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
(cherry picked from commit 12fb7d7008)
2020-05-06 19:32:28 +02:00
Eric Engestrom
6486ac1a4c .pick_status.json: Update to 29da521280 2020-05-06 19:32:19 +02:00
Eric Engestrom
ad9b00ee4e .pick_status.json: Mark 3fac55ce0d as denominated 2020-05-06 19:09:48 +02:00
Marek Olšák
de3a2b29bc ac/surface: fix MSAA crash with FORCE_SWIZZLE_MODE on gfx9
Fixes: 3dc2ccc14c "ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE"

Closes: #2884

Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4862>
(cherry picked from commit c4cdef64ad)
2020-05-05 18:56:46 +02:00
Marek Olšák
12d23b4a08 Revert "ac: reassociate FP expressions for inexact instructions for radeonsi"
This reverts commit cf2f3c2753.

It breaks shadows in Unigine Superposition.

Fixes: cf2f3c2753

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4837>
(cherry picked from commit b97cc41aa2)
2020-05-05 18:56:46 +02:00
Christian Gmeiner
33a086f44e etnaviv: do not use int filter when anisotropic filtering is used
The blob does not use this combination. This change moves the
decision if int filter gets used to state emit time.

Fixes: 7aaa0e5908 ("etnaviv: add anisotropic filter support")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4872>
(cherry picked from commit 89a41dae77)
2020-05-05 18:56:46 +02:00
Christian Gmeiner
00001525f5 etnaviv: fix SAMP_ANISOTROPY register value
This caused some serious problems like shredded output, ~1fps and GPU hungs.

Fixes: 7aaa0e5908 ("etnaviv: add anisotropic filter support")
Reported-by: Lukas F. Hartmann <lukas@mntmn.com>
Tested-by: Lukas F. Hartmann <lukas@mntmn.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4872>
(cherry picked from commit b38e51bd96)
2020-05-05 18:56:46 +02:00
Jason Ekstrand
86629193f5 vulkan: Allow destroying NULL debug report callbacks
Fixes: 086cfa5652 "anv: implementation of VK_EXT_debug_report extension"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4690>
(cherry picked from commit 9d10bde5a8)
2020-05-05 18:56:46 +02:00
Tapani Pälli
e1e22e38e7 st/mesa: destroy only own program variants when program is released
Earlier commit tried to achieve this but actually did more. This makes
sure the variants for other contexts continue to live.

Fixes: de3d7dbed5 ("mesa/st: release variants for active programs before unref")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2865
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4831>
(cherry picked from commit 46b3cb011f)
2020-05-05 18:56:45 +02:00
Pierre-Eric Pelloux-Prayer
4af564cb92 radeonsi: fix export count
Fixes: 17acff01a0 ("radeonsi: skip vs output optimizations for some outputs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2877
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4871>
(cherry picked from commit 7e7bb38bd8)
2020-05-05 18:56:45 +02:00
Eric Engestrom
7a93e75a41 .pick_status.json: Update to 5779694698 2020-05-05 18:56:45 +02:00
Marek Olšák
4e07d00fa5 Revert "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
This reverts commit f6d87ec8a9.

It breaks RADV.

Fixes: f6d87ec8a9 "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4864>
(cherry picked from commit f1a40a26a9)
2020-05-05 18:56:45 +02:00
Bas Nieuwenhuizen
ec918aa04c radv: Extend tiling flags to 64-bit.
SCANOUT is bit 63 ....

Fixes: bfd9e7ff24 "radv: Use new scanout gfx9 metadata flag."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2879
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4859>
(cherry picked from commit df9629e593)
2020-05-05 18:56:45 +02:00
Rhys Perry
afa6e8cc0b aco: add message to static_assert
static_assert without a message is only supported with C++17 and later.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: c99107ece0
    ('aco: add explicit padding for all Instruction sub-structs')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4850>
(cherry picked from commit b5f7b0ce19)
2020-05-05 18:56:45 +02:00
Rhys Perry
a63ca1776f aco: remove use of f-strings
f-strings require Python 3.6 but 3.5 is still maintained and used.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2839
Fixes: 2ab45f41 ("aco: implement sub-dword swaps")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4850>
(cherry picked from commit 8e02de4d7f)
2020-05-05 18:56:45 +02:00
D Scott Phillips
263451f9c9 anv,iris: Fix input vertex max for tcs on gen12
gen12 does away with the single patch dispatch mode for tcs, and
increases some limits so that 8_patch mode can always work. Make the
necessary changes so we don't try to fall back to single patch mode.

Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others

Fixes: 44754279ac ("intel/fs/gen12: Use TCS 8_PATCH mode.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4843>
(cherry picked from commit 65b05ebdda)
2020-05-05 18:56:45 +02:00
D Scott Phillips
3668e27ec3 intel/fs: Update location of Render Target Array Index for gen12
Render Target Array Index has moved from R0.0[26:16] to
R1.1[26:16] on gen12.

Fixes dEQP-VK.multiview.input_attachments.*

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4836>
(cherry picked from commit 7bd15135a6)
2020-05-05 18:56:45 +02:00
Tomeu Vizoso
5a7b5ea470 panfrost: Add Bifrost texture trampoline BO to batch
Fixes: d3eb23adb5 ("panfrost: Emit sampler descriptor on bifrost")
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
(cherry picked from commit 3a81abf3b2)
2020-05-05 18:56:45 +02:00
Samuel Pitoiset
e2037aea0c ci: fix reporting the number of unexpected/flakes
`wc -l $file` returns the number of lines and the filename.

Fixes: b8c66aeb93 ("ci: Clean up some excessive use of pipes in dEQP results processing.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4829>
(cherry picked from commit cc2c3b41b8)
2020-05-05 18:56:45 +02:00
Marek Olšák
725f45bc63 radeonsi: revert an accidental change in si_clear_buffer
The change was in: 7b0b085c94

Fixes: 7b0b085c94 ("radeonsi: drop the negation from fmask_is_not_identity")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
(cherry picked from commit bdd2f284d9)
2020-05-05 18:56:45 +02:00
Marek Olšák
16c3eca327 radeonsi: unify and align down the max SSBO/TBO/UBO buffer binding size
Rounding down the size fixes:
    KHR-GL45.enhanced_layouts.ssb_member_invalid_offset_alignment

Fixes: 03e2adc990

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
(cherry picked from commit e58dcc47c3)
2020-05-05 18:56:45 +02:00
Lionel Landwerlin
c98e895185 iris: don't assert on unfinished aux import in copy paths
After a resource is created the first command using it could be a copy
command.

In iris_state we finish the import on surface/view creation but we
don't do that for copies.

v2: Move finish call to gallium entrypoints (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2725
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4657>
(cherry picked from commit 612e35c8d9)
2020-05-05 18:56:45 +02:00
Andres Gomez
8c0ad1d2db gitlab-ci: update tracie README after changes in main script
v2:
  - Update the default location for the traces when there is no
    traces-db entry in the traces definition file (Alexandros).

Fixes: 90a39af5f6 "(ci: Drop the git dependency in tracie)"
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4640>
(cherry picked from commit 5e9ae40430)
2020-05-04 22:00:04 +02:00
Francisco Jerez
4e710b3c37 intel/ir: Update performance analysis parameters for memory fence codegen changes.
The SFID field of the SHADER_OPCODE_MEMORY_FENCE and
SHADER_OPCODE_INTERLOCK instructions now indicates the target function
of the memory fence.  Account the cycle-count cost to the right shared
unit.

Fixes: f858fa26b4 ("intel/fs,vec4: Pull stall logic for memory fences up into the IR")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4817>
(cherry picked from commit 0842758ec0)
2020-05-04 22:00:03 +02:00
Rob Clark
8229d22234 freedreno: fix buffer import
`rsc->layout.cpp` is zero until we `fd_resource_layout_init()`

Fixes: 5a8718f01b ("freedreno: Make the slice pitch be bytes, not pixels.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4818>
(cherry picked from commit a0fe98b478)
2020-05-04 22:00:02 +02:00
Bas Nieuwenhuizen
6236c97699 radv: Fix implicit sync with recent allocation changes.
the implicit sync flag gets set at the beginning at the function,
but I used = instead of |= later.

Fixes: bec9285027 "radv: Stop using memory type indices."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4814>
(cherry picked from commit 85fe0e551f)
2020-05-04 22:00:00 +02:00
Eric Engestrom
1b0e98c295 .pick_status.json: Update to af55bdd05d 2020-05-04 21:59:52 +02:00
Eric Engestrom
0865c5107f VERSION: bump to 20.1.0-rc1
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2020-04-30 00:09:58 +02:00
Jonathan Marek
3e1b93ec4f turnip: fix wrong substream size in parse_multisample_and_color_blend
Missed updating this when adding tu6_emit_sample_locations

Fixes: a92d2e1109 ("turnip: implement VK_EXT_sample_locations")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4795>
2020-04-29 20:09:54 +00:00
Eric Anholt
05e6f763e7 util/ra: Improve ra_set_finalize() performance.
BITSET_FOR_EACH_SET can walk a sparse set (such as a register class's set
of registers) much faster than just iterating over individual bits.

Improves freedreno startup time (as measured by shader-db ./run
shaders/closed/gputest/triangle on my x86 system) by -4.12679% +/-
1.99006% (n=151)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
2020-04-29 19:46:08 +00:00
Eric Anholt
53ac2dabec util/ra: Use util_dynarray for handling the conflict lists.
Again, shortens the code significantly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
2020-04-29 19:46:08 +00:00
Eric Anholt
57088854e6 util/ra: Use util_dynarray for the adjacency list.
This make the code significantly more readable, I think (along with
shorter).  Also, using util_dynarray_delete_unordered() saves us a move of
the rest of the list when removing adjacency on a node.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
2020-04-29 19:46:08 +00:00
Eric Anholt
a1de267a21 util/ra: Sanity check that we're adding a valid reg to a class.
BITSET_SET might not segfault on you right away if you're just slightly
off, and an assert is nicer anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
2020-04-29 19:46:08 +00:00
Eric Anholt
5bcaf30aba util/ra: Sanity check that the driver selected a valid reg.
freedreno was returning -1 when it didn't pick a reg from the given bitset
due to an off-by-a-small-number error.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
2020-04-29 19:46:08 +00:00
Konrad Dybcio
fc66800032 freedreno/a4xx: enable A405
This patch brings support for Adreno A405
as found on MSM8939. That chip is a cut-down
version of A4XX IP and requires no special handling.

Tested on Asus Zenfone 2 Laser (Z00T) smartphone.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4753>
2020-04-29 19:15:58 +00:00
Mike Blumenkrantz
328cc00d39 iris: handle PIPE_CAP_CLEAR_SCISSORED
this allows passing scissored clear calls through the driver where it can
be handled by a repclear shader

fix kwg/mesa#61

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4310>
2020-04-29 18:05:06 +00:00
Mike Blumenkrantz
1c8bcad81a gallium: add pipe cap for scissored clears and pass scissor state to clear() hook
this adds a new pipe cap that drivers can support which enables passing buffer
clears with scissor test enabled through to be handled by the driver instead
of having mesa draw a quad

also adjust all existing clear() hooks to have the new parameter

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4310>
2020-04-29 18:05:06 +00:00
Caio Marcelo de Oliveira Filho
882928dcaa i965: Use correct constant for max_variable_local_size
Fixes: 5664bd6db3 ("i965: Implement ARB_compute_variable_group_size")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4799>
2020-04-29 17:12:42 +00:00
Mike Blumenkrantz
91375f13ce iris: move iris_vtable to iris_screen
instead of inlining this into every context, now a struct is used in the screen
struct to reduce memory usage and simplify a couple of the methods

Closes: https://gitlab.freedesktop.org/kwg/mesa/-/issues/6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4376>
2020-04-29 16:59:45 +00:00
Jason Ekstrand
e581ddeeee intel/fs: Don't delete coalesced MOVs if they have a cmod
Shader-db results on ICL:

    total instructions in shared programs: 17133088 -> 17133287 (<.01%)
    instructions in affected programs: 61300 -> 61499 (0.32%)
    helped: 0
    HURT: 199

This means it's likely fixing 199 bugs. :-)  All the changed shaders are
in Mad Max.  It's surprisingly difficult to get the back-end compiler to
generate a pattern that hits this we don't tend to emit a lot coalescable
MOVs.  The pattern in Mad Max that's able to hit is fsign(fsat(x)) under
the right conditions.

Closes: #2820
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4773>
2020-04-29 16:45:51 +00:00
Marek Olšák
6fe7d6758a st/mesa: expose more SPIR-V capabilities
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4760>
2020-04-29 16:25:06 +00:00
Marek Olšák
a2542deb63 mesa: report GL_INVALID_OPERATION for invalid glTextureBuffer target
This fixes:
    KHR-GL46.direct_state_access.textures_buffer_errors
    KHR-GL46.direct_state_access.textures_buffer_range_errors

Fixes: 98e64e538a - main: Added entry point for glTextureBuffer

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4759>
2020-04-29 15:58:45 +00:00
Alyssa Rosenzweig
ffa314eab3 pan/mdg: Replicate 16-bit swizzles
We don't support vec8 quite yet anyway, this fixes dot products.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
c571d31b8b pan/mdg: Ensure fdot is scalar out in disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
95664b177f pan/mdg: Move condense_writemask to disasm
The compiler should *never* use this. Packing should be 1 way.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
efc9ab6dcc pan/mdg: Pass through some types from scheduling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
d8d7df6f09 pan/mdg: Don't crash on unknown branch target
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
e27fd4b3ec pan/mdg: Make some branch targets more explicit
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
dfa7c26ff8 pan/mdg: Always print the mask
Meaningful for fp16.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
459cf59c61 pan/mdg: Specialize swizzle to type
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
62768590d5 pan/mdg: Lower specials to 32-bit
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
bb0e85fca4 pan/mdg: Move sampler_type emission to pack time
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
08af4c788d pan/mdg: Set texture full fields at pack time
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
4fb02174a3 pan/mdg: Track texture types
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
53c183736e pan/mdg: Track v_mov type (force uint32 for now?)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
74fadc8859 pan/mdg: Denoise prints
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
714eba8762 pan/mdg: Track a primary type for I/O
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
04f76ad8ae pan/mdg: Another goofy comment gone
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
ecf946638e pan/mdg: Track ALU dest type
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
6757c480ab pan/mdg: Track ALU src types
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
742b272314 pan/mdg: Add type fields to IR
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
b9f7f06a61 pan/bi: Share ALU type printing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
6c08e294c8 pan/mdg: Set lower_flrp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
05f5267f23 pan/mdg: Remove old hack
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
2020-04-29 15:35:54 +00:00
Alyssa Rosenzweig
d7f98a87f2 pan/mdg: Remove goofy 16-bit comment
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
3b10bcd417 pan/mdg: Don't break SSA
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
23337fd590 pan/mdg: SSA_FIXED_MINIMUM already covered by PAN_IS_REG
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
63eec105b2 pan/mdg: Use PAN_IS_REG
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
d4600c4340 pan/mdg: Remove nir_alu_src_index
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
fbbe3d4b75 pan/bi: Use common IR indices
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
5860b18665 panfrost: Move Bifrost IR indexing to common
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Alyssa Rosenzweig
e3062edff4 panfrost: Fix BO reference counting
Typo.

Fixes: 3283c7f4da ("panfrost: Inline reference counting routines")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
2020-04-29 15:18:38 +00:00
Marek Olšák
22a4cb4937 ac: enable displayable DCC on Navi12 & Navi14
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
3b45631d7a ac/surface: validate that DCC is enabled correctly on gfx9+
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
5e31e4b697 ac/surface: add code for gfx10 displayable DCC
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
e2fbba7720 ac/surface: move non-displayable DCC to the end of the buffer
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
a3dc7fffbb ac/surface: don't compute DCC if it's unsupported by DCN on gfx9+
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
5d785f99b7 ac/surface: match get_display_flag() with expectations for is_displayable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
3dc2ccc14c ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
f6d87ec8a9 ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set
So that drivers can enable it without worrying how the texture was
allocated.

v2: reworked the mechanism, hopefully fixes now
    added Bas Nieuwenhuizen's diff to fix radv

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Marek Olšák
25d3cc293e ac/surface: rename micro tile mode enums like gfx10 uses them
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
2020-04-29 14:53:25 +00:00
Thomas Hellstrom
298e247776 winsys/svga: Optionally avoid caching buffer maps
Mapping of graphics kernel buffers is quite costly. Therefore the svga
drm winsys caches all kernel buffer maps. However, that may lead to
less testing coverage of the unmap paths and (possibly) processes running
out of virtual memory space. Introduce a possibility to avoid that caching
by setting the environment variable SVGA_FORCE_KERNEL_UNMAPS to 1.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matthew McClure <mcclurem@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4804>
2020-04-29 13:45:12 +00:00
Thomas Hellstrom
422148de52 gallium/pipebuffer: Use persistent maps for slabs
Instead of the ugly practice of relying on the provider caching maps,
introduce and use persistent pipebuffer maps. Providers that can't handle
persistent maps can't use the slab manager.

The only current user is the svga drm winsys which always maps
persistently.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4804>
2020-04-29 13:45:12 +00:00
Timur Kristóf
e4e1a0ac13 radv: Use smaller esgs_itemsize for ACO.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
ee5f04c9c9 aco: Use new default driver locations.
The way the new locations are set up has much fewer gaps
between each I/O slot, so this results in a massive reduction
in the LDS usage of tessellation shaders.

Totals (GFX10):
VGPRS: 3976792 -> 3974864 (-0.05 %)
Code Size: 260552784 -> 260532860 (-0.01 %) bytes
LDS: 48723 -> 30179 (-38.06 %) blocks
Max Waves: 1053407 -> 1053583 (0.02 %)

Totals from affected shaders (1407 shaders on GFX10):
SGPRS: 59144 -> 59216 (0.12 %)
VGPRS: 63024 -> 61096 (-3.06 %)
Code Size: 2695508 -> 2675584 (-0.74 %) bytes
LDS: 47109 -> 28565 (-39.36 %) blocks
Max Waves: 12999 -> 13175 (1.35 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
efa4976709 radv: Use new linking helper to set default driver locations.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
7aa61c84fe nir: Add new linking helper to set linked driver locations.
This commit introduces a new function nir_assign_linked_io_var_locations
which is intended to help with assigning driver locations to shaders
during linking, primarily aimed at the VS->TCS->TES->GS stages.

It ensures that the linked shaders have the same driver locations,
and it also packs these as close to each other as possible.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
7056714f50 aco: Set config->lds_size when TES or VS is running on HW ESGS.
This doesn't fix anything, just reports the LDS size used by
merged ESGS shaders, such as vertex_geometry_gs and
tess_eval_geometry_gs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
baa46878d4 aco: Calculate workgroup size of legacy GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
fdbb296853 aco: Remember VS/TCS output driver locations.
Instead of relying on calling shader_io_get_unique_index repeatedly,
remember the which output driver location corresponds to which
varying slot.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
ab07c4ea70 aco: Use context variables instead of calculating TCS inputs/outputs.
VS needs the number of TCS inputs, and TES needs the number of TCS
outputs.

It is error-prone to repeat those calculations in both instruction
selection and setup. Just set them in one place instead.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Timur Kristóf
fd0248c37b radv: Refactor calculate_tess_lds_size and get_tcs_num_patches.
Previously these functions needed the bit mask of the TCS outputs
and patch outputs written, and concluded the number of outputs
from that.

Now, they take the number of outputs and patch outputs instead.
This will allow the backend compiler to better optimize the
LDS layout.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
2020-04-29 11:51:04 +00:00
Rhys Perry
9392ddab43 aco: consider blocks unreachable if they are in the logical cfg
unreachable was true if the last block is unreachable in the linear cfg,
but it should also be true if it is unreachable in the logical cfg.

Fixes dEQP-VK.graphicsfuzz.for-with-ifs-and-return

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 8d8c864beb
    ('aco: improve check for unreachable loop continue blocks')

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4764>
2020-04-29 11:07:09 +00:00
Christopher James Halse Rogers
98675d34c1 egl/wayland: Fix zwp_linux_dmabuf usage
There's no guarantee that the formats advertised by wl_drm and the formats
advertised by zwp_linux_dmabuf_v1 are the same.

get_back_bo() handles this by falling back from createImageWithModifiers() to
createImage() when there's a wl_drm format but no corresponding linux_dmabuf
format, but create_wl_buffer() unconditionally tries to create a linux_dmabuf
buffer unless DRIimage has DRM_FORMAT_MOD_INVALID.

Fix this by always checking if the DRIimage modifier has been advertised
by zwp_linux_dmabuf_v1, and falling back to wl_drm if not.

If DRM_FORMAT_MOD_INVALID has been advertised then we trust the client
has allocated something appropriate and treat any modifier as matching.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2220
Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4294>
2020-04-29 11:29:40 +01:00
Danylo Piliaiev
8f0d387441 iris/bufmgr: Check if iris_bo_gem_mmap failed
After refactoring of iris_bo_map_cpu and iris_bo_map_wc - immediate
return of NULL on failure to mmap a buffer was lost.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2855
Fixes: 5bc3f52dd8
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4786>
2020-04-29 08:51:33 +00:00
Tapani Pälli
1a33358b27 anv: remove assert from GetImageMemoryRequirements[2]
This assert is actually correct but due to how android hardware buffer
support is implemented we should remove it, otherwise debug build of
mesa hits the assert with Android CTS tests.

Test creates VkImage with non-external format and sets up
VkExternalMemoryImageCreateInfo to indicate that image *may* be used
with Android hardwarebuffer handle. Then test attempts to get image
memory requirements. Problem with this is that we setup all android
supporting images as having external format and thus hit the assert as
the size has not been set yet. This is not a problem in practice since
android will bind ahw memory with the image later on.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2807
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4762>
2020-04-29 08:30:42 +00:00
Samuel Pitoiset
2f6648dc3c gitlab-ci: add a list of expected failures for FIJI with ACO
Timur has this chip now. The depth stencil resolve failures are
somehow unexpected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4805>
2020-04-29 09:53:48 +02:00
Samuel Pitoiset
0e6afbbe56 radv: advertise VK_EXT_robustness2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
0f1ead7b53 radv: handle NULL vertex bindings
With VK_EXT_robustness2, an element of pBuffers can be NULL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
c1ef225d18 radv: handle NULL descriptors
All fields must be zero, otherwise the HW hangs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
60cc065c7d aco: fix adjusting the sample index with FMASK if value is negative
The SPIR-V spec doesn't say explicitly that the sample index
must be an unsigned integer.

This fixes crashes with some new VK_EXT_robustness2 tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
a112ec4c11 aco: fix nir_texop_texture_samples with NULL descriptors
With VK_EXT_robustness2, descriptors can be NULL and the number of
samples returned by nir_texop_texture_samples should be 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Samuel Pitoiset
aa94213781 ac/llvm: fix nir_texop_texture_samples with NULL descriptors
With VK_EXT_robustness2, descriptors can be NULL and the number of
samples returned by nir_texop_texture_samples should be 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4775>
2020-04-29 07:29:54 +00:00
Caio Marcelo de Oliveira Filho
a3cba3c771 intel/fs: Only stall after sending all memory fence messages
In Gen11+, when emitting a fence for both L3 and SLM, the generated
code would look like

    SEND, MOV (for stall), SEND, MOV (for stall)

This commit change that so two SENDs are emitted before the MOVs for
stall.  This is similar to the approach used in Ivy Bridge for the
render fence.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
2020-04-29 07:17:27 +00:00
Caio Marcelo de Oliveira Filho
f858fa26b4 intel/fs,vec4: Pull stall logic for memory fences up into the IR
Instead of emitting the stall MOV "inside" the
SHADER_OPCODE_MEMORY_FENCE generation, use the scheduling fences when
creating the IR.

For IvyBridge, every (data cache) fence is accompained by a render
cache fence, that now is explicit in the IR, two
SHADER_OPCODE_MEMORY_FENCEs are emitted (with different SFIDs).

Because Begin and End interlock intrinsics are effectively memory
barriers, move its handling alongside the other memory barrier
intrinsics.  The SHADER_OPCODE_INTERLOCK is still used to distinguish
if we are going to use a SENDC (for Begin) or regular SEND (for End).

This change is a preparation to allow emitting both SENDs in Gen11+
before we can stall on them.

Shader-db results for IVB (i965):

    total instructions in shared programs: 11971190 -> 11971200 (<.01%)
    instructions in affected programs: 11482 -> 11492 (0.09%)
    helped: 0
    HURT: 8
    HURT stats (abs)   min: 1 max: 3 x̄: 1.25 x̃: 1
    HURT stats (rel)   min: 0.03% max: 0.50% x̄: 0.14% x̃: 0.10%
    95% mean confidence interval for instructions value: 0.66 1.84
    95% mean confidence interval for instructions %-change: 0.01% 0.27%
    Instructions are HURT.

  Unlike the previous code, that used the `mov g1 g2` trick to force
  both `g1` and `g2` to stall, the scheduling fence will generate `mov
  null g1` and `mov null g2`.  During review it was decided it was not
  worth keeping the special codepath for the small effect will have.

Shader-db results for HSW (i965), BDW and SKL don't have a change
on instruction count, but do report changes in cycles count, showing
SKL results below

    total cycles in shared programs: 341738444 -> 341710570 (<.01%)
    cycles in affected programs: 7240002 -> 7212128 (-0.38%)
    helped: 46
    HURT: 5
    helped stats (abs) min: 14 max: 1940 x̄: 676.22 x̃: 154
    helped stats (rel) min: <.01% max: 2.62% x̄: 1.28% x̃: 0.95%
    HURT stats (abs)   min: 2 max: 1768 x̄: 646.40 x̃: 362
    HURT stats (rel)   min: <.01% max: 0.83% x̄: 0.28% x̃: 0.08%
    95% mean confidence interval for cycles value: -777.71 -315.38
    95% mean confidence interval for cycles %-change: -1.42% -0.83%
    Cycles are helped.

  This seems to be the effect of allocating two registers separatedly
  instead of a single one with size 2, which causes different register
  allocation, affecting the cycle estimates.

while ICL also has not change on instruction count but report changes
negative changes in cycles

    total cycles in shared programs: 352665369 -> 352707484 (0.01%)
    cycles in affected programs: 9608288 -> 9650403 (0.44%)
    helped: 4
    HURT: 104
    helped stats (abs) min: 24 max: 128 x̄: 88.50 x̃: 101
    helped stats (rel) min: <.01% max: 0.85% x̄: 0.46% x̃: 0.49%
    HURT stats (abs)   min: 2 max: 2016 x̄: 408.36 x̃: 48
    HURT stats (rel)   min: <.01% max: 3.31% x̄: 0.88% x̃: 0.45%
    95% mean confidence interval for cycles value: 256.67 523.24
    95% mean confidence interval for cycles %-change: 0.63% 1.03%
    Cycles are HURT.

  AFAICT this is the result of the case above.

Shader-db results for TGL have similar cycles result as ICL, but also
affect instructions

    total instructions in shared programs: 17690586 -> 17690597 (<.01%)
    instructions in affected programs: 64617 -> 64628 (0.02%)
    helped: 55
    HURT: 32
    helped stats (abs) min: 1 max: 16 x̄: 4.13 x̃: 3
    helped stats (rel) min: 0.05% max: 2.78% x̄: 0.86% x̃: 0.74%
    HURT stats (abs)   min: 1 max: 65 x̄: 7.44 x̃: 2
    HURT stats (rel)   min: 0.05% max: 4.58% x̄: 1.13% x̃: 0.69%
    95% mean confidence interval for instructions value: -2.03 2.28
    95% mean confidence interval for instructions %-change: -0.41% 0.15%
    Inconclusive result (value mean confidence interval includes 0).

  Now that more is done in the IR, more dependencies are visible and
  more SWSB annotations are emitted.  Mixed with different register
  allocation decisions like above, some shaders will see more `sync
  nops` while others able to avoid them.

  Most of the new `sync nops` are also redundant and could be dropped,
  which will be fixed in a separate change.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
2020-04-29 07:17:27 +00:00
Caio Marcelo de Oliveira Filho
0e96b0d6dd intel/fs: Allow FS_OPCODE_SCHEDULING_FENCE stall on registers
It will generate the MOVs (or SYNC_NOP in Gen12+) needed for stall.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
2020-04-29 07:17:27 +00:00
Bas Nieuwenhuizen
9248b04528 radv: Expose 4G element texel buffers.
Old value seems to be copied from anv.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4787>
2020-04-29 07:05:04 +00:00
Kenneth Graunke
506414e837 iris: Fix downcast of bound_vertex_buffers from uint64_t to int
This is the wrong data type, the original field - and the values we're
adding in - are both 64-bit unsigned.  Keep the original data type.

Thanks to Dave Airlie for finding this while reading the code.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4802>
2020-04-29 06:50:54 +00:00
Francisco Jerez
5e2a7e11b4 intel/ir: Remove scheduling-based cycle count estimates.
The cycle count estimation logic part of the scheduler is now
redundant with the shader performance modeling pass, and the estimates
can be consolidated into the brw::performance analysis result object
instead of being part of the CFG, which guarantees that the estimates
cannot be accessed without previously calling the
performance_analysis::require() method, which makes sure that the
right analysis pass is executed at the right time if we don't already
have up-to-date cached results.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
486f3b04a5 intel/ir: Pass block cycle count information explicitly to disassembler.
So we can eventually remove the cycle count estimates from the CFG
data structure and consolidate performance information in the
brw::performance object.

It would be cleaner to pass the brw::performance object directly to
the disassembler but that isn't straightforward since the disassembler
is built as a plain C file unlike the rest of the compiler back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
6579f562c3 intel/ir: Use brw::performance object instead of CFG cycle counts for codegen stats.
These should be more accurate than the current cycle counts, since
among other things they consider the effect of post-scheduling passes
like the software scoreboard on TGL.  In addition it will enable us to
clean up some of the now redundant cycle-count estimation
functionality in the instruction scheduler.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
65342be3ae intel/fs: Add INTEL_DEBUG=no32 debugging flag.
This is useful in order to identify codegen issues caused by SIMD32.
It doesn't currently have any effect on compute shaders since SIMD32
dispatch is only enabled for CS when it's strictly necessary to do so
in order to support the workgroup size requested for the shader --
That might change in the future though when we hook up the SIMD32
heuristic to CS compilation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
14f0a5cf64 intel/fs: Implement performance analysis-based SIMD32 heuristic for fragment shaders.
The heuristic enables the SIMD32 fragment shader based on whether the
IR performance modeling pass predicts it to have greater throughput
than the SIMD16 and SIMD8 variants of the same shader.  It would be
straightforward to do the same thing in order to control whether
SIMD16 dispatch is enabled, but it's pending additional performance
evaluation.

The INTEL_DEBUG=do32 option is left around in order to force the
SIMD32 shader to be used regardless of the result of the heuristic,
since it's useful as a debugging aid e.g. in order to identify
SIMD32-specific codegen issues which may be masked by the SIMD32
heuristic, or cases where the heuristic is incorrectly disabling
SIMD32 shaders that offer a performance advantage.

Currently this is only enabled on Gen6+, since SIMD32 codegen support
is incomplete on earlier platforms.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
d6aa0c261f intel/fs: Heap-allocate fs_visitors in brw_compile_fs().
This makes brw_compile_fs() look a bit more similar to
brw_compile_cs().  It saves us three v*_shader_stats local variables,
and will save us additional triplicated declarations as we start
tracking IR performance analysis results.

The triplicated cfg pointers are left around because they're set to
NULL to mark specific dispatch modes as disabled (e.g. in order to
enforce hardware restrictions).  Doing the same thing with the visitor
pointers would cause data leaks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:27 -07:00
Francisco Jerez
188a3659ae intel/ir: Import shader performance analysis pass.
This introduces an analysis pass intended to estimate several
performance statistics of the shader, including cycle count latency
and throughput values, based on static modeling.  It has instruction
performance information more comprehensive than the current scheduling
pass for all platforms between Gen4-11, and works on both the FS and
VEC4 back-end.

The most immediate purpose of this pass is to implement a heuristic
meant to determine whether using SIMD32 dispatch for a fragment shader
can be expected to help more than it hurts.  In addition this will
allow the effect of passes run after scheduling (e.g. the TGL software
scoreboard pass and the VEC4 dependency control pass) to be visible in
shader-db statistics.

But that isn't the end of the story, other potential applications of
this pass (not part of this MR) I've been playing around with are:

 - Implement a similar SIMD16 heuristic allowing the identification of
   inefficient SIMD16 fragment shaders.

 - Implement similar SIMD16 and SIMD32 heuristics for the compute
   shader stage -- Currently compute shader builds always use the
   SIMD16 shader if available and never use the SIMD32 shader unless
   strictly necessary, which is suboptimal under certain conditions.

 - Hook up to the instruction scheduler in order to improve the
   accuracy of its timing information.

 - Use as heuristic in order to drive the selection of scheduling
   modes (Matt was experimenting with that).

 - Plug to the TGL software scoreboard pass in order to implement a
   more effective SBID token allocation algorithm, since in general
   the optimal token allocation depends on the timings of all
   instructions in the program.

 - Use its bottleneck detection functionality in order to implement a
   heuristic computing a more optimal bound for the number of fragment
   shader threads executed in parallel (by adjusting the
   MaximumNumberofThreadsPerPSD control of 3DSTATE_PS).

As a follow-up I'm planning to submit updated timing information for
Gen12 platforms -- Everything else required to support Gen12 like SWSB
handling is already included in this patch, but there were some IP
concerns regarding the TGL timing parameters since they cannot
currently be obtained with the documentation and hardware which is
publicly available.  The timing parameters for any previous Gen7-11
platforms can be obtained by anyone by sampling the timestamp register
using e.g. shader_time, though I have some more convenient
instrumentation coming up.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:01:03 -07:00
Francisco Jerez
c8ce1cfc9c intel/vec4: Fix constness of vec4_instruction::reads_flag() and ::writes_flag().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
bda1d72dd9 intel/fs: Replace fs_visitor::bank_conflict_cycles() with stand-alone function.
This will be re-usable by the IR performance analysis pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
d2ed740795 intel/fs: Fix constness of argument of fs_instruction_scheduler::is_compressed().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
6310a05f68 intel/fs: Rename half() helpers to quarter(), allow index up to 3.
Makes more sense considering SIMD32.  Relaxing the assertion in
brw_ir_fs.h will be required in order to avoid assertion failures on
SNB with SIMD32 fragment shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
bdad7f429a intel/ir: Add missing initialization of backend_reg::offset during construction.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
e549e4f6c0 intel/fs/gen12: Fix Render Target Read header setup for new thread payload layout.
In Gen12 the Poly 0 Info DWORD containing the Viewport Index and
Render Target Index fields were moved from r0.0 to r1.1 in order to
make room for dual-polygon dispatch.  The render target message format
was updated to expect that information in the same location, so we
didn't need to make any changes for framebuffer fetch to work with
SIMD8 and SIMD16 dispatch.  Unfortunately that won't work with SIMD32,
since the render target message header is assembled from r0 and r2
instead of r1, and the r2 thread payload wasn't updated with an
additional copy of the same information.  We need to fix things up
manually instead.  This avoids a handful of
EXT_shader_framebuffer_fetch regressions in combination with SIMD32
fragment shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:29 -07:00
Francisco Jerez
72324035fb intel/fs/gen12: Work around dual-source blending hangs in combination with SIMD32.
This applies the same work-around I commited as b84fa0b31e
"intel/fs/gen11: Work around dual-source blending hangs in combination
with SIMD32." to Gen12, which seems to suffer from the same hardware
bug found empirically.  The failure mode seems to be identical.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:28 -07:00
Francisco Jerez
d6ae079771 intel/fs/gen12: Fix hangs with per-sample SIMD32 fragment shader dispatch.
The Gen12 docs are rather contradictory regarding the dispatch
configurations supported by the fragment shader -- The same table
present in previous generations seems to imply that only one dispatch
mode can be enabled when doing per-sample shading, but a restriction
documented in the 3DSTATE_PS_BODY page implies the opposite: That
SIMD32 can only be used in combination with some other dispatch mode.

The latter seems to match the behavior of real hardware as I could
tell from my testing: A bunch of multisample test-cases that do
per-sample shading hang if we only provide a SIMD32 shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-04-28 23:00:28 -07:00
Dylan Baker
35ee6b3d36 mesa: Follow OpenGL conversion rules for values that exceed storage size
Section 2.2.2 (Data Conversions For State Query Commands) of the
OpenGL 4.5 spec says:

  Following these steps, if a value is so large in magnitude that
  it cannot be represented by the returned data type, then the
  nearest value representable using that type is returned.

The current code doesn't do the correct thing, because it truncates a
long (potentially a 64bit values) to an int.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2828
Fixes: 53c36dfcfe
       ("replace IROUND with util functions")

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4673>
2020-04-29 04:26:41 +00:00
Alyssa Rosenzweig
76c5688018 pan/bit: Add BITWISE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4790>
2020-04-29 00:30:05 +00:00
Alyssa Rosenzweig
844c3f94b5 pan/bit: Interpret BI_BITWISE
No shifting yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4790>
2020-04-29 00:30:05 +00:00
Alyssa Rosenzweig
a077da6273 pan/bi: Handle iand/ior/ixor in NIR->BIR
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4790>
2020-04-29 00:30:05 +00:00
Alyssa Rosenzweig
ef9582738e pan/bi: Pack BI_BITWISE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4790>
2020-04-29 00:30:05 +00:00
Alyssa Rosenzweig
9b415bf6a0 pan/bi: Add bitwise modifiers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4790>
2020-04-29 00:30:05 +00:00
Rob Clark
6de01faac5 freedreno/a6xx: invalidate tex state cache entries on rebind
When a resource's backing bo changes, its seqno will be incremented.
Which would result in a new tex state cache key, and nothing to clean
up the old tex state until the sampler view/state is destroyed.  But
in some games, that may never happen, or at least not happen before
we run out of memory.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2830
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
ca05e6b04d freedreno: rebind_resource() *before* bo changes
This will matter in the next patch, where we need the original
rsc->seqno.

It means slight shuffling of where we call rebind_resource() in the
`fd_try_shadow_resource()` path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
d9e56d8a69 freedreno: rebind resource in all contexts
If the resource is rebound, we need to invalidate in all contexts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
f12188ff52 freedreno: optimize rebind_resource()
Track how resources are used, ie. which state they may potentially dirty
if the backing bo is changed/reallocated, to optimize rebind_resource().

This will be more important in a later patch when we hook up eviction of
entries in a6xx tex state cache.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
1e18c58047 freedreno: mark more state dirty when rebinding resources
Plus a bonus typo fix.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
bf97cc9221 freedreno: don't realloc idle bo's
The `DISCARD_WHOLE_RESOURCE` is just a hint.  And `rebind_resource()` is
a bunch of faffing about (and going to get worse in a later patch), so
let's not bother when the bo is already idle.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Rob Clark
938b6ed645 freedreno: small whitespace fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4744>
2020-04-29 00:08:57 +00:00
Jan Zielinski
a93b728bc6 gallium/swr: Fix crashes and failures in vertex fetch
This commit fixes two problems:
- In some cases SWR does not correctly report to Gallium
  which formats are supported.
- Incorrect LLVM instructions are used in vertex fetch in some situations

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4788>
2020-04-28 23:53:08 +00:00
Rob Clark
de0d3d1726 freedreno/log-parser: support to read gzip'd logs
~50MB gzip'd log files are nicer than ~300MB uncompressed

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4750>
2020-04-28 23:31:58 +00:00
Rob Clark
f561e516c8 freedreno/a6xx: pre-calculate expected vsc stream sizes
We should only rely on overflow detection for indirect draws, where we
have no other option.

This doesn't use quite the worst-possible-case sizes, which in practice
seem to be ~20x larger than what is required.  But instead uses roughly
half of that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4750>
2020-04-28 23:31:58 +00:00
Rob Clark
99d802ccc7 freedreno: add helper to estimate # of bins per pipe
For vsc size calculation, we need to know the # of bins per pipe.  Or at
least the worst-case # of bins, assuming we don't eliminate an unused depth/
stencil buffer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4750>
2020-04-28 23:31:58 +00:00
Rob Clark
a9c255d70c freedreno/a6xx+tu: rename VSC_DATA/VSC_DATA2
These are the draw-stream and primitive-stream, so lets give them more
descriptive names.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4750>
2020-04-28 23:31:58 +00:00
Rhys Perry
3ee3ad561a aco: fix vgpr nir_op_vecn with sgpr operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
c5eda3c746 aco: improve clamped integer addition disassembly workaround
Make it work with 16-bit and GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
4ed83e2f94 aco: add various GFX10 int16 opcodes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
43f2ba39ef aco: fix sub-dword overwrite check in RA validator
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
cca8d6ce06 aco: fix sub-dword out-of-bounds check in RA validator
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
307aca83a2 aco: add missing adjust_max_used_regs()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
99ca96fbf5 aco: improve RA for uneven p_split_vector
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
24116a8a56 aco: don't recurse in sub-dword get_reg_simple()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
09c584caeb aco: split self-intersecting copies instead of swapping
Example situation:
v1 = {v0.hi, v1.lo}
v0.hi = v1.hi

The 4-byte copy's definition is completely used, but swapping it makes no
sense. We have to split it to generate correct code:
swap(v0.hi, v1.lo)
swap(v0.hi, v1.hi)

Found in dEQP-VK.spirv_assembly.type.vec3.i16.constant_composite_vert

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
be4a34966c aco: fix neighboring register check in get_reg_simple()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
fb59ed6bb9 aco: check alignment of non-subdword registers in get_reg_specified()
When splitting a v6b vector into v1 and v2b components, we should ensure
the v1 definition doesn't start at the upper half.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Rhys Perry
916cc3e231 aco: make RegisterFile::block() take a regclass
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4772>
2020-04-28 23:16:55 +00:00
Jason Ekstrand
b43366497b anv: Claim VK_EXT_robustness2 support
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
b07d26be65 anv: Handle null vertex buffer bindings
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
fd817291c7 anv: Handle NULL descriptors
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
ac581a06a4 nir/combine_stores: Handle volatile
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
cb9292091b nir/dead_write_vars: Handle volatile
We can't remove volatile writes and we can't combine them with other
volatile writes so all we can do is clear the unused bits.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
ed67717167 nir/copy_prop_vars: Report progress when deleting self-copies
Fixes: 62332d139c "nir: Add a local variable-based copy prop..."

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
d9af5277b3 nir/copy_prop_vars: Handle volatile better
For deref_store, we can still delete invalid stores that write to
statically OOB data.  For everything, we need to make sure that we kill
aliases of destinations even if it's volatile.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
118f045fb7 vulkan: Update Vulkan XML and headers to 1.2.139
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4767>
2020-04-28 22:55:25 +00:00
Jason Ekstrand
76d2772472 anv: Allow all clear colors for texturing on Gen11+
Starting with Gen11, we have two indirect clear colors: An unconverted
float/int version which is us used for rendering and a converted pixel
value version which is used for texturing.  Because the one used for
texturing is stored as a single pixel of that color, it works no matter
what format is being used.  Because it's a simple HW indirect and
doesn't involve copying surface states around, we can use it in the
sampler without having to worry about surface states having out-of-date
clear values.  The result is that we can now allow any clear color when
texturing.

This cuts the number of resolves in a RenderDoc trace of Dota2 by 95%
on Gen11+ (you read that right) and improves perf by 3.5%.  It improves
perf in a handful of other workloads by < 1%.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
e63c662c26 anv: Use anv_layout_to_aux_usage for color during render passes
Previously, we tried to treat color image layouts as a special case
during render passes.  This is largely an artifact of history as our
initial understanding of Vulkan placed much more emphasis on render
passes than our current understanding.  The only real practical use for
magic layouts in the middle of a render pass, as far as I can tell, is
to allow more clear colors to get passed through to input attachments.
However, most apps aren't very creative with their clear colors and very
few of them (none coming from DXVK) actually use render passes in any
interesting way.  Therefore, the risk of being able to pass fewer clear
colors through to input attachments should be minimal.

There are, however, three very big advantages to this change:

 1. We are now consistent in our handling of aux usage and layouts
    between color and depth/stencil.

 2. We are now actually following the layout guidelines from the app and
    aren't nearly as likely to see strange behavior due to us overriding
    the image layouts manually.

 3. It's more obviously correct.  While I think our old render pass code
    was probably correct, it was full of corner cases and it's very
    possible that it was behaving badly in weird ways.  This follows the
    Vulkan API much more blindly and, as such, is more likely to be
    correct and behave the same as other implementations.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
30016f6e82 anv: Split color_attachment_compute_aux_usage in two
In particular, we split out an anv_can_fast_clear_color_view helper
which only cares about fast-clear and not aux_usage itself.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
3fe45a9b6c anv: Rework depth_stencil_attachment_compute_aux_usage
Instead of making it a function that pretends to choose aux usage (which
isn't what it does at all), make it a function which returns whether or
not we want to do a fast clear.  This is far more accurate to the
purpose of the function.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
26e6da90ab anv: Refactor cmd_buffer_setup_attachments
This commit just renames some things so that we use names for temporary
variables which are more consistent with other places in the code-base.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
36a74835df anv: Stop allowing non-zero clear colors in input attachments
Previously, we bent over backwards to allow non-zero clear colors input
attachments whenever we could.  However, very few apps use input
attachments and very few use non-zero clear colors.  Getting rid of
support for non-zero clear colors input attachments will allow us to
treat them identically to textures which should help us simplify things
a good bit.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
bf92e96d9c anv: Disallow fast-clears which require format-reinterpretation
In order to actually hit this case you have to be using a very odd
color/view combination.  The common cases of clear-to-zero and 0/1 clear
colors with an sRGB view don't require any re-interpretation.  This is
probably better than always resolving whenever we have a format mismatch
like we are today because that hits the sRGB case every time.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
20e72e435c intel: Move swizzle_color_value from blorp to ISL
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
814dc66935 anv: Allocate surface states per-subpass
Instead of allocating surface states for attachments in BeginRenderPass,
we now allocate them in begin_subpass.  Also, since we're zeroing
things, we can be a bit cleaner about or implementation and just fill
out all those passes for which we have allocated surface states.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
a3d185d091 anv: Split command buffer attachment setup in three
This commit splits genX(cmd_buffer_setup_attachments)() into three
functions: one which sets up cmd_buffer->state.attachments, one which
allocates surface states, and one which fills out the surface states.
While we're here, we make both functions take the framebuffer (if any)
as an argument instead of pulling it from the command buffer so it's
more clear what things are inputs to the functions.  We also make the
render pass and framebuffer parameters const as those are immutable
objects.  The only functional change here should be that we now
vk_zalloc the attachments which should be a bit safer.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
c195d55161 anv: Mark images written in end_subpass
This makes a lot more sense than marking them written in begin_subpass
since, at that point, we haven't written them yet.  This should reduce
the chances of accidental extra resolves.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
d5e30872ca anv: Use ANV_FROM_HANDLE for pInheritanceInfo fields
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
7cbc5fde13 anv: Assert surface states are valid
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
eaa8f043cd anv: Stop filling out the clear color in compute_aux_usage
It's a pointless micro-optimization that just makes compute_aux_usage
unnecessarily entangled with setting up surface states.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
5808efdf40 anv: Add TRANSFER_SRC to pass usage not subpass usage
The subpass usage flags are supposed to always be one bit and never
multiple bits.  However, when adding in TRANSFER_SRC usage for resolve
attachments we were adding it to the subpass bits and not the render
pass bits.  This potentially is causing issues where images aren't
getting marked written properly.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Jason Ekstrand
513ed7542a anv: Return an error if allocating attachment memory fails
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
2020-04-28 22:45:39 +00:00
Samuel Pitoiset
0549fba3cc radv: advertise VK_AMD_memory_overallocation_behavior
Doom Eternal explicitly allows overallocation via this extension
but that shouldn't change anything because it's the default RADV
behavior.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
2020-04-28 21:03:26 +00:00
Samuel Pitoiset
5832f2b8a3 radv: track memory heaps usage if overallocation is explicitly disallowed
By default, RADV supports overallocation by the sense that it doesn't
reject an allocation if the target heap is full.

With VK_AMD_overallocation_behaviour, apps can disable overallocation
and the driver should account for all allocations explicitly made by
the application, and reject if the heap is full.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
2020-04-28 21:03:26 +00:00
Samuel Pitoiset
32035cca3f radv: remove unused radv_device_memory::map_size field
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
2020-04-28 21:03:25 +00:00
Ian Romanick
7b869710a1 nir/algebraic: Require operands to iand be 32-bit
With the mask value 0x80000000, the other operand must be 32-bit.  This
fixes failures in
dEQP-VK.subgroups.ballot_mask.ext_shader_subgroup_ballot.*.gl_subgroupgemaskarb_*
tests from Vulkan 1.2.2 CTS.

Checking one of the tests, it appears that the tests are doing 64-bit
iand with 0x0000000080000000, then comparing the result with zero.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2834
Fixes: 88eb8f190b ("nir/algebraic: Simplify logic to detect sign of an integer")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4770>
2020-04-28 20:33:56 +00:00
Rob Clark
656051d735 freedreno/ir3/ra: only assign array base in first pass
In particular, we specifically don't want to let the base change between
passes, as it could end up conflicting with registers assigned in the
first pass.

Mostly-closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2838
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
2020-04-28 20:06:49 +00:00
Rob Clark
3d8ec96762 freedreno/ir3/ra: split out helper for array assignment
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
2020-04-28 20:06:49 +00:00
Rob Clark
6313b8d881 freedreno/ir3/ra: use ir3_debug_print helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
2020-04-28 20:06:49 +00:00
Rob Clark
8b3ac7084a freedreno/ir3/ra: remove unused variable
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
2020-04-28 20:06:49 +00:00
Rob Clark
997828e31b freedreno/computer: add script to test widening/narrowing
Just something I hacked together to help figure out which instructions
can fold in a wideing/narrowing conversion.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
2020-04-28 20:06:49 +00:00
Alyssa Rosenzweig
6b551d9f36 pan/bi: Add initial fcmp test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
778e27b5ac pan/bit: Interpret CMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
71501972e9 pan/bit: Prepare condition evaluation for vectors
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
0b8724c340 pan/bi: Relax double-abs condition
Only if both ports (<==> registers) same.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
81156ad55a pan/bi: Pack fma.fcmp16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
7a689470d0 pan/bi: Factor out fp16 abs logic
Also used for fcmp16

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
c94d41ad7c pan/bi: Pack FMA 32 FCMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
1520131d82 pan/bi: Fix source mod testing for CMP
Outputs u32.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
12ca99f2c1 pan/bi: Structify ADD ICMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
ddcefefa7d pan/bi: Structify FMA ICMP 16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
3d41468e7d pan/bi: Structify FMA ICMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
527d7303ca pan/bi: Structify ADD FCMP16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
74795dd328 pan/bi: Structify FMA FCMP16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
28afe3037a pan/bi Strucitfy ADD FCMP 32
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
c861292ce2 pan/bi: Structify FMA FCMP
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
7fe3c145d9 pan/bi: Remove bi_round_op
No purpose.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
95fc71ece2 pan/bi: Deduplicate csel/cmp cond
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
df486689c0 pan/bi(t): Fix SELECT tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
814f2f1d33 pan/bi: Add CSEL.8 opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
e23d191245 pan/bi: Add FCMP.GL.v2f16 on ADD opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
b4f2d3a51c pan/bi: Add 64-bit int compares
Likewise.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
52cc7165c6 pan/bi: Add some 8-bit compares
Not all but enough to see the pattern.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
2f286eed2a pan/bi: Add CSEL.64 opcode
Chain twice for full 64-bit CSEL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Alyssa Rosenzweig
100edfe26d pan/bi: Add bool->float opcodes
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
2020-04-28 17:17:48 +00:00
Samuel Pitoiset
523e9603d3 radv: enable FMASK for color attachments only
The reason behind this is that FMASK requires CMASK and also that
FMASK for non color attachments looks unnecessary. It's currently
much easier to add this simple check because the driver tries to
always enable DCC first and if we enable FMASK only if CMASK, we
might loose some FMASK compressions.

This helps fixing some new robustness2 tests which fails because
only FMASK is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4783>
2020-04-28 17:23:05 +02:00
Jason Ekstrand
81ac741f89 anv: Expose CS workgroup sizes based on a maximum of 64 threads
Otherwise, we'll hit asserts in brw_compile_cs.

Fixes: cf12faef61 "intel/compiler: Restrict cs_threads to 64"
Closes: #2835
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4746>
2020-04-28 14:51:08 +00:00
Jason Ekstrand
86f67952d3 intel/devinfo: Compute the correct L3$ size for Gen12
Fixes: 8125d7960b "intel/dev: Add preliminary device info for Tigerlake"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4782>
2020-04-28 14:34:17 +00:00
Bas Nieuwenhuizen
7262c743dc radv: Determine memory type for import based on fd.
This would be necessary for an application to figure out if the
memory was allocated using a memory type with VK_MEMORY_PROPERTY_PROTECTED_BIT.

It also allows one to determine VRAM vs. GTT etc.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
2020-04-28 15:45:03 +02:00
Bas Nieuwenhuizen
f30983be3a radv/winsys: Add function to get domains/flags from fd.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
2020-04-28 15:45:00 +02:00
Bas Nieuwenhuizen
bec9285027 radv: Stop using memory type indices.
Lots of extra coding was involved in managing them.

And for protected memory I was thinking of making a function that
goes from domain+flags to memory types, which can reuse this array.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
2020-04-28 15:44:56 +02:00
Bas Nieuwenhuizen
4a8d172d3f radv: Use actual memory type count for setting app-visible bitset.
Otherwise we might make a bitset that is too large.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
2020-04-28 15:44:27 +02:00
Bas Nieuwenhuizen
8e03cf15f9 radeonsi: Count planes for imported textures.
For the DRI2 lowered YUV import separate pipe_resources get created
but in the end the first resource just gets asked for NPLANES.

Since

1) (Almost) everything uses the first resource + a plane index in the
  Gallium interface.
2) This mirrors non-imported textures.

lets fix this in the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4779>
2020-04-28 11:16:03 +00:00
Gert Wollny
6747a984f5 r600: Enable tesselation for NIR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
b6d4452661 r600/sfn: Add tesselation shaders
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
d77b81ce50 r600/sfn: Add lowering passes for Tesselation IO
Lower the input and output intrinsics to r600 specific LDS intrinsics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
1b3e103d0b r600/sfn: Move removing of unused variables
It doesn't make sense to do this in the optimization loop

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
74e0a0a723 r600/sfn: Handle LDS output in VS
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
f102301cc4 r600/sfn: derive the GS from the vertex stage for a common interface
The GS can also provide the primid

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
f7df2c57a2 r600/sfn: extract class to handle the VS export to different stages
This code can be shared with the TESS_EVAL shader

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
38038b369f r600/sfn: Move some shader base methods to the public interface
This will be needed for handling the VS stage export better.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
93f5f9e584 r600/sfn: Add methods to valuepool to get a vector of values
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
7cbca9cf64 r600/sfn: Move emission of barrier from compute shader to shader base
Tess shaders also use these barriers.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
46a3033b43 r600/sfn: Emit some LDS instructions
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
a122303711 r600/sfn: Handle umul24 and umad24
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
7e064659cb r600/sfn: Add IR instruction to fetch the TESS parameters
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
075ea32e48 r600/sfn: Add TF write instruction
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
230beac5f8 r600/sfn: Add LDS instruction to assembly conversion
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
b9d175bed2 r600/sfn: Add LDS IO instructions to r600 IR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
172868167e r600/sfn: Don't emit inline constants in the r600 IR
This can be handled when lowering to assembly, and it makes testing
for indirect buffer and sampler access easier.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
9bc6c135ac r600/sfn: simplify UBO lowering pass
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Gert Wollny
096a026354 r600: Handle texcoord semantics in LDS index evaluation
With NIR the texcoord semantic is enabled, and hence we have to handle
index evaluation differently here.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
2020-04-28 08:06:33 +00:00
Christian Gmeiner
7d476a1360 ci: bare-metal: power down device after tests
Helps to save electricity.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4754>
2020-04-28 07:17:24 +00:00
Icecream95
b4cc116339 panfrost: Fix GL_EXT_vertex_array_bgra
Previously, attributes would always use an RGBA swizzle, even if the
format was BGRA.

Fixes piglit tests bgra-sec-color-pointer and bgra-vert-attrib-pointer.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4752>
2020-04-28 00:20:53 +00:00
Dave Airlie
0e135ca227 ci: add llvmpipe paths to virgl rules
since llvmpipe changes will affect virgl

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4777>
2020-04-28 09:55:49 +10:00
Samuel Pitoiset
7a0a6a7180 radv: do not expose GTT as device local memory mostly for APUs
On APUs, the memory is unified (all heaps are equally fast) and
apps should count all memory heaps together. But some games like
Id Tech games (Youngblood and such) don't manage memory correctly
on APUs and they spill everything when one VRAM heap is full.

Instead of spilling buffers, they should just allocate new buffers
in the second heap but it seems like these games are confused if
two memory heaps have the DEVICE_LOCAL_BIT set.

This is probably a first step towards better memory management on
APUs but there is still some work to do if we want to run most apps
with a small dedicated VRAM (256MB or so).

This gives a huge boost for Id Tech games on APUs, and doesn't
seem to reduce Feral games performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4771>
2020-04-27 22:41:41 +00:00
Jan Zielinski
4a523baa00 gallium/swr: Fix LLVM 11 compilation issues
Changes needed to adapt to LLVM API changes in vector
and pointer types.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4769>
2020-04-27 22:29:52 +00:00
Eric Anholt
5082ac007d ci/freedreno: Add a test run of a few driver options.
This lets us get coverage of corner cases of the driver that are tricky to
force a testcase to hit.  We don't want to do a full run of the CTS with
each option because that's a lot of runner time, so stack a bunch of
fractional runs in one test job to amortize the test run setup overhead.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Eric Anholt
b8c66aeb93 ci: Clean up some excessive use of pipes in dEQP results processing.
Given that we use set -x in the script, this actually makes the user
experience of viewing logs nicer.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Eric Anholt
951e101fec ci: Allow namespacing of dEQP run results files.
I want to do multiple runs of some bits of the CTS in one test job to test
some driver options, but I want to be able to see the results from any of
them.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Eric Anholt
69c8dfd49f freedreno: Fix calculation of the const buffer cmdstream size.
The HW packet requires padding the number of pointers you emit, and we
would assertion fail about running out of buffer space if the number of
UBOs to be uploaded was odd.

Fixes: b4df115d3f ("freedreno/a6xx: pre-calculate userconst stateobj size")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Eric Anholt
8b221e0914 ci: Add sanity checking that dEQP gets the expected GL_RENDERER.
It's easy to get something wrong in the driver build or container or
something that results in falling back to swrast, and then your only clue
was runtime and how your failure cases suspiciously match a swrast
driver's.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Eric Anholt
a9e6a3ecc7 ci: Enable --compact-display false on all dEQP runs.
We always want to see status updates happening in the logs, otherwise it
can like maybe your machine hung until the run actually completes.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4621>
2020-04-27 22:10:10 +00:00
Mike Blumenkrantz
acc56300dc zink: explicitly unref old fb object when setting new one
this object has a ref from being created, and its lifetime is expected to
be a single frame, so remove that initial ref when we expect to stop
using it

Closes: #2648
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4768>
2020-04-27 21:55:51 +00:00
Mike Blumenkrantz
d3f0022a43 zink: remove framebuffer cache
this can only match when re-rendering identical frames, which is not a
typical case. the lack of cache eviction also leads to memory ballooning.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4768>
2020-04-27 21:55:51 +00:00
Bas Nieuwenhuizen
afd9274d48 st/dri: Set next in template instead of after creation. (v2)
This should prevent horrors like Iris has with the delayed calls
to iris_resource_finish_aux_import just because info is not
available at allocation time.

AFAICT all drivers just copy the template except radeonsi/r600
which reset the next pointer.

AFAICT there is also no other place we get a state tracker setting
next ptrs on a resource.

v2: Updated Gallium docs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3792>
2020-04-27 21:08:01 +00:00
Erik Faye-Lund
a1e453f504 mesa/st: call _mesa_initialize() early
This allows drivers to reliably do things like using the GLSL
type-system during initialization.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Erik Faye-Lund
57f4c66028 mesa/main: one_time_init() -> _mesa_initialize()
This exposes the logic inside one_time_init() as _mesa_initialize(), so
drivers who needs to use functionality initialized in one_time_init
earlier if they need.

This means we can reliably use the GLSL type-system when compiling
driver built-in shaders.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Erik Faye-Lund
6ff94735c9 mesa/main: Do not pass context to one_time_init
There's no longer any reason to pass the context down to one_time_init,
because we always do the same thing regardless of the context, and we
don't change the context.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Erik Faye-Lund
ac9d30431e mesa/main: do not init remap-table per api
This hasn't really been nessecary since 8386088e3d ("dispatch: stop
using _mesa_create_exec_table_es1() for GLES1."), when we stopped
diverging the logic here based on the context-API. So let's simplify the
code a bit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Erik Faye-Lund
9bc98778a4 mesa/main: do not pass context to one-time extension init
_mesa_problem doesn't use the ctx argument for anything, so there's no
reason to pass it. This saves us from needing a context passed down this
code-path in the first place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Erik Faye-Lund
05c69752cf mesa/main: do not store unrecognized extensions in context
We process extension overrides only when we initialize the first
context, which means that unrecognized extensions only appear in the
first context created.

Let's instead store them in a global array, so we can apply them to all
contexts. This has the added benefit of making the initialization of the
first context less special, which allows us to clean up code a bit more.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4765>
2020-04-27 20:40:01 +00:00
Dave Airlie
9bc5b2d169 vulkan: add initial device selection layer. (v6.1)
This is code Bas has out of tree but I think mesa should be shipping it, and I've improved it.

Initially-written-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
v2: add infinite recursion fix (Bas)
v3: Fix wayland/xcb barrier, whitespace
v4: use a macro for getting apis, shorten some lines, use outarray
v5: rewrite in C, use hash_table/mutex.
v6: use once_init to init the mutex, fix freeing ht

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1766>
2020-04-27 19:57:49 +00:00
Eric Anholt
4a42a50585 freedreno/ir3: Add support for disasm of cat2 float32 immediates.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
292231596b freedreno/ir3: Refactor out print_reg_src().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
3bcf819b43 freedreno/ir3: Convert remaining disasm src prints to reginfo.
More lines of code, but they're much more intelligible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
1462b00391 freedreno/ir3: Add a unit test for our disassembler.
Makes sure that we can maintain consistent output from our disassembly as
we refactor.  I've only included stuff that matches qcom's disasm so far.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
90984ba853 freedreno/ir3: Print a space after nop counts, like qcom's disasm.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
916629f9d7 freedreno/ir3: Fix the disasm of half-float STG dests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4736>
2020-04-27 19:35:00 +00:00
Eric Anholt
6c01152c92 ci: Enable GLES 3.1 testing on db820c (a530).
The driver exposes GLES3.1, so let's make sure we're not regressing its
featureset.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
2020-04-27 19:06:57 +00:00
Eric Anholt
b34ee185f4 freedreno: Fix derivatives without texturing on a3xx-a5xx.
The shader variant tells us if we should set the PIXLODENABLE flag.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
2020-04-27 19:06:57 +00:00
Eric Anholt
fa49a5032f ci: Enable GLES3 testing on db410c/db820c (freedreno a306 and a530).
We haven't had it enabled due tointermittent failures.  Those failures
are, as far as I can tell, due to GPU faults from buffer overflows where a
failing test in a thread stomps an otherwise passing thread's buffers.  By
running deqp single-threaded, we can get more consistent failures, at the
cost of needing to do a tiny subset of the tests to keep runtime down.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
2020-04-27 19:06:57 +00:00
Eric Anholt
c259b3ea12 ci: Drop redundant freedreno stage specification.
The source rules give us the stage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
2020-04-27 19:06:57 +00:00
Jonathan Marek
065068c66a freedreno/ir3: run nir_lower_pack
This lowers pack_32_2x16/unpack_32_2x16 into the scalar versions of those
instructions.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4738>
2020-04-27 18:40:03 +00:00
Jonathan Marek
42093bb694 nir: add pack_32_2x16_split/unpack_32_2x16_split lowering
The new option replaces the two other _split lowering options, since
there's no need for separate options.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4738>
2020-04-27 18:40:03 +00:00
Bas Nieuwenhuizen
cbeda7f78e radv: Add WSI buffers to BO list only if they can be used.
Also reverse the BO list removal loop. This way typical WSI usage
should find the entry in O(active swapchains) iterations, which
should not be a performance issues. Tested with Doom(2106) which
found the entry in 1 iteration every time.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4306>
2020-04-27 18:01:24 +00:00
Bas Nieuwenhuizen
9a61f2a8a9 vulkan/wsi: Add callback to set ownership of buffer.
For radv BO list pruning.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4306>
2020-04-27 18:01:24 +00:00
Samuel Pitoiset
42b1696ef6 ac,radeonsi: fix compilations issues with LLVM 11
Latest LLVM replaced LLVMVectorTypeKind.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2826
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4755>
2020-04-27 17:13:36 +00:00
Jan Zielinski
52aa730d07 gallium/gallivm: remove unused header include for newer LLVM
In the top of the trunk LLVM (11) llvm/IR/CallSite.h header
has been removed. The file compiles without this include also
for LLVM 8, but I'm not sure about 9, 10, and older versions
so I disable it only for the latest LLVM

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4748>
2020-04-27 16:53:44 +00:00
Jan Zielinski
e2a7436dd1 gallium/gallivm: fix compilation issues with llvm 11
Top of the trunk LLVM removes old vector type
and introduces two new ones - one for fixed-width
and one for scalable vectors. This commit fixes
compilation issues by switching from LLVMVectorTypeKind
to LLVMFixedVectorTypeKind for new LLVM.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4748>
2020-04-27 16:53:44 +00:00
Alyssa Rosenzweig
6943eda5c9 ir3: Use shared mediump output lowering
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4716>
2020-04-27 16:32:24 +00:00
Alyssa Rosenzweig
42c9bbaeed nir: Move nir_lower_mediump_outputs from ir3
(Original code from ir3)

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4716>
2020-04-27 16:32:24 +00:00
Ian Romanick
ba8f7f3fa2 nir/algebraic: Detect some kinds of malformed variable names
I spent over an hour trying to debug a problem if a condition on a
variable not being applied.  The problem turned out to be
"a(is_not_negative" instead of "a(is_not_negative)".  This commit would
have detected that problem and failed to build.

v2: Just add $ to the end of the existing regex, and it will fail to
match a malformed string.  Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4720>
2020-04-27 09:08:34 -07:00
Alyssa Rosenzweig
fc4eb0714c pan/bi: Implement 16-bit COMBINE lowering
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
280b65126e pan/bi: Fix RA wrt 16-bit swizzles
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
64c33a459f pan/bit: Add SELECT tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
23ffaa16c7 pan/bit: Interpret BI_SELECT
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
a5bfe59196 pan/bi: Force BI_SELECT arguments scalar
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
c12081dca1 pan/bi: Pack ADD SEL16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
d31e4879f0 pan/bi: Pack FMA SEL8
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
7b31f04bac pan/bi: Pack FMA SEL16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
ee561f0e6b pan/bi: Rename BI_SWIZZLE to BI_SELECT
The select version is more general.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
b2c6cf2b6d pan/bi: Eliminate writemasks in the IR
Since the hardware doesn't support them, they're a burden to deal with,
so let's ensure we never get to a place where we would need to at all.

Disables COMBINE lowering for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
1622478fbd pan/bi: Fix ADD.v4i8 opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
de12311431 pan/bi: Add missing BI_VECTOR
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:26 +00:00
Alyssa Rosenzweig
667190d38a pan/bi: Assign blend descriptor for BLEND op
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:25 +00:00
Alyssa Rosenzweig
1a8f1a324a pan/bi: Passthrough blend types
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:25 +00:00
Alyssa Rosenzweig
5f953b8f50 pan/bi: Passthrough type for ATEST
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:25 +00:00
Alyssa Rosenzweig
462af10bb7 pan/bi: Pack fp16 ATEST
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4766>
2020-04-27 14:52:25 +00:00
Michel Dänzer
c50bbfa0ab mesa: Skip 3-byte array formats in _mesa_array_format_flip_channels
Byte swapping makes no sense for 3-byte formats: Swapping the order of 2
or 4 bytes at a time would inevitably result in bytes getting mixed up
between neighbouring pixels.

Fixes crash with a debugging build on a big endian machine due hitting
the unreachable() at the end of the function.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2665
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4735>
2020-04-27 14:14:00 +00:00
Marek Olšák
ad5da3e63e mesa: replace GLenum target with gl_shader_stage in NewProgram
So that the GLSL compiler doesn't have to use the GLenum conversion
functions.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4756>
2020-04-27 12:49:53 +00:00
Bas Nieuwenhuizen
531728d6cb drm-uapi,radv,radeonsi: Add amdgpu_drm.h header.
Use it instead of the libdrm provided amdgpu_drm.h header. I used
the kernel revision from the README to get the header so the
header versions should be consistent.

Tested by removing /usr/include/libdrm/amdgpu_drm.h from my dev-machine.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4749>
2020-04-27 12:27:02 +00:00
Marek Olšák
03ba57c6c5 mesa: extend _mesa_bind_vertex_buffer to take ownership of the buffer reference
This reduces overhead of _mesa_reference_buffer_object_ from 6% to 4%
with glthread when profiling the game "torcs" with non-VBO data uploaded
by glthread.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
e9afe045cf mesa: add offset_is_int32 param into _mesa_bind_vertex_buffer for glthread
glthread will pass signed integer offsets, so don't reset negative offsets
to 0 there.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
b8223244c3 mesa: add Const.BufferCreateMapUnsynchronizedThreadSafe & MESA_MAP_THREAD_SAFE
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
19eb89b0f3 gallium: add PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE for glthread
and add radeonsi support.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
6215465842 glthread: sort variables in marshal structures to pack them optimally
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
6f8a387b37 glthread: use GLenum16 in batch buffers to save space
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
b6b1ab8d54 glthread: reduce dereferences of the next batch
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
fc4b78f4cc glthread: use 32-bit align instead of 64-bit ALIGN
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
41671ec544 mesa: remove exec="dynamic" from Draw functions that are not really dynamic
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
00b5791541 mesa: reset primitive restart state in glClientAttribDefaultEXT
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
ee0263e03f mesa: replace _NEW_EVAL with vbo_exec_update_eval_maps
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
2020-04-27 11:56:06 +00:00
Marek Olšák
cf2f3c2753 ac: reassociate FP expressions for inexact instructions for radeonsi
Totals:
SGPRS: 2591784 -> 2590696 (-0.04 %)
VGPRS: 1666888 -> 1666736 (-0.01 %)
Spilled SGPRs: 4131 -> 4107 (-0.58 %)
Spilled VGPRs: 38 -> 38 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2228 -> 2228 (0.00 %) dwords per thread
Code Size: 52715468 -> 52693584 (-0.04 %) bytes
LDS: 92 -> 92 (0.00 %) blocks
Max Waves: 479897 -> 479892 (-0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
4b9370cb0f ac: generate FMA for inexact instructions for radeonsi
NIR mostly does this already.

Totals:
SGPRS: 2588520 -> 2591784 (0.13 %)
VGPRS: 1666984 -> 1666888 (-0.01 %)
Spilled SGPRs: 4074 -> 4131 (1.40 %)
Spilled VGPRs: 38 -> 38 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2228 -> 2228 (0.00 %) dwords per thread
Code Size: 52726872 -> 52715468 (-0.02 %) bytes
LDS: 92 -> 92 (0.00 %) blocks
Max Waves: 479872 -> 479897 (0.01 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
f2c2a28073 ac: update and document fast math flags used by radeonsi
This should have no effect, because we never use FP division, but
it's safer for the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Marek Olšák
3bb65c0670 ac: force enable -structurizecfg-skip-uniform-regions for LLVM 11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4696>
2020-04-27 11:20:16 +00:00
Danylo Piliaiev
eeab9c93db st/mesa: Treat vertex inputs absent in inputMapping as zero in mesa_to_tgsi
After updating vertex inputs being read based on optimized NIR, they may go out
of sync with inputs in mesa IR. Which is translated to TGSI and used together
with NIR if draw doesn't have llvm.

It's much easier to treat such inputs as zero because there is no pass to
entirely get rid of them and they don't contribute to shader's output.

Fixes: d684fb37bf
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2815
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4705>
2020-04-27 09:30:06 +00:00
Samuel Pitoiset
b785ad5853 gitlab-ci: add lists of expected failures for RADV CI
Currently only supports PITCAIRN, POLARIS10, VEGA10 and NAVI10
with ACO only, but it's a start.

Unfortunately, we have to duplicate and we will have to try to
keep these lists up-to-date, but it's better than nothing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4689>
2020-04-27 07:59:27 +00:00
Samuel Pitoiset
574196d5f6 radv: fix robust_buffer_access if enabled via VkPhysicalDeviceFeatures2
It can be enabled via pEnabledFeatures or via vkPhysicalDeviceFeatures2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4706>
2020-04-27 09:33:44 +02:00
Dave Airlie
8faa0e2c1b gallivm: fix stencil border
Fixes:
dEQP-GLES31.functional.texture.border_clamp.unused_channels.depth32f_stencil8_sample_stencil
dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
565df65651 llvmpipe: clamp color storage for integer types.
If storing to an integer for lower bit size (i.e. 16-bit uint to
10-bit uint), we need to clamp to the maximum value not truncate.

Fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r16_uint.a2b10g10r10_uint_pack32.optimal_optimal_nearest

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
024b5dfc1c llvmpipe: enable stencil only formats. (v2)
This fixes two bugs, one in clearing and one in sign extensions
for S8 only types, and enables it for use.

These are useful for vulkan support later.

v2: move casting to same place as Z casting.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
65906d1331 llvmpipe/setup: add point size clamping
Fixes
dEQP-GLES2.functional.rasterization.limits.points
dEQP-VK.rasterization.primitive_size.points.point_size*

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
1f071db43a llvmpipe: fix d32 unorm depth conversions.
When the depth value was 1.0 and was being converted to Z32_UNORM
the conversion would scale it up to INT32_MAX + 1 which would
cause FPToSI to give incorrect results, changing it to use
FPToUI for the unsigned 32-bit case only fixes it.

Fixes:
GTF-GL45.gtf30.GL3Tests.depth_texture.depth_texture_fbo_clear

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
fe5a8e1ace draw/tess: fix TES patch vertices in.
Fixes CTS KHR-GL45.tessellation_shader.single.max_patch_vertices

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
7b4a7a1117 llvmpipe: fix ssbo alignment
KHR-GL45.geometry_shader.api.max_shader_storage_blocks

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
93b8d89275 llvmpipe: bump max images to 16
This is needed to make some tests run, and helps for vulkan later.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
e1c006204f util/indirect: handle stride less than number of parameters.
It's legal to have a stride less than the num of parameters,
in this case no need to try and over map the buffer which asserts

Fixes:
GTF-GL45.gtf43.GL3Tests.multi_draw_indirect.multi_draw_indirect_stride

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:24 +10:00
Dave Airlie
23efd323aa gallivm/nir: add helper invocation support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 12:35:21 +10:00
Dave Airlie
13e5f331db gallivm/nir: fix image store conversions
This fixes a few of the image store paths, to do the
correct clamping of unsigned/signed values

Fixes: KHR-GLES31.core.layout_binding.block_layout_binding_block_ComputeShader
KHR-GL45.shader_image_load_store.basic-allFormats-store
KHR-GL46.shader_image_load_store.multiple-uniforms

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4574>
2020-04-27 10:06:00 +10:00
Connor Abbott
bf3c9d2770 tu: Don't invert point coords
We shouldn't need to invert them, and the Vulkan blob doesn't either.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4733>
2020-04-25 16:15:48 +00:00
Connor Abbott
180f98678f ir3: Remove VARYING_SLOT_PNTC remapping hack
The st now does this for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4732>
2020-04-25 15:52:05 +00:00
Connor Abbott
662e9c1801 st/nir: Fix assigning PointCoord location with !PIPE_CAP_TEXCOORD
This was trying to emulate the effect of mapping GL -> TGSI -> NIR,
but failed to handle VARYING_SLOT_PNTC which led to a kludgy workaround
in freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4732>
2020-04-25 15:52:05 +00:00
Connor Abbott
a64d266134 freedreno/a6xx: Implement PrimID passthrough
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
2020-04-25 01:06:21 +00:00
Connor Abbott
a661d18a39 tu: Implement PrimID passthrough
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
2020-04-25 01:06:21 +00:00
Connor Abbott
1f9839907a ir3: Skip missing VS outputs in VS out map when linking
The hardware is capable of automatically filling in certain values in
the VPC without writing them from the last geometry stage, like
gl_PointCoord or gl_PrimitiveID when there is no GS. However, we *do*
have to enable these outputs (i.e. set the VPC_VAR_DISABLE bit to 0) as
VPC_VAR_DISABLE is really about FS inputs rather than VS outputs. To do
this, we move the computation of the enable bits to ir3_link_add(),
which is also a nice refactor anyway. In addition we detect the PrimID
case specifically so that the driver can program the location.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
2020-04-25 01:06:21 +00:00
Connor Abbott
cc530858c1 freedreno/a6xx: Document PrimID passthrough registers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
2020-04-25 01:06:21 +00:00
Joshua Ashton
0b44582394 radv: Pass logical device to si_emit_graphics
We'll need this in order to retrieve the va of a bo for a future ext.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4728>
2020-04-25 00:32:20 +00:00
Kristian H. Kristensen
bf542484ea freedreno/ir3: Print @tex write mask using 0x%x
That way we can parse it again with the assembler.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4741>
2020-04-25 00:03:43 +00:00
Kristian H. Kristensen
c801228f0d freedreno/ir3: Reset lex line number when we start parsing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4741>
2020-04-25 00:03:43 +00:00
Kristian H. Kristensen
34e7179dfa freedreno/ir3: Parse, but ignore @in, @out and @tex headers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4741>
2020-04-25 00:03:43 +00:00
Kristian H. Kristensen
da467817e3 freedreno/ir3: Move ir3 assembler to backend compiler
For easier reuse.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4741>
2020-04-25 00:03:43 +00:00
Kristian H. Kristensen
869d86e664 freedreno/computerator: Decouple ir3 assembler
Specifically, don't include ir3_asm.h in the parser as that's
computerator specific.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4741>
2020-04-25 00:03:43 +00:00
Andres Gomez
375c7a3863 Revert "meson,ci: Disable sparse_array tests on windows"
The Wine version in the build image has been upgraded.

This reverts commit 6be65b0777.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4678>
2020-04-24 20:01:31 +00:00
Andres Gomez
cb055c6ca4 gitlab-ci: install winehq-stable to get 5.0 instead of 4.0
Additionally, purge the winehq-stable package and its dependencies to
avoid crashing when building for s390x.

v2:
  - Remove winehq-stable and dependencies for s390x.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2657
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com> [v1]
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4678>
2020-04-24 20:01:31 +00:00
Marek Vasut
c8ccd63911 etnaviv: Fix depth stencil ops on GC880/GC2000
This patch fixes depth stencil ops on MX6S GC880 and MX6Q GC2000.
The following dEQPs now pass:
  dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.*
  dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.*
which is roughly 600 fixed dEQP tests.

The problem is that if the front-facing stencil has a value mask 0x00 and
the back-facing stencil has some non-zero value mask, then the stencil part
of the depth stencil buffer is written with 0x00 unconditionally. The blob
replicates the value mask of the back-facing stencil to the value mask of
the front-facing stencil to achieve correct rendering, replicate the same
behavior here.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4275>
2020-04-24 21:22:55 +02:00
Rhys Perry
5c5c2dd48f radv/aco: enable 8/16-bit storage and int8/int16 on GFX8+
With this, Doom Eternal should now run with ACO on GFX8+.

The generated 8/16-bit storage code is okay but the generated int8/int16
code is currently pretty bad but it works and apparently Doom Eternal
doesn't actually use it (even though it requires it).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4707>
2020-04-24 20:04:39 +01:00
Rhys Perry
eeccb1a941 aco: lower 8/16-bit integer arithmetic
dEQP-VK.spirv_assembly.type.* passes with the features and extensions
enabled.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4707>
2020-04-24 20:03:59 +01:00
Rhys Perry
bcd9467d5c aco: improve sub-dword emit_split_vector() with sgprs
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
a3dc1441f0 aco: clobber scc in s_bfe_u32 in get_alu_src()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
78389f4cbc aco: handle undef p_create_vector operands in the optimizer
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
deea4b7c5a aco: vectorize global loads/stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
7db7206631 aco: allow 8/16-bit shared loads
These should work now

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
48b7beb7b0 aco: add and use get_buffer_store_op() helper
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
936b70c8cf aco: refactor visit_store_scratch() to use new helpers
Should support 8/16-bit stores now

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
18817041f7 aco: refactor visit_store_global() to use new helpers
Should support 8/16-bit stores now

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
c7bd69b3ae aco: refactor visit_store_ssbo() to use new helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
f75c830433 aco: refactor store_vmem_mubuf() to use new helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
98b4cc7110 aco: refactor store_lds() to use new helpers
It should also work correctly for 8/16-bit stores

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
562353e1f1 aco: add helpers for splitting stores
split_store_data() splits a vector and p_as_uniforms it if needed.

scan_write_mask()/advance_write_mask() are similar to
u_bit_scan_consecutive_range(), but makes it easier to only clear part of
the range and will also give ranges for zero'd bits.

split_buffer_store() is a helper for splitting VMEM/SMEM stores.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
211a9f2057 aco: use emit_load helper for VMEM/SMEM loads
Also implements 8/16-bit loads for scratch/global.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
57e6886f98 aco: refactor load_lds to use new helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
542733dbbf aco: add emit_load helper
This helper is used for recombining split loads, passing the result to
p_as_uniform, aligning the offset down and shifting it right if needed and
handling large constant offsets.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
b77d638e1b aco: add and use RegClass::get() helper
Eventually, we'll probably want to replace the current
RegClass(type, size) constructor with this.

This has a functional change in that get_reg_class() now creates v1/v2
instead of v4b/v8b.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
69b92db131 aco: be more careful about using SMEM for load_global
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
03568249f9 radv: allocate larger shader memory slabs if needed
Fixes dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 hang with ACO
(features needed for the test are implemented in a later commit)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Rhys Perry
51363bd475 radv: align buffer descriptor sizes to dword
This is needed to prevent bounds checking issues when load 8/16-bit values
with dword loads.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>
2020-04-24 18:52:54 +00:00
Timur Kristóf
62ff2ff808 aco: Move s_setprio to correct place after the gs_alloc_req.
Previously the setprio was inside the branch, so it would only reset
the priority on the first wave, but not the others.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
277f37d036 aco: Use 24-bit multiplication for NGG wave id and thread id.
Both of them should always fit 24 bits anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
eafc1e7365 aco: Use 24-bit multiplication in TCS I/O
The TCS inputs and outputs must always fit into the LDS,
which implies that their addresses also always fit 24 bits.

On AMD GPUs, 24-bit multiplication is much faster than 32-bit
multiplication, so we can take the opportunity to use that
for TCS I/O instead.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
64332a0937 aco: Const correctness for aco_print_ir.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
0c0691d43e aco: Const correctness for get_barrier_interaction.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
f321dc33c8 aco: Abort when RA can't find a register.
Previously, it was just unreachable, which means it will generate
invalid shaders when it encounters a situation when it can't allocate
registers for eg. a large load.

This commit makes it slightly easier to notice such problems without
triggering a GPU hang.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
f2e7aee244 aco: Increase barrier_count to 7 to include barrier_barrier.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
25775d346c aco: Only store TCS outputs to VMEM when they are read by TES.
Totals from affected shaders (GFX10):
Code Size: 10832 -> 10736 (-0.89 %) bytes

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Timur Kristóf
b779d05d71 radv: Add inputs read by TES to radv_shader_info.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4536>
2020-04-24 17:58:57 +00:00
Jonathan Marek
c3ef0275c4 turnip: add adreno 650
Tile alignment is 96, with gmem alignment of 0x6000

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4608>
2020-04-24 17:42:01 +00:00
Jonathan Marek
aa3624b8ab turnip: use RESOLVE_TS event
This is required on a650 to flush the GMEM store.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4608>
2020-04-24 17:42:01 +00:00
Jonathan Marek
f81e56c9a0 turnip: remove unused RB_UNKNOWN_8E04_blit
New blit code doesn't change this value, and different values seem to be
related to the driver version and not the GPU version.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4608>
2020-04-24 17:42:01 +00:00
Mike Blumenkrantz
c683138689 zink: set UBO alignments in nir_intrinsic_load_uniform lowering
resolves this error
  error: nir_intrinsic_align_offset(instr) < nir_intrinsic_align_mul(instr) (../src/compiler/nir/nir_validate.c:582)
in ext_packed_depth_stencil-readdrawpixels piglit test

port of f5b14d983e

Fixes: fb64954d9d ("nir: Validate that memory load/store ops work on whole bytes")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4711>
2020-04-24 17:27:30 +00:00
Fritz Koenig
155033bbb3 freedreno: allow FMT6_8_UNORM as a UBWC format
FMT6_8_UNORM is necessary for NV12 textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4722>
2020-04-24 17:10:39 +00:00
Jason Ekstrand
9c2a11430e spirv: Rewrite CFG construction
This commit completely rewrites the way we extract a structured CFG from
SPIR-V.  The new approach is different in a few ways:

 1. It does a breadth-first search instead of depth-first.  This means
    that we've visited the merge node for a construct before we visit
    any of the nodes inside the construct.  This makes it easier to
    validate things like loop and switch nesting.

 2. We record more information in the CFG.  Earlier commits added a
    parent pointer to vtn_cf_node but we now record all of the merge and
    other special blocks for each CFG node.  This lets us validate
    things more precisely.

 3. It makes heavy use of merge blocks for walking the CFG.  Previously,
    we sort of used them as hints for trying to guess the CFG structure
    but things got dicey whenever a merge was missing.  We had some
    heuristics for how to handle short-circuiting if statements but it
    was a bunch of special cases.

    Now, we make them a fundamental part of walking the CFG.  When we
    encounter a control-flow construct, we add the body components of
    the construct to the BFS work list and then jump to the merge block
    if one exists to continue scanning the current CFG nesting level.
    If no merge block exists, we assume that means that control-flow
    never re-converges in a normal way and that the only way to get back
    to normality is with a direct jump such as a loop break or continue.
    This should make things far more robust when trying to deal with the
    more creative placement (or lack thereof) of merge instructions.

Reviewed-by: Alan Baker <alanbaker@google.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
Closes: #2760
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4446>
2020-04-24 16:29:24 +00:00
Jason Ekstrand
80ffbe915f anv: Add support for HiZ+CCS
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
752eefdb3d intel/isl: Refactor isl_surf_get_ccs_surf
This refactor breaks out a new isl_surf_supports_ccs function which does
most of the validity checking.  The isl_surf_get_ccs_surf function calls
this function and then dives right into constructing the CCS aux_surf.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
3eb1993625 intel/isl: Delete a misleading comment
Untyped messages are only use on Gen9+ for UBOs and SSBOs.  They will
never be used on anything using an isl_surf.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
483a1d5e6c anv/cmd_buffer: Move anv_image_init_aux_tt higher
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
65e541ab16 anv: Simplify a case in layout_to_aux_usage
If it's depth, the only possible value of planes[plane].aux_usage is
ISL_AUX_USAGE_HIZ at least right now.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
5cb6c5d11d intel/blorp: Allow more HiZ usages in hiz_clear_depth_stencil
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
0d91dae7f0 anv: Generalize some aux usage checks
For the checks dealing with fast-clear values, we change them to check
for the depth aspect because the distinction there really is between
color and depth more than between HiZ and CCS.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:45 +00:00
Jason Ekstrand
86ded00c40 anv/blorp: Do less hard-coding of aux usages
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:44 +00:00
Jason Ekstrand
54b525caf0 anv: Rework anv_layout_to_aux_state
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:44 +00:00
Jason Ekstrand
eb0cede586 anv: Be more conservative about image view usage
We were ORing together the image and stencil usage rather than actually
following the formula in the spec.  This can lead to assertions in other
parts of the driver if we're not careful.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:44 +00:00
Jason Ekstrand
d2f3576d33 anv: Move vk_image_layout_is_read_only higher
While we're at it, we drop some _KHR suffixes

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:44 +00:00
Jason Ekstrand
5de9f4409a anv: Add a vk_image_layout_to_usage_flags helper
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
2020-04-24 16:17:44 +00:00
Rafael Antognolli
e3ab86c599 anv: Enable HiZ on multi-layer depth buffers.
Improves The Witcher 3 fps by 2-10% on ICL (depending on the configs and
system).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4661>
2020-04-24 15:14:59 +00:00
Christian Gmeiner
709f26c47d etnaviv: support for using generic blit path
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1641>
2020-04-24 13:51:28 +00:00
Christian Gmeiner
b043c40edd etnaviv: call util_blitter_save_fragment_constant_buffer_slot(..)
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1641>
2020-04-24 13:51:28 +00:00
Christian Gmeiner
e731740388 etnaviv: drop default state for FE_HALTI5_ID_CONFIG
It gets emitted when needed - see emit_halti5_only_state(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4729>
2020-04-24 13:39:58 +00:00
Christian Gmeiner
4b0a732db3 docs/features: mark GL_ARB_texture_filter_anisotropic as done for etnaviv
Needs GPUs with HALT0.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4725>
2020-04-24 13:36:56 +00:00
Jonathan Marek
73f7f73ef3 freedreno/ir3: fix incorrect conversion folding
Fixes dEQP-VK.glsl.builtin.function.pack_unpack.unpackhalf2x16_compute

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4708>
2020-04-24 13:11:58 +00:00
Jonathan Marek
dd49a40410 freedreno/ir3: set even bit for f2f16_rtne
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4708>
2020-04-24 13:11:58 +00:00
Jonathan Marek
edc35c1f54 freedreno/ir3: fix 16-bit ssbo access
Update cat6 instruction type, and shift 1 in lower_offset_for_ssbo.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4708>
2020-04-24 13:11:58 +00:00
Rhys Perry
ede1c171c5 aco: fix outdated label_vec from p_create_vector labelling
Fixes random dEQP-VK.transform_feedback.fuzz.* crashes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 2dc550202e
    ('aco: copy-propagate p_create_vector copies of vectors')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4730>
2020-04-24 12:21:15 +00:00
Jason Ekstrand
fdf9b674ee nir/lower_subgroups: Mask off unused bits in ballot ops
Thanks to VK_EXT_subgroup_size_control, we can end up with
gl_SubgroupSize being as low as 8 on Intel.

Fixes: d10de25309 "anv: Implement VK_EXT_subgroup_size_control"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4694>
2020-04-24 11:37:03 +00:00
Jason Ekstrand
9c009da208 anv: Drop an assert
Ever since Vulkan 1.2, this feature has been in core so enabling the
extension is no longer required.

Fixes: 4ef3f7e3d3 "anv: Enable Vulkan 1.2 support"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4694>
2020-04-24 11:37:03 +00:00
Marek Olšák
b520a58cc1 radeonsi: use pipe_blend_state::max_rt to update fewer blend registers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
2020-04-24 10:38:55 +00:00
Marek Olšák
b4fd8f1919 ac,radeonsi: simplify checking for Navi1x chips
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
2020-04-24 10:38:54 +00:00
Marek Olšák
d8443b211e ac: out-of-order rasterization is not supported on gfx10
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
2020-04-24 10:38:54 +00:00
Jonathan Marek
e43fc003e0 turnip: divide cube map depth by 6
This matches the GL driver and fixes these tests:

dEQP-VK.glsl.texture_functions.query.texturesize.samplercubearray*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4709>
2020-04-24 10:24:55 +00:00
Jason Ekstrand
bc5c438289 spirv: Fix passing combined image/samplers through function calls
Fixes dEQP-VK.spirv_assembly.instruction.function_params.sampler_param

cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4684>
2020-04-24 09:43:21 +00:00
Jason Ekstrand
a1a08a5802 nir/opt_deref: Remove certain sampler type casts
The SPIR-V parser sometimes generates casts from specific sampler types
like sampler2D to the bare sampler type.  This results in a cast which
causes heartburn for drivers but is harmless to remove.

cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4684>
2020-04-24 09:43:21 +00:00
Jason Ekstrand
f4addfdde3 spirv: Use nir_const_value for spec constants
When we originally wrote spirv_to_nir we didn't have a good scalar value
union to handily use so we rolled our own thing for spec constants.  Now
that we have nir_const_value, we can use that and simplify a bunch of
the spec constant logic.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4675>
2020-04-24 09:23:59 +00:00
Jason Ekstrand
6211e79ba5 turnip: Properly handle all sizes of specialization constants
cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4675>
2020-04-24 09:23:59 +00:00
Jason Ekstrand
a4885df9f8 radv: Properly handle all sizes of specialization constants
cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4675>
2020-04-24 09:23:59 +00:00
Jason Ekstrand
a44e63398b anv: Properly handle all sizes of specialization constants
Closes: #2812
cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4675>
2020-04-24 09:23:59 +00:00
Jason Ekstrand
64e4297629 spirv: Allow constants and NULLs in SpvOpConvertUToPtr
We were accidentally asserting that the value had to be a vtn_ssa_value
which isn't true if it, for instance, comes from a spec constant.

Fixes: fb282a68bc "spirv: Implement OpConvertPtrToU and OpConvertUToPtr"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4675>
2020-04-24 09:23:59 +00:00
Eduardo Lima Mitev
4dc7b76276 anv/radv: Resolving 'GetInstanceProcAddr' should not require a valid instance
Since vk_icdGetInstanceProcAddr() is wired through
vkGetInstanceProcAddr() in both drivers, we lost the ability for
'GetInstanceProcAddr' to resolve itself prior to having a valid
instance.

An upcoming spec change will fix that and allow
vkGetInstanceProcAddr() to resolve itself passing NULL as
instance. See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
for details.

This patch implements the change in both radv and anvil.

CTS changes have already landed:
https://gitlab.khronos.org/Tracker/vk-gl-cts/issues/2278

vulkan-loader changes have also landed:
https://gitlab.khronos.org/Tracker/vk-gl-cts/issues/2278

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4273>
2020-04-24 09:09:14 +00:00
Rhys Perry
665250e830 aco: fix v_or(s_lshl) and v_add(s_lshl) optimizations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: d1621834f3
    ('aco: combine VALU and SALU into various VOP3 instructions')

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2822
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4717>
2020-04-24 08:55:19 +00:00
Timothy Arceri
58b8fbb824 glsl: remove some duplicate code from the nir uniform linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4721>
2020-04-24 08:31:01 +00:00
Timothy Arceri
ffbec55072 glsl: some nir uniform linker fixes
This fixes find_and_update_named_uniform_storage() for subroutines
and also updates num_shader_uniform_components for non opaque
uniforms.

The following patch will ensure this type of bug won't happen again.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4721>
2020-04-24 08:31:01 +00:00
Lionel Landwerlin
9df1d92bbd drm-shim: stub syncobj wait ioctl
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4726>
2020-04-24 10:19:43 +03:00
Lionel Landwerlin
53f151f422 drm-shim: provide a valid fake syncobj handle at creation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4726>
2020-04-24 10:19:43 +03:00
Quentin Glidic
00f5ea9fdc meson: Use dependency.partial_dependency()
It avoids calling pkg-config which was searched for in a wrong way, thus
breaking setup where unprefixed pkg-config was banned (e.g. on Exherbo).

Signed-off-by: Quentin Glidic <sardemff7+git@sardemff7.net>
Fixes: 53f9131205
       ("meson: fix getting cflags from pkg-config")

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4701>
2020-04-24 06:58:32 +00:00
Christian Gmeiner
7aaa0e5908 etnaviv: add anisotropic filter support
I have not seen any usage of TEXTURE_FILTER_ANISOTROPIC in the cmd streams
from the binary blob. Maybe it gets used on some model/rev combinations.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2888>
2020-04-24 06:46:00 +00:00
Christian Gmeiner
1d4c191572 etnaviv: update headers from rnndb
Update to etna_viv commit b40ec2a.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2888>
2020-04-24 06:46:00 +00:00
Christian Gmeiner
7d77295515 etnaviv: anisotropic filtering is supported starting with HALTI0
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2888>
2020-04-24 06:46:00 +00:00
Caio Marcelo de Oliveira Filho
7ee9f851e2 spirv: Update the headers from latest Khronos master
This corresponds to 2ad0492fb00919d99500f1da74abf5ad3c870e4e ("Discuss
generator magic number reservations.")  in
https://github.com/KhronosGroup/SPIRV-Headers.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4682>
2020-04-24 05:56:05 +00:00
Caio Marcelo de Oliveira Filho
5620c3efd8 spirv: Handle instruction aliases in vtn_gather_types
Same solution as done in spirv_info generation.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4682>
2020-04-24 05:56:05 +00:00
Tomeu Vizoso
8cba1a13fa gitlab-ci: Test Virgl with traces
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4659>
2020-04-24 05:37:06 +00:00
Tomeu Vizoso
5a5316ee1b gitlab-ci: Test OpenGL ES 3.1 on virgl
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4659>
2020-04-24 05:37:06 +00:00
Tomeu Vizoso
9b7c20b315 gitlab-ci: Allow test jobs to add options to the dEQP invocation
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4659>
2020-04-24 05:37:06 +00:00
Tomeu Vizoso
34ed5fff5b gitlab-ci: Update virglrenderer in the x86_test-gl image
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4659>
2020-04-24 05:37:06 +00:00
Alyssa Rosenzweig
a3d2936a8e panfrost: The texture descriptor has a pointer to a trampoline
Not to the texture itself, and can have a stride right after for linear
textures.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:55:05 +02:00
Alyssa Rosenzweig
36d49b1fb1 panfrost: Identify texture layout field
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:55:02 +02:00
Alyssa Rosenzweig
ad4024968e pan/decode: Remove is_zs weirdness
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:54:36 +02:00
Tomeu Vizoso
e41894ba15 panfrost: Emit texture descriptor on bifrost
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:42 +02:00
Tomeu Vizoso
d3eb23adb5 panfrost: Emit sampler descriptor on bifrost
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:39 +02:00
Alyssa Rosenzweig
497977bbe6 panfrost: decode textures and samplers on bifrost
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:34 +02:00
Alyssa Rosenzweig
0167391a1a panfrost: Add tentative bifrost_texture_descriptor
It looks very similar to the Midgard texture descriptor, just with a
bunch of fields moved around and the whole descriptor flattened (so
basically just memory access optimizations, from what I can tell).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:30 +02:00
Alyssa Rosenzweig
81a31911dd panfrost: Set clear_color_[12] in the extra fb desc
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:26 +02:00
Tomeu Vizoso
0a0b670d63 panfrost: Clean up a bit the tiler structs for Bifrost
And set a fixed hierarchy mask for now that seems to generally work.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4680>
2020-04-24 06:53:21 +02:00
Eric Anholt
0d6019302e vc4: Use NIR shader's num_outputs for generating our new output.
Simplifies the code (we don't have struct or matrix varyings that would
have previously made this code break), and makes sure we keep
s->num_outputs accurate.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Eric Anholt
5593d80a2c freedreno/ir3: Fix sizing of the inputs/outputs array.
If you have a struct, the var's base driver location is not the last
driver location that will be accessed in that var.  We have a shader
struct member with this number for us, already.  Fixes overflows in:

dEQP-GLES31.functional.program_interface_query.program_output.type.interface_blocks.out.named_block_explicit_location.struct.mat3x2

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Eric Anholt
ac937bf878 freedreno/ir3: Fix driver_location of the added vertex_flags varying.
It was ignoring the sizes of the output variables and assuming
single-slot, and failing to update num_outputs.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Eric Anholt
e82ce1852a gallium: Fix setup of pstipple frag coord var.
If the last input was a struct or matrix, we would have overlapped driver
locations for our new position var.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Eric Anholt
035fd4fb9f nir/lower_clip: Fix picking of unused driver locations.
This fixes things when the last input/output is a struct or matrix.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Eric Anholt
91668ae839 nir/lower_two_sided_color: Fix picking of new driver location.
We have shader->num_inputs for "last used input + 1" already, which
respects struct/matrix varyings.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4670>
2020-04-23 18:52:46 +00:00
Gert Wollny
49ce749d0e nir: Add umad24 and umul24 opcodes
So far only the singed versions are defined.

v2: Make umad24 and umul24 non-driver specific (Eric Anholt)

v3: Take care of nir_builder and automatic lowering of the
    opcodes if they are not supported by the backend.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4610>
2020-04-23 18:23:04 +00:00
Gert Wollny
42aa348dad nir: Add r600 specific intrinsics for tesselation shader IO
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4610>
2020-04-23 18:23:04 +00:00
Eric Anholt
e9add0c501 drm-shim: Let the driver choose to overwrite the first render node.
When I was writing drm-shim, I was focused on the v3d kmsro case -- use my
intel device as the kmsro display device and add on a simulator-based v3d
device that we could render with.  But for the noop backends we use for
shader-db, it's a lot more useful to just overwrite the first render node
in the system so that you don't have to pass a -d <how many render nodes I
already have in my system> argument.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4664>
2020-04-23 17:54:54 +00:00
Eric Anholt
5a8718f01b freedreno: Make the slice pitch be bytes, not pixels.
Back in a2xx, HW pitches were in pixels, so storing that was reasonable.
Ever since then, the HW wants pitches in bytes, and we have only one
instance of using pitch in pixels in the code (a3xx sysmem path).

Flip things around so that only a2xx has to worry about the cpp for
looking at pitches.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4558>
2020-04-23 16:37:50 +00:00
Eric Anholt
bd76a24fd1 freedreno: Introduce a "cpp_shift" value for cpp divs/muls.
This only converts part of the driver to use it, leaving the rest to the
following commit (which inspired this one).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4558>
2020-04-23 16:37:50 +00:00
Samuel Pitoiset
6a6e71524d radv: adjust the supported subgroup stages
VK_SHADER_STAGE_ALL now includes all ray-tracing related stages.
Noticed while comparing vulkaninfo with some other drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4679>
2020-04-23 16:16:09 +00:00
Lionel Landwerlin
efdb7fa9a8 anv: force whole EU array to be powered for perf queries
Because of functional requirements for Gen11, when perf is enabled we
only power half the EU array.

This change forces it to enable everything.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4021>
2020-04-23 15:55:59 +00:00
Lionel Landwerlin
a7998371ed intel/perf: specify sseu configuration when supported
Because of functional requirements for Gen11, when perf is enabled we
only power half the EU array.

This change forces it to enable everything.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4021>
2020-04-23 15:55:59 +00:00
Lionel Landwerlin
8f152ed101 intel/perf: store default sseu configuration
This is the powergating configuration of the EU array. The default is
everything powered.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4021>
2020-04-23 15:55:59 +00:00
Lionel Landwerlin
ea8cb79742 include/drm-uapi: bump headers
From drm-next at the following commit :

  commit 1aa63ddf726ea049279989b93b69b57ce6efd75b
  Merge: 774f1eeb18b0 14d0066b8477
  Author: Dave Airlie <airlied@redhat.com>
  Date:   Wed Apr 22 10:40:34 2020 +1000

      Merge tag 'drm-misc-next-2020-04-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4021>
2020-04-23 15:55:59 +00:00
Samuel Pitoiset
ff3f775476 radv: simplify checking for Navi1x chips
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4702>
2020-04-23 15:54:32 +02:00
Rhys Perry
0d9fe0405f aco: improve code for 32-bit isign
No shader-db changes on Navi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4667>
2020-04-23 12:39:33 +00:00
Rhys Perry
d1621834f3 aco: combine VALU and SALU into various VOP3 instructions
shader-db (Navi):
Totals from 2916 (2.28% of 127638) affected shaders:
SGPRs: 184427 -> 184283 (-0.08%); split: -0.10%, +0.02%
VGPRs: 143520 -> 143640 (+0.08%); split: -0.00%, +0.09%
CodeSize: 14913548 -> 14913288 (-0.00%); split: -0.00%, +0.00%
MaxWaves: 26034 -> 26012 (-0.08%)
Instrs: 2935435 -> 2930960 (-0.15%); split: -0.15%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4667>
2020-04-23 12:39:33 +00:00
Rhys Perry
607fb4153d aco: move call to store_output_to_temps in store_ls_or_es_output earlier
Skips get_intrinsic_io_basic_offset()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4667>
2020-04-23 12:39:33 +00:00
Rhys Perry
b497b774a5 aco: remove copy in load_input_from_temps()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4667>
2020-04-23 12:39:33 +00:00
Rhys Perry
2dc550202e aco: copy-propagate p_create_vector copies of vectors
Instead of copying the operands of the other p_create_vector and labelling
the definition with label_vec, copy the operands and label it with
label_temp so that it can be copy-propagated.

This was found while removing a redundant copy in load_input_from_temps()
which removed duplicate p_create_vector instructions.

shader-db (Navi):
Totals from 139 (0.11% of 127638) affected shaders:
VGPRs: 8472 -> 7948 (-6.19%)
CodeSize: 514592 -> 512368 (-0.43%)
MaxWaves: 1089 -> 1195 (+9.73%)
Instrs: 100214 -> 99658 (-0.55%)
Cycles: 400856 -> 398632 (-0.55%)
VMEM: 15545 -> 15338 (-1.33%)
Copies: 5140 -> 4584 (-10.82%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4667>
2020-04-23 12:39:33 +00:00
Rhys Perry
e4383b5c7f aco: decrease the uses of other copy operations after splitting/removing
For copies like v[7:8] = v[8:9], what currently happens is:
- do_copy() will skip the second dword
- the uses of the second dword will be reduced to 0
- the copy operation will be removed from the map
and v8 will never be set to v9.

So just decrease the uses of other operations after splitting or removing
the current operation, so: "v8 = v9" will be split off, it's uses reduced
and then the new copy will be done in the next iteration.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4686>
2020-04-23 11:39:23 +00:00
Erik Faye-Lund
7f17a0a809 meson: correct windows-version define
The macro "_WINVER" does nothing, the macro definitions that matter for
windows API version selection are "_WIN32_WINNT" and "WINVER".

The header "sdkddkver.h" (which is included from thousands of
different windows-headers) defines "WINVER" to the same value as
"_WIN32_WINNT" of only the latter is defined, which explains why this
works right now. But we shouldn't depend on that kind of luck, and
instead define the right maco.

Fixes: 3aee462781 ("meson: add windows compiler checks and libraries")
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4681>
2020-04-23 11:19:52 +00:00
Rhys Perry
32d871b48f nir/algebraic: don't undo lowering of 8/16-bit comparisons to 32-bit
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4387>
2020-04-23 10:57:38 +00:00
Rhys Perry
6d79298992 nir/lower_bit_size: fix lowering of {imul,umul}_high
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4387>
2020-04-23 10:57:38 +00:00
Rhys Perry
715ef95700 nir/lower_bit_size: fix lowering of shifts
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4387>
2020-04-23 10:57:38 +00:00
Joshua Ashton
58f25098a0 radv: Use TRUNC_COORD on samplers
The default behaviour (0) is: "round-nearest-even to n.6 and drop fraction when point sampling" whereas the Vulkan spec simply wants us to floor it (1) "truncate when point sampling".

See 15.6.1 in the Vulkan spec.
https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#textures-normalized-operations

The Direct3D spec also mandates this (https://microsoft.github.io/DirectX-Specs/d3d/archive/D3D11_3_FunctionalSpec.htm#7.18.7%20Point%20Sample%20Addressing)

This fixes some point-sampling texture precision issues in some Direct3D 9 titles such as Guild Wars 2 and htoL#NiQ: The Firefly Diary that are not present on other vendors.

Fixes dEQP-VK.pipeline.sampler.exact_sampling.*

https://github.com/Joshua-Ashton/d9vk/issues/450
https://github.com/doitsujin/dxvk/issues/1433

CC: <mesa-stable@lists.freedesktop.org>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3951>
2020-04-23 09:57:08 +00:00
Samuel Pitoiset
7086b38c81 radv: make sure to export the viewport index if FS needs it
If FS reads gl_ViewportIndex but VS doesn't export it, it should
be zero to avoid reading garbage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2818
Fixes: b424d49ac0 ("radv/llvm: fix exporting the viewport index if the fragment shader needs it")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4687>
2020-04-23 08:10:25 +00:00
Indrajit Kumar Das
133efa112d radeonsi: enable support for AlphaToCoverageDitherControlNV
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
2020-04-23 12:02:56 +05:30
Indrajit Kumar Das
ede36a2efe mesa: add support for AlphaToCoverageDitherControlNV
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
2020-04-23 12:02:45 +05:30
Indrajit Kumar Das
d82f057218 gallium: prepare framework for supporting AlphaToCoverageDitherControlNV
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
2020-04-23 11:58:49 +05:30
Hyunjun Ko
227df2a2ba turnip: Fix crashes when geometry shader constants aren't used
Fixes dEQP-VK.transform_feedback.fuzz.2_level_array.float.geometry, for
example.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4693>
2020-04-23 05:19:04 +00:00
Rob Clark
85f84ea148 gallium: add # of MRT to blend state
To make it possible for drivers to avoid unnecessary blend state change
for unused MRTs.  Otherwise the driver would have to manage different
blend CSOs for different potential #s of render targets.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4619>
2020-04-23 04:49:52 +00:00
Rob Clark
b88778e2de mesa/st: avoid u_vbuf for GLES
64b VBO types are not required for GLES.  So avoid u_vbuf if that was
otherwise the only reason it was used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4619>
2020-04-23 04:49:52 +00:00
Rob Clark
7e1b57a6d9 mesa: avoid redundant VBO updates
Avoids re-emitting unchanged VBO state, which is a big chunk of the
state updates in gfxbench driver2

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4619>
2020-04-23 04:49:52 +00:00
Kenneth Graunke
155bb74ea9 nir: Actually do load/store vectorization beyond vec2
nir_opt_load_store_vectorize has an is_strided_vector() function that
looks for types with weird explicit strides.  It does so by comparing
the explicit stride against the type-size-derived typical stride.

This had a subtle bug.  Simple vector types (vec2/3/4) have no explicit
stride, so glsl_get_explicit_stride() returns 0.  This never matches the
typical stride for a vector, so is_strided_vector() would return true
for basically any vector type, causing the vectorizer to bail.

I found this by looking at a compute shader with scalar SSBO loads at
offsets 0x220, 0x224, 0x228, 0x22c.  nir_opt_load_store_vectorize would
properly vectorize the first two into a vec2 load, but would refuse to
extend it to a vec3 and ultimately vec4 load because is_strided_vector()
saw a vec2 and freaked out.

Neither ACO nor ANV do load/store vectorization before lowering derefs,
so this shouldn't affect them.  However, I'd like to fix this bug to
avoid the trap for anyone who decides to in the future.  In a branch
where anv used this lowering, this cut an additional 38% of the send
messages in the shader by properly vectorizing more things.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4255>
2020-04-22 21:22:36 -07:00
Simon Zeni
51c1c4d95a mesa: enable GL_EXT_draw_instanced for gles2
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3204>
2020-04-23 03:56:03 +00:00
Hyunjun Ko
0edff5123c turnip: Skip unused regs when setting up streamout buffers
Fixes: 374406a7c4

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Brian Ho <brian@brkho.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4604>
2020-04-23 01:14:19 +00:00
Hyunjun Ko
e892733b80 turnip : Fix wrong offset calculation for xfb buffer.
In vulkan, offsets are already provided through the api
vkCmdBindTransformFeedbackBuffersEXT, so this is duplicated
calculation.

Fixes : 9ff1959ca5

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Brian Ho <brian@brkho.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4604>
2020-04-23 01:14:19 +00:00
Hyunjun Ko
e34b0d65f9 turnip: Implement and enable VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
Tested by
dEQP-VK.transform_feedback.simple.query*

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Brian Ho <brian@brkho.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4604>
2020-04-23 01:14:19 +00:00
Hyunjun Ko
aff02dd76b turnip: make the struct slot_value of queries get 2 values
In case of transform feedback query, it writes two integer values,
which one is for primitives written and another is for primitives
generated.

To handle this, the second member of the struct slot_value is worth
to be presented not as a padding.

In addition, we also need to modify get/copy_result to access both
values.

This patch is the prep work for the transform feedback query support.

Tested with
dEQP-VK.pipeline.timestamp.*
dEQP-VK.query_pool.occlusion_query.*

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Brian Ho <brian@brkho.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4604>
2020-04-23 01:14:19 +00:00
Kenneth Graunke
259cae4442 intel/compiler: Don't create 64-bit src1 immediates in opt_peephole_sel
64-bit immediates are only allowed as src0.  Long ago, we decided to
avoid constructing such illegal situations in the IR, rather than
allowing them in the IR but then promoting bogus immediates to GRFs
later.  So, we need to fix opt_peephole_sel to not put 64-bit immediates
as src1 of the new SEL instruction.

Fixes: a4b36cd3dd ("intel/fs: Coalesce when the src live range is contained in the dst")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2816
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4692>
2020-04-23 00:53:14 +00:00
Kenneth Graunke
4459a70a6e intel/compiler: Delete abs/neg handling in fsign code
This should have gone away when removing source modifiers.  They won't
be set any longer, so this is simply dead code.

Fixes: b7c47c4f7c ("intel/compiler: Drop nir_lower_to_source_mods() and related handling.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4691>
2020-04-22 17:04:37 -07:00
Kenneth Graunke
220f0e10d8 intel/compiler: Don't copy prop source mods into PICK_HIGH_32BIT
VEC4_OPCODE_PICK_HIGH_32BIT performs 32-bit UD access on a 64-bit DF
value.  abs and negate make sense on DF, but break entirely when
trying to access pieces of the value as unsigned integer dwords.

Fixes an fsign Piglit test on Ivybridge:
tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-sign-neg-abs

It had regressed when I removed nir_lower_to_source_modifiers, as that
caused us to start generating different code which provoked this bug.

Fixes: b7c47c4f7c ("intel/compiler: Drop nir_lower_to_source_mods() and related handling.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2817
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4691>
2020-04-22 17:03:18 -07:00
Dylan Baker
be33cf8ad0 docs: update calendar, add news item, and link releases notes for 20.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4688>
2020-04-22 22:10:31 +00:00
Dylan Baker
defc6400e1 docs: Add sha256 sums for 20.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4688>
2020-04-22 22:10:31 +00:00
Dylan Baker
c790e1c642 docs: Add relnotes for 20.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4688>
2020-04-22 22:10:31 +00:00
Alejandro Piñeiro
ad460c5dd6 v3d: support for textureQueryLOD
Fixes all the ARB_texture_query_lod piglit tests, and needed to get
the Vulkan CTS textureQueryLOD passing with the ongoing Vulkan driver.

Note that LOD Query bit flag became only available on V42 of the hw,
but the v3d40_tex is using V41 as reference. In order to avoid setting
up the infrastructure to support both v41 and v42, we manually set the
bit if the device version is the correct one.

We also fix how the ARB_texture_query_lod (so EXT_texture_query_lod)
is exposed. Before this commit it was always exposed (wrongly as it
was not really supported). Now it is exposed for devinfo.ver >= 42.

v2: move _need_sampler helper to nir.h (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4677>
2020-04-22 23:43:23 +02:00
Alejandro Piñeiro
9fd180394b nir: add nir_tex_instr_need_sampler helper
That is basically nir_tex_instr sampler_index documentation comment
expressed as a helper.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4677>
2020-04-22 23:43:18 +02:00
Alejandro Piñeiro
41bfd0812b v3d/packet: fixing TMU_Config_Parameter_2 definition
v41 interchanged the size and start values for the Padding, and it
seems that v42 inherited it when adding the LOD Query bit.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4677>
2020-04-22 23:39:41 +02:00
Alejandro Piñeiro
9967c26ae6 v3d/tex: Configuration Parameter 1 can be only skipped if P2 can be skipped too
Configuration Parameter packets 1 and 2 are pointed as optional, but
it is not clearly stated if you can skip only P1 when P2 is needed.

In the practice, it seems that the situation P0 - non-P1 - P2 can
causes problems, and at least on the simulator, it seems that sampler
info are attempted to be accessed. So let's just be conservative, and
only skip P1 configuration if we can skip P2 configuration too.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4677>
2020-04-22 23:39:34 +02:00
Alejandro Piñeiro
d0b644d9f9 v3d/tex: don't configure tmu config 1 if not needed
TMU configuration parameter 1 configures the sampler for the texture
operation. But there are some texture operations that doesn't need a
sampler. Skipping the configuration could provide a small perf
improvement on OpenGL. On the incoming Vulkan driver, would allow us
to avoid to set up an unneeded sampler.

Note that we still need to add the sampler configuration parameter if
the output is a 32bit, as it is on the sampler where we configure that
info.

Also, note that for images this is done comparing against a unpacked
p1 default. But in order to do that it is needed to go through the
code that fills up the unpacked p1. We can skip that too.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4677>
2020-04-22 23:38:18 +02:00
Jonathan Marek
c552b5fd1d turnip: implement VK_EXT_sampler_filter_minmax
Passes dEQP-VK.pipeline.sampler.view_type.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4662>
2020-04-22 20:12:14 +00:00
Jonathan Marek
a77e2ac835 turnip: enable cube arrays
Passes dEQP-VK.pipeline.sampler.view_type.cube_array.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4663>
2020-04-22 19:57:20 +00:00
Jonathan Marek
9daeb50454 turnip: implement VK_EXT_filter_cubic
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4672>
2020-04-22 19:03:58 +00:00
Jonathan Marek
a92d2e1109 turnip: implement VK_EXT_sample_locations
Passes tests in:

dEQP-VK.pipeline.multisample.sample_locations_ext.*

Note that these tests fail because of gl_PrimitiveID not working correctly:

dEQP-VK.pipeline.multisample.sample_locations_ext.verify_location.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4665>
2020-04-22 18:46:46 +00:00
Jonathan Marek
83b2f1d8cf turnip: set shader key msaa field
Fixes per-sample interpolation.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4665>
2020-04-22 18:46:46 +00:00
Daniel Schürmann
36e0d2f39b aco: coalesce v_mad's accumulator with definition's affinities
Totals from affected shaders:
Code Size: 8922676 -> 8915192 (-0.08 %) bytes

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
d000d76f13 aco: use upper part of gap in register file if it is beneficial for striding
Totals from affected shaders:
SGPRS: 1717288 -> 1716984 (-0.02 %)
VGPRS: 1305924 -> 1304904 (-0.08 %)
Code Size: 138508892 -> 138420144 (-0.06 %) bytes
Max Waves: 115726 -> 115735 (0.01 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
d666d83be2 aco: try to always find a register with stride for even sizes
Totals from affected shaders:
SGPRS: 1162400 -> 1162400 (0.00 %)
VGPRS: 947364 -> 946960 (-0.04 %)
Code Size: 98399300 -> 98399004 (-0.00 %) bytes
Max Waves: 74665 -> 74682 (0.02 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
5a3c1f4f0b aco: stop get_reg_simple after reaching max_used_gpr
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
2796cb4c24 aco: refactor get_reg_simple() to return early on exact matches
in the best fit algorithm

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
6792e134f3 aco: don't create vector affinities for operands which are not killed or are duplicates
Totals from affected shaders:
SGPRS: 825184 -> 825184 (0.00 %)
VGPRS: 697640 -> 697240 (-0.06 %)
Code Size: 79244104 -> 79201072 (-0.05 %) bytes
Max Waves: 42388 -> 42386 (-0.00 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
edc2b57ac1 aco: allocate full register for subdword definitions if HW doesn't support it
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
97a870cf88 aco: move attempt to find strided register into get_reg_simple()
This simplifies code and helps some shaders

Totals from affected shaders:
Code Size: 51227172 -> 51202216 (-0.05 %) bytes
Max Waves: 19955 -> 19948 (-0.04 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
c7f97f110c aco: use DefInfo in more places to simplify RA
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
734f86db6b aco: create and use DefInfo struct in RA
for maintaining all information necessary to find a register.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
5b2f628da3 aco: create pseudo dummy instruction in RA to be used for live-range splits
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
d9f7d1d5cb aco: refactor get_reg() to also handle affinities
This simplifies definition handling and
helps a few shaders

Totals from affected shaders:
Code Size: 659540 -> 659376 (-0.02 %) bytes

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:23 +00:00
Daniel Schürmann
7c8f4ebca9 aco: refactor get_reg() to take Temp instead of RegClass
This patch also moves get_reg_specified() and
get_reg_vec() before get_reg() to make use of it later.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:22 +00:00
Daniel Schürmann
0a9ed98178 aco: simplify operand handling in RA
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4573>
2020-04-22 18:23:22 +00:00
Jonathan Marek
a5cce95280 turnip: enable VK_FORMAT_S8_UINT as stencil format
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4588>
2020-04-22 17:45:33 +00:00
Jonathan Marek
44c6c145da turnip: improve GMEM load/store logic
Determine load/store at renderpass creation time.

This also fixes behavior with S8_UINT.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4588>
2020-04-22 17:45:33 +00:00
Jonathan Marek
e72201c787 turnip: disable depth test for S8_UINT attachment
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4588>
2020-04-22 17:45:33 +00:00
Rhys Perry
f13049f48a aco: implement 64-bit sgpr swaps
In our pipeline-db, helps almost exclusively Detroit: Become Human.

Totals from 6726 (5.36% of 125503) affected shaders:
CodeSize: 74680952 -> 74102228 (-0.77%)
Instrs: 14551507 -> 14406001 (-1.00%)
Cycles: 1748272436 -> 1690173104 (-3.32%)
VMEM: 964671 -> 964058 (-0.06%)
Copies: 1993312 -> 1847806 (-7.30%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4469>
2020-04-22 13:25:17 +00:00
Rhys Perry
2ab45f41e0 aco: implement sub-dword swaps
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4469>
2020-04-22 13:25:17 +00:00
Rhys Perry
83fdb1ed3d aco: add VOP3P_instruction
The optimizer isn't yet updated to handle this, since lower_to_hw_instr
will be the only user for now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4469>
2020-04-22 13:25:17 +00:00
Rhys Perry
8fc24f9a45 aco: fix copy statistic for 64-bit vgpr constant copy
The statistic is in units of instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4469>
2020-04-22 13:25:17 +00:00
Connor Abbott
4daa3917a3 ir3: Fix bug with shaders that only exit via discard
discard is supposed to be a terminator, killing the thread, so that it's
possible to exit main solely by a discard e.g. inside of an infinite
loop. However, it currently isn't treated as a terminator in NIR due to
workarounds turning it into demote (d3d-style kill) and even if that
were fixed, we probably wouldn't want to treat discard_if as a jump
since otherwise the scheduler wouldn't be able to schedule things around
it. So, add this workaround which inserts jump instructions as
necessary to guarantee that the program always terminates.

This fixes a hang in dEQP-VK.graphicsfuzz.while-inside-switch, which
conditionally does a discard inside an infinite loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4658>
2020-04-22 09:49:40 +00:00
Connor Abbott
8cfa60eab8 ir3: Don't double-insert the first block
The first block was being added to the list twice, once here and once in
emit_block(), leading to list corruption and infinite loops when trying
to traverse the list of blocks backwards.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4658>
2020-04-22 09:49:40 +00:00
Danylo Piliaiev
66229aa169 spirv: Expand workaround for OpControlBarrier on old GLSLang
In SPIRV of compute shader in Aztec Ruins benchmark there is:

OpControlBarrier %uint_1 %uint_1 %uint_0
// ControlBarrier(Device, Device, rdcspv::MemorySemantics(0));

which is an incorrect translation of glsl barrier().

GLSLang, prior to c3f1cdfa, emitted the OpControlBarrier with
Device instead of Workgroup for execution scope.

2365520c covers similar case but isn't applied when execution_scope
is SpvScopeDevice.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2742
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4660>
2020-04-22 08:46:12 +00:00
Lionel Landwerlin
f402b7c576 iris: fail screen creation when kernel support is not there
v2: Bump check to I915_PARAM_HAS_CONTEXT_ISOLATION (v4.16) (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2803
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4643>
2020-04-22 08:18:33 +00:00
Samuel Pitoiset
bca97abffa gitlab-ci: add a list of excluded tests for RADV
Exclude WSI related tests in CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4656>
2020-04-22 09:11:53 +02:00
Jason Ekstrand
f1a12d6855 meta,i965: Rip GL_EXT_texture_multisample_blit_scaled support out of meta
i965 is the only driver that ever linked to this code and it's been
doing it in BLORP for a long time now.  The only possible case where it
would have fallen back to meta was for depth/stencil but that should
have ended starting with 6cec618e82.  Rip out the dead code.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4622>
2020-04-22 03:02:23 +00:00
Alyssa Rosenzweig
c6244f9311 panfrost: Assert on unimplemented fragcoord etc
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:18 +00:00
Alyssa Rosenzweig
133c1aba05 panfrost: Fix crashes with small BOs
Affects Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:18 +00:00
Alyssa Rosenzweig
5c6952108c pan/bi: Assert out multiple textures
Only for a moment.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:18 +00:00
Alyssa Rosenzweig
3551c138de pan/bi: Pack TEX compact instructions
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:18 +00:00
Alyssa Rosenzweig
cd5fe3b9e0 pan/bi: Generate TEX_COMPACT instruction
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
0769036a5c pan/bi: Stub out tex_compact logic
We may generate either texture type.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
f85746af35 pan/bi: Add normal/compact/dual switch to IR
For tex.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
93be49b14b pan/bi: Feed data register to BI_TEX
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
76d1bb03d5 pan/bi: Include TEX_COMPACT f16 opcode
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
bfc06b10de pan/bi: Structify TEX compact
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
cf7b952308 pan/bi: Disassemble f16 dual tex
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
a2c735350f pan/bi: Document when dual-tex is triggered
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Alyssa Rosenzweig
6fe41a12e3 pan/bi: Print tex_compact coordinates
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4671>
2020-04-22 01:01:17 +00:00
Kenneth Graunke
902c8731f4 intel/compiler: Put back saturate on [iu]add_sat opcodes
I deleted one too many inst->saturate = ... lines.  This one must stay.

Fixes: b7c47c4f7c ("intel/compiler: Drop nir_lower_to_source_mods() and related handling.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4669>
2020-04-22 00:47:40 +00:00
Roman Stratiienko
f699bb42af panfrost: Align Android makefiles with recent changes
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4634>
2020-04-22 00:27:15 +00:00
Eric Anholt
2f4a3c1ca0 freedreno/ir3: Drop handling FRAG_RESULT_DEPTH writing to .z
Since we consume NIR, we get FRAG_RESULT_DEPTH in .x.  Something must have
been working out for this code to not be trying to get an undefined value,
but go ahead and drop it now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4668>
2020-04-21 23:30:53 +00:00
Jonathan Marek
eab73799d1 turnip: fix GMEM resolve in CmdNextSubpass
The BLIT scissor must be set correctly for tu_store_gmem_attachment.

Fixes this deqp test:

dEQP-VK.pipeline.multisample_shader_builtin.sample_id.137_191_1.samples

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4666>
2020-04-21 23:04:34 +00:00
Andres Gomez
e4521aeafc gitlab-ci: adapt query_traces_yaml to gitlab specific changes
This change was missing after acf7e73be5 "(gitlab-ci: make explicit
tracie is gitlab specific)".

Fixes: acf7e73be5 "(gitlab-ci: make explicit tracie is gitlab specific)".
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4638>
2020-04-22 01:37:21 +03:00
Emil Velikov
0a884d7304 egl: simplify client/platform extension handling
For GLVND reasons the client/platform extensions strings should be
split. While in the non GLVND case they're one big string.

Currently we handle this distinction at run-time for not obvious reason.
Adding additional code and complexity.

Swap those with a few well placed #if USE_LIBGLVND guards.

As a side result this removes a minor memory leak due to the
concatenation in the non GLVND case.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4491>
2020-04-21 22:20:24 +00:00
Erik Faye-Lund
013d9e40fe mesa/gallium: do not use enum for bit-allocated member
The signedness of enums are undefined, so on platforms with signed
enums, this isn't going to work. One such platform is Microsoft Windows.

So let's just use an unsigned here instead.

Fixes: b1c4c4c7f5 ("mesa/gallium: automatically lower alpha-testing")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4648>
2020-04-21 21:56:21 +00:00
Jesse Natalie
a842dc154d util/ralloc: fix ralloc alignment on Win64
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4648>
2020-04-21 21:56:21 +00:00
Kenneth Graunke
b7c47c4f7c intel/compiler: Drop nir_lower_to_source_mods() and related handling.
I think we're unanimous in wanting to drop nir_lower_to_source_mods.
It's a bit of complexity to handle in the backend, but perhaps more
importantly, would be even more complexity to handle in nir_search.

And, it turns out that since we made other compiler improvements in the
last few years, they no longer appear to buy us anything of value.
Summarizing the results from shader-db from this patch:

 - Icelake (scalar mode)

   Instruction counts:

   - 411 helped, 598 hurt (out of 139,470 shaders)
   - 99.2% of shaders remain unaffected.  The average increase in
     instruction count in hurt programs is 1.78 instructions.
   - total instructions in shared programs: 17214951 -> 17215206 (<.01%)
   - instructions in affected programs: 1143879 -> 1144134 (0.02%)

   Cycles:

   - 1042 helped, 1357 hurt
   - total cycles in shared programs: 365613294 -> 365882263 (0.07%)
   - cycles in affected programs: 138155497 -> 138424466 (0.19%)

 - Haswell (both scalar and vector modes)

   Instruction counts:

   - 73 helped, 1680 hurt (out of 139,470 shaders)
   - 98.7% of shaders remain unaffected.  The average increase in
     instruction count in hurt programs is 1.9 instructions.
   - total instructions in shared programs: 14199527 -> 14202262 (0.02%)
   - instructions in affected programs: 446499 -> 449234 (0.61%)

   Cycles:

   - 5253 helped, 5559 hurt
   - total cycles in shared programs: 359996545 -> 360038731 (0.01%)
   - cycles in affected programs: 155897127 -> 155939313 (0.03%)

Given that ~99% of shader-db remains unaffected, and the affected
programs are hurt by about 1-2 instructions - which are all cheap
ALU instructions - this is unlikely to be measurable in terms of
any real performance impact that would affect users.

So, drop them and simplify the backend, and hopefully enable other
future simplifications in NIR.

Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4616>
2020-04-21 21:42:21 +00:00
Dylan Baker
fdd0ce12ac meson: update llvm dependency logic for meson 0.54.0
In meson 0.54.0 I fixed the llvm cmake dependency to return "not found"
if shared linking is requested. This means that for 0.54.0 and later we
don't need to do anything, and for earlier versions we only need to
change the logic to force the config-tool method if shared linking is
required.

Fixes: 821cf6942a
       ("meson: Use cmake to find LLVM when building for window")

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4556>
2020-04-21 20:55:12 +00:00
Dylan Baker
8e3696137f remove final imports.h and imports.c bits
This moves the fi_types to a new mesa_private.h and removes the
imports.c file. The vast majority of this patch is just removing
pound includes of imports.h and fixing up the recursive includes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:04 -07:00
Dylan Baker
289f02d1d5 dri/nouveau: replace assert with unreachable
I don't know why removing imports.h suddenly makes clang realize that
this function can not return in a non-debug build, but it does.
Unreachable is better because it doesn't have this problem.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
c3db0936ef mesa: move ADD_POINTERS to macros.h
I'm not really sure where else to put it. Since imports.h only has two
things left in it (neither of which are abstractions for smoothing away
libc differences) I'd like to get them out of there. macros.h is the
only place I can think of to put this macro.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
bf188f3494 mesa|mapi: replace _mesa_[v]snprintf with [v]snprintf
MSVC 2015 and newer has perfectly valid snprintf and vsnprintf
implementations, let's just use those.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
c495c3af26 replace imports memory functions with utils memory functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
bb560f2d65 util: Add an aligned realloc function
Mesa has one of these in imports.h, so u_memory needs one as well. This
is the version from mesa ported.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
b85775900d replace malloc macros in imports.h with u_memory.h versions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
9ee6e78a87 Replace IS_INF_OR_NAN with util_is_inf_or_nan
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
369f002591 move windows strtok_r define to u_string
This makes more sense for it, it's only used in the glsl compiler
currently, so we could probably move it there, but this seems fine for a
header only #define.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
53c36dfcfe replace IROUND with util functions
This adds two new util functions to rounding.h, _mesa_iroundf and
mesa_lround, which are just wrappers around roundf and round, that cast
to int and long int respectively. This is possible since mesa recently
dropped support for VC2013, since 2015 and 2017 support roundf.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
df3ce8fb77 mesa/main: remove unused IROUNDD
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
64014c8302 Replace IROUND_POS with _mesa_roundevenf
Which has the same behavior as long as you don't change the FPU rounding
mode. Other code in mesa makes the same assumption so it should be safe
to make that assumption more generally.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
9d9a2819ee replace IFLOOR with util_ifloor
which are exactly the same function with exactly the same implementation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
72acb66527 u_math: add x86 optimized version of ifloor
This is copied from the one in src/mesa/main/imports.h, which is the
same otherwise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
bd4e769515 replace LOG2 with util_fast_log2
The implementation is somewhat different, although if you go back in
time far enough they're the same, but the one in u_math was changed a
long time back to be faster.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
f8e4542bad replace _mesa_logbase2 with util_logbase2
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
e190e8cef2 replace _mesa_next_pow_two_* with util_next_power_of_two_*
The 64 bit variant in imports.h isn't even used.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Dylan Baker
e533fad182 replace _mesa_is_pow_two with util_is_power_of_two_*
Mostly this uses util_is_power_of_two_or_zero, which has the same
behavior as _mesa_is_pow_two when the input is zero. In cases where the
value is known to be != 0 ahead of time I used the _nonzero variant as
it may be faster on some platforms.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-04-21 11:09:03 -07:00
Eric Anholt
c1e7c1f422 freedreno/drm-shim: Add support for faking other adreno chips.
I wanted to look at the effect of a core NIR change on a2xx codegen, but I
don't have any of those boards.  This could also prove useful for quickly
sanity-checking the compiler by running shader-db on it -- a2xx fails in a
few ways on glmark2, and a3xx-a5xx fails on glmark2 in a debug_assert
(which we don't have enabled in our dEQP runs).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4652>
2020-04-21 15:47:39 +00:00
Gert Wollny
cc23920746 r600/sfn: use new temp register allocation when loading single value temporaries
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
50b66622f1 r600/sfn: Count only literals that are not inline to split instruction groups
An instruction group can only support 4 distinct literals, but inline
constants count into this number, so skip them when counting.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
9c7ce4d76e r600/sfn: Fix using the result of a fetch instruction in next fetch
The result of a fetch instruction can't be used as source in the same CF
block, so force a new CF block when the result would be used in the same
vertex fetch block.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
67495ff9aa r600/sfn: Fix handling of GS inputs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
58d6cda5f5 r600/sfn: Handle b2b1 like it was a mov
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
de7ea88ff8 r600/sfn: Fix null pointer deref in live range evalation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
5d10e3ec60 r600/nir: Pin interpolation results to channel
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
5e036fef1f r600/sfn: Implementing instructions blocks
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
b51ced7306 r600/sfn: Fix setting alignments when lowering UBOs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
bc9cf6adff r600/sfn: Reduce array limit for scratch usage
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Gert Wollny
6fdc75d1c6 r600: Dump a few more variables when requested
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4609>
2020-04-21 15:10:43 +00:00
Abhishek Kumar
f06e4ab319 anv/android: fix assert in anv_import_ahw_memory
Commit fixes assert that triggers when running
   dEQP-VK.api.external.memory.android_hardware_buffer.dedicated.buffer#bind_export_import_bind

on a debug build of Mesa.

Fixes: c79a528d ("anv/android: support import/export of AHardwareBuffer objects")
Signed-off-by: Abhishek Kumar <abhishek4.kumar@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4655>
2020-04-21 11:50:15 +00:00
Danylo Piliaiev
829013d0ca st/mesa: Re-assign vs in locations after updating nir info for ffvp/ARB_vp
After call to nir_shader_gather_info - inputs_read may have changed so
st_nir_assign_vs_in_locations should be called for shader to remain in
sync with vbo state.

Fixes piglit tests:
  gl-1.0-fpexceptions
  gl-1.1-color-material-unused-normal-array
  arb_vertex_program-unused-attributes
regression on several gallium drivers.

Fixes: d684fb37bf
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4645>
2020-04-21 11:16:41 +00:00
Connor Abbott
ae169f38ce tu: Fix the advertised maxFragmentInputComponents
This appears to be limited by VPC_CNTL_0::NUMNONPOSVAR, which is an
8-bit bitfield with no possibility for expansion. Also, in practice
we'll be limited by the vertex shader output maximum, which includes
gl_Position, of 128, so that users won't be able to use more than 124
components anyways. Lower it to match the GL blob.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4641>
2020-04-21 10:04:13 +00:00
Connor Abbott
45ec9c0f3d freedreno/a6xx: Expand various varying-count bitfields
The extra bit needs to be used when using the maximum of 128 varying
components. I confirmed that PC_PRIMITIVE_CNTL_1 and SP_PRIMITIVE_CNTL
are expanded using a trace of the Vulkan blob with the maximum number of
varyings, and changed the others by analogy.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4641>
2020-04-21 10:04:13 +00:00
Erik Faye-Lund
d29fea77b9 docs: remove outdated sentence
The releasing documentation no longer contains this step, so this seems
out of date. The anchor for this link is also removed, making it point
nowhere.

Fixes: d4cb9ef826 ("docs: Update release notes with current process")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4654>
2020-04-21 09:49:22 +00:00
Pierre-Eric Pelloux-Prayer
56f174d14e st/omx: fix gcc warnings
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4584>
2020-04-21 09:16:28 +02:00
Pierre-Eric Pelloux-Prayer
07071cac7b gallium/utils: silence strncpy warning
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4584>
2020-04-21 09:16:26 +02:00
Pierre-Eric Pelloux-Prayer
dbfeec62c3 mesa: fix crash in find_value
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4584>
2020-04-21 09:16:18 +02:00
Jason Ekstrand
7c43b8ce1b nir: Delete the fnoise opcodes
As of the previous commit, they are never used.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4624>
2020-04-21 06:16:13 +00:00
Jason Ekstrand
4386c06770 glsl: Hard-code noise to zero in builtin_functions.cpp
Version 4.4 of the GLSL spec changed the definition of noise*() to
always return zero and earlier versions of the spec allowed zero as a
valid implementation.

All drivers, as far as I can tell, unconditionally call lower_noise()
today which turns ir_unop_noise into zero.  We've got a 10-year-old
comment in there saying "In the future, ir_unop_noise may be replaced by
a call to a function that implements noise."  Well, it's the future now
and we've not yet gotten around to that.  In the mean time, the GLSL
spec has made doing so illegal.

To make things worse, we then pretend to handle the opcode in
glsl_to_nir, ir_to_mesa, and st_glsl_to_tgsi even though it should never
get there given the lowering.  The lowering in st_glsl_to_tgsi defines
noise*() to be 0.5 which is an illegal implementation of the noise
functions according to pre-4.4 specs.  We also have opcodes for this in
NIR which are never used because, again, we always call lower_noise().

Let's just kill the whole opcode and make builtin_builder.cpp build a
bunch of functions that just return zero.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4624>
2020-04-21 06:16:13 +00:00
Timothy Arceri
95f555a93a st/glsl_to_nir: make use of nir linker for linking uniforms
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4395>
2020-04-21 01:57:34 +00:00
Timothy Arceri
0f79e0f7c6 glsl: fix gl_nir_set_uniform_initializers() for bindless textures
We need to skip opaque variables inside blocks, this is handled
elsewhere and will cause a crash here.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4395>
2020-04-21 01:57:34 +00:00
Timothy Arceri
9546440227 glsl: add bindless support to nir uniform linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4395>
2020-04-21 01:57:34 +00:00
Eric Engestrom
57e65cabd4 pick-ui: show commit sha in the pick list
Useful to get more context when a manual merge is needed, for instance.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4651>
2020-04-21 01:25:44 +00:00
Eric Engestrom
32451a15ec pick-ui: make .pick_status.json path relative to the git root instead of the script
This allows the script to be called from another git worktree for instance,
which I need for my workflow :)

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4649>
2020-04-21 01:13:53 +00:00
Eric Engestrom
26a26a3584 pick-ui: compute .pick_status.json path only once
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4649>
2020-04-21 01:13:53 +00:00
Jason Ekstrand
a4b36cd3dd intel/fs: Coalesce when the src live range is contained in the dst
Consider the following case:

    // g119-123 are written somewhere above
    mul.sat(16)   g67<1>F    g6.4<0,1,0>F   g125<8,8,1>F
    mul.sat(16)   g69<1>F    g6.5<0,1,0>F   g125<8,8,1>F
    mul.sat(16)   g71<1>F    g6.6<0,1,0>F   g125<8,8,1>F
    mov(16)       g119<1>F   g67<8,8,1>F
    mov(16)       g121<1>F   g69<8,8,1>F
    mov(16)       g123<1>F   g71<8,8,1>F

We should be able to coalesce it into

    mul.sat(16)   g119<1>F   g6.4<0,1,0>F   g125<8,8,1>F
    mul.sat(16)   g121<1>F   g6.5<0,1,0>F   g125<8,8,1>F
    mul.sat(16)   g123<1>F   g6.6<0,1,0>F   g125<8,8,1>F

What's stopping us is an overly conservative check for writes to the two
registers being coalesced.  The check walks over the intersection of
their live ranges and checks for no writes to either one.  However,
because the register which starts the live range (the mul.sat in this
case) is inside that intersection, we flag it as a write in the
intersection and don't coalesce.  However, this case is safe because the
destination register of the copy is never read after the source is
written.

Shader-db changes on ICL:

    total instructions in shared programs: 16043613 -> 16042610 (<.01%)
    instructions in affected programs: 43036 -> 42033 (-2.33%)
    helped: 226
    HURT: 0
    helped stats (abs) min: 1 max: 30 x̄: 4.44 x̃: 4
    helped stats (rel) min: 0.09% max: 26.67% x̄: 4.89% x̃: 3.43%
    95% mean confidence interval for instructions value: -4.86 -4.02
    95% mean confidence interval for instructions %-change: -5.57% -4.22%
    Instructions are helped.

    total cycles in shared programs: 334766372 -> 334710124 (-0.02%)
    cycles in affected programs: 617548 -> 561300 (-9.11%)
    helped: 214
    HURT: 2
    helped stats (abs) min: 15 max: 1512 x̄: 263.21 x̃: 212
    helped stats (rel) min: 0.30% max: 75.36% x̄: 25.30% x̃: 21.58%
    HURT stats (abs)   min: 40 max: 40 x̄: 40.00 x̃: 40
    HURT stats (rel)   min: 0.15% max: 0.15% x̄: 0.15% x̃: 0.15%
    95% mean confidence interval for cycles value: -277.91 -242.90
    95% mean confidence interval for cycles %-change: -27.58% -22.55%
    Cycles are helped.

No spill/fill changes or gained/lost

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4627>
2020-04-21 01:00:24 +00:00
Jason Ekstrand
14b8d979db intel/fs: Rename block to scan_block in can_coalesce_vars
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4627>
2020-04-21 01:00:24 +00:00
Jonathan Marek
064d39e620 radv: use common nir_convert_ycbcr
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
2020-04-20 22:01:43 +00:00
Jonathan Marek
7870d71459 anv: use common nir_convert_ycbcr
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
2020-04-20 22:01:43 +00:00
Jonathan Marek
71820c6b02 nir: convert_ycbcr: preserve alpha channel
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
2020-04-20 22:01:43 +00:00
Jonathan Marek
f8558fb1ce nir: add common convert_ycbcr for vulkan csc
Copied from anv, replaced state with passing model/range directly.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4528>
2020-04-20 22:01:43 +00:00
Dave Airlie
c2d8a4bf17 nir/linking: fix issue with two compact variables in a row. (v2)
If we have a clip dist float[1] compact followed by a tess factor
float[2] we don't want to overlap them, but the partial check
only happens for non-compact vars.

This fixes some issues seen with my sw vulkan layer with
dEQP-VK.clipping.user_defined.clip_distance*

v2: v1 failed with clip/cull mixtures, since in that
case the cull has a location_frac to follow after the clip
so only reset if we get a location_frac of 0 in a subsequent
clip var

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4635>
2020-04-20 21:08:54 +00:00
Eric Engestrom
a24ab26ff7 pick-ui: auto-scroll the feedback window
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4650>
2020-04-20 22:11:00 +02:00
Dylan Baker
8b8a99ba56 bin/pick-ui: Add a new maintainer script for picking patches
In the long term the goal of this script is to nearly completely
automate the process of picking stable nominations, in a well tested
way.

In the short term the goal is to provide a better, faster UI to interact
with stable nominations.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3608>
2020-04-20 19:40:55 +00:00
Dylan Baker
0123b8f634 bin/gen_release_notes.py: Fix version detection for .0 release
The previous version is being calculated incorrectly, resulting in
20.0.0 deciding it's version is 19.3.x+1. This fixes that.

Fixes: 3226b12a09
       ("release: Add an update_release_calendar.py script")

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4070>
2020-04-20 19:21:15 +00:00
Rafael Antognolli
4abf0837cd anv: Add support for new MMAP_OFFSET ioctl.
v2: Update getparam check (Ken).

[jordan.l.justen@intel.com: use 0 offset for MMAP_OFFSET]

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:06 -07:00
Rafael Antognolli
0d387da083 anv: Add anv_device parameter to anv_gem_munmap.
Also update all of its callers.

On the next commit, the device will be used by anv_gem_munmap to choose
whether we need to call the valgrind code or not, depending on which
type of mmap we are using.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:06 -07:00
Rafael Antognolli
d1c1ead7cd iris/bufmgr: Add support for MMAP_OFFSET ioctl.
Use the new DRM_IOCTL_I915_GEM_MMAP_OFFSET ioctl when available.

[jordan.l.justen@intel.com: iris port]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

v2: Update getparam check (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:06 -07:00
Rafael Antognolli
ae6f06c509 i965/bufmgr: Add support for MMAP_OFFSET ioctl.
Use the new DRM_IOCTL_I915_GEM_MMAP_OFFSET ioctl when available.

v2: update getparam check (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:06 -07:00
Rafael Antognolli
5bc3f52dd8 iris/bufmgr: Factor out GEM_MMAP ioctl from mmap_cpu and mmap_wc.
We want to add a new ioctl for mmap'ing buffers, so let's avoid
duplicating that code on both functions by extracting it from them
first.

[jordan.l.justen@intel.com: iris port]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

v2: Rename helper function names (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:06 -07:00
Rafael Antognolli
a42d715784 i965/bufmgr: Factor out GEM_MMAP ioctl from mmap_cpu and mmap_wc.
We want to add a new ioctl for mmap'ing buffers, so let's avoid
duplicating that code on both functions by extracting it from them
first.

v2: Update helper function names (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:05 -07:00
Rafael Antognolli
16be8ff022 drm-uapi: Update headers from Linux 5.7-rc1.
commit 8f3d9f354286745c751374f5f1fcafee6b3f3136
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Apr 12 12:35:55 2020 -0700

    Linux 5.7-rc1

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
2020-04-20 10:59:05 -07:00
Caio Marcelo de Oliveira Filho
a1f6ae4744 spirv: Fix propagation of OpVariable access flags
After the decorations of a variable are evaluated, propagate the
access flag to the associated vtn_pointer.  This was done when
creating the pointer but at that point there was no access flags for
the variable.

Inline the pointer creation to make this point clearer, in isolation
the helper made the impression that the value was being propagated.

Issue found by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4620>
2020-04-20 16:46:06 +00:00
Caio Marcelo de Oliveira Filho
c76f2292b5 intel/fs,vec4: Properly account SENDs in IVB memory fence
Change brw_memory_fence to return the number of messages emitted, and
use that to update the send_count statistic in code generation.

This will fix the book-keeping for IVB since the memory fences will
result in two SEND messages.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4646>
2020-04-20 09:29:09 -07:00
Daniel Schürmann
c3c1f4d6bc aco: move src1 to vgpr instead of using VOP3 for VOP2 instructions during isel
Is simpler and helps a couple of shaders.
Totals from affected shaders: (Vega)
Code Size: 16341296 -> 16335460 (-0.04 %) bytes

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
2020-04-20 15:12:50 +00:00
Daniel Schürmann
be0bb7e101 aco: fix 64bit fsub
Fixes: 425558bfd5 ('aco: use v_subrev_f32 for fsub with an sgpr operand in src1')

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
2020-04-20 15:12:50 +00:00
Tomeu Vizoso
ad3ef6d0fc gitlab-ci: Test virgl driver
Add virglrenderer to the container and use the vtest transport to test
the Gallium driver. On the "host", llvmpipe is used.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4433>
2020-04-20 13:53:09 +00:00
Erik Faye-Lund
d6b7439619 meson: do not disable incremental linking for debug-builds
Meson specifies /EDITANDCONTINUE for MSVC projects when using the debug
build-type. This collides with our across-the-board disabling of
incremental linking.

It's clear that we don't want to do incremental linking for
release-builds; it increase the code-size, and adds some needless jumps
to be able to patch in new code. But for debug-builds this seems like a
good thing; we can now debug and on-the-fly recompile changes if we want
to.

This flag seems to have been simply forwarded from the SCons build
system, where it makes a bit more sense; SCons doesn't really integrate
with visual studio, so you can't properly debug with it. But Meson does,
so let's keep some bells-and-whistles here.

So let's avoid disabling incremental linking for debug-builds. For other
builds we still want to do this, because Meson only disables it
automatically for minsize-builds.

This avoids a boat-loads of warnings on the form:

warning LNK4075: ignoring '/EDITANDCONTINUE' due to '/INCREMENTAL:NO' specification

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4572>
2020-04-20 12:25:42 +00:00
Erik Faye-Lund
ed29b24e23 gtest: Update to 1.10.0
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4576>
2020-04-20 11:57:11 +00:00
Samuel Pitoiset
59427b6d1d nir/opt_algebraic: lower 64-bit fmin3/fmax3/fmed3
This unconditionally lowers 64-bit fmin3/fmax3/fmed3 because
AMD hardware doesn't have native instructions, and no drivers
except RADV uses these instructions.

Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.f64.*
with ACO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
2020-04-20 06:59:47 +00:00
Samuel Pitoiset
eed0ace466 nir/lower_int64: lower imin3/imax3/umin3/umax3/imed3/umed3
Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.i64.*
with ACO because this backend compiler expects most of the 64-bit
operations to be lowered.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
2020-04-20 06:59:47 +00:00
Pierre-Eric Pelloux-Prayer
17acff01a0 radeonsi: skip vs output optimizations for some outputs
If PT_SPRITE_TEX is enabled, PS inputs are overriden at runtime so
we can't apply the vs output optim.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2747
Fixes: 3ec9975555 ("radeonsi: eliminate trivial constant VS outputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4559>
2020-04-20 08:45:16 +02:00
Timothy Arceri
839818332c nir/gcm: dont move movs unless we can replace them later with their src
This helps us avoid moving the movs outside if branches when there
src can't be scalarized.

For example it avoids:

   vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler),
   if ... {
      r0 = imov ssa_7.z
      r1 = imov ssa_7.y
      r2 = imov ssa_7.x
      r3 = imov ssa_7.w
      ...
   } else {
      ...
      if ... {
         r0 = imov ssa_7.x
         r1 = imov ssa_7.w
         ...
      else {
         r0 = imov ssa_7.z
         r1 = imov ssa_7.y
         ...
      }
      r2 = imov ssa_7.x
      r3 = imov ssa_7.w
   }
   ...
   vec4 32 ssa_36 = vec4 r0, r1, r2, r3

Becoming something like:

   vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler),
   r0 = imov ssa_7.z
   r1 = imov ssa_7.y
   r2 = imov ssa_7.x
   r3 = imov ssa_7.w

   if ... {
      ...
   } else {
      if ... {
         r0 = imov r2
         r1 = imov r3
         ...
      else {
         ...
      }
      ...
   }

While this is has a smaller instruction count it requires more work
for the same result. With more complex examples we can also end up
shuffling the registers around in a way that requires more registers
to use as temps so that we don't overwrite our original values along
the way.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Timothy Arceri
e4e5beee8a nir/gcm: be more conservative about moving instructions from loops
Here we only pull instructions further up control flow if they are
constant or texture instructions. See the code comment for more
information.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Timothy Arceri
bf4a6c99d2 nir/gcm: allow derivative dependent intrinisics to be moved earlier
We can't move them later as we could move them into non-uniform
control flow, but moving them earlier should be fine.

This helps avoid a bunch of spilling in unigine shaders due to
moving the tex instructions sources earlier (outside if branches)
but not the instruction itself.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
50a6dd0d65 nir/gcm: Prefer the instruction's original block
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
d4cf2df01a nir/gcm: Delete dead instructions
Classically, global code motion is also a dead code pass.  However, in
the initial implementation, the decision was made to place every
instruction and let conventional DCE clean up the dead ones.  Because
any uses of a dead instruction are unreachable, we have no late block
and the dead instructions are always scheduled early.  The problem is
that, because we place the dead instruction early, it  pushes the
placement of any dependencies of the dead instruction earlier than they
may need to be placed.  In order prevent dead instructions from
affecting the placement of live ones, we need to delete them.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
dca3f351e5 nir/gcm: Add a real concept of "progress"
Now that the GCM pass is more conservative and only moves instructions
to different blocks when it's advantageous to do so, we can have a
proper notion of what it means to make progress.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
5b1615fdb7 nir/gcm: Move block choosing into a helper function
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
1f60f1aa3d nir/gcm: Use an array for storing the early block
We are about to adjust our instruction block assignment algorithm and we
will want to know the current block that the instruction lives in.  In
order to allow for this, we can't overwrite nir_instr::block in the
early scheduling pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
6006a9e275 nir/gcm: Loop over blocks in pin_instructions
Now that we have the new block iterators, we can simplify things a bit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Jason Ekstrand
4d083b52c0 nir/dominance: Better handle unreachable blocks
v2: Fix minor comments (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
2020-04-20 03:46:29 +00:00
Daniel Schürmann
425558bfd5 aco: use v_subrev_f32 for fsub with an sgpr operand in src1
This fixes an accidentally introduced regression.

Fixes: 9be4be515f ('aco: implement 16-bit nir_op_fsub/nir_op_fadd')
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4633>
2020-04-19 16:16:27 +00:00
Daniel Stone
adeef43d15 CI: Disable Lima jobs due to lab unhealthiness
The BayLibre LAVA host appears to be down.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4631>
2020-04-19 12:57:04 +01:00
Daniel Stone
e6c7bdc851 ci/windows: Make Chocolatey installs more reliable
Chocolatey installs depend on downloading binaries from SourceForge,
which is an unreliable host: container builds often fail because it
cannot pick up winflexbison.

Add a loop to retry chocolatey installs if any installs have failed, and
ensure Python is in the accessible PowerShell path rather than relying
on the path being externally refreshed.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4631>
2020-04-19 12:55:02 +01:00
Arcady Goldmints-Orlov
ec1b96fdc8 nir: Lower returns correctly inside nested loops
Inside nested flow control, nir_lower_returns inserts predicated breaks
in the outer block. However, it would omit doing this if the remainder
of the outer block (after the inner block) was empty. This is not
correct in the case of loops, as execution just wraps back around to the
start of the loop, so this change doesn't skip the predication inside
loops.

Fixes: 79dec93ead (nir: Add return lowering pass)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2724

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4603>
2020-04-19 02:54:08 +00:00
Jason Ekstrand
969aeb6a93 anv: Apply any needed PIPE_CONTROLs before emitting state
Push constants in particular can get picked up by the hardware at weird
times that happen *before* 3DPRIMITIVE.  Therefore, we need to flush
before we emit all our state to ensure that any data they may pick up is
in memory in time.  This fixes an app which does vkCmdCopyBuffers
immediately followed by a vkCmdBeginRenderPass and vkCmdDraw which uses
the destination of the copy as a UBO which we push.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
2020-04-19 02:41:22 +00:00
Jason Ekstrand
ffc84eac0d anv: Move vb_emit setup closer to where it's used in flush_state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
2020-04-19 02:41:22 +00:00
Albert Astals Cid
06c5875fd6 Fix promotion of floats to doubles
Use the f variants of the math functions if the input parameter is a
float, saves converting from float to double and running the double
variant of the math function for gaining no precision at all

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3969>
2020-04-18 19:55:45 +00:00
Connor Abbott
94cb129d51 ir3/ra: Fix off-by-one issues with live-range extension
The intersects() function assumes that inside each instruction values
always die before they are defined, so that if the end of one range is
the same instruction as the beginning of the next then they don't
intersect. However, this isn't the case for values that become live at
the beginning of a basic block, which become live *before* the first
instruction, or instructions that die at the end of a basic block which
die after the last instruction.

For example, imagine that we have two values, A which is defined earlier
in the block and B which is defined in the last instruction of the block
and both die at the end of the basic block (e.g. are used in the next
iteration of a loop). We would compute a range for A of, say, (10, 20)
and for B of (20, 20) since each block's end_ip is the same as the ip of
the last instruction, and RA would consider them to not interfere.
There's a similar problem with values that become live at the beginning.

The fix is to offset the block's start_ip and end_ip by one so that they
don't correspond to any actual instruction. One way to think about this
is that we're adding fake instructions at the beginning and end of a
block where values become live & die. We could invert the order, so that
values consumed by each instruction are considered dead at the end of
the previous instruction, but then values that become dead at the
beginning of the basic block would incorrectly have an empty live range,
with a similar problem at the end of the basic block if we try to say
that values are defined at the beginning of the next instruction. So
the extra padding instructions are unavoidable.

This fixes an accidental infinite loop in the shader for
dEQP-VK.spirv_assembly.type.scalar.u32.switch_vert.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4614>
2020-04-18 17:31:56 +00:00
Lionel Landwerlin
cdc4377591 util/sparse_free_list: manipulate node pointers using atomic primitives
Probably doesn't fix anything but those should be accessed in an
atomic way just like the head pointer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e4f01eca3b ("util: Add a free list structure for use with util_sparse_array")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4613>
2020-04-18 12:18:03 +00:00
Timothy Arceri
36d2a0eed6 glsl: only set stage ref when uniforms referenced in stage
This updates the NIR uniform linker to behave like the GLSL IR
linker and fixes a number of CTS tests once we enable the NIR
linker for glsl.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
6afd0954e1 glsl: pull mark_array_elements_referenced() out into common helper
We will reuse this helper in the NIR linker in the following
patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
5d992b539e glsl: fix block index in NIR uniform linker
We only want to set the index for the first block of an array. Also
add a comment about why we do not break here.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
5dbebf4982 glsl: error check max user assignable uniform locations
This adds the error check to the NIR uniform linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
c7355c4fb9 glsl: fix explicit locations for the glsl linker
We already reserved explicit locations in the GLSL linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
5442712c6d Revert "glsl: fix resizing of the uniform remap table"
This reverts commit e0aa0a839f.

Instead we fix it correctly in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
723edf859f glsl: tidy up uniform storage value count code in NIR linker
This makes the code cleaner and better reflects what the existing
glsl IR  linker does possibly fixing subtle bugs.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
3e2dbb6e70 glsl: fix struct offsets in the nir uniform linker
This change properly applies layouts to structs of uniforms in a
similar way to the GLSL IR linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Timothy Arceri
c19ebca308 nir: add matrix_layout to nir_variable data
This will be used by the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
2020-04-18 11:50:44 +00:00
Lionel Landwerlin
f27c707585 anv: skip writing perfcntr in results on Gen12+
We were not capturing the register already so don't bother writing the
delta in the results (we were previously doing a delta between two 0
values).

v2: Fix unused function warning

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
2020-04-18 13:32:27 +03:00
Lionel Landwerlin
086ea1ac7e intel/perf: Enable MDAPI queries for Gen12
We're missing the cases for gen12 leading to those metrics going
missing.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15b7b56eb2 ("intel/perf: add TGL support")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
2020-04-18 02:04:09 +03:00
Alyssa Rosenzweig
29fb5451a9 pan/bit: Add fp16 min/max tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
532dfebc71 pan/bit: Add constants test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
15fe8d5d7b pan/bit: Add fexp2_fast test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
20f255b18e pan/bit: Add fexp2_fast interp
Kind of a hack and not at all how the h/w does it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
8890fa4050 pan/bit: Add FMA_MSCALE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
b7dd5b579d pan/bit: _MSCALE interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
1e3960a725 pan/bit: Add BI_TABLE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
93fffd8a11 pan/bit: Add log2 helper interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
1c45b58ceb pan/bit: Add FMA_REDUCE test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
5546d1958b pan/bit: Add BI_REDUCE_FMA interp
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
68b4e708f1 pan/bit: Add frexp_log test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
36cfe722e5 pan/bit: Add FREXP interp support
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
c05860789a pan/bi: Lower special ops to 32-bit
We don't have 16-bit tables. We could probably do a bit better to avoid
so many conversions but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
4d0f941036 pan/bi: Round constants to 32-bit
We can only access lo/hi at 32-bit intervals.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:36 -04:00
Alyssa Rosenzweig
d30df466b5 pan/bi: Dump extra bits for disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
590d66fa0c pan/bi: Pack MAX.v2f16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
f87403c4c1 pan/bi: Pack ADD.v2f16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
7e76c2b806 pan/bi: Structify add and min/max fp16 ADD
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
1647884cec pan/bi: Workaround constant packing errata
Incomplete fix.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
d772bf0101 pan/bi: Try to reuse constants in ALU
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
aba7f09902 pan/bi: Handle st_vary with <4 components
Still no writemasks.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
438e445e17 pan/bi: Fix vec2/3 handling
Otherwise we get moves from null.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
031ad0ecc2 pan/bi: Implement flog2
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
8e52206dbe pan/bi: Add fexp2 implementation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
b1d4d8f743 pan/bi: Fix lower_combine swizzle rewrite
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
60f252708f pan/bi: Fix packing with low-nibble-set on hi constant
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
10fb5fb460 pan/bi: Fix packing with multiple constants
Need to use bottom nibble of the 64, not the half.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
86c2a6b9fe pan/bi: Fix bi_get_immediate with multiple imms
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
df69304ac8 pan/bi: Ensure CONSTANT srcs have types
So the next commit is valid.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
8f70f4432c pan/bi: Split src/dest index printing
So we can handle constant printing correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
db5c1ae8fd pan/bi: Add fexp2_fast packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
c3eebfeb11 pan/bi: Pack FMA_MSCALE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
0cb703984e pan/bi: Structify FMA_MSCALE
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
4570c34fc7 pan/bi: Add _MSCALE flag for FMA/ADD
So we can bias by exponents.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
d3643cdd81 pan/bi: Add log2_help packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
6039d51e32 pan/bi: Pack ADD_FREXPM
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
ffa9f6a789 pan/bi: Add bi_pack_fma_2src helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
9904ed170a pan/bi: Add frexp_log packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:35 -04:00
Alyssa Rosenzweig
e067fd7b00 pan/bi: Add log_frexpe op to IR
As part of BI_FREXP

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
40befaa965 pan/bi: Add FLOG2_U op to disassembler
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
62c8c3445e pan/bi: Add op for ADD_FREXPM
Used in log2. Needs a new class as well due to scheduling silliness.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
cc61156626 pan/bi: Add special op for exp2
Needs some extra help but basically exp2_fast

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
af01378dce pan/bi: Add BI_TABLE for fast table accesses
Used to implement SPECIAL ops. Separate class since they are faster
which means you can pair them with actual work on FMA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
83d961b0c2 pan/bi: Disable FMA scheduling for CONVERT
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Alyssa Rosenzweig
86c0ea383d pan/bi: Add disasm for ADD.i8
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
2020-04-17 16:25:34 -04:00
Jason Ekstrand
f5deed138a spirv,nir: Move the SPIR-V vector insert code to NIR
This also makes spirv_to_nir a bit simpler because the new
nir_vector_insert helper automatically handles a constant component
selector like nir_vector_extract does.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
Jason Ekstrand
feca439697 spirv: Call nir_builder directly for vector_extract
The nir_builder helper already handles checking if the component
selector is an immediate and returns an undef in the OOB case.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
Jason Ekstrand
acaccff4d3 nir/builder: Handle any bit-size selector in nir_extract
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
Jason Ekstrand
4b160c6776 spirv: Error if OpCompositeInsert/Extract has OOB indices
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
Jason Ekstrand
c478f8ad6c spirv,nir: Add a better vector_insert
The old one in spirv_to_nir was besel'ing the whole vector for every
component.  If we think about this as a vector operation, we can do it
way more efficiently.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
Jason Ekstrand
380bf556bf spirv: Handle OOB vector extract operations
We use vtn_vector_extract to handle vector component level derefs.  This
makes us gracefully handle the case where your vector component is OOB
and give you an undef.  The SPIR-V working group is still working out
whether or not this is technically legal but it's very little code for
us to handle it so we may as well.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4495>
2020-04-17 19:21:44 +00:00
D Scott Phillips
dc3a17997b util/sparse_array: don't stomp head's counter on pop operations
By temporarily storing the new_head by a uint32_t, we wipe out the
counter section of the head pointer.

Fixes: e4f01eca ("util: Add a free list structure for use with util_sparse_array")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4612>
2020-04-17 18:41:40 +00:00
Danylo Piliaiev
d684fb37bf st/mesa: Update shader info of ffvp/ARB_vp after translation to NIR
We must update stp->Base.info after translation and before
st_prepare_vertex_program is called, because inputs_read
may become outdated after NIR optimization passes.

For ffvp/ARB_vp inputs_read is populated based on declared
attributes without taking their usage into consideration.
When creating shader variants we expect that their inputs_read
would match the base ones for input mapping to work properly.

Cc: <mesa-stable@lists.freedesktop.org>
Fixes: 8a0dd0af3f
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2758
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4598>
2020-04-17 20:16:15 +03:00
Samuel Pitoiset
c4ca9e66dd aco: fix exporting the viewport index if the fragment shader needs it
It's like the layer, it has to be exported via the pos and also
as a varying if the fragment shader reads it.

Fixes dEQP-VK.draw.shader_viewport_index.fragment_shader_*

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4564>
2020-04-17 16:23:24 +00:00
Samuel Pitoiset
b424d49ac0 radv/llvm: fix exporting the viewport index if the fragment shader needs it
It's like the layer, it has to be exported via the pos and also
as a varying if the fragment shader reads it.

Fixes dEQP-VK.draw.shader_viewport_index.fragment_shader_*

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4564>
2020-04-17 16:23:24 +00:00
Samuel Pitoiset
19aa68ae31 radv: set missing SHARED_VGPR_CNT for NGG VS and ACO
shuffle is implemented with shared VGPRs with ACO and Wave64.

Fixes dEQP-VK.subgroups.shuffle.framebuffer.subgroupshuffle*_vertex
with Wave64.

Fixes: c24d9522da ("radv: Enable ACO for NGG VS/TES, but disable NGG for ACO GS.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4595>
2020-04-17 16:11:17 +00:00
Samuel Pitoiset
fd6e44236c radv: fix geometry shader primitives query with ACO on GFX10
Fixes
dEQP-VK.query_pool.statistics_query.*.geometry_shader_primitives.*.

Fixes: c24d9522da ("radv: Enable ACO for NGG VS/TES, but disable NGG for ACO GS.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4593>
2020-04-17 17:39:16 +02:00
Ian Romanick
f7d620f47d intel/compiler: Fixup operands in fs_builder::emit() that takes array
The versions that take a specific number of operands will do various
fixups depending on the platform and the opcode.  However, the version
that takes an array of sources did not.  This makes all version operate
similarly.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:47 -07:00
Ian Romanick
39ad0c2af8 intel/compiler: CSEL can do saturate
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:46 -07:00
Ian Romanick
5afaa407c1 intel/compiler: Only GE and L modifiers are commutative for SEL
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:43 -07:00
Ian Romanick
a80e44902f intel/compiler: Silence unused parameter warning in update_inst_scoreboard
src/intel/compiler/brw_fs_scoreboard.cpp: In function ‘void {anonymous}::update_inst_scoreboard(const fs_visitor*, const ordered_address*, const fs_inst*, unsigned int, {anonymous}::scoreboard&)’:
src/intel/compiler/brw_fs_scoreboard.cpp:793:45: warning: unused parameter ‘shader’ [-Wunused-parameter]
  793 |    update_inst_scoreboard(const fs_visitor *shader, const ordered_address *jps,
      |                           ~~~~~~~~~~~~~~~~~~^~~~~~

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:42 -07:00
Ian Romanick
c836295dfd intel/compiler: Silence unused parameter warning in fs_live_variables::setup_one_read
src/intel/compiler/brw_fs_live_variables.cpp: In member function ‘void brw::fs_live_variables::setup_one_read(brw::fs_live_variables::block_data*, fs_inst*, int, const fs_reg&)’:
src/intel/compiler/brw_fs_live_variables.cpp:56:67: warning: unused parameter ‘inst’ [-Wunused-parameter]
   56 | fs_live_variables::setup_one_read(struct block_data *bd, fs_inst *inst,
      |                                                          ~~~~~~~~~^~~~

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:40 -07:00
Ian Romanick
62f70a353f intel/compiler: Silence unused parameter warnings in vec4_tcs_visitor
In file included from src/intel/compiler/brw_vec4_tcs.cpp:31:
src/intel/compiler/brw_vec4_tcs.h: In member function ‘virtual void brw::vec4_tcs_visitor::emit_urb_write_header(int)’:
src/intel/compiler/brw_vec4_tcs.h:74:43: warning: unused parameter ‘mrf’ [-Wunused-parameter]
   74 |    virtual void emit_urb_write_header(int mrf) {}
      |                                       ~~~~^~~
src/intel/compiler/brw_vec4_tcs.h: In member function ‘virtual brw::vec4_instruction* brw::vec4_tcs_visitor::emit_urb_write_opcode(bool)’:
src/intel/compiler/brw_vec4_tcs.h:75:57: warning: unused parameter ‘complete’ [-Wunused-parameter]
   75 |    virtual vec4_instruction *emit_urb_write_opcode(bool complete) { return NULL; }
      |                                                    ~~~~~^~~~~~~~

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4582>
2020-04-17 08:21:37 -07:00
Jason Ekstrand
030e5ceac4 intel/blorp: Delete an unused enum
This was lying around from back when BLORP write to fs_visitor directly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4606>
2020-04-17 15:01:10 +00:00
Jason Ekstrand
d0d039a4d3 anv: Emit pushed UBO bounds checking code in the back-end compiler
This commit fixes performance regressions introduced by e03f965280
in which we started bounds checking our push constants.  This added a
LOT of shader code to shaders which use the robustBufferAccess feature
and led to substantial spilling.  The checking we just added to the FS
back-end is far more efficient for two reasons:

 1. It can be done at a whole register granularity rather than per-
    scalar and so we emit one SIMD8 SEL per 32B GRF rather than one
    SIMD16 SEL (executed as two SELs) for each component loaded.

 2. Because we do it with NoMask instructions, we can do it on whole
    pushed GRFs without splatting them out to SIMD8 or SIME16 values.
    This means that robust buffer access no longer explodes our register
    pressure for no good reason.

As a tiny side-benefit, we're now using can use AND instead of SEL which
means no need for the flag and better scheduling.

Vulkan pipeline database results on ICL:

    Instructions in all programs: 293586059 -> 238009118 (-18.9%)
    SENDs in all programs: 13568515 -> 13568515 (+0.0%)
    Loops in all programs: 149720 -> 149720 (+0.0%)
    Cycles in all programs: 88499234498 -> 84348917496 (-4.7%)
    Spills in all programs: 1229018 -> 184339 (-85.0%)
    Fills in all programs: 1348397 -> 246061 (-81.8%)

This also improves the performance of a few apps:

 - Shadow of the Tomb Raider: +4%
 - Witcher 3: +3.5%
 - UE4 Shooter demo: +2%

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4447>
2020-04-17 14:48:06 +00:00
Jason Ekstrand
eb5a10ff63 intel/cfg: Add first/last_block helpers
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4447>
2020-04-17 14:48:06 +00:00
Connor Abbott
64e3b8d66b tu: Use tu_cs_add_entries() with non-render-pass secondaries
Even though vkCmdRenderPassBegin() isn't allowed inside a secondary
command buffer, vkCmdDispatch() is, and we emit an IB with compute
dispatches, which means that if the secondary command buffer records a
vkCmdDispatch() then we'll have an IB inside an IB, which is illegal.
Fixes hangs in e.g.
dEQP-VK.api.command_buffers.record_simul_use_secondary_one_primary.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4605>
2020-04-17 14:11:07 +00:00
Ilia Mirkin
ac0b8d58b9 mesa: add interaction between compute derivatives and variable local sizes
This is an added interaction in NV_compute_shader_derivatives added in
Sep 2019.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4583>
2020-04-17 13:51:11 +00:00
Karol Herbst
8c949b2aa6 st/mesa: properly guard fallback_copy_texsubimage aginst failed maps
Fixes random crashes in some packed_pixel GLES CTS tests

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4592>
2020-04-17 11:50:21 +00:00
Pierre-Eric Pelloux-Prayer
8521acd660 radeonsi: don't assume ctx is always a threaded_context
Fixes: dcb1e8fef8 ("radeonsi: use thread_context::bytes_mapped_limit")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4587>
2020-04-17 11:36:20 +02:00
Daniel Stone
791134658e Revert "CI: Disable Windows/VS2019 builds"
DNS is now fixed.

This reverts commit 460b8b1758d953b2b820443615d73ccdb1455b5e.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4591>
2020-04-16 22:40:24 +00:00
Ilia Mirkin
2f009c4b49 docs: update for recently-added nvc0 features
Also sort while we're at it.

And add NV_pixel_buffer_object.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4599>
2020-04-16 15:58:37 -04:00
Ilia Mirkin
6ae214ac2e nv50,nvc0: update with latest caps
One notable change is that DRAW_INFO_START_WITH_USER_INDICES is enabled.
An audit of the code indicates that it should work, and a number of
piglit tests exercising glMultiDrawElements continue to function.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4520>
2020-04-16 18:19:27 +00:00
Jason Ekstrand
029471c3c4 intel/batch_decoder: Stop printing to stdout
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4597>
2020-04-16 17:26:16 +00:00
Jason Ekstrand
b8acf9a3d4 anv: Report correct SLM size
Fixes: d787a2d0 "anv: Implement VK_KHR_pipeline_executable_properties"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4597>
2020-04-16 17:26:16 +00:00
Jason Ekstrand
e003104605 intel: Add _const versions of prog_data cast helpers
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4597>
2020-04-16 17:26:16 +00:00
Jason Ekstrand
9b17d7caac nir: Add some sanity assertions in opt_large_constants
We make some assumptions in opt_large_constants such as the size_align
function returning the obvious sizes for vectors.  Now that we've got
the deref_size lying around, we may as well assert it's consistent with
our assumptions.  In particular, we now assert that it really claims
booleans are 32-bit.  If anyone's driver ever decides to be clever and
change this, we'll now catch the breakage earlier.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4468>
2020-04-16 17:00:13 +00:00
Jason Ekstrand
33eb43349e nir: Add an alignment to nir_intrinsic_load_constant
In f1883cc73d we tried to pass through alignments from load_constant
intrinsics when rewriting them to load_ubo in iris.  However, those
intrinsics don't have ALIGN_MUL or ALIGN_OFFSET indices.  It's easy
enough to add them.  We just call the size/align function on the vector
type at the end of our deref chain and use the alignment returned from
there.  It's possible we could do better by walking the whole deref
chain but this should be good enough.

Fixes: f1883cc73d "iris: Set alignments on cbuf0 and constant reads"
Closes: #2739
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4468>
2020-04-16 17:00:13 +00:00
Jan Vesely
8cbeb13704 clover: Check if the detected clang libraries are usable
clang-cpp.so is broken in LLVM-9 and doesn't exist in LLVM<9,
however meson will find and try to use system libraries in these cases.

v2: Use helper variable to dedpulicate test code
    Move second test inside the condition to avoid testing good clang-cpp twice
v3: Check for cross compilation
v4: style fixes

Fixes: ff1a3a00cb
Signed-off-by: Jan Vesely <jano.vesely@gmail.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4457>
2020-04-16 16:29:44 +00:00
Rhys Perry
839c886b34 aco: add missing scc clobber to nir_op_unpack_32_2x16_split_y
The ISA doc is inconsistent whether this instruction writes SCC. It does.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4552>
2020-04-16 17:04:53 +01:00
Rhys Perry
ac74367bef aco: implement various 8/16-bit conversions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4552>
2020-04-16 17:04:45 +01:00
Rafael Antognolli
0443a4a0af iris: Enable EXT_depth_bounds_test extension.
It was implemented in 1df871f8ff, but to
really enable it we need to enable PIPE_CAP_DEPTH_BOUNDS_TEST.

v2: Add release notes (Ian).

Suggested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4540>
2020-04-16 15:28:59 +00:00
Erik Faye-Lund
daeff19608 meson: tell flex that we support c99
flexint.h uses stdint.h if the compiler claims to support C99. MSVC
doesn't support enough of C99 to enable this flag, but it supports
enough to keep flex happy.

Without this, we end up with *both* some flex-specific definitions as
well as our own definitions from mesa-headers, producing a slew of
compiler warnings.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Erik Faye-Lund
0752648a99 vbo: avoid including wingdi.h on win32
On Windows, main/glheader.h ends up including windows.h which in turn
includes wingdi.h unless the NOGDI macro is defined. And wingdi.h
defines a macro called "ERROR", which we end up redefining below.

To avoid a warning on the redefinition, we can define NOGDI to prevent
wingdi.h from implicitly being included.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Erik Faye-Lund
b55b033f76 mesa: fixup cast expression
This cast-expression was meant to cast the result of the terniary
expression, but it just casted the condition expression instead. Let's
correct this, to silence a compiler-warning.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Erik Faye-Lund
c55fc35435 util/tests: initialize variable
This just silences a compiler-warning about a potentially uninitialized
variable. It's not uninitialized, but it's a bit hard for the compiler
to see. So let's just initialize it to zero.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Erik Faye-Lund
522bb08131 wgl: silence some cast-warnings
These casts cause warnings on x64. We're passing integers through
pointers, which works fine.

So let's make the casts a bit more explicit, to silence that warning.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Erik Faye-Lund
e9ad8af6f3 meson: use override_options to change warning-level
This pevents MSVC from complaining about multiple warning-levels on the
command-line.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4577>
2020-04-16 14:48:40 +00:00
Jonathan Marek
2437808671 turnip: image_view rework
Instead of exposing various layout functions, move image-related logic
into tu_image.c and have the image_view pre-fill relevant register values.

This changes the clear/blit code to use image_view.

This will make it much easier to deal with aspect masks, in particular for
planar formats and D32_S8.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4581>
2020-04-16 14:04:18 +00:00
Jonathan Marek
300d0e2b80 turnip: don't limit framebuffer size to image size
Minor cleanup, I couldn't find anything that suggests this should be done,
and anv doesn't do it either.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4581>
2020-04-16 14:04:18 +00:00
Jonathan Marek
b6455e9a6a turnip: compute render_components/srgb_cntl at renderpass creation time
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4581>
2020-04-16 14:04:18 +00:00
Bas Nieuwenhuizen
d80fb02430 winsys/amdgpu: Retrieve WC flags from imported buffers.
Otherwise reading from an imported mapped GTT+WC linear texture
is painfully slow.

Sadly no radeon winsys implementation, as I don't know a suitable
kernel driver operation.

Hit this  in vaGetImage with an image imported from minigbm (which
we are switching to allocate WC for SCANOUT images).

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4542>
2020-04-16 13:51:28 +00:00
Marek Olšák
80797edd71 st/mesa: fix a crash due to passing a draw vertex shader into the driver
Fixes: bc99b22a30
Closes: #2754

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4527>
2020-04-16 13:31:46 +00:00
Daniel Stone
7a794b1de4 CI: Disable Windows/VS2019 builds
An update seems to have poisoned gitlab-runner, and it can no longer
resolve DNS even though the host system can.

Disable this until we can figure out what's going on.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4589>
2020-04-16 14:03:49 +01:00
Daniel Stone
9ecd9463de meson: Make shared-llvm into a tri-state boolean
Choosing LLVM's link mode is legitimate on UNIX systems, but only static
actually really works under Windows.

Give shared-llvm a default 'auto' mode which will pick the previous
default of true (shared) on UNIX systems, but newly defaulting to false
(static) on Windows.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Suggested-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4555>
2020-04-16 12:18:36 +00:00
Connor Abbott
0c05d46237 tu: Align GMEM resolve blit scissor
Even though we normally use the CP_BLIT path with resolves that aren't
aligned, there's a special case when we're resolving the entire image
and there's enough padding so that we can still use CP_EVENT_WRITE::BLIT
when the render area isn't aligned. The hardware seems to not like
unaligned scissors when not clearing, and sometimes hangs rather than
silently round the scissor. This causes hangs in e.g.
dEQP-VK.glsl.derivate.dfdx.texture.msaa4.float_highp.

There was some concern that the CP_BLIT path might use this scissor
also, but I confirmed that this isn't the case by setting it to 0 before
resolving and then noting that CP_BLIT still works (but CP_EVENT_WRITE
doesn't). Furthermore, this is actually impossible because of how the 2D
engine is set up: it gets its own pair of register banks, which can be
switched independently of the 3D register banks, so that 2D events
(CP_BLIT) normally aren't synchronized relative to 3D events
(CP_EVENT_WRITE, CP_DRAW_*, and CP_EXEC_CS) and therefore they can't
share any registers except for non-pipelined registers like RB_CCU_CNTL
that don't use the register bank mechanism at all.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4585>
2020-04-16 12:00:22 +00:00
Erik Faye-Lund
d2e172c03f .mailmap: add an alias for Zhongmin Wu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
eafacdc0fa .mailmap: add alias for Zhaowei Yuan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
56222c13cf .mailmap: add an alias for Yaakov Selkowitz
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
8be72b4c79 .mailmap: add an alias for Xavier Bouchoux
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
a96e1a2d9f .mailmap: specify spelling for Wladimir J. van der Laan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
f9e1e5857d .mailmap: specify spelling for Vivek Kasireddy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
47d17238dd .mailmap: add an alias for Varad Gautam
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
55f883b8ea .mailmap: add an alias for Vadym Shovkoplias
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
d8982ce84c .mailmap: add an alias for Topi Pohjolainen
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
0399b4f298 .mailmap: add an alias for Tomasz Figa
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
049ce5f417 .mailmap: add an alias for Tom Stellard
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
05b2a4471c .mailmap: add an alias for Tim Wiederhake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
e430136cc9 .mailmap: add a couple of aliases for Timothy Arceri
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
34ab507c1f .mailmap: add an alias for Timo Aaltonen
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:15 +00:00
Erik Faye-Lund
cb177e054a .mailmap: add an alias for Thierry Reding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
032a603e3c .mailmap: add a couple of aliases for Suresh Guttula
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
6d1fe4a687 .mailmap: add a couple of aliases for Steinar H. Gunderson
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
5ee82189f2 .mailmap: specify spelling for Sonny Jiang
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
d3f36056fa .mailmap: add an alias for Sergii Romantsov
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
00d9496a12 .mailmap: add an alias for Samuel Li
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
9a5bd1512a .mailmap: add an alias for Rodrigo Vivi
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
c6fcca4bd8 .mailmap: add an alias for Rob Clark
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
b7c1f150c9 .mailmap: add an alias for Renato Caldas
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3dac186704 .mailmap: specify spelling for Randy Xu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
9e904253e4 .mailmap: add an alias for Qiang Yu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3ba1d912a0 .mailmap: add an alias for Plamena Manolova
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
b42a25320e .mailmap: update aliases for Pierre-Eric Pelloux-Prayer
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3ffa511d60 .mailmap: add an alias for Philipp Zabel
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
2b82c50e79 .mailmap: update aliases for Nicolai Hähnle
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
f40c48c0c4 .mailmap: add an alias for Nicholas Bishop
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
004c69fbfa .mailmap: specify spelling for Nian Wu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3ce0e25a98 .mailmap: add an alias for Neil Roberts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
1ac6946ded .mailmap: add an alias for Neha Bhende
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
a9ed1085ab .mailmap: add alias for Matthias Groß
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3223198b4d .mailmap: update aliases for Marc-André Lureau
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
79bb330904 .mailmap: specify spelling for Liviu Prodea
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
25dcbcbb5b .mailmap: add an alias for Lionel Landwerlin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
2e53e65e23 .mailmap: add a few aliases for Kristian Høgsberg
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
69489e48bc .mailmap: add a few aliases for Kevin Rogovin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
ab4c32a50e .mailmap: add a few aliases for Karol Herbst
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
92e4597544 .mailmap: add an alias for Julien Isorce
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
ec001fd323 .mailmap: clean up aliases for Jeremy Huddleston
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
f131469d14 .mailmap: add an alias for Jan Beich
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
d8cb7efd30 .mailmap: specify spelling for James Zhu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
16ed147cab .mailmap: add an alias for Illia Iorin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
b7f912f11a .mailmap: add an alias for Igor Gnatenko
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
ebaa8765fe .mailmap: specify spelling for Henri Verbeet
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
eb96435aaf .mailmap: specify spelling for Heinrich Fink
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
02b2dc22d3 .mailmap: add an alias for Harish Krupo
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
3c86bc03b3 .mailmap: add an alias for Haihao Xiang
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
5ea2e1044e .mailmap: specify spelling for Gurchetan Singh
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
194c9f9982 .mailmap: specify spelling for Francesco Ansanelli
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
edb4e21e26 .mailmap: add an alias for Erik Faye-Lund
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
c11e1d4408 .mailmap: add an alias for Emmanuel Gil Peyrot
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
8efee3cea3 .mailmap: add a couple of aliases for Dylan Noblesmith
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
ee068df4f5 .mailmap: add an alias for Dylan Baker
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
e7699f92e9 .mailmap: add an alias for Dave Airlie
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
4e793b7b4b .mailmap: add an alias for Danylo Piliaiev
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
aa6ad898ba .mailmap: add an alias for Daniel Schürmann
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
e8764917c4 .mailmap: add an alias for Craig Stout
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
7f4d26b3cd .mailmap: specify spelling for Constantine Kharlamov
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
5437ccda31 .mailmap: add an alias for Colin McDonald
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
a07c11b0fe .mailmap: add a few aliases for Christoph Haag
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
0d6af7f9b1 .mailmap: add an alias for Christian Inci
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
832d1f913e .mailmap: add an alias for Christian Gmeiner
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
9278ea2920 .mailmap: add alias for Chenglei Ren
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
43bdff8a5c .mailmap: add a couple of aliases for Chandu Babu Namburu
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
d89e963133 .mailmap: add an alias for Chad Versace
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
a3a2c49e13 .mailmap: update aliases for Carl-Philip Hänsch
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
88eb6b7d58 .mailmap: add an alias for Bruce Cherniak
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
da8a309882 .mailmap: add an alias for Boris Brezillon
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
0efc82183d .mailmap: add an alias for Axel Davy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
84a9fe7766 .mailmap: add an alias for Anuj Phogat
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
5cf8dc7f54 .mailmap: add an alias for Andrii Simiklit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
174e97e969 .mailmap: add an alias for Alyssa Rosenzweig
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Erik Faye-Lund
12ec5b94ea .mailmap: add an alias for Alan Swanson
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1999>
2020-04-16 11:46:14 +00:00
Tapani Pälli
a934c8e7ed mesa/st: initialize all winsys_handle fields for memory objects
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reported-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4547>
2020-04-16 11:25:29 +00:00
Michel Dänzer
e3e704c7e7 amd/addrlib: Use enum instead of sparse chars to identify dimensions
The enum values can be used directly as indices into arrays, simplifying
the code.

This significantly cuts down the number of CPU cycles spent inside

* Addr::V2::Gfx9Lib::HwlComputeDccAddrFromCoord:

+------------------------------------------------------------------------+
|+         +++    +                                                x x xx|
|    |_____AM____|                                                 |_A__||
+------------------------------------------------------------------------+
    N           Min           Max        Median           Avg        Stddev
x   5         14.89         15.44         15.14        15.156    0.24704251
+   5          8.26          9.96          9.37         9.282     0.6262747
Difference at 95.0% confidence
	-5.874 +/- 0.694294
	-38.7569% +/- 4.58098%
	(Student's t, pooled s = 0.476051)

* Addr::V2::CoordEq::solve:

+------------------------------------------------------------------------+
| +                                                                x     |
| + +   +   +                                       x           x  x    x|
||__MA____|                                              |______A__M____||
+------------------------------------------------------------------------+
    N           Min           Max        Median           Avg        Stddev
x   5          8.11          9.59          9.21          9.02    0.55605755
+   5          4.28          5.05          4.48         4.564    0.32867917
Difference at 95.0% confidence
	-4.456 +/- 0.666135
	-49.4013% +/- 7.38509%
	(Student's t, pooled s = 0.456744)

(The measured numbers are the percentages of samples inside the
respective function and its calles for
`perf record --call-graph=fp kitty -e false`, measured on a Lenovo
Thinkpad E595 (Picasso))

v2:
* Add missed 'coords[dim] |= bit << ord;' (Pierre-Eric Pelloux-Prayer)
* Put 'ADDR_ASSERT(dim < DIM_S);' where the code previous had
  'ADDR_ASSERT_ALWAYS()' for the s/m dimensions.
* Use 1u for BitsValid (since it's 32-bit unsigned values).
* Use parens in 'BitsValid[dim] & (1u << ord)' for clarity.

Acked-by: Marek Olšák <marek.olsak@amd.com> # v1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4523>
2020-04-16 11:10:52 +00:00
Michel Dänzer
e58509cdec gbm/dri: Propagate queryDmaBufModifiers return value
We were treating count == 0 as the format not being supported at all,
but queryDmaBufModifiers would return false in that case.

Fixes spuriously reporting all formats as unsupported with radeonsi
(which doesn't support modifiers yet), which would e.g. cause mutter
to think the HW cursor format isn't supported and fall back to SW
cursor.

Suggested-by: Daniel Stone <daniels@collabora.com>
Fixes: 4e3a7dcf6e "gallium: enable
                     EGL_EXT_image_dma_buf_import_modifiers
                     unconditionally"

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4532>
2020-04-16 10:19:35 +00:00
Erik Faye-Lund
b5b25ee032 zink: be less picky about tiled resources
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2678>
2020-04-16 09:57:25 +00:00
Erik Faye-Lund
040a2643c0 st/dri: make sure software color-buffers are linear
Otherwise, we might end up with a tiling-capable driver creating a
tiled resource here instead of linear. This is currently possible with
Zink, although we currently force all display-targets to be linear.

But that doesn't seem like a good idea in the long run, so let's loosen
this restriction.

Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2678>
2020-04-16 09:57:25 +00:00
Lepton Wu
1c4f68b089 virgl: Use ETC2 formats directly when possible.
Don't emulate them with uncompressed formats if the host
support them since uncompressed formats like GL_R16 could
be not available on GLES hosts.

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
2020-04-16 09:21:21 +00:00
Pierre-Eric Pelloux-Prayer
dcb1e8fef8 radeonsi: use thread_context::bytes_mapped_limit
Limit the amount of "in-flight" mapping to 1/4 of the total RAM.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2735
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4508>
2020-04-16 08:36:04 +00:00
Pierre-Eric Pelloux-Prayer
15cf7d170b gallium/u_threaded: flush batch when hitting mapping limit
tc_transfer_map maps buffers directly, but the unmap operation is executed
in the driver thread.
When an application does a lot of map/unmap operations, without flushing,
this increase the RAM used (and eventually get the app killed by the oom-killer).

This commit allows tc to keep track of how many bytes were mapped during
the current batch. When this estimation becomes higher than a threshold,
we flush the batch.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2735
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4508>
2020-04-16 08:36:04 +00:00
Samuel Pitoiset
35b3963928 radv: do not abort with unknown/unimplemented descriptor types
To workaround a crash with Wolfeinstein Younglood because the
games creates one descriptor with
VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_NV...

I reported the problem to Machine Games, but still no answer, so
let's remove the unreachable calls (which are technically not
unreachable for buggy apps) to help gamers.

Note that AMDVLK and AMDGPU-PRO don't crash because they ignore
unsupported descriptor types.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4571>
2020-04-16 08:14:56 +00:00
Samuel Pitoiset
11faaf646d aco: fix emitting stream output with tess eval shaders
Fixes dEQP-VK.transform_feedback.simple.winding_patch_list_12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4553>
2020-04-16 07:57:39 +00:00
Samuel Pitoiset
91aa596ca7 aco: implement nir_op_f2i8/nir_op_f2u8
I think we should really refactor the conversions path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4551>
2020-04-16 08:47:49 +02:00
Ilia Mirkin
04a7ec7c8a nvc0: enable GL_NV_viewport_array2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-By: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:21:18 -04:00
Ilia Mirkin
cd092bf937 st/mesa: add support for GL_NV_viewport_array2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:48 -04:00
Ilia Mirkin
b0d0a3c916 gallium: add PIPE_CAP_VIEWPORT_MASK
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:48 -04:00
Ilia Mirkin
8f191e0c37 gallium: add TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:00 -04:00
Ilia Mirkin
17308c1014 gallium: add TGSI_SEMANTIC_VIEWPORT_MASK
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:00 -04:00
Ilia Mirkin
2d4787d77e mesa: add NV_viewport_array2 enable, attach to glsl
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:00 -04:00
Ilia Mirkin
cc6661bfc8 glsl: add NV_viewport_array2 support
This enables gl_Layer/gl_ViewportIndex when the ext is enabled, as well
as adding the new gl_ViewportMask[] array and viewport_relative layout
qualifier for gl_Layer.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:00 -04:00
Ilia Mirkin
54424a3d13 compiler: add VARYING_SLOT_VIEWPORT_MASK
See GL_NV_viewport_array2::gl_ViewportMask for how this is supposed
to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4529>
2020-04-15 20:12:00 -04:00
Connor Abbott
3a9e66277a ir3: Handle load_ubo_ir3 when promoting to constants
This restores support for promoting UBO loads to constant loads when
using LDC.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4568>
2020-04-15 22:38:20 +00:00
Connor Abbott
abcfb64370 ir3: Fix LDC offset units
I had missed that LDC actually uses vec4 units for its offset. This
means that we have to create a new instruction, and lower it in
ir3_nir_lower_io_offsets, similar to the existing SSBO instructions.
Unfortunately we can't assume that loads are always vec4-aligned, so we
have to use the alignment information that NIR gives us. Unfortunately,
it's currently woefully inadequate, and will have to be fixed to give us
good codegen in the future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4568>
2020-04-15 22:38:20 +00:00
Karol Herbst
2d489f76f4 Revert "nvc0: fix line width on GM20x+"
This reverts commit a0e57432b7.

It's unclear what caused the test to fail back then. Now it's seems to be
reversed. I tested with a close enough piglit and mesa branch and wasn't
able to reproduce the same test result I've got in some older piglit runs.

Fixes:
dEQP-GLES2.functional.rasterization.primitives.lines_wide
dEQP-GLES2.functional.rasterization.primitives.line_strip_wide
dEQP-GLES2.functional.rasterization.primitives.line_loop_wide
dEQP-GLES2.functional.rasterization.limits.points
dEQP-GLES2.functional.clipping.line.wide_line_z_clip
dEQP-GLES2.functional.clipping.line.wide_line_z_clip_viewport_center
dEQP-GLES2.functional.clipping.line.wide_line_z_clip_viewport_corner
dEQP-GLES2.functional.clipping.line.wide_line_clip
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES2.functional.clipping.line.wide_line_attrib_clip
dEQP-GLES2.functional.polygon_offset.default_result_depth_clamp
dEQP-GLES2.functional.polygon_offset.default_factor_1_slope
dEQP-GLES2.functional.polygon_offset.fixed16_result_depth_clamp
dEQP-GLES2.functional.polygon_offset.fixed16_factor_1_slope

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4575>
2020-04-15 22:03:46 +00:00
Jason Ekstrand
26a1adce5b anv: Fix UBO range detection in anv_nir_compute_push_layout
This fixes two bugs:  First, if the same block index showed up twice, we
only pick the first one.  Second, we weren't multiplying by 32.  This
didn't show up in tests because RBA testing is garbage.  Found while
looking at shaders from the UE4 Shooter demo.

Fixes: e03f9652 "anv: Bounds-check pushed UBOs when..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4578>
2020-04-15 21:51:55 +00:00
Jason Ekstrand
b2e4157143 anv: Advertise SEND count through VK_EXT_pipeline_executable_properties
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4578>
2020-04-15 21:51:55 +00:00
Paulo Zanoni
2c82b13c8f iris: make BATCH_SZ smaller by BATCH_RESERVED bytes
Iris allocates gem buffers using buckets of allocation sizes that are
page aligned. We always ask for batch buffers of size BATCH_SZ +
BATCH_RESERVED, which is not page aligned: we ask for 65552 bytes,
which ends up in the bucket of size 81920, resulting in 20% unused
space. Adjust things so there is no waste of space: BATCH_SZ +
BATCH_RESERVED is now 65536.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
2020-04-15 21:35:14 +00:00
Paulo Zanoni
103cb32c79 iris: remove useless bo->gtt_offset assignment
We assign a real value a few lines below, and none of the lines in
between rely on the zeroed bo->gtt_offset value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
2020-04-15 21:35:14 +00:00
Paulo Zanoni
c586cb23e0 iris: remove unnecessary forward declaration
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
2020-04-15 21:35:14 +00:00
Paulo Zanoni
f3f5016c0b iris: remove hole from struct iris_bo
This decreases the size of the struct on a 64bit machine from 144 to
136. While that's not a lot, this is one of the structs that we're
allocating all the time.

For a full Aztec run on BDW we allocate this struct 3273 times, and we
can have up to 3259 of them live at the same time. So we end up saving
just a little over 6 pages for this benchmark.

Spotted this while trying to add another bool for an unrelated
feature.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
2020-04-15 21:35:14 +00:00
Jon Turney
0158f73f08 Fix util/process test on Cygwin
It seems meson returns the filename with extension for full_path(), even
though Cygwin does it's best to pretend the file doesn't have that
extension.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4514>
2020-04-15 21:10:11 +00:00
Dave Airlie
befe2ff3a6 llvmpipe/nir: free the nir shader
Fixes: 18f896e55d (llvmpipe: add initial nir support)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4563>
2020-04-16 06:25:46 +10:00
Dave Airlie
cb0a2b3df6 draw/tess: free the NIR
Fixes: 0d02a7b8ca (draw: add main tessellation code)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4563>
2020-04-16 06:25:43 +10:00
Dave Airlie
f01c0565bb draw: free the NIR IR.
Not sure how I missed this, the ownership was a bit blurry,
free the NIR.

Fixes: bf12bc2dd7 (draw: add nir info gathering and building support)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4563>
2020-04-16 06:25:39 +10:00
Brian Ho
13ce637f1b freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEX
After some experimentation, I believe that GRAS_LAYER_CNTL is
actually just a count register storing the number of layers in the
render target. While debugging cube_array geometry tests, I noticed
that the blob was setting an unknown 0x8 to LAYER_CNTL, so I checked
the value of LAYER_CNTL for various layer sizes:

1: LAYER_CNTL=0
2: LAYER_CNTL=1
3: LAYER_CNTL=2
4: LAYER_CNTL=3
9: LAYER_CNTL=8
256: LAYER_CNTL=255
2000: LAYER_CNTL=1999

Seems like this register just stores a count of the largest layer
that can be written to via gl_Layer. This commit updates the reg
docs, freedreno's gs implementation, and turnip's gs implementation.

Fixes dEQP-VK.geometry.layered.cube_array.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4541>
2020-04-15 16:19:34 +00:00
Brian Ho
c2399e9574 turnip: Emit geometry shader descriptor consts
Without these consts, the geometry shader is unable to read from
textures or uniforms.

Fixes dEQP-VK.geometry.layered.*.readback

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4541>
2020-04-15 16:19:34 +00:00
Brian Ho
d6d5ee29ab turnip: Correctly set layer stride for 3D images
Previously we were using layout.layer_size for the layer stride, but
in Vulkan, you can alias a 3D image as an array of 2D images via the
VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT flag. One reason to use
this behavior is so the geometry shader can write to a specific
depth in a 3D framebuffer with gl_Layer.

Since the 3D image is not a *true* layered image, layer_size is 0.
Instead, we can copy what freedreno does and use the slice size.

Fixes dEQP-VK.geometry.layered.3d.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4541>
2020-04-15 16:19:34 +00:00
Karol Herbst
7e525d29ab gallium: initialize viewport swizzle in cso_set_viewport_dims
Fixes: dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_* and more
Fixes: 4137a79c2a ("gallium: add viewport swizzling state and cap")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4567>
2020-04-15 16:43:57 +02:00
Karol Herbst
1aefe78b47 mesa: fix enum value of VIEWPORT_SWIZZLE_POSITIVE_W_NV
Fixes: ff168b297d ("mesa: add GL_NV_viewport_swizzle support")
Reported-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4567>
2020-04-15 16:43:36 +02:00
Samuel Pitoiset
e2650db952 radv/aco: do not advertise VK_KHR_shader_subgroup_extended_types
It's unsupported because small bitsizes are still not completely
supported. It should have been disabled by default with ACO.

Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4549>
2020-04-15 14:45:43 +02:00
Karol Herbst
4ee2370972 nvc0: enable ASTC and ETC on GM20B
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4554>
2020-04-15 12:08:02 +00:00
Emil Velikov
22406da756 glx: omit loader_loader() for macOS
Earlier commit added the code unconditionally, since the loader code
itself is already built on macOS.
Although it did not consider the #include mayhem that src/glx is.

In particular, none of the __GLXDRI{screen,context,drawable) are
available for macOS... those are pulled by dri_common.[ch].

Ideally we'll untangle that, but for the time being simply #ifdef out
the include/call.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2726
Fixes: b699d070a6 ("glx: set the loader_logger early and for everyone")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4490>
2020-04-15 11:37:21 +00:00
Karol Herbst
471fd41e84 clover: expose cl_arm_shared_virtual_memory for devices with SVM support
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
657ff3b3b8 clover: implement cl_arm_shared_virtual_memory
v2: use static array to keep name -> func mapping
v3: use unordered_map
v4: handle ARM constants
    reorder dispatch table
    wrap enqueue APIs as the command value differs between khr and arm
v5: move declarations into dispatch.hpp
    handle CL_MEM_USES_SVM_POINTER_ARM in clGetMemObjectInfo
v6: breaking long lines

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
a218658556 clover: implement SVM functions for devices with fine grained system SVM support
all of the functionality can be mapped to malloc/free if the device supports
fine grained system SVM.

v2: fix some API bugs found with the OpenCL CTS
v3: remove validate_even_wait_list
    improve implementation of clSetKernelExecInfo
    make clEnqueueSVMFree spec compliant
    rename can_emulate_non_system_svm to has_system_svm and make it a member method
    improve validation in clEnqueueSVMMemFill
    handle CL_MEM_USES_SVM_POINTER in clGetMemObjectInfo
v4: break long lines and other minor cosmetic adjustments

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
d6754eb920 clover: implement clSetKernelArgSVMPointer
it is pretty much identical to a clSetKernelArg for a scalar field, except
it is only valid for global and constant memory pointers.

Also the type equals void* on the Host, so we can just check the size of it.

v2: prefer using target_size to extend the pointer value
v3: handle more corner cases in combiation to clSetKernelArg

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
035e882819 clover: implement CL_DEVICE_SVM_CAPABILITIES
v2: without supporting userptrs SVM can't be implemented as it's impossible
    to ensure memory consistency with HOST_PTR buffers
v3: fix comment style
v4: fixes typo in comment

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
c170c0cfe4 clover: add stubs for SVM
although most of those are 2.0 core functions, there is
cl_arm_shared_virtual_memory to expose those in a 1.2 context. But we
should be able to expose this extension with 1.1 as well as there is no
technicaly reason why this shouldn't work.

v2: move svm functions into existing files
v3: rename func args to match convention

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Karol Herbst
e738967d6e gallium: add PIPE_CAP_SYSTEM_SVM
v2: split enum in specific caps to abstract the CL enum
v3: remove BUFFER_SVM caps

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2076>
2020-04-15 11:08:13 +00:00
Rhys Perry
c818b5c089 aco: fix 1D textureGrad() on GFX9
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 6f718edced ('aco: simplify gathering of MIMG address components')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4550>
2020-04-15 10:45:07 +00:00
Lionel Landwerlin
8ce46f352e iris: drop cache coherent cpu mapping for external BO
We have to assume any external buffer could be used by the display HW.
In the case that buffer is also CPU mapped, we want to assume no cache
coherency as it is only available between GT & CPU, not display.

Many thanks to Michel Dänzer for the hint!

v2: Move cache coherent drop to bufmgr (Chris)

v3: Also make BO external if created with PIPE_BIND_SHARED (Eric)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2552
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4533>
2020-04-15 09:01:52 +00:00
Samuel Pitoiset
08a396033b aco: fix nir_op_frexp_exp with 16-bit floats and negative exponents
v_frexp_exp_i16_f16 returns the two's complement for negative
exponents. For example, with 0.333252 it returns 0.666504 for
the mantissa and 65535 for the exponent (-1 in decimal).

RADV/LLVM and AMDVLK do a v_bfe_i32 and AMDGPU-PRO uses SDWA with
the sign extension bit set. The latter is probably what we want to
do in long term but for now RA doesn't support changing non-SDWA
instructions to SDWA if useful/needed.

Fixes dEQP-VK.glsl.builtin.precision_fp16_storage16b.frexp.compute.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4546>
2020-04-15 10:12:44 +02:00
Dave Airlie
9bf8e92386 u_blitter: fix stencil blitting
Fixes: KHR-GL45.packed_depth_stencil.blit.depth32f_stencil8

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:33 +10:00
Dave Airlie
381e9fe64a draw: fix user culling pipeline order. (v2)
GL spec requires user culling, then clipping then face culling.
llvmpipe was doing clipping then user culling then face culling.

Fix the ordering by adding a new user_cull stage that does the user
culling

Fixes piglit clip_cull-4.shader_test

v2: simplify this a lot (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:29 +10:00
Dave Airlie
30ef6f5137 draw/cull: run pipeline for culled points.
This just appears to be missing:
Fixes:
KHR-GL45.cull_distance.functional

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:24 +10:00
Dave Airlie
dc261cdd42 llvmpipe/setup: move line stats collection earlier.
You have to count the stats pre-culling here.

Fixes:
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:20 +10:00
Dave Airlie
80fa8304c8 draw: fix tessellation stats query
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:17 +10:00
Dave Airlie
335827eade llvmpipe: fix no tokens detections.
this only applies to the TGSI path, fixes
KHR-GLES31.core.geometry_shader.api.program_pipeline_vs_gs_capture

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:14 +10:00
Dave Airlie
ccc6a48ec5 gallivm/draw: calloc prim id toavoid undef
Otherwise masked off channels can access random bad memory

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:11 +10:00
Dave Airlie
e20b3b3720 gallivm/nir: lower implicit lod to tex.
Fixes some sampling issues in vertex shaders

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:08 +10:00
Dave Airlie
c494ed0467 gallivm: fix left over shader vote debug
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:06 +10:00
Dave Airlie
7690606bf7 llvmpipe/query: fix transform feedback overflow any queries.
The any queries need to signal if any stream has overflowed,
so we have to track all the streams.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:03 +10:00
Dave Airlie
96e12ca7d7 llvmpipe: report tessellation shader statistics.
Fixes KHR-GL45.pipeline_statistics_query_tests_ARB.functional_tess_queries

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:26:00 +10:00
Dave Airlie
202bc38ce9 draw: collect tessellation invocations statistics
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:25:56 +10:00
Dave Airlie
f4edc6f8bd llvmpipe: fixup context leaks.
Make sure we unreference all resources for all shaders on context
destruction.

Fixes: eb5227173f (llvmpipe: add support for tessellation shaders)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4560>
2020-04-15 14:25:50 +10:00
Vinson Lee
68b40cfe27 swr: Remove Byte Order Mark.
before:
$ file src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_types.py
src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_types.py: Python script text executable, UTF-8 Unicode (with BOM) text

after:
$ file src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_types.py
src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_types.py: Python script text executable, ASCII text

This patch also fixes this build error.

  File "src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_types.py", line 1

    # Copyright (C) 2014-2018 Intel Corporation.   All Rights Reserved.

    ^

SyntaxError: invalid character in identifier

Fixes: c6e67f5a93 ("gallium/swr: add OpenSWR rasterizer")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4221>
2020-04-14 13:23:38 -07:00
Danylo Piliaiev
600c91fed8 glsl/list: Fix undefined behaviour of foreach_* macros
These macros produced a lot of errors with ubsan preventing us from
expanding the ubsan coverage on CIs.

C++ spec has such clause:

 "If the prvalue of type "pointer to cv1 B" points to a B that is
  actually a subobject of an object of type D, the resulting pointer
  points to the enclosing object of type D. Otherwise, the result
  of the cast is undefined."

Ubsan error example:

 ../src/compiler/glsl/builtin_functions.cpp:4945:4: runtime error: downcast of address 0x559b926abb50 which does not point to an object of type 'ir_instruction'
 0x559b926abb50: note: object has invalid vptr
  9b 55 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  58 ba 6a 92 9b 55 00 00  01 00 00 00
               ^~~~~~~~~~~~~~~~~~~~~~~
               invalid vptr
     #0 0x559b914dbe1a in call ../src/compiler/glsl/builtin_functions.cpp:4945

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4129>
2020-04-14 19:29:38 +00:00
Jonathan Marek
23be216071 freedreno/ir3: don't overwrite wrmask in ir3_SAM
Fixes (with other patches to allow these tests to run):

dEQP-VK.ycbcr.query.size_lod.vertex.*

Suggested-by: Rob Clark <robclark@gmail.com>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4557>
2020-04-14 19:12:47 +00:00
Jonathan Marek
aeb5b9cebf freedreno/ir3: fix emit_tex_info split_dest
Fixes a "free(): invalid next size (fast)" error in:

dEQP-VK.glsl.texture_functions.query.texturequerylevels.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4557>
2020-04-14 19:12:47 +00:00
Gert Wollny
cb08f451d0 gallium/tgsi_to_nir: Set nir_intrinsic_align_mul to 16 and offset to 0
Since the alignment is now checked in the validator we must set it.

v2: Use alignement of 4, i.e. dest bit size by eight.
v3: Use alignment 16 (Rhys Perry & Jason Ekstand)
v4: Use nir_intrinsic_set_align to make it clear that align offset is 0
    (Jason)

Fixes: e78a7a1825
    nir: Assert memory loads are aligned

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4544>
2020-04-14 18:47:09 +00:00
Connor Abbott
31988baba4 ir3: Fix txs with bindless
I missed that this had a micro-optimization to assume that there was
only ever one source, which is no longer valid for the bindless model
since we now have a bindless handle source. Remove the optimization to
fix assertion failures with turnip.

Fixes e.g.
dEQP-VK.glsl.texture_functions.query.texturesize.sampler2d_fixed_vertex

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4548>
2020-04-14 16:25:34 +00:00
Andres Gomez
acf7e73be5 gitlab-ci: make explicit tracie is gitlab specific
Tracie main script and traces.yml file talk about repo(sitory) when it
actually means GitLab's project.

Since the script is GitLab's API specific, make it clear.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4496>
2020-04-14 16:07:28 +03:00
Andres Gomez
1ca91683e2 gitlab-ci: protect usage of shell variables with double quotes
Not really needed right now, but seems dangerous to have paths without
the double quote.

I went ahead and used in the rest of values too.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4496>
2020-04-14 16:07:19 +03:00
Andres Gomez
35782b6593 gitlab-ci: Vulkan tracie runner to return last command exit code
No need to cache the return value if there is only a single trace
execution call.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4496>
2020-04-14 16:06:51 +03:00
Alexandros Frantzis
4c6ce826af gitlab-ci: Check the Mesa version used for tracie tests
Verify that the Mesa version used when running tracie tests is the
one that was built by CI, rather than any installed distro version.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3894>
2020-04-14 11:34:02 +00:00
Rhys Perry
fbd2be3f5d aco: clear moved operands in get_reg_create_vector()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4507>
2020-04-14 10:49:12 +00:00
Rhys Perry
52cc1f8237 aco: improve p_create_vector RA for sub-dword operands
These's still improvements needed for sub-dword definitions, but that's
not as simple.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4507>
2020-04-14 10:49:12 +00:00
Rhys Perry
e18711cda3 aco: fix p_extract_vector validation
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4507>
2020-04-14 10:49:12 +00:00
Rhys Perry
41ac44e1b3 aco: improve vector optimization with sub-dword vectors
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4507>
2020-04-14 10:49:12 +00:00
Samuel Pitoiset
849eb0a776 radv: use RMW packets for updating the maximum sample distance
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4531>
2020-04-14 11:31:37 +02:00
Samuel Pitoiset
cb6ab17d1f radv: add radeon_set_context_reg_rmw() helper
For emitting RMW packets in the command stream. This new helper
will be useful for implementing extended dynamic states to only
overwrite the fields that need to be updated instead of storing
more values in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4531>
2020-04-14 11:31:33 +02:00
pal1000
f0b94262c1 scons/windows: Support build with LLVM 10.
LLVM engine component contains 2 new libraries, LLVMCFGuard and LLVMTextAPI.
Without them build fails like in this run: https://ci.appveyor.com/project/Alexpux/mingw-packages/builds/32102425/job/wkmb4gimfqkkb3cg

Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4521>
2020-04-14 08:40:56 +00:00
Tobias Jakobi
c38946e62d meson: Link Gallium Nine with ld_args_build_id
This fixes an assertion in iris_disk_cache_init() when the initialization
goes through drm_create_adapter(), which lives in d3dadapter9.so.
In this case build_id_find_nhdr_for_addr() fails and returns NULL, since
the shared library does not include a build ID.

The issue can be reproduced with an iris capable GPU and Xnine, while
removing the shader cache prior to launching the application.

Fix this by doing the same as in 29ea92e6a1.

Fixes: 4756864cdc "iris: Start wiring up on-disk shader cache"
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4499>
2020-04-14 00:22:45 +00:00
Greg V
924f3f3de7 svga: fix build on FreeBSD
MADV_HUGEPAGE only exists on Linux

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3966>
2020-04-13 23:51:43 +00:00
Eric Anholt
9ce4db6231 freedreno/a5xx+: Skip compiling the old gmem blit programs.
Saves a bunch of noise for me to sort through in IR3_SHADER_DEBUG=vs,fs
shader-db/run <single shader_test>.  I found that we were crashing on
destroy of NULL programs in fd_prog_fini, so I replicated the gpu_id < 300
early exit from fd_prog_init() down to _fini as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4538>
2020-04-13 22:50:58 +00:00
Alyssa Rosenzweig
2513d0257c pan/bit: Add BI_CONVERT tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
9f50b19534 pan/bit: Add BI_CONVERT interpretation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
640d69d166 pan/bi: ADD packing for CONVERT
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
8cfe660326 pan/bi: Rewrite conversion packing
To support roundmodes and other goodies.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
0b000c54c0 pan/bi: Fix incorrect swizzle packing assert
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
d0cf8b977c pan/bi: Set BI_ROUNDMODE for BI_CONVERT
It's rarely used in GL but converts do have roundmodes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Alyssa Rosenzweig
2799353f5b pan/midgard: Fix f2u naming confusion
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
2020-04-13 22:32:40 +00:00
Matt Turner
e4268ffb99 meson: Specify the maximum required libdrm in dri.pc
When dealing with a regression in libdrm-2.4.101, I masked the package
in Gentoo. In doing so, we discovered that Mesa's dri.pc specifies a
version requirement in dri.pc for >= the version of libdrm Mesa was
built against, thus preventing packages from being rebuilt with the
older version of libdrm installed.

Let's reduce this version requirement to the latest libdrm required by
Mesa instead, since libdrm is backward compatible.

Fixes: a3a16d4aa7 ("meson: use dep_libdrm version for pkg-config")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4534>
2020-04-13 22:07:41 +00:00
Rob Clark
4b24b9647d freedreno/ir3/ra: cleanup some leftovers
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
751c11a8c7 freedreno/ir3: rename depth->dce
Since DCE is the only remaining function of this pass, after the pre-RA
scheduler rewrite.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
cf74048fd1 freedreno/ir3: better cleanup when removing unused instructions
Do a better job of pruning when removing unused instructions, including
cleaning up dangling false-deps.

This introduces a new ssa src pointer iterator, which makes it easy to
clear links without having to think about whether it is a normal ssa
src or a false-dep.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
96ff2a4099 freedreno/ir3/ra: handle array case for SFU select_reg opt
The src of the SFU instruction could also be array/reg (non-SSA).
Handle this case too.

The postsched cp pass makes this scenario more likely.

Fixes: cc82521de4 ("freedreno/ir3: round-robin RA")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
b787b353d0 freedreno/ir3: add mov/cov stats
While not always avoidable, cov instructions are a useful thing to look
at to see if we could fold into src.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
89a78a07de freedreno/ir3/postsched: avoid moving tex ahead of kill
Add extra dependencies of tex/mem instructions on previous kill
instructions to avoid moving them ahead of kills.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
017fdab217 freedreno/ir3/postsched: remove some leftovers
These aren't used in postsched.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
9701008d64 freedreno/ir3/sched: awareness of partial liveness
Realize that certain instructions make a vecN live, and account for
this, in hopes of scheduling the remaining components of the vecN
sooner.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
d2f4d332db freedreno/ir3: new pre-RA scheduler
This replaces the depth-first search scheduler with a more traditional
ready-list scheduler.  It primarily tries to reduce register pressure
(number of live values), with the exception of trying to schedule kills
as early as possible.  (Earlier iterations of this scheduler had a
tendency to push kills later, and in particular moving texture fetches
which may not be necessary ahead of kills.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
0f22f85fe7 freedreno/ir3: fix location of inserted mov's
If the group pass must insert a mov to resolve conflicts, avoid the mov
appearing *after* the meta:collect whose src it is.

The current pre-RA scheduler doesn't really care about the initial
instruction order, but the new one will in some cases.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
908044ef4b freedreno/ir3: simplify grouping pass
Since bdf6b7018c the logic only needs to
handle grouping collect srcs, So remove the now unnecessary indirection.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
860f5981f0 freedreno/ir3: make falsedep use's optional
Add option when collecting uses to control whether they include
falsedeps or not.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Rob Clark
d09e3afdcc freedreno/ir3: spiff out disasm a bit
for verbose mode, print also the instruction "cycle" (which takes into
account (rptN) and (nopN)) in addition to instruction offset.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
2020-04-13 20:47:28 +00:00
Jonathan Marek
40ccbae622 freedreno/computerator: support bindless sampler instructions
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4526>
2020-04-13 20:15:48 +00:00
Jonathan Marek
bc9a28beed freedreno/computerator: support nop prefix
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4526>
2020-04-13 20:15:48 +00:00
Eric Anholt
95d4a956c0 freedreno/ir3: CSE the up/downconversion of SEL's cond's size.
Not many programs hit this, but if you were, say, selecting between vec4s,
you'd convert the cond 4 times.

instructions in affected programs: 2957 -> 2717 (-8.12%)
nops in affected programs: 989 -> 899 (-9.10%)
non-nops in affected programs: 1968 -> 1818 (-7.62%)
dwords in affected programs: 3232 -> 2752 (-14.85%)
last-baryf in affected programs: 102 -> 90 (-11.76%)
full in affected programs: 5 -> 4 (-20.00%)
sstall in affected programs: 329 -> 329 (0.00%)
(ss) in affected programs: 86 -> 105 (22.09%)
(sy) in affected programs: 14 -> 12 (-14.29%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4516>
2020-04-13 19:24:52 +00:00
Eric Anholt
82375ccaa4 freedreno/ir3: Stop doing b2n on the SEL condition.
SEL_B32 (and presumably B16) checks for 0 or nonzero in the condition
(tested by just stuffing a uniform's value into it), so there's no need to
do ir3_b2n() on it, or any preceding ir3_n2b().

instructions in affected programs: 664444 -> 659927 (-0.68%)
nops in affected programs: 267898 -> 266312 (-0.59%)
non-nops in affected programs: 420260 -> 417329 (-0.70%)
dwords in affected programs: 144032 -> 137568 (-4.49%)
last-baryf in affected programs: 10801 -> 10321 (-4.44%)
full in affected programs: 2003 -> 2002 (-0.05%)
sstall in affected programs: 76670 -> 77405 (0.96%)
(ss) in affected programs: 4515 -> 4525 (0.22%)
(sy) in affected programs: 612 -> 604 (-1.31%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4516>
2020-04-13 19:24:52 +00:00
Ian Romanick
0d1917da86 tnl: Code formatting in t_rebase.c
Many little changes.  Almost everything is indentation or removal of
trailing whitespace.  Some places move a loop variable declaration to
the loop.  Some comments either re-wrapped or converted to single
line.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:27:00 -07:00
Ian Romanick
887ae78718 tnl: Code formatting in t_draw.c
So many little changes.  Almost everything is indentation or removal of
trailing whitespace.  There's a couple places where an "else" is moved
to the previous line with the "}".  Some places move a loop variable
declaration to the loop.  One change of assert to unreachable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:57 -07:00
Ian Romanick
ac13258a6e tnl: Silence unused parameter warnings in _tnl_split_inplace
Unused since db0eb3a437 ("vbo: Fix up in-place splitting for non-contiguous/indexed primitives.") which landed in 2010.

src/mesa/tnl/t_split_inplace.c: In function ‘_tnl_split_inplace’:
src/mesa/tnl/t_split_inplace.c:270:27: warning: unused parameter ‘min_index’ [-Wunused-parameter]
  270 |                    GLuint min_index,
      |                    ~~~~~~~^~~~~~~~~
src/mesa/tnl/t_split_inplace.c:271:27: warning: unused parameter ‘max_index’ [-Wunused-parameter]
  271 |                    GLuint max_index,
      |                    ~~~~~~~^~~~~~~~~

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:54 -07:00
Ian Romanick
7a004f7987 tnl: Silence unused parameter warnings in dump_draw_info
src/mesa/tnl/t_split_copy.c: In function ‘dump_draw_info’:
src/mesa/tnl/t_split_copy.c:149:35: warning: unused parameter ‘ctx’ [-Wunused-parameter]
  149 | dump_draw_info(struct gl_context *ctx,
      |                ~~~~~~~~~~~~~~~~~~~^~~
src/mesa/tnl/t_split_copy.c:154:23: warning: unused parameter ‘min_index’ [-Wunused-parameter]
  154 |                GLuint min_index,
      |                ~~~~~~~^~~~~~~~~
src/mesa/tnl/t_split_copy.c:155:23: warning: unused parameter ‘max_index’ [-Wunused-parameter]
  155 |                GLuint max_index)
      |                ~~~~~~~^~~~~~~~~

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:51 -07:00
Ian Romanick
114e078001 tnl: Silence unused parameter warnings in _tnl_draw_prims
A tangled mess of a couple parameters that nobody wanted.

src/mesa/tnl/t_draw.c: In function ‘_tnl_draw_prims’:
src/mesa/tnl/t_draw.c:440:42: warning: unused parameter ‘tfb_vertcount’ [-Wunused-parameter]
  440 |     struct gl_transform_feedback_object *tfb_vertcount,
      |     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~
src/mesa/tnl/t_draw.c:441:35: warning: unused parameter ‘stream’ [-Wunused-parameter]
  441 |                          unsigned stream)
      |                          ~~~~~~~~~^~~~~~

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:48 -07:00
Ian Romanick
1996f1d3dd tnl: Silence unused parameter 'attrib' warning in convert_half_to_float
Also clean up some trivial code / whitespace style issues.

src/mesa/tnl/t_draw.c: In function ‘convert_half_to_float’:
src/mesa/tnl/t_draw.c:121:57: warning: unused parameter ‘attrib’ [-Wunused-parameter]
  121 |                       const struct gl_array_attributes *attrib,
      |                       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:45 -07:00
Ian Romanick
7a03240b63 tnl: Don't dereference NULL obj pointer in t_rebase_prims
Structurally the code is now similar to the handling of other
gl_buffer_object::obj pointers elsewhere in TNL.  The fixes tag is a
little bit misleading.  I think the change in that commit just exposes a
previously existing bug.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2746
Fixes: f3cce7087a ("mesa: don't ever bind NullBufferObj for glBindBuffer targets")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:43 -07:00
Ian Romanick
2e43b32e72 tnl: Don't dereference NULL obj pointer in replay_init
Structurally the code is now similar to the handling of other
gl_buffer_object::obj pointers elsewhere in TNL.  The fixes tag is a
little bit misleading.  I think the change in that commit just exposes a
previously existing bug.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2746
Fixes: f3cce7087a ("mesa: don't ever bind NullBufferObj for glBindBuffer targets")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:40 -07:00
Ian Romanick
65f14fd68d tnl: Don't dereference NULL obj pointer in bind_indices
Structurally the code is now similar to bind_inputs.  The fixes tag is a
little bit misleading.  I think the change in that commit just exposes a
previously existing bug.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2746
Fixes: f3cce7087a ("mesa: don't ever bind NullBufferObj for glBindBuffer targets")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4512>
2020-04-13 10:26:38 -07:00
Daniel Schürmann
28d36d26c2 aco: fix p_extract_vector optimization in presence of unequally sized vector operands
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4506>
2020-04-13 16:35:40 +00:00
Alyssa Rosenzweig
0e4432bfba pan/bi: Lower fsqrt
For G72+ anyway. G71 will want something a bit more fine grained. I hope
this has enough precision for GL (the blob apparently does some exponent
fixup).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4530>
2020-04-13 15:44:31 +00:00
Alyssa Rosenzweig
3025ea6abe panfrost: Drop dependency on nonexistant write_value
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4530>
2020-04-13 15:44:31 +00:00
Tapani Pälli
53e4159eaa glsl: stop processing function parameters if error happened
Fixes: d1fa69ed61 ("glsl: do not attempt assignment if operand type not parsed correctly")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2696
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4341>
2020-04-13 15:53:15 +03:00
Samuel Pitoiset
fc1068de0d aco: fix nir_op_pack_32_2x16_split if one operand is a constant
Because 16-bit constants are represented with the s1 RegClass, we
have to extract the low half.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4509>
2020-04-13 11:51:17 +00:00
Samuel Pitoiset
4cfaef68d7 aco: implement 16-bit nir_op_f2i64/nir_op_f2u64
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4509>
2020-04-13 11:51:17 +00:00
Samuel Pitoiset
729bdc0d70 aco: fix f2i64/f2u64 with sgprs if the exponent computation overflow
This fixes f16->{i64,u64} conversions for +0/-0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4509>
2020-04-13 11:51:17 +00:00
Michel Dänzer
6a8e5dde66 gitlab-ci: Use all_paths in .test-manual rules
Without this, the .test-manual jobs could end up as 'when: manual' when
the jobs they depend on were 'when: never', which was flagged as
invalid YAML, preventing the pipeline from being created.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4522>
2020-04-13 10:29:48 +00:00
Ilia Mirkin
5e6267b20b nvc0: add NV_viewport_swizzle support for GM200+
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4519>
2020-04-12 12:01:46 -04:00
Ilia Mirkin
90fcb3fef2 st/mesa: add NV_viewport_swizzle support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4519>
2020-04-12 12:01:46 -04:00
Ilia Mirkin
ff168b297d mesa: add GL_NV_viewport_swizzle support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4519>
2020-04-12 12:01:46 -04:00
Ilia Mirkin
4137a79c2a gallium: add viewport swizzling state and cap
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4519>
2020-04-12 12:01:46 -04:00
Tapani Pälli
e2457bedd3 glsl: remove redudant assignment
CID: 1461087
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4500>
2020-04-12 16:48:53 +03:00
Tapani Pälli
e667802a7c mesa: remove redudant assignment
CID: 1461397
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4500>
2020-04-12 16:48:45 +03:00
Tapani Pälli
fd24172200 mesa: remove redudant check
CID: 1461410
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4500>
2020-04-12 16:48:27 +03:00
Qiang Yu
25a61cce7d lima: set offset when export resource
We missed set reource offset.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4517>
2020-04-12 10:02:24 +00:00
Lionel Landwerlin
4094558e86 i965: share buffer managers across screens
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
2020-04-11 22:04:37 +03:00
Lionel Landwerlin
865b840a6b i965: store DRM fd on intel_screen
v2: Fix storing of drm fd (Ajax)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
2020-04-11 22:04:33 +03:00
Lionel Landwerlin
0a497eb130 iris: make resources take a ref on the screen object
Because St creates resources from a screen and attach them onto
another we need to ensure the resources associated to a screen &
bufmgr stay around until we don't need them anymore.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
2020-04-11 22:04:28 +03:00
Lionel Landwerlin
7557f16059 iris: share buffer managers accross screens
St happilly uses pipe_resources created with one screen with other
screens. Unfortunately our resources have a single identifier that
related to a given screen and its associated DRM file descriptor.

To workaround this, let's share the buffer manager between screens for
a given DRM device. That way handles are always valid.

v2: Don't forget to close the fd that bufmgr now owns
    Take a copy of the fd to ensure it stays alive even if the dri
    layer closes it

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
2020-04-11 22:04:25 +03:00
Lionel Landwerlin
bd3e505453 iris: properly free resources on BO allocation failure
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
2020-04-11 22:04:22 +03:00
Rob Clark
7aa6720ba4 freedreno/log: better decoding for multiple chunks per batch
For larger render targets or smaller GMEM size, we could end up needing
multiple chunks of tracepoints per batch.  But we still want to decode
the traces as single batch.  So we need a bit of a state across
process_chunk() calls to accumulate timestamp information.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4510>
2020-04-10 19:29:54 +00:00
Rob Clark
7aa55f5acb freedreno/log: spiff out parser some more
Extract breakdown of time in GMEM passes.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4510>
2020-04-10 19:29:54 +00:00
Rob Clark
b5b32387d6 freedreno/log: android support
In particular, when stdout doesn't go anywhere useful we need to log to
file.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4510>
2020-04-10 19:29:54 +00:00
Eric Anholt
904d5d63b4 freedreno: Fix leak of binning shader variants.
The v->binning variant is never added to shader->variants, so just free
each one as we free the nonbinning variant.

Noticed from drm-shim mode running out of open fds, since each bo ends up
with an fd.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4502>
2020-04-10 18:42:20 +00:00
Kristian H. Kristensen
5ec1f264f1 freedreno/ir3: Fix sz vs class confusion
Add bounds checking to make sure we don't silently access out of
bounds again.

Fixes: 90f7d12236 ("freedreno/ir3/ra: pick higher numbered scalars in first pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4503>
2020-04-10 10:24:14 -07:00
Alyssa Rosenzweig
65e2eaa4d3 pan/decode: Print Bifrost blend descriptor
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:54:02 +02:00
Alyssa Rosenzweig
80dd692813 pan/bi: Let !b2b imply branch_cond
Like the blob. Probably doesn't matter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:59 +02:00
Alyssa Rosenzweig
3439c24bdb panfrost: Fix BI_BLEND packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:57 +02:00
Alyssa Rosenzweig
e34add229f pan/bi: Fix backwards registers ports
Will matter when packing multiple instructions per bundle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:56 +02:00
Alyssa Rosenzweig
23620d1830 panfrost: Pass compiler-appropriate options
FMAs need to fuse for Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:54 +02:00
Alyssa Rosenzweig
e30091bc51 panfrost: Move uniform_count to pan_assemble
Again, not Midgard specific.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:53 +02:00
Alyssa Rosenzweig
d10423989e panfrost: Move varying linking to cmdstream
This isn't ISA/compiler specific, it's just looking at the NIR. So let's
move it from midgard to pan_assemble.c so it runs for Bifrost too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:51 +02:00
Alyssa Rosenzweig
776697dd34 pan/midgard: Remove unused max_varying variable
I don't know why this was here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:50 +02:00
Alyssa Rosenzweig
90e02db9a1 pan/bi: Fix nondeterministic register packing
Uninitialized read.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:48 +02:00
Alyssa Rosenzweig
8016906cf2 panfrost: Call the Bifrost compiler on bi devices
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:47 +02:00
Alyssa Rosenzweig
0a9fa4bcb6 panfrost: Set mfbd.msaa.sample_locations on Bifrost
And mfbd.shared_memory only on Midgard.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:44 +02:00
Tomeu Vizoso
46e4246d49 panfrost: On Bifrost, set the right tiler descriptor
On both fragment and tiler jobs.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:39 +02:00
Tomeu Vizoso
547f999e2c panfrost: Don't emit write_value jobs on Bifrost
As on Bifrost GPUs there's a different mechanism for reusing the tiler
data structures.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:31 +02:00
Tomeu Vizoso
30e7027e1c panfrost: Pass IS_BIFROST to pandecode_jc
So we can decode the right structures on Bifrost hw.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:21 +02:00
Tomeu Vizoso
7b10d4ece6 panfrost: Remove most usage of midgard_payload_vertex_tiler
By passing the prefix and postfix structs around, we can use most of the
cmdstream functions as well for bifrost, as those structs haven't
changed between midgard and bifrost.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:53:03 +02:00
Alyssa Rosenzweig
b010a6d5f1 panfrost: Unify vertex/tiler structures
Some fields were shuffled but these are essentially the same across the
generations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:52:59 +02:00
Alyssa Rosenzweig
aee68b06c8 panfrost: Staticize a few cmdstream functions
They are only used within the same source file.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:52:56 +02:00
Alyssa Rosenzweig
dd09571c77 panfrost: Populate bifrost-specific structs within mali_shader_meta
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:52:54 +02:00
Alyssa Rosenzweig
b096a1dbd3 panfrost: Add IS_BIFROST quirk
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
2020-04-10 16:51:57 +02:00
Christian Gmeiner
693480a581 etnaviv: remove the "active" member of queries
The state tracker only gets to begin/query/destroy when !active and end
when active, so we have no need to try to track this ourselves.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>
2020-04-10 12:42:24 +00:00
Christian Gmeiner
7cb98e02e4 etnaviv: change begin_query(..) to a void function
We always return true.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>
2020-04-10 12:42:24 +00:00
Christian Gmeiner
7a9cbb2b61 etnaviv: drop redundant calls to etna_acc_query_suspend(..)
Introduced by accident during rebase.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>
2020-04-10 12:42:24 +00:00
Jose Maria Casanova Crespo
b06fdb8edd v3d: Primitive Counts Feedback needs an extra 32-bit padding.
Store Primitive Counts operations write 7 counters in 32-bit words
but also a padding 32-bit with 0. So we need 8 32-bit words instead
of the current 7 allocated.

This was causing an corruption in the next buffer when Transform
Feedback was enabled that were exposed on tests like:
dEQP-GLES3.functional.transform_feedback.*.points.*

This patch fixes 196 tests that were failing when they were run isolated
but they were passing when run using cts-runner.

Fixes: 0f2d1dfe65 ("v3d: use the GPU to record primitives written to transform feedback")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2674
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4501>
2020-04-10 10:02:56 +02:00
Daniel Schürmann
38622de2ec aco: make some reg_file helpers private and fix their uses
Fixes various subdword RA issues

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Daniel Schürmann
331794495e aco: rename aco_lower_bool_phis() -> aco_lower_phis()
We also lower subdword phis, now.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Daniel Schürmann
1d41521b16 aco: lower subdword phis with SGPR operands
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Daniel Schürmann
a39df3bfce aco: don't constant-propagate into subdword PSEUDO instructions
PSEUDO instructions are lowered using SDWA, and thus,
cannot take literals and before GFX9 cannot take constants
at all. As the in-register representation differs between
32bit and 16bit floats, we first need to ensure correct
behavior.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Daniel Schürmann
1de18708cb aco: ensure correct bit representation of subdword constants
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Daniel Schürmann
637f45f390 aco: setup subdword regclasses for ssa_undef & load_const
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>
2020-04-10 07:19:27 +00:00
Samuel Pitoiset
67b567d0d0 aco: implement nir_op_b2f16/nir_op_i2f16/nir_op_u2f16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
3119f978e5 aco: implement 16-bit comparisons
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
ccf8e23f59 aco: implement 16-bit nir_op_fmax3/nir_op_fmin3/nir_op_fmed3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
981ced07a5 aco: implement 16-bit nir_op_ldexp
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
55537ed9d3 aco: implement 16-bit nir_op_f2i32/nir_op_f2u32
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
68339ff7a7 aco: implement 16-bit nir_op_bcsel
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
0646562a17 aco: implement 16-bit nir_op_fsign
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
6793ae1c5e aco: implement 16-bit nir_op_fsat
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
0ecca65d11 aco: implement 16-bit nir_op_fmul
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
b0c60999bc aco: implement 16-bit nir_op_fcos/nir_op_fsin
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
9be4be515f aco: implement 16-bit nir_op_fsub/nir_op_fadd
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
b0b637ca17 aco: implement 16-bit nir_op_fabs/nir_op_fneg
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
acc5912786 aco: implement 16-bit nir_op_fmax/nir_op_fmin
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
66d5bfb09a aco: implement 16-bit nir_op_ffloor/nir_op_fceil
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
c097c9f20c aco: implement 16-bit nir_op_fsqrt/nir_op_frcp/nir_op_frsq
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
26ed9fb79e aco: implement 16-bit nir_op_ftrunc/nir_op_fround_even
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
ee96181ad9 aco: implement 16-bit nir_op_fexp2/nir_op_flog2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:05 +02:00
Samuel Pitoiset
b8486041df aco: implement 16-bit nir_op_ffract
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:04 +02:00
Samuel Pitoiset
a8b45d7034 aco: implement 16-bit nir_op_frexp_sig/nir_op_frexp_exp
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>
2020-04-10 08:05:04 +02:00
Caio Marcelo de Oliveira Filho
db74ad0696 intel/compiler: Remove cs_prog_data->threads
At this point all drivers are doing this math on their own -- since
most of them need to cover the variable group size case, in which at
compile time the group size (and number of threads) is not defined.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:20 -07:00
Caio Marcelo de Oliveira Filho
9ff55621d9 iris: Stop using cs_prog_data->threads
This is a preparation for dropping this field since this value is
expected to be calculated by the drivers now for variable group size
case.  And also the field would get in the way of brw_compile_cs
producing multiple SIMD variants (like FS).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:12 -07:00
Caio Marcelo de Oliveira Filho
928f5f5434 anv: Stop using cs_prog_data->threads
Move the calculation to helper functions -- similar to what GL already
needs to do.

This is a preparation for dropping this field since this value is
expected to be calculated by the drivers now for variable group size
case.  And also the field would get in the way of brw_compile_cs
producing multiple SIMD variants (like FS).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:12 -07:00
Plamena Manolova
5664bd6db3 i965: Implement ARB_compute_variable_group_size
This patch adds the implementation of ARB_compute_variable_group_size
for i965. We do this by storing the local group size in a push constant.

Additional changes made by Caio Marcelo de Oliveira Filho.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:12 -07:00
Plamena Manolova
c77dc51203 intel/compiler: Add support for variable workgroup size
Add new builtin parameters that are used to keep track of the group
size.  This will be used to implement ARB_compute_variable_group_size.

The compiler will use the maximum group size supported to pick a
suitable SIMD variant.  A later improvement will be to keep all SIMD
variants (like FS) so the driver can select the best one at dispatch
time.

When variable workgroup size is used, the small workgroup optimization
is disabled as it we can't prove at compile time that the barriers
won't be needed.

Extracted from original i965 patch with additional changes by
Caio Marcelo de Oliveira Filho.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:12 -07:00
Caio Marcelo de Oliveira Filho
c54fc0d07b intel/compiler: Replace cs_prog_data->push.total with a helper
The push.total field had three values but only one was directly
used (size).  Replace it with a helper function that explicitly takes
the cs_prog_data and the number of threads -- and use that in the
drivers.

This is a preparation for ARB_compute_variable_group_size where the
number of threads (hence the total size for push constants) is not
defined at compile time (not cs_prog_data->threads).

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
2020-04-09 19:23:12 -07:00
Vinson Lee
0536ca20d7 swr/rasterizer: Use private functions for min/max to avoid namespace issues.
This is a similiar fix as bb2287ccdf ("gallivm/tessellator: use
private functions for min/max to avoid namespace issues").

Fixes: ab55708200 ("swr/rasterizer: Add tessellator implementation to the rasterizer")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4208>
2020-04-09 17:57:02 -07:00
Connor Abbott
089e1fb287 tu: Implement descriptor set update templates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
e1595026f6 tu: Add missing code for immutable samplers
Actually fill out the samplers, based on the radv implementation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
a07b55443b tu: Emit CP_LOAD_STATE6 for descriptors
This restores the pre-loading of descriptor state, using the new
SS6_BINDLESS method that allows us to pre-load bindless resources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
d37843fee1 tu: Switch to the bindless descriptor model
Under the bindless model, there are 5 "base" registers programmed with a
64-bit address, and sam/ldib/ldc and so on each specify a base register
and an offset, in units of 16 dwords. The base registers correspond to
descriptor sets in Vulkan. We allocate a buffer at descriptor set
creation time, hopefully outside the main rendering loop, and then
switching descriptor sets is just a matter of programming the base
registers differently. Note, however, that some kinds of descriptors
need to be patched at command recording time, in particular dynamic
UBO's and SSBO's, which need to be patched at CmdBindDescriptorSets
time, and input attachments which need to be patched at draw time based
on the the pipeline that's bound. We reserve the fifth base register
(which seems to be unused by the blob driver) for these, creating a
descriptor set on-the-fly and combining all the dynamic descriptors from
all the different descriptor sets. This way, we never have to copy the
rest of the descriptor set at draw time like the blob seems to do. I
mostly chose to do this because the infrastructure was already there in
the form of dynamic_descriptors, and other drivers (at least radv) don't
cheat either when implementing this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
fc850080ee ir3: Rewrite UBO push analysis to support bindless
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
274f3815a5 ir3: Plumb through bindless support
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
7d0bc13fca ir3: LDC also has a destination
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
1842961e58 ir3: Also don't propagate immediate offset with LDC
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
de7d90ef53 ir3: Plumb through support for a1.x
This will need to be used in some cases for the upcoming bindless
support, plus ldc.k instructions which push data from a UBO to const
registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
c8b0f90439 ir3: Add bindless instruction encoding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
122a900d7d freedreno/a6xx: Add registers for the bindless model
In Vulkan, descriptors for samplers, SSBO's, etc. are collected into
descriptor sets, and shaders can use multiple descriptor sets. At
command-recording time, users can swap out only some of the descriptor
sets, and the driver is supposed to do the minimum amount necessary to
update any internal binding tables, knowing that only some of the
descriptors have changed.

With the old binding model, focused on GL, where there are separate
tables for each type of resource, we can do somewhat better than now by
preserving descriptors from lower descriptor sets when switching higher
descriptor sets. However we still have to copy around descriptors before
each draw.

At least for a6xx, qualcomm went further, essentially copying the Vulkan
binding model as an alternate way to load resources. There's an array of
registers (actually an array for compute and one for everything else),
where each register holds a pointer to a descriptor set that can contain
various different descriptor types. The descriptors are padded out to 16
dwords, so that every instruction can use an index instead of a dword
offset. It's called "bindless", I think, because it can also be used to
implement the old GL bindless extensions (presumably it allows more
samplers and textures than the old model).

This commit adds the register and cmdstream parts. Next up will be the
instruction encoding.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
e088d82aa6 freedreno/a6xx: Add UBO size field
Verified with the vulkan blob, which uses ldc and UBO descriptors, and
turnip will too soon.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
d3b7681df2 tu: ir3: Emit push constants directly
Carve out some space at the beginning for push constants, and push them
directly, rather than remapping them to a UBO and then relying on the
UBO pushing code. Remapping to a UBO is easy now, where there's a single
table of UBO's, but with the bindless model it'll be a lot harder. I
haven't removed all the code to move the remaining UBO's over by 1,
though, because it's going to all get rewritten with bindless anyways.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Connor Abbott
63c2e8137d tu: Dump out shader assembly when requested
We don't use the ir3 variant machinery, so we have to do this ourselves.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
2020-04-09 15:56:55 +00:00
Daniel Schürmann
d22e2b3bd0 aco: RA - move all std::function objects into proper functions
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
5351fee56a aco: move all needed helper containers to ra_ctx
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
2ae27b96ef aco: change live_out variables to std::unordered_set
Improves performance of live_var_analysis for larger shaders

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
acc10a7e51 aco: change some std::map to std::unordered_map in register_allocation
This improves compile times slightly for larger shaders

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
69b6069dd2 aco: refactor try_remove_trivial_phi() in RA
Minor refactoring to avoid some pointer chasing.
This patch also changes the live_out argument to be
passed by reference to avoid an unnecessary copy.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
b66f474121 aco: improve speed of live_var_analysis
by merging live_sgprs and live_vgprs sets.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
09850e0a94 aco: during RA only insert into renames table if a variable got renamed
This improves the speed of register allocation.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
48a74b6815 aco: replace assignment hashmap by std::vector in register allocation
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
ba482c2e5f aco: improve register assignment when live-range splits are necessary
When finding a good place for a register, we can ignore
killed operands.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
fb5a7902f2 aco: improve hashing for value numbering
An improved hashing greatly reduces the number of collisions,
and thus, increases the speed for lookups in the hash table.
The hash function now uses Murmur3 written by Austin Appleby.

This patch also pre-reserves space for the hashmap to avoid rehashing.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
c99107ece0 aco: add explicit padding for all Instruction sub-structs
This patch also adds static_asserts on the size of Instructions
to ensure no internal padding is present.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Daniel Schürmann
7f962a9362 aco: guarantee that Temp fits in 4 bytes
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>
2020-04-09 15:08:57 +00:00
Jonathan Marek
2e084c2cb3 turnip: new clear/blit implementation with shader path fallback
The shader path is used to implement the following cases:
* stencil aspect mask on D24S8 (for image_to_buffer,buffer_to_image)
* clear/copy msaa destination (2D engine can't have msaa dest)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
de6967488a turnip: add vk_format_is_snorm/is_float
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
51fe52d2fd turnip: rework format helpers
* Take tile_mode as input directly
* tu6_format_gmem to tu6_base_format, use may not be limited to GMEM
* Add new helpers that will return the correct tile_mode as for image level
  as part of the format.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
009082dcff turnip: use dirty bits for dynamic viewport/scissor state
CmdClearAttachments shader path will overwrite this state, so it needs to
be re-emitted with dirty bits in that case.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
ed83281f0c turnip: save attachment samples in renderpass state
This is needed to be able to know the number of samples during
CmdClearAttachments which can be used while the framebuffer is unknown.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
0637eab678 turnip: disable 8x msaa
Not everything supports 8x msaa, and the blob doesn't support it at all.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
f03e63cd99 turnip: fix nir validate failure from push constant lowering
Fixes newly added checks in nir validate failing.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
86d1a4c907 turnip: split up gmem/tile alignment
Note: the x1/y1 align in tu6_emit_blit_scissor was broken

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
f494799a7f turnip: RB_CCU_CNTL fixes
* Correct bypass value for a618
* Bypass value for blitter
* Don't set RB_CCU_CNTL again unnecessarily in tu6_emit_binning_pass

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
cca7c29980 freedreno/a6xx: set bypass RB_CCU_CNTL value for blitter
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Jonathan Marek
e4c05a5335 freedreno/registers: add RB_CCU_CNTL bitfields
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
2020-04-09 14:43:02 +00:00
Samuel Pitoiset
2d8453e6e6 radv: allow TC-compat HTILE with GENERAL outside of render loops
This gives +8% with Wolfeinstein Youngblood on my Vega64, and
according to someone else, it also improves performance with Doom
2016 and Wolfenstein 2 (and probably other ID Tech games).

This improvement is because Youngblood uses GENERAL for the main
depth-only pass and TC-compat HTILE is now enabled with GENERAL if
we know that we are outside of a render loop. This obviously also
reduces the number of HTILE decompressions from/to GENERAL.

Note that Youngblood violates the Vulkan spec regarding render loops
because they are only allowed with input attachments. Expect possible
rendering issues if apps use render loops with the wrong way (ie.
without input attachmens) because HTILE might not be coherent if
a depth-stencil texture is sampled and rendered in the same draw.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2704
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4391>
2020-04-09 12:10:37 +00:00
Samuel Pitoiset
4de84c8cbd radv: only enable TC-compat HTILE for images readable by a shader
If no texture fetches happen it's useless to enable TC-compat HTILE.

Because the driver currently doesn't support TC-compat HTILE for
storage images we don't have to check.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4497>
2020-04-09 11:55:59 +00:00
Samuel Pitoiset
63f07a3047 radv: only expose fp16 control features for chips with double rate fp16
This disables all fp16 shader control features on GFX8 because only
GFX9+ supports double rate packed math.

This improves consistency regarding other AMD Vulkan drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>
2020-04-09 13:35:08 +02:00
Samuel Pitoiset
1e4bd1de98 radv: only expose storageInputOutput16 for chips with double rate fp16
This feature allows to use both 16-bit integers and 16-bit floats
as inputs/outputs.

This disables storageInputOutput16 on GFX8 because only GFX9+ supports
double rate packed math.

This improves consistency regarding other AMD Vulkan drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>
2020-04-09 13:35:08 +02:00
Samuel Pitoiset
1d74c6565d radv: only expose shaderFloat16 for chips with double rate fp16
This disables shaderFloat16 on GFX8 because only GFX9+ supports
double rate packed math.

This improves consistency regarding other AMD Vulkan drivers and
it makes no sense to enable that feature without packed math.

This also reduces performance with Wolfeinstein Youngblood if
fp16 is forced enabled on GFX8, while it's similar on GFX9.

We might re-introduce that feature in the future with ACO support
if it ends up being faster and correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>
2020-04-09 13:34:36 +02:00
Samuel Pitoiset
a3113e07b9 ac,radv: add ac_gpu_info::has_double_rate_fp16
Only GFX9+ support double rate packed math instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>
2020-04-09 13:30:54 +02:00
Jonathan Marek
420ca1e4a1 turnip: use buffer size instead of bo size for VFD_FETCH_SIZE
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4224>
2020-04-09 02:05:52 +00:00
Jonathan Marek
e62f8ae15a turnip: improve vertex input handling
Emit vertexBindingDescriptionCount bindings, instead of one per attribute.

Verified with dEQP-VK.pipeline.vertex_input.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4224>
2020-04-09 02:05:52 +00:00
James Zhu
98743f648a radeonsi: fix Segmentation fault during vaapi enc test
Fix Segmentation fault during vaapi enc test on Arcturus.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by Leo Liu <leo.liu@amd.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4472>
2020-04-08 18:11:45 +00:00
Bas Nieuwenhuizen
a7e2efa7c9 radv: Use correct buffer count with variable descriptor set sizes.
Fixes dEQP-VK.binding_model.descriptorset_random.sets16.noarray.ubolimitlow.sbolimitlow.imglimitlow.iublimitlow.frag.ialimitlow.0

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2607
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4489>
2020-04-08 15:26:50 +00:00
Bas Nieuwenhuizen
bb7e44a23d radv: Whitespace fixup.
Review comment that I did, but forgot to git add before amending ...

From https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4334

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4488>
2020-04-08 11:18:18 +00:00
Samuel Iglesias Gonsálvez
8b42d26132 radv: set sparseAddressSpaceSize to RADV_MAX_MEMORY_ALLOCATION_SIZE
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4487>
2020-04-08 11:03:35 +00:00
Samuel Iglesias Gonsálvez
cc678c9ce9 radv: check buffer size in vkCreateBuffer()
Fixes:

   dEQP-VK.api.buffer.basic.size_max_uint64

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4487>
2020-04-08 11:03:35 +00:00
Bas Nieuwenhuizen
a3682670c8 radv: Consider maximum sample distances for entire grid.
The other pixels in the grid might have samples with a larger
distance than the (0,0) pixel.

Fixes dEQP-VK.pipeline.multisample.sample_locations_ext.verify_location.samples_8_packed
when CTS is compiled with clang.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4480>
2020-04-08 10:53:33 +00:00
Samuel Pitoiset
9f005f1f85 radv: enable lowering of GS intrinsics for the LLVM backend
This replaces emit_vertex with:
   if (vertex_count < max_vertices) {
      emit_vertex_with_counter vertex_count ...
      vertex_count += 1
   }

Which is exactly what NIR->LLVM was doing but at NIR level. This
pass is already called by ACO.

pipeline-db changes on GFX10:
Totals from affected shaders:
SGPRS: 1952 -> 1912 (-2.05 %)
VGPRS: 2112 -> 2044 (-3.22 %)
Code Size: 189368 -> 185620 (-1.98 %) bytes
Max Waves: 494 -> 491 (-0.61 %)

No pipeline-db changes on other generations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4182>
2020-04-08 08:24:05 +02:00
Samuel Pitoiset
cd99ea7318 radv: remove radv_layout_has_htile() helper
The goal of this function was to return whether a depth-stencil image
has HTILE, in comparison to radv_layout_is_htile_compressed() which
is used to know whether a depth-stencil image has HTILE compressed.

These two functions are actually similar and they have never been
used for what they were supposed to. Remove radv_layout_has_htile()
in favour of radv_layout_is_htile_compressed() for now. If it's
needed in the future, I will re-introduce this concept properly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4389>
2020-04-08 07:55:16 +02:00
Samuel Pitoiset
ffea3e7348 radv: cleanup creating the decompress/resummarize pipelines
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4389>
2020-04-08 07:55:14 +02:00
Samuel Pitoiset
6f6276bd24 radv: rename extra graphics pipeline decompress/resummarize fields
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4389>
2020-04-08 07:55:12 +02:00
Samuel Pitoiset
8b7586655f radv: rename decompress/resummarize depth/stencil functions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4389>
2020-04-08 07:55:10 +02:00
Jonathan Marek
d6a8591f72 turnip: fix compute shaders crashing after geometry shader change
Fixes: 1af71bee73 ("turnip: Set has_gs in ir3_shader_key")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4483>
2020-04-08 01:56:53 +00:00
Timothy Arceri
52c8bc0130 nir: make opt_if_loop_terminator() less strict
nir_cf_{extract,reinsert}() can't stitch a block together
if the block we are extracting ends in a jump but other jumps
nested in further ifs should be fine to move.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4477>
2020-04-08 01:35:45 +00:00
Timothy Arceri
1f649ff107 radeonsi: don't lower constant arrays to uniforms in GLSL IR
This re-enables the change made in 2f5783bc2b which was
incorrectly disabled by 3e1dd99adc.

For radeonsi, we will prefer the NIR pass as it'll generate better code
(some index calculation and a single load vs. a load, then index
calculation, then another load) and oftentimes NIR optimization can kick
in and make all the access indices constant.

Fixes: 3e1dd99adc ("radeonsi: Remove a bunch of default handling of pipe caps.")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4474>
2020-04-08 01:23:40 +00:00
Dominik Behr
c682ea598f meson: fix debug build on Android
debug_stack functions are implemented in another file for Android.
Also add backtrace library dependency.

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-bu: Kristian H. Kristensen <hoegsber@google.com>
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2435>
2020-04-07 23:15:11 +00:00
Bas Nieuwenhuizen
940ed5078d radv: Store 64-bit availability bools if requested.
Fixes dEQP-VK.query_pool.*.reset_before_copy.* on RAVEN.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2296
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4334>
2020-04-07 22:57:24 +00:00
Vinson Lee
ff8daa0136 gallivm: Add missing header for powf.
Fix build error after llvm-11 commit 3a29393b4709 ("Remove
math.h/cmath include from DataTypes.h").

src/gallium/auxiliary/gallivm/lp_bld_format_srgb.c: In function ‘lp_build_linear_to_srgb’:
src/gallium/auxiliary/gallivm/lp_bld_format_srgb.c:194:44: error: implicit declaration of function ‘powf’ [-Werror=implicit-function-declaration]
  194 |                                  exp2f_c * powf(coeff_f, 1.0f / exp_f));
      |                                            ^~~~
src/gallium/auxiliary/gallivm/lp_bld_format_srgb.c:194:44: warning: incompatible implicit declaration of built-in function ‘powf’
src/gallium/auxiliary/gallivm/lp_bld_format_srgb.c:78:1: note: include ‘<math.h>’ or provide a declaration of ‘powf’
   77 | #include "lp_bld_format.h"
  +++ |+#include <math.h>
   78 |

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4473>
2020-04-07 21:48:31 +00:00
Kristian H. Kristensen
4399cacaf0 turnip: Drop dep_llvm from dependencies
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
2020-04-07 18:44:21 +00:00
Kristian H. Kristensen
5789505ab3 turnip: Make Android platform build
We still don't have a way to keep this from breaking, but I don't
think this ever built.  Let's call it progress.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
2020-04-07 18:44:21 +00:00
Kristian H. Kristensen
97578c69e8 turnip: Stub out VK_KHR_external_{fence,semaphore}_fd
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
2020-04-07 18:44:21 +00:00
Kristian H. Kristensen
e99f6f2ea1 turnip: Add missing VKAPI_ATTR annotations
Make sure the types match.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
2020-04-07 18:44:21 +00:00
Rohan Garg
80c13a81b1 tracie: Reformat code to fix indentation
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4435>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4435>
2020-04-07 18:21:32 +00:00
Rohan Garg
efbbf8bb81 tracie: Print results in a machine readable format
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4435>
2020-04-07 18:21:32 +00:00
Eric Anholt
1618159772 freedreno/a6xx: Set a level's pitch based on minified level0 pitch, not width0.
Found from piglit fbo-generatemipmaps failures, then tracked down with the
texturator test.  The piece that really revealed things was finding that
1024x1 linear RGBA8 on the older blob drivers would have a pitch of 5120
instead of 4096, and the following levels minified that pitch.

Fixes ~124 piglit tests (~8.5% of piglit failures) on cheza.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
2020-04-07 18:02:56 +00:00
Eric Anholt
4b881d5270 freedreno: Add the outline of a test for a6xx texture layout.
Trying to work out texture layout by remembering what things looked like
in texturator is hard.  Instead, let's use texture layouts from tracing
the blob as a source of truth to make sure that we pick the same layouts
they do (and don't break known-good ones).  More testcases will be added
as I fix layout bugs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
2020-04-07 18:02:56 +00:00
Eric Anholt
9c6bfe8733 freedreno/a6xx: Drop the "alignment" layout temporary.
It's just 1 for !3d, which means that the align we're doing in that case
is pointless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
2020-04-07 18:02:56 +00:00
Eric Anholt
59a2220398 freedreno/a6xx: Remove the "aligned_height" temporary.
Now that we're not incrementally minifying height, we can just modify it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
2020-04-07 18:02:56 +00:00
Eric Anholt
cdff81fa9a freedreno/a6xx: Sink the per-level size temps inside the loop.
u_minify(n, 1) is no cheaper than u_minify(n, level), and this makes the
logic a lot simpler to follow.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3987>
2020-04-07 18:02:56 +00:00
Michel Dänzer
4176dfa880 gitlab-ci: Run merge request pipelines automatically only for Marge Bot
MR pipelines not triggered by Marge Bot can still be triggered manually.

Motivation: The main & forked Mesa project CI pipelines combined are
currently generating over 1 TB of egress traffic per week. ~80% of this
is from pre-merge pipelines. Assuming this corresponds to 4 pre-merge
and one post-merge pipeline per MR on average, this change could
potentially eliminate up to ~60% of the overall traffic (by preventing
3 of the 4 pre-merge pipelines from running automatically).

(Of course, this could be subverted if all jobs of the other pipelines
were triggered manually anyway... In most cases, manually triggering
just a few jobs should suffice)

v2:
* $GITLAB_USER_NAME was the wrong variable, $GITLAB_USER_LOGIN should
  do the trick.

Suggested-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432>
2020-04-07 17:36:15 +00:00
Michel Dänzer
42fe600c0c gitlab-ci: Don't require triggering build/test jobs manually
Let them run automatically once all their dependencies have passed.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432>
2020-04-07 17:36:15 +00:00
Michel Dänzer
27c4ef1397 gitlab-ci/lava: Add needs: for container image to test jobs (again)
Without this, the test jobs could spuriously run after the container
job failed or was cancelled, even if the build job didn't run at all.

(I already did this in 94cfe59070, but it
got dropped accidentally in 22d976454f)

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432>
2020-04-07 17:36:15 +00:00
Michel Dänzer
c12576efbe gitlab-ci: Rename "paths" YAML anchor to "all_paths"
To avoid confusion with `paths:` elements.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432>
2020-04-07 17:36:15 +00:00
Caio Marcelo de Oliveira Filho
cf54785239 anv/gen12: Lower VK_KHR_multiview using Primitive Replication
Identify if view_index is used only for position calculation, and use
Primitive Replication to implement Multiview in Gen12.  This feature
allows storing per-view position information in a single execution of
the shader, treating position as an array.

The shader is transformed by adding a for-loop around it, that have an
iteration per active view (in the view_mask).  Stores to the position
now store into the position array for the current index in the loop,
and load_view_index() will return the view index corresponding to the
current index in the loop.

The feature is controlled by setting the environment variable
ANV_PRIMITIVE_REPLICATION_MAX_VIEWS, which defaults to 2 if unset.
For pipelines with view counts larger than that, the regular
instancing will be used instead of Primitive Replication.  To disable
it completely set the variable to 0.

v2: Don't assume position is set in vertex shader; remove only stores
    for position; don't apply optimizations since other passes will
    do; clone shader body without extract/reinsert; don't use
    last_block (potentially stale). (Jason)

    Fix view_index immediate to contain the view index, not its order.
    Check for maximum number of views supported.
    Add guard for gen12.

v3: Clone the entire shader function and change it before reinsert;
    disable optimization when shader has memory writes. (Jason)

    Use a single environment variable with _DEBUG on the name.

v4: Change to use new nir_deref_instr.
    When removing stores, look for mode nir_var_shader_out instead
    of the walking the list of outputs.
    Ensure unused derefs are removed in the non-position part of the
    shader.
    Remove dead control flow when identifying if can use or not
    primitive replication.

v5: Consider all the active shaders (including fragment) when deciding
    that Primitive Replication can be used.
    Change environment variable to ANV_PRIMITIVE_REPLICATION.
    Squash the emission of 3DSTATE_PRIMITIVE_REPLICATION into this patch.
    Disable Prim Rep in blorp_exec_3d.

v6: Use a loop around the shader, instead of manually unrolling, since
    the regular unroll pass will kick in.
    Document that we don't expect to see copy_deref or load_deref
    involving the position variable.
    Recover use_primitive_replication value when loading pipeline from
    the cache.
    Set VARYING_SLOT_LAYER to 0 in the shader.  Earlier versions were
    relying on ForceZeroRTAIndexEnable but that might not be
    sufficient.
    Disable Prim Rep in cmd_buffer_so_memcpy.

v7: Don't use Primitive Replication if position is not set, fallback
    to instancing; change environment variable to be
    ANV_PRIMITVE_REPLICATION_MAX_VIEWS and default it to 2 based on
    experiments.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
2020-04-07 17:16:09 +00:00
Caio Marcelo de Oliveira Filho
395de69b1f intel/fs: Allow multiple slots for position
Change brw_compute_vue_map() to also take the number of pos slots.  If
more than one slot is used, the VARYING_SLOT_POS is treated as an
array.

When using Primitive Replication, instead of a single position, the
VUE must contain an array of positions.  Padding might be
necessary (after clip distance) to ensure rest of attributes start
aligned.

v2: Add note about array in the commit message and assert that
    pos_slots >= 1 to make clear 0 is invalid. (Jason)
    Move padding to be after the clip distance.

v3: Apply the correct offset when gathering the sources from outputs.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
2020-04-07 17:16:09 +00:00
Caio Marcelo de Oliveira Filho
afa5447312 intel/gen12: Add XML description for 3DSTATE_PRIMITIVE_REPLICATION
v2: Use groups for the 16-element arrays "Viewport Offset"
    and "RTAI Offset". (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
2020-04-07 17:16:09 +00:00
Caio Marcelo de Oliveira Filho
5dc85abc4f nir: Add per_view attribute to nir_variable
If a nir_variable is tagged with per_view, it must be an array with
size corresponding to the number of views.  For slot-tracking, it is
considered to take just the slot for a single element -- drivers will
take care of expanding this appropriately.

This will be used to implement the ability of having per-view position
in a vertex shader in Intel platforms.

Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
2020-04-07 17:16:09 +00:00
Simon Ser
0bc77bcdb2 mesa: add support for NV_pixel_buffer_object
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4422>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4422>
2020-04-07 16:52:15 +00:00
Jonathan Marek
a1727598a0 turnip: implement timestamp query
Passes tests in:
dEQP-VK.pipeline.timestamp.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4027>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4027>
2020-04-07 14:58:47 +00:00
Brian Ho
d64a7d6e69 turnip: Enable geometryShader device feature
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:21 +00:00
Brian Ho
bdf6b481d8 turnip: Enable geometry shaders for CP_DRAWs
Enable geometry shading on draw if the pipeline has a geometry
stage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
b80dc4f5a6 turnip: Populate tu_pipeline.active_stages
This can be used to determine if the pipeline has a specific shader
stage (e.g. geometry shader).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
8eb0096312 turnip: Update maxGeometryShaderInvocations to match blob
Geometry shaders support an invocations parameter up to a limit
defined by maxGeometryShaderInvocations. This was set to 127, but
executing with invocations > 32 causes a crash. As it turns out, the
blob only advertises a max of 32 invocations, so we set that in
turnip as well.

Fixes dEQP-VK.geometry.instanced.draw_*_instances_{127, 64}_geometry_invocations

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
3550e20229 turnip: Selectively configure GRAS_LAYER_CNTL
One of the features of geometry shaders is the ability to render to
different layers by assigning to the gl_Layer (Layer in SPIR-V)
builtin.

While have already plumbed the layer regid to the geometry shader,
we also need to GRAS_LAYER_CNTL to actually use layered rendering.
In addition, gmem does not support layered rendering, so we need to
force sysmem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
475fe500bf turnip: Set up REG_A6XX_SP_GS_CONFIG
Updates GS_CONFIG and HLSQ_GS_CNTL registers to match those emitted
by the blob and fd.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
fceccc411a turnip: Configure VFD_CONTROL with gsheader and primitiveid
This commit updates VFD_CONTROL to use the GS header and primitive
ID sysvals if a geometry shader stage is present in the pipeline.
Like in the case of VPC, the code here is adapted from fd6_program.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
012773be26 turnip: Configure VPC for geometry shaders
This commit updates tu6_emit_vpc to selectively emit GS-specifc
configuration. Most of this is repurposed from fd6_program.c.

This also refactors `link_geometry_stages` to ir3_nir_lower_tess.c
so it can be shared between fd and tu.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
6eabd6bd51 turnip: Emit geometry shader obj and related consts
Like with other shader types, we need to emit the geometry shader
object and the consts it uses. In addition, we need to emit
additional geometry-specific consts that link primitive/vertex stride
between the vs and gs. In conjunction with the gsheader, these are
used by the vs to determine where to stlw outputs and used by the gs
to determine where to ldlw those outputs from.

FD emits these consts in the draw call because in GL, you can mix
and match shaders in different programs. In Vulkan, however, we
compile and link the shaders at pipeline creation, so we can emit
these in the pipeline IB instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Brian Ho
1af71bee73 turnip: Set has_gs in ir3_shader_key
The ir3 compiler only lowers the VS and GS for geometry shading if
the corresponding has_gs key is set in the shader key. Without it,
GS-specific intrinsics like load_per_vertex_input won't get lowered
and the GS header will be initialized with invalid values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
2020-04-07 14:13:20 +00:00
Timur Kristóf
db2ee3686d radv: Print shader stage before disassembly.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
aa42b504d6 aco: Print shader stage in aco_print_program.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
c24d9522da radv: Enable ACO for NGG VS/TES, but disable NGG for ACO GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
64225c4f96 aco/ngg: Run GS_ALLOC_REQ on priority 3 for NGG VS and TES.
It is recommended to do this as quickly as possible.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
e4da482d9e aco/ngg: Schedule position exports of NGG VS/TES.
Similarly to the HW VS stage, the HW NGG GS stage also
benefits from executing these exports as early as possible.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
c633edad72 aco/ngg: Implement NGG VS and TES.
When NGG is used, vertex and tess eval shaders are executed on the
hardware NGG geometry stage. There is a series of steps they
must perform:

* Request GS space using GS_ALLOC_REQ
* Export the primitive
* Finally, export the normal VS outputs

In this commit, two modes are implemented:

* "late" which matches what the RADV LLVM backend currently does
* "early" which is an optimized version as seen in radeonsi

Vulkan doesn't allow the shader to write the edge flags, so we can
currently always use the "early" mode.

Exporting the primitive ID is also supported by having the GS threads
write that into LDS and reading them from LDS in the ES threads.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
c5ed0883fc aco/ngg: Setup NGG VS and TES stages.
ngg_vertex_gs and ngg_tess_eval_gs work very similarly to
vertex_vs and tess_eval_vs, but they run on the HW NGG GS stage.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
d7b4bb3a88 aco/ngg: Fix exports for NGG VS and TES.
The exports in NGG VS and TES work just like VS exports,
so the assembler needs to fix these too in the same manner.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
ec72c504c6 aco/ngg: Initialize exec mask for NGG VS and TES.
They behave like merged ESGS shaders, so the exec mask needs
to be manually initialized for these NGG shaders too.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
1436c0b8e0 aco/ngg: Add new stage for hw_ngg_gs.
This is needed to distinguish between NGG and legacy.
Otherwise, vertex_geometry_gs and ngg_vertex_geometry_gs
have the same value, which we want to avoid.

Also, there is no such thing as ngg_vertex_tess_control_hs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
35e58314d8 aco: Treat s_setprio as a scheduling barrier.
We want to execute instructions after s_setprio in the given
priority, so we must prevent the scheduler from scheduling beyond
s_setprio, otherwise some instructions could be executed in a
different priority.

Rename hazard_fail_memtime to hazard_fail_unreorderable and include
s_setprio in the list of unreorderable opcodes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
d345bfe195 aco: Extract merged_wave_info_to_mask to its own function.
Currently we only use this at the beginning of merged shader parts,
but we are going to need to use	it with	some NGG code as well.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
90b1047fdf aco: Print block_kind_export_end.
Useful when debugging issues with exports.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
b9cbdb6a45 aco: Extract uniform if handling to separate functions.
Currently we only use this for uniform ifs that come from NIR,
but we are going to need to use it with some NGG parts as well.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3576>
2020-04-07 11:29:35 +00:00
Timur Kristóf
cc8a85d05a aco: Fix crash in insert_wait_states.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4465>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4465>
2020-04-07 09:51:14 +00:00
Alyssa Rosenzweig
eeb626257d pan/bit: Wire up add/add op+test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
e456630bd9 pan/bit: Add fmin/max16 tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
fc446dc322 pan/bit: Enable more debug for run
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
0e0f7f110c pan/bit: Add min/max support to interpreter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
e9967e9f80 pan/bit: Unify test frontends
Random.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
f91929e515 pan/bi: Force ADD scheduling for MINMAX
Might be GPU version specific.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
9279ed1550 pan/bi: Fix incorrect abs flip in fma/fadd16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
3bbce876e6 pan/bi: Set BI_MODS for MINMAX
We support it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
822f127fe5 pan/bi: Add ADD add/min/max fp32 packing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
36e4c6b267 pan/bi: Structify ADD unit add/min/max
..since it's missing for FMA

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
f6bd0ec907 pan/bi: Implement min/max on FMA
Unfortunately, while this looks fine to the disasm, it's raising
INSTR_INVALID_ENC on my g31 board here. Looks like it might be ADD only
on newer Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
545fc7b26a pan/bit: Add special unit test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
8e50d44950 pan/bit: Add special op interpreting
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
c37c799284 pan/bi: Add fp16 support for frcp/frsq
More ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
d7bb7b79a8 pan/bi: Add 32-bit _FAST packing
For frcp/frsq on newer Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Alyssa Rosenzweig
a6ae2d8f94 pan/bi: Remove nontrivial SPECIAL ops
These require a lot more handholding in the IR than we can deal with at
this stage; we need to restrict ourselves to frcp/sqrt.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
2020-04-06 19:41:56 +00:00
Rhys Perry
20a4b1461b aco: zero-initialize Temp
Fixes dEQP-VK.transform_feedback.* crashes from accesses garbage
temporaries in emit_extract_vector().

Fixes: 85521061 ("aco: prepare helper functions for subdword handling")
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4463>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4463>
2020-04-06 19:15:19 +00:00
Rhys Perry
8dd6a51e80 aco: remove divergence check in sanitize_if()
We also need to do this if a side ends in a divergent break.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4461>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4461>
2020-04-06 18:39:29 +00:00
Rob Clark
57557783f6 nir/lower_amul: fix slot calculation
Fixes incorrect indexing in
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.packed.mat2x3

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4455>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4455>
2020-04-06 18:00:17 +00:00
Rob Clark
4638a16a93 nir: add some swizzle helpers
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4455>
2020-04-06 18:00:17 +00:00
Jason Ekstrand
e78a7a1825 nir: Assert memory loads are aligned
We've had alignment parameters on these operations for a while but a
bunch of places weren't setting them.  That should be resolved now so we
can start validating that they're always set.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4441>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4441>
2020-04-06 15:57:30 +00:00
Marek Olšák
068a3bf0d7 util: move and adjust the vertex upload heuristic equation from u_vbuf
This will also be used by glthread.

The new equation is optimized for glthread.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:30:10 -04:00
Marek Olšák
d9cb0ec5e6 vbo: expose helper function vbo_get_minmax_index_mapped for glthread
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:29:52 -04:00
Marek Olšák
e69e59778c mesa: split _mesa_primitive_restart_index into a function without gl_context
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:29:38 -04:00
Marek Olšák
e6bc1702f4 mesa: precompute _mesa_primitive_restart_index during state changes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:29:16 -04:00
Marek Olšák
10beee8a77 mesa: remove no longer needed _mesa_is_bufferobj function
All buffers have Name != 0.

Note that there is no longer the pointer dereference to get Name,
so it's faster.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:28:53 -04:00
Marek Olšák
58fab9a6fe mesa: remove NullBufferObj
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:28:53 -04:00
Marek Olšák
54525808aa mesa: don't ever bind NullBufferObj to glBindBuffer(Base,Range) slots
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:28:53 -04:00
Marek Olšák
f3cce7087a mesa: don't ever bind NullBufferObj for glBindBuffer targets
Since VAOs don't use NullBufferObj for vertex attribs anymore, let's remove
more uses of NullBufferObj.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:28:53 -04:00
Marek Olšák
e630271e0e mesa: don't ever set NullBufferObj in gl_vertex_array_binding
This improves performance by 5% in the game "torcs", FPS: 98.83 -> 103.73

It does a lot of glPush/PopClientAttrib, which exacerbates the overhead
of setting NullBufferObj.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:28:53 -04:00
Marek Olšák
a0a0c68150 mesa: optimize initialization of new VAOs
Precompute the default state in gl_context, and just copy it when we create
a VAO.

This also helps glPushClientAttrib function, which always creates a VAO,
which has a substantial CPU overhead in profiles.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4466>
2020-04-06 10:27:59 -04:00
Mauro Rossi
dbdd0149ed android: aco: add various compiler statistics
Fixes a building error due to compiler/aco_statistics.cpp
missing in src/amd/Makefile.sources

Fixes: b1544352 ("aco: add various compiler statistics")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-04-06 12:59:13 +02:00
Hyunjun Ko
9f174eb2df nir: fix wrong assignment to buffer in xfb_varyings_info
Tested with dEQP-VK.transform_feedback.fuzz.various_buffers.buffers100_instance_array_vertex

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4459>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4459>
2020-04-06 08:55:05 +00:00
Tapani Pälli
84e845c969 mesa/st: release variants for active programs before unref
Programs can be shared among many contexts and each program holds a
variant list which has context specific variants. When context gets
destroyed it must make sure it relases all variants, otherwise remaining
context that utilizes same program will attempt to save a zombie shader
for already deleted context when releasing program and its variants.

Fixes:
   dEQP-EGL.functional.sharing.gles2.program.render

and other flaky multihread dEQP-EGL failures.

v2: pass program pointer via & (Marek)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4386>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4386>
2020-04-06 08:00:00 +03:00
Tapani Pälli
4822cc9700 mesa/st: unbind shader state before deleting it
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4386>
2020-04-06 08:00:00 +03:00
Alyssa Rosenzweig
82597c46c3 pan/bit: Add mode to run unit tests
Probably the most useful of the bunch going forward.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
1a1c55709e pan/bit: Make run more useful
..by printing some output.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
50476efb61 pan/bit: Add csel tests
..and pull out common instruction generation to reduce duplication in
tests a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
9b262208b6 pan/bit: Add CSEL to interpreter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
069189ff0f pan/bit: Add FMA tests
Now that the earlier reg ctrl issue is fixed these should pass.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
78ba6d50a4 pan/bit: Add 16-bit fmod tests
These raise another set of issues -- indeed, not all of these tests are
passing, since it turns out I have an actual bug in the packing code. So
after all this work, test bringup has identified an actual issue :)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
40160c576d pan/bit: Add verbose printing for tests
We'd like to dump both the generated IR (so we know exactly what's being
tested) as well as the compiled program (so we know what's running for
comparison).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
7c887d368e pan/bit: Add helper for generating floating mod tests
We can iterate them, isn't that adorable!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
14c5343867 pan/bit: Add packing test framework
Given an instruction, we'd like to wrap it in a clause with some I/O on
each end so we can pack it up and send it to the hardware to compare
against the simulator.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
5e3e32e368 pan/bit: Implement floating source mods
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
dbb8a564f2 pan/bit: Implement outmods
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
ab58185604 pan/bit: Add preliminary FMA/ADD/MOV implementations
Missing some details about modifiers but the core structure should
look like this for 32 and 16-bit, I think. My sincerest apologies for
the macro magic, I tried to make it the least bad I could but trying to
keep down repitition.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
fbe504e221 pan/bit: Handle read/write
We case the various sources and destinations to model register file
access and passthrough in particular.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
7904a29340 pan/bit: Stub out BIR interpreter
We'd like to step through a BIR program to evaluate it for testing.
Let's stub out some infrastructure for modeling Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
8eefb2765a pan/bi: Match CSEL argument order with hw
It turns out ports need to be in order of the arguments of an
instruction (port 3, that is), which breaks on instructions whose IR
argument order is different from the packed order, like csel. So fix
that.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
9114ebbe79 pan/bi: Add helper to debug port assignment
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
0ab3f687c0 pan/bi: Handle BIFROST_FIRST_WRITE_FMA_P2_READ_P3
It's a special case for unclear reasons, and if you mess it up you get
INSTR_INVALID_ENC. Isn't hardware fun?

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
75aabc6ea1 pan/bi: Allow BI_FMA to take mods
It doesn't take abs but it can take outmod/neg.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
69dde49f80 pan/bi: Don't gobble zero ports
In case we've reading/writing R0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
c7a6df4638 pan/bi: Fix negation in ADD.v2f16
When we flip the sources we need to flip the negates as well to stay
consistent.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
5f48caf98b pan/bi: Fix duplicated source in ADD.v2f16
Typo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Alyssa Rosenzweig
08fe1081b7 pan/bi: Export bi_class_name
For use in naming tests.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
2020-04-05 23:26:04 +00:00
Vasily Khoruzhick
c04964c690 lima: avoid situations when scissor minx > maxx or miny > maxy
Clip scissor to viewport and then to framebuffer to avoid that since
hardware can't handle this case.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4427>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4427>
2020-04-05 18:52:11 +00:00
Christian Gmeiner
eed5a00989 etnaviv: convert perfmon queries to acc queries
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
20e0ef88ed etnaviv: move generic perfmon functionality into own file
This change removes the basic infrastructure to work with perfmon
from the perfmon query impl and puts it into its own place.
Makes the whole series easier to review and ends smaller changes.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
c111f79b1c etnaviv: extend acc sample provide with an allocate(..)
We might be able to sub-class etna_acc_query.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
e0bc251ef8 etnaviv: extend result(..) to return if data is ready
For the upcoming conversion of perfmon queries to the acc query
framework we need a way to tell that the data is not ready.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
e5b0eed0f5 etnaviv: make use of a fixed size array to track of all acc query provider
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
6963fcd81f etnaviv: extend acc query provider with supports(..) function
Move the logic if a query provider supports a query_type
directly to the provider.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
f47b4eddd9 etnaviv: rework wait/flush logic
Saves us from doing an extra flush in !wait case and seems more
logical now. Also evaluate etna_bo_cpu_prep(..) retun value.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
d1697fef1a etnaviv: reset no_wait_cnt after triggered flush
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
2381904030 etnaviv: explicitly call resource_written(..)
We might end in cases where etna_acc_get_query_result(..) gets called
within one draw call (aka before flushing). At this point the status
of the resource was not set but gets used in etna_acc_get_query_result(..)
to handle different wait cases. Fix this issue by calling resource_written(..)
explicitly.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
f2c4892512 etnaviv: rework etna_acc_sample_provider
Simplify the interface a sampler provider needs to implement. The start(..)
and stop(..) functions got called by resume(..) and suspend(..) so lets
get rid of start(..) and stop(..). Also the way we count and use samples
is much easier to follow now.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Christian Gmeiner
46096a4cb4 etnaviv: rename hw queries to acc queries
The name hw queries was choosen as occlusion queries are 'feeling'
like nothing special. It is possible to interact with them only
via the command stream - unlike perfom queries where some kernel
magic is needed.

Accumulated HW queries is a much better name for this type of queries.
We read some hardware values over some draw calls and need to accumulate
them to get the final result.

This is some prep work for the following perfmon changes.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1530>
2020-04-05 18:01:43 +00:00
Eric Engestrom
7af813d48a glx: use anonymous namespace to avoid -Wodr issues when building with LTO enabled
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2597>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2597>
2020-04-04 17:46:05 +00:00
Eric Engestrom
17d783b2ed glx: fix 630 times -Wlto-type-mismatch when building with LTO enabled
The prototypes are simply copied from include/GL/gl*.h

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2597>
2020-04-04 17:46:05 +00:00
Jason Ekstrand
a0a4df7e4f Revert "spirv: Rewrite CFG construction"
This reverts commit fa5a36dbd4.
2020-04-04 09:47:00 -05:00
Dave Airlie
51492f20f7 Revert "gallivm: disable rgtc/latc SNORM accellerated fetches"
This reverts commit 4897e70ccd.

Fixed in previous commits.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4425>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4425>
2020-04-04 12:37:20 +10:00
Dave Airlie
aa95b6aed5 gallivm/rgtc: enable fast path for snorm types.
As per Roland's suggestions it should be easy to enable the
fast path fetch for rgtc snorm as well here.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4425>
2020-04-04 12:37:20 +10:00
Dave Airlie
03204dadbc gallivm/rgtc: fix the truncation to 8-bit
The 8 bit type wasn't 8-bit so when doing signed work we lost
the sign bit. This fixes it to use a proper vector type,
even if we just end up in here with the 1-wide path for now.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4425>
2020-04-04 12:33:49 +10:00
Rob Clark
0b06adb750 glsl: don't limit fp16 lowering to frag
This restriction doesn't belong in core code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
f054230ea3 freedreno: limit fp16 to frag and compute
To avoid dealing w/ some backend varying linking issues when mixing
precision vs geom/tess.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
c0d56efa31 freedreno/ir3: also precompile compute shaders for shaderdb
Similar as with draw shaders, nothing will trigger the final variant in
shader-db.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
37e052c8b0 freedreno: fix missing locking
Fixes: d0b3ccb060 ("freedreno: Fix detection of being in a blit for acc queries.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
f8fc690d1c freedreno/a6xx: add some compute logging
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
629c0cee0a freedreno/ir3/cf: use ssa-uses
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
72f6b03aec freedreno/ir3: add a pass to collect SSA uses
We don't really track these as the ir is transformed, but it would be a
useful thing for some passes to have.  So add a pass to collect this
information.  It uses instr->data (generic per-pass ptr), with the
hashsets hanging under a mem_ctx for easy disposal at the end of the
pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
67dbe8088f freedreno/ir3/cf: skip array load/store
Don't fold conversions into array (incl phi lowered to regs/array).
These aren't SSA.  Avoids crashes in particular in frag shaders with
flow control, which would leave a dangling array write disconnect from
the original cov src.

Possibly this could be slightly relaxed, if there is no other consumer
of the src, and it were in the same block.  But it would require
updating block->keeps, and taking care of barrier state.  Which isn't a
thing the cf pass does currently.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
c2d0cc8b8d freedreno/ir3: fixup cat3 32b vs 16b
These should be keyed on src arg type.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
e73a8a9703 freedreno/ir3/cf: handle widening too
We can also fold f16->f32 conversions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Rob Clark
bf64648864 nir: fix definition of imadsh_mix16 for vectors
Fixes: c27b3758fa ("nir/opcodes: Add new 'umul_low' and 'imadsh_mix16' opcodes")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4423>
2020-04-04 00:07:10 +00:00
Daniel Schürmann
1d293096d0 aco: use MUBUF to load subdword SSBO
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
8cfddc9199 aco: implement 8bit/16bit store_ssbo
Currently without alignment check, so that
we can only use the _byte and _short versions
and multi-component stores are split.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
3df0a41c75 aco: implement 8bit/16bit load_buffer
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
c70d014455 aco: implement storagePushConstant8 & storagePushConstant16
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
5718347c2b aco: implement vec2/3/4 with subdword operands
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
85521061d6 aco: prepare helper functions for subdword handling
- get_alu_src()
- emit_extract_vector()
- emit_split_vector()

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
fe08f0ccf9 aco: add byte_align_scalar() & trim_subdword_vector() helper functions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
23ac24f5b1 aco: add missing conversion operations for small bitsizes
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
d223e4e8de aco: don't vectorize 8/16bit load/store_ssbo
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
0bb3537676 aco: don't assume split_vector(create_vector) has the same number of elements when optimizing
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
c436743b0c aco: don't propagate SGPRs into subdword PSEUDO instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
8f1712ba2f aco: lower subdword shuffles correctly.
Note that subdword swaps are not yet implemented

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
ca38c1f1f1 aco: add builder function for subdword copy()
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
9f779a2518 aco: small refactoring of shuffle code lowering
Uses now bytes instead of 32bit size

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
0680b258f4 aco: align subdword registers during RA when necessary
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
031edbc4a5 aco: adapt register allocation for subdword registers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
2c74fc98b8 aco: create helper function to collect variables from register area
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
aca2bbf975 aco: add notion of subdword registers to register allocator
To not having to split the register file into single bytes,
we maintain a map with registers which contain subdword variables.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
90811554da aco: remove unnecessary reg_file.fill() operation in get_reg_create_vector()
No pipelinedb changes

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
7de003473c aco: fix Temp and assignment of renamed operands during RA
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
2d957311f1 aco: print subdword registers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
3c0c28a1ff aco: validate RA of subdword assignments
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
799bb10328 aco: validate uninitialized operands
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
9374659426 aco: validate register alignment of subdword operands and definitions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
ad4e104bb9 aco: validate p_create_vector with subdword elements properly
Also allows for undef operands

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
f01bf51a2b aco: refactor regClass setup for subdword VGPRs
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Rhys Perry
c4223fa512 aco: add emission support for register-allocated sdwa sels
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
8acb384471 aco: add sub-dword regclasses
Co-authored-by: Rhys Perry <pendingchaos02@gmail.com>

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Rhys Perry
9915af5ca1 aco: print and validate opsel
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Rhys Perry
b84d59af50 aco: add SDWA_instruction
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
00312f3c95 aco: add comparison operators for PhysReg
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Rhys Perry
34424b81df aco: make PhysReg in units of bytes
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Daniel Schürmann
dc69738b0f nir: fix unpack_64_4x16 in lower_alu_to_scalar()
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4002>
2020-04-03 23:13:15 +01:00
Lionel Landwerlin
373f1eb9de drm-shim: stub libdrm's use of realpath()
libdrm started using realpath to get the type of bus associated with a
given device. This stubs the very specific usage that prevents
drm-shim's device from being listed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4429>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4429>
2020-04-03 21:14:18 +00:00
Lionel Landwerlin
c3e305616c drm-shim: return device platform as specified
v2: Embed the libdrm dependency inside the drm-shim dependency

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Anholt <eric@anholt.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4429>
2020-04-03 21:14:18 +00:00
Jason Ekstrand
fa5a36dbd4 spirv: Rewrite CFG construction
This commit completely rewrites the way we extract a structured CFG from
SPIR-V.  The new approach is different in a few ways:

 1. It does a breadth-first search instead of depth-first.  This means
    that we've visited the merge node for a construct before we visit
    any of the nodes inside the construct.  This makes it easier to
    validate things like loop and switch nesting.

 2. We record more information in the CFG.  Earlier commits added a
    parent pointer to vtn_cf_node but we now record all of the merge and
    other special blocks for each CFG node.  This lets us validate
    things more precisely.

 3. It makes heavy use of merge blocks for walking the CFG.  Previously,
    we sort of used them as hints for trying to guess the CFG structure
    but things got dicey whenever a merge was missing.  We had some
    heuristics for how to handle short-circuiting if statements but it
    was a bunch of special cases.

    Now, we make them a fundamental part of walking the CFG.  When we
    encounter a control-flow construct, we add the body components of
    the construct to the BFS work list and then jump to the merge block
    if one exists to continue scanning the current CFG nesting level.
    If no merge block exists, we assume that means that control-flow
    never re-converges in a normal way and that the only way to get back
    to normality is with a direct jump such as a loop break or continue.
    This should make things far more robust when trying to deal with the
    more creative placement (or lack thereof) of merge instructions.

Reviewed-by: Alan Baker <alanbaker@google.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
2de5a41595 spirv: Add a parent field to vtn_cf_node
This makes it easier to crawl up the CF tree when trying to validate the
incoming SPIR-V control-flow.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
d94e464a9f spirv: Make vtn_function a vtn_cf_node
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
255aacbec1 spirv: Make vtn_case a vtn_cf_node
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
9d7fcf1de0 spirv: Add cast and loop helpers for vtn_cf_node
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
8c5c65d0d6 spirv: Add a vtn_block() helper
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3820>
2020-04-03 20:54:00 +00:00
Jason Ekstrand
991c426160 intel/nir: Enable load/store vectorization
This commit enables the I/O vectorization pass that was originally
written for ACO for Intel drivers.  We enable it for UBOs, SSBOs, global
memory, and SLM.  We only enable vectorization for the scalar back-end
because it vec4 makes certain alignment assumptions.

Shader-db results with iris on ICL:

    total instructions in shared programs: 16077927 -> 16068236 (-0.06%)
    instructions in affected programs: 199839 -> 190148 (-4.85%)
    helped: 324
    HURT: 0
    helped stats (abs) min: 2 max: 458 x̄: 29.91 x̃: 4
    helped stats (rel) min: 0.11% max: 38.94% x̄: 4.32% x̃: 1.64%
    95% mean confidence interval for instructions value: -37.02 -22.80
    95% mean confidence interval for instructions %-change: -5.07% -3.58%
    Instructions are helped.

    total cycles in shared programs: 336806135 -> 336151501 (-0.19%)
    cycles in affected programs: 16009735 -> 15355101 (-4.09%)
    helped: 458
    HURT: 154
    helped stats (abs) min: 1 max: 77812 x̄: 1542.50 x̃: 75
    helped stats (rel) min: <.01% max: 34.46% x̄: 5.16% x̃: 2.01%
    HURT stats (abs)   min: 1 max: 22800 x̄: 336.55 x̃: 20
    HURT stats (rel)   min: <.01% max: 17.11% x̄: 2.12% x̃: 1.00%
    95% mean confidence interval for cycles value: -1596.83 -542.49
    95% mean confidence interval for cycles %-change: -3.83% -2.82%
    Cycles are helped.

    total sends in shared programs: 814177 -> 809049 (-0.63%)
    sends in affected programs: 15422 -> 10294 (-33.25%)
    helped: 324
    HURT: 0
    helped stats (abs) min: 1 max: 256 x̄: 15.83 x̃: 2
    helped stats (rel) min: 1.33% max: 67.90% x̄: 21.21% x̃: 15.38%
    95% mean confidence interval for sends value: -19.67 -11.98
    95% mean confidence interval for sends %-change: -23.03% -19.39%
    Sends are helped.

    LOST:   7
    GAINED: 2

Most of the helped shaders were in the following titles:

 - Doom
 - Deus Ex: Mankind Divided
 - Aztec Ruins
 - Shadow of Mordor
 - DiRT Showdown
 - Tomb Raider (Rise, I think)

Five of the lost programs are SIMD16 shaders we lost from dirt showdown.
The other two are compute shaders in Aztec Ruins which switched from
SIMD8 to SIMD16.

Vulkan pipeline-db stats on ICL:

    Instructions in all programs: 296780486 -> 293493363 (-1.1%)
    Loops in all programs: 149669 -> 149669 (+0.0%)
    Cycles in all programs: 90999206722 -> 88513844563 (-2.7%)
    Spills in all programs: 1710217 -> 1730691 (+1.2%)
    Fills in all programs: 1931235 -> 1958138 (+1.4%)

By far the most help was in the Tomb Raider games.  A couple of Batman
games with DXVK were also helped.  In Shadow of the Tomb Raider:

    Instructions in all programs: 41614336 -> 39408023 (-5.3%)
    Loops in all programs: 32200 -> 32200 (+0.0%)
    Cycles in all programs: 1875498485 -> 1667034831 (-11.1%)
    Spills in all programs: 196307 -> 214945 (+9.5%)
    Fills in all programs: 282736 -> 307113 (+8.6%)

Benchmarks of real games I've done on this patch:

 - Rise of the Tomb Raider: +3%
 - Shadow of the Tomb Raider: +10%

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
36a32af008 nir/load_store_vectorize: Add support for nir_var_mem_global
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
b6273291b5 nir/load_store_vectorize: Use nir_iadd_imm for offsets
This makes it capable of handling 64-bit offsets

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
04d08ea149 nir/load_store_vectorize: Fix shared atomic info
These were clearly copied and pasted from SSBOs.  The shared atomics
don't have an SSBO index so their offset is src0 and data is src1.

Fixes: ce9205c03b "nir: add a load/store vectorization pass"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
c1bcb025db intel/nir: Lower memory access bit sizes later
We're about to do load/store vectorization right before this but we need
that to happen after we've done a round of optimization.  Otherwise,
we'll be getting unoptimized NIR in from ANV and the vectorizer won't be
able to do anything with it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
f1883cc73d iris: Set alignments on cbuf0 and constant reads
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
4c8b100388 anv: Improve brw_nir_lower_mem_access_bit_sizes
This commit makes us take both bit size and alignment into account so
that we can properly handle cases such as when we have a 32-bit store
to an 8-bit-aligned address.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Jason Ekstrand
c643979228 intel/fs: Choose memory message type based on bit size
Thanks to the NIR vectorizing pass, we're about to see alignments that
are higher than the bit size.  Previously, we could use either and we
just happened to choose alignment (probably the wrong choice) so it's
harmless to switch to detecting based on bit size.  This commit changes
things to take both into account which is more accurate to what the
messages we're using do.  We also beef up the asserts and make them more
consistent, more accurate, and more complete.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
2020-04-03 20:26:54 +00:00
Brian Ho
6e76453472 ir3: Disable copy prop for immediate ldlw offsets
Immediate offsets are currently collapsed for ldlw, but ldlw does
behave correctly with immediate values. For example,
`ldlw.u32 r0.x, l[4], 1` actually means to use the value of
regid 4 (r1.x) as the offset when we actually want it to use the
imm value of 4 as the offset.

This commit disables copy prop for ldlw offsets so the same
intrinsic gets compiled to:
  mov.u32u32 r0.y, 0x00000004
  ldlw.u32 r0.x, l[r0.y], 1

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439>
2020-04-03 19:44:46 +00:00
Rhys Perry
ea51f8f79a radv: fix null winsys gpu_info array
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: de550805c5 ('radv/winsys: spoof some values for num_render_backends in the null winsys')
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4437>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4437>
2020-04-03 17:40:32 +00:00
Icecream95
319158a814 pan/midgard: Fix a divide by zero in emit_alu_bundle
util_dynarray_grow_bytes divides by eltsize, but it's possible for
bundle->padding to be zero.

I changed the other call to util_dynarray_grow_bytes for consistency.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4397>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4397>
2020-04-03 16:49:04 +00:00
Brian Ho
355abfeed5 turnip: Advertise 8 bit subpixel precision
Previously, turnip advertised 4-bit subpixel precision when in
practice, a6xx seems to render with 8-bit precision. This caused
dEQP-VK.renderpass2.suballocation.subpass_dependencies.late_fragment_tests.*
to fail because they compare images rendered with turnip against
ones rendered via a software reference implementation parameterized
by turnip's VkPhysicalDeviceLimits.subPixelPrecisionBits value.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4172>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4172>
2020-04-03 16:27:56 +00:00
Pierre-Eric Pelloux-Prayer
61566f2ae1 mesa: update pipeline when re-linking a program in use
Updating was only done for bound program, so add the
same logic for existing pipelines.

This fixes piglit test arb_shader_storage_buffer_object-issue1258.
It might also help the following issue:
  https://gitlab.freedesktop.org/mesa/mesa/-/issues/1258

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4404>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4404>
2020-04-03 13:42:43 +00:00
Ilia Mirkin
1288ac7632 nv50: don't try to upload MSAA settings for BUFFER textures
We need the MSAA scaling parameters to properly fetch samples from MSAA
textures. These are stored in the miptree which wraps all regular
textures. However it does not wrap buffer textures, so make sure to skip
them rather than accessing out-of-bounds or unmapped memory.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2727
Fixes: 3bd40073b9 ("nv50: add support for texelFetch'ing MS textures")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4424>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4424>
2020-04-03 13:00:08 +00:00
Lionel Landwerlin
b38c32a573 intel/aub_viewer: fix access to freed memory
Windows closed while we're displaying them might lead to invalid
memory accessed, so use the safe iterators on the list of windows.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4430>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4430>
2020-04-03 15:46:24 +03:00
Rhys Perry
7e6aec6687 radv, aco: collect statistics if requested but executables are not
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2965>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2965>
2020-04-03 12:12:08 +00:00
Rhys Perry
507956ed04 aco: add vmem/smem score statistic
This isn't perfect (for example, changes might not be too meaningful when
comparing shaders with different control flow) but it should be useful for
evaluating scheduler changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2965>
2020-04-03 12:12:08 +00:00
Rhys Perry
b1544352c0 aco: add various compiler statistics
Adds these statistics:
- hash of code and constant data
- number of instructions
- number of copies from pseudo-instructions
- number of branches
- estimate of cycles spent not waiting in s_waitcnt
- number of vmem/smem "clauses"
- sgpr/vgpr usage before scheduling

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2965>
2020-04-03 12:12:08 +00:00
Rhys Perry
ad2703653f radv: add code for exposing compiler statistics
Statistics will be added to ACO in later commits.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2965>
2020-04-03 12:12:08 +00:00
Daniel Stone
bfb9c08e5c EGL: Add eglSetDamageRegionKHR to GLVND dispatch list
This was missed in the original conversion, which added support for
eglSetDamageRegionKHR to local EGL exports, but forgot to generate
updated dispatch for GLVND.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: 9827547313 ("egl/android: support for EGL_KHR_partial_update")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4403>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4403>
2020-04-03 12:22:51 +01:00
Eric Engestrom
8af2eba424 docs: update calendar, add news item, and link releases notes for 20.0.4
Note that the next 20.0.x releases numbers have been shifted as this was
not one of the planned releases.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4428>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4428>
2020-04-03 13:16:07 +02:00
Eric Engestrom
a89b08b744 docs/relnotes: add sha256sum for 20.0.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4428>
2020-04-03 13:11:59 +02:00
Eric Engestrom
71e6f15a24 docs: add release notes for 20.0.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4428>
2020-04-03 13:11:59 +02:00
Pierre-Eric Pelloux-Prayer
43f785419c util/xmlconfig: fix sha1 comparison code
Fixes: 8f48e7b1e9 ("util/xmlconfig: add new sha1 application attribute")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2730
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4426>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4426>
2020-04-03 11:44:00 +02:00
Samuel Pitoiset
655e8449d0 radv/llvm: enable 16-bit storage features on GFX6-GFX7
Should allow to play Doom Eternal on GFX6-GFX7 because the
driver now supports storageBuffer16BitAccess.

It's now supported and all CTS tests pass.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/857
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
3cd5450df5 ac/nir: split 16-bit SSBO stores on GFX6
Due to possible alignment issues, make sure to split stores of
16-bit vectors.

Doom Eternal requires storageBuffer16BitAccess.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
55fdcc03de ac/nir: split 16-bit load/store to global memory on GFX6
Due to possible alignment issues, make sure to split loads/stores
of 16-bit vectors.

Doom Eternal requires storageBuffer16BitAccess.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
7308f2e912 radv/llvm: enable 8-bit storage features on GFX6-GFX7
It's now supported and all CTS tests pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
c6bf1597d1 ac/nir: split 8-bit SSBO stores on GFX6
Due to possible alignment issues, make sure to split stores of
8-bit vectors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
433f3380eb ac/nir: split 8-bit load/store to global memory on GFX6
Due to possible alignment issues, make sure to split loads/stores
of 8-bit vectors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
2020-04-03 08:01:28 +00:00
Samuel Pitoiset
c953292630 aco: always optimize v_mad to v_madak in presence of literals
v_mad and v_madak are both 64-bit instructions, so it doesn't
increase code size to always apply a 32-bit literal instead of
using v_mad and a sgpr which contains that literal.

Found with some Youngblood shaders but help some other games.

vkpipeline-db (VEGA10):
Totals from affected shaders:
SGPRS: 46168 -> 46016 (-0.33 %)
VGPRS: 45576 -> 45564 (-0.03 %)
Code Size: 5187208 -> 5179584 (-0.15 %) bytes
Max Waves: 3297 -> 3297 (0.00 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4410>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4410>
2020-04-03 07:30:49 +00:00
Neil Roberts
63b4fcba33 glsl/lower_precision: Use vector.back() instead of vector.end()[-1]
The use of vector.end()[-1] seems to generate warnings in Coverity about
not allowing a negative argument to a parameter. The intention with the
code snippet is just to access the last element of the vector. The
vector.back() call acheives the same thing, is clearer and will
hopefully fix the Coverity warning.

I’m not exactly sure why Coverity thinks the array index can’t be
negative. cplusplus.com says that vector::end() returns a random access
iterator and that the type of the array index operator argument to that
should be the difference type for the container. It then also says that
difference_type for a vector is "a signed integral type".

Reviewed-by: Eric Anholt <eric@anholt.net>
2020-04-03 09:10:17 +02:00
Karol Herbst
ff1a3a00cb clover: fix build with single library clang build
Closes: #2560
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4417>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4417>
2020-04-03 04:07:38 +00:00
Drew Davenport
2243f0cd01 radv: Filter extensions not whitelisted for Android
Android enforces through CTS a whitelist of Vulkan extensions that are
allowed in each Android version. When building radv for Android, disable
extensions that are unknown to the version of Android for which
radv is being built.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4398>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4398>
2020-04-03 02:25:50 +00:00
Ilia Mirkin
d6368d404b st/vdpau: make query test for 2D support
The 3D check has been there since the dawn of time, but I see no reason
for it, most likely a typo. When the surfaces are actually created, they
use the 2D resource type (as expected).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4108>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4108>
2020-04-03 01:40:35 +00:00
Ilia Mirkin
c1cc79739a st/vdpau: avoid asserting on new VDP_YCBCR_* formats
Depending on user's vdpau headers, not all of those defines may exist.
Eventually we may want a private copy of these, but this is simple
enough for now.

Fixes asserts when running vdpauinfo which supports these recently added
formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4108>
2020-04-03 01:40:35 +00:00
Jason Ekstrand
c71c1f44b0 nir/from_ssa: Only chain movs when a src is also a dest
The algorithm we use for resolving parallel copy instructions plays this
little shell game with the values.  The reason for this is that it lets
us handle cases where, for instance we have a -> b and b -> a and we
need to use a temporary to do a swap.  One result of this algorithm is
that it tends to emit a lot of mov chains which are typcially really bad
for GPUs where a mov is far from free.  For instance, it's likely to
turn this:

    r16 = ssa_0; r17 = ssa_0; r18 = ssa_0; r15 = ssa_0

into this:

    r15 = mov ssa_0
    r18 = mov r15
    r17 = mov r18
    r16 = mov r17

which, if it's the only thing in a block (this is common for phis) is
impossible for a scheduler to fix because of the dependencies and you
end up with significant stalling.  If, on the other hand, we only do the
chaining in the actual case where we need to free up a so that it can be
used as a destination, we can emit this:

    r15 = mov ssa_0
    r18 = mov ssa_0
    r17 = mov ssa_0
    r16 = mov ssa_0

which is far nicer to the scheduler.  On Intel, our copy propagation
pass will undo the chain for us so this has no shader-db impact.
However, for less intelligent back-ends, it's probably a lot better.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4412>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4412>
2020-04-02 19:06:46 +00:00
Connor Abbott
73e574acb8 freedreno: Rename RB_DONE_TS
This makes the various cache_flush implementations make more sense.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065>
2020-04-02 16:18:25 +00:00
Connor Abbott
36133a5434 freedreno: Cleanup event names
It turns out that every *_TS event, i.e. every event which requires a
seqno pointer, also allows generating an interrupt in the kernel, at
least since a3xx. And furthermore these interrupts are named by the kgsl
kernel driver and already in envytools. Therefore it's possible to map
out what the *_TS events are with 100% certainty, given access to the
hardware, by sending a CP_EVENT_WRITE with bit 31 set, unmasking all
interrupts in the kernel, and logging which ones get hit. I've done this
for a6xx, and I've also looked at the a5xx firmware, and the list of TS
interrupts is the same as a6xx, so I have a pretty good idea of what the
a5xx events are. I also fixed a few related things along the way:

- VIZQUERY_END overlaps with WT_DONE_TS, but VIZQUERY_START was also a
mess, with neither VIZQUERY_START nor HLSQ_FLUSH using variants. I added
what seems like reasonable variants, based on the existing comment
and the fact that HLSQ_FLUSH is only used in Mesa with a3xx and a4xx.
- CACHE_FLUSH_AND_INVALIDATE seems to come straight from R600, and I
have no idea if it's actually valid with a2xx, but given that RB_DONE_TS
exists in the interrupt mask since a3xx, I guessed that RB_DONE_TS
hasn't changed position since then and put it down as a3xx+ and limited
CACHE_FLUSH_AND_INVALIDATE to a2xx. Someone with the relevant hardware
should be able to confirm.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065>
2020-04-02 16:18:25 +00:00
Roland Scheidegger
2077421437 gallivm: fix stream id fetch
Fetching the stream id directly can crash since bld->immediates may not
exist (if there's too many immediates or we use the array due to indirect
accesses). So just call emit_fetch_immediate instead.

v2: fix the swizzle

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4416>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4416>
2020-04-02 15:53:23 +00:00
Roland Scheidegger
0a3a880670 gallivm: switch the mask6/mask7 cases for signed rgtc formats
This fixes some regressions where -1.0/1.0 results got flipped, but it's still
broken in some cases.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4416>
2020-04-02 15:53:23 +00:00
Roland Scheidegger
ebb5b88a02 gallivm: fix rgtc2 format
In some cases, there can be garbage in the upper bits after the channel
decode - for dxt5 this didn't matter (as the upper bits are shifted out
anyway) but for rgtc2 formats it does.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4416>
2020-04-02 15:53:23 +00:00
Jason Ekstrand
5cc27d59a1 anv/image: Use align_u64 for image offsets
The ALIGN functions in util/u_math.h work on uintptr_t whose size
changes depending on your platform.  Use ones which take an explicit
64-bit type instead to avoid 32-bit platform issues.

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4414>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4414>
2020-04-02 15:08:42 +00:00
Adam Jackson
4e3a7dcf6e gallium: enable EGL_EXT_image_dma_buf_import_modifiers unconditionally
This is a re-do of [1].

Enable EGL_EXT_image_dma_buf_import_modifiers with
EXT_image_dma_buf_import. This allows users to use queryDmaBufFormats to
query the list of supported formats even if modifiers are not supported.

With this change, queryDmaBufModifiers always returns zero modifiers. A
compositor survey reveals that this should be fine: wlroots [2],
Weston [3], Mutter [4] [5], kwin [6] and xorg-xserver [7] seem to all
support this case gracefully.

Tested with Sway and wlroots by running weston-info and checking the
list of formats advertised by zwp_linux_dmabuf_v1. Also ran weston-simple-egl
and checked zwp_linux_dmabuf_v1 was used instead of wl_drm.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1812
[2]: 8707a9b7ec/render/egl.c (L629)
[3]: 786490cb53/libweston/renderer-gl/gl-renderer.c (L2337)
[4]: f0df07cba3/src/wayland/meta-wayland-dma-buf.c (L486)
[5]: 0a6034ef3a/src/backends/native/meta-renderer-native.c (L399)
[6]: https://cgit.kde.org/kwin.git/tree/platformsupport/scenes/opengl/egl_dmabuf.cpp?id=9b7ab4d16a8ee0cb35108362ee5aa046f4ae20b7#n473
[7]: 26004df63c/glamor/glamor_egl.c (L682)

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4298>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4298>
2020-04-02 14:22:58 +00:00
Marek Olšák
e0aa203fa9 driconf: whilelist more games for glthread
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4402>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4402>
2020-04-02 09:55:57 -04:00
Rohan Garg
d0f836e5ae tracie: Switch to using shutil.move for cross filesystem moves
When running tracie in a docker container, renaming files from
inside the container to a bind-mounted folder on the host causes
a invalid cross-device link due to os.rename limitations.

Switching to shutil allows us to overcome this.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4377>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4377>
2020-04-02 10:53:05 +00:00
Erik Faye-Lund
7b7dbd4fc8 wgl: do not create screen from DllMain
There's a lot of operations that aren't allowed from DllMain, so we
shouldn't create a driver-screen from there. So let's instead delay this
until it's needed from a normal function call.

See https://docs.microsoft.com/en-us/windows/win32/dlls/dllmain for
details about what is allowed and isn't from DllMain.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4307>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4307>
2020-04-02 09:51:58 +00:00
Erik Faye-Lund
99a0864b48 wgl: move screen-init to a helper
This will be useful in the next commit.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4307>
2020-04-02 09:51:58 +00:00
Erik Faye-Lund
098d4cf25f wgl: drop unused member
While we're at it, drop trying to re-calculate the max-size from the
max-level. It's not accurate on any drivers where the max-size isn't a
power of two anyway.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4307>
2020-04-02 09:51:58 +00:00
Erik Faye-Lund
0a8da6102d wgl: drop pointless debug_printf
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4307>
2020-04-02 09:51:58 +00:00
Pierre-Eric Pelloux-Prayer
dbc86fa3de radeonsi: dump shader stats when hitting the live cache
With the introduction of the live shader cache, when a shader is
fetched from the cache no stats are printed for shaderdb.
So in a sequence like this: vs1, fs1, vs1, fs2, shaderdb may see
3 or 4 lines, depending on the threads being used.
If one run produces 3 lines while the other produces 4 lines, it
would compare vs1 stats with fs2 stats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4355>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4355>
2020-04-02 08:31:37 +02:00
Pierre-Eric Pelloux-Prayer
8306c533fe gallium/util: let shader live cache users know if a hit occured
This will be used in next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4355>
2020-04-02 08:31:37 +02:00
Timothy Arceri
d259768e62 glsl_to_nir: remove dead code
This code was made unused by the changes described in be2990d8fb.

NIR based Gallium drivers switched to the NIR based lowering in
efa4fc0ebd.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4415>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4415>
2020-04-02 04:49:10 +00:00
Juan A. Suarez Romero
191ced539a anv/pipeline: allow more than 16 FS inputs
A fragment shader can have more than 16 inputs, so SBE emission should
deal with all of them.

This fixes dEQP-VK.pipeline.max_varyings.*

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2010>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2010>
2020-04-01 23:36:28 +00:00
Juan A. Suarez Romero
460de2159e intel/compiler: store the FS inputs in WM prog data
Store the fragment shader inputs in the program data so we can use them
later when required without needing the NIR shader.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2010>
2020-04-01 23:36:28 +00:00
Juan A. Suarez Romero
67c7cabd7f anv: use urb_setup_attribs in SBE
Avoid looping over all VARYING_SLOT_MAX urb_setup arrray entries.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2010>
2020-04-01 23:36:28 +00:00
Eric Engestrom
1ac9f362e0 docs: update calendar, add news item, and link releases notes for 20.0.3
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4413>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4413>
2020-04-02 00:06:57 +02:00
Eric Engestrom
a264edd74c docs/relnotes: add sha256sum for 20.0.3
(cherry picked from commit a680481532)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4413>
2020-04-02 00:04:10 +02:00
Eric Engestrom
2e01090b54 docs: add release notes for 20.0.3
(cherry picked from commit b04ae1f964)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4413>
2020-04-02 00:04:10 +02:00
Dave Airlie
2a2fd4c530 gallium/llvmpipe: add an optimised 32-bit memset
This might have other users beyond filling/clearing buffers,

increase a fullscreen 4k gears from 68->74 fps on my Ryzen
since gears is really just a clear benchmark, and this helps
clearing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4394>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4394>
2020-04-01 20:58:23 +00:00
Mark Janes
c07bbdbe82 nir: place aligned members after bitfields in shader_info.tess
The placement of new shader_info.tess members unnecessarily wastes
space by interspersing 64bit members between bitfields.

Fixes: f1dd81ae10 ("nir: Collect if shader uses cross-invocation or indirect I/O.")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4408>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4408>
2020-04-01 20:25:55 +00:00
Mark Janes
90a8b458ac nir: check shader type before writing to shaderinfo.tess union
If the shader is not a tesselation shader, then writing to the tess
member of the shaderinfo union will overwrite other members and crash.

Closes: #2722
Fixes: f1dd81ae10 ("nir: Collect if shader uses cross-invocation or indirect I/O.")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4408>
2020-04-01 20:25:55 +00:00
Danylo Piliaiev
e47bf7dadf anv: Do not sample from 3d depth image with HiZ
For Gen8-11, there are some restrictions around sampling from HiZ.
The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
say:

    "If this field is set to AUX_HIZ, Number of Multisamples must
    be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."

Fixes: dEQP-VK.geometry.layered.3d.*.readback

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2720
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Arcady Goldmints-Orlov <agoldmints@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4409>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4409>
2020-04-01 20:12:29 +00:00
Krzysztof Raszkowski
0487130d34 gallium/swr: Re-enable scratch space for client-memory buffers
Commit 7d33203b44 fixed race condition
in freeing scratch memory mechanism but that approach creates
performance regression in some cases. This change revert previous
changes and fix freeing scratch memory mechanism.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4406>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4406>
2020-04-01 20:00:06 +00:00
Krzysztof Raszkowski
37b8130bf9 gallium/swr: Fix array stride problem.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4405>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4405>
2020-04-01 19:43:50 +00:00
Eric Anholt
c1e7e83d52 ci: Consistently use -j4 across x86 build jobs and -j8 on ARM.
Our shared runners are set up for concurrent jobs ~= CPUs / 4 (x86) or 8
(ARM).  If you use more build processes than that, then jobs may be
fighting each other for shared system resources, possibly to the point of
failure (we've seen one of the runners OOM on some jobs before, though I'm
not sure if this was the cause).

To try to systematically prevent the problem, we make a ninja wrapper in
the containers that passes the -j flags, and set MAKEFLAGS in the
container builds.  This doesn't cover make in non-container builds, but I
believe we don't have any of those.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3782>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3782>
2020-04-01 18:33:58 +00:00
Samuel Pitoiset
2f424c83e0 aco: only break SMEM clauses if XNACK is enabled (mostly APUs)
According to LLVM, it seems only required for APUs like RAVEN, but
we still ensure that SMEM stores are in their own clause.

pipeline-db (VEGA10):
Totals from affected shaders:
SGPRS: 1775364 -> 1775364 (0.00 %)
VGPRS: 1287176 -> 1287176 (0.00 %)
Spilled SGPRs: 725 -> 725 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 65386620 -> 65107460 (-0.43 %) bytes
Max Waves: 287099 -> 287099 (0.00 %)

pipeline-db (POLARIS10):
Totals from affected shaders:
SGPRS: 1797743 -> 1797743 (0.00 %)
VGPRS: 1271108 -> 1271108 (0.00 %)
Spilled SGPRs: 730 -> 730 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 64046244 -> 63782324 (-0.41 %) bytes
Max Waves: 254875 -> 254875 (0.00 %)

This only affects GFX6-GFX9 chips because the compiler uses a
different pass for GFX10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4349>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4349>
2020-04-01 17:50:31 +00:00
Jason Ekstrand
68f325b256 Revert "spirv: Implement OpCopyObject and OpCopyLogical as blind copies"
This reverts commit 7a53e67816.
2020-04-01 12:40:34 -05:00
Emil Velikov
91478db20d loader: fallback to kernel name, if PCI fails
Currently, if the PCI machinery fails, we return a NULL driver name.
In the past this has resulted in various workarounds.

To avoid those, fallback to loader_get_kernel_driver_name(). It's not
perfect, yet perfectly reasonable.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:57:22 +01:00
Emil Velikov
bf1838838a loader: move "using driver..." message to loader_get_kernel_driver_name
Move the message to the function which fetches the name.

While here use the same DEBUG/WARNING approach like in the PCI case. The
current method spam a tad much, plus isn't consistent.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:57:22 +01:00
Emil Velikov
e3572f977f loader: simplify codeflow in drm_get_pci_id_for_fd
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:57:22 +01:00
Emil Velikov
164f4a9a4a loader: simplify loader_get_user_preferred_fd()
Reoder the function a bit to make the code-flow more obvious and short.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:57:22 +01:00
Emil Velikov
25b2b32588 loader: use a maximum of 64 drmDevices
Currently that's the hard-coded maximum in the kernel, even though the
libdrm API allows for more. Latter is done with extendability in mind.

Allocate 64 pointers^Wdevices on stack for now. Making for shorter and
ever-so-slightly faster code.

v2: Use single MAX_DRM_DEVICES #define (Eric)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com> (v1)
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:57:22 +01:00
Emil Velikov
d3c9143971 Revert "egl/dri2: Don't dlclose() the driver on dri2_load_driver_common failure"
This reverts commit 1b87f4058d.

dlclose() of the handle is perfectly reasonable, a follow-up NULL
assignment is missing.

As-is this causes a leak for nearly every platform, since they call
dri2_load_driver* initially, followed by a second swrast fallback call.

Some platforms even loop through the existing drivers probing.

Revert the commit and add the NULL check.

Fixes: 1b87f4058d ("egl/dri2: Don't dlclose() the driver on dri2_load_driver_common failure")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:24:19 +01:00
Emil Velikov
fa5e800e05 egl/drm: reinstate (kms_)swrast support
With earlier commit we've added a generic LIBGL_ALWAYS_SOFTWARE handling
yet did not consider that the existing codebase unconditionally errors
out when set. That was fixed with a latter commit, while the fix itself
added erroneous restriction for egl/drm.

As mentioned in the report - the feature was working for ages. It was a
Gnome developer who added kms_swrast support for gbm in the first place.

Admittedly kms_swrast is somewhat in the middle between traditional
swrast and HW drivers, regardless - reinstate support.

Fixes: 47273d7312 ("egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/165
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:21:36 +01:00
Emil Velikov
b699d070a6 glx: set the loader_logger early and for everyone
Currently we set the logger only for DRI3. Even though it's used nearly
everywhere. For platforms where we don't the function is effectively a
no-op.

With this in place, LIBGL_DEBUG=verbose works across the board.

Fixes: d971a4230d ("loader: Factor out the common driver opening logic from each loader.")
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:21:32 +01:00
Emil Velikov
06f758b093 meson: glx: drop with_glx == dri check
We can get into src/glx only with with_glx == dri. Thus there's no point
in the secondary, nested, check - it's always true.

Cc: Dylan Baker <dylan@pnwbakers>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4084>
2020-04-01 16:21:28 +01:00
Erik Faye-Lund
70ac7f5b0c mesa/main: remove unused macro
This macro is no longer used, so let's get rid of it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
9ddd9d454c mesa/main: clean up extension-check for GL_TEXTURE_EXTERNAL
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
dd6b35c99e mesa/main: clean up extension-check for GL_RASTERIZER_DISCARD
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
0006dfbaed mesa/main: clean up extension-check for GL_TEXTURE_CUBE_MAP_SEAMLESS
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
994675b24d mesa/main: clean up extension-check for GL_FRAGMENT_SHADER_ATI
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
541708680f mesa/main: clean up extension-check for AMD_depth_clamp_separate
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
e2dbd31dc0 mesa/main: clean up extension-check for GL_DEPTH_BOUNDS_TEST
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
67a7022f83 mesa/main: clean up extension-check for GL_STENCIL_TEST_TWO_SIDE
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
421a1accf0 mesa/main: clean up extension-check for GL_TEXTURE_RECTANGLE
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
81d901aef1 mesa/main: clean up extension-check for GL_VERTEX_PROGRAM_POINT_SIZE
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
a5e781aa80 mesa/main: clean up extension-check for GL_VERTEX_PROGRAM_TWO_SIDE
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
12e228fc9c mesa/main: clean up extension-check for GL_VERTEX_PROGRAM
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
23570066bf mesa/main: clean-up extension-checks for point-sprites
This is the only user of the CHECK_EXTENSION2 macro, so let's remove
that while we're at it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:57 +02:00
Erik Faye-Lund
70b6972140 mesa/main: correct extension-checks for GL_BLACKHOLE_RENDER_INTEL
KHR_blend_equation_advanced_coherent isn't exposed on OpenGL ES 1.x
nor OpenGL versions prior to 30, so we shouldn't allow to query its
enum-states there either.

Fixes: 74ec39f66d ("mesa: add INTEL_blackhole_render")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/329>
2020-04-01 12:57:43 +02:00
Eric Anholt
1e3b74ee73 loader: Warn when we fail to open a device node due to permissions.
This is definitely not the first time I've debugged why I'm getting swrast
on a device only to find out I'm not a member of the render node's group.

This does mean that you'll get a warning print even without EGL_LOG_LEVEL
set.  This may be an issue if we expect people outside of the DRI node's
group to actually be using swrast instead of getting their permissions
fixed.  Right now surfaceless throws a "libEGL warning: No hardware driver
found, falling back to software rendering" in that case anyway, so this is
just more informative.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3703>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3703>
2020-04-01 09:32:25 +00:00
Thomas Hellstrom
15a9f6c072 svga: Treat forced coherent maps as maps of persistent memory
A previous commit made sure we sent a BindGBSurface command at map time
rather than at unmap time for persistent memory. To be consistent, do the
same for forced coherent maps. This makes it possible to avoid the
explicit UpdateGBSurface at unmap time for discard maps and to instead rely
on the kernel's dirty-tracking mechanism at the cost of an additional flush.

Tested with SVGA_FORCE_COHERENT=1, piglit run quick. No regressions.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4399>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4399>
2020-04-01 08:58:28 +02:00
Thomas Hellstrom
46fdc288fb svga, winsys/svga: Fix persistent memory discard maps
The kernel driver requires immediate notification using a
BindGBSurface command when a graphics coherent memory resource changes
backing MOB, so that it can start dirty-tracking the new MOB.
Since we always use graphics coherent memory for persistent memory, enqueue
and flush a BindGBSurface commmand at map time rather than at unmap time.
Since we're dealing with persistent memory, It's OK to flush while mapped.

This fixes an issue with gnome-shell / Wayland which uses persistent
memory together with discard maps when we advertise ARB_buffer_storage.
XWayland clients will render incorrectly.

Fixes: 71b43490dd ("svga: Support ARB_buffer_storage")
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4399>
2020-04-01 08:38:04 +02:00
Alyssa Rosenzweig
1b16d6354b pan/bi: Fix outmod/roundmode flip
I misread the disassembler, the fields are in the other order.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
12cf9f43f0 pan/bi: Handle fmov class ops
We need to lower them to something reasonable (ideally, the modifier
would be attached but we need to do something for the case it's not). We
specifically have to lower pre-sched as well, but we can do the lower
literally at schedule time for now (if this proves annoying, we can move
it earlier, but I want to leave room for modifier-aware copyprop should
that prove interesting).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
357b8b5906 pan/bi: Fix unused port swapping
Fixes INSTR_INVALID_ENC

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b150fa214b pan/bi: Add cmdline option for verbose disassembly
Useful for debugging packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
ae4f48b2bc pan/bi: Don't set the back-to-back bit yet
This is bad for performance but we can't assume it's true without some
analysis, which we presently don't do. Leave it for future work and
don't break the present.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
0b241c70b6 pan/bi: Use STAGE srcs for scheduler nops
..rather than using port 0 for the source, which may or may not actually
exist.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
2292e2aa10 pan/bi: Fix writes_component for VECTOR
I'm not convinced this is the best way and it's sort of a hack, but it
fixes RA for st_vary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b033189dd7 pan/bit: Wire through I/O
We'd like to wire in attributes and uniforms as inputs and look at the
varying as output for automatic testing on-device, building up a test
framework for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Alyssa Rosenzweig
b26214e907 pan/bit: Add run mode to the cmdline
This emulates the functionality of shader_runner (built for kbase) using
the bifrost testing infrastructure so it runs on mainline. Ideally this
will let us test shaders from the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
2020-04-01 02:25:05 +00:00
Jose Fonseca
cb56d5d9f8 appveyor: Remove Meson job.
Appveyor Meson fails misteriously some times, e.g.,
- https://ci.appveyor.com/project/mesa3d/mesa/builds/31780753/job/w8b28iahboxq4na2
- https://ci.appveyor.com/project/mesa3d/mesa/builds/31857376
and now that we have msvc coverage on gitlab ci this is no longer necessary.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4392>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4392>
2020-04-01 01:13:21 +00:00
Rob Clark
59754409cc freedreno/log: fix build error
It seems some versions of gcc are less clever about const initializers:

```
../src/gallium/drivers/freedreno/freedreno_log.c:58:33: error: initializer element is not constant
 const unsigned msgs_per_chunk = bo_size / sizeof(uint64_t);
                                 ^~~~~~~
```

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/2713

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4390>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4390>
2020-04-01 00:51:09 +00:00
Ian Romanick
b097e326b8 nir/algebraic: Remove a redundant fabs pattern
Made redundant by 5544b2cbbd ("nir/algebraic: Use value range analysis
to eliminate useless unary ops").

No shader-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
Ian Romanick
af1bc7e0c7 nir/algebraic: Use value range analysis to convert fmax to fsat
This is conceptually similar to the 1-fsat(a) <=> fsat(1-a) rearragement
done in:

3b74790941 ("nir/algebraic: Recognize open-coded flrp(a, b, fsat(c))")

2d259713b7 ("nir/algebraic: Commute 1-fsat(a) to fsat(1-a) for all
non-fmul instructions").

Note: this helps the Aztex Ruins shader that was hurt for spills and
fills on Braodwell in the previous commit, but it does not fix the
spills or fills. :(

All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14528985 -> 14526116 (-0.02%)
instructions in affected programs: 477300 -> 474431 (-0.60%)
helped: 2332
HURT: 0
helped stats (abs) min: 1 max: 18 x̄: 1.23 x̃: 1
helped stats (rel) min: 0.07% max: 8.89% x̄: 0.88% x̃: 0.64%
95% mean confidence interval for instructions value: -1.27 -1.19
95% mean confidence interval for instructions %-change: -0.92% -0.85%
Instructions are helped.

total cycles in shared programs: 203723684 -> 203692984 (-0.02%)
cycles in affected programs: 4878847 -> 4848147 (-0.63%)
helped: 1764
HURT: 324
helped stats (abs) min: 1 max: 706 x̄: 22.94 x̃: 17
helped stats (rel) min: <.01% max: 17.75% x̄: 1.94% x̃: 1.66%
HURT stats (abs)   min: 1 max: 400 x̄: 30.15 x̃: 10
HURT stats (rel)   min: <.01% max: 17.76% x̄: 1.91% x̃: 0.69%
95% mean confidence interval for cycles value: -16.55 -12.86
95% mean confidence interval for cycles %-change: -1.44% -1.24%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
Ian Romanick
62795475e8 nir/algebraic: Distribute source modifiers into instructions
There are three main classes of cases that are helped by this change:

1. When the negation is applied to a value being type converted (e.g.,
   float(-x)).  This could possibly also be handled with more clever
   code generation.

2. When the negation is applied to a phi node source (e.g., x = -(...);
   at the end of a basic block).  This was the original case that caught
   my attention while looking at shader-db dumps.

3. When the negation is applied to the source of an instruction that
   cannot have source modifiers.  This includes texture instructions and
   math box instructions on pre-Gen7 platforms (see more details below).

In many these cases the negation can be propagated into the instructions
that generate the value (e.g., -(a*b) = (-a)*b).

In addition to the operations implemtned in this patch, I also tried:

 - frcp - Helped 6 or fewer shaders on Gen7+, and hurt just as many on
   pre-Gen7.  On Gen6 and earlier, frcp is a math box instruction, and
   math box instructions cannot have source modifiers.

   I suspect this is why so many more shaders are helped on Gen6 than on
   Gen5 or Gen7.  Gen6 supports OpenGL 3.3, so a lot more shaders
   compile on it.  A lot of these shaders may have things like cos(-x)
   or rcp(-x) that could result in an explicit negation instruction.

 - bcsel - Hurt a few shaders with none helped.  bcsel operates on
   integer sources, so the fabs or fneg cannot be a source modifier in
   the bcsel itself.

 - Integer instructions - No changes on any Intel platform.

Some notes about the shader-db results below.

 - On Tiger Lake, a single Deus Ex fragment shader is hurt for both
   spills and fills.

 - On Haswell, a different Deus Ex fragment shader is hurt for both
   spills and fills.

 - On GM45, the "LOST: 1" and "GAINED: 1" is a single Left4Dead 2
   (very high graphics settings, lol) fragment shader that upgrades
   from SIMD8 to SIMD16.

v2: Add support for fsign.  Add some patterns that remove redundant
negations and redundant absolute value rather than trying to push them
down the tree.

Tiger Lake
total instructions in shared programs: 17611333 -> 17586465 (-0.14%)
instructions in affected programs: 3033734 -> 3008866 (-0.82%)
helped: 10310
HURT: 632
helped stats (abs) min: 1 max: 35 x̄: 2.61 x̃: 1
helped stats (rel) min: 0.04% max: 16.67% x̄: 1.43% x̃: 1.01%
HURT stats (abs)   min: 1 max: 47 x̄: 3.21 x̃: 2
HURT stats (rel)   min: 0.04% max: 5.08% x̄: 0.88% x̃: 0.63%
95% mean confidence interval for instructions value: -2.33 -2.21
95% mean confidence interval for instructions %-change: -1.32% -1.27%
Instructions are helped.

total cycles in shared programs: 338365223 -> 338262252 (-0.03%)
cycles in affected programs: 125291811 -> 125188840 (-0.08%)
helped: 5224
HURT: 2031
helped stats (abs) min: 1 max: 5670 x̄: 46.73 x̃: 12
helped stats (rel) min: <.01% max: 34.78% x̄: 1.91% x̃: 0.97%
HURT stats (abs)   min: 1 max: 2882 x̄: 69.50 x̃: 14
HURT stats (rel)   min: <.01% max: 44.93% x̄: 2.35% x̃: 0.74%
95% mean confidence interval for cycles value: -18.71 -9.68
95% mean confidence interval for cycles %-change: -0.80% -0.63%
Cycles are helped.

total spills in shared programs: 8942 -> 8946 (0.04%)
spills in affected programs: 8 -> 12 (50.00%)
helped: 0
HURT: 1

total fills in shared programs: 9399 -> 9401 (0.02%)
fills in affected programs: 21 -> 23 (9.52%)
helped: 0
HURT: 1

Ice Lake
total instructions in shared programs: 16124348 -> 16102258 (-0.14%)
instructions in affected programs: 2830928 -> 2808838 (-0.78%)
helped: 11294
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.96 x̃: 1
helped stats (rel) min: 0.07% max: 17.65% x̄: 1.32% x̃: 0.93%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 3.45% max: 4.00% x̄: 3.72% x̃: 3.72%
95% mean confidence interval for instructions value: -1.99 -1.93
95% mean confidence interval for instructions %-change: -1.34% -1.29%
Instructions are helped.

total cycles in shared programs: 335393932 -> 335325794 (-0.02%)
cycles in affected programs: 123834609 -> 123766471 (-0.06%)
helped: 5034
HURT: 2128
helped stats (abs) min: 1 max: 3256 x̄: 43.39 x̃: 11
helped stats (rel) min: <.01% max: 35.79% x̄: 1.98% x̃: 1.00%
HURT stats (abs)   min: 1 max: 2634 x̄: 70.63 x̃: 16
HURT stats (rel)   min: <.01% max: 49.49% x̄: 2.73% x̃: 0.62%
95% mean confidence interval for cycles value: -13.66 -5.37
95% mean confidence interval for cycles %-change: -0.69% -0.48%
Cycles are helped.

LOST:   0
GAINED: 2

Skylake
total instructions in shared programs: 14949240 -> 14927930 (-0.14%)
instructions in affected programs: 2594756 -> 2573446 (-0.82%)
helped: 11000
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.94 x̃: 1
helped stats (rel) min: 0.07% max: 18.75% x̄: 1.39% x̃: 0.94%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 4.76% max: 4.76% x̄: 4.76% x̃: 4.76%
95% mean confidence interval for instructions value: -1.97 -1.91
95% mean confidence interval for instructions %-change: -1.42% -1.37%
Instructions are helped.

total cycles in shared programs: 324829346 -> 324821596 (<.01%)
cycles in affected programs: 121566087 -> 121558337 (<.01%)
helped: 4611
HURT: 2147
helped stats (abs) min: 1 max: 3715 x̄: 33.29 x̃: 10
helped stats (rel) min: <.01% max: 36.08% x̄: 1.94% x̃: 1.00%
HURT stats (abs)   min: 1 max: 2551 x̄: 67.88 x̃: 16
HURT stats (rel)   min: <.01% max: 53.79% x̄: 3.69% x̃: 0.89%
95% mean confidence interval for cycles value: -4.25 1.96
95% mean confidence interval for cycles %-change: -0.28% -0.02%
Inconclusive result (value mean confidence interval includes 0).

Broadwell
total instructions in shared programs: 14971203 -> 14949957 (-0.14%)
instructions in affected programs: 2635699 -> 2614453 (-0.81%)
helped: 10982
HURT: 2
helped stats (abs) min: 1 max: 12 x̄: 1.93 x̃: 1
helped stats (rel) min: 0.07% max: 18.75% x̄: 1.39% x̃: 0.94%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 4.76% max: 4.76% x̄: 4.76% x̃: 4.76%
95% mean confidence interval for instructions value: -1.97 -1.90
95% mean confidence interval for instructions %-change: -1.42% -1.37%
Instructions are helped.

total cycles in shared programs: 336215033 -> 336086458 (-0.04%)
cycles in affected programs: 127383198 -> 127254623 (-0.10%)
helped: 4884
HURT: 1963
helped stats (abs) min: 1 max: 25696 x̄: 51.78 x̃: 12
helped stats (rel) min: <.01% max: 58.28% x̄: 2.00% x̃: 1.05%
HURT stats (abs)   min: 1 max: 3401 x̄: 63.33 x̃: 16
HURT stats (rel)   min: <.01% max: 39.95% x̄: 2.20% x̃: 0.70%
95% mean confidence interval for cycles value: -29.99 -7.57
95% mean confidence interval for cycles %-change: -0.89% -0.71%
Cycles are helped.

total fills in shared programs: 24905 -> 24901 (-0.02%)
fills in affected programs: 117 -> 113 (-3.42%)
helped: 4
HURT: 0

LOST:   0
GAINED: 16

Haswell
total instructions in shared programs: 13148927 -> 13131528 (-0.13%)
instructions in affected programs: 2220941 -> 2203542 (-0.78%)
helped: 8017
HURT: 4
helped stats (abs) min: 1 max: 12 x̄: 2.17 x̃: 1
helped stats (rel) min: 0.07% max: 15.25% x̄: 1.40% x̃: 0.93%
HURT stats (abs)   min: 1 max: 7 x̄: 2.50 x̃: 1
HURT stats (rel)   min: 0.33% max: 4.76% x̄: 2.73% x̃: 2.91%
95% mean confidence interval for instructions value: -2.21 -2.13
95% mean confidence interval for instructions %-change: -1.43% -1.37%
Instructions are helped.

total cycles in shared programs: 321221791 -> 321079870 (-0.04%)
cycles in affected programs: 126886055 -> 126744134 (-0.11%)
helped: 4674
HURT: 1729
helped stats (abs) min: 1 max: 23654 x̄: 56.47 x̃: 16
helped stats (rel) min: <.01% max: 53.22% x̄: 2.13% x̃: 1.05%
HURT stats (abs)   min: 1 max: 3694 x̄: 70.58 x̃: 18
HURT stats (rel)   min: <.01% max: 63.06% x̄: 2.48% x̃: 0.90%
95% mean confidence interval for cycles value: -33.31 -11.02
95% mean confidence interval for cycles %-change: -0.99% -0.78%
Cycles are helped.

total spills in shared programs: 19872 -> 19874 (0.01%)
spills in affected programs: 21 -> 23 (9.52%)
helped: 0
HURT: 1

total fills in shared programs: 20941 -> 20941 (0.00%)
fills in affected programs: 62 -> 62 (0.00%)
helped: 1
HURT: 1

LOST:   0
GAINED: 8

Ivy Bridge
total instructions in shared programs: 11875553 -> 11853839 (-0.18%)
instructions in affected programs: 1553112 -> 1531398 (-1.40%)
helped: 7304
HURT: 3
helped stats (abs) min: 1 max: 16 x̄: 2.97 x̃: 2
helped stats (rel) min: 0.07% max: 15.25% x̄: 1.62% x̃: 1.15%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.05% max: 3.33% x̄: 2.44% x̃: 2.94%
95% mean confidence interval for instructions value: -3.04 -2.90
95% mean confidence interval for instructions %-change: -1.65% -1.59%
Instructions are helped.

total cycles in shared programs: 178246425 -> 178184484 (-0.03%)
cycles in affected programs: 13702146 -> 13640205 (-0.45%)
helped: 4409
HURT: 1566
helped stats (abs) min: 1 max: 531 x̄: 24.52 x̃: 13
helped stats (rel) min: <.01% max: 38.67% x̄: 2.14% x̃: 1.02%
HURT stats (abs)   min: 1 max: 356 x̄: 29.48 x̃: 10
HURT stats (rel)   min: <.01% max: 64.73% x̄: 1.87% x̃: 0.70%
95% mean confidence interval for cycles value: -11.60 -9.14
95% mean confidence interval for cycles %-change: -1.19% -0.99%
Cycles are helped.

LOST:   0
GAINED: 10

Sandy Bridge
total instructions in shared programs: 10695740 -> 10667483 (-0.26%)
instructions in affected programs: 2337607 -> 2309350 (-1.21%)
helped: 10720
HURT: 1
helped stats (abs) min: 1 max: 49 x̄: 2.64 x̃: 2
helped stats (rel) min: 0.07% max: 20.00% x̄: 1.54% x̃: 1.13%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.04% max: 1.04% x̄: 1.04% x̃: 1.04%
95% mean confidence interval for instructions value: -2.69 -2.58
95% mean confidence interval for instructions %-change: -1.57% -1.51%
Instructions are helped.

total cycles in shared programs: 153478839 -> 153416223 (-0.04%)
cycles in affected programs: 22050900 -> 21988284 (-0.28%)
helped: 5342
HURT: 2200
helped stats (abs) min: 1 max: 1020 x̄: 20.34 x̃: 16
helped stats (rel) min: <.01% max: 24.05% x̄: 1.51% x̃: 0.86%
HURT stats (abs)   min: 1 max: 335 x̄: 20.93 x̃: 6
HURT stats (rel)   min: <.01% max: 20.18% x̄: 1.03% x̃: 0.30%
95% mean confidence interval for cycles value: -9.18 -7.42
95% mean confidence interval for cycles %-change: -0.82% -0.71%
Cycles are helped.

Iron Lake
total instructions in shared programs: 8114882 -> 8105574 (-0.11%)
instructions in affected programs: 1232504 -> 1223196 (-0.76%)
helped: 4109
HURT: 2
helped stats (abs) min: 1 max: 6 x̄: 2.27 x̃: 1
helped stats (rel) min: 0.05% max: 8.33% x̄: 0.99% x̃: 0.66%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.94% max: 4.35% x̄: 2.65% x̃: 2.65%
95% mean confidence interval for instructions value: -2.31 -2.21
95% mean confidence interval for instructions %-change: -1.01% -0.96%
Instructions are helped.

total cycles in shared programs: 188504036 -> 188466296 (-0.02%)
cycles in affected programs: 31203798 -> 31166058 (-0.12%)
helped: 3447
HURT: 36
helped stats (abs) min: 2 max: 92 x̄: 11.03 x̃: 8
helped stats (rel) min: <.01% max: 5.41% x̄: 0.21% x̃: 0.13%
HURT stats (abs)   min: 2 max: 30 x̄: 7.33 x̃: 6
HURT stats (rel)   min: 0.01% max: 1.65% x̄: 0.18% x̃: 0.10%
95% mean confidence interval for cycles value: -11.16 -10.51
95% mean confidence interval for cycles %-change: -0.22% -0.20%
Cycles are helped.

LOST:   0
GAINED: 1

GM45
total instructions in shared programs: 4989697 -> 4984531 (-0.10%)
instructions in affected programs: 703952 -> 698786 (-0.73%)
helped: 2493
HURT: 2
helped stats (abs) min: 1 max: 6 x̄: 2.07 x̃: 1
helped stats (rel) min: 0.05% max: 8.33% x̄: 1.03% x̃: 0.66%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.95% max: 4.35% x̄: 2.65% x̃: 2.65%
95% mean confidence interval for instructions value: -2.13 -2.01
95% mean confidence interval for instructions %-change: -1.07% -0.99%
Instructions are helped.

total cycles in shared programs: 128929136 -> 128903886 (-0.02%)
cycles in affected programs: 21583096 -> 21557846 (-0.12%)
helped: 2214
HURT: 17
helped stats (abs) min: 2 max: 92 x̄: 11.44 x̃: 8
helped stats (rel) min: <.01% max: 5.41% x̄: 0.24% x̃: 0.13%
HURT stats (abs)   min: 2 max: 8 x̄: 4.24 x̃: 4
HURT stats (rel)   min: 0.01% max: 1.65% x̄: 0.20% x̃: 0.09%
95% mean confidence interval for cycles value: -11.75 -10.88
95% mean confidence interval for cycles %-change: -0.25% -0.22%
Cycles are helped.

LOST:   1
GAINED: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
Ian Romanick
c0bdf37c91 nir/algebraic: Change the default cursor location when replacing a unary op
If the expression tree that is being replaced has a unary operation at
its root, set the cursor (location where new instructions are inserted)
at the source instruction instead.

This doesn't do much now because there are very few patterns that have a
unary operation as the root.  Almost all of the patterns that do have a
unary operation as the root have inot.  All of the shaders that are
affected by this commit have expression trees with an inot at the root.

This change prevents some significant, spurious caused by the next
commit.  There is further explanation in the large comment added in
the code.

I also considered a couple other options that may still be worth exploring.

1. Add some mark-up to the search pattern to denote where new
   instructions should be added.  I considered using "@" to denote the
   cursor location.  For example,

    (('fneg', ('fadd@', a, b)), ...)

2. To prevent other kinds of unintended code motion, add the ability to
   name expressions in the search pattern so that they can be reused in
   the replacement.  For example,

   (('bcsel', ('ige', ('find_lsb=b', a), 0), ('find_lsb', a), -1), b),

   An alternative would be to add some kind of CSE at the time of
   inserting the replacements.  Create a new instruction, then check to
   see if it already exists.  That option might be better overall.

Over the years I know Matt has heard me complain, "I added a pattern
that just deleted an instruction, but it added a bunch of spills!"  This
was always in large, complex shaders that are very hard to analyze.  I
always blamed these cases on the scheduler being dumb.  I am now very
suspicious that unintended code motion was the real problem.

All Gen4+ Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 17611405 -> 17611333 (<.01%)
instructions in affected programs: 18613 -> 18541 (-0.39%)
helped: 41
HURT: 13
helped stats (abs) min: 1 max: 18 x̄: 4.46 x̃: 4
helped stats (rel) min: 0.27% max: 5.68% x̄: 1.29% x̃: 1.34%
HURT stats (abs)   min: 1 max: 20 x̄: 8.54 x̃: 7
HURT stats (rel)   min: 0.30% max: 4.20% x̄: 2.15% x̃: 2.38%
95% mean confidence interval for instructions value: -3.29 0.63
95% mean confidence interval for instructions %-change: -0.95% 0.02%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 338366118 -> 338365223 (<.01%)
cycles in affected programs: 257889 -> 256994 (-0.35%)
helped: 42
HURT: 15
helped stats (abs) min: 2 max: 120 x̄: 39.38 x̃: 34
helped stats (rel) min: 0.04% max: 2.55% x̄: 0.86% x̃: 0.76%
HURT stats (abs)   min: 6 max: 204 x̄: 50.60 x̃: 34
HURT stats (rel)   min: 0.11% max: 4.75% x̄: 1.12% x̃: 0.56%
95% mean confidence interval for cycles value: -30.39 -1.02
95% mean confidence interval for cycles %-change: -0.66% -0.02%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
Ian Romanick
d2b4f3f137 intel/vec4: Allow late copy propagation on vec4
This change incurs a small amount of hurt now, but it enables a lot of
benefit on vec4 shaders on the next commit.  nir_opt_algebraic_late
converts dph, dot3, etc. to dhp_replicated, dot_replicated3, etc.  In
the process, it introduces extra moves.  If the original NIR contained

        vec1 32 ssa_45 = fdot4 ssa_51, ssa_44
        vec1 32 ssa_46 = fneg ssa_45

nir_opt_algebraic_late will produce

        vec4 32 ssa_18 = fdot_replicated4 ssa_1, ssa_15
        vec1 32 ssa_19 = mov ssa_18.x
        vec1 32 ssa_17 = fneg ssa_19

The algebraic pass added in the next commit can't see through the move
to know that the fneg applies to a fdot_replicated4.

Haswell, Ivy Bridge, and Sandybridge had similar results. (Haswell shown)
total cycles in shared programs: 187077604 -> 187079858 (<.01%)
cycles in affected programs: 350132 -> 352386 (0.64%)
helped: 174
HURT: 194
helped stats (abs) min: 2 max: 124 x̄: 23.60 x̃: 16
helped stats (rel) min: 0.12% max: 15.88% x̄: 4.98% x̃: 3.86%
HURT stats (abs)   min: 2 max: 164 x̄: 32.78 x̃: 16
HURT stats (rel)   min: 0.17% max: 22.82% x̄: 6.46% x̃: 0.86%
95% mean confidence interval for cycles value: 2.04 10.21
95% mean confidence interval for cycles %-change: 0.17% 1.93%
Cycles are HURT.

No shader-db changes on any other Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1359>
2020-04-01 00:28:38 +00:00
Timothy Arceri
0f4a81430e nir: fix crash in varying packing on interface mismatch
For example when the outputs are scalars but the inputs are struct
members.

Fixes: 26aa460940 ("nir: rewrite varying component packing")

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4351>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4351>
2020-03-31 23:43:31 +00:00
Eric Anholt
31011c7a39 freedreno/turnip: Use the NIR info to decide if we need helper invocations.
We had an approximation that was assuming any ddx or tex instruction
needed helper invocations, but that's not true for texelFetch() or
textureSize().  It also meant that we were setting PIXLOD on vertex and
compute shaders doing texturing, which doesn't really make sense.

shader-db (with a hack to log pixlod):
total pixlod in shared programs: 582 -> 573 (-1.55%)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2681
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4308>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4308>
2020-03-31 22:29:22 +00:00
Eric Anholt
974b9c57c1 freedreno: Drop an unnecessary include marked "this should go away"
It came in with the initial import, and doesn't seem to be necessary any
more.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4289>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4289>
2020-03-31 21:20:11 +00:00
Rob Clark
127fa5d00c freedreno/ir3: fix android build
Fixes: e5339fe4a4 ("Move compiler.h and imports.h/c from src/mesa/main into src/util")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4381>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4381>
2020-03-31 18:46:04 +00:00
Rob Clark
ae7da1a017 util: move ALIGN/ROUND_DOWN_TO to u_math.h
These are less mesa specific than the rest of macros.h, and would be
nice to use outside of mesa.  Prep for next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4381>
2020-03-31 18:46:04 +00:00
Jason Ekstrand
7a53e67816 spirv: Implement OpCopyObject and OpCopyLogical as blind copies
Because the types etc. are required to logically match, we can just
copy-propagate the guts of the vtn_value.  This was causing issues with
some new CTS tests that are doing an OpCopyObject of a sampler which is
a special-cased type in spirv_to_nir.  Of course, this is only a partial
solution.  Ideally, we've got a bit of work to do to make all the
composite stuff able to handle all types including images, sampler, and
combined image/samplers but this gets some CTS tests passing.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4375>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4375>
2020-03-31 17:55:30 +00:00
Lionel Landwerlin
88c046a6d3 isl: don't warn in physical extent calculation for yuv formats
Those format have correct descriptions already with the exception of
the planar format. In that case we introduce an assert.

This fine because we don't use the planar format in any of our
drivers. There are restrictions on how the addresses of the 2 planes
are relative to one another which make this annoying. The sampler is
also more limited than what we can do with a shader snippet.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2999>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2999>
2020-03-31 15:59:21 +00:00
Lionel Landwerlin
015f08dd43 isl: set bpb for Y8_UNORM
This isn't a format we use in any of the drivers but for consistency
just give it a correct bpb.

We also set the luminance in the G channel. We can't actually use this
format with the 3D sampler (only media).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2999>
2020-03-31 15:59:21 +00:00
Eric Engestrom
5f4d9b419a scons: prune unused Makefile.sources
Fixes: 2e92d33819 ("scons: Prune out unnecessary targets.")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed by: Jose Fonseca <jfonseca@vmware.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4373>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4373>
2020-03-31 09:42:07 +00:00
Connor Abbott
d63acce5f4 tu: Return the correct alignment for images
The alignment field was never initialized, so we were just returning an
alignment of 0. Return the alignment from fdl, and while we're here
cleanup some leftovers in tu_private.h.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4357>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4357>
2020-03-31 08:22:58 +00:00
Connor Abbott
d84c206d85 freedreno/fdl: Add base_align
Tell users what the base address of the image needs to be aligned to.
These values are based on experimentation via passing an offset to
vkBindImageMemory with turnip and seeing if tests still pass. Note that
r8g8 is also special in this regard, however it actually has an
increased alignment (in bytes).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4357>
2020-03-31 08:22:58 +00:00
Jason Ekstrand
896a7c28eb anv/allocator: Use util_dynarray for blocks in anv_state_stream
When we originally wrote a bunch of the allocation data structures, we
re-used the GPU memory for CPU-side data structures.  It's a bit more
memory efficient and usually ok.  However, this has a couple of
problems:

 1. It makes it MUCH more likely that the GPU will accidentlly stomp
    CPU-side data structures and cause nearly impossible to debug
    crashes.

 2. With discrete GPUs, the memory will be mapped somehow and that map
    may be across the BAR so it could have horribly slow CPU access.
    This is bad for our CPU-side data structures.

In the case of anv_state_stream, it also made the data structure
massively more complex than it needed to be.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
2020-03-31 08:12:07 +00:00
Jason Ekstrand
63bec07e14 anv: Account for the header in anv_state_stream_alloc
If we have an allocation that's exactly the block size, we end up
computing a new block size to allocate that's exactly the block size,
add in the header, and then assert fail.  When computing the block size,
we need to account for the header.

Fixes: 955127db93 "anv/allocator: Add support for large stream..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
2020-03-31 08:12:07 +00:00
Marek Olšák
6e672074dd st/mesa: add environment variable pin_app_thread for faster glthread on AMD Zen
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4369>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4369>
2020-03-30 23:57:52 -04:00
Marek Olšák
4df3c7a207 gallium/u_threaded: call the driver to pin threads to L3 immediately
This is thread-safe and we want it to be done immediately for good L3 cache
usage.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4369>
2020-03-30 23:57:49 -04:00
Qiang Yu
4de35bed42 lima: also check tiled and depth case when import
We missed the tiled and depth case when check buffer alignment.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4362>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4362>
2020-03-31 01:40:29 +00:00
Qiang Yu
e46b2ef724 lima: fix buffer import with offset
With EGL_EXT_image_dma_buf_import, user can import dma_buf
with offset.

This is also used by AOSP GLConsumer::updateTexImage
with HAL_PIXEL_FORMAT_YV12 buffer which store YUV planes in
the same buffer with offset. Render sample from it using
GL_OES_EGL_image_external. This should fix some video
display problem when using MediaCodec soft decoding which
generates HAL_PIXEL_FORMAT_YV12 buffer and render it on
screen.

Test program:
https://github.com/yuq/gfx/tree/master/yuv2rgb/dma-buf

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4362>
2020-03-31 01:40:29 +00:00
Alyssa Rosenzweig
02ad147c5c pan/bi: Fix handling of constants with COMBINE
We should never see COMBINE constants explicitly since they'll become
moves anyway, so we can simplify that. On the other hand, we do need the
type information for the lowering to work properly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
bd19e76340 pan/bi: Handle fp16/abs scheduling restriction
See previous commit for the packing side. Here we update the scheduler
to accomodate this. Note we don't actually hit this path yet, but it's
good to be proactive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c88f816169 pan/bi: Handle abs packing for fp16/FMA add/min
It's seriously quirky, and all to save a single bit. Alas. It also
introduces an edge case for the scheduler which is a bit annoying.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
ba8e11f0f1 pan/bi: Handle core faddminmax16 packing
This works without the exception of absolute values, which have some...
odd properties to be handled in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
12a16f2247 pan/bi: Structify fadd/min/max16
There is some quirky encoding here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c12a208d78 pan/bi: Add v2f16 versions of rounding ops
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
f81b67b857 pan/bi: Handle round opcodes in frontend
These correspond to various ops routed through BI_ROUND

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c7170e9742 pan/bi: Assert out i16 related converts for now
Needs more investigation, and GLSL doesn't use it quite yet sadly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
2fd8b2e6d4 pan/bi: Add one-source f32->f16 op
This really has a second op for vectorization but we don't handle this
quite yet...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
197c6414ea pan/bi: Add bifrost_fma_2src generic
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
57a8e6e8d0 pan/bi: Handle standard FMA conversions
These are plain old 1-sources so they're easy to start with.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
499e97b519 pan/bi: Enumerate conversions
There are lots of Bifrost conversion opcodes that can all be emitted
from BI_CONVERT, let's pattern match.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
902f99a45d pan/bi: Expand out FMA conversion opcodes
There are a *lot* of them, with lots of symmetry we can exploit to
simplify the packing logic (but not entirely). Let's add the
corresponding header structs/defines, although we don't actually poke
the disassembler at this stage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
73715124ea pan/bi: Pack outmod and roundmode with FMA
The fields got missed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
158f2452f2 pan/bi: Add FMA16 packing
It's like the original FMA packing but with swizzles introduced.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
b5148b6b49 pan/bi: Fix missing type for fmul
We add a zero argument, we want it to align with the size of whatever
the other arguments were for optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
5eb209a05f pan/bi: Finish FMA structures
There were some missing fields for the 32-bit case, and the 16-bit case
has separate packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
375a7d0f32 pan/bi: Ignore swizzle in unwritten component
Otherwise we can trip the assert for no good reason.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
aa77d8128e pan/bi: Handle f2f* opcodes
Just more converts that got missed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
c2a8ef907b panfrost: Enable PIPE_SHADER_CAP_FP16 on Bifrost
We don't have fp16 implemented on Midgard yet but on Bifrost we can flip
it on now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
77e04eb2e2 pan/bi: Enable precision lowering in standalone compiler
..since there's no CAP to guide here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
683cd9b6f4 pan/bi: Fix off-by-one in scoreboarding packing
Clauses actually encode the *next* clauses' dependencies.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
f3726a0874 pan/bi: Fix overzealous write barriers
It's possible this triggers an INSTR_INVALID_ENC.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
3d7166fa69 pan/bit: Begin generating a vertex job
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
a0d1be30e1 pan/bit: Submit a WRITE_VALUE job as a sanity check
If this fails, everything else probably will too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
97029c773e panfrost: Stub out G31/G52 quirks
There are none so far, but we'll need quirks accessible for Bifrost
specific details in the future, and in the mean time we need to handle
the cases somehow to avoid the unreachable(..)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
bf1929e479 pan/bit: Open up the device
As a start and a sanity check.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
39378eec57 panfrost: Move device open/close to root panfrost
We need it for standalone testing too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
fd18695a26 pan/bit: Link standalone compiler with en/decoder
We would like to submit jobs from the standalone compiler for testing
purposes, so let's get things wired up.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
0f65f00a0d panfrost: Move pan_bo to root panfrost
Now that its Gallium dependencies have been resolved, we can move this
all out to root. The only nontrivial change here is keeping the
pandecode calls in Gallium-panfrost to avoid creating a circular
dependency between encoder/decoder. This could be solved with a third
drm folder but this seems less intrusive for now and Roman would
probably appreciate if I went longer than 8 hours without breaking the
Android build.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
3283c7f4da panfrost: Inline reference counting routines
We use only a very small subset of the capabilities of
pipe_reference (just wrappers for atomic ints..). Let's inline it and
drop the dependency on Gallium from pan_bo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
02a638cc51 panfrost: Isolate panfrost_bo_access_for_stage to pan_cmdstream.c
We don't use it outside this file (and really shouldn't) and it has a
strict Gallium dependency in pan_bo.h.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Alyssa Rosenzweig
ca8c62592c panfrost: Split panfrost_device from panfrost_screen
We would like to access properties of the device in a
Gallium-independent way (for out-of-Gallium testing in the short-term,
and would help a theoretical Vulkan implementation in the long run).
Let's split up the struct.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4382>
2020-03-31 01:12:26 +00:00
Icecream95
50e3b2e390 panfrost: Correctly identify format 0x4c
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
2020-03-31 00:48:58 +00:00
Icecream95
bd87bcb8ac panfrost: Add support for R3G3B2
Tested with texenv from mesa-demos.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
2020-03-31 00:48:58 +00:00
Icecream95
49a81a431e st/mesa: Fall back on R3G3B2 for R3_G3_B2
It's simpler for Panfrost to use R3G3B2 instead of B2G3R3, but
format_map only listed the BGR variation.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
2020-03-31 00:48:58 +00:00
Icecream95
81d059c898 panfrost: Add support for B5G5R5X1
Tested with texenv from mesa-demos.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
2020-03-31 00:48:58 +00:00
Icecream95
bad6fc4871 panfrost: Mark 64-bit formats as unsupported
There is no hardware support for these formats, but some games use
them for vertex data.

This fixes a crash in Aleph One.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4292>
2020-03-31 00:48:58 +00:00
Jason Ekstrand
9468f0729b nir: Handle vec8/16 in nir_shrink_array_vars
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
c26bf848ba nir: Handle vec8/16 in opt_undef_vecN
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
99540edfde nir: Treat vec8/16 as select in opt_peephole_select
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
e3554a293b nir: Handle vec8/16 in opt_split_alu_of_phi
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
2aab7999e4 nir: Handle vec8/16 in lower_regs_to_ssa
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
1033255952 nir: Handle vec8/16 in lower_phis_to_scalar
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
ac7a940eba nir: Handle vec8/16 in gather_ssa_types
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
a18c4ee7b0 nir: Handle vec8/16 in bool_to_bitsize
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
f5bbdf7621 nir: Copy propagate through vec8s and vec16s
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
842338e2f0 nir: Add a nir_op_is_vec helper
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
84ab61160a nir/algebraic: Add downcast-of-pack opts
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Jason Ekstrand
14a49f31d3 nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64
We have the code to do the lowering, we were just missing the
boilerplate bits to make should_lower_int64_alu_instr return true.

Fixes: 62d55f1281 "nir: Wire up int64 lowering functions"
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
2020-03-31 00:18:05 +00:00
Rob Clark
1b3aefad46 freedreno/log: avoid duplicate ts's
In cases where `fd_log()`/`fd_log_stream()` are called multiple times
back-to-back, just use the timestamp of the first trace.

This seems to avoid some occasional GPU hangs I was seeing with logging
enabled.  Although not exactly sure the reason for the hangs.  (Looks
like GPU hangs *after* all the cmdstream is processed, according to
crashdec.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:13 +00:00
Rob Clark
2bf7dba80b freedreno/a6xx: add some more tracepoints
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:13 +00:00
Rob Clark
31173a7e7a freedreno: add some initial fd_log tracepoints
Mostly convert over existing DBG traces.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:13 +00:00
Rob Clark
55839fd41c freedreno/a6xx: timestamp logging support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:13 +00:00
Rob Clark
a0ca1462f3 freedreno: add logging infrastructure
Provides a way to log msgs timestamped at the corresponding position in
the GPU cmdstream, mostly for the purposes of profiling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:12 +00:00
Rob Clark
ffd3226678 util: fix u_fifo_pop()
Seems like no one ever depended on it to actually return false when fifo
is empty.

Fixes: 6e61d06209 ("util: Add super simple fifo")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:12 +00:00
Rob Clark
356b93f102 freedreno: remove some obsolete debug options
'fraghalf' is unused (superceeded by actually lowering output based on
the precision information in nir).  And glsl140 support in ir3 is long
past the experimental stage, so the glsl120 option is no longer needed.
So remove them and free up some bits for new things.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
2020-03-30 23:20:12 +00:00
Jason Ekstrand
b113170559 nir/opt_loop_unroll: Fix has_nested_loop handling
In 87839680c0, a very subtle mistake was made with the CFG walking
recursion.  Instead of setting the local has_nested_loop variable when
process child loops, has_nested_loop_out was passed directly into the
process_loop_in_block call.  This broke nested loop detection heuristics
and caused loop unrolling to run massively out of control.  In
particular, it makes the following CTS test compile virtually forever:

dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.struct_mixed_types.uniform_buffer_block_geom

Fixes: 87839680c0 "nir: Fix breakage of foreach_list_typed_safe..."
Closes: #2710
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4380>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4380>
2020-03-30 22:20:47 +00:00
Eric Anholt
92afe94d28 freedreno: Work around UBWC flakiness.
In trying to track down the new failure in #2670, I found that I could get
the flaky test set down to 4 tests, and dropping any remaining test
wouldn't trigger the failure (a bad 8x4 block in the middle of
dEQP-GLES3.functional.fbo.msaa.4_samples.r16f's render target).  Disabling
gmem or bypass didn't help, and adding lots of CCU flushing didn't help.
What did help was disabling blitting, or this memset to initialize the
UBWC area after we (presumably) pull a BO out of the BO cache.  My guess
is that the 2D blitter can't handle some rare set of state in the flags
buffer and emits some garbage.

I've run 8 gles3 and 7 gles31 runs with this branch now so hopefully I've got the4 right set of flakes marked for removal.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2670
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4290>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4290>
2020-03-30 21:48:59 +00:00
Eric Anholt
d0b3ccb060 freedreno: Fix detection of being in a blit for acc queries.
The batch might not have stage == FD_STAGE_BLIT set because
fd_blitter_pipe_begin was sticking the stage on some random batch (or none
at all) rather than the one that would be used in the meta operation.

What we actually wanted to be looking at was set_active_query_state(),
which is already called by util_blitter and whose state we just needed to
track.

Fixes piglit occlusion_query_meta_no_fragments.  I haven't changed
query_hw.c's stage handling to clean the rest up because I don't have a
db410c/db820c at home to iterate over the piglit tests.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
57d54bcf99 freedreno: Rename "is_blit" to "is_discard_blit"
It's about the special case of an overwrite of a level meaning we can
discard old batch contents.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
8cdc6c1e4b freedreno/a6xx: Fix timestamp queries.
We were returning the same kind of result as time_elapsed (an end - start
time in ns), which on a timestamp query is approximately zero since
begin/end are at the same point in time.  What we're supposed to return is
a converted-to-ns timestamp based on the GPU clock.  Remove the _pause()
function for time_elapsed to reduce the command stream overhead, and just
capture start (which is, unfortunately, going to happen on each tile and
thus the final start value we ready will be the last tile of the frame,
not the first).

Fixes piglit spec/arb_timer_query/query gl_timestamp

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
7ef61c1f10 freedreno: Count blits in GL_TIME_ELAPSED and perf counter queries.
Fixes 0 gpu time reported for glBlitFramebuffer in apitrace replay --pgpu.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
4a07839948 freedreno: Associate the acc query bo with the batch.
Otherwise, a result query with wait won't trigger flushing the batch, and
we can end up with zeroed results.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
36612c96bd freedreno: Fix acc query handling in the presence of batch reordering.
When we switch batches and start a new draw, we need to cap the queries in
the previous batch and start queries again in the new one.

FD_STAGE_NULL got renamed to 0 so that it would naturally return
!is_active and end the queries at the end of the batch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
a99ff93374 freedreno: Remove the "active" member of queries.
The state tracker only gets to begin/query/destroy when !active and end
when active, so we have no need to try to track this ourselves.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Eric Anholt
b7fe793869 freedreno: Remove always-true return from per-gen begin_query.
You should do failure-prone allocation in create_query, not begin, anyway.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
2020-03-30 21:35:21 +00:00
Rhys Perry
1ef9658906 util/u_queue: fix race in total_jobs_size access
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
CC: <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
2020-03-30 20:17:43 +00:00
Rhys Perry
d101ca3f5a glsl: fix race in instance getters
Insertions can modify entry->data. Seems to fix random Fossilize crashes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
CC: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
2020-03-30 20:17:43 +00:00
Jason Ekstrand
f5b14d983e nir: Set UBO alignments in lower_uniforms_to_ubo
Fixes: fb64954d9d "nir: Validate that memory load/store ops work on..."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4378>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4378>
2020-03-30 19:18:17 +00:00
Rhys Perry
4a909068ad aco: look at p_{extract,split}_vector's definitions in pred_by_exec_mask()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4333>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4333>
2020-03-30 17:34:46 +00:00
Daniel Stone
9197fd59da CI: Re-enable Windows VS2019 builds
The failures are fixed, but I didn't notice this had been silently
disabled in !4272.

Re-enable the VS2019 build.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4374>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4374>
2020-03-30 16:22:20 +00:00
Jason Ekstrand
fb64954d9d nir: Validate that memory load/store ops work on whole bytes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
4e80151c5d anv: Set alignments on descriptor and constant loads
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
c217ee8d35 nir: Insert b2b1s around booleans in nir_lower_to
By inserting a b2b1 around the load_ubo, load_input, etc. intrinsics
generated by nir_lower_io, we can ensure that the intrinsic has the
correct destination bit size.  Not having the right size can mess up
passes which try to optimize access.  In particular, it was causing
brw_nir_analyze_ubo_ranges to ignore load_ubo of booleans which meant
that booleans uniforms weren't getting pushed as push constants.  I
don't think this is an actual functional bug anywhere hence no CC to
stable but it may improve perf somewhere.

Shader-db results on ICL with iris:

    total instructions in shared programs: 16076707 -> 16075246 (<.01%)
    instructions in affected programs: 129034 -> 127573 (-1.13%)
    helped: 487
    HURT: 0
    helped stats (abs) min: 3 max: 3 x̄: 3.00 x̃: 3
    helped stats (rel) min: 0.45% max: 3.00% x̄: 1.33% x̃: 1.36%
    95% mean confidence interval for instructions value: -3.00 -3.00
    95% mean confidence interval for instructions %-change: -1.37% -1.29%
    Instructions are helped.

    total cycles in shared programs: 338015639 -> 337983311 (<.01%)
    cycles in affected programs: 971986 -> 939658 (-3.33%)
    helped: 362
    HURT: 110
    helped stats (abs) min: 1 max: 1664 x̄: 97.37 x̃: 43
    helped stats (rel) min: 0.03% max: 36.22% x̄: 5.58% x̃: 2.60%
    HURT stats (abs)   min: 1 max: 554 x̄: 26.55 x̃: 18
    HURT stats (rel)   min: 0.03% max: 10.99% x̄: 1.04% x̃: 0.96%
    95% mean confidence interval for cycles value: -79.97 -57.01
    95% mean confidence interval for cycles %-change: -4.60% -3.47%
    Cycles are helped.

    total sends in shared programs: 815037 -> 814550 (-0.06%)
    sends in affected programs: 5701 -> 5214 (-8.54%)
    helped: 487
    HURT: 0

    LOST:   2
    GAINED: 0

The two lost programs were SIMD16 shaders in CS:GO.  However, CS:GO was
also one of the most helped programs where it shaves sends off of 134
programs.  This seems to reduce GPU core clocks by about 4% on the first
1000 frames of the PTS benchmark.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
d2dfcee7f7 nir: Use b2b opcodes for shared and constant memory
No shader-db changes on ICL with iris

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
16a80ff18a aco: Implement b2b32 and b2b1
The implementations here just clone i2b32 and i2b1.  This means that
b2b32 doesn't technically generate true NIR 0/-1 booleans but it should
be fine as it's only ever generated for shared variable writes which
will always be consumed by something which will then run it through an
i2b again.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
b2db84153a nir: Add b2b opcodes
These exist to convert between different types of boolean values.  In
particular, we want to use these for uniform and shared memory
operations where we need to convert to a reasonably sized boolean but we
don't care what its format is so we don't want to make the back-end
insert an actual i2b/b2i.  In the case of uniforms, Mesa can tweak the
format of the uniform boolean to whatever the driver wants.  In the case
of shared, every value in a shared variable comes from the shader so
it's already in the right boolean format.

The new boolean conversion opcodes get replaced with mov in
lower_bool_to_int/float32 so the back-end will hopefully never see them.
However, while we're in the middle of optimizing our NIR, they let us
have sensible load_uniform/ubo intrinsics and also have the bit size
conversion.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Jason Ekstrand
2cb9cc56d5 intel/nir: Run copy-prop and DCE after lower_bool_to_int32
No shader-db impact on ICL with iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4338>
2020-03-30 15:46:19 +00:00
Christian Gmeiner
5278e9dea7 etnaviv: compiled_framebuffer_state: get rid of SE_SCISSOR_*
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Christian Gmeiner
22ee3eabca etnaviv: s/scissor_s/scissor
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Christian Gmeiner
43b4eb394c etnaviv: get rid of struct compiled_scissor_state
We can reuse pipe_scissor_state.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Christian Gmeiner
9491c1b04d etnaviv: do the left shift by 16 at emit time
Also round up the max bounds.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Christian Gmeiner
5ba2d398d8 etnaviv: rework clippling calculation to be a derived state
This moves the whole clipping calculation out of the emit function.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Christian Gmeiner
95763e20ce etnaviv: get rid of SE_CLIP_*
The only difference between e.g. SE_SCISSOR_RIGHT and SE_CLIP_RIGHT
is the used margin value. With that information we can remove
SE_CLIP_* and apply the different margins during emit time.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4278>
2020-03-30 15:30:15 +00:00
Jose Fonseca
27d58a1c20 gitlab-ci: Prune all SCons jobs except scons-win64, and allows failures.
Based on the discussion in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4352

Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4363>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4363>
2020-03-30 14:52:34 +00:00
Samuel Pitoiset
3935a729d9 nir/algebraic: add fexp2(fmul(flog2(a), 0.5) -> fsqrt(a) optimization
Helps some Wolfenstein II and Wolfenstein Youngblood shaders.

pipeline-db (VEGA10/ACO):
Totals from affected shaders:
SGPRS: 17904 -> 17904 (0.00 %)
VGPRS: 14492 -> 14492 (0.00 %)
Spilled SGPRs: 20 -> 20 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 1753152 -> 1749708 (-0.20 %) bytes
Max Waves: 2581 -> 2581 (0.00 %)

pipeline-db (VEGA10/LLVM):
Totals from affected shaders:
SGPRS: 26656 -> 26656 (0.00 %)
VGPRS: 23780 -> 23780 (0.00 %)
Spilled SGPRs: 2112 -> 2112 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 2552712 -> 2549236 (-0.14 %) bytes
Max Waves: 3359 -> 3359 (0.00 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4353>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4353>
2020-03-30 14:07:43 +00:00
Jose Fonseca
2e92d33819 scons: Prune out unnecessary targets.
This prunes out all targets except libgl-gdi, libgl-xlib, and svga, as
suggested by Marek Olšák.

libgl-xlib will be remove once I have had time to confirm no automated
tests we have rely upon it.

There are also a bunch of Makefile.sources which become orphaned as
result, that are not taken care of in this change.

v2: Prune remainders of swr support.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4348>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4348>
2020-03-30 13:38:01 +00:00
Timur Kristóf
0f847b18bc aco: Don't store LS VS outputs to LDS when TCS doesn't need them.
Totals:
Code Size: 254764624 -> 254745104 (-0.01 %) bytes

Totals from affected shaders:
VGPRS: 12132 -> 12112 (-0.16 %)
Code Size: 573364 -> 553844 (-3.40 %) bytes

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
798dd98d6e aco: When LS and HS invocations are the same, pass LS outputs in temps.
We know that in this case, the LS and HS invocations are working
on the exact same vertex, so it's safe to skip the LDS.

Totals:
VGPRS: 3960744 -> 3961844 (0.03 %)
Code Size: 254824300 -> 254764624 (-0.02 %) bytes
Max Waves: 1053748 -> 1053574 (-0.02 %)

Totals from affected shaders:
VGPRS: 26152 -> 27252 (4.21 %)
Code Size: 1496600 -> 1436924 (-3.99 %) bytes
Max Waves: 4860 -> 4686 (-3.58 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
0a91c086b8 aco: Extract store_output_to_temps into a separate function.
Will be used by LS output stores.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
0f35b3795d aco: Fix workgroup size calculation.
Clear the workgroup size for all supported shader stages.
Also, unify the workgroup size calculation accross various places.

As a result, insert_waitcnt can use the proper workgroup size
which means that some waits can be dropped from tessellation
shaders. Also, in cases where the previous calculation was wrong,
we now insert s_barrier instructions.

Totals from affected shaders (GFX10):
Code Size: 340116 -> 338484 (-0.48 %) bytes

Fixes: a8d15ab6da
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
99ad62ff27 aco: Extract setup_tcs_info to a separate function.
Will be required by the workgroup size calculation.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
0ad65f2c55 aco: Zero-fill undefined elements in create_vec_from_array.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
50634ad4a0 aco: Change isel inputs/outputs to a flat array.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
e4a1b246a4 aco: Treat outputs of the previous stage as inputs of the next stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
f1dd81ae10 nir: Collect if shader uses cross-invocation or indirect I/O.
The following new fields are added to tess shader info:

* `tcs_cross_invocation_inputs_read`
* `tcs_cross_invocation_outputs_read`

These are I/O masks that are a subset of inputs_read and outputs_read
and they contain which per-vertex inputs and outputs are read
cross-invocation.

Additionall, the following new fields are added to shader_info:

* `inputs_read_indirectly`
* `outputs_accessed_indirectly`
* `patch_inputs_read_indirectly`
* `patch_outputs_accessed_indirectly`

These new fields can be used for optimizing TCS in a back-end compiler.
If you can be sure that the TCS doesn't use cross-invocation inputs
or outputs, you can choose a different strategy for storing VS and TCS
outputs. However, such optimizations might need to be disabled when
the inputs/outputs are accessed indirectly due to backend limitations,
so this information is also collected.

Example: RADV currently has to store all VS and TCS outputs in LDS, but
for shaders when only inputs and/or outputs belonging to the current
invocation ID are used, it could skip storing these in LDS entirely.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
e7d733fdab aco: Use more optimal sequence at the beginning of merged shaders.
It can be further optimized in the future, but
the new sequence already has a few advantages:

* Uses fewer instructions
* Uses even fewer instructions in wave32 mode
* Doesn't use the VALU at all

Totals from affected shaders (GFX10):
VGPRS: 43504 -> 43496 (-0.02 %)
Code Size: 2436000 -> 2423688 (-0.51 %) bytes
Max Waves: 8704 -> 8705 (0.01 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
17c779ab9e aco: Skip 2nd read of merged wave info when TCS in/out vertices are equal.
When TCS has an equal number of input and output, it means that the
number of VS and TCS invocations (LS and HS) are the same; and that
the HS invocations operate on the same vertices as the LS.

When this is the case, this commit removes the else-if between
the merged VS and TCS halves, making it possible to schedule
and optimize the code accross the two halves.

Totals:
SGPRS: 5577367 -> 5581735 (0.08 %)
VGPRS: 3958592 -> 3960752 (0.05 %)
Code Size: 254867144 -> 254838244 (-0.01 %) bytes
Max Waves: 1053887 -> 1053747 (-0.01 %)

Totals from affected shaders:
SGPRS: 29032 -> 33400 (15.05 %)
VGPRS: 35664 -> 37824 (6.06 %)
Code Size: 1979028 -> 1950128 (-1.46 %) bytes
Max Waves: 7310 -> 7170 (-1.92 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
4ec48440a0 aco: Allow combining LDS loads when loading tess factors.
Previously the tess factors were loaded individually, but now they can
be loaded using a single LDS load instruction.

Note that the inner and outer tess factors are not yet combined.

Totals (GFX10):
Code Size: 254896008 -> 254879212 (-0.01 %) bytes

Totals from affected shaders (GFX10):
Code Size: 2028352 -> 2011556 (-0.83 %) bytes

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
ace3833293 aco: Allow combining TCS output VMEM stores.
Some copypasta may have stuck in the code.
This was left on false by mistake.

Totals (GFX10):
Code Size: 254939248 -> 254896008 (-0.02 %) bytes

Totals from affected shaders (GFX10):
VGPRS: 16196 -> 16212 (0.10 %)
Code Size: 1126332 -> 1083092 (-3.84 %) bytes
Max Waves: 2336 -> 2334 (-0.09 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
e2b1d749b1 aco: Fix handling of tess factors.
There is no need to check whether they are written using indirect
indices, because all tess factors should be written to VMEM only
at the end of the shader.

No pipeline db changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
d3f6adcaed aco: Extract tcs_driver_location_matches_api_mask to separate function.
Also clear up should_write_tcs_output_to_lds a little bit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Timur Kristóf
e0dff5fd86 aco: Create null exports in instruction selection instead of assembler.
This allows the passes after isel to assume that the exports are
always correct, and also allows to schedule these null exports later.
Additionally, it ensures that the correct exec mask is used for
these exports.

Totals from affected shaders (GFX10):
SGPRS: 84224 -> 84344 (0.14 %)
VGPRS: 23088 -> 23076 (-0.05 %)
Code Size: 882892 -> 894368 (1.30 %) bytes

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
2020-03-30 13:09:08 +00:00
Danylo Piliaiev
87839680c0 nir: Fix breakage of foreach_list_typed_safe assumptions in loop unrolling
foreach_list_typed_safe works with assumption that even if current node
becomes invalid, the next will be still valid.

However process_loops broke this assumption, because during iteration
when immediate child is unrolled - not only current node could be removed
but also the one after it.

This doesn't cause issues now but it will cause issues when undefined
behaviour in foreach* macros is fixed.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4189>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4189>
2020-03-30 14:41:30 +03:00
Pierre-Eric Pelloux-Prayer
716a065ac0 radeon: switch to 3-spaces style
For clang-format config see the previous commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
2020-03-30 11:05:52 +00:00
Pierre-Eric Pelloux-Prayer
d7008fe46a radeonsi: switch to 3-spaces style
Generated automatically using clang-format and the following config:

AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlwaysBreakAfterReturnType: None
BasedOnStyle: LLVM
BraceWrapping:
  AfterControlStatement: false
  AfterEnum: true
  AfterFunction: true
  AfterStruct: false
  BeforeElse: false
  SplitEmptyFunction: true
BinPackArguments: true
BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
ForEachMacros:
  - LIST_FOR_EACH_ENTRY
  - LIST_FOR_EACH_ENTRY_SAFE
  - util_dynarray_foreach
  - nir_foreach_variable
  - nir_foreach_variable_safe
  - nir_foreach_register
  - nir_foreach_register_safe
  - nir_foreach_use
  - nir_foreach_use_safe
  - nir_foreach_if_use
  - nir_foreach_if_use_safe
  - nir_foreach_def
  - nir_foreach_def_safe
  - nir_foreach_phi_src
  - nir_foreach_phi_src_safe
  - nir_foreach_parallel_copy_entry
  - nir_foreach_instr
  - nir_foreach_instr_reverse
  - nir_foreach_instr_safe
  - nir_foreach_instr_reverse_safe
  - nir_foreach_function
  - nir_foreach_block
  - nir_foreach_block_safe
  - nir_foreach_block_reverse
  - nir_foreach_block_reverse_safe
  - nir_foreach_block_in_cf_node
IncludeBlocks: Regroup
IncludeCategories:
  - Regex:           '<[[:alnum:].]+>'
    Priority:        2
  - Regex:           '.*'
    Priority:        1
IndentWidth: 3
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
2020-03-30 11:05:52 +00:00
Pierre-Eric Pelloux-Prayer
53e5e802f8 radeon: fix includes
And add required forward declarations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
2020-03-30 11:05:52 +00:00
Pierre-Eric Pelloux-Prayer
7f52bbb7c0 ddebug: add missing forward declaration
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
2020-03-30 11:05:52 +00:00
Daniel Stone
04885d61dd meson: Add VS 4624 warning exclusion to remove piles of LLVM warnings
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
2020-03-30 10:13:40 +00:00
Erik Faye-Lund
5127160fb6 meson: disable some more warnings on msvc
These warnings triggers for me, and they are harmless as-is. Let's
disable them to avoid hiding actually scary warnings.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
2020-03-30 10:13:40 +00:00
Daniel Stone
2db1d73e53 CI: Avoid htz4 runner for VS2019
The htz4 runner needs to be updated in order for our support binaries
like Chocolatey to work. Temporarily restrict jobs to the EC2 runner
until this has happened.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371>
2020-03-30 10:19:35 +01:00
Eric Engestrom
8970b7839a intel: drop unused include directories
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
2020-03-28 21:36:54 +01:00
Eric Engestrom
231273d588 vulkan: drop unused include directories
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
2020-03-28 21:36:54 +01:00
Eric Engestrom
79af30768d meson: inline inc_common
Let's make it clear what includes are being added everywhere, so that
they can be cleaned up.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
2020-03-28 21:36:54 +01:00
Eric Engestrom
5a32dda8e6 meson: use existing variables in inc_common
Stepping stone to make review of the next commits easier.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
2020-03-28 21:36:54 +01:00
Vinson Lee
7df7520305 mesa: Change _mesa_exec_malloc argument type.
Fix build error.

In file included from ../src/mesa/x86/rtasm/x86sse.c:7:0:
../src/mesa/main/execmem.h:31:19: error: unknown type name ‘GLuint’; did you mean ‘uint’?
 _mesa_exec_malloc(GLuint size);
                   ^~~~~~
                   uint

Suggested-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5339fe4a4 ("Move compiler.h and imports.h/c from src/mesa/main into src/util")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361>
2020-03-28 13:14:42 -07:00
Michel Dänzer
fcd3377cfe gitlab-ci: Update to current templates
The .fdo.container-ifnot-exists template has been replaced by
.fdo.container-build.

We need to include "debian/" in FDO_REPO_SUFFIX for now, we can drop it
for individual images when their tags are bumped if we want.

Miscellaneous other goodies this gets us:
* The templates now add some labels to images which may be useful for
  garbage collecting unused tags in the future.
* The templates now copy the current tag from the main project
  registry to the forked project's if it already exists in the latter
  but points to a different image hash. This will avoid false failures
  (or passes) due to using the wrong image.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286>
2020-03-28 16:12:38 +00:00
Tomeu Vizoso
447890ad64 Revert "gitlab-ci: Disable jobs for Collabora's LAVA lab"
Lab is online again.

This reverts commit 1351ee0335.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347>
2020-03-28 09:45:03 +00:00
Marek Olšák
e609737526 radeonsi/gfx10: fix descriptors and compute registers for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
4ef1c8d60b radeonsi/gfx10: fix the wave size for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
b4a0087a1c radeonsi/gfx10: user correct ACQUIRE_MEM packet for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
acc5bdf887 radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
ee4d797d8b radeonsi/gfx10: don't use NGG culling if compute-based culling is used
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
65e9239977 radeonsi: add num_vbos_in_user_sgprs into the shader cache key
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
be9455bdf7 radeonsi: always create wait_mem_scratch for compute-based culling
used by the primitive restart emulation

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
42ce52b904 radeonsi: set amdgpu-gds-size for mode == 2 of compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
3381f2fa06 radeonsi: fix incorrect ordered_wave_id initilization for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Marek Olšák
d89b19cfe1 radeonsi: remove obsolete TODO comment related to compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
2020-03-28 00:58:34 +00:00
Vasily Khoruzhick
5d45ffbfb6 lima: Implement lima_texture_subdata
We can avoid intermediate copy if we implement it ourselves.
Improves x11perf -shmput500 from 199.0/s to 283.0/s

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281>
2020-03-28 00:17:40 +00:00
Rob Clark
6a10397a01 gitlab-ci: disable vs2019 build
Seems to be broken atm and blocking merging anything.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 16:34:27 -07:00
Rob Clark
f7d53275fb freedreno/ir3/ra: re-work a6xx merged register file conflicts
In particular setup the full/half conflicts first.  This avoids spurious
conflicts that where causing RA to place vecN half-regs poorly.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
faf276b4c8 freedreno/ir3/ra: split building regs/classes and conflicts
Split out the construction of registers and classes (which is the same
on all gens) from setting up conflicts.  Prep to re-work how we setup
conflicts on a6xx+ which merged half/full register file.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
90f7d12236 freedreno/ir3/ra: pick higher numbered scalars in first pass
Since we are re-assigning the scalars anyways in the second pass, assign
them to the highest free reg in the first pass (rather than lowest) to
allow packing vecN regs as low as possible.

Note this required some changes specifically for tex instructions with a
single component writemask that is not necessarily .x, as previously
these would get assigned in the first RA pass, and since they are still
scalar, we'd end up w/ some r47.* and other similarly way-to-high
assignments after the 2nd pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
1da90ca9bf freedreno/ir3/ra: compute register target from liveranges
Using the output of the first pass isn't ideal, as it can bake in the
losses from fragmentation which the scalar pass is intended to fill in.
This gets worse when we start using "vectorish" instructions, due to
higher use of vecN values.

Instead, we can just use the outputs of the liveness analysis to get a
more accurate # of maximum live values at any point.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
d2cc92c747 freedreno/ir3/ra: fix array liveranges
Fixes: 1b658533e1 ("freedreno/ir3: extend liverange of arrays")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
6347c2ea89 freedreno/ir3/ra: add def/use iterators
Decouple the messy logic of figuring out vreg names defined/used by an
instruction from the logic of what to do about it by introducing
iterators.  There is still *some* array vs ssa special casing in
ra_block_compute_live_ranges(), but less than before.  And this will
avoid introducing a second copy of the def/use logic in a following
patch which uses the liveranges to calculate the maximum # of live
values (which is the optimal target for max physical register window
to round-robin within).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
bf0aa7ed90 freedreno/ir3/ra: drop extending output live-ranges
This is no longer needed as we create meta:collect instructions in the
end block, which achieves the same result.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
0e7d24b532 freedreno/ir3/ra: add helper to map name to array
For vreg names that refer to arrays rather than SSA values, this is the
counterpart to name_to_instr().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
d99d358389 freedreno/ir3/ra: fix target register calculation
Account for the # of regs an instruction writes, and fix an off-by-one.

(We are about to replace this with calculating the register target using
the live-ranges, but in debugging that it was useful to assert() if it
chose a higher target.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
d20a06e401 freedreno/ir3/ra: add helper to map name to instruction
Extract out a helper from the select_reg callback.  And include all the
instructions in the hashtable, not just SFU.  This will be useful in the
following commits.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
29992a039e freedreno/ir3/ra: split-up
Split out regset and shared header, since the RA pass is already getting
large-ish.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
6da53911c1 freedreno/ir3/ra: add debug option for RA debug msgs
Similar to the debug switch for sched debug msgs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
142f2d4551 freedreno/ir3: convert debug bitfield to BITFIELD_BIT()
(Little more verbose than the kernel's BIT())

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
3d0905582a freedreno/ir3: reformat disasm output
In particular, make sure we see all the shader-db stats.  The format
(order) is the sameish, except split across multiple lines to make it
easier to read.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
afdb8e3907 freedreno/ir3: fix bogus register footprint with tess/gs
When we have a tess or gs stage, VS outputs aren't normal varyings, so
regid is r63.x.. we shouldn't extend our registerfootprint to 64!

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
1b4b455739 freedreno/ir3: remove unused helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
c6a8792753 freedreno/ir3: add bary_ij as src for meta:tex_prefetch
This way RA doesn't have to special case it in use/def accounting..

This gets rid of an extra level of split/collect, which shouldn't be
needed.  And interferes with scheduler trying to put tex-prefetches
after inputs but before other instructions.  (Otherwise it would have
to figure out which split/collects need to go before the tex-prefetch)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
a0de0db0e4 freedreno/ir3: small cleanup and comments
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Rob Clark
7d9a794f35 freedreno/a6xx: register update
No functional change, and this register isn't used in userspace.  Just
syncing from envytools tree to eliminate the delta.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
2020-03-27 22:41:36 +00:00
Daniel Stone
46a32f0b6b CI: Disable Panfrost Mali-T820 jobs
The BayLibre T820 runners appear to be unhealthy.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359>
2020-03-27 21:32:01 +00:00
Marek Olšák
871bd2819d util: remove duplicated MALLOC_STRUCT and CALLOC_STRUCT
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:10 +00:00
Marek Olšák
7164674500 util: don't include p_defines.h and u_pointer.h from gallium
It's a mess, but this is what I arrived at.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:10 +00:00
Marek Olšák
013b65635f radv: stop including files from mesa/main
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:10 +00:00
Marek Olšák
76f79db3f5 util: stop including files from mesa/main
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:09 +00:00
Marek Olšák
c42fa40a51 mesa: don't use <> for including internal headers
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:09 +00:00
Marek Olšák
e5339fe4a4 Move compiler.h and imports.h/c from src/mesa/main into src/util
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
2020-03-27 21:00:09 +00:00
Jesse Natalie
6cfe074b86 wgl: use gldrv.h instead of stw_icd.h
Now that we have the official header, let's use that instead of
stw_icd.h.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
2020-03-27 19:50:24 +00:00
Jesse Natalie
ec20169264 wgl: add official gldrv.h header-file
This is the official, Microsoft-provided gldrv.h that describes the
driver-interface for OpenGL drivers on Windows.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
2020-03-27 19:50:24 +00:00
Karol Herbst
c9091f1f24 nv50, nvc0: fix must_check warning of util_dynarray_resize_bytes
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
2020-03-27 18:20:20 +00:00
Erik Faye-Lund
f4a4d4607e nv50: remove unused variable
This isn't used anymore, so let's get rid of it to silence a warning.

Fixes: c574cda3c6 ("util: Make helper functions for pack/unpacking pixel rows.")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
2020-03-27 18:20:20 +00:00
Lionel Landwerlin
aad0e6f810 intel/perf: store the probed i915-perf version
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
2020-03-27 14:14:49 +00:00
Lionel Landwerlin
8e7202d45f intel/perf: document meaning of query field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
2020-03-27 14:14:49 +00:00
Lionel Landwerlin
dde96d31b7 intel/perf: move mdapi query definitions to their own file
Where they belong.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
2020-03-27 14:14:49 +00:00
Lionel Landwerlin
33b9c7a7f6 intel/perf: break GL query stuff away
This stuff is somewhat specific to the GL extension & drivers. On
Vulkan we won't use this, it also made a rather large file.

v2: Fix Android build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
2020-03-27 14:14:49 +00:00
Lionel Landwerlin
f5c5574f42 intel/perf: move register definition to special file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
2020-03-27 14:14:49 +00:00
Andres Gomez
b9d2b5dcec gitlab-ci/traces: Add D3D11 sample entry for POLARIS10
v2:
  - Updated traces-db commit.
  - Changed the reference DXVK trace.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Andres Gomez
07e5b3ad50 gitlab-ci: add Wine and DXVK env variables to Vulkan's tracie runner
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Andres Gomez
6bae042b3d gitlab-ci: replay apitrace traces in headless mode
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Andres Gomez
9f4acd465e gitlab-ci: add apitrace's DXGI traces support
v2:
  - Pass the whole retrace command for apitrace traces (Alexandros).

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Andres Gomez
fb8fa83a30 gitlab-ci: add Wine, win64's apitrace and DXVK to the Vulkan testing container
In preparation for having automated testing with DXGI traces.

v2:
  - Updated DXVK version.
  - Merged the new Wine container into the existing Vulkan
    one (Michel).

v3:
  - Updated commit log.
  - Use a particular known-good apitrace version (Alexandros).

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Andres Gomez
05a3b49308 gitlab-ci: Don't use buster-backports packages by default for x86_test-vk
The backports repository can be temporarily inconsistent between
architectures, which can break the docker image build.

Suggested-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
2020-03-27 13:48:17 +00:00
Daniel Stone
4a8876b025 CI: Windows: Fix Docker tag argument inversion
docker tag takes its arguments as source and dest, not dest and source.
Went unnoticed as the host already had a tag for my image when I was
testing.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4346>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4346>
2020-03-27 13:23:33 +00:00
Daniel Stone
07885cbcdb CI: Add native Windows VS2019 build
Adds a native build of Mesa using Meson with the Visual Studio 2019
toolchain on a Windows host.

Though Docker is supported on Windows, Docker-in-Docker is not possible,
nor are podman and skopeo available. We handle this by creating the
container from a shell-executor Windows machine, which gives us a native
PowerShell that we can execute Docker from. This attempts to do the same
copy-from-upstream-or-create-if-not-exists optimisation as the
ci-templates do for our Linux builds, albeit open-coded in PowerShell.

The Mesa build itself is executed inside a container, using Meson and
Ninja.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Brian Paul <brianp@vmware.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
2020-03-27 10:32:47 +00:00
Daniel Stone
bc98de4d14 util/test: Use MAX_PATH on Windows
Windows provides MAX_PATH rather than PATH_MAX for the maximum allowable
path length. This is not a limit on the length of filename which can
exist on the filesystem, but a length on the length of path which can be
passed to Win32 API calls.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
2020-03-27 10:32:47 +00:00
Pierre-Eric Pelloux-Prayer
8f573bdaaa util: fix process_test path
Make sure we only use winepath when needed.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2690
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
2020-03-27 10:32:31 +00:00
Tomeu Vizoso
1351ee0335 gitlab-ci: Disable jobs for Collabora's LAVA lab
The lab is going down for a few hours to upgrade the LAVA installation
to the latest stable release.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4342>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4342>
2020-03-27 09:25:20 +01:00
Timothy Arceri
b5e00f5c2b nir: fix packing of TCS varyings not read by the TES
Unlike other stages TCS outputs not read by the TES cannot always
be demoted to globals e.g. when they are read by other TCS
invocations.

We were not taking these outputs into account when packing which
could result in other outputs being assigned to the same location.

Here we make sure to gather information on these outputs and group
them together when packing.

This fixes rendering issues in QUBE 2 via Proton.

Closes: #2653
Fixes: 26aa460940 ("nir: rewrite varying component packing")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
2020-03-27 07:26:39 +00:00
Timothy Arceri
8b9ebbcb54 glsl: fix varying packing for 64bit integers
Without this we can incorrectly end up marking things as making
use of ARB_enhanced_layouts style packing.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
2020-03-27 07:26:39 +00:00
Samuel Pitoiset
ba2ec1f369 ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv()
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

No pipeline-db changes with VEGA10/LLVM 9.

pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 6672 -> 6672 (0.00 %)
VGPRS: 6652 -> 6652 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 561780 -> 561692 (-0.02 %) bytes
Max Waves: 1043 -> 1043 (0.00 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 84608 -> 83768 (-0.99 %)
VGPRS: 106768 -> 106636 (-0.12 %)
Spilled SGPRs: 1625 -> 1713 (5.42 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 10850936 -> 10726712 (-1.14 %) bytes
Max Waves: 3152 -> 3180 (0.89 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
2020-03-27 08:05:43 +01:00
Samuel Pitoiset
d548384fc6 ac/nir: use llvm.amdgcn.rsq for nir_op_frsq
Instead of emitting 1.0 / sqrt(x) which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

pipeline-db (VEGA10/LLVM 9):
Totals from affected shaders:
SGPRS: 16872 -> 16864 (-0.05 %)
VGPRS: 15320 -> 15464 (0.94 %)
Spilled SGPRs: 2021 -> 2133 (5.54 %)
Code Size: 1915464 -> 1917476 (0.11 %) bytes
Max Waves: 641 -> 639 (-0.31 %)

pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 43936 -> 44120 (0.42 %)
VGPRS: 41776 -> 41972 (0.47 %)
Spilled SGPRs: 875 -> 875 (0.00 %)
Code Size: 4468164 -> 4468120 (-0.00 %) bytes
Max Waves: 2412 -> 2414 (0.08 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 60096 -> 60096 (0.00 %)
VGPRS: 63552 -> 63648 (0.15 %)
Spilled SGPRs: 6135 -> 6117 (-0.29 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 6252996 -> 6249772 (-0.05 %) bytes
Max Waves: 2324 -> 2337 (0.56 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
2020-03-27 07:45:47 +01:00
Samuel Pitoiset
66426ce119 ac/nir: use llvm.amdgcn.rcp for nir_op_frcp
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.

pipeline-db (VEG10/LLVM 9):
Totals from affected shaders:
SGPRS: 50384 -> 50312 (-0.14 %)
VGPRS: 42572 -> 42696 (0.29 %)
Spilled SGPRs: 1372 -> 1372 (0.00 %)
Code Size: 5692040 -> 5691428 (-0.01 %) bytes
Max Waves: 3954 -> 3951 (-0.08 %)

pipeline-db (VEG10/LLVM 10):
Totals from affected shaders:
SGPRS: 78512 -> 78464 (-0.06 %)
VGPRS: 62408 -> 62484 (0.12 %)
Spilled SGPRs: 1502 -> 1502 (0.00 %)
Code Size: 8106188 -> 8103372 (-0.03 %) bytes
Max Waves: 7759 -> 7753 (-0.08 %)

pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 112760 -> 113232 (0.42 %)
VGPRS: 111132 -> 110568 (-0.51 %)
Spilled SGPRs: 5870 -> 5940 (1.19 %)
Spilled VGPRs: 650 -> 652 (0.31 %)
Code Size: 11887232 -> 11561744 (-2.74 %) bytes
Max Waves: 8964 -> 9015 (0.57 %)

LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
2020-03-27 07:45:43 +01:00
H.J. Lu
e352e7e792 x86: Add ENDBR at function entries
Intel Control-flow Enforcement Technology (CET):

https://software.intel.com/en-us/articles/intel-sdm

contains shadow stack (SHSTK) and indirect branch tracking (IBT).
When IBT is enabled, all indirect branch targets must start with
ENDBR instruction which is a NOP on non-CET processors.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2538

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
2020-03-26 16:38:46 -07:00
Marek Olšák
9899a8e26c mesa: try to fix the android build
Fixes: 8a3e2cd9b2
Closes: #2685

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
2020-03-26 18:43:42 -04:00
Francisco Jerez
36c155a017 intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround.
This has been reported to fix a hang in Shadow of Mordor on Gen12.
One of its compute shaders seems to cause an in-order exec_all
dependency to be merged into an out-of-order SET dependency slot,
which would prevent us from baking the SET dependency into the parent
instruction, leading to an assert failure in emit_inst_dependencies()
(Thanks to Rafael for noticing that).  Prevent that by avoiding
combination of in-order dependencies whenever that would cause a SET
dependency to be demoted to a SYNC.NOP instruction.

Fixes: e14529ff32 "intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow."
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-03-26 19:09:42 +00:00
H.J. Lu
007e623025 x86_init_func_common: Add ENDBR at function entry
Intel Control-flow Enforcement Technology (CET):

https://software.intel.com/en-us/articles/intel-sdm

when IBT is enabled, all indirect branch targets must start with ENDBR
instruction which is a NOP on non-CET processors.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2575

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
2020-03-26 18:36:20 +00:00
Danylo Piliaiev
2d0599b1b4 intel/aub_viewer: Fix format specifier for uint64_t
Use PRIx64 instead of lx for uint64_t

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2692
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
2020-03-26 18:00:15 +00:00
Icecream95
7b9f1b6ef7 panfrost: Extend the tiled store fast-path to loads
The access functions are forced to be inline, so performance shouldn't
be impacted for stores.

WebGL performance in Firefox is more than doubled, and track loading
in STK is noticeably faster.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
2020-03-26 14:34:55 +00:00
Icecream95
dac1573a35 mesa/format_utils: Add a fast-path for RGBA to BGRA
This is similar to an existing fast-path, but this is for an array
source while the existing one is for an array destination.

Firefox can hit this case for WebGL when GL compositing is not used.
For a WebGL sample on the Panfrost driver, the frame-rate increased
from 19.4 fps to 20.6 fps, which is a 6% gain.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
2020-03-26 13:36:47 +00:00
Tapani Pälli
0847fe6e7f glsl: set error_emitted true if type not ok for assignment
Patch changes also existing assert to not trigger when we have
error types in assignment.

v2: simplify, cleanup (Ian)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2629
Fixes: d1fa69ed61 ("glsl: do not attempt assignment if operand type not parsed correctly")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
2020-03-26 12:41:12 +00:00
Alexandros Frantzis
05069e1f07 gitlab-ci: Fix traces caching in tracie
We are currently comparing a hex string representation of the git lfs
OID with a byte array representation of the locally calculated OID,
causing detection of valid cached traces to fail. Ensure we are
comparing compatible representations (in this case hex strings).

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4300>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4300>
2020-03-26 13:55:26 +02:00
Boris Brezillon
efdce97e4b vtn/opencl: add rint-support
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
6d69ed88f8 vtn/opencl: add native exp2/log2-support
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
7b2bfb6bc4 vtn/opencl: add native exp10/log10-support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
25cb87bcdd vtn/opencl: add native exp/log-support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
c98e745e78 compiler/nir: move build_log helper into builtin-builder
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
f59ae68838 compiler/nir: move build_exp helper into builtin-builder
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Erik Faye-Lund
4821ec6d8f vtn/opencl: fully enable OpenCLstd_Clz
Fixes: 7325f6ac98 ("vtn/opencl: add clz support")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
2020-03-26 10:14:22 +00:00
Neil Armstrong
51831537a2 gitlab-ci: re-enable mali400/450 and t820 jobs
The FILES_HOST_NAME and FILES_HOST_URL are in the baylibre's runner
environment to make it more flexible.

Also use the new aarch64 mesa-ci-aarch64-lava-baylibre runner with
embedded nginx server to serve the LAVA artifacts.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
2020-03-26 09:30:48 +00:00
Neil Armstrong
842f13d8f8 gitlab-ci: add FILES_HOST_URL and move FILES_HOST_NAME into jobs
The FILES_HOST_URL & FILES_HOST_NAME will be in the Baylibre's runner
environment, move them into the t860/t720/t760 jobs using Collabora's
runner.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
2020-03-26 09:30:48 +00:00
Tomeu Vizoso
b123849880 gitlab-ci: Serve files for LAVA via separate service
Currently, we store the kernel and ramdisk for each LAVA job in the
artifacts of the job that built them. Because artifacts are stored in
GCE and LAVA labs aren't, this causes a lot of egress with is expensive.

To avoid this, have runners download most of the data via the (cached)
container images once, and for each job upload the kernel and ramdisk to
a server outside GCE.

Right now we only have Collabora's runner with a local web server, so
jobs that go to Baylibre's lab have been disabled.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
2020-03-26 09:30:48 +00:00
Tomeu Vizoso
92f3c51560 gitlab-ci: Place files from the Mesa repo into the build tarball
There's some files from the .gitlab-ci directory that are needed in the
test stage and that, because the Mesa repository isn't checked out in
that stage, need to be made available through other means.

Because those files are going to be needed in LAVA devices, place them
ino the tarball containing the built files so it's available to both
gitlab-ci runners and LAVA devices.

Before those files were passed in the artifacts of the Gitlab CI job,
but this commit places them into the built tarball so scripts later in
the pipeline don't need to account for this discrepancy.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
2020-03-26 09:30:48 +00:00
Marek Olšák
b94c277fd1 radeonsi: enable full out-of-order drawing when allow_draw_out_of_order is set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Marek Olšák
8c053e5fad mesa: allow out-of-order drawing to optimize immediate mode if it's safe
This increases performance by 11-13% in Viewperf11/Catia - first scene.

Set allow_draw_out_of_order=true to enable this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Marek Olšák
0c6a667d93 glsl_to_tgsi: set shader_info::writes_memory
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Marek Olšák
85a723975b nir: add and gather shader_info::writes_memory
for out-of-order drawing.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
2020-03-26 03:08:34 -04:00
Kristian H. Kristensen
d269fb33b0 radeonsi: Stop exposing PIPE_SHADER_CAP_FP16
Not fully supported.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
2020-03-25 22:43:41 +00:00
Vinson Lee
603f38f171 util/u_process: Add util_get_process_exec_path for macOS.
Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2682
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4313>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4313>
2020-03-25 14:38:03 -07:00
Christian Gmeiner
8cdace95ac freedreno: ssbo: mark resource read or written depending on usage
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
061b262a0c freedreno: ssbo: keep track if a buffer gets written
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
0ed053f03d freedreno: simplify fd_set_shader_buffers(..)
Clear the modified bits for enabled_mask and then iterate over the
whole range and set the specific bit where there is a buffer.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Christian Gmeiner
3340cbd398 freedreno: calculate modified bit mask only once
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1963>
2020-03-25 20:49:32 +00:00
Roland Scheidegger
3cbcb1b73e gallium/util: Add back (and rename) util_float_to_half implementation
This implementation was removed by 8b8af6d3 ("gallium/util: Switch
util_float_to_half to _mesa_float_to_half()'s impl.")
It was not actually broken, but _mesa_float_to_half() implements
round-to-nearest-even, whereas util_float_to_half() implemented
round-to-zero. So rename it appropriately.
GL actually never cares about rounding (except a broken piglit test),
however d3d10 very much does and requires RTZ for float to half
conversion. Moreover, apparently at least radeon gpus actually always
do RTZ when doing RT writes (and I'd suspect for shader image writes
as well). Hence it seems appropriate to hook up this rtz function to
the format instead. This will cause llvmpipe and softpipe to use rtz
rounding for clears with half float formats, and softpipe would use rtz
behavior for rt writes as well (llvmpipe has that hardcoded), not sure
if "real" hw drivers hit this function for much.
(For shader opcodes would still need to figure out what rounding to use
appropriately, but this is a question for another day.)
Note should probably unify with _mesa_float_to_float16_rtz. Unclear at
this point which one is better, so just restore previous function here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4312>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4312>
2020-03-25 19:16:13 +00:00
Marek Vasut
9e78f17b74 etnaviv: Emit PE.ALPHA_COLOR_EXT* on GPUs with half-float support
At least GC880 (iMX6S), GC2000 (iMX6Q) blobs do not emit the
PE.ALPHA_COLOR_EXT0 and PE.ALPHA_COLOR_EXT1 into the command
stream. The GCnano (STM32MP1) is not affected by this change
either. This is because neither of these GPUs support the
half-float feature.

Emit PE.ALPHA_COLOR_EXT* in etnaviv only if half-float support
is present in the GPU. This fixes all of the currently failing
dEQPs in this group:
  dEQP-GLES2.functional.fragment_ops.blend.*

Fixes: 76adf041f2 ("etnaviv: fix blend color on newer GPUs")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
2020-03-25 19:21:05 +01:00
Roland Scheidegger
4897e70ccd gallivm: disable rgtc/latc SNORM accellerated fetches
Unfortunately this appears to be bugged (it seems the piglit tests aren't
quite exhaustive enough). I'm almost certain it's the lerp
(lp_build_lerpdxta()) which doesn't handle signed numbers correctly, let's
disable for now.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4311>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4311>
2020-03-25 17:56:11 +00:00
Erik Faye-Lund
8c30b9d987 rbug: do not return void-value
Returning a void-value is nonsensical, and in this case it seems like a
mistake.

This eliminates a warning when building on MSVC.

Fixes: fb04e5da97 ("gallium: add pipe_screen::finalize_nir")
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Erik Faye-Lund
411d7429c9 rbug: clean up cast-warnings
Similarly to the previous cast; on 64-bit Windows, unsigned long is
32-bit, and casting a pointer to a non-matchin bit-width integer produce
warnings. So let's use uintpre_t for this purpose instead.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Erik Faye-Lund
079cb4949d pipebuffer: clean up cast-warnings
This code produces warnings, so let's fix that. The problem is that
casting a pointer to an integer of non-pointer-size triggers warnings on
MSVC, and on 64-bit Windows unsigned long is 32-bit large.

So let's instead use uintptr_t, which is exactly for these kinds of
things.

While we're at it, let's make the resulting index a plain "unsigned",
which is the type this originated from before we started with this
cast-dance.

Fixes: 1a66ead1c7 ("pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flags")
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
2020-03-25 14:19:37 +00:00
Lionel Landwerlin
1271193932 vulkan/overlay: Add a workaround semaphore for application presenting without one
When an application calls vkQueuePresent() on a different queue than
the one we run our drawing on and it doesn't give a semaphore to wait
on, let's insert our own semaphore so that we don't race the
application's drawing.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2540
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3893>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3893>
2020-03-25 13:42:01 +02:00
Pierre-Eric Pelloux-Prayer
5533c41541 ac: fix ac_build_is_helper_invocation when postponed_kill is null
If there was no demote() in the shader, ac_build_is_helper_invocation
behaves exactly the same as ac_build_load_helper_invocation, i.e.
the helper lanes are the same as they were at the beginning of the shader.

Fixes: de57ea2a3d ("amd/llvm: implement nir_intrinsic_demote(_if) and nir_intrinsic_is_helper_invocation")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4301>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4301>
2020-03-25 08:19:38 +01:00
Pierre-Eric Pelloux-Prayer
84da4ded4b nir: update uses_demote flag in discard_to_demote pass
Otherwise the ctx.ac.postponed_kill will not be allocated.

Fixes: ce87da71e9 ("nir: add pass to lower discard() to demote()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2662
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4301>
2020-03-25 08:19:33 +01:00
Neil Roberts
fc8432e6d6 glsl/lower_precision: Lower builtins depending on arguments
When an ir_call is encountered that invokes a builtin, it will now try
to generate a lowered version of the builtin. This only happens if all
of the arguments to the function are lowerable. Previously the builtin
would be inlined before the lowering pass is invoked and then the
implementation would be lowered as a consequence of the pass. However
this causes problems if the builtin has multiple arguments and the
implementation has operations on only a few of the arguments before
combining it with the others. In that case the entire builtin should
only be lowered if all of the arguments are lower precision. The
previous approach would end up lowering only parts of the
implementation.

The lowered implementations are cached in a hash table in case they can
be reused.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
e7434c0a06 glsl: Inline builtins in a separate pass
Previously, the ir_call functions for builtin functions were replaced
with the inline implementation immediately after being added to the
instruction list. This patch replaces that with a separate pass that
lowers them after the conversion from AST to IR is complete. This will
be useful to be able to insert some handling for the precision lowering
pass before the inlining. This needs to happen because the precision
of the operations in the inlined implementation depends on the highest
precision of all of the arguments to the call.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Hyunjun Ko
1ee2ad584c freedreno/ir3: enable nir_opt_loop_unroll on a6xx
If precision lowering happens at GLSL IR, loop_analysis at IR doesn't
work as expected since it can't handle things like:

"(expression bool < (expression float16_t f2fmp (var_ref ndx) ) (constant float16_t (1.000000)) )"

So we'd rather do this optimization at the NIR stage.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
61f7a1dfc5 freedreno/ir3: Lower bools to bitsize
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Iago Toral Quiroga
467c9a0faa nir: add a bool bitsize lowering pass
The pass lowers 1-bit booleans produced by NIR to the native bitsize
of the operations that produce them.

v2: change on lower_load_const_instr after upstream changes. Added
    TODO2 to explain it, as it was not properly tested yet (see
    already existing TODO) (Neil)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Hyunjun Ko
75674ed4d4 freedreno: Enable mediump lowering
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
cc09745714 glsl: Add unit tests for the lower_precision pass
Adds a unit tests script that invokes the standalone compiler with
--lower-precision and verifies that lowered operations are being used.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
32cd3bd850 glsl/standalone: Add an option to lower the precision
Adds a --lower-precision option that just sets the LowerPrecision
compiler option. That way it can be used in unit tests to test the
precision lowering pass.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
b83f4b9fa2 glsl: Add an IR lowering pass to convert mediump operations to 16-bit
This works by finding the first rvalue that it can lower using an
ir_rvalue_visitor. In that case it adds a conversion to float16
after each rvalue and a conversion back to float before storing
the assignment.

Also it uses a set to keep track of rvalues that have been
lowred already. The handle_rvalue method of the rvalue visitor doesn’t
provide any way to stop iteration. If we handle a value in
find_precision_visitor we want to be able to stop it from descending into
the lowered rvalue again.

Additionally this pass disallows converting nodes containing non-float.
The can_lower_rvalue function explicitly excludes any branches
that have non-float types except bools. This avoids the need to have
special handling for functions that convert to int or double.

Co-authored-by: Hyunjun Ko <zzoon@igalia.com>

v2. Adds lowering for texture samples

v3. Instead of checking whether each node can be lowered while walking the
tree, a separate tree walk is now done to check all of the nodes in a
single pass. The lowerable nodes are added to a set which is checked
during find_precision_visitor instead of calling can_lower_rvalue.

v4. Move the special case for temporaries to find_lowerable_rvalues. This
needs to be handled while checking for lowerable rvalues so that any
later dereferences of the variable will see the right precision.

v5. Add an override to visit ir_call instructions and apply the same
technique to override the precision of the temporary variable in the
same way as done for builtin temporaries and ir_assignment calls.

v6. Changes the pass so that it doesn’t need to lower an entire subtree in
order do perform a lowering. Instead, certain instructions can be
marked as being indepedent of their child instructions. For example,
this is the case with array dereferences. The precision of the array
index doesn’t have any bearing on whether things using the result of
the array deref can be lowered.

Now, only toplevel lowerable nodes are added to the lowerable_rvalues
instead instead of additionally adding all of the subnodes.

It now also only needs one hash table instead of two.

v7. Don’t try to lower sampler types. Instead, the sample instruction is
now treated as an independent point where the result of the sample can
be used in a lowered section. The precision of the sampler type
determines the precision of the sample instruction. This also means
the coordinates to the sampler can be lowered.

v8. Use f2fmp instead of f2f16.

v9.  Disable lowering derivatives calcualtions, which might not work
properly on some hw backends.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
c525785edc glsl/hierarchical_visitor: Call leave_callback on leaf nodes
Previously for leaf ir_instructions only the enter callback was
called. This makes it a bit difficult to make a pass that wants to
visit every instruction using a stack. Making it call the leave
callback as well makes it behave less surprisingly.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Neil Roberts
0e1680a1e2 glsl: Add a method to get precision from a deref instruction
Adds ir_dereference::precision(). For a normal variable dereference,
the precision comes from the variable. For a record member it comes
from the field within the record. For an array it can come from
either, depending on where the underlying array is stored. The method
recursively walks the derefs until it finds one of the first two.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3885>
2020-03-24 23:21:21 +00:00
Lionel Landwerlin
ba56684a14 i965/iris: fix crash when calling GetPerfQueryDataINTEL
On a query that was never begun.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4302>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4302>
2020-03-24 22:54:12 +00:00
Marek Olšák
8a3e2cd9b2 glthread: compile marshal_generated.c faster by breaking it up into 8 files
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4270>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4270>
2020-03-24 16:28:30 -04:00
Marek Olšák
cadddbd269 glthread: declare marshal and unmarshal functions as non-static
Declare them in the header file. Then we can split marshal_generated.c
into multiple files.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4270>
2020-03-24 16:28:30 -04:00
Marek Olšák
03da51eb07 glthread: inline SET_func and add -O1 to build _mesa_create_marshal_table faster
The compile time of marshal_generated.c improved from 30.1s to 12.4s.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4270>
2020-03-24 16:28:30 -04:00
Samuel Pitoiset
238e2ed210 radv: enable VK_KHR_8bit_storage on GFX6-GFX7
Enabling a Vulkan extension doesn't mean that all features need
to be implemented. DOOM Eternal crashes at launch if that ext
is not supported but it doesn't matter if the features are enabled
or not.

Let's enable it like we did for VK_KHR_16bit_storage.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4299>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4299>
2020-03-24 16:34:21 +00:00
Pierre-Eric Pelloux-Prayer
bd22a0f710 util/u_process: fix Windows build
Reported by Brian Paul.

Fixes: f8f1413070 ("util/u_process: add util_get_process_exec_path")
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4303>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4303>
2020-03-24 15:58:34 +00:00
Alyssa Rosenzweig
6a4fadce12 pan/bi: Rewrite aligned vectors as well
This still isn't optimal, but it handles another common case where we
have a vector "prefix" and can rewrite directly. The last case is one
where writemasks and such would start coming into play and - for the
moment - is not worth the hike in complexity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4288>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4288>
2020-03-24 15:29:35 +00:00
Alyssa Rosenzweig
5a3493c536 pan/bi: Lower combines to rewrites for scalars
This avoids unneeded moves for scalars. It still generates suboptimal
code for vectors, however.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4288>
2020-03-24 15:29:35 +00:00
Alyssa Rosenzweig
e0a51d5308 pan/bi: Ingest vecN directly (again)
Last time, I swear. We still generate writemasks but SSA-like ones and
do the lowering ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4288>
2020-03-24 15:29:35 +00:00
Jonathan Marek
04509dae7f turnip: implement depth clamp
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
2020-03-24 13:01:44 +00:00
Jonathan Marek
afe27d5345 turnip: fix znear clipping
Vulkan clips znear at 0 instead of -1.

Fixes dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
2020-03-24 13:01:44 +00:00
Jonathan Marek
07a8100aed freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMP
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
2020-03-24 13:01:44 +00:00
Rhys Perry
43918c9a7f aco: implement 64-bit VGPR constant copies in handle_operands()
64-bit VGPR constant copies can happen because of 64-bit constant copy
propagation. Since this optimization is beneficial and more annoying to
deal with in the optimizer, I've implemented 64-bit VGPR constant copies
in handle_operands().

This also sets copy_operation::size correctly for 64-bit constant copies.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4260>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4260>
2020-03-24 11:28:55 +00:00
Rhys Perry
21ba2bc595 aco: remove dead code in handle_operands()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4260>
2020-03-24 11:28:55 +00:00
Rhys Perry
9f4ba2d2b4 nir/gather_info: fix per-vertex handling in try_mask_partial_io
pipeline-db (Navi, ACO):
Totals from affected shaders:
SGPRS: 6432 -> 6432 (0.00 %)
VGPRS: 11924 -> 11924 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 1596 -> 1596 (0.00 %) dwords per thread
Code Size: 575524 -> 518620 (-9.89 %) bytes
LDS: 12187 -> 12187 (0.00 %) blocks
Max Waves: 2695 -> 2695 (0.00 %)

Helps a few hundred Dark Souls 3 shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4190>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4190>
2020-03-24 11:09:15 +00:00
Pierre-Eric Pelloux-Prayer
f1cc13727c radeonsi: enable workarounds for YoYo engine based games
Without the radeonsi_sync_compile option the games crashes at
startup.
The engine seems to be using a custom global new operator and
it doesn't plays well with multithreading it seems.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1310
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1271
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1272
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1288
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2611
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
2020-03-24 08:33:29 +01:00
Pierre-Eric Pelloux-Prayer
8f48e7b1e9 util/xmlconfig: add new sha1 application attribute
This is useful to enable workarounds for applications with a generic name.

For instance all games made with the YoYo game engine have the same executable
name "runner".

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
2020-03-24 08:33:29 +01:00
Pierre-Eric Pelloux-Prayer
f8f1413070 util/u_process: add util_get_process_exec_path
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
2020-03-24 08:30:34 +01:00
Pierre-Eric Pelloux-Prayer
2cb965e5b6 util/os_file: extend os_read_file to return the file size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4181>
2020-03-24 08:30:34 +01:00
Pierre-Eric Pelloux-Prayer
bd6234f24b radeonsi: clarify the conditions when FLUSH_AND_INV_DB is needed
FLUSH_AND_INV_DB should be done when we're changing surface state
registers of a bound depth target.

When depth_clear_value changes, si_state will modify
S_028038_ZRANGE_PRECISION so we need to flush the DB caches.

Verified with the captures from bugs cited below.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1283
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1330
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4263>
2020-03-24 08:05:12 +01:00
Jason Ekstrand
67a10ea215 intel/dump_gpu: Handle a bunch of getparam in the no-HW case
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
2020-03-24 06:28:29 +00:00
Jason Ekstrand
7fd4184378 intel/dump_gpu: Add an ensure_device_info helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
2020-03-24 06:28:29 +00:00
Jason Ekstrand
be451f71ab anv: Stop fetching the timestamp frequency ourselves
gen_get_device_info_from_fd fetches the timestamp frequency from the
kernel.  ANV also carrying code for it is redundant.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4250>
2020-03-24 06:28:28 +00:00
Chia-I Wu
d63d000686 egl/android: enable/disable KHR_partial_update correctly
Commit f3728816af (egl/android: require ANDROID_native_fence_sync
for buffer age) re-added some stale code removed in commit
b4345da876 (egl/android: Delete set_damage_region from egl dri
vtbl).  Remove it now.

Commit b4345da876 assumes KHR_partial_update is only
driver-dependent.  That is mostly true except that the extension
also introduces buffer age query, which depends on
ANDROID_native_fence_sync on Android.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4235>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4235>
2020-03-23 16:22:24 -07:00
Eric Anholt
41412cc4b7 ci: Ban the recent popular freedreno a630 intermittent failure.
This popped up last thursday.  The only relevant code commit was my pixel
center half integer change, but the more likely thing to me seems to be
having shuffled the test order by introducing more skips the day before.

Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2670
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4287>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4287>
2020-03-23 20:22:53 +00:00
Marek Olšák
719063d4d0 st/mesa: fix use of uninitialized memory due to st_nir_lower_builtin
reported by valgrind

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>
2020-03-23 20:01:31 +00:00
Rhys Perry
17c7f4e30e aco: fix boolean undef regclass
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>
2020-03-23 19:43:09 +00:00
Roman Stratiienko
4ed12efb58 lima: Add missing source file to Android.mk
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4283>
2020-03-23 19:26:29 +00:00
D Scott Phillips
1182a3934a intel/tools/aubinator_error_decode: Decode ring buffers from HEAD to TAIL
Capture the HEAD and TAIL register values from the dump and
properly index the ring buffer using those. Previously we would
decode the ring buffer from the beginning, printing out whatever
happened to be there.

Also, properly pass the `from_ring` parameter to gen_print_batch()
so that decoding doesn't stop once MI_BATCH_BUFFER_END is
encoutered.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4261>
2020-03-23 19:10:50 +00:00
Elie Tournier
84e707e6f2 docs/features: Update virgl OpenGL 4.5 features
GL_ARB_clip_control and GL_KHR_robustness are now expose in the guest.

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4160>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4160>
2020-03-23 18:49:13 +00:00
D Scott Phillips
49f9a0bb57 intel/tools/aubinator_error_decode: read HW Context before other batches
The hardware context buffer has state that was set before the
batch started. By decoding it first, references to things like
Dynamic State Base Address are decodable in the command batches.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4246>
2020-03-23 18:13:37 +00:00
Sagar Ghuge
c40acdef52 iris: Set patch count threshold in 3DSTATE_HS
Lets specifiy maximum number of patches that will be accumulated before
a thread is dispatched.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
2020-03-23 17:57:57 +00:00
Sagar Ghuge
60c789543e anv: Set patch count threshold in 3DSTATE_HS
Lets specifiy maximum number of patches that will be accumulated before
a thread is dispatched.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
2020-03-23 17:57:57 +00:00
Sagar Ghuge
1a5ac646ce intel/compiler: Track patch count threshold
Return the number of patches to accumulate before an 8_PATCH mode thread
is launched.

v2: (Kenneth Graunke)
- Track patch count threshold instead of input control points.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
2020-03-23 17:57:57 +00:00
Sagar Ghuge
b3dd54fe13 intel/genxml: Add patch count threshold field on gen12
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
2020-03-23 17:57:57 +00:00
Andres Gomez
39ac87bf50 gitlab-ci/traces: Add Vulkan sample entries for POLARIS10
v2:
  - Updated commit log.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4103>
2020-03-23 17:36:32 +00:00
Denys
6bca192e12 gitlab: add bug report template
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4089>
2020-03-23 17:15:42 +00:00
Rhys Perry
9d56ed199b aco: emit IR in IF's merge block instead if the other side ends in a jump
Fixes NIR such as:
if (divergent) {
   a = sgpr()
} else {
   break;
}
use(a)

Previously we would have emitted:
if (divergent) {
   a = sgpr()
}
if (!divergent) {
   break;
}
use(a)

But "a" isn't available at it's use. Now we emit:
if (divergent) {
}
if (!divergent) {
   break;
}
a = sgpr()
use(a)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 1936 -> 1936 (0.00 %)
VGPRS: 1264 -> 1264 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 159408 -> 159152 (-0.16 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 81 -> 81 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2557
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Rhys Perry
8d8c864beb aco: improve check for unreachable loop continue blocks
The old code would have previously caught:
loop {
   ...
   break
}
when it was meant to just catch:
loop {
   if (...)
      break
   else
      break
}

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Rhys Perry
46e94fd854 aco: skip NIR in unreachable merge blocks
NIR removes most of this but undef instructions for loop header phis can
remain. These were harmless because ACO would DCE them itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Rhys Perry
638cbc21a1 aco: handle when ACO adds new continue edges
Usually a loop ends with a uniform continue. If it doesn't and we end up
adding our own continue edges (because of continue_or_break or divergent
breaks at the end), we have to add extra operands to the loop header phis.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Rhys Perry
f2c4878de9 aco: handle missing second predecessors at merge block phis
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Rhys Perry
f1a2e1df78 aco: set has_divergent_branch for discards in loops
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
2020-03-23 15:55:12 +00:00
Andres Gomez
8bc3d6574c gitlab-ci: add python3-requests to the test-vk container
After 90a39af5f6 ("ci: Drop the git dependency in tracie"), we have
this error in the radv-polaris10-traces job:

"
...

+ /builds/tanty/mesa/artifacts/tracie/tests/test.sh
tracie_succeeds_if_all_images_match: Fail
Traceback (most recent call last):
  File "/tmp/tracie.test.glY0O23HJo/tracie.py", line 6, in <module>
    import requests
ModuleNotFoundError: No module named 'requests'

...
"

v2:
  - Updated commit log to be more descriptive (Michel).

Fixes: 90a39af5f6 ("ci: Drop the git dependency in tracie")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4237>
2020-03-23 17:17:56 +02:00
Samuel Pitoiset
7ac8bb33cd radv/llvm: fix subgroup shuffle for chips without bpermute
bpermute only exists on GFX8+ and only with Wave32 on GFX10. Instead
we have to use readlane with a waterfall loop to defeat the LLVM
backend.

This fixes DOOM Eternal which requires subgroup shuffle.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
2020-03-23 14:19:03 +00:00
Roman Stratiienko
2a70a1d69d panfrost: Align Android makefiles with recent changes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Roman Stratiienko <roman.stratiienko@nure.ua>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
2020-03-23 14:03:22 +00:00
Samuel Pitoiset
6c8ccbe41b gitlab-ci: add a bunch of new fossils from the Sascha Vulkan demos
The whole fossils-db is only 448KB of data which is pretty small.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
2020-03-23 12:16:02 +00:00
Samuel Pitoiset
48e920315c gitlab-ci: add a new stage for RADV CI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
2020-03-23 12:16:02 +00:00
Samuel Pitoiset
e22d562c17 gitlab-ci: compile fossils with more ASICs
I think we want to cover these 3 generations at the barely minimum.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
2020-03-23 12:16:02 +00:00
Samuel Pitoiset
1517e58c1b gitlab-ci: compile fossils with both RADV compiler backends (LLVM/ACO)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4082>
2020-03-23 12:16:02 +00:00
Jan Zielinski
8b3b07afc0 gallium/gallivm: Remove workaround disabling AVX code for newer CPUs
The change enables using full 256-bit AVX and AVX2 instructions
on newer platforms.

Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4225>
2020-03-23 09:20:51 +00:00
Samuel Pitoiset
de550805c5 radv/winsys: spoof some values for num_render_backends in the null winsys
To avoid crashes when RADV_FORCE_FAMILY is set to GFX9+ because
num_render_backends is used to compute binning state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
2020-03-23 09:50:53 +01:00
Samuel Pitoiset
b911af06cd radv/winsys: fix wrong PCI ID for Vega10 in the null winsys
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4282>
2020-03-23 09:50:51 +01:00
Eric Anholt
050ec8ff53 glsl: Restore the IsES flag on the shader when reading from cache.
I found that when trying to MESA_SHADER_CAPTURE_PATH a trace, I was
getting "GLSL >= 3.00" for the ES shaders I was trying to capture.
Keeping this metadata in the cached shader program lets us capture
correctly.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4219>
2020-03-22 20:49:37 -07:00
Dave Airlie
9e3efa4294 gallivm: add support for rgtc/latc fetches.
Annoyingly heaven uses rgtc2 snorm but this at least avoids
the function call overheads to the util fetch functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
2020-03-23 11:02:03 +10:00
Dave Airlie
b3894e52c2 gallivm/s3tc: split out dxt5 alpha code
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3924>
2020-03-23 11:02:00 +10:00
Jordan Justen
f02ae69867 intel: Add TGL PCI ID
Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-03-21 23:49:38 -07:00
Jordan Justen
1c6ef0165f intel: Update TGL PCI strings
Ref: Bspec 44455
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-03-21 23:49:34 -07:00
Alyssa Rosenzweig
d9d549ff88 pan/bi: Pack csel4 opcodes
These are pretty straightforward but there's a lot of details to keep
straight. In the IR, we keep a general logical comparator and types
separately; in the hardware, the type gets fused with a (much more)
limited number of comparators. So there's a fair bit of code here to
account for these differences, fusing in the type information, and
changing up argument order as necessary to make it actually correct.
Anything to save a bit!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
5cdc31abd6 pan/bi: Default csel to "!= 0" mode
This way we always have regular csel conditions instead of a weird
.always special case for 3-src CSEL mode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
46f526eb1e pan/bi: Use bi_lookup_immediate when packing
This gets us part of the way there to packing lo/hi separately. A little
more work is needed to do this "properly", but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
11bccb0564 pan/bi: Respect shift when printing immediates
We allow packing multiple immediates in, but we were missing this in the
print.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
3f786ed10b pan/bi: Implement csel fusing
When generating csel instructions, we can peak to see what condition is
being used. If we're using a "nice" condition, we can fuse it in with
the csel itself, ideally letting the condition itself be DCE'd away.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
5a02c871f2 pan/bi: Add soft NIR->BIR condition translation
We would like to use this routine opportunistically when fusing
conditions into csels and branches, so let's add a mode where we don't
abort.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
cd7fec782e pan/bi: Remove hacks for 1-bit booleans in IR
Now that we lower them away, a bunch of special cases disappear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
12299dead7 pan/bi: Lower bool to ints
Currently we lower to int32, but once mediump lands we'll be ready for
that too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
1097c69087 pan/bi: Pack LD_ATTR
Also requires the usual R61/62 games.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
0be1116b81 pan/bi: Pack st_vary
This should let varying writes go through finally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
9213b2520c pan/bi: Add store_channels property
It can't be inferred from the usual writemask since stores don't write
to a register destination.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
c57ac9d136 pan/bi: Generalize data register setting
So we can use it for stores too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
9458b017a9 pan/bi: Flesh out st_vary IR
We need to make the semantics of BI_VECTOR a bit more precise -
vectorize only the first argument, not all of them. This is enough for
current and future users, as far as I know.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
409e4f8a49 pan/bi: Pack ld_var_addr
Choo choo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
7321a17c6a pan/bi: Pack ld_ubo ops
Routes some infrastructure to do so at least slightly generically but
we'll see.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
908341ea3f pan/bi: Add bi_load32_components helper
Pattern seems to crop up a lot.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
8bb16138b6 pan/bi: Include UBO index for sysval reads
Trivially zero.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
fc0b49bb2c pan/bi: Index out constants in instructions
We rewrite BIR_INDEX_CONSTANT (and _ZERO) to preassigned constant ports
when assign uniform_const for the bundle. There are a lot of issues
raised here, unfortunately, and the implementation here is woefully
incomplete with a nasty hack for loads... nevertheless, it's somewhere
to start.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
d2d0de962e pan/bi: Document constant related errata(?)
We're not totally sure what's up with this but Connor says if you
violate it Bad Things happen in your shader. I think this might be an
issue affecting early Bifrost (G71, ..?); when we know more we can look
into patching in a fix.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
eb590a98d2 pan/bi: Pack a constant quadword
The piping isn't there to make use of it yet, but this stubs out
constant support at the clause level.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
50d3f4df45 pan/bi: Add move lowering pass
We need ALU mostly scalarized, but we get vector moves created from
lower_vec_to_mov so let's scalarize that ourselves rather than bother
NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:35 +00:00
Alyssa Rosenzweig
58a51c49bb pan/bi: Add bi_emit_before helper
For BIR lowering passes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:34 +00:00
Alyssa Rosenzweig
6b7077efda pan/bi: Implement FMA/MOV without modifiers
We split off MOV from FMOV since the canonical move on Bifrost doesn't
accept modifiers. (We can still do fmov, but with something like add-0.)
This will also make copyprop a little nicer, I think. Anyway, the
non-modifier version we can implement as-is for FMA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
2020-03-22 03:32:34 +00:00
Jonathan Marek
f8bbf44ca4 etnaviv: nir: add compile_check_limits
To match TGSI compiler behaviour in glmark terrain scene for example.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4199>
2020-03-22 00:29:36 +00:00
Marek Olšák
303842b2db ac: fix fast division
This stopped working with LLVM 11 and might occasionally have been broken
on older LLVM, because the metadata was set on the mul, not on the rcp.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
2020-03-21 22:34:17 +00:00
Eduardo Lima Mitev
55b0a676fd turnip: Instance can be NULL resolving 'GetInstanceProcAddr' entry point
Using turnip driver without a vulkan loader is currently broken because
the entry point resolver is expecting a valid instance when resolving
'vkGetInstanceProcAddr' through vk_icdGetInstanceProcAddr().

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4257>
2020-03-21 18:56:07 +01:00
Marek Olšák
5cc3ab0ba0 vbo,gallium: make glBegin/End buffer size configurable by drivers
The default is 512 KB, but radeonsi wants 4 MB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
2020-03-21 03:39:51 +00:00
Marek Olšák
11d3aa5e7b glthread: remove the marshal_fail XML attribute
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
c02a1347e5 glthread: ignore vertex arrays with user pointers if they're disabled
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
0b1dd18591 glthread: track which vertex array attribs are enabled
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
c571dda1e0 glthread: rename non_vbo helper functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
bde4505f61 glthread: handle buffer unbinding via glDeleteBuffers
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
15b0719ae2 mesa: put gl_thread_state inside gl_context to remove pointer indirection
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
8a4114b929 glthread: rename marshal.h/c to glthread_marshal.h and glthread_shaderobj.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
df74163995 glthread: move buffer functions into glthread_bufferobj.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
37725e6c38 glthread: autogenerate prototypes for custom-marshalled functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
4ded23a4ad glthread: simplify printing safe_mul in gl_marshal.py
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Marek Olšák
01a50e2493 glthread: remove _mesa_post_marshal_hook, because it's not very useful
and also remove the useless forward declaration of enum marshal_dispatch_cmd_id.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4124>
2020-03-20 23:01:13 -04:00
Jason Ekstrand
aee004a7c8 util/sparse_array: Stash the node level in the node pointer
This reworks the data structure a bit and, in my view, simplifies it.
Instead of each node having a header which has the node level in it, we
use the bottom 6 bits of the pointer for that.  This requires us to
allocate with the os_malloc/free_aligned helpers (which call into
posix_memalign on Linux) but cache-line aligning our allocations is
actually probably a good thing given that we're doing atomics on them.

The primary advantages to doing this is that it changes the number of
memory accesses per tree level from 2 to 1 when walking the tree because
we no longer have to look at node->level.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
2020-03-20 15:31:10 -05:00
Jason Ekstrand
6be65b0777 meson,ci: Disable sparse_array tests on windows
As soon as I switch to using the allocation helpers in os_memory.h,
these tests start blowing up on the Windows build in GitLab CI.  As far
as I can tell, the issue is something with the combination of the debug
allocator in u_debug_memory.c and the mutex implementation in the
version of Wine running in CI.  The tests don't fail on real windows nor
do they fail with newer versions of Wine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
2020-03-20 15:26:07 -05:00
Jason Ekstrand
9fcd8bdbfc util/sparse_array: Add a node_size_log2 temporary
We use this value several times.  It's probably best to encourage the
compiler to only read it once.  I have no proof that this actually makes
any performance improvement whatsoever.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
2020-03-20 15:26:07 -05:00
Jason Ekstrand
7893872a6c util/sparse_array: Finish the sparse_array in the tests
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4228>
2020-03-20 15:26:07 -05:00
Eric Anholt
8edaa843ab ci: Move db820c and db410c's gles3 tests to manual, like radv did.
This should make these tests available for clicking on the web ui in
personal branches, while hiding them from marge and the post-merge CI
pipelines.  We had already disabled db410c's gles3, but it wasn't
available in the ui and you had to hack .gitalb-ci.yml.  db820c is now
being disabled by default, due to instaboots mentioned in
https://gitlab.freedesktop.org/mesa/mesa/issues/2649

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4247>
2020-03-20 18:27:37 +00:00
Mark Menzynski
866a8da2a4 tgsi/util: Change boolean for bool
I was getting errors with "boolean" when compiling. This patch changes
boolean to bool from <stdbool.h>.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
2020-03-20 17:25:25 +00:00
Mark Menzynski
24e82e4533 util/blob: Add overwrite function for uint8
Overwrite function for this type  was missing and I needed it for my project.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3903>
2020-03-20 17:25:25 +00:00
Vasily Khoruzhick
1b49534df2 lima: add support for R and RG formats
Unfortunately these are not supported natively for sampling
so we have to lower them.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
2020-03-20 17:00:10 +00:00
Vasily Khoruzhick
e763c6778c lima: split pixel and texel format tables
This is preparation for the next commit where we may need different
swap_r_b flags for pixel and texel formats.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4241>
2020-03-20 17:00:10 +00:00
Erik Faye-Lund
d4b0e28f62 zink/spirv: do not use bitwise operations on booleans
According to the SPIR-V specification, these operations require
integer-types. When bit_size is 1, we use booleans, which makes us emit
illegal code.

So let's fix the emitting to check if the first source is one bit wide.

For inot we can take a short-cut, and check the destination instead.
This doesn't work for ieq and ine, so let's not bother to do this
BINOP_LOG.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4036>
2020-03-20 16:37:30 +00:00
Michel Dänzer
130c0ba1cc gitlab-ci: Restrict s390x/ppc64el jobs to packet runners
They are hitting timeouts on the gstreamer runners now... *sigh*

Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4233>
2020-03-20 16:39:17 +01:00
Rhys Perry
500842399a radv/winsys: set has_syncobj_wait_for_submit in the null winsys
Needed for Vulkan 1.1+

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4249>
2020-03-20 09:51:06 +00:00
Lionel Landwerlin
58deebe547 intel: add new TGL pci ids
Update following kernel : https://patchwork.freedesktop.org/patch/357921/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bspec: 44455
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
2020-03-20 10:55:57 +02:00
Samuel Pitoiset
2d3223ca90 radv: fix optional pSizes parameter when binding streamout buffers
The Vulkan spec 1.2.135 says:

   "pSizes is an optional array of buffer sizes, specifying the maximum
   number of bytes to capture to the corresponding transform feedback
   buffer. If pSizes is NULL, or the value of the pSizes array element
   is VK_WHOLE_SIZE, then the maximum bytes captured will be the size
   of the corresponding buffer minus the buffer offset."

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2650
Fixes: b4eb029062 ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
2020-03-20 09:25:14 +01:00
Caio Marcelo de Oliveira Filho
fdc6032928 mesa/main: Fix overflow in validation of DispatchComputeGroupSizeARB
An uint64_t can store the result of multiplying two GLuint (uint32_t),
so use that property to check for overflow when calculating the total.

Change the error message so we don't need to care about the actual
total -- which means we don't need a larger than 64-bit value to hold
it.

Fixes: 45ab63c0cb ("mesa/main: add support for ARB_compute_variable_groups_size")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
2020-03-20 03:07:45 +00:00
Marek Olšák
4ac1d3cc45 driconf: enable glthread for "From The Depths"
25% perf improvement

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4254>
2020-03-19 21:27:01 -04:00
Marek Olšák
7a59d6eaa2 winsys/radeon: change to 3-space indentation
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4192>
2020-03-19 20:33:01 -04:00
Marek Olšák
b13d5265cc glthread: don't declare unmarshal functions as inline
They are never inlined.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
efaeac9e84 glthread: clean up debug_print_sync code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
b00d219ec0 glthread: remove debug_print_marshal function
We don't need to print every function we execute.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
951c6acb07 glthread: don't execute any custom VAO and BindBuffer code in the Core profile
It's not needed, because user pointers can never occur there.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
87f6be4456 glthread: track VAOs created by CreateVertexArrays
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
720f34d5eb glthread: enable display lists
They seem to work fine.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
4dcdf974f8 glthread: align the batch buffer to 8 bytes for pointers and doubles again
This was changed when I switched to types from size_t to int.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4251>
2020-03-20 00:00:22 +00:00
Marek Olšák
ff0881c686 mesa: remove redundant api_loopback functions
vbo_attrib_tmp.h implements them, so this loopback code isn't needed
and shouldn't be used.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
2020-03-19 23:24:08 +00:00
Marek Olšák
98d1197233 mesa: use vbo_attrib_tmp.h to generate display list vertex attrib functions
This removes about 1150 lines of code.

The diff is messy, but the new code really starts with save_Attr32bit and
below. Ignore false Eval/Material/Begin changes etc. Git can't figure out
what was really changed. I didn't change them.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4123>
2020-03-19 23:24:08 +00:00
Jason Ekstrand
3252041a78 anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL
Fixes: 43dc842cb9 "anv: Wait for the GPU to be idle before..."
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: D Scott Phillips <d.scott.phillips@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
2020-03-19 21:58:49 +00:00
Eric Anholt
5b57aa79e2 freedreno: Switch to exposing only half-integer pixel centers.
This is what the HW provides us.  If we need integer pixel centers, we
want the state tracker to do the lowering pass so that it gets to optimize
on the subtract.  This is also the shader instructions that the blob is
doing on GLES, and is what Vulkan wants too, as was noted in MR !4172.

shader-db on a630:
total instructions in shared programs: 186689 -> 186168 (-0.28%)
total nops in shared programs: 66253 -> 66139 (-0.17%)
total non-nops in shared programs: 120436 -> 120029 (-0.34%)
total dwords in shared programs: 292192 -> 291168 (-0.35%)
total last-baryf in shared programs: 4810 -> 4734 (-1.58%)
total full in shared programs: 10176 -> 10195 (0.19%)
total constlen in shared programs: 54589 -> 54575 (-0.03%)
total sstall in shared programs: 24582 -> 24802 (0.89%)
total (ss) in shared programs: 3921 -> 3925 (0.10%)
total (sy) in shared programs: 1934 -> 1923 (-0.57%)

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4223>
2020-03-19 21:35:49 +00:00
John Stultz
5c8ba96a54 r600: Fix build error in sfn_nir_lower_fs_out_to_vector.cpp
In trying a full build under AOSP, I ran into the following error:

In file included from external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:33:
external/libcxx/include/set:942:26: error: the specified comparator type does not provide a const call operator [-Werror,-Wuser-defined-warnings]
    static_assert(sizeof(__diagnose_non_const_comparator<_Key, _Compare>()), "");
                         ^
external/mesa3d/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp:78:34: note: in instantiation of template class 'std::__1::multiset<nir_intrinsic_ins
tr *, r600::nir_intrinsic_instr_less, std::__1::allocator<nir_intrinsic_instr *> >' requested here
   using InstrSubSet = std::pair<InstrSet::iterator, InstrSet::iterator>;
                                 ^
external/libcxx/include/__tree:967:5: note: from 'diagnose_if' attribute on '__diagnose_non_const_comparator<nir_intrinsic_instr *, r600::nir_intrinsic_instr_less>':
    _LIBCPP_DIAGNOSE_WARNING(!std::__invokable<_Compare const&, _Tp const&, _Tp const&>::value,
    ^                        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
external/libcxx/include/__config:1244:21: note: expanded from macro '_LIBCPP_DIAGNOSE_WARNING'
     __attribute__((diagnose_if(__VA_ARGS__, "warning")))
                    ^           ~~~~~~~~~~~
1 error generated.

Which is pretty opaque to me, but searching the web suggested
adding a cost, which seems to resovle it.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
0df48e5d1f vc4_bufmgr: Remove duplicative VC definition
This is already defined in
  src/broadcom/cle/v3d_packet_helpers.h:42:9

And was causing build issues in AOSP when building with mmma

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
e3bbe1fa65 etnaviv: Avoid shift overflow
Building with AOSP I'm seeing:

external/mesa3d/src/gallium/drivers/etnaviv/etnaviv_screen.c:245:31: error: signed shift result (0x100000000) requires 34 bits to represent, but 'int' only has 32 bits [-Werror,-Wshift-overflow]
         system_memory = 4096 << 20;

system_memory is a uint_64t, so this patch addresses the issue
by casting 4096 to a unint_64t before the shift is done.

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
John Stultz
511c6408f4 Android.mk: Tweak MESA_ENABLE_LLVM checks
Change the MESA_ENABLE_LLVM checks in Android.mk
files in order to get mesa3d to build w/ AOSP
using mmma.

This tries to re-create a change that was introduced
in the following merge in the AOSP branch:
  69f2c0128d2b Merge branch 'aosp/upstream-18.0'

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
2020-03-19 21:20:08 +00:00
Jason Ekstrand
9dbff6f6ce intel/iris: Always initialize CCS to 0
Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a
misunderstanding of the following lines in the bspec:

    The following are the general SW requirements for MCS buffer clear
    functionality:
        ...
         - If Software wants to enable Color Compression without Fast
           clear, Software needs to initialize MCS with zeros.
         - Lossless compression and CCS initialized to all F (using HW
           Fast Clear or SW direct Clear) on the same surface is not
           supported.

The first line does not refer to the CCS as the comment author supposed
but refers to the MCS as the comment says.  It means that if you want to
use MCS compression without a fast-clear, you should initialize the MCS
to 0x00.  This is because the value 0x00 in the MCS means "all data is
in plane 0" which is a perfectly valid non-fast-clear initialization.
It's also the value the MCS should be in if you do a RECTLIST slow-clear
where the primitive fully covers each pixel such that the same value is
written to all samples.

The second line in the above quote seems to imply that CCS fast-clear is
incompatible with MCS fast-clear.  In particular, MCS+CCS fast-clear
uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in
either the compressed or the pass-through state.  Therefore, we should
initialize the CCS to 0x00 even for MCS+CCS surfaces.

Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
2020-03-19 20:54:19 +00:00
Lionel Landwerlin
507abc3959 isl: drop min row pitch alignment when set by the driver
When the caller of the isl_surf_init() specifies a row pitch, do not
consider the minimum CCS requirement if it's incompatible with the
caller's value.

isl_surf_get_ccs_surf() will check that the main surface alignment
matches CCS expectations.

v2: Simplify checks (Nanley)

v3: Add Comment about isl_surf_get_ccs_surf() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Fixes: a3f6db2c4e ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
2020-03-19 19:17:10 +00:00
Lionel Landwerlin
def3470e9b isl: only apply main surface ccs pitch constraint with CCS
We could be creating a Y-tiled surface that isn't going to use CCS
(this could be the case when clearly indicated through modifiers).
Don't apply the main surface pitch alignment constraint in that case.

v2: Use logical NOT (Sagar)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3f6db2c4e ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
2020-03-19 19:17:10 +00:00
Lionel Landwerlin
dab0aadea9 isl: properly filter supported display modifiers on Gen9+
Y tiling is supported for display on Gen9+ so don't filter it from the
possible flags.

v2: Drop Yf from display supported tilings on Gen12+ (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
2020-03-19 19:17:10 +00:00
Lionel Landwerlin
157a3cf3ec isl: implement linear tiling row pitch requirement for display
We're missing a requirement for alignment of row pitch for the display
HW. In linear tiling, the row pitch must be a 64bytes aligned.

v2: Use correct formula to align to 64bytes (Chad)

v3: Matching {} (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
2020-03-19 19:17:10 +00:00
Eric Anholt
f778c48869 ci: Only run the freedreno baremetal tests when freedreno/core changes.
Same as we do for a630 (docker) tests.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4229>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4229>
2020-03-19 17:21:24 +00:00
Dylan Baker
7524717ba2 docs/release-calendar: Add calendar for 20.1 Release candidates
It's time to start getting the calendar going for 20.1 so that everyone
is clear on when the close date for new features is. Eric Engstrom has
agreed to help out with the 20.1 series, and will be the primary point,
he's also helping out with a few of the 20.0.x point releases.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4077>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4077>
2020-03-19 09:26:11 -07:00
Rhys Perry
cf62c2b2ac radv: call nir_shader_gather_info again
pipeline-db (Navi, ACO):
Totals from affected shaders:
SGPRS: 11840 -> 11840 (0.00 %)
VGPRS: 19012 -> 19124 (0.59 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 3696 -> 3696 (0.00 %) dwords per thread
Code Size: 998680 -> 921388 (-7.74 %) bytes
LDS: 19646 -> 19646 (0.00 %) blocks
Max Waves: 3398 -> 3401 (0.09 %)

pipeline-db (Navi, LLVM):
Totals from affected shaders:
SGPRS: 17016 -> 17128 (0.66 %)
VGPRS: 19564 -> 14876 (-23.96 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 3872 -> 3872 (0.00 %) dwords per thread
Code Size: 820416 -> 743576 (-9.37 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 3367 -> 3534 (4.96 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4193>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4193>
2020-03-19 15:37:07 +00:00
Rhys Perry
5193688e1a nir/gather_info: handle emit_vertex_with_counter
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4193>
2020-03-19 15:37:07 +00:00
Tomasz Pyra
36ec3cbcf8 gallium/swr: spin-lock performance improvement
Currently, the worker threads are very aggresively
polling for new tasks. If the work is not constantly
fed into the pipeline (which is a case for most of
interactive applications), this creates unnecessary
memory pressure and is using CPU cycles that
could otherwise be used by the applications.
The change implements simple back off mechanism
to help with this problem

Change by Tomasz Pyra (tomasz.pyra@intel.com)

Reviewed-by: Alok Hota <alok.hota@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4226>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4226>
2020-03-19 11:11:26 +00:00
Pierre-Eric Pelloux-Prayer
db5cc6a7dd radeonsi: enable glsl_zero_init for Curse of the Dead Gods
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2598
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4214>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4214>
2020-03-19 08:47:09 +01:00
Marek Olšák
3c03718fd7 nir: fix clip/cull_distance_array_size in nir_lower_clip_cull_distance_arrays
This fixes a GPU hang on radeonsi.

It only works if optimizations have already been run.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4194>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4194>
2020-03-19 01:47:28 -04:00
Alyssa Rosenzweig
73812999d9 pan/bi: Pack BI_BLEND
MRT not yet supported to keep things easy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
a4fb88723e pan/bi: Flesh out BI_BLEND
It ingests the output of ATEST, whatever that actually is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
e06426ea85 pan/bi: Add ATEST packing
Only fp32 for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
b18d0ef708 pan/bi: Flesh out ATEST in IR
ATEST actually takes two sources and has a destination. Although the
details are a little funny, we should still model this correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
61260819ba pan/bi: Track clause types during scheduling
There's an easy mapping for this, so let's do it. Note we do this at
schedule-time instead of emit since we'll need to lookahead clause
types. The alternative is a prepass running after schedule but before
codegen, but there's no reason not to just stick it here when we're
preparing bi_clause in the first place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
e323df05a9 pan/bi: Don't hide SCHED_ADD inside HI_LATENCY
It makes bitwise property checking annoying.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
d797822d31 pan/bi: Pretty-print clause types in disassembler
Also note that type=1 is for load_vary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
42af9f47c8 pan/bi: Route through clause header
We already track almost all the information we need, let's dump it onto
the wire now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
d4fbf751cf pan/bi: Skip over data registers in port assignment
They bypass the usual mechanism entirely, let's add some props to
describe this and respect them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
32e5a7e6e9 pan/bi: Emit load_vary ops
Annoyingly long code to do so, but this should theoretically work for
both direct and indirect load_vary. Still need to handle destination.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
37f14c9e50 pan/bi: Pass second src for load_vary ops
For direct, this is just 0, but for indirct, this is a sample mask
preloaded in R61. Handle this at code emit time instead of trying to do
crazy monkeypatching later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
265169f48a pan/bi: Generalize bi_get_src a bit
Allow it to work with ADD ops and stub out some immediate fetching
infrastructure (currently only works with 0).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
1c0e786084 pan/bi: List ADD classes in bi_pack_add
Handling will be... somewhat tricky.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
6069904bbd pan/bi: Pack fadd32
Choo choo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
f2afcc6101 pan/bi: Pack BI_FMA ops
This is our first instruction we've emitted, requiring us to pipe
through registes/ports and various details from the IR. It's quite a bit
of code, but overall I'm happy with this structure. With some tedium we
should be able to emit the rest of the ALU ops this way, too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
8a3bf3f1a1 pan/bi: Add struct bifrost_fma_fma
So we can pack regular FMA ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
cd40e189b6 pan/bi: Model 3-bit Bifrost srcs in IR
We'll want to set these manually for schedule-time passthrough, as well
as use the enum for packing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
fe379776c7 pan/bi: Route through first_instruction field
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
90ca6a9a6b pan/bi: Assign registers to ports
Now that we can pack registers given the assigned ports, and we can
assign registers from the indices, the missing link is assigning ports
from the registers, and now finally we get some real data showing up in
a disassembly exercising lots of different code paths.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
ff39f57a48 pan/bi: Add missing __attribute__((packed))
That this code worked before makes me rather nervous...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
9080ea8b57 pan/bi: Pack register fields
Now that we have ctrl, the rest is natural... sorta.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
03a271bf15 pan/bi: Add packing for register control field
Filling in some gaps based on intuition from the bit patterns but this
should be vaguely right. More investigation needed down the line.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
50bce53cd0 pan/bi: Sketch out instruction word packing
Instructions are 78-bits with some seriously suspicious packing
requirements but hey, gotta save 'em bits.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Alyssa Rosenzweig
9269c85578 pan/bi: Setup initial clause packing
At the moment, we just iterate the clauses in the post-RA, post-sched IR
and generate a dummy clause corresponding, passing the results to the
disassembler to verify.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
2020-03-19 03:23:07 +00:00
Dylan Baker
0c5aab626b docs: update calendar, add news item, and link releases notes for 20.0.2
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
2020-03-18 22:47:06 +00:00
Dylan Baker
3c572fa571 docs/relnotes: Add sha256 sums for 20.0.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
2020-03-18 22:47:06 +00:00
Dylan Baker
552078aec6 Docs: Add release notes for 20.0.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
2020-03-18 22:47:06 +00:00
Eric Anholt
3210214b67 ci: Disable tests that showed intermittent fails on a530 in day 1.
Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2649
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
2020-03-18 22:17:53 +00:00
Eric Anholt
116a3ac481 ci: Ban the recent popular freedreno a630 flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
2020-03-18 22:17:53 +00:00
Samuel Pitoiset
56de6f698e radv: remove wrong assert that checks compute subgroup size
Ooops. For some reasons, I have been confused with Wave32 on GFX10,
but it's still possible to require a specific subgroup size if
only Wave64 is supported.

Fixes: 672d106199 ("radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4227>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4227>
2020-03-18 21:31:47 +00:00
Jason Ekstrand
46187bb54f anv: Swizzle fast-clear values
Starting with Gen12, we can fast-clear a lot more surface formats and we
are suddenly in the position of having to fast-clear surfaces with
formats with an implicit swizzle such as VK_FORMAT_R4G4B4A4_UNORM_PACK16
which is represented as ISL_FORMAT_A4B4G4R4 with a BGRA swizzle.  In
order for blorp to do the fast-clear color conversion for us, it needs
a properly swizzled color.

This fixes the following Vulkan CTS groups on TGL:

 - dEQP-VK.pipeline.blend.format.b4g4r4a4_unorm_pack16.*
 - dEQP-VK.api.image_clearing.core.clear_color_image.*.b4g4r4a4*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
2020-03-18 21:05:07 +00:00
Jason Ekstrand
3fb8f19481 intel/blorp: Add support for swizzling fast-clear colors
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
2020-03-18 21:05:07 +00:00
Ian Romanick
bf2eb3e0ee soft-fp64: Split a block that was missing a cast on a comparison
This function has code like:

   if (0x7FD <= zExp) {
      if ((0x7FD < zExp) ||
         ((zExp == 0x7FD) &&
            (0x001FFFFFu == zFrac0 && 0xFFFFFFFFu == zFrac1) &&
               increment)) {
         ...
	 return ...;
      }
      if (zExp < 0) {

I saw that, and I thought, "Uh... what?  Dead code?"  I thought it was a
bit fishy, so I grabbed the Berkeley SoftFloat Library 3e code, and
there is similar code in softfloat_roundPackToF64
(source/s_roundPackToF64.c), but it has an extra (uint16_t) cast in the
first comparison.  This is basicially a shortcut for

   if (zExp < 0 || zExp >= 0x7FD) {

So, having the nesting kind of makes sense. On a CPU, nesting the flow
control can be an optimization.  On a GPU, it's just fail.  Split the
block so that we don't need the uint16_t cast magic.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 683638 -> 658127 (-3.73%)
instructions in affected programs: 666839 -> 641328 (-3.83%)
helped: 92
HURT: 0
helped stats (abs) min: 26 max: 2456 x̄: 277.29 x̃: 144
helped stats (rel) min: 3.21% max: 4.22% x̄: 3.79% x̃: 3.90%
95% mean confidence interval for instructions value: -345.84 -208.75
95% mean confidence interval for instructions %-change: -3.86% -3.73%
Instructions are helped.

total cycles in shared programs: 5458858 -> 5344600 (-2.09%)
cycles in affected programs: 5360114 -> 5245856 (-2.13%)
helped: 92
HURT: 0
helped stats (abs) min: 126 max: 10300 x̄: 1241.93 x̃: 655
helped stats (rel) min: 1.71% max: 2.37% x̄: 2.12% x̃: 2.17%
95% mean confidence interval for cycles value: -1539.93 -943.94
95% mean confidence interval for cycles %-change: -2.16% -2.08%
Cycles are helped.

Fixes: f111d72596 ("glsl: Add "built-in" functions to do add(fp64, fp64)")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
a8882132f9 soft-fp64/fadd: Common code optimization for differing sign case
This is basically the same ideas from the previous 4 commits applied
to the aSign != bSign part... and all smashed into one commit.

The shader hurt for spill and / or fills is from
KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake
total instructions in shared programs: 787258 -> 683638 (-13.16%)
instructions in affected programs: 725435 -> 621815 (-14.28%)
helped: 74
HURT: 0
helped stats (abs) min: 152 max: 10261 x̄: 1400.27 x̃: 975
helped stats (rel) min: 11.61% max: 20.92% x̄: 15.40% x̃: 14.86%
95% mean confidence interval for instructions value: -1740.11 -1060.43
95% mean confidence interval for instructions %-change: -16.01% -14.79%
Instructions are helped.

total cycles in shared programs: 6483227 -> 5458858 (-15.80%)
cycles in affected programs: 6051245 -> 5026876 (-16.93%)
helped: 74
HURT: 0
helped stats (abs) min: 1566 max: 95474 x̄: 13842.82 x̃: 9757
helped stats (rel) min: 13.94% max: 23.26% x̄: 17.98% x̃: 17.57%
95% mean confidence interval for cycles value: -17104.25 -10581.40
95% mean confidence interval for cycles %-change: -18.61% -17.35%
Cycles are helped.

total spills in shared programs: 553 -> 445 (-19.53%)
spills in affected programs: 553 -> 445 (-19.53%)
helped: 1
HURT: 0

total fills in shared programs: 1307 -> 1323 (1.22%)
fills in affected programs: 1307 -> 1323 (1.22%)
helped: 0
HURT: 1

Ice Lake
total instructions in shared programs: 781216 -> 678470 (-13.15%)
instructions in affected programs: 720088 -> 617342 (-14.27%)
helped: 74
HURT: 0
helped stats (abs) min: 153 max: 8863 x̄: 1388.46 x̃: 975
helped stats (rel) min: 11.24% max: 21.03% x̄: 15.47% x̃: 15.01%
95% mean confidence interval for instructions value: -1703.57 -1073.35
95% mean confidence interval for instructions %-change: -16.09% -14.85%
Instructions are helped.

total cycles in shared programs: 6464085 -> 5453997 (-15.63%)
cycles in affected programs: 6031771 -> 5021683 (-16.75%)
helped: 74
HURT: 0
helped stats (abs) min: 1552 max: 90317 x̄: 13649.84 x̃: 9650
helped stats (rel) min: 13.84% max: 23.11% x̄: 17.83% x̃: 17.41%
95% mean confidence interval for cycles value: -16802.89 -10496.79
95% mean confidence interval for cycles %-change: -18.46% -17.21%
Cycles are helped.

total spills in shared programs: 279 -> 368 (31.90%)
spills in affected programs: 279 -> 368 (31.90%)
helped: 0
HURT: 1

total fills in shared programs: 973 -> 1155 (18.71%)
fills in affected programs: 973 -> 1155 (18.71%)
helped: 0
HURT: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
2d1216a039 soft-fp64/fadd: Move common code out of both branches of an if-statement
The previous two commits were just setting the scene for this change.

The mix(..., __propagateFloat64NaN(a, b), propagate) statements are not
identical in the two halves, but they are equivalent.  The first clause
of the mix in the else-branch is trivally ±Inf.  The first clause in the
then-branch __packFloat64(aSign, aExp, aFracHi, aFracLo).  The
preceeding conditions prove that aExp=0x7ff, aFracHi=0, and aFracLo=0.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 819560 -> 787258 (-3.94%)
instructions in affected programs: 757737 -> 725435 (-4.26%)
helped: 74
HURT: 0
helped stats (abs) min: 43 max: 3545 x̄: 436.51 x̃: 296
helped stats (rel) min: 3.54% max: 6.16% x̄: 4.52% x̃: 4.36%
95% mean confidence interval for instructions value: -548.42 -324.61
95% mean confidence interval for instructions %-change: -4.68% -4.37%
Instructions are helped.

total cycles in shared programs: 6817254 -> 6483227 (-4.90%)
cycles in affected programs: 6385272 -> 6051245 (-5.23%)
helped: 74
HURT: 0
helped stats (abs) min: 430 max: 33271 x̄: 4513.88 x̃: 3047
helped stats (rel) min: 4.28% max: 7.45% x̄: 5.48% x̃: 5.31%
95% mean confidence interval for cycles value: -5610.46 -3417.30
95% mean confidence interval for cycles %-change: -5.65% -5.32%
Cycles are helped.

total spills in shared programs: 591 -> 553 (-6.43%)
spills in affected programs: 591 -> 553 (-6.43%)
helped: 1
HURT: 0

total fills in shared programs: 1353 -> 1307 (-3.40%)
fills in affected programs: 1353 -> 1307 (-3.40%)
helped: 1
HURT: 0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
16dfd06472 soft-fp64/fadd: Use absolute value of expDiff
In one branch we know that expDiff is already positive.

In the other branch we know the expDiff is negative.  Previously in that
branch the code was -(expDiff + 1).  This is equvialent to (-expDiff) -
1, and since expDiff is negative, abs(expDiff) - 1.

The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 818246 -> 819560 (0.16%)
instructions in affected programs: 756423 -> 757737 (0.17%)
helped: 1
HURT: 73
helped stats (abs) min: 1205 max: 1205 x̄: 1205.00 x̃: 1205
helped stats (rel) min: 1.36% max: 1.36% x̄: 1.36% x̃: 1.36%
HURT stats (abs)   min: 2 max: 149 x̄: 34.51 x̃: 27
HURT stats (rel)   min: 0.14% max: 1.09% x̄: 0.41% x̃: 0.30%
95% mean confidence interval for instructions value: -16.56 52.07
95% mean confidence interval for instructions %-change: 0.30% 0.47%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 6816686 -> 6817254 (<.01%)
cycles in affected programs: 6384704 -> 6385272 (<.01%)
helped: 37
HURT: 37
helped stats (abs) min: 30 max: 5790 x̄: 289.05 x̃: 102
helped stats (rel) min: 0.04% max: 0.86% x̄: 0.29% x̃: 0.31%
HURT stats (abs)   min: 2 max: 1020 x̄: 304.41 x̃: 232
HURT stats (rel)   min: <.01% max: 1.58% x̄: 0.55% x̃: 0.43%
95% mean confidence interval for cycles value: -165.37 180.72
95% mean confidence interval for cycles %-change: <.01% 0.27%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 705 -> 591 (-16.17%)
spills in affected programs: 705 -> 591 (-16.17%)
helped: 1
HURT: 0

total fills in shared programs: 1501 -> 1353 (-9.86%)
fills in affected programs: 1501 -> 1353 (-9.86%)
helped: 1
HURT: 0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
da3fa01891 soft-fp64/fadd: Rename aFrac and bFrac variables
Exchanging aFracHi / bFracHi and aFracLo / bFracLo should not affect the
result of the later call to __add64.

The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

v2: Fix a typo in a comment.  Noticed by Matt.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 812094 -> 818246 (0.76%)
instructions in affected programs: 750271 -> 756423 (0.82%)
helped: 0
HURT: 74
HURT stats (abs)   min: 7 max: 520 x̄: 83.14 x̃: 59
HURT stats (rel)   min: 0.52% max: 1.48% x̄: 0.89% x̃: 0.84%
95% mean confidence interval for instructions value: 63.96 102.31
95% mean confidence interval for instructions %-change: 0.83% 0.95%
Instructions are HURT.

total cycles in shared programs: 6797157 -> 6816686 (0.29%)
cycles in affected programs: 6365175 -> 6384704 (0.31%)
helped: 0
HURT: 74
HURT stats (abs)   min: 16 max: 1690 x̄: 263.91 x̃: 181
HURT stats (rel)   min: 0.14% max: 0.68% x̄: 0.32% x̃: 0.27%
95% mean confidence interval for cycles value: 199.74 328.07
95% mean confidence interval for cycles %-change: 0.29% 0.36%
Cycles are HURT.

total spills in shared programs: 703 -> 705 (0.28%)
spills in affected programs: 703 -> 705 (0.28%)
helped: 0
HURT: 1

total fills in shared programs: 1499 -> 1501 (0.13%)
fills in affected programs: 1499 -> 1501 (0.13%)
helped: 0
HURT: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
3c9ff97215 soft-fp64/fadd: Combine an if-statement into the preceeding else-clause
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 812590 -> 812094 (-0.06%)
instructions in affected programs: 672135 -> 671639 (-0.07%)
helped: 57
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 8.70 x̃: 7
helped stats (rel) min: <.01% max: 0.49% x̄: 0.12% x̃: 0.09%
95% mean confidence interval for instructions value: -10.46 -6.94
95% mean confidence interval for instructions %-change: -0.15% -0.09%
Instructions are helped.

total cycles in shared programs: 6798039 -> 6797157 (-0.01%)
cycles in affected programs: 5810059 -> 5809177 (-0.02%)
helped: 54
HURT: 2
helped stats (abs) min: 2 max: 68 x̄: 16.44 x̃: 12
helped stats (rel) min: <.01% max: 0.12% x̄: 0.03% x̃: 0.02%
HURT stats (abs)   min: 2 max: 4 x̄: 3.00 x̃: 3
HURT stats (rel)   min: <.01% max: <.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -19.50 -12.00
95% mean confidence interval for cycles %-change: -0.03% -0.02%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
480565812c soft-fp64/fadd: Reformat after previous commit
Convert

   } else if (...) {
      ...
   } else {
      ...
   }

to

   } else {
      if (...) {
         ...
      } else {
         ...
      }
   }

Not doing this reformatting in the previous commit makes the previous
commit easier to review, and doing it before the next commit makes the
next commit easier to review.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
9496a67eec soft-fp64/fadd: Delete a redundant condition check
Previous condition checks already guaranteen that expDiff != 0 and
!(expDiff > 0), so expDiff < 0 is the only option left.

The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 815491 -> 812590 (-0.36%)
instructions in affected programs: 753668 -> 750767 (-0.38%)
helped: 74
HURT: 0
helped stats (abs) min: 3 max: 281 x̄: 39.20 x̃: 25
helped stats (rel) min: 0.29% max: 0.73% x̄: 0.42% x̃: 0.40%
95% mean confidence interval for instructions value: -48.50 -29.91
95% mean confidence interval for instructions %-change: -0.45% -0.40%
Instructions are helped.

total cycles in shared programs: 6813681 -> 6798039 (-0.23%)
cycles in affected programs: 6381699 -> 6366057 (-0.25%)
helped: 74
HURT: 0
helped stats (abs) min: 24 max: 1488 x̄: 211.38 x̃: 149
helped stats (rel) min: 0.20% max: 0.44% x̄: 0.26% x̃: 0.25%
95% mean confidence interval for cycles value: -261.68 -161.08
95% mean confidence interval for cycles %-change: -0.28% -0.25%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
7078105592 soft-fp64/fadd: Just let the subtraction happen when the result will be zero
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 815717 -> 815491 (-0.03%)
instructions in affected programs: 735489 -> 735263 (-0.03%)
helped: 39
HURT: 34
helped stats (abs) min: 2 max: 192 x̄: 20.79 x̃: 12
helped stats (rel) min: 0.01% max: 0.46% x̄: 0.26% x̃: 0.28%
HURT stats (abs)   min: 1 max: 65 x̄: 17.21 x̃: 11
HURT stats (rel)   min: <.01% max: 1.11% x̄: 0.35% x̃: 0.19%
95% mean confidence interval for instructions value: -10.40 4.21
95% mean confidence interval for instructions %-change: -0.07% 0.13%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 6820707 -> 6813681 (-0.10%)
cycles in affected programs: 6388725 -> 6381699 (-0.11%)
helped: 51
HURT: 23
helped stats (abs) min: 3 max: 1837 x̄: 184.76 x̃: 120
helped stats (rel) min: <.01% max: 0.48% x̄: 0.25% x̃: 0.25%
HURT stats (abs)   min: 18 max: 216 x̄: 104.22 x̃: 98
HURT stats (rel)   min: 0.06% max: 0.73% x̄: 0.31% x̃: 0.11%
95% mean confidence interval for cycles value: -154.67 -35.22
95% mean confidence interval for cycles %-change: -0.15% <.01%
Inconclusive result (%-change mean confidence interval includes 0).

total spills in shared programs: 702 -> 703 (0.14%)
spills in affected programs: 702 -> 703 (0.14%)
helped: 0
HURT: 1

total fills in shared programs: 1497 -> 1499 (0.13%)
fills in affected programs: 1497 -> 1499 (0.13%)
helped: 0
HURT: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
cae36fa217 soft-fp64/fadd: Pick zero or non-zero result based on subtraction result
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 817327 -> 815717 (-0.20%)
instructions in affected programs: 755504 -> 753894 (-0.21%)
helped: 73
HURT: 1
helped stats (abs) min: 1 max: 159 x̄: 22.12 x̃: 14
helped stats (rel) min: 0.05% max: 0.40% x̄: 0.22% x̃: 0.23%
HURT stats (abs)   min: 5 max: 5 x̄: 5.00 x̃: 5
HURT stats (rel)   min: 0.07% max: 0.07% x̄: 0.07% x̃: 0.07%
95% mean confidence interval for instructions value: -27.27 -16.24
95% mean confidence interval for instructions %-change: -0.24% -0.20%
Instructions are helped.

total cycles in shared programs: 6822826 -> 6820707 (-0.03%)
cycles in affected programs: 6390844 -> 6388725 (-0.03%)
helped: 71
HURT: 3
helped stats (abs) min: 2 max: 537 x̄: 30.72 x̃: 18
helped stats (rel) min: <.01% max: 0.08% x̄: 0.03% x̃: 0.03%
HURT stats (abs)   min: 10 max: 32 x̄: 20.67 x̃: 20
HURT stats (rel)   min: 0.01% max: 0.02% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for cycles value: -43.41 -13.86
95% mean confidence interval for cycles %-change: -0.04% -0.03%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
70be98f17a soft-fp64/fadd: Massively split the live range of zFrac0 and zFrac1
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 822766 -> 817327 (-0.66%)
instructions in affected programs: 760943 -> 755504 (-0.71%)
helped: 74
HURT: 0
helped stats (abs) min: 8 max: 515 x̄: 73.50 x̃: 51
helped stats (rel) min: 0.58% max: 1.10% x̄: 0.77% x̃: 0.73%
95% mean confidence interval for instructions value: -91.17 -55.83
95% mean confidence interval for instructions %-change: -0.81% -0.74%
Instructions are helped.

total cycles in shared programs: 6816791 -> 6822826 (0.09%)
cycles in affected programs: 6384809 -> 6390844 (0.09%)
helped: 0
HURT: 74
HURT stats (abs)   min: 6 max: 1179 x̄: 81.55 x̃: 50
HURT stats (rel)   min: 0.02% max: 0.17% x̄: 0.09% x̃: 0.09%
95% mean confidence interval for cycles value: 48.99 114.12
95% mean confidence interval for cycles %-change: 0.09% 0.10%
Cycles are HURT.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
73fa3a1ca4 soft-fp64/fadd: Instead of tracking "b < a", track sign of the difference
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 824403 -> 822766 (-0.20%)
instructions in affected programs: 756260 -> 754623 (-0.22%)
helped: 68
HURT: 1
helped stats (abs) min: 1 max: 118 x̄: 26.26 x̃: 18
helped stats (rel) min: 0.02% max: 0.97% x̄: 0.31% x̃: 0.23%
HURT stats (abs)   min: 149 max: 149 x̄: 149.00 x̃: 149
HURT stats (rel)   min: 0.17% max: 0.17% x̄: 0.17% x̃: 0.17%
95% mean confidence interval for instructions value: -31.94 -15.51
95% mean confidence interval for instructions %-change: -0.37% -0.23%
Instructions are helped.

total cycles in shared programs: 6828935 -> 6816791 (-0.18%)
cycles in affected programs: 6385191 -> 6373047 (-0.19%)
helped: 73
HURT: 0
helped stats (abs) min: 2 max: 852 x̄: 166.36 x̃: 120
helped stats (rel) min: <.01% max: 0.80% x̄: 0.22% x̃: 0.17%
95% mean confidence interval for cycles value: -210.80 -121.91
95% mean confidence interval for cycles %-change: -0.27% -0.17%
Cycles are helped.

total fills in shared programs: 1442 -> 1497 (3.81%)
fills in affected programs: 1442 -> 1497 (3.81%)
helped: 0
HURT: 1

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
5b07f542e5 soft-fp64: Optimize __fmin64 and __fmax64 by using different evaluation order [v2]
v2: Go to extra effort to avoid flow control inserted to implement
short-circuit evaluation rules.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 797779 -> 796849 (-0.12%)
instructions in affected programs: 3499 -> 2569 (-26.58%)
helped: 21
HURT: 0
helped stats (abs) min: 8 max: 112 x̄: 44.29 x̃: 44
helped stats (rel) min: 16.09% max: 33.15% x̄: 25.72% x̃: 24.62%
95% mean confidence interval for instructions value: -55.94 -32.63
95% mean confidence interval for instructions %-change: -28.14% -23.30%
Instructions are helped.

total cycles in shared programs: 6601355 -> 6588351 (-0.20%)
cycles in affected programs: 25376 -> 12372 (-51.25%)
helped: 21
HURT: 0
helped stats (abs) min: 156 max: 1410 x̄: 619.24 x̃: 526
helped stats (rel) min: 42.39% max: 53.98% x̄: 50.12% x̃: 50.75%
95% mean confidence interval for cycles value: -776.58 -461.89
95% mean confidence interval for cycles %-change: -51.57% -48.67%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
617a69107e soft-fp64/ffloor: Simplify the >= 0 comparison
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 797951 -> 797779 (-0.02%)
instructions in affected programs: 126482 -> 126310 (-0.14%)
helped: 15
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 11.47 x̃: 10
helped stats (rel) min: <.01% max: 0.60% x̄: 0.28% x̃: 0.29%
95% mean confidence interval for instructions value: -14.79 -8.14
95% mean confidence interval for instructions %-change: -0.40% -0.16%
Instructions are helped.

total cycles in shared programs: 6601437 -> 6601355 (<.01%)
cycles in affected programs: 1089336 -> 1089254 (<.01%)
helped: 15
HURT: 0
helped stats (abs) min: 2 max: 12 x̄: 5.47 x̃: 6
helped stats (rel) min: <.01% max: 0.04% x̄: 0.01% x̃: 0.01%
95% mean confidence interval for cycles value: -7.06 -3.87
95% mean confidence interval for cycles %-change: -0.02% <.01%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
abf28d6a70 soft-fp64: Relax the way NaN is propagated
Also reassociate a couple expressions to encourage some CSE.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 813599 -> 797951 (-1.92%)
instructions in affected programs: 796110 -> 780462 (-1.97%)
helped: 92
HURT: 0
helped stats (abs) min: 3 max: 5198 x̄: 170.09 x̃: 83
helped stats (rel) min: 0.36% max: 5.50% x̄: 1.57% x̃: 1.40%
95% mean confidence interval for instructions value: -282.42 -57.75
95% mean confidence interval for instructions %-change: -1.71% -1.42%
Instructions are helped.

total cycles in shared programs: 6687128 -> 6601437 (-1.28%)
cycles in affected programs: 6582246 -> 6496555 (-1.30%)
helped: 92
HURT: 0
helped stats (abs) min: 36 max: 14442 x̄: 931.42 x̃: 592
helped stats (rel) min: 0.45% max: 3.16% x̄: 1.44% x̃: 1.23%
95% mean confidence interval for cycles value: -1257.58 -605.27
95% mean confidence interval for cycles %-change: -1.58% -1.30%
Cycles are helped.

total spills in shared programs: 759 -> 702 (-7.51%)
spills in affected programs: 759 -> 702 (-7.51%)
helped: 3
HURT: 0

total fills in shared programs: 2412 -> 1442 (-40.22%)
fills in affected programs: 2412 -> 1442 (-40.22%)
helped: 3
HURT: 0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
8178fa8876 soft-fp64/fsat: Micro-optimize x >= 1 test
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841590 -> 841332 (-0.03%)
instructions in affected programs: 121957 -> 121699 (-0.21%)
helped: 7
HURT: 0
helped stats (abs) min: 15 max: 54 x̄: 36.86 x̃: 41
helped stats (rel) min: 0.16% max: 0.33% x̄: 0.23% x̃: 0.18%
95% mean confidence interval for instructions value: -49.73 -23.98
95% mean confidence interval for instructions %-change: -0.29% -0.16%
Instructions are helped.

total cycles in shared programs: 6926828 -> 6923967 (-0.04%)
cycles in affected programs: 1038569 -> 1035708 (-0.28%)
helped: 7
HURT: 0
helped stats (abs) min: 128 max: 616 x̄: 408.71 x̃: 446
helped stats (rel) min: 0.18% max: 0.44% x̄: 0.29% x̃: 0.22%
95% mean confidence interval for cycles value: -571.72 -245.70
95% mean confidence interval for cycles %-change: -0.38% -0.19%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
b6f58b4709 soft-fp64/fsat: Micro-optimize x < 0 test
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841647 -> 841590 (<.01%)
instructions in affected programs: 122014 -> 121957 (-0.05%)
helped: 7
HURT: 0
helped stats (abs) min: 3 max: 12 x̄: 8.14 x̃: 9
helped stats (rel) min: 0.04% max: 0.07% x̄: 0.05% x̃: 0.04%
95% mean confidence interval for instructions value: -11.23 -5.06
95% mean confidence interval for instructions %-change: -0.06% -0.03%
Instructions are helped.

total cycles in shared programs: 6926904 -> 6926828 (<.01%)
cycles in affected programs: 1038645 -> 1038569 (<.01%)
helped: 7
HURT: 0
helped stats (abs) min: 4 max: 16 x̄: 10.86 x̃: 12
helped stats (rel) min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -14.97 -6.74
95% mean confidence interval for cycles %-change: -0.01% <.01%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
7673dcbd21 soft-fp64/fsat: Correctly handle NaN
fsat is defined as min(max(a, 0.0), 1.0), and IEEE defines both min and
max to return the non-NaN value when one value is NaN.  Based on this,
fsat should definitely return 0.0 for NaN.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841666 -> 841647 (<.01%)
instructions in affected programs: 122033 -> 122014 (-0.02%)
helped: 7
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.71 x̃: 3
helped stats (rel) min: 0.01% max: 0.02% x̄: 0.02% x̃: 0.01%
95% mean confidence interval for instructions value: -3.74 -1.69
95% mean confidence interval for instructions %-change: -0.02% -0.01%
Instructions are helped.

total cycles in shared programs: 6927246 -> 6926904 (<.01%)
cycles in affected programs: 1038987 -> 1038645 (-0.03%)
helped: 7
HURT: 0
helped stats (abs) min: 18 max: 72 x̄: 48.86 x̃: 54
helped stats (rel) min: 0.03% max: 0.05% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -67.38 -30.33
95% mean confidence interval for cycles %-change: -0.05% -0.02%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: a42163cbbc ("compiler: Add lowering support for 64-bit saturate operations to software")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
b421c0466d soft-fp64/flt: Perform checks in a different order
The change to nir_opt_algebraic cleans up a pattern that was never
produced before the rest of this commit was added.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 843005 -> 841666 (-0.16%)
instructions in affected programs: 460655 -> 459316 (-0.29%)
helped: 64
HURT: 17
helped stats (abs) min: 1 max: 72 x̄: 21.72 x̃: 20
helped stats (rel) min: 0.01% max: 28.07% x̄: 12.67% x̃: 16.07%
HURT stats (abs)   min: 1 max: 7 x̄: 3.00 x̃: 2
HURT stats (rel)   min: 0.01% max: 0.04% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -20.87 -12.19
95% mean confidence interval for instructions %-change: -12.35% -7.66%
Instructions are helped.

total cycles in shared programs: 6944998 -> 6927246 (-0.26%)
cycles in affected programs: 3891872 -> 3874120 (-0.46%)
helped: 71
HURT: 10
helped stats (abs) min: 2 max: 772 x̄: 254.21 x̃: 156
helped stats (rel) min: <.01% max: 66.44% x̄: 21.72% x̃: 18.40%
HURT stats (abs)   min: 18 max: 69 x̄: 29.70 x̃: 20
HURT stats (rel)   min: 0.02% max: 0.04% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -270.82 -167.50
95% mean confidence interval for cycles %-change: -24.41% -13.65%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
f6992bf624 soft-fp64/fneg: Don't treat NaN specially
__fabs64 doesn't do anything special, and the value is still NaN
regardless of the value of the MSB.  In a strict sense, it's possible
that both functions should set the "signal" bit.

lts on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 844558 -> 843005 (-0.18%)
instructions in affected programs: 725975 -> 724422 (-0.21%)
helped: 53
HURT: 4
helped stats (abs) min: 1 max: 313 x̄: 29.87 x̃: 21
helped stats (rel) min: 0.01% max: 0.94% x̄: 0.30% x̃: 0.22%
HURT stats (abs)   min: 4 max: 11 x̄: 7.50 x̃: 7
HURT stats (rel)   min: 0.03% max: 0.09% x̄: 0.05% x̃: 0.04%
95% mean confidence interval for instructions value: -39.02 -15.47
95% mean confidence interval for instructions %-change: -0.34% -0.21%
Instructions are helped.

total cycles in shared programs: 6962024 -> 6944998 (-0.24%)
cycles in affected programs: 6185470 -> 6168444 (-0.28%)
helped: 59
HURT: 0
helped stats (abs) min: 64 max: 2863 x̄: 288.58 x̃: 208
helped stats (rel) min: 0.11% max: 0.87% x̄: 0.33% x̃: 0.27%
95% mean confidence interval for cycles value: -387.15 -190.00
95% mean confidence interval for cycles %-change: -0.38% -0.28%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
de4acd8816 soft-fp64: Store sign value as 0 or 0x80000000
...instead of 0 or 1.  Many places the sign bit is extracted, then later
put back in the same position.  This saves some left-shift operations.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 848106 -> 844558 (-0.42%)
instructions in affected programs: 833480 -> 829932 (-0.43%)
helped: 106
HURT: 1
helped stats (abs) min: 1 max: 995 x̄: 33.48 x̃: 12
helped stats (rel) min: 0.15% max: 2.20% x̄: 0.60% x̃: 0.35%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: <.01% max: <.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for instructions value: -51.88 -14.43
95% mean confidence interval for instructions %-change: -0.71% -0.47%
Instructions are helped.

total cycles in shared programs: 6969125 -> 6962024 (-0.10%)
cycles in affected programs: 6717689 -> 6710588 (-0.11%)
helped: 78
HURT: 7
helped stats (abs) min: 2 max: 2083 x̄: 110.27 x̃: 56
helped stats (rel) min: <.01% max: 0.30% x̄: 0.11% x̃: 0.11%
HURT stats (abs)   min: 2 max: 1340 x̄: 214.29 x̃: 4
HURT stats (rel)   min: 0.01% max: 0.71% x̄: 0.13% x̃: 0.02%
95% mean confidence interval for cycles value: -144.02 -23.06
95% mean confidence interval for cycles %-change: -0.12% -0.07%
Cycles are helped.

total spills in shared programs: 814 -> 759 (-6.76%)
spills in affected programs: 814 -> 759 (-6.76%)
helped: 2
HURT: 1

total fills in shared programs: 2488 -> 2412 (-3.05%)
fills in affected programs: 2488 -> 2412 (-3.05%)
helped: 2
HURT: 1

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
598e2fc6a1 soft-fp64: Pick a single idiom for treating sign value as a Boolean
Replace all of the bool(qSign) with qSign != 0u.  Remove unnecessary
parenthesis from around most of the existing qSign != 0u.

This dramatically simplifies the next commit.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 848109 -> 848106 (<.01%)
instructions in affected programs: 53 -> 50 (-5.66%)
helped: 1
HURT: 0

total cycles in shared programs: 6969145 -> 6969125 (<.01%)
cycles in affected programs: 396 -> 376 (-5.05%)
helped: 1
HURT: 0

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
325a21f5eb soft-fp64: Simplify __countLeadingZeros32 function
findMSB returns -1 for an input of zero, so 31 - findMSB(a) is
sufficient on its own.

There's only one user of findMSB in shader-db, and it does not match
this pattern.

TODO: Add a pattern in the backend code generator that emits 31 -
nir_op_ufind_msb(a) as if it were nir_op_uclz.  That should save a couple
instructions.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 859509 -> 848109 (-1.33%)
instructions in affected programs: 841058 -> 829658 (-1.36%)
helped: 97
HURT: 0
helped stats (abs) min: 3 max: 1161 x̄: 117.53 x̃: 72
helped stats (rel) min: 0.98% max: 6.74% x̄: 1.70% x̃: 1.35%
95% mean confidence interval for instructions value: -147.21 -87.84
95% mean confidence interval for instructions %-change: -1.94% -1.46%
Instructions are helped.

total cycles in shared programs: 7072275 -> 6969145 (-1.46%)
cycles in affected programs: 6955767 -> 6852637 (-1.48%)
helped: 97
HURT: 0
helped stats (abs) min: 32 max: 10900 x̄: 1063.20 x̃: 560
helped stats (rel) min: 1.18% max: 7.58% x̄: 1.84% x̃: 1.45%
95% mean confidence interval for cycles value: -1339.43 -786.96
95% mean confidence interval for cycles %-change: -2.11% -1.57%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
812230fd94 soft-fp64: Don't open-code umulExtended
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 928859 -> 859509 (-7.47%)
instructions in affected programs: 866293 -> 796943 (-8.01%)
helped: 76
HURT: 0
helped stats (abs) min: 75 max: 8042 x̄: 912.50 x̃: 688
helped stats (rel) min: 5.35% max: 21.02% x̄: 10.35% x̃: 7.58%
95% mean confidence interval for instructions value: -1138.37 -686.63
95% mean confidence interval for instructions %-change: -11.69% -9.00%
Instructions are helped.

total cycles in shared programs: 7272912 -> 7072275 (-2.76%)
cycles in affected programs: 6763486 -> 6562849 (-2.97%)
helped: 76
HURT: 0
helped stats (abs) min: 214 max: 30136 x̄: 2639.96 x̃: 1923
helped stats (rel) min: 1.75% max: 9.20% x̄: 4.04% x̃: 2.41%
95% mean confidence interval for cycles value: -3455.29 -1824.63
95% mean confidence interval for cycles %-change: -4.69% -3.39%
Cycles are helped.

total spills in shared programs: 817 -> 814 (-0.37%)
spills in affected programs: 791 -> 788 (-0.38%)
helped: 2
HURT: 0

total fills in shared programs: 2438 -> 2488 (2.05%)
fills in affected programs: 2392 -> 2442 (2.09%)
helped: 0
HURT: 2

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
d1e0227ef1 soft-fp64/b2f: Reimplement using bitwise logic ops
This doesn't help a lot of shaders, but it helps those few a LOT.

This could also be implemented using bcsel.  That version is very
slightly worse because the generated SEL instruction wants to have two
immediate sources, so one of them usually needs an extra MOV instruction
to load.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 929619 -> 928859 (-0.08%)
instructions in affected programs: 1651 -> 891 (-46.03%)
helped: 8
HURT: 0
helped stats (abs) min: 38 max: 152 x̄: 95.00 x̃: 95
helped stats (rel) min: 42.70% max: 86.36% x̄: 49.88% x̃: 44.66%
95% mean confidence interval for instructions value: -132.97 -57.03
95% mean confidence interval for instructions %-change: -62.28% -37.49%
Instructions are helped.

total cycles in shared programs: 7280180 -> 7272912 (-0.10%)
cycles in affected programs: 12960 -> 5692 (-56.08%)
helped: 8
HURT: 0
helped stats (abs) min: 352 max: 1456 x̄: 908.50 x̃: 910
helped stats (rel) min: 52.45% max: 91.19% x̄: 59.24% x̃: 55.15%
95% mean confidence interval for cycles value: -1274.03 -542.97
95% mean confidence interval for cycles %-change: -70.06% -48.41%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
4e3d69ad07 nir/algebraic: Simplify a contradiction that can occur in __flt64_nonnan
The pattern is added to opt_algebraic because, for example, comparisons
with constant 0.0 will produce (a1 < 0).

Even with a pass that optimized Boolean expressions, I think this would
be very difficult to automatically recognize and optimize.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 933054 -> 929619 (-0.37%)
instructions in affected programs: 784041 -> 780606 (-0.44%)
helped: 59
HURT: 0
helped stats (abs) min: 2 max: 213 x̄: 58.22 x̃: 44
helped stats (rel) min: 0.02% max: 2.51% x̄: 0.72% x̃: 0.46%
95% mean confidence interval for instructions value: -70.80 -45.64
95% mean confidence interval for instructions %-change: -0.92% -0.53%
Instructions are helped.

total cycles in shared programs: 7304712 -> 7280180 (-0.34%)
cycles in affected programs: 7176260 -> 7151728 (-0.34%)
helped: 92
HURT: 0
helped stats (abs) min: 8 max: 1414 x̄: 266.65 x̃: 166
helped stats (rel) min: 0.04% max: 2.34% x̄: 0.43% x̃: 0.22%
95% mean confidence interval for cycles value: -333.05 -200.26
95% mean confidence interval for cycles %-change: -0.54% -0.31%
Cycles are helped.

Regular shader-db changes:

No changes on any Intel platform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
e0cefc5a23 nir/algebraic: Constant reassociation for bitwise operations too
Like 5886cd79a0, but for iand, ior, and ixor.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake
total instructions in shared programs: 903108 -> 902830 (-0.03%)
instructions in affected programs: 654910 -> 654632 (-0.04%)
helped: 31
HURT: 5
helped stats (abs) min: 2 max: 31 x̄: 9.58 x̃: 7
helped stats (rel) min: 0.01% max: 0.23% x̄: 0.06% x̃: 0.04%
HURT stats (abs)   min: 1 max: 10 x̄: 3.80 x̃: 3
HURT stats (rel)   min: 0.01% max: 0.10% x̄: 0.03% x̃: 0.02%
95% mean confidence interval for instructions value: -10.55 -4.89
95% mean confidence interval for instructions %-change: -0.07% -0.03%
Instructions are helped.

total cycles in shared programs: 7059681 -> 7058006 (-0.02%)
cycles in affected programs: 5081309 -> 5079634 (-0.03%)
helped: 33
HURT: 12
helped stats (abs) min: 1 max: 444 x̄: 60.91 x̃: 18
helped stats (rel) min: <.01% max: 2.17% x̄: 0.25% x̃: 0.05%
HURT stats (abs)   min: 1 max: 288 x̄: 27.92 x̃: 2
HURT stats (rel)   min: <.01% max: 1.00% x̄: 0.23% x̃: 0.02%
95% mean confidence interval for cycles value: -68.32 -6.12
95% mean confidence interval for cycles %-change: -0.28% 0.03%
Inconclusive result (%-change mean confidence interval includes 0).

Ice Lake
total instructions in shared programs: 895384 -> 895159 (-0.03%)
instructions in affected programs: 658678 -> 658453 (-0.03%)
helped: 37
HURT: 0
helped stats (abs) min: 3 max: 16 x̄: 6.08 x̃: 4
helped stats (rel) min: <.01% max: 0.07% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for instructions value: -7.46 -4.70
95% mean confidence interval for instructions %-change: -0.04% -0.03%
Instructions are helped.

total cycles in shared programs: 7092224 -> 7091195 (-0.01%)
cycles in affected programs: 5221666 -> 5220637 (-0.02%)
helped: 35
HURT: 11
helped stats (abs) min: 1 max: 247 x̄: 43.46 x̃: 12
helped stats (rel) min: <.01% max: 2.17% x̄: 0.23% x̃: 0.05%
HURT stats (abs)   min: 2 max: 432 x̄: 44.73 x̃: 5
HURT stats (rel)   min: <.01% max: 1.00% x̄: 0.25% x̃: 0.02%
95% mean confidence interval for cycles value: -49.00 4.26
95% mean confidence interval for cycles %-change: -0.27% 0.03%
Inconclusive result (value mean confidence interval includes 0).

Regular shader-db results:

All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 17611408 -> 17611398 (<.01%)
instructions in affected programs: 1648 -> 1638 (-0.61%)
helped: 2
HURT: 0

total cycles in shared programs: 338366148 -> 338366124 (<.01%)
cycles in affected programs: 124048 -> 124024 (-0.02%)
helped: 2
HURT: 0

No changes on any earlier Intel platforms.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
1d36af9338 nir/algebraic: Generalize some and-of-shift-right patterns [v2]
Generalizes some of the patterns from 76289fbfa8 and 905ff86198.  In
particular, some of the soft-fp64 code generates (a & 0x7fffffff) << 1
when constant 0.0 is compared (flt or feq).

v2: Reduce the set of added patterns to those that actually help
something.  This reduces the size of the state transition tables by
about 29k.  Suggested by Jason.  Remove the existing patterns that this
commit subsumes.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake
total instructions in shared programs: 903171 -> 903108 (<.01%)
instructions in affected programs: 635903 -> 635840 (<.01%)
helped: 25
HURT: 11
helped stats (abs) min: 1 max: 16 x̄: 5.04 x̃: 3
helped stats (rel) min: <.01% max: 0.15% x̄: 0.04% x̃: 0.03%
HURT stats (abs)   min: 2 max: 14 x̄: 5.73 x̃: 5
HURT stats (rel)   min: <.01% max: 0.11% x̄: 0.04% x̃: 0.02%
95% mean confidence interval for instructions value: -3.91 0.41
95% mean confidence interval for instructions %-change: -0.03% <.01%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 7059527 -> 7059681 (<.01%)
cycles in affected programs: 5249401 -> 5249555 (<.01%)
helped: 41
HURT: 9
helped stats (abs) min: 2 max: 76 x̄: 11.90 x̃: 10
helped stats (rel) min: <.01% max: 11.86% x̄: 0.99% x̃: 0.01%
HURT stats (abs)   min: 2 max: 380 x̄: 71.33 x̃: 12
HURT stats (rel)   min: <.01% max: 0.22% x̄: 0.04% x̃: 0.01%
95% mean confidence interval for cycles value: -14.93 21.09
95% mean confidence interval for cycles %-change: -1.40% -0.20%
Inconclusive result (value mean confidence interval includes 0).

Ice Lake
total instructions in shared programs: 895506 -> 895384 (-0.01%)
instructions in affected programs: 658800 -> 658678 (-0.02%)
helped: 37
HURT: 0
helped stats (abs) min: 2 max: 8 x̄: 3.30 x̃: 2
helped stats (rel) min: <.01% max: 0.03% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -4.00 -2.59
95% mean confidence interval for instructions %-change: -0.02% -0.02%
Instructions are helped.

total cycles in shared programs: 7092748 -> 7092224 (<.01%)
cycles in affected programs: 5272008 -> 5271484 (<.01%)
helped: 36
HURT: 14
helped stats (abs) min: 2 max: 440 x̄: 21.67 x̃: 8
helped stats (rel) min: <.01% max: 11.86% x̄: 1.12% x̃: 0.02%
HURT stats (abs)   min: 2 max: 122 x̄: 18.29 x̃: 6
HURT stats (rel)   min: <.01% max: 0.07% x̄: 0.01% x̃: <.01%
95% mean confidence interval for cycles value: -29.24 8.28
95% mean confidence interval for cycles %-change: -1.40% -0.21%
Inconclusive result (value mean confidence interval includes 0).

Regular shader-db results:

All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 17611489 -> 17611408 (<.01%)
instructions in affected programs: 21188 -> 21107 (-0.38%)
helped: 23
HURT: 1
helped stats (abs) min: 1 max: 16 x̄: 3.78 x̃: 3
helped stats (rel) min: 0.03% max: 5.82% x̄: 1.13% x̃: 0.85%
HURT stats (abs)   min: 6 max: 6 x̄: 6.00 x̃: 6
HURT stats (rel)   min: 0.60% max: 0.60% x̄: 0.60% x̃: 0.60%
95% mean confidence interval for instructions value: -5.27 -1.48
95% mean confidence interval for instructions %-change: -1.70% -0.42%
Instructions are helped.

total cycles in shared programs: 338418502 -> 338366148 (-0.02%)
cycles in affected programs: 2289052 -> 2236698 (-2.29%)
helped: 18
HURT: 3
helped stats (abs) min: 4 max: 18000 x̄: 2909.67 x̃: 38
helped stats (rel) min: 0.09% max: 4.07% x̄: 0.96% x̃: 0.43%
HURT stats (abs)   min: 2 max: 14 x̄: 6.67 x̃: 4
HURT stats (rel)   min: 0.22% max: 1.13% x̄: 0.66% x̃: 0.64%
95% mean confidence interval for cycles value: -5204.00 217.91
95% mean confidence interval for cycles %-change: -1.31% -0.14%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total instructions in shared programs: 11875617 -> 11875615 (<.01%)
instructions in affected programs: 1339 -> 1337 (-0.15%)
helped: 2
HURT: 0

No changes on any earlier Intel platforms.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
d6d63aec18 nir/algebraic: optimize ior(ine(a, 0), ine(b, 0)) to ine(ior(a, b), 0)
Like 70f9e2589e.  Also scrub the unnecessary size qualifier in both
replacement patterns.

This occurs in a handful of places in the soft-fp64 code, and that is
the primary reason for the change.

Perhaps the patterns that generate umin should be conditioned on
something, but I'm not sure what.  lower_bitops might cover the cases
that matter, but it seems ugly.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 936505 -> 933388 (-0.33%)
instructions in affected programs: 925719 -> 922602 (-0.34%)
helped: 154
HURT: 1
helped stats (abs) min: 1 max: 211 x̄: 35.45 x̃: 16
helped stats (rel) min: 0.34% max: 9.30% x̄: 2.28% x̃: 0.96%
HURT stats (abs)   min: 2342 max: 2342 x̄: 2342.00 x̃: 2342
HURT stats (rel)   min: 2.28% max: 2.28% x̄: 2.28% x̃: 2.28%
95% mean confidence interval for instructions value: -51.21 10.99
95% mean confidence interval for instructions %-change: -2.61% -1.89%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 7323502 -> 7306184 (-0.24%)
cycles in affected programs: 7220376 -> 7203058 (-0.24%)
helped: 126
HURT: 1
helped stats (abs) min: 2 max: 946 x̄: 159.10 x̃: 95
helped stats (rel) min: 0.01% max: 9.62% x̄: 0.80% x̃: 0.37%
HURT stats (abs)   min: 2728 max: 2728 x̄: 2728.00 x̃: 2728
HURT stats (rel)   min: 0.37% max: 0.37% x̄: 0.37% x̃: 0.37%
95% mean confidence interval for cycles value: -192.07 -80.66
95% mean confidence interval for cycles %-change: -1.07% -0.51%
Cycles are helped.

total spills in shared programs: 635 -> 817 (28.66%)
spills in affected programs: 635 -> 817 (28.66%)
helped: 0
HURT: 3

total fills in shared programs: 2065 -> 2438 (18.06%)
fills in affected programs: 2019 -> 2392 (18.47%)
helped: 0
HURT: 2

Regular shader-db results:

All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 17611506 -> 17611489 (<.01%)
instructions in affected programs: 33442 -> 33425 (-0.05%)
helped: 32
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 1.69 x̃: 1
helped stats (rel) min: 0.08% max: 1.90% x̄: 0.27% x̃: 0.11%
HURT stats (abs)   min: 1 max: 15 x̄: 6.17 x̃: 5
HURT stats (rel)   min: 0.09% max: 1.50% x̄: 0.65% x̃: 0.55%
95% mean confidence interval for instructions value: -1.70 0.80
95% mean confidence interval for instructions %-change: -0.30% 0.05%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 338419218 -> 338418502 (<.01%)
cycles in affected programs: 385795 -> 385079 (-0.19%)
helped: 42
HURT: 3
helped stats (abs) min: 2 max: 192 x̄: 24.57 x̃: 16
helped stats (rel) min: 0.04% max: 2.09% x̄: 0.33% x̃: 0.22%
HURT stats (abs)   min: 64 max: 164 x̄: 105.33 x̃: 88
HURT stats (rel)   min: 0.77% max: 1.58% x̄: 1.09% x̃: 0.93%
95% mean confidence interval for cycles value: -29.76 -2.06
95% mean confidence interval for cycles %-change: -0.40% -0.07%
Cycles are helped.

Ivy Bridge and Sandy Bridge had similar results. (Ivy Bridge shown)
total instructions in shared programs: 11875620 -> 11875617 (<.01%)
instructions in affected programs: 421 -> 418 (-0.71%)
helped: 2
HURT: 0

total cycles in shared programs: 178245336 -> 178245326 (<.01%)
cycles in affected programs: 3425 -> 3415 (-0.29%)
helped: 2
HURT: 0

No changes on Gen4 or Gen5.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Ian Romanick
88eb8f190b nir/algebraic: Simplify logic to detect sign of an integer
This occurs in a handful of places in the soft-fp64 code, and that is
the primary reason for the change.

v2: Fix a typo in a comment.  Noticed by Matt.  Copy the correct fp64
shader-db results to the commit message.  I realized that I used
accidentally used the results from the next commit.

Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 906235 -> 906149 (<.01%)
instructions in affected programs: 353966 -> 353880 (-0.02%)
helped: 31
HURT: 2
helped stats (abs) min: 1 max: 8 x̄: 3.03 x̃: 3
helped stats (rel) min: 0.01% max: 1.59% x̄: 0.10% x̃: 0.04%
HURT stats (abs)   min: 3 max: 5 x̄: 4.00 x̃: 4
HURT stats (rel)   min: 0.02% max: 0.02% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -3.51 -1.70
95% mean confidence interval for instructions %-change: -0.19% <.01%
Inconclusive result (%-change mean confidence interval includes 0).

total cycles in shared programs: 7076552 -> 7076173 (<.01%)
cycles in affected programs: 2878361 -> 2877982 (-0.01%)
helped: 37
HURT: 2
helped stats (abs) min: 2 max: 48 x̄: 10.81 x̃: 6
helped stats (rel) min: <.01% max: 2.17% x̄: 0.47% x̃: 0.01%
HURT stats (abs)   min: 1 max: 20 x̄: 10.50 x̃: 10
HURT stats (rel)   min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -13.96 -5.48
95% mean confidence interval for cycles %-change: -0.72% -0.16%
Cycles are helped.

total fills in shared programs: 2064 -> 2065 (0.05%)
fills in affected programs: 45 -> 46 (2.22%)
helped: 0
HURT: 1

Regular shader-db results:

All Gen7+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 17611530 -> 17611506 (<.01%)
instructions in affected programs: 5934 -> 5910 (-0.40%)
helped: 10
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 2.40 x̃: 2
helped stats (rel) min: 0.14% max: 1.24% x̄: 0.47% x̃: 0.34%
95% mean confidence interval for instructions value: -3.53 -1.27
95% mean confidence interval for instructions %-change: -0.78% -0.17%
Instructions are helped.

total cycles in shared programs: 338419178 -> 338419218 (<.01%)
cycles in affected programs: 19244 -> 19284 (0.21%)
helped: 4
HURT: 2
helped stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.05% max: 0.11% x̄: 0.08% x̃: 0.08%
HURT stats (abs)   min: 26 max: 26 x̄: 26.00 x̃: 26
HURT stats (rel)   min: 1.20% max: 1.20% x̄: 1.20% x̃: 1.20%
95% mean confidence interval for cycles value: -9.08 22.41
95% mean confidence interval for cycles %-change: -0.35% 1.04%
Inconclusive result (value mean confidence interval includes 0).

No changes on any earlier Intel platform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
2020-03-18 20:36:29 +00:00
Pierre-Eric Pelloux-Prayer
e7f3a8d695 st/mesa: disallow deferred flush if there are multiple contexts
u_threaded can hang in these situation, with one context waiting on a
deferred fence from the other context.
But the other context isn't flushing its pending work (because it's waiting
for more work to pushed) so everything is stuck.

Fixes: d17b35e671 ("gallium: add PIPE_FLUSH_DEFERRED")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1430
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
2020-03-18 20:01:57 +00:00
Chad Versace
6ee971c882 anv: Use isl_drm_modifier_get_default_aux_state()
Use it in anv_layout_to_aux_state().

Refactor only. No change in behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881>
2020-03-18 11:39:33 -07:00
Jason Ekstrand
0905d5a14a intel/isl: Don't align linear images to 64K on Gen12+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048>
2020-03-18 17:33:28 +00:00
Samuel Pitoiset
94e37859a9 radv: fix random depth range unrestricted failures due to a cache issue
The shader module name is used to compute the pipeline key. The
driver used to load the wrong pipelines because the shader names
were similar.

This should fix random failures of
dEQP-VK.pipeline.depth_range_unrestricted.*

Fixes: f11ea22666 ("radv: fix a performance regression with graphics depth/stencil clears")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216>
2020-03-18 11:36:24 +00:00
Hyunjun Ko
a6625b15a4 turnip: Do gathering xfb info after nir_remove_dead_variables
So we could align stream outputs correctly even if unused in/outs are
removed.

Fixes:
  dEQP-VK.transform_feedback.fuzz.random_vertex.scalar_types.*
  dEQP-VK.transform_feedback.fuzz.random_vertex.vector_types.*

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
2020-03-18 09:47:04 +00:00
Hyunjun Ko
c11a2bc202 turnip: Fix wrong assignment of xfb output's offset.
Should be divided by 4 so we could calculate the offset correctly in
tu6_setup_streamout.

Fixes: 2a1d6b81ed
Related: 374406a7c4

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
2020-03-18 09:47:04 +00:00
Lionel Landwerlin
25a54554b3 intel/decoder: don't consider header fields past dword0
v2: use ULL

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
2020-03-18 09:19:53 +00:00
Vasily Khoruzhick
0c41937440 lima: decode depth/stencil write bits in RSW
Now that we know the bits that are responsible for enabling depth/stencil
writes in shader we can decode them properly.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Icenowy Zheng
9205762cae lima: implement zsbuf reload
Fragment shader can write depth and stencil if we set necessary flags
in RSW. In addition to that we need to use special format for Z24S8.
Original format is apparently Z24X8 since we can't sample stencil in GLES2.
This new format also seems to use several components for storing depth
since we saw r != g != b when sampling with this format.

[vasily: - initialize clear->depth to 0xffffff if we reload depth, just
           like blob does. Reloading doesn't work otherwise
         - use single bitmap for reload type]

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Vasily Khoruzhick
dbceabed72 lima: disable Z16 format
Unfortunately we don't know how to reload Z16 buffers yet and blob
is using Z24 for dEQP tests that need depth reload.

Reviewed-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
2020-03-18 08:36:17 +00:00
Eric Anholt
8b8af6d398 gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl.
The util_float_to_half() implementation was much smaller, but when trying
to switch _mesa_float_to_half to it, many testcases
(dEQP-VK.spirv_assembly.instruction.graphics.opquantize.*,
piglit.spec.arb_shading_language_packing.*packhalf2x16) start failing on
Intel.  Replace the broken impl so that people don't have to debug it
later.

Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
2020-03-17 22:28:12 +00:00
Bas Nieuwenhuizen
8e4e2cedcf amd/llvm: Fix divergent descriptor regressions with radeonsi.
piglit/bin/arb_bindless_texture-limit -auto -fbo:
  Needed to deal with non-NULL dynamic_index without deref in tex instructions.

piglit/bin/shader_runner tests/spec/arb_bindless_texture/execution/images/multiple-resident-images-reading.shader_test -auto:
  Need to deal with non-deref images in enter_waterfall_imae.

Fixes: b83c9aca4a "amd/llvm: Fix divergent descriptor indexing. (v3)"
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4191>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4191>
2020-03-17 22:53:16 +01:00
Dave Airlie
040ce9a1b3 gallium: fix build with latest meson and gcc10
In Fedora 32 build was failing with meson-0.53.2-1.git88e40c7.fc32
and gcc-10.0.1-0.9.fc32.x86_64.

Worked with meson-0.53.1-1 and same gcc.

/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri2.c.o): in function `dri2_interop_export_object':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri2.c:1813: undefined reference to `st_finalize_texture'
/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri_screen.c.o): in function `dri_init_screen_helper':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri_screen.c:580: undefined reference to `st_gl_api_create'

Moving this around seems to fix it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
2020-03-17 21:14:38 +00:00
Marek Olšák
8dc5e174c7 ac: don't set old denormals flags with LLVM >= 11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
2020-03-17 20:47:48 +00:00
Marek Olšák
63a5051ea6 ac: set new LLVM denormal flags
See: https://reviews.llvm.org/D71358

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
2020-03-17 20:47:48 +00:00
Marek Olšák
56cc10bd27 ac: unify denorm setting enforcement
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
2020-03-17 20:47:48 +00:00
Marek Olšák
e4959add2f gallium/u_vbuf: simplify the first if statement in u_vbuf_upload_buffers
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
2020-03-17 19:13:57 +00:00
Marek Olšák
99a29a20d2 gallium/u_threaded: don't sync the thread for all unsychronized mappings
This was missing for the READ case. This improves glBegin/End performance.
(vbo maps with WRITE | READ | UNSYCHRONIZED)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
2020-03-17 19:13:57 +00:00
Eric Anholt
5960dadd1f freedreno/a5xx: Fix min-vs-mag filtering decisions on non-mipmap tex.
This a port of 3338d6e5f8 ("freedreno/a3xx: Mostly fix min-vs-mag
filtering decisions on non-mipmap tex.")

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
2020-03-17 11:11:51 -07:00
Eric Anholt
4bc15e78fa ci: Enable testing GLES2-3 on a530 (Dragonboard 820c).
Following on from the db410c conversion to baremetal testing, reuse the
same scripts in the same rack to run 7 db820c boards (#4/8 is failing in
the bootloader for unknown reasons).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
2020-03-17 11:11:51 -07:00
Eric Anholt
8997757c6a ci: Enable ccaching of CMake builds as well.
They ignore $PATH for unknown reasons, so you have to force the ccache
wrapping yourself.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
2020-03-17 10:44:39 -07:00
Eric Anholt
ba39cc5e85 ci: Enable ccache in the container builds.
This should reduce our container rebuild times, particularly on the
40-minute ARM build (which is split across only 2 runners and thus likely
to have a hot cache) when working on updating containers.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
2020-03-17 10:44:39 -07:00
Eric Anholt
af7dca3560 ci: Update the ci-templates commit.
There has been a big rename of variables in the upstream repo to make it
clear what's being handed to ci-templates.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
2020-03-17 10:44:37 -07:00
Jason Ekstrand
d60375cbc2 anv: Do an end-of-pipe sync before updating AUX table entries
We've found in GL that an actual end-of-pipe sync is required before
invalidating the aux tables and that a simple CS stall is insufficient.
If we're about to modify the actual AUX table entries from the GPU, we
should definitely make sure it's stopped dead before we do so.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206>
2020-03-17 16:38:50 +00:00
Caio Marcelo de Oliveira Filho
3dd0d12aa5 intel/blorp: Plumb the stage through blorp upload_shader
Vulkan uses that for its own upload function -- even though for BLORP
it doesn't really currently care.  Neither Iris and i965 makes use of
it at the moment.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
2020-03-17 08:24:46 -07:00
Duncan Hopkins
4c35bc7e61 zink: zero out zink_render_pass_state
Since zink_render_pass_state is used as a hash-key, the entire struct gets
compared. This means we don't want any uninitialized padding in there, or
else we risk getting false negatives. This has led to issues on macOS builds.

So let's zero out the struct before we start filling it out.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
2020-03-17 13:04:30 +00:00
Samuel Pitoiset
c923de68dd radv/gfx10: fix required ballot size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to use the correct ballot size.

Fixes dEQP-VK.subgroups.ballot_other.compute.*_requiredsubgroupSize.

Fixes: fb07fd4e6c ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
2020-03-17 12:45:01 +00:00
Samuel Pitoiset
672d106199 radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to return the correct one.

Fixes dEQP-VK.subgroups.size_control.compute.required_subgroup_size_*.

Fixes: fb07fd4e6c ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
2020-03-17 12:45:01 +00:00
Samuel Pitoiset
46e8ba1344 radv: only inject implicit subpass dependencies if necessary
The Vulkan 1.2.134 spec update clarified when implicit subpass
dependencies should be injected by the driver. They only make
sense if automatic layout transitions are performed.

This should fix a performance regression with RPCS3 (although
they added a workaround for RADV since the regression has been found).

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2502
Fixes: e60de08547 ("radv: handle missing implicit subpass dependencies")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4210>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4210>
2020-03-17 13:24:36 +01:00
Michel Dänzer
a0591863db gitlab-ci: Enable more Gallium drivers in meson-i386 job
These are the ones which can be enabled with the current x86_build
docker image and which build without warnings.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
2020-03-17 11:21:45 +01:00
Michel Dänzer
106bf59ca9 llvmpipe: Use uintptr_t for pointer values
Instead of uint64_t. Fixes potentially writing beyond the end of the
handles pointer array on 32-bit architectures (and copying all 0s
instead of the computed pointer values to the array on big endian
ones).

Corresponding compiler warning:

../src/gallium/drivers/llvmpipe/lp_state_cs.c: In function ‘llvmpipe_set_global_binding’:
../src/gallium/drivers/llvmpipe/lp_state_cs.c:1312:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
 1312 |       va = (uint64_t)((char *)lp_res->data + offset);
      |            ^

Fixes: 264663d55d "gallivm/llvmpipe: add support for global
                     operations."

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
2020-03-17 11:20:49 +01:00
Michel Dänzer
c56f09124b gitlab-ci: Move classic driver testing to a new meson-classic job
The motivation is to allow llvmpipe to be enabled instead in the
meson-i386 job.

v2: (Eric Engestrom)
* Rename meson-main job to meson-gallium
* Remove stale comment above meson-i386 job

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
2020-03-17 11:20:23 +01:00
Michel Dänzer
c3727ae431 gitlab-ci: Fold scons-swr job into scons job
Should be fast enough.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
2020-03-17 11:17:10 +01:00
Connor Abbott
3ff437abb3 tu: Fix border color with compute shaders
I wasn't able to find any CTS tests that used compute shaders with
samplers and set a border color, so I hacked one of the tests included
with amber:

https://gist.github.com/cwabbott0/e72f0ed8259b84ed6bf3920c68fefee6

The register was found via looking at dumps of the Vulkan blob, and
setting it fixes this test.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204>
2020-03-17 09:40:26 +00:00
Michel Dänzer
32eecf5879 gitlab-ci: Don't use buster-backports packages by default for x86_build
The backports repository can be temporarily inconsistent between
architectures, which can break the docker image build.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4209>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4209>
2020-03-17 09:49:09 +01:00
Rohan Garg
90a39af5f6 ci: Drop the git dependency in tracie
Instead of using git, use python and the Gitlab API
to fetch traces. This helps us slim down our ramdisks
in preparation for integrating trace replay on LAVA
devices.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
2020-03-17 07:23:27 +01:00
Tomeu Vizoso
43873afda4 gitlab-ci: Use surfaceless platform also for apitrace
In preparation for using apitrace to replay traces in LAVA jobs, build a
newer waffle so apitrace can use the surfaceless EGL platform.

As things were before this commit, Xvfb would have been needed in the
LAVA images.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
2020-03-17 07:12:36 +01:00
Tomeu Vizoso
2ca662fb61 gitlab-ci: Update renderdoc
Get closer to upstream to avoid accumulating changes.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
2020-03-17 07:12:36 +01:00
Vasily Khoruzhick
ac1dbd5ef8 lima/gpir: fix crash in schedule_insert_ready_list()
Fix crash if node is already at position we want. Otherwise we remove
it from list (and list->prev becomes NULL) and then we dereference list->prev
in list_addtail()

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
2020-03-16 16:28:33 -07:00
Vasily Khoruzhick
2756b62917 lima/gpir: add better lowering for ftrunc
GP doesn't support ftrunc natively and unfortunately one in generic
opt_algebraic is not GP-friendly either. Introduce our own lowering
that utilizes fsign() that GP supports:
ftrunc(a) = fmul(fsign(a), ffloor(fmax(a, -a)))

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
2020-03-16 16:28:33 -07:00
Vasily Khoruzhick
b7d89476f1 lima/gpir: kill dead writes to regs in DCE
Writes to regs that are never read will confuse regalloc since they
are never live and don't conflict with any regs. Kill them to prevent
overwriting another live reg.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
2020-03-16 23:08:06 +00:00
Connor Abbott
8c1bcc8555 lima/gpir: Optimize nots created from branch lowering
We also add a DCE pass to cleanup the result of this pass, which turns
out to also be necessary to cleanup the result of nir->gpir in some
cases that we didn't hit until the next commit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
2020-03-16 23:08:06 +00:00
Connor Abbott
47dacf3867 lima/gpir: Optimize conditional break/continue
Optimize the result of a conditional break/continue. In NIR something
like:

loop {
   ...
   if (cond)
      continue;

would get lowered to:

block_0:
...
block_1:
branch_cond !cond block_3
block_2:
branch_uncond block_0
block_3:
...

We recognize the conditional branch skipping over the unconditional
branch, and turn it into:

block_0:
...
block_1:
branch_cond cond block_0
block_2:
block_3:

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
2020-03-16 23:08:06 +00:00
Connor Abbott
9fb0fda8e7 lima/gpir: Make lima_gpir_node_insert_child() useful
We weren't using this function before. The name is confusing, but it
changes the child while also fixing up the dependence link, if you don't
have access to it already. Or at least, I think that's what the
intention is, and what we'll need to change the branch condition in the
next commit. Adding a dependency between the new and old source doesn't
make any sense for this, and we also need to change the actual source.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
2020-03-16 23:08:06 +00:00
Vinson Lee
5c3f20a25b panfrost: Fix gnu-empty-initializer error.
../src/gallium/drivers/panfrost/pan_cmdstream.c:1553:54: error: use of GNU empty initializer extension [-Werror,-Wgnu-empty-initializer]
        union mali_attr varyings[PIPE_MAX_ATTRIBS] = { };
                                                     ^

Fixes: 836686daf3 ("panfrost: Move panfrost_emit_varying_descriptor() to pan_cmdstream.c")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4198>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4198>
2020-03-16 15:06:57 -07:00
Rhys Perry
2d14a8f237 aco: fix operand order for LS VGPR init bug workaround
Fixes: a952bf3946 ('aco: Fix LS VGPR init bug on affected hardware.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
2020-03-16 19:34:32 +00:00
Rhys Perry
ded7a8bb46 aco: fix instruction encoding for LS VGPR init bug workaround
Fixes: a952bf3946 ('aco: Fix LS VGPR init bug on affected hardware.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
2020-03-16 19:34:32 +00:00
Rhys Perry
ee9e0d1eca aco: set late kill for v_interp_p1_f32 for some APUs
Apparently needed for Stoney Ridge, Kabini and Mullins APUs.

gfx702 also has 16-bank LDS and https://llvm.org/docs/AMDGPUUsage.html
lists some dGPUs under there. Those GPUs seem to be Hawaii actually
(gfx701) and we don't seem to have gotten any interpolation related bugs
reported with them so far.

The late kill flag was tested by running pipeline-db with
ACO_DEBUG=validatera while setting late kill for SMEM buffer loads,
emit_vop2_instruction() and texture instructions. I also tested with
just setting the flag for v_interp_p1_f32.

As far as I know, the only other thing we have to consider for 16-bank LDS
is something to do with 16-bit interpolation. We don't do that yet.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
2020-03-16 16:09:02 +00:00
Rhys Perry
1872759f55 aco: add a late kill flag
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
2020-03-16 16:09:02 +00:00
Rhys Perry
c51348bd9b aco: move some register demand helpers into aco_live_var_analysis.cpp
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
2020-03-16 16:09:02 +00:00
Samuel Pitoiset
e1b08b55ff radv/sqtt: handle thread trace capture in sqtt_QueuePresentKHR()
To avoid wasting CPU cycles when thread trace is not enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4180>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4180>
2020-03-16 15:42:04 +00:00
Jason Ekstrand
4061ac859d anv: Push UBO ranges relative to the start of the binding
There was a disconnect between anv_nir_compute_push_layout and the code
which sets up the push_ubo_sizes array.  The NIR code we emit checks
relative to the start of the bound UBO range so that, if we end up with
a vector which straddles the start of the push range, we can perform the
bounds check without risking overflow issues.  The code which sets up
the push_ubo_sizes, on the other hand, assumed it was relative to the
start of the push range.  Somehow, this didn't get get caught by any of
the available tests.

Fixes: e03f965280 "anv: Bounds-check pushed UBOs when ..."
Closes: #2623
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
2020-03-16 15:14:14 +00:00
Jason Ekstrand
ae15b4fd73 anv: Fix the comparison in an assert
Fixes: e03f965280 "anv: Bounds-check pushed UBOs when ..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
2020-03-16 15:14:14 +00:00
Samuel Pitoiset
299fad5585 gitlab-ci: bump Vulkan CTS to 1.2.1.0
Vulkan CTS 1.1.6.0 is quite old.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4179>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4179>
2020-03-16 14:36:41 +00:00
Samuel Pitoiset
af6d8dea00 gitlab-ci: do not set the number of deqp-parallel jobs for RADV CTS
Let's the runner uses the maximum number of jobs to speedup CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4179>
2020-03-16 14:36:41 +00:00
Samuel Pitoiset
4668a08e9d gitlab-ci: allow deqp-runner to use the maximum number of jobs
if $DEQP_PARALLEL is not set, it will use the maximum number of
jobs instead of 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4179>
2020-03-16 14:36:41 +00:00
Samuel Pitoiset
888b41f0ee gitlab-ci: remove useless 'patch' package in the VK test image
It was copied from the GL test image but it's actually unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4179>
2020-03-16 14:36:41 +00:00
Connor Abbott
3349fe9a26 tu: Rewrite border color handling
Emit a single table of all possible Vulkan border colors up front, and
then index into it using the Vulkan enum directly. In fact this seems to
be the entire point of separating out border colors in the first place.

In addition to being simpler and having less CPU overhead, and fixing
cases where more than one sampler uses border color, this paves the way
for bindless samplers because the existing approach isn't great for
bindless.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4200>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4200>
2020-03-16 13:17:54 +00:00
Jose Fonseca
f6dad10d04 meson: Avoid duplicate symbols.
All the stubs in src/compiler/glsl/glcpp/pp_standalone_scaffolding.c
are duplicate symbols.  They should only be used as replacement for
Mesa functions when building glcpp and glsl standalone compilers, but
in fact they are getting linked with Mesa.

This change fixes this by moving the standalone stubs to a
libglcpp_standalone target, that's only linked with the glcpp/glsl
tools.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4186>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4186>
2020-03-16 11:52:26 +00:00
Neil Armstrong
4b61ad372d Revert "ci: Remove T820 from CI temporarily"
This reverts commit 089c8f0b8d.

Our office changes are finished and power is now stable in our lab
for T820 CI to run again.

Cc: Daniel Stone <daniels@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4057>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4057>
2020-03-16 11:16:27 +00:00
Neil Armstrong
bbdb4b1a6d gitlab-ci/lava: fix handling of lava tags
The lava tags was a python array not it's a gitlab CI string,
slit the string with periods in the jinja2 template to avoid having
the following tags :

tags:
 - p
 - a
 - n
 - f
 - r
 - o
 - s
 - t

instead of :
tags:
 - panfrost

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4057>
2020-03-16 11:16:27 +00:00
Tapani Pälli
fd1436440b iris: allow compression conditionally for images on gen12
With this change, amount of resolves happening with deqp-gles31
(--deqp-case=*load_store*) drops ~50%.

v2: use iris_image_view_get_format to get the format,
    get devinfo from context instead of passing it (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
d836f3fadf isl: allow compression for storage images on gen12+
This is done to be able to use ISL_AUX_USAGE_CCS_E with images.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
cd132a8eed iris: determine aux usage during predraw and state setup
Patch changes surface state setup to alloc/fill states for all possible
usages for image resource on gen12. Also predraw and binding table
population is changed to determine correct aux usage with the new
iris_image_view_aux_usage.

v2: alloc always all states independent on current image
    aux state on gen >= 12 , code cleanups (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
d4c879e69e iris: move existing image format fallback as a helper function
Patch adds a helper function for determining image format and changes
iris_set_shader_images to use it.

v2: pass iris_context instead of pipe one, rename function,
    code cleanup (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
fe2baf72e7 iris: provide dummy iris_image_view_aux_usage
Similar to iris_resource_texture_aux_usage this function will
determine proper aux_usage for image, now it will default to
ISL_AUX_USAGE_NONE.

v2: drop gen_device_info parameter, rename function (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
e8f0483ec4 intel/compiler: detect if atomic load store operations are used
Patch adds a new arg and modifies existing calls from i965, anv
pass NULL but iris stores this information for later use.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
6dd654ba41 iris: use the images_used mask in resolve pass
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Tapani Pälli
5910c938a2 nir/glsl: gather bitmask of images used by program
In a similar fashion as commit f5c7df4dc9 does for textures.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
2020-03-16 10:34:21 +00:00
Danylo Piliaiev
51b1b102bd st/mesa: Fix signed integer overflow when using util_throttle_memory_usage
../src/mesa/state_tracker/st_cb_texture.c:1719:57: runtime error: signed integer overflow: 203489280 * 16 cannot be represented in type 'int'

Fixes: 21ca322e63
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4185>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4185>
2020-03-16 10:10:13 +00:00
Matt Turner
b93a195225 isl: Avoid EXPECT_DEATH in unit tests
EXPECT_DEATH works by forking the process and letting the forked process
fail with an assertion. This process is evidently incredibly expensive,
taking ~30 seconds to run the whole isl_aux_info_test on a 2.8GHz
Skylake. Annoyingly all of the (expected) assertion failures also leaves
lots of messages in dmesg and potentially generates lots of coredumps.

Instead, avoid the expense of fork/exec by redefining assert() and
unreachable() in the code we're testing to return a unit-test-only
value. With this patch, the test takes ~1ms.

Also, while modifying the EXPECT_EQ() calls, reverse the arguments so
that the expected value comes first, as is intended. Otherwise gtest
failure messages don't make much sense.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/issues/2567
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4174>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4174>
2020-03-13 17:48:03 -07:00
Jan Zielinski
5e523c9265 gallium/swr: use ElementCount type arguments for getSplat()
Reviewed-by: Alok Hota <alok.hota@intel.com>

In LLVM11, ConstantVector::getSplat() function definition
has changed and the first function argument has now ElementCount type.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4188>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4188>
2020-03-13 17:56:13 +00:00
Christian Gmeiner
a19d8c836f etnaviv: enable shareable shaders
We are not using any pctx reference in the shader so it seems fine
to enable this cap.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4095>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4095>
2020-03-13 16:50:19 +00:00
Christian Gmeiner
fe204de632 etnaviv: get rid of etna_spec in etna_context
There is no need to have a complete copy of etna_spec - just
reference the one and only from etna_screen.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4095>
2020-03-13 16:50:19 +00:00
Jason Ekstrand
4432dd6ea4 anv: Dump push ranges via VK_KHR_pipeline_executable_properties
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4173>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4173>
2020-03-13 16:31:44 +00:00
Rhys Perry
625d8705f0 aco: don't stop scheduling at exports
This allows us to move v_cvt_pkrtz_f16_f32 instructions upwards, improving
schedules and (somewhat unintentionally) moving the exports slightly
closer together.

Totals from affected shaders:
SGPRS: 1030224 -> 1030248 (0.00 %)
VGPRS: 794080 -> 794392 (0.04 %)
Spilled SGPRs: 127117 -> 127117 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 89028152 -> 89032312 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 65252 -> 65219 (-0.05 %)
SMEM score: 843808.00 -> 843918.00 (0.01 %)
VMEM score: 5331687.00 -> 5397802.00 (1.24 %)
SMEM clauses: 567659 -> 567655 (-0.00 %)
VMEM clauses: 290715 -> 290716 (0.00 %)
Instructions: 17143219 -> 17144259 (0.01 %)
Cycles: 1098442808 -> 1098446968 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3776>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3776>
2020-03-13 14:04:50 +00:00
Rhys Perry
6b4c31f814 aco: allow barriers to be skipped during scheduling
Much better scheduling apparently in 160 shaders

Totals from affected shaders:
SGPRS: 6272 -> 6344 (1.15 %)
VGPRS: 4832 -> 4844 (0.25 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 467192 -> 467428 (0.05 %) bytes
LDS: 459 -> 459 (0.00 %) blocks
Max Waves: 1407 -> 1409 (0.14 %)
SMEM score: 9309.00 -> 11216.00 (20.49 %)
VMEM score: 26679.00 -> 33652.00 (26.14 %)
SMEM clauses: 1817 -> 1776 (-2.26 %)
VMEM clauses: 2286 -> 2288 (0.09 %)
Instructions: 86537 -> 86596 (0.07 %)
Cycles: 676260 -> 676568 (0.05 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3776>
2020-03-13 14:04:50 +00:00
Rhys Perry
928ac97875 aco: add helpers for ensuring correct ordering while scheduling
Pipeline-db changes in 721 shaders.

Totals from affected shaders:
SGPRS: 42336 -> 42656 (0.76 %)
VGPRS: 38368 -> 38636 (0.70 %)
Spilled SGPRs: 11967 -> 11967 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 5268088 -> 5269840 (0.03 %) bytes
LDS: 1069 -> 1069 (0.00 %) blocks
Max Waves: 4473 -> 4447 (-0.58 %)
SMEM score: 41155.00 -> 41826.00 (1.63 %)
VMEM score: 146339.00 -> 147471.00 (0.77 %)
SMEM clauses: 24434 -> 24535 (0.41 %)
VMEM clauses: 16637 -> 16592 (-0.27 %)
Instructions: 996037 -> 996388 (0.04 %)
Cycles: 76476112 -> 75281416 (-1.56 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3776>
2020-03-13 14:04:50 +00:00
Rhys Perry
2cd760847a aco: add helpers for moving instructions for scheduling
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3776>
2020-03-13 14:04:50 +00:00
Samuel Pitoiset
2d295ab3f3 radv: add llvm_compiler_shader() helper
To match aco_compile_shader().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
2020-03-13 10:22:13 +00:00
Samuel Pitoiset
4d991c2de4 radv: remove unnecessary LLVM includes
They are already included from src/amd/llvm.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
2020-03-13 10:22:13 +00:00
Samuel Pitoiset
5ea32a6201 radv: remove radv_shader_variant::aco_used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
2020-03-13 10:22:13 +00:00
Samuel Pitoiset
3fea948177 radv: cleanup occurences of use_aco everywhere
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4163>
2020-03-13 10:22:13 +00:00
Danylo Piliaiev
1305b93274 glsl: do not crash if string literal is used outside of #include/#line
Fixes: 67b32190f3
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2619
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4146>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4146>
2020-03-13 11:49:06 +02:00
Caio Marcelo de Oliveira Filho
f8051f77ea anv: Remove duplicate code in anv_cmd_buffer_bind_descriptor_set
Also use a single condition statement instead of two.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
0a5053b687 anv: Reduce compute pipeline batch_data size
The batch associated with the compute pipeline only needs room for a
MEDIA_VFE_STATE. So this patch moves the batch_data to each pipeline
struct and cap the one in compute pipeline.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
925df46b7e anv: Split graphics and compute bits from anv_pipeline
Add two new structs that use the anv_pipeline as base.  Changed all
functions that work on a specific pipeline to use the corresponding
struct.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
af33f0d767 anv: Use a separate field in the pipeline for compute shader
This is a preparation for splitting the compute and graphics pipelines
into separate structs.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
bff45b6a7f anv: Decouple flush_descriptor_sets() from pipeline struct
Explicitly pass the active stages and the array (and size) of shaders
to be processed.  This will make easy to store only the shaders needed
for each pipeline.

The active stages can be identified by a non-NULL shader in the
shaders array, so stop using it and keep track of the flushed stages
as iteration happens.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
6df0ac2653 anv: Decouple flush_descriptor_sets() helpers from pipeline struct
Pass the `anv_shader_bin *` instead of expecting the helpers to peek
into the pipeline struct.  Also reach for the device from the
cmd_buffer instead of the pipeline.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
d1c13f01aa anv: Remove redundant check in flush_descriptor_sets() helpers
These helpers are only called for stages that are active, so the code
for a non-active stage is never executed.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
eec04c0aae anv: Pass the right pipe_state to flush_descriptor_sets()
The caller has this information, so pass directly instead of making
each helper function call figure that one out.  Also, since we can
reach the pipeline from pipe_state, drop that parameter from the
function.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
88df3bf79a anv: Keep the shader stage in anv_shader_bin
This will be used to decouple the logic flush_descriptor_sets() from
the position in the shader array, allowing us to store just the
shaders needed for each pipeline.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
9bf044d254 anv: Use a dynamic array for storing executables in pipeline
Avoids waste for pipelines that don't use all the shaders, and is
flexible enough to cover cases where there are multiple variants per
shader (e.g. SIMD8/16/32 for fragment shader).

Even though we could pre-calculate the exact size of the array, this
is not a critical path so it is worth preventing the bug that will
likely happen when new variants are added but not accounted for.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
9b0682df82 anv: Use pipeline type to decide whether or not lower multiview
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Caio Marcelo de Oliveira Filho
613c9b78e3 anv: Add a new enum to identify the pipeline type
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
2020-03-12 13:18:54 -07:00
Eric Anholt
d0a52432b1 glsl/tests: Fix waiting for disk_cache_put() to finish.
We were wasting 4s on waiting for expected-not-to-appear files to show
up on every test.  Using timeouts in test code is error-prone anyway,
as our shared runners may be busy on other jobs.

Fixes: 50989f87e6 ("util/disk_cache: use a thread queue to write to shader cache")
Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2505
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140>
2020-03-12 19:47:23 +00:00
Eric Anholt
e178bca5cc glsl/tests: Catch mkdir errors to help explain when they happen.
A recent pipeline
(https://gitlab.freedesktop.org/Venemo/mesa/-/jobs/1893357) failed
with what looks like an intermittent error related to making files for
the cache test inside of the core of the cache.  Given some of the
errors, it looks like maybe a mkdir failed, so log those errors
earlier so we can debug what's going on next time.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4140>
2020-03-12 19:47:23 +00:00
Caio Marcelo de Oliveira Filho
7d54b84d49 intel/fs: Combine adjacent memory barriers
This will avoid generating multiple identical fences in a row.

For Gen11+ we have multiple types of fences (affecting different
variable modes), but is still better to combine them in a single
scoped barrier so that the translation to backend IR have the option
of dispatching both fences in parallel.

This will clean up redundant barriers from various
dEQP-VK.memory_model.* tests.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
2020-03-12 19:21:36 +00:00
Caio Marcelo de Oliveira Filho
bf432cd831 nir: Add pass to combine adjacent scoped memory barriers
SPIR-V generates very granular barriers, however HW and backends might
not necessarily take advantage of those.  This pass provides a general
mechanism to combine such barriers.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
2020-03-12 19:21:36 +00:00
Caio Marcelo de Oliveira Filho
d31a8ed8fd nir: Reorder nir_scopes so wider scope has larger numeric value
Makes code comparing and combining scopes slightly more readable.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
2020-03-12 19:21:36 +00:00
Caio Marcelo de Oliveira Filho
67fc88fbb9 nir: Don't skip a bit in nir_memory_semantics
There was another enum entry in the draft versions of
nir_memory_semantics, but when it got dropped the entries were not
updated.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3224>
2020-03-12 19:21:36 +00:00
Samuel Pitoiset
a46e9f4d9a radv: use ac_gpu_info::use_late_alloc
Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
2020-03-12 18:17:47 +00:00
Samuel Pitoiset
741dd9e32b radv: rewrite late alloc computation
Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
2020-03-12 18:17:47 +00:00
Samuel Pitoiset
74e7b442f2 radv: tune primitive binning for small chips
Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
2020-03-12 18:17:47 +00:00
Samuel Pitoiset
22d3e047e5 radv: use better tessellation tunables on GFX9+
Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
2020-03-12 18:17:47 +00:00
Samuel Pitoiset
6d27022ce1 radv/gfx10: cache metadata in L2 on small chips
Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>
2020-03-12 18:17:47 +00:00
Jason Ekstrand
6310c666a4 intel/isl: Set DepthStencilResource based on aux usage
In ISL, usage flags only carry intent and not semantic meaning.  We
don't have a bulletproof way in ISL to specify that an image is of
depth/stencil type.  The usage flags are great but blorp, for instance,
loves to disrespect them.  One proposed solution to this problem is to
add explicit depth/stencil formats which are distinct from the
corresponding color formats.

Fortunately, however, empirical evidence suggests that this bit only
affects the sampler's interpretation of the CCS data.  Therefore, we can
set the bit based off of the aux_usage which is now very specific and
does carry semantic meaning.  In particular, aux_usage now makes a
distinction between color CCS and depth/stencil CCS which appears to be
exactly what the DepthStencilResource bit is for.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
f047e504a5 intel: Require ISL_AUX_USAGE_STC_CCS for stencil CCS
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
56e15bf31c iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCS
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
69a0150e4e intel/blorp: Allow STC_CCS in blit sources
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
6fa92cd015 intel/isl: Add a separate ISL_AUX_USAGE_STC_CCS
Stencil CCS is slightly different from color CCS.  Using a color CCS
resolve with stencil CCS doesn't do the right thing and you can't sample
from a stencil CCS image without the DepthStencilResource bit set or you
will get the wrong data.  Stencil CCS also has it's own rules such as it
doesn't support fast-clear and has no partial resolve.  This seems to
indicate that it should probably be its own isl_aux_usage.  Now that
adding new isl_aux_usage values is pretty cheap, let's split stencil CCS
out on its own.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
05a8e981ad intel/isl: Require ISL_AUX_USAGE_HIZ_CCS_WT for HZ+CCS WT mode
We also delete the badly named isl_surf_supports_hiz_ccs_wt.  The name
is misleading because it doesn't return whether or not the surface
supports HiZ+CCS in write-through mode (any single-sampled HiZ+CCS
capable surface does) but rather a heuristic decision about whether or
not we want to enable write-through mode based on the usage flags in the
isl_surf.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
ff1f0a720d iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZ
Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let
ISL choose write-through based on isl_surf_supports_hiz_ccs_wt.  This
commit makes us choose explicitly at surface creation time whether to
use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions.  This is
more explicit and should be more robust as it lets us choose WT mode in
one place rather than trusting isl_surf_supports_hiz_ccs_wt to return
the same thing every time.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
e13ed0e9e5 intel/blorp: Allow HIZ_CCS_WT in copy sources
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
98dc7f56b7 intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT
This is distinct from ISL_AUX_USAGE_HIZ_CCS in that the HiZ surface
operates in write-through mode which means that the HiZ surface is only
used for depth-testing acceleration and the CCS-compressed main surface
is always valid so we can texture from it.

Separating full HiZ from write-through mode at the isl_aux_usage level
has a couple of advantages:

 1. It's more explicit.  Instead of write-through mode depending on the
    heuristic decision in isl_surf_supports_hiz_ccs_wt, it's now
    something that's explicitly requested by the driver.  This should be
    more robust than hoping isl_surf_supports_hiz_ccs_wt always returns
    the same thing every time.  If someone (say BLORP) ever drops a
    usage flag on the isl_surf, there's a chance it could return a
    different value without us noticing leading to corruptions.

 2. Because ISL_AUX_USAGE_HIZ_CCS_WT is it's own isl_aux_usage flag, we
    can say inside the driver that HIZ_CCS does not support sampling but
    HIZ_CCS_WT does.  We can also pass HIZ_CCS_WT to isl_surf_fill_state
    and it can do some validation for us beyond what we would be able to
    do if we conflate HIZ_CCS_WT and CCS_E.

 3. In the future, we can add new heuristics to the driver which do
    things such as start all depth surfaces (regardless of usage flags)
    off in HIZ_CCS and then do a full resolve and drop to HIZ_CCS_WT the
    first time it gets used by the sampler.  This would potentially let
    us enable the faster HIZ_CCS mode even in cases where it technically
    comes in through the API as a texture.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Jason Ekstrand
feaedc1fbe intel/isl: Clean up some aux surface logic
The first check is redundant because the first thing we do in the "emit
the aux surface" section is assert that we actually have an aux_surf.
The second check involves an exclusion list of things which don't have
aux surfaces on Gen12 but an inclusion list is much simpler because it's
just "does it have MCS?".

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
2020-03-12 17:51:28 +00:00
Marek Olšák
84f97a21a6 ac: disable late alloc on small gfx10 chips
same as PAL.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
2020-03-12 17:27:23 +00:00
Marek Olšák
7ba5e94c50 ac: add radeon_info::use_late_alloc to control LATE_ALLOC globally
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
2020-03-12 17:27:23 +00:00
Marek Olšák
09295e95eb radeonsi: tune primitive binning for small chips
same as PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
2020-03-12 17:27:23 +00:00
Marek Olšák
629b6ddd71 radeonsi: set better tessellation tunables on gfx9 and gfx10
same as PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
2020-03-12 17:27:23 +00:00
Marek Olšák
bf5b65d0fd radeonsi/gfx10: cache metadata in L2 on small chips
same as PAL.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
2020-03-12 17:27:23 +00:00
Samuel Pitoiset
e6e97ea92e radv/sqtt: describe layout transitions with user markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138>
2020-03-12 17:04:55 +00:00
Samuel Pitoiset
b229302b96 radv/sqtt: describe begin/end subpass barriers with user markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4138>
2020-03-12 17:04:55 +00:00
Juan A. Suarez Romero
90550b2a3e nir/algebraic: coalesce fmod lowering
As fmod for 16/32/64 bits lowering does the same, let's merge all of
them in a single case.

Fixes dEQP-VK.glsl.builtin.precision_double.mod.compute.* on ACO.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118>
2020-03-12 16:42:52 +00:00
Juan A. Suarez Romero
acd0dd3b4b nir/lower_double_ops: relax lower mod()
Currently when lowering mod() we add an extra instruction so if
mod(a,b) == b then 0 is returned instead of b, as mathematically
mod(a,b) is in the interval [0, b).

But Vulkan spec has relaxed this restriction, and allows the result to
be in the interval [0, b].

For the OpenGL case, while the spec does not allow this behaviour, due
the allowed precision errors we can end up having the same result, so
from a practical point of view, this behaviour is allowed (see
https://github.com/KhronosGroup/VK-GL-CTS/issues/51).

This commit takes this in account to remove the extra instruction
required to return 0 instead.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4118>
2020-03-12 16:42:52 +00:00
Bas Nieuwenhuizen
b83c9aca4a amd/llvm: Fix divergent descriptor indexing. (v3)
There are multiple LLVM passes that very much move the
intrinsic using the descriptor outside of the loop, defeating
the entire point of creating the loop.

Defeat the optimizer by  splitting the break into a separate
if-statement and putting an optimization barrier on the bool
in between.

v2: Move from a callback based system to begin/end loop.
    This does not make it significantly less intrusive but
    is a bit nicer with all the extra struct and callback
    stubs.
v3: Deal with non-divergent values in divergent path.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2160
Fixes: 028ce52739 "radv: Add non-uniform indexing lowering."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4109>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4109>
2020-03-12 16:12:02 +00:00
Ian Romanick
ba88e95187 intel/fs: Fix NULL destinations on 3-source instructions again after late DCE
We considered moving this down near the call to
insert_gen4_send_dependency_workarounds.  By that point it's too late
for a couple reasons.  One, we're potentially increasing resiter
pressure that may lead to anoter spill.  Two, fixup_3src_null_dest tries
to allocate a VGRF, but the post-register allocation shader uses
physical registers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2621
Fixes: ba2fa1ceaf ("intel/fs: Do cmod prop again after scheduling")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4155>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4155>
2020-03-12 08:22:43 -07:00
Timur Kristóf
cfa299eadb radv: Enable subgroup shuffle on GFX10 when ACO is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159>
2020-03-12 13:34:41 +00:00
Timur Kristóf
967eb23261 radv: Enable lowering dynamic quad broadcasts.
This will lower dynamic quad broadcasts into something that both
LLVM and ACO can understand. On hardware which supports shuffles,
they are lowered to shuffle, on older hardware (GFX6-7) they will
get lowered to constant quad broadcasts.

Fixes dEQP-VK.subgroups.quad.*.subgroupquadbroadcast_nonconst_*

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147>
2020-03-12 13:16:07 +00:00
Timur Kristóf
ec16535b49 nir: Add ability to lower non-const quad broadcasts to const ones.
Some hardware doesn't support subgroup shuffle, and on such hardware
it makes no sense to lower quad broadcasts to shuffle. Instead, let's
lower them to four const quad broadcasts, paired with bcsel instructions.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4147>
2020-03-12 13:16:07 +00:00
Eric Engestrom
3aa83d809f gen_release_notes: resolve ambiguity by renaming version to previous_version and next_version to this_version
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113>
2020-03-12 12:57:11 +00:00
Eric Engestrom
64af6b3bcf gen_release_notes: fix version in "you should wait" message
Fixes: 86079447da ("scripts: Add a gen_release_notes.py script")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4113>
2020-03-12 12:57:11 +00:00
Alyssa Rosenzweig
dcc50f4302 pan/bi: Interpret register allocation results
Once LCRA has run, we have a map from IR indices to byte offsets into
the register file, so we need to "install" these results, rewriting the
IR to use native registers and fixing up writemasks/swizzles to
substitute vectorization for adjacent registers (for LCRA, we're
modeling in terms of real vectors).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
e8139ef645 pan/bi: Add register allocator
We model the machine as vector (with restrictions) to natively handle
mixed types and I/O and other goodies. We use LCRA for the heavylifting.
This commit adds only the modeling to feed into LCRA and spit LCRA
solutions back; next commit will integrate it with the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
116c541c07 pan/bi: Fix missing src_types
We want types to be consistent throughout the IR so we don't have to
make exceptions to parse things out. These cases just got missed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
e1d9533925 pan/bi: Fix vector handling of readmasks
The issue was messing with liveness analysis... with Midgard we look at
the writemask to decide how the instruction behaves. Here, since our ALU
is scalar (except for subdivision which doesn't have proper writemasks
anyway) we just look at the component count directly -- either 4 for
vector instructions (essentially - for smaller loads we can replicate
manually without much burden), or 1 for scalar.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
c63105f988 pan/bi: Minor fixes in iteration macros
Found during RA bringup.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
545dedba13 pan/midgard: Remove incorrect comment in RA
Ironically, this comment was mistakenly added by the commit that fixed
the purported issue in the comment (1bce7fdecd - found by `git blame`)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Alyssa Rosenzweig
f06db4d54c panfrost: Move lcra to panfrost/util
We'll want to use it for the Bifrost RA as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
2020-03-12 12:41:08 +00:00
Rhys Perry
4d0203aa83 glsl/list: use uintptr_t for exec_node_data()'s subtraction
This fixes UBSan warnings when foreach_list_typed_safe() passes NULL:
pointer index expression with base 0x000000000000 overflowed to 0xffffffffffffffa8

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4157>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4157>
2020-03-12 12:09:07 +00:00
Rhys Perry
85d05b3fd7 aco: fix uninitialized data error in waitcnt pass
Shouldn't create any incorrect waitcnts but may create suboptimial
waitcnts in rare cases.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4133>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4133>
2020-03-12 11:46:56 +00:00
Samuel Pitoiset
cc320ef9af ac/llvm: add missing optimization barrier for 64-bit readlanes
Otherwise, LLVM optimizes it but it's actually incorrect.

Fixes: 0f45d4dc2b ("ac: add ac_build_readlane without optimization barrier")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3585>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3585>
2020-03-12 08:46:42 +01:00
Tapani Pälli
9c53a3bb22 iris: toggle on PIPE_CAP_MIXED_COLOR_DEPTH_BITS
This enables additional EGL configs where we have depth/stencil buffer
with different number of bits per pixel than color buffer has. This
enables some Android games to work that require such config.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127>
2020-03-12 05:08:48 +00:00
Hyunjun Ko
1896b44aee turnip: Add tu6_control struct.
Follow the way that freedreno is doing so that we could see the whole
layout of the scratch buffer.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:17 +00:00
Hyunjun Ko
e4f1697b54 turnip: Enable VK_EXT_transform_feedback
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
Hyunjun Ko
4a45c84672 turnip: Implement an empty function vkCmdDrawIndirectByteCountEXT
TODO. We should implement this since indirect draw is enabled.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
Hyunjun Ko
9ff1959ca5 turnip: Implement stream-out emit and vkApis for transform feedback
1. Implement vkCmdBindTransformFeedbackBuffersEXT,
vkCmdBeginTransformFeedbackEXT and vkCmdEndTransformFeedbackEXT.
 - Not handling counter buffers yet.
2. Implement streamout emit function, mostly taken from fd6_emit.c

v2. Replace emit_pkt4 funcs with emit_regs.

v3. Don't copy the state of stream-output from tu_pipeline.

v4. Set zero to VPC_SO_CNTL/VPC_SO_BUF_CNTL in tu6_init_hw.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
Hyunjun Ko
374406a7c4 turnip: Setup stream-output when linking program
Mostly taken from fd6_program.c.

v2. Note that it forces to use full VS instead of binning pass VS if
there's stream output as the binning pass VS will have outputs on
other than position/psize stripped out, which is the same as freedreno.

v3. fix indentation.

v4. Use register index instead of location when setup streamout.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
Hyunjun Ko
82fdb13c25 turnip: Define structs for transform feedback
Define new structures for streamout buffers and state.
Most members of the state struct are taken from freedreno driver.

v2. Use IR3_MAX_SO_* and avoid using magic values.

v3. Remove the state of stream-output in tu_cmd_state and use one in
tu_pipeline and split out reset and enabled fields.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
Hyunjun Ko
2a1d6b81ed turnip: Gather information for transform feedback
- Add one member to the existed ir3_stream_output so that we could
assign location information from nir_xfb_info, rather than defining
new struct.

- Redefine maximum of so buffers, streams and outputs, which will be
used for turnip.

- Also enable caps for transform feedback for spirv_to_nir.

v2. Remove redefined maximums and use IR3_MAX_SO_* and add
IR3_MAX_SO_STREAMS.

v3. Remove the newly added location field so that we could keep aligned
with 32 bytes. Instead we create an array mapping between the location
and consecutive index, which is GL driver is doing.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3942>
2020-03-12 03:10:16 +00:00
David Stevens
31c420565c egl/android: set window usage flags
When creating an egl surface from an ANativeWindow, the window's usage
flags need to be set so that buffers are allocated properly.

Signed-off-by: David Stevens <stevensd@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lepton Wu <lepton@chromium.org>
2020-03-12 11:03:32 +09:00
Eric Anholt
cf5ba9d409 ci: Make a simple little bare-metal fastboot mode for db410c.
This supports powering up the device (using an external tool you
provide based on your particular lab), talking over serial to wait for
the fastboot prompt, and then booting a fastboot image on a target
device.

I was previously relying on LAVA for this, but that ran afoul of
corporate policies related to the AGPL.  However, LAVA wasn't doing
too much for us, given that gitlab already has a job scheduler and
tagging and runners.  We were spending a lot of engineering on making
the two systems match up, when we can just have gitlab do it directly.

Lightly-reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4076>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4076>
2020-03-11 21:36:47 +00:00
Eric Anholt
d51da8610f ci: Fix installation of firmware for db410c's nic.
The debian firmware package doesn't actually contain it, costing us a
minute of boot time waiting for it to show up.

Lightly-reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4076>
2020-03-11 21:36:47 +00:00
Eric Anholt
ff1183648a ci: Print the renderer/version that our dEQP invocation is using.
This is useful for sanity checking how the driver loads.

Lightly-reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4076>
2020-03-11 21:36:47 +00:00
Yevhenii Kolesnikov
32b7ba66b0 intel/compiler: fix cmod propagation optimisations
Knowing following:
 - CMP writes to flag register the result of
   applying cmod to the `src0 - src1`.
   After that it stores the same value to dst.
   Other instructions first store their result to
   dst, and then store cmod(dst) to the flag
   register.
 - inst is either CMP or MOV
 - inst->dst is null
 - inst->src[0] overlaps with scan_inst->dst
 - inst->src[1] is zero
 - scan_inst wrote to a flag register

There can be three possible paths:

 - scan_inst is CMP:

   Considering that src0 is either 0x0 (false),
   or 0xffffffff (true), and src1 is 0x0:

   - If inst's cmod is NZ, we can always remove
     scan_inst: NZ is invariant for false and true. This
     holds even if src0 is NaN: .nz is the only cmod,
     that returns true for NaN.

   - .g is invariant if src0 has a UD type

   - .l is invariant if src0 has a D type

 - scan_inst and inst have the same cmod:

   If scan_inst is anything than CMP, it already
   wrote the appropriate value to the flag register.

 - else:

   We can change cmod of scan_inst to that of inst,
   and remove inst. It is valid as long as we make
   sure that no instruction uses the flag register
   between scan_inst and inst.

Nine new cmod_propagation unit tests:
 - cmp_cmpnz
 - cmp_cmpg
 - plnnz_cmpnz
 - plnnz_cmpz (*)
 - plnnz_sel_cmpz
 - cmp_cmpg_D
 - cmp_cmpg_UD (*)
 - cmp_cmpl_D (*)
 - cmp_cmpl_UD

(*) this would fail without changes to brw_fs_cmod_propagation.

This fixes optimisation that used to be illegal (see issue #2154)

= Before =
 0: linterp.z.f0.0(8) vgrf0:F, g2:F, attr0<0>:F
 1: cmp.nz.f0.0(8) null:F, vgrf0:F, 0f
= After =
 0: linterp.z.f0.0(8) vgrf0:F, g2:F, attr0<0>:F

Now it is optimised as such (note change of cmod in line 0):

= Before =
 0: linterp.z.f0.0(8) vgrf0:F, g2:F, attr0<0>:F
 1: cmp.nz.f0.0(8) null:F, vgrf0:F, 0f
= After =
 0: linterp.nz.f0.0(8) vgrf0:F, g2:F, attr0<0>:F

No shaderdb changes

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2154

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3348>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3348>
2020-03-11 21:21:25 +00:00
Alyssa Rosenzweig
3b76b3bc09 pan/bi: Fix swizzle for second argument to ST_VARY
Off-by-one.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
f6d96aa962 pan/bi: Implement nir_op_ffma
We have native FMA which works for graphics usage (unlike Midgard where
it's really reserved for compute for various reasons), let's use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
58f9171894 pan/bi: Add dead code elimination pass
Now that we have liveness analysis, we can cleanup the IR considerably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
56e1c606f8 pan/bi: Add liveness analysis pass
Now that all the guts are shared with Midgard, it's just a matter of
wiring it in.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
0bff6e5e07 pan/bi: Add bi_max_temp helper
Instead of trying to reindex all the times, just be okay with consistent
but sparse indices, then figuring out the max index is easy enough.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
6e0479a6a8 pan/bi: Add bi_next/prev_op helpers
From Midgard. These are surprisingly helpful.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
e623007eb7 pan/bi: Add bi_bytemask_of_read_components helpers
Same purpose as the Midgard version, but the implementation is
*dramatically* simpler thanks to our more regular IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
e94754a7c4 pan/bi: Paste over bi_has_arg
While we're at it, cleanup the Midgard one.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
9b75f410c4 panfrost: Sync Midgard/Bifrost control flow
We can move e v e n more code to be shared and let bi_block inherit from
pan_block, which will allow us to use the shared data flow analysis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
933e44dd43 panfrost: Move liveness analysis to root panfrost/
This way we can share the code with Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:21 +00:00
Alyssa Rosenzweig
5aaaf7b12c pan/midgard: Subclass midgard_block from pan_block
Promote as much as we feasibly can while keeping it Midgard/Bifrost
agnostic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
c5dd1d542d pan/midgard: Sync midgard_block field names with Bifrost
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
4998925d6a pan/midgard: Decontextualize liveness analysis core
We mostly just need the temp_count from it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
3bbec3bc64 pan/midgard: Localize visited tracking
Instead of a property on the block, just track it within the function to
minimize IR dependencies.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
218785c4a9 pan/bi: Implement sysvals
Now that it's all abstracted nicely with an implementation shared with
Midgard, this is pretty easy to get.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
e6f5ae88a7 pan/bi: Switch to panfrost_program
...now that it's shared.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
e610267510 panfrost: Move Midgard sysval code to common Panfrost
We'll use this all as-is in Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
b756a66607 pan/midgard: Remove dest_override sysval argument
Unused, noticed while working on porting over to Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
c2ff3bb0fe pan/midgard: Decontextualize midgard_nir_assign_sysval_body
Now all sysval code should be fairly generic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
674b24dcfd pan/midgard: Remove indexing dependency of sysvals
Ideally we would sync the compilers to use the same indexing scheme but
that's a lot more Midgard refactoring than I have time for right now.
This is good enough honestly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
7c2647f411 pan/midgard: Adjust sysval-related prototypes
We'd like to share this big chunk of code with Bifrost but that requires
removing the compiler_context parameter... which is totally unused in
fact!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
c3f438e023 pan/midgard: Remove unused iterators
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Alyssa Rosenzweig
3a4524e2fe panfrost: Promote midgard_program to panfrost/util
We'll want Bifrost to reuse the same linking mechanisms for the most
part.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
2020-03-11 20:28:20 +00:00
Samuel Pitoiset
529c0ba219 gitlab-ci: build RADV in meson-i386 to avoid 32-bit build failures
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4044>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4044>
2020-03-11 19:30:13 +00:00
Samuel Pitoiset
f0178f516f radv: fix 32-bits build (again)
Fixes: dcfc08f5b8 ("radv/sqtt: describe begin/end command buffers with user markers")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4044>
2020-03-11 19:30:13 +00:00
Marek Olšák
fb477cc421 mesa: don't unroll glMultiDrawElements with user indices for gallium
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
2020-03-11 18:45:28 +00:00
Marek Olšák
70298ec4c0 gallium: add PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
2020-03-11 18:45:28 +00:00
Marek Olšák
510bd474e6 vbo: fix vbo_copy_vertices for GL_PATCHES and adjacency primitive types
Fixes: 4c6323c49f - vbo: handle GS and tess primitive types when splitting Begin/End

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
2020-03-11 18:45:28 +00:00
Marek Olšák
218dfd8c1a vbo: fix transitions from glVertexN to glVertexM where M < N
Fixes: 1f6e53e2 "vbo: don't store glVertex values temporarily into exec"

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
2020-03-11 18:45:28 +00:00
Marek Olšák
ec7d48afc4 vbo: use vbo_exec_wrap_upgrade_vertex for glVertex in ATTR_UNION
We can't decrease the size for glVertex before a flush,
so use vbo_exec_wrap_upgrade_vertex directly.

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
2020-03-11 18:45:28 +00:00
Marek Olšák
a398a9d7e7 st/mesa: keep serialized NIR instead of nir_shader in st_program
This decreases memory usage, because serialized NIR is more compact.

The first variant is created from nir_shader for uncached shaders.
All other variants are created from serialized NIR.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2909>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2909>
2020-03-11 18:17:46 +00:00
Michel Dänzer
86d270cde4 gitlab-ci: Don't restrict ppc64el/s390x build jobs to gstreamer runners
The packet runners have beefier CPUs now and don't seem to run into
test timeouts anymore.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4128>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4128>
2020-03-11 17:20:40 +00:00
Andres Gomez
bbdf215fbd gitlab-ci: Sort packages to install alphabetically
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-03-11 16:17:20 +02:00
Andres Gomez
f5235a5b73 gitlab-ci: Remove unneeded python3-pilkit dependency
It was added with tracie, but it doesn't depend on it.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-03-11 16:17:05 +02:00
Andres Gomez
52c53c4a49 gitlab-ci: Fix indentation and dangerous "\" in the last multiline line
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-03-11 16:16:56 +02:00
Chris Lord
b760ccfedb vc4: Fix query_dmabuf_modifiers mis-reporting external_only property
vc4_screen_query_dmabuf_modifiers doesn't consider that the given format
may only be supported by lowering, which only happens for external
textures.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4063>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4063>
2020-03-11 09:10:13 +00:00
Timur Kristóf
61f2e8d9bb aco: Don't store TCS outputs to LDS when we're sure that none are read.
This allows us not to write an output to LDS, even if it has
an indirect offset.

No pipeline DB changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
9b36d8c23a aco: Only write TCS outputs to LDS when they are read by the TCS.
Note that tess factors are always read at the end of the shader,
so those are still always saved to LDS.

Totals from affected shaders:
VGPRS: 25244 -> 25164 (-0.32 %)
Code Size: 1768268 -> 1690804 (-4.38 %) bytes
Max Waves: 4947 -> 4953 (0.12 %)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
4dcca26945 aco: Store tess factors in VMEM only at the end of the shader.
This optimizes out several superfluous stores of the tess factors,
especially if the shader wrote those outputs multiple times.

Pipeline DB changes on GFX10:
Totals from affected shaders:
SGPRS: 30384 -> 29536 (-2.79 %)
Code Size: 2260720 -> 2214484 (-2.05 %) bytes

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
8c3ab49c6b aco: Don't generate an if when the first part of a merged HS or GS is empty.
In some cases (eg. in a few tessellation CTS tests) the VS part of
a merged HS is completely empty. Let's not generate a divergent if
in these cases. (LLVM also doesn't do it.)

No pipeline DB changes, only affects the CTS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
b969501398 radv: Enable ACO on all stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
cec6a856e5 aco: Enable running TES as ES, including merged TES+GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
4fe5eadfae radv: Enable ACO for TES when there is no GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
926bdfae7d aco: Implement loading TES inputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
ec56a7093c aco: Enable streamout when TES runs on the HW VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
6047e51430 aco: Store TES outputs when TES runs on the HW VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
1d9d1cbce9 aco: Use TES output info when TES runs on the VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:11 +00:00
Timur Kristóf
0e8f4baede aco: Setup tessellation evaluation shader variables.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
80d281c6dc radv: Enable ACO for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
a952bf3946 aco: Fix LS VGPR init bug on affected hardware.
Vega 10 and Raven have a HW bug: when the HS thread count is zero,
the LS input arguments are loaded in the wrong registers. This commit
works around this by using the registers where the data actually is,
for the affected arguments.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
57a7d58c5d aco: Store VS outputs correctly when tessellation is used.
When tessellation is used, the VS runs on the HW LS stage (merged
into HS on GFX9-10). This commit enables such VS to store its
outputs properly in LDS so that the TCS can load them as its
per-vertex inputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
7b7f196fbc aco: Implement tessellation control shader input/output.
Tessellation control shaders can have per-vertex inputs,
and both per-vertex and per-patch outputs. TCS can not only store,
but also load their outputs.

The TCS outputs are stored in RING_HS_TESS_OFFCHIP in VMEM, which
is where the TES reads them from. Additionally, the are also stored
in LDS to make sure they can be loaded fast when read by the TCS.

Tessellation factors are always just stored in LDS.
At the end of the shader, the first shader invocation reads these
from LDS and writes them to RING_HS_TESS_FACTOR in VMEM, and
additionally to RING_HS_TESS_OFFCHIP when they are read by
the Tessellation Evaluation Shader.

This implementation matches the memory layouts used by radv_nir_to_llvm.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
655c050119 aco: Fix combining DS additions in the optimizer.
Previously, it was calculated incorrectly for 64-bit writes and reads.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
c70b0d0267 aco: Slight fix to lds_store and lds_load.
This commit fixes lds_store and lds_load so that they can
properly support 32 and 64-bit loads and stores; and makes
them a little more reusable so they can be used by
tessellation control shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
db93af5f1b aco: Refactor VS output stores in preparation for tessellation.
This commit takes the new helpers into use by the VS output
store function. This function is also where the VS outputs will
be handled when the VS runs on the HW LS stage.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
0062bb04ac aco: Refactor load_per_vertex_input in preparation for tessellation.
This commit carves out the GS per-vertex input load, and takes the
new helper functions into use.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
4e692d65e1 aco: Introduce new helpers for calculating address offsets.
These helpers are going to make it unnecessary to reimplement the
(almost) same address offset calculation in mulitple places.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
19d5dc9cee aco: Introduce new VMEM load/store helpers.
These are going to be used for loading and storing inputs
and outputs in various stages, such as GS, TCS and TES.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
4fc1da208e aco: Remove esgs_itemsize from LDS alignment calculation.
It was problematic to have it, because some shader stages might
not even know about the esgs_itemsize, for example TCS and
the merged VS+TCS stages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
ca342701c5 aco: Extract LDS alignment calculation to a separate function.
This function is going to be reused in multiple functions when
storing or loading something in the LDS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
fe80f22470 aco: Remove vertex_geometry_gs assertion from merged shaders.
We are going to support more kinds of merged shaders, such
as vertex_tess_control_hs and tess_eval_geometry_gs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
f53d31fb9b aco: Use mesa shader stage when loading inputs.
This makes it more clear which stages should load these inputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
9016711273 aco: Setup correct HW stages when tessellation is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
89ff5b1e51 aco: Implement load_view_index for TCS and TES.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
aa5eed673c aco: Implement memory_barrier_tcs_patch.
TCS outputs are going to be written to LDS, so it
has to use memory_barrier_shared in order to ensure
that it waits for LDS writes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
a8d15ab6da aco: Implement control_barrier for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
2489e4dfd1 aco: Implement load_invocation_id for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
5107b0312a aco: Implement load_patch_vertices_in.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
6edf6ad130 aco: Implement load_primitive_id for tessellation shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
754837f3b5 aco: Implement load_tess_coord.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
9ca2b254ca aco: Setup tessellation control shader variables.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
7b3316f3c9 aco: Extract setup_gs_variables into a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Timur Kristóf
346bd0c623 radv: Move some helper functions to the radv_shader.h header file.
Move calculate_tess_lds_size and get_tcs_num_patches to radv_shader.h
ACO will need to call these functions too.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
2020-03-11 08:34:10 +00:00
Pierre-Eric Pelloux-Prayer
78d42d41d4 vdpau: remove bogus assert
The assert introduced by 24f2b0a856 triggers when an application
requests a chroma_type that's different to the one from the
PIPE_VIDEO_CAP_PREFERED_FORMAT (before this change the chroma_type
was set but ignored).

So restore this behavior and ignore the chroma_type.

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Fixes: 24f2b0a856 ("gallium/video: remove pipe_video_buffer.chroma_format")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4104>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4104>
2020-03-11 08:17:07 +00:00
Samuel Pitoiset
b6cebf6439 radv: do not recursively begin/end render pass for meta operations
To avoid breaking SQTT user markers that are emitted to report
barriers and layout transitions to RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
2020-03-11 07:54:43 +00:00
Vasily Khoruzhick
c78e88e8a6 lima/gpir: print acc ops even if we have only one source
floor and sign have only one source, so we need to print acc ops
even if src1 is unused.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
2020-03-11 07:36:45 +00:00
Vasily Khoruzhick
492ef353fb lima/gpir: improve disassembler output
Print each op at new line and add unit name suffix for each op.
It improves readability a bit and gives us a hint what unit
was used for particular op.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
2020-03-11 07:36:44 +00:00
Vasily Khoruzhick
bcbc2b61b5 lima: print gp uniforms if gp debug is enabled
Since we keep other constants there as well it's useful for reading disassembly.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
2020-03-11 07:36:44 +00:00
Samuel Pitoiset
8f5543990e gitlab-ci: add rules:changes for RADV
Including mesa_core_file_list is probably not the best but it's
better than nothing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117>
2020-03-11 08:04:05 +01:00
John Stultz
be22995ecf gallium: hud_context: Fix scalar initializer warning.
When trying to build mesa/master under AOSP, I've run into the
following error:

external/mesa3d/src/gallium/auxiliary/hud/hud_context.c:1821:31: error: braces around scalar initializer [-Werror,-Wbraced-scalar-init]
   struct sigaction action = {{0}};
                              ^~~
1 error generated.

This patch addresses this by switching to using memset instead of
using an initializer.

Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
2020-03-11 02:52:58 +00:00
John Stultz
09fbde830f panfrost: Move pan_afbc.c file to the the right Makefile.source file
It seems pan_afbc.c was added to the wrong Makefile.sources file.

So fix this, so we don't run into build issues with mesa/master
trying to build under AOSP.

Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
2020-03-11 02:52:58 +00:00
John Stultz
67aae8f98f freedreno: Add ir3_cf.c and ir3_delay.c to Makefile.sources
This patch adds missing ir3_cf.c and ir3_delay.c files to
the Makefile.sources file to address build issues seen
when trying to build mesa/master on AOSP

Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
2020-03-11 02:52:58 +00:00
Marek Olšák
2dc300421d gallium/cso_context: remove cso_delete_xxx_shader helpers to fix the live cache
With the live shader cache, equivalent shaders can be backed by the same
CSO. This breaks the logic that identifies whether the shader being deleted
is bound.

For example, having shaders A and B, you can bind shader A and delete
shader B. Deleting shader B will unbind shader A if they are equivalent.

Pierre-Eric figured out the root cause for this issue.

Fixes: 0db74f479b - radeonsi: use the live shader cache
Closes: #2596

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078>
2020-03-10 22:19:47 -04:00
Eric Engestrom
1fa259b035 vulkan/wsi: fix cleanup when dup() fails
Fixes: f5433e4d6c ("vulkan/wsi: Add modifiers support to wsi_create_native_image")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137>
2020-03-10 22:43:25 +00:00
Karol Herbst
6e035c01fb Revert "gallium: make handles of set_global_binding 64 bit"
This reverts commit e1ffb72a05
2020-03-10 22:41:26 +00:00
Karol Herbst
e1ffb72a05 gallium: make handles of set_global_binding 64 bit
needed by CL

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072>
2020-03-10 22:06:19 +00:00
Alyssa Rosenzweig
0541350e3a pan/bi: Implement comparison opcodes via BI_CMP
Pretty straightforward for the moment. Ideally these would be fused into
csel/branches but that will come a bit later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:26:00 +00:00
Alyssa Rosenzweig
6409896ca7 pan/bi: Print source types unconditionally
We track them all now, let's use them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:26:00 +00:00
Alyssa Rosenzweig
20c7d57ede pan/bi: Specify comparison op for BI_CMP
...and adjust printing so we can use it as an op name.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:26:00 +00:00
Alyssa Rosenzweig
08ab7cecd9 pan/bi: Lower b2f to bcsel
Since we can get a zero for free and a one inlined into the constant,
the obvious turns out to be efficient (while allowing flexibility for
boolean size).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
d3823551b4 pan/bi: Implement nir_op_bcsel
No condition fusing yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
3a1baafede pan/bi: Import algebraic pass from midgard
We'll need some of these at least.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
55f0d811e4 pan/bi: Add isub op
Can't be a regular ADD since there's no negate modifier for integers
(it's a different opcode entirely).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
acab788578 pan/bi: Disable lower_sub
For float, fixing up the modifier ourselves is easy. For int, we have a
dedicated isub instruction anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
1216a63ff2 pan/bi: Implement fabs, fneg as fmov with mods
Fusing will come later with the appropriate NIR support.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
8ed79c9ed7 pan/bi: Handle special ops in NIR->BIR
Only on supported GPUs at the moment; for older Bifrost that don't
support these, I'm not sure yet where the right place to do the lowering
is. NIR algebraic rules would be "nice" but probably impractical -- but
it wouldn't be hard to do it directly in BIR (as a lowering pass or
alternative implementation).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
b674e39d72 pan/bi: Add BI_SPECIAL_* enum
To disambiguate the different special ops from each other.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
c862234ab3 pan/bi: Add a bunch of ALU ops
These are all regular ALU ops found in GLES2 which makes them
particularly nice targets at the moment. Just translate straight to our
IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
5a5896cd76 pan/bi: Implement fsat as mov.sat
Soon we'll have a NIR support to handle this the Right Way along with
pos and sat_signed support, but we'll always need the fallback anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
48e50efd5d pan/bi: Allow inlining constants
This will allow us to optimize out the constant moves (although that
will require a DCE pass which has yet to be written).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
929baf3f88 pan/bi: Add initial handling of ALU ops
We do the bare minimum translation, just enough for fmov/fadd/fmul right
now with no modifiers / inlined constants / etc. The rest is to come!
But hopefully I got bitsize handling right this time around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
330e9a6696 pan/bi: Lower vec* to writemasks in NIR
I was hoping not to tread down this path but it seems inevitable now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
69c66ffd84 pan/bi: Remove bi_load
This is now made redundant with writemasks, so let's regularize the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
e9d480ca1b pan/bi: Introduce writemasks
I feel so dirty. But this will let the IR be a lot more flexible seeing
as we really are vector in a certain sense (I/O, small types)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
795646d8f8 pan/bi: Generalize swizzles to avoid extracts
We'd really rather not emit extracts. We are approaching on a vector IR
anyway which is annoying but really necessary to handle I/O and fp16
correctly. So let's just go all the way and deal with swizzles and masks
within reason; it'll still be somewhat saner in the long-term.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Alyssa Rosenzweig
9b8cb9f5ae panfrost: Move mir_to_bytemask to common code
...also so we can start sharing code properly between the panfrost
compilers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
2020-03-10 19:25:59 +00:00
Rob Clark
ba03e308b6 freedreno/fdperf: set locale
Set local to get numbers printed w/ commas.. much easier to read that
way.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
2020-03-10 16:52:02 +00:00
Rob Clark
30dd059925 freedreno/computerator: add performance counter support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
2020-03-10 16:52:02 +00:00
Jason Ekstrand
af68b0d346 vulkan/wsi: Return an error if dup() fails
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
2020-03-10 16:39:27 +00:00
Jason Ekstrand
34d2637fa7 vulkan/wsi: Don't leak the FD when GetImageDrmFormatModifierProperties fails
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
2020-03-10 16:39:27 +00:00
Rob Clark
3c96e25de7 freedreno/ir3: try to avoid syncs
Update postsched to be better aware of where costly (ss) syncs would
result.  Sometimes it is better to allow a nop or two, to avoid a
sync quickly after an SFU.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
cc82521de4 freedreno/ir3: round-robin RA
In the second (scalar pass) use the information about # of registers
used in the first pass as the target max, and round-robin within that
range.  This generally gives the post-RA sched pass more opportunities
to re-order instructions to remove nop's.

Also, we can be a bit clever when assigning dest registers for SFU
instructions, by picking the register used for it's src (if available
and already assigned).  This avoids some (ss) syncs caused by write
after read hazards.  (Ie. the SFU instruction will read it's own src
before writing dest.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
b2b349096f freedreno/ir3: track register usage in first RA pass
We'll use the feedback from the first pass to select a target register
usage in the second pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
9ae93be8fb freedreno/ir3: fix has_latency_to_hide
Also count tex-prefetch instructions.  And only let the no-latency rule
kick in for frag shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
b6eb11295a freedreno/ir3: split out has_latency_to_hide()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
dd2e050a84 util/ra: move NO_REG to header
In the select_reg callback, I want to be able to determine if a given
node is already assigned, and if so what physical register has been
assigned.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
36aed70b59 util/ra: spiff out select_reg_callback
Add a parameter so the callback can know which node it is selecting a
register for.  And remove the graph parameter, as it is unused by
existing users, and somewhat unnecessary (ie. the callback data could
be used instead).

And add a comment so $future_me remembers how this works.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
b3efa2a4da freedreno: fix FD_MESA_DEBUG=inorder
Fixes: 2c07e03b79 ("freedreno: allow ctx->batch to be NULL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
752b9985be freedreno/ir3: add simplified stall estimation
Doesn't take into account stalls that result from a register written in
a different block, etc.  But this should be more useful than just using
number of (ss)'s by trying to estimate how costly a given sync is.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
64ae2ef8bb freedreno/ir3: remove extra nops inserted in scheduler
They were inserting a nop between back to back SFU instrucions.  But
that doesn't actually appear to be required.  And they get stripped out
later anyways before legalize.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
ad2ff7a278 freedreno/computerator: add hrsq/hlog2/hexp2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
4a8e4c18d2 freedreno/ir3: also lower lowp frag outputs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Rob Clark
3535797e8c nir/print: show variable precision
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
2020-03-10 16:01:39 +00:00
Danylo Piliaiev
10eee6d8c6 intel/tools: Fix compilation with UBSan
Compilation failed with several similar errors:

../src/intel/tools/aub_read.c:322:4: error: case label does not reduce to an integer constant
  322 |    case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_HEADER):

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132>
2020-03-10 15:20:26 +00:00
Mathias Fröhlich
74be835a84 i965: Use gl_vertex_format in brw_vertex_element.
State upload needs to cope with the vertex format
rather than with the full attribute data.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
e62b82a693 i965: Make use of the vertex format functions in i965.
v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
cf929823bf mesa: Provide gl_vertex_format accessors.
Provide the same set of VAO and current value gl_vertex_format
accessor functions like we have for the gl_array_attributes.
For most purpose the vertex format is what we need.

v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
1641c872ed mesa: Remove now unused _mesa_draw_attrib.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
305724dd7b mesa: Remove now unused _mesa_draw_attrib_and_binding.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
4ccda7bfd9 i965: Remove glbinding from brw_vertex_element.
v2: Rebase.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
38db4f1720 i965: Reorder workaround flags computation.
Vertex processing workaround flags can be split into
array and current vertex attributes. By that we
can use specific access functions for these different
vertex attribute kinds. This finally obsoletes
some access functions that I introduced last winter
for a smooth transition.

v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
e53fd073be i965: Split merge_inputs and clear_buffers.
The merge_inputs function handles that part that changes when the
inputs change. The clear_buffers function triggers when we may need
a new upload. Thus the merge_inputs can be limited to be once
per brw_draw_prims.

v2: Move declaration of attribute index into the for scope.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
de579ffba2 i965: Test original vertex array pointer to skip array upload.
Rather than do a NULL pointer check on a pointer that may be offset by the
min-max index range of an GL draw operation, execute the NULL test on the
original vertex array pointer.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
b684030c3a i965: Use the VAOs binding information in array setup.
The change basically reimplements array setup by walking
the gl_contex::Array._DrawVAO on a per binding sequence.
In this way we can make direct use of the application
provided minimum set of buffer objects and emit fewer relocs.

v2: Rebase onto:
    compiler: Move double_inputs to gl_program::DualSlotInputs
v3: Rebase onto introduction of gl_vertex_format
v4: Reorder and extend patch series.
v5: Split out two hunks into seperate patches.
v6: Avoid using GL* types.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
e1f2c84282 i965: Use 32 bit u_bit_scan for vertex attribute setup.
The vertex array object contains 32 vertex arrays. By that we cannot
reference more then these in the vertex shader inputs. So, we can use
the 32 bits u_bit_scan function to iterate the vertex shader inputs
and place an assert that only these are present. Also place an other
assert that the vertex array setup in i965 does not overrun the
enabled array in brw_context:🆚:enabled.

v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:37 +00:00
Mathias Fröhlich
0ea3ca3eca iris: Move down iris_emit_sbe_swiz in profiles.
Harvest the information gathered in the previous patch
inside of iris.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:36 +00:00
Mathias Fröhlich
630154e77b i965: Move down genX_upload_sbe in profiles.
Avoid looping over all VARYING_SLOT_MAX urb_setup array
entries from genX_upload_sbe. Prepare an array indirection
to the active entries of urb_setup already in the compile
step. On upload only walk the active arrays.

v2: Use uint8_t to store the attribute numbers.
v3: Change loop to build up the array indirection.
v4: Rebase.
v5: Style fix.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
2020-03-10 14:28:36 +00:00
Boris Brezillon
b1a6a15aaf panfrost: Get rid of ctx->payloads[]
Now that vertex/tiler payloads are re-initialized at draw/launch_grid
time we can get of of the ctx->payloads[] field and allocate those
payload templates on the stack.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
093da77ce6 panfrost: Use ctx->active_prim in panfrost_writes_point_size()
Check ctx->active_prim instead of prefix.draw_mode so we can eventually
get rid of ctx->payloads.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
d66ef690d1 panfrost: Re-init the VT payloads at draw/launch_grid() time
Doing that should help us avoiding state leaks between draw/launch_grid
calls.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
836686daf3 panfrost: Move panfrost_emit_varying_descriptor() to pan_cmdstream.c
Move panfrost_emit_varying_descriptor() to pan_cmdstream.c where other
emit functions live and adjust the prototype to be consistent with other
emit helpers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
b95530bef2 panfrost: Move panfrost_emit_vertex_data() to pan_cmdstream.c
Move panfrost_emit_vertex_data() to pan_cmdstream.c where other emit
functions live, and adjust the prototype for consistency.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
251e685e72 panfrost: Inline panfrost_queue_draw() and panfrost_emit_for_draw()
Now that panfrost_queue_draw() and panfrost_emit_for_draw() are
small enough, we can move the code to panfrost_draw_vbo() and have all
vt and emit calls grouped in one place.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
5d9995e82c panfrost: Move vertex/tiler payload initialization out of panfrost_draw_vbo()
Add a panfrost_vt_set_draw_info() function taking care of the draw
related initialization of the vertex and tiler payloads.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
13881a4dad panfrost: Move streamout offset update out of panfrost_draw_vbo()
That's part of out attempt to shrink panfrost_draw_vbo().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
046c154585 panfrost: Rename panfrost_stage_attributes()
panfrost_stage_attributes() is emitting mali_attr_meta descriptors, so
let's rename it accordingly and move it to pan_cmdstream.c.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
dcc0b1ff01 panfrost: Move the mali_attr.src_offset adjustment to a sub-function
Create a panfrost_vertex_state_upd_attr_offs() helper to adjust
the attr_meta src_offsets.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
575f62ea02 panfrost: Emit attribute descriptors after patching the templates
Patching attribute desc when they are in cacheable memory should be
more efficient.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
4a2ee61a22 panfrost: Prepare attribute for builtins at state creation time
The attribute meta slots reserved for gl_VertexID and gl_InstanceID
can be pre-filled at state creation time. Only the index needs to be
adjusted when attributes are generated.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
b692ab076a panfrost: Ignore BO start addr when adjusting src_offset
BOs are guaranteed to be aligned on 4K which inherently guarantees the
64 byte alignment.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
128820b886 panfrost: Drop initial mali_attr_meta.src_offset assignment
The mali_attr_meta.src_offset is initialized to
pipe_vertex_element.src_offset at vertex element creation time, but
this field is then adjusted when the descrptors are emitted. Let's
use the pipe_vertex_element data we saved earlier and drop this initial
assignment.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
528384cb6d panfrost: Add an helper to emit a pair of vertex/tiler jobs
Add the panfrost_emit_vertex_tiler_jobs() helper and use it in
panfrost_queue_draw().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
8e0a08bc8e panfrost: Move sampler/tex descs emission helpers to pan_cmdstream.c
Move panfrost_upload_texture_descriptors() and
panfrost_upload_sampler_descriptors() to pan_cmdstream.c where other
cmdstream related helpers live. While at it, change their prototype
and name to make it consistent with the other helpers and prepare
things for ctx->payloads[] removal.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
2b946a1d2b panfrost: Add a panfrost_sampler_desc_init() helper
It just makes sense to group all HW descriptor initilization logic in
pan_cmdstream.c, so let's move this code out of
panfrost_create_sampler_state().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
b02f97c875 panfrost: Prepare shader_meta descriptors at emission time
This way we avoid potential state leaks and keep the shader_meta
initialization in once place. The time spent preparing the shader
descriptors should be negligible compared to the time spent pushing
those descriptors to the transient buffer (remember we are writing to
non-cacheable memory here).

Note that we might get back to some sort of shader_meta descriptor
caching at some point if that proves necessary, but now we have those
panfrost_frag_meta_xxx_update() helpers now where xxx maps directly to
a CSO bind, which should ease desc template updates.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
55e014336f panfrost: Prepare things to get rid of panfrost_shader_state.tripipe
panfrost_shader_state.tripipe is used as a template for shader_meta
desc emission, but shader_meta desc preparation time should be negligible
compared to desc emission time (remember we are writing to non-cacheable
memory here). Let's prepare for generating the the shader_meta desc
entirely at draw time by adding the necessary fields to
panfrost_shader_state.

Note that we might brink back some sort of shader_meta desc caching at
some point, but let's simplify things a bit for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
e94076f8f5 panfrost: Add an helper to update the rasterizer part of a tiler job desc
That's part of our attempt to make panfrost_emit_for_draw() a bit more
dry and eventually get rid of it by inlining the code in
panfrost_draw_vbo(). This is just one step in this direction.

Note that we get rid of the panfrost_rasterizer.tiler_gl_enables field
along the way, as setting/clearing those bits at draw time instead of
doing when the state is created should make a huge difference. We might
get back to pre-computed VT descs at some point, but let's keep things
simple for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
56aeb921e9 panfrost: Add an helper to update the occclusion query part of a tiler job desc
That's part of our attempt to make panfrost_emit_for_draw() a bit more
dry and eventually get rid of it by inlining the code in
panfrost_draw_vbo(). This is just one step in this direction.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
5f043cc776 panfrost: Simplify panfrost_emit_for_draw() and make it private
Now that panfrost_launch_grid() no longer calls panfrost_emit_for_draw(),
we can keep it private to pan_context.c and drop all compute-related
stuff.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
8ac17139b1 panfrost: Stop using panfrost_emit_for_draw() for compute jobs
We actually need a small subset of what's done in
panfrost_emit_for_draw() when emitting compute jobs, so let's copy
what we need directly in panfrost_launch_grid() instead of re-using
this function whose initial purpose was to generate vertex/tiler jobs
for draw operations.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
0d75eb002e panfrost: Move panfrost_attach_vt_framebuffer() to pan_cmdstream.c
Move panfrost_attach_vt_framebuffer() to pan_cmdstream.c and change its
name to panfrost_vt_attach_framebuffer() so we can use a consistent
prefix (panfrost_vt_) for all helpers initializing/updating
midgard_payload_vertex_tiler fields.

Note that the function only initializes one VT object now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:34 +01:00
Boris Brezillon
5d33d42b4d panfrost: Dissociate shader meta patching from the desc emission
Right now we emit two shader descriptors for the fragment shader, one
when panfrost_patch_shader_state() is called, and the final one
including both the shader_meta and the blend RT descriptors.
The first generated fragment shader descriptor is never used, since the
second one overrides the postfix.shader pointer.

Let's dissociate the state patching logic from the descriptor emission
so we don't upload descriptors that are never used.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
36725be4d9 panfrost: Move shared mem desc emission out of panfrost_launch_grid()
Let's move the shared memory descriptor emission to a dedicated function
living with its pairs in pan_cmdstream.c.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
0b735a2d80 panfrost: Move the const buf emission logic out of panfrost_emit_for_draw()
Let's move the constant buffer emission logic in a dedicated helper
to make panfrost_emit_for_draw() a bit more dry.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
a72bab1c3e panfrost: Move viewport desc emission out of panfrost_emit_for_draw()
Let's move the viewport descriptor emission logic to a dedicated helper
in order to shrink a bit the panfrost_emit_for_draw().

Note that this helper is placed in a new pan_cmdstream.c file where we
will group all cmdstream related helpers (everything that's related to
HW descriptor initialization emission).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
79f8850527 panfrost: Move the batch stack size adjustment out of panfrost_queue_draw()
That's part of our attempt to sanitize panfrost_queue_draw(),
panfrost_draw_vbo() and panfrost_emit_for_draw(). The new
panfrost_batch_adjust_stack_size() helper is placed in pan_job.c, where
all batch related functions live.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
b28f4bb67c panfrost: Add an helper to retrieve the currently active shader state
Doing that improves readability and helps avoiding code duplication.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Boris Brezillon
a0402f7960 panfrost: Assign primitive_size.pointer only if writes_point_size() returns true
Checking vs->writes_point_size is not enough, as we might have a vertex
shader writing point size, but a primitive that's not MALI_POINT. That
currently works because emit_varying_descriptor() is called before the
primitive_size.constant field is update, but let's make the logic more
robust, just in case things are re-ordered at some point.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>
2020-03-10 12:47:33 +01:00
Samuel Pitoiset
24db276d11 radv/sqtt: describe pipeline and wait events barriers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 10:05:40 +01:00
Samuel Pitoiset
c04e9befc0 radv/rgp: bump the instrumentation spec version to 1
RGP expects the version to be 1, otherwise it doesn't display the
barriers (including layout transitions) correctly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 10:05:40 +01:00
Samuel Pitoiset
ac0d5b6b11 radv/sqtt: describe render pass color/depthstencil clears
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 10:05:40 +01:00
Samuel Pitoiset
b829fbb7f0 radv/sqtt: describe draw/dispatch and emit event markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 10:05:40 +01:00
Samuel Pitoiset
dcfc08f5b8 radv/sqtt: describe begin/end command buffers with user markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 09:58:02 +01:00
Samuel Pitoiset
31ecf0b17d radv: initial implementation of the driver internal layer SQTT
This layer is used to emit SQTT user markers to command buffers. It
currently only emits API markers but it will consolidated soon with
barrier markers and more.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 09:57:59 +01:00
Samuel Pitoiset
be700775dc radv/sqtt: add a helper that emits thread trace userdata markers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 09:57:56 +01:00
Samuel Pitoiset
f4fbcfe818 radv: use device entrypoints from the SQTT layer if enabled
This allows to override RADV device entrypoints if the prefix
is 'sqtt' instead of 'radv'.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 09:57:53 +01:00
Samuel Pitoiset
9c88e4a272 radv/entrypoints: declare a driver internal layer for SQTT
Some Vulkan commands will be overriden to emit user SQTT markers.
These markers are then used by the Radeon GPU Profiler to display
timings, barrier operations (cache flushes, pipeline stalls, layout
transitions) and more.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
2020-03-10 09:57:49 +01:00
Boris Brezillon
a64599a303 panfrost: Pass the sampler view format when creating a tex descriptor
A sampler can use a different format than the native texture format.
Let's pass the sampler format instead of the native texture format when
creating a texture descriptor.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101>
2020-03-10 08:43:08 +01:00
Boris Brezillon
ce845f44e9 Revert "panfrost: Z24 variants should be sampled as R32UI"
Commit 0406ea4856 ("panfrost: Z24 variants should be sampled as
R32UI") causes a regression when depth textures are sampled.

It's still not clear how MALI_Z32 can work for for Z32 and Z24{S,X}8,
but let's leave that question for later.

Reported-by: Icecream95 <ixn@keemail.me>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101>
2020-03-10 08:42:05 +01:00
Tomeu Vizoso
8d0ec5b8a6 gallium: Add forgotten docs for new CAPs related to transform feedback
These three caps were missing docs.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4115>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4115>
2020-03-10 07:26:13 +01:00
Vasily Khoruzhick
251c6991a3 lima: enable minmax cache for index buffers
Re-use minmax cache for index buffers from panfrost.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051>
2020-03-10 02:41:27 +00:00
Vasily Khoruzhick
53d6bb9fc6 panfrost: split index cache into shared part
Split it into shared part since we're going to re-use it in lima.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051>
2020-03-10 02:41:27 +00:00
Marek Olšák
040a7117c3 st/mesa: fix a possible crash with selection and feedback modes
The index bounds are always valid without an index buffer, but they won't be.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986>
2020-03-09 21:26:55 -04:00
Marek Olšák
7b0e043d48 st/mesa: flush the bitmap cache before st/dri and vbo flushes
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986>
2020-03-09 21:26:55 -04:00
Francisco Jerez
45d4665dc7 intel/fs: Fix workaround for VxH indirect addressing bug under control flow.
The current workaround for this hardware bug involved marking the ADD
instruction used to initialize the address register as NoMask on
Gen12, which was based on the assumption that the problem was caused
by a hardware bug affecting the application of the execution mask to
the address register write.

However that doesn't seem to be the case: The address register write
was working correctly, the real problem leading to hangs on TGL is
that the indirect addressing logic is unable to deal with garbage
values in the address register (e.g. misaligned offsets), even for
channels which are currently inactive due to non-uniform control flow.
The current workaround isn't able to avoid that situation in general,
since the result of the NoMask ADD instruction for a dead channel is
calculated based on the corresponding (dead) component of the
indirect_byte_offset source, which would still be undefined in the
likely case that the source was initialized under control flow itself.

This would lead to hangs whenever MOV_INDIRECT was used under
non-uniform control flow in some scenarios like a tessellation shader
from GFXBench5/gl_4 (AKA Car Chase) on TGL.  In addition I've managed
to reproduce the same issue on earlier platforms by initializing the
whole address register with garbage before the ADD instruction, so
this seems to be a long-standing issue we have avoided mostly by luck.

This patch fixes the problem and applies the workaround to all
platforms, since even when the hardware is able to deal with garbage
address values without hanging there might be a significant
performance cost from reading random GRF registers due to the useless
extra EU cycles spent fetching registers for dead channels and due to
the potential for unintended serialization with respect to other
random instructions that could be executed in parallel, which may have
had a cost of the order of hundreds of cycles in the worst case
scenario.

Fixes: f93dfb509c "intel/fs: Write the address register with NoMask for MOV_INDIRECT"
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-03-10 00:42:50 +00:00
Ian Romanick
c144875f62 intel/fs: Allow NOT instructions in conditional discard optimization
I don't know why I explicitly disallowed NOT in the first place. :(

All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14549846 -> 14549770 (<.01%)
instructions in affected programs: 12934 -> 12858 (-0.59%)
helped: 76
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.13% max: 5.56% x̄: 1.04% x̃: 0.90%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -1.25% -0.84%
Instructions are helped.

total cycles in shared programs: 203793967 -> 203792696 (<.01%)
cycles in affected programs: 77920 -> 76649 (-1.63%)
helped: 67
HURT: 1
helped stats (abs) min: 2 max: 36 x̄: 19.00 x̃: 16
helped stats (rel) min: 0.04% max: 4.68% x̄: 2.35% x̃: 2.28%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -20.75 -16.63
95% mean confidence interval for cycles %-change: -2.57% -2.05%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
2020-03-09 16:46:28 -07:00
Ian Romanick
ba2fa1ceaf intel/fs: Do cmod prop again after scheduling
Pre-RA scheduling can create more opportunities for CMOD propagation.
This takes advantage of that.

It may be worth doing this again in post-RA scheduling, but there are
additional problems there.

I'm a little torn about the use of the OPT() macro.  On the one hand, it
would be confusing to see dumps from INTEL_DEBUG=optimizer that don't
match the final output.  On the other hand, since register allocation
can fail, the same pass can be run multiple times.  Each time one or
both passes might or might not make progress.  This would also lead to
incongruous, confusing output.

Ice Lake
total instructions in shared programs: 14549808 -> 14548529 (<.01%)
instructions in affected programs: 231985 -> 230706 (-0.55%)
helped: 632
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 2.02 x̃: 1
helped stats (rel) min: 0.05% max: 2.56% x̄: 0.57% x̃: 0.41%
95% mean confidence interval for instructions value: -2.25 -1.79
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.

total cycles in shared programs: 203770850 -> 203776599 (<.01%)
cycles in affected programs: 2495653 -> 2501402 (0.23%)
helped: 282
HURT: 197
helped stats (abs) min: 1 max: 242 x̄: 20.37 x̃: 16
helped stats (rel) min: <.01% max: 11.65% x̄: 0.91% x̃: 0.64%
HURT stats (abs)   min: 2 max: 609 x̄: 58.35 x̃: 20
HURT stats (rel)   min: <.01% max: 10.97% x̄: 1.35% x̃: 0.66%
95% mean confidence interval for cycles value: 5.27 18.73
95% mean confidence interval for cycles %-change: -0.16% 0.21%
Inconclusive result (%-change mean confidence interval includes 0).

LOST:   0
GAINED: 2

Skylake
total instructions in shared programs: 13447708 -> 13446594 (<.01%)
instructions in affected programs: 216813 -> 215699 (-0.51%)
helped: 623
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 1.79 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.42%
95% mean confidence interval for instructions value: -1.99 -1.59
95% mean confidence interval for instructions %-change: -0.63% -0.55%
Instructions are helped.

total cycles in shared programs: 193759224 -> 193762726 (<.01%)
cycles in affected programs: 2540035 -> 2543537 (0.14%)
helped: 249
HURT: 190
helped stats (abs) min: 2 max: 196 x̄: 16.67 x̃: 14
helped stats (rel) min: <.01% max: 4.71% x̄: 0.66% x̃: 0.62%
HURT stats (abs)   min: 2 max: 614 x̄: 40.27 x̃: 14
HURT stats (rel)   min: 0.02% max: 5.78% x̄: 0.86% x̃: 0.37%
95% mean confidence interval for cycles value: 2.57 13.39
95% mean confidence interval for cycles %-change: -0.11% 0.11%
Inconclusive result (%-change mean confidence interval includes 0).

LOST:   0
GAINED: 1

Broadwell
total instructions in shared programs: 13418631 -> 13417393 (<.01%)
instructions in affected programs: 243192 -> 241954 (-0.51%)
helped: 694
HURT: 0
helped stats (abs) min: 1 max: 31 x̄: 1.78 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.44%
95% mean confidence interval for instructions value: -1.95 -1.62
95% mean confidence interval for instructions %-change: -0.62% -0.55%
Instructions are helped.

total cycles in shared programs: 200822940 -> 200829128 (<.01%)
cycles in affected programs: 2128651 -> 2134839 (0.29%)
helped: 251
HURT: 226
helped stats (abs) min: 1 max: 200 x̄: 14.32 x̃: 12
helped stats (rel) min: <.01% max: 3.56% x̄: 0.60% x̃: 0.50%
HURT stats (abs)   min: 2 max: 611 x̄: 43.28 x̃: 18
HURT stats (rel)   min: 0.02% max: 7.03% x̄: 0.93% x̃: 0.54%
95% mean confidence interval for cycles value: 7.44 18.50
95% mean confidence interval for cycles %-change: 0.02% 0.23%
Cycles are HURT.

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 11569710 -> 11568829 (<.01%)
instructions in affected programs: 147862 -> 146981 (-0.60%)
helped: 487
HURT: 0
helped stats (abs) min: 1 max: 34 x̄: 1.81 x̃: 1
helped stats (rel) min: 0.12% max: 4.75% x̄: 0.57% x̃: 0.45%
95% mean confidence interval for instructions value: -2.03 -1.59
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.

total cycles in shared programs: 187079425 -> 187079437 (<.01%)
cycles in affected programs: 1088494 -> 1088506 (<.01%)
helped: 234
HURT: 124
helped stats (abs) min: 2 max: 282 x̄: 22.66 x̃: 16
helped stats (rel) min: 0.03% max: 7.88% x̄: 0.93% x̃: 0.75%
HURT stats (abs)   min: 1 max: 276 x̄: 42.86 x̃: 20
HURT stats (rel)   min: 0.03% max: 6.70% x̄: 0.99% x̃: 0.53%
95% mean confidence interval for cycles value: -5.54 5.61
95% mean confidence interval for cycles %-change: -0.41% -0.11%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 7746 -> 7740 (-0.08%)
spills in affected programs: 6 -> 0
helped: 1
HURT: 0

total fills in shared programs: 6264 -> 6258 (-0.10%)
fills in affected programs: 6 -> 0
helped: 1
HURT: 0

Sandy Bridge
total instructions in shared programs: 10688576 -> 10688177 (<.01%)
instructions in affected programs: 137875 -> 137476 (-0.29%)
helped: 358
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 1.11 x̃: 1
helped stats (rel) min: 0.15% max: 1.43% x̄: 0.35% x̃: 0.28%
95% mean confidence interval for instructions value: -1.18 -1.05
95% mean confidence interval for instructions %-change: -0.37% -0.32%
Instructions are helped.

total cycles in shared programs: 153397144 -> 153393046 (<.01%)
cycles in affected programs: 1220713 -> 1216615 (-0.34%)
helped: 255
HURT: 31
helped stats (abs) min: 1 max: 304 x̄: 16.71 x̃: 16
helped stats (rel) min: <.01% max: 6.70% x̄: 0.41% x̃: 0.31%
HURT stats (abs)   min: 1 max: 41 x̄: 5.29 x̃: 3
HURT stats (rel)   min: 0.02% max: 0.65% x̄: 0.16% x̃: 0.11%
95% mean confidence interval for cycles value: -17.44 -11.22
95% mean confidence interval for cycles %-change: -0.40% -0.29%
Cycles are helped.

Iron Lake
total instructions in shared programs: 8106894 -> 8105529 (-0.02%)
instructions in affected programs: 287197 -> 285832 (-0.48%)
helped: 1099
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 4.55% x̄: 0.67% x̃: 0.61%
95% mean confidence interval for instructions value: -1.29 -1.19
95% mean confidence interval for instructions %-change: -0.70% -0.64%
Instructions are helped.

total cycles in shared programs: 188347022 -> 188344266 (<.01%)
cycles in affected programs: 3740632 -> 3737876 (-0.07%)
helped: 758
HURT: 10
helped stats (abs) min: 2 max: 38 x̄: 3.68 x̃: 2
helped stats (rel) min: <.01% max: 1.00% x̄: 0.12% x̃: 0.08%
HURT stats (abs)   min: 2 max: 4 x̄: 3.20 x̃: 4
HURT stats (rel)   min: 0.03% max: 0.07% x̄: 0.06% x̃: 0.07%
95% mean confidence interval for cycles value: -3.82 -3.35
95% mean confidence interval for cycles %-change: -0.13% -0.11%
Cycles are helped.

GM45
total instructions in shared programs: 4985449 -> 4984768 (-0.01%)
instructions in affected programs: 145154 -> 144473 (-0.47%)
helped: 547
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 2.86% x̄: 0.66% x̃: 0.61%
95% mean confidence interval for instructions value: -1.31 -1.18
95% mean confidence interval for instructions %-change: -0.69% -0.62%
Instructions are helped.

total cycles in shared programs: 128835062 -> 128833144 (<.01%)
cycles in affected programs: 2720650 -> 2718732 (-0.07%)
helped: 517
HURT: 1
helped stats (abs) min: 2 max: 38 x̄: 3.71 x̃: 2
helped stats (rel) min: <.01% max: 0.89% x̄: 0.11% x̃: 0.07%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.04% max: 0.04% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for cycles value: -4.02 -3.39
95% mean confidence interval for cycles %-change: -0.12% -0.10%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
2020-03-09 16:46:19 -07:00
Eric Engestrom
461ee85248 docs: update calendar, add news item, and link releases notes for 19.3.5
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
2020-03-09 23:04:36 +00:00
Eric Engestrom
b06471b77d docs: add release notes for 19.3.5
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
2020-03-09 23:04:36 +00:00
Vinson Lee
5ffa6eab88 st/nine: Fix incompatible-pointer-types-discards-qualifiers errors.
../src/gallium/state_trackers/nine/nine_ff.c:129:28: error: initializing 'struct nine_ff_vs_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
    struct nine_ff_vs_key *vs = key;
                           ^    ~~~
../src/gallium/state_trackers/nine/nine_ff.c:145:28: error: initializing 'struct nine_ff_ps_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
    struct nine_ff_ps_key *ps = key;
                           ^    ~~~

Fixes: fdd96578ef ("nine: Add state tracker nine for Direct3D9 (v3)")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Andre Heider <a.heider@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015>
2020-03-09 15:37:54 -07:00
Marek Olšák
c1b8e84961 radeonsi: determine uses_bindless_samplers correctly
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
2020-03-09 16:08:14 -04:00
Marek Olšák
fc65df5651 ac: add a bug workaround for the 100% NGG culling case
Fixes: 8db00a51f8 - radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
2020-03-09 16:08:11 -04:00
Marek Olšák
7481c4be58 radeonsi: add a bug workaround for NGG - LATE_ALLOC_GS
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
2020-03-09 16:08:10 -04:00
Sonny Jiang
5ea2034f58 radeonsi: enable EXT_texture_shadow_lod
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
2020-03-09 16:08:07 -04:00
Chia-I Wu
f3728816af egl/android: require ANDROID_native_fence_sync for buffer age
Querying buffer age requires a buffer to be dequeued.  But dequeuing
without ANDROID_native_fence_sync might imply eglClientWaitSync,
which results in a deadlock as the display lock is already held by
eglQuerySurface.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221>
2020-03-09 18:27:11 +00:00
Edmondo Tommasina
c7976ed43a radv/sqtt: fix RADV_THREAD_TRACE_BUFFER_SIZE spelling
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116>
2020-03-09 17:26:33 +00:00
Eric Engestrom
7bbd10da23 docs/releasing: add missing </li> tags
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
2020-03-09 17:23:45 +00:00
Eric Engestrom
68d8606c4c docs: trivial fix for html structure
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
2020-03-09 17:23:45 +00:00
Neil Roberts
83e20139db glsl/opt_minmax: Add support for float16
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
e3cc81e86c glsl/lower_instructions: Handle fp16 for FDIV_TO_MUL_RCP
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Hyunjun Ko
4fcac46cbd glsl/lower_instructions: Handle fp16 for MOD_TO_FLOOR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
6c1c2b779a glsl/lower_instructions: Use float16 constants when appropriate
When lowering instructions that involve floating-point constants, pick
the appropriate type for the constant so that it will also work with
float16 parameters.

v2: Use float16_t constructor instead of helper function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
2b39bb4fc0 glsl/validate: Allow float16 in the expression tree
v2. [Hyunjun Ko (zzoon@igalia.com)] squashed 3 commits
into one commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
198d4a535b glsl: Add type queries for fp16+float and fp16+float+double
Following the is_integer_32_64() convention, add is_float_16_32() and
float_16_32_64() for these commonly tested combinations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Hyunjun Ko
ad27eb28d9 glsl: Handle fp16 unary operations when lowering matrix operations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
1b8edffaa5 glsl: Add ir_unop_f2fmp
This is the same as ir_unop_f2f16 except that it comes with a promise
that it is safe to optimise it out if the result is immediately
converted back to float32 again. Normally this would be a lossy
operation but it is safe to do if the conversion was generated as part
of the precision lowering pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
5d6b007da8 glsl: Add b2f16 and f162b conversion operations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
6b9f6caf06 glsl: Add IR conversion ops for 16-bit float types
Adds ir_unop_f162f and ir_unop_f2f16.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
878a35db9d glsl: Expand fp16 to float before constant expression evaluation
This way the generated constant folding code doesn't need to
understand fp16.  All operations have to be expanded to full float for
evaulation on the CPU, so we might as well do it up front.  As far as
GLSL is concerned, fp16 isn't a separate type from float, so
everything we're supposed to support for float we need to do for fp16.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
505428f20b glsl: Implement constant propagation for fp16
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
83afebf359 glsl: Add fp16 case for ir_triop_lrp optimization
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Neil Roberts
668ab9f19d glsl: Add support for float16 types in the IR tree
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
4068d6baff glsl: Add ir_constant constructor for fp16
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:08 +00:00
Kristian H. Kristensen
b75a166e68 freedreno/ir3: Don't fold conversions into sign
Not supported.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
2020-03-09 16:31:07 +00:00
Pierre-Eric Pelloux-Prayer
2a9d6fdd8c gitlab-ci: rules:changes to test on tested drivers changes
For now tests only use these drivers:
  * llvmpipe
  * softpipe
  * freedreno
  * lima
  * etnaviv
  * panfrost

So using rules:changes gitlab feature to run the tests when the changes
made are potentially affecting these drivers.

A few notes:
  * the following code:
      .piglit-test:
        extends:
          - .test-gl
          - .llvmpipe-rules
    makes gitlab replace .test-gl "rules:changes" values by the one from
    ".llvmpipe-rules".
  * rules:changes always matches for non-MR new branches so jobs will always be
    created (and they'll be run if their dependencies are run). For pushes to
    existing branches the files changed by the push are used to match the
    rules:changes path.
  * the same gitlab feature could be used for some build jobs

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569>
2020-03-09 16:31:55 +01:00
Daniel Schürmann
61fb17e8d7 amd: join emit_kill() from radv and radeonsi in ac_nir_to_llvm
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Daniel Schürmann
bdd7587414 radv: use nir_lower_discard_to_demote to work around game bugs
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Daniel Schürmann
9d64ad2fe7 radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabled
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Daniel Schürmann
de57ea2a3d amd/llvm: implement nir_intrinsic_demote(_if) and nir_intrinsic_is_helper_invocation
The current implementation uses a temporary helper variable
to ensure correct behavior until LLVM provides an intrinsic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Daniel Schürmann
ce87da71e9 nir: add pass to lower discard() to demote()
This pass is intended to work around game bugs, only!
It also lowers nir_intrinsic_load_helper_invocation to
nir_intrinsic_is_helper_invocation for consistency.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Daniel Schürmann
5adcfa68a9 nir: gather info whether a shader uses demote_to_helper
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
2020-03-09 12:29:32 +00:00
Eli Schwartz
66bb314cb4 docs: fix typo in v20 release notes
It makes no sense to wait for it to stabilize on a version released
months previously in the previous major release cycle.

This was probably intended to be recommending the first bugfix release
of the current major.minor release cycle.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106>
2020-03-09 12:09:09 +00:00
Eric Engestrom
4390c232ad Revert "docs/relnotes/19.3: fix vulkan version reported"
This reverts commit 5ff443b8aa

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4112>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4112>
2020-03-09 11:41:59 +00:00
Tapani Pälli
24408acca4 nir: fix compilation warning on glsl_get_internal_ifc_packing
Removes following warning:
   warning: 'const' type qualifier on return type has no effect

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4111>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4111>
2020-03-09 09:43:49 +00:00
Krzysztof Raszkowski
ad66b25415 gallium/swr: Fix vcvtph2ps llvm intrinsic compile error
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4090>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4090>
2020-03-09 09:21:00 +00:00
Pierre-Eric Pelloux-Prayer
33b255e107 meson: enable -fno-common by default
This flag is enabled by default starting with gcc 10.
All the compilation issues have been fixed, so use it by default
to make sure we're not introducing regressions.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
2020-03-09 09:11:07 +01:00
Pierre-Eric Pelloux-Prayer
283e815339 omx: fix build with gcc 10
bellagio/omx header files reference a global variable without the
extern keyworkd.
Now that gcc-10 enables the '-fno-common' by default the build fails.
Since these are external headers we can't easily fix them, so for
now build the omx module with the '-fcommon' flag to keep the
previous behavior.

See https://gitlab.freedesktop.org/mesa/mesa/issues/2385

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
2020-03-09 09:11:00 +01:00
Matt Turner
e924181ea8 intel/compiler: Discount NOPs from instruction counts
Scheduler changes can cause changes in the number of instructions due to
this workaround, so just don't include NOPs in the instruction counts to
prevent shader-db noise.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
bb3e7b0fe3 intel/compiler: Pass shader_stats for each SIMD mode
Passing shader_stats to the fs_generator constructor means that the
SIMD8 shader stats from the visitor (such as the scheduler mode) will be
reported out for the SIMD16/SIMD32 versions as well.

As you can see, we are now passing 'shader_stats' and 'stats' to
generate_code(), which is obviously odd looking. Ian rebased and
committed an old patch of mine which added the shader_stats struct on
July 30 in commit dabb5d4bee (i965/fs: Add a shader_stats struct.) and
shortly after on August 12 Jason added the brw_compile_stats struct in
commit 134607760a (intel/compiler: Fill a compiler statistics struct).

I'd like to combine the two, but I'm not sure how. shader_stats is an
input to generate_code() while brw_compile_stats is an output and is
only used by the Vulkan driver. Leave it as is for now...

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
e7d0460d58 intel/compiler: Pass backend_shader * to cfg_t()
As you can see, not having a pointer to the backend_shader from within
the class makes for some weird looking code.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
edae75037f intel/compiler: Mark visitor parameters to scheduler const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:12 +00:00
Matt Turner
75a33e268e intel/compiler: Mark some methods and parameters const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
03ac90aae5 intel/compiler: Make instructions_to_schedule a local variable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
43019c6f2c intel/compiler: Remove unnecessary local variables
These are already provided in the fs_reg_alloc class.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Matt Turner
3d0821a216 intel/vec4: Make implied_mrf_writes() a vec4_instruction method
Same as commit c20dc9b836 (intel/fs: Make implied_mrf_writes() an
fs_inst method.)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
2020-03-09 04:44:11 +00:00
Christian Gmeiner
d8f3d0a3a8 etnaviv: implement emit_string_marker
Writes string to cmdstream in payload of a nop command.
Could be useful for internal driver debugging too.

Here is how it looks decoded:

    0x18000000, /* NOP (3) OP=NOP */
    0x65736572, /*   rese */
    0x18000000, /* NOP (3) OP=NOP */
    0x00000074, /*   t */
    0x00000000, /*   GL.API_MODE := OPENGL */

or

    0x00000705, /*   GL.STALL_TOKEN := FROM=RA,TO=PE,FLIP0=0,FLIP1=0 */
    0x00000001, /*   TS.FLUSH_CACHE := FLUSH=1 */
    0x18000000, /* NOP (3) OP=NOP */
    0x616e7465, /*   etna */
    0x18000000, /* NOP (3) OP=NOP */
    0x6275735f, /*   _sub */
    0x18000000, /* NOP (3) OP=NOP */
    0x5f74696d, /*   mit_ */
    0x18000000, /* NOP (3) OP=NOP */
    0x735f7372, /*   rs_s */
    0x18000000, /* NOP (3) OP=NOP */
    0x65746174, /*   tate */
    0x00004606, /*   RS.CONFIG := SOURCE_FORMAT=A8R8G8B8

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3744>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3744>
2020-03-08 13:29:56 +00:00
Christian Gmeiner
4460628330 etnaviv: increase number of supported varyings to 16
No deqp regressions.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
2020-03-08 11:08:59 +00:00
Christian Gmeiner
53c6cb1bad etnaviv: update headers from rnndb
Update to etna_viv commit fd2e2cfd.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
2020-03-08 11:08:59 +00:00
Christian Gmeiner
84816c22e4 etnaviv: ask kernel for max number of supported varyings
The inital etnaviv kernel driver in 4.5 has support for this param.
See kernel commit 602eb48966d7b7f7e64dca8d9ea2842d83bfae73

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
2020-03-08 11:08:59 +00:00
Michel Dänzer
0103f02acb gitlab-ci: Always name artifacts archive after the job producing it
This will help determine which artifacts generate how much traffic.

v2:
* Add "mesa_" prefix to make it obvious which project the artifacts are
  from.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4085>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4085>
2020-03-07 11:09:50 +01:00
Lionel Landwerlin
20c09c9c06 anv: stop storing prog param data into shader blobs
We have no use for this data in Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason EKstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3517>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3517>
2020-03-07 05:51:45 +00:00
Jason Ekstrand
e03f965280 anv: Bounds-check pushed UBOs when robustBufferAccess = true
We also have to add nir_intrinsic_load_push_constant to the list of
intrinsics which use push constants in brw_nir_analyze_ubo_ranges
because we're moving the loop where we rewrite the intrinsics to after
we've analyzed UBO loads.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:29 +00:00
Jason Ekstrand
faea84e254 anv: Add an align_down_u32 helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:29 +00:00
Jason Ekstrand
61ac8cf083 anv: Align UBO sizes to 32B
This makes all of our bounds checking consistent with the block loads we
do for constant offset UBO accesses.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:28 +00:00
Jason Ekstrand
4610d69e37 anv: Delete some pointless break statements
They immediately follow returns.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:28 +00:00
Jason Ekstrand
28c243e9ec anv: Pass buffer addresses into emit_push_constant*
While we're here, we add an assert that bind_map::push_ranges is tightly
packed.  If it isn't, it breaks assumptions in the emit_push_constant*
functions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:28 +00:00
Jason Ekstrand
ff5de35127 anv: Mark max_push_range UNUSED and simplify the code
The compiler should be smart enough to figure out that it's unused on
Gen11 and earlier and delete the code which calculates.  Us adding an
`if (GEN_GEN >= 12)` check is unnecessary and just dirties the code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:28 +00:00
Jason Ekstrand
35ca2ad22e anv: Parse VkPhysicalDeviceFeatures2 in CreateDevice
The client may enable robustBufferAccess2 via either
pCreateInfo->pEnabledFeatures or via a chained-in
VkPhysicalDeviceFeatures2 struct.  We need to parse both.

Fixes: 022e5c7e5a "anv: Implement VK_KHR_get_physical_device_properties2"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
2020-03-07 04:51:28 +00:00
Eric Engestrom
0e4c001951 docs/relnotes/20.0: fix vulkan version reported
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
2020-03-07 00:57:15 +00:00
Eric Engestrom
5ff443b8aa docs/relnotes/19.3: fix vulkan version reported
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
2020-03-07 00:57:15 +00:00
Eric Engestrom
2557d614d3 gen_release_notes: fix vulkan version reported
Fixes: 4ef3f7e3d3 ("anv: Enable Vulkan 1.2 support")
Fixes: 7f5462e349 ("radv: enable Vulkan 1.2")
Fixes: 75755e0eba ("turnip: Pretend to support Vulkan 1.2")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
2020-03-07 00:57:15 +00:00
Alyssa Rosenzweig
de30a7ae6e pan/bi: Fix Android.mk
Files listed in Makefile.sources did not exist, this affects the android
build for other drivers as well.

[Patch by Tapani manually cherrypicked into this branch]

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
0b0be49005 pan/bi: Rename next-wait to simply 'wait'
next-wait is from a quirk of packing that the dependency indices are
"off by one"; we don't emulate this quirk in the IR since it's easy
enough to patch over in the disassembler. Let's not confuse anybody with
it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
b329f8c750 pan/bi: Add dummy scheduler
Do the absolute simplest possible thing -- create a clause for every
instruction, and just pick whichever slot we can, nopping the other,
copying whatever constant we have whether it's used or not.

To be clear - this is not to be used in a production compiler. But this
lets actual bundles and clauses show up in the BIR, which unblocks work
on final code generation and packing (which can happen more or less in
parallel to NIR->BIR, optimization, register allocation, and writing an
actual scheduling).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
51e537c9fa pan/bi: Implement load_const
In the laziest possible way...  We can just emit worst case moves which
DCE will eat for breakfast anyway, and inline constants on instructions
where that is supported directly. This approach eliminates a lot of
nasty corner cases that Midgard's crazy cache scheme has hit, at the
expense of slightly more work for DCE (but it's only a single iteration
of an O(N) pass that has to run anyway..)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
1ead0d3488 pan/bi: Add preliminary LOAD_UNIFORM implementation
Lots of things are missing (indirect access, UBOs) but we have this
stubbed out for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
48910e8388 pan/bi: Implement store_vary for vertex shaders
As far as I/O goes, these four should hold us over for a while.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
d86659ca57 pan/bi: Add helpers for creating temporaries
Also from Midgard, adapted to our addressing scheme.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
59b476e11a pan/bi: Implement load_input for vertex shaders
Corresponds to a single LD_ATTR instruction, easy enough.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
dabb6c6b9f pan/bi: Implement store_output for fragment shaders
Corresponds to a BLEND instruction, possibly preceded by an ATEST
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
79c1af0623 pan/bi: Add bi_schedule_barrier helper
Copypaste from Midgard.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
92a4f26e7f pan/bi: Add blend_location to IR for BI_BLEND
To specify which render target is being written.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
0767182665 pan/bi: Implement nir_intrsinic_load_interpolated_input
Enough for basic varying reads.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
806533ba7f pan/bi: Fix destination printing
It should get the same treatment as sources to handle SSA/reg/etc.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
65c8dcca3b pan/bi: Handle jumps (breaks, continues)
Loops should behave reasonably now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
987aea1400 pan/bi: Handle loops when ingesting CFG
Not very useful without also handling breaks and continues, of course.
We use the strategy from v3d (vir_to_nir) instead of Midgard's, since
the latter is mildly insane. I mean, it passes deqp but...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
9a00cf3d1e pan/bi: Add support for if-else blocks
Branch lowering code lifted from Midgard as usual.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
977a38c87f pan/bi: Call nir_lower_io_to_temporaries in cmdline
Normally mesa/st would do this for us, but we're using the standalone
compiler (in advance of having the hardware) and need this pass
particularly for fragment writeout.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
55dab92073 pan/bi: Add instruction emit/remove helpers
As we start descending into code generation these will be of interest.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
7fd22c3bbd pan/bi: Print branch target
...if it's present, anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
2e9b5f8ef4 pan/bi: Don't print types for unconditional branches
There's nothing to type!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
5c7ee8a974 pan/bi: Improve block printing
Skip predecessor printing if there are none and match a missing brace,
also fixup the spacing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
83c4562503 pan/bi: Walk through the NIR control flow graph
Copypaste from Midgard with some cleanups. That seems to be a trend
these days. Hopefully boilerplate will come to a close soon.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Alyssa Rosenzweig
0d29184f69 pan/bi: Lower and optimize NIR
Pretty much a copypaste from Midgard except where architectural
decisions diverge around vectorization. On that note, we will need our
own ALU scalarization pass at some point (or rather we'll need to extend
nir_lower_alu_scalar) to allow partial lowering for 8/16-bit ops. I.e.
we'll approximately need to lower

   vec4 16 ssa_2 = fadd ssa_0, ssa_1

to

   vec2 16 ssa_2 = fadd ssa_0.xy, ssa_1.xy
   vec2 16 ssa_3 = fadd ssa_0.zw, ssa_1.zw
   vec4 16 ssa_4 = vec4 ssa_2.x, ssa_2.y, ssa_3.x, ssa_4

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
2020-03-07 00:37:39 +00:00
Chad Versace
c652ff8caa anv: Flatten the logic add_aux_surface_if_supported (v3)
Reduces the function's max indentation level from 5 to 3 inside the big
'if' tree. And enables more comments to be attached to the condition
they describe.

v2:
  - Add missing DEBUG_NO_RBC check.
v3:
  - Return early on DISABLE_AUX_BIT.
  - Restore original order of gen7 hiz check.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
2020-03-06 23:40:41 +00:00
Chad Versace
615c65ba1b anv: Refactor creation of aux surfaces (v2)
make_surface() contained a giant if-tree for creation of aux surfaces.
Move the if-tree into its own function, add_aux_surface_if_supported().
This will simplify future changes for VK_EXT_image_drm_format_modifier.

This patch merely moves the code verbatim, then extracts duplicate
assertions to the top.

v2: Rename func to add_aux_surface_if_supported [for jekstrand].

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
2020-03-06 23:40:41 +00:00
Chad Versace
d1b7d80bc3 anv: Add anv_image_plane_needs_shadow_surface() (v2)
The function returns true if hardware limitations require the image
plane to use a shadow surface. It replaces equivalent code in
make_surface().

Refactor only. No intended change in behavior.

Why extract this code out of vkCreateImage? If an image requires
a shadow surface, then that may impact its support for DRM format
modifiers, which must be evaluated during
vkGetPhysicalDeviceImageFormatProperties2.

v2:
  - Use early return. [for jekstrand]
  - Unexport function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
2020-03-06 23:40:41 +00:00
Timothy Arceri
1da6b7f8a3 glsl: add subroutine support to nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
b1bc24f826 glsl: dont try to assign uniform storage for uniform blocks
Fixes a crash in some shaders.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
576b5ace9e glsl: add support for builtins to the nir uniform linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
79127f8d5b glsl: set ShaderStorageBlocksWriteAccess in the nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
17f240b874 glsl: nir linker fix setting of ssbo top level array
This helps correcly set it for each top level member and correctly
handle unsized arrays.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
8ffd09f311 glsl: find the base offset for block members from unnamed blocks
These block member have been split into individual vars so we need
to set the correct offsets for each member in the new glsl nir
linker. We also take this opportunity to set the correct location
for the variable.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
76ce775240 glsl: correctly set explicit offsets for struct members
This correctly sets offsets set in glsl when using the nir linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
590a59437f glsl: add std140 and std430 layouts to nir uniform linker
The current ARB_gl_spirv linking only supports explicit layouts so
we need to update it to support std140 and std430 layouts before
we can use the linker for glsl.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
858a49a10d nir: add glsl_get_std430_size() helper
This will be used by the nir glsl linker for linking uniforms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
a005f1a6e7 nir: add glsl_get_std430_base_alignment() helper
This will be used by the nir glsl linker for linking uniforms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
1ccfe821b2 nir: add glsl_get_std140_size() helper
This will be used by the nir glsl linker for linking uniforms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
120a26c6f2 nir: add glsl_get_std140_base_alignment() helper
This will be used by the nir glsl linker for linking uniforms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
262b611a5b nir: add glsl_get_internal_ifc_packing() helper
This will be used by the nir glsl linker for linking uniforms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
a02d8e040f glsl: correctly find block index when linking glsl with nir linker
The existing code for spirv expects all vars to have explicit
bindings set which is not true for glsl.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
10b816d27e glsl: add name support to nir uniform linker
Name support is optional for spirv support but is required for glsl
support.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
aa9b457062 glsl: move get_next_index() earlier in nir link uniforms
We will use get_next_index() in more of the helper functions in
the following patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
219cefe24f glsl: move add_parameter() earlier in nir link uniforms
We will use add_parameter() in more of the helper functions in
the following patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Timothy Arceri
51898c8ee5 glsl: move nir link uniforms struct defs earlier
We will need to use the state in more of the helper functions in
the following patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
2020-03-06 23:22:14 +00:00
Vasily Khoruzhick
4d5a0ae22c lima: gpir: enforce instruction limit earlier
Enforce instruction limit of 512 instructions earlier. This is a
workaround for infinite loops in gpir compiler and allows us to
pin point the tests that are affected.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4055>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4055>
2020-03-06 21:06:54 +00:00
Francisco Jerez
70349a2252 intel/compiler: Calculate num_instructions in O(1) during register pressure calculation
And mark the variable declaration as const.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:13 -08:00
Francisco Jerez
e5e4d016b9 intel/compiler: Move register pressure calculation into IR analysis object
This defines a new BRW_ANALYSIS object which wraps the register
pressure computation code along with its result.  For the rationale
see the previous commits converting the liveness and dominance
analysis passes to the IR analysis framework.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:10 -08:00
Francisco Jerez
f6cdf66cd6 entel/compiler: Simplify new_idom reduction in dominance tree calculation
Trivial, just use a few less tokens to do the same thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:07 -08:00
Francisco Jerez
c9a608c090 intel/compiler: Move dominance tree data structure into idom_tree object
It makes sense to keep the result of analysis passes independent from
the IR itself.  Instead of representing the idom tree as a pointer in
each basic block pointing to its immediate dominator, the whole
dominator tree is represented separately from the IR as an array of
pointers inside the idom_tree object.  This has the advantage that
it's no longer possible to use stale dominance results by accident
without having called require() beforehand, which makes sure that the
idom tree is recalculated if necessary.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:05 -08:00
Francisco Jerez
c2a7eababf intel/compiler: Move idom tree calculation and related logic into analysis object
This only does half of the work.  The actual representation of the
idom tree is left untouched, but the computation algorithm is moved
into a separate analysis result class wrapped in a BRW_ANALYSIS
object, along with the intersect() and dump_domtree() auxiliary
functions in order to keep things tidy.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:03 -08:00
Francisco Jerez
2878817197 intel/compiler: Drop invalidate_live_intervals()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:21:01 -08:00
Francisco Jerez
acf24df201 intel/compiler/vec4: Switch liveness analysis to IR analysis framework
This involves wrapping vec4_live_variables in a BRW_ANALYSIS object
and hooking it up to invalidate_analysis() so it's properly
invalidated.  Seems like a lot of churn but it's fairly
straightforward.  The vec4_visitor invalidate_ and
calculate_live_intervals() methods are no longer necessary after this
change.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:59 -08:00
Francisco Jerez
ea44de6d8c intel/compiler/fs: Switch liveness analysis to IR analysis framework
This involves wrapping fs_live_variables in a BRW_ANALYSIS object and
hooking it up to invalidate_analysis() so it's properly invalidated.
Seems like a lot of churn but it's fairly straightforward.  The
fs_visitor invalidate_ and calculate_live_intervals() methods are no
longer necessary after this change.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:57 -08:00
Francisco Jerez
bb8cfa6837 intel/compiler/vec4: Add live interval validation pass
This could be improved somewhat with additional validation of the
calculated live in/out sets and by checking that the calculated live
intervals are minimal (which isn't strictly necessary to guarantee the
correctness of the program).  This should be good enough though to
catch accidental use of stale liveness results due to missing or
incorrect analysis invalidation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:55 -08:00
Francisco Jerez
24535604aa intel/compiler/fs: Add live interval validation pass
This could be improved somewhat with additional validation of the
calculated live in/out sets and by checking that the calculated live
intervals are minimal (which isn't strictly necessary to guarantee the
correctness of the program).  This should be good enough though to
catch accidental use of stale liveness results due to missing or
incorrect analysis invalidation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:53 -08:00
Francisco Jerez
a9cdc14f60 intel/compiler: Pass single backend_shader argument to the vec4_live_variables constructor
The IR analysis framework requires the analysis result to be
constructible with a single argument.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:51 -08:00
Francisco Jerez
d0433971f9 intel/compiler: Pass single backend_shader argument to the fs_live_variables constructor
This removes the dependency of fs_live_variables on fs_visitor.  The
IR analysis framework requires the analysis result to be constructible
with a single argument -- The second argument was redundant anyway.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:49 -08:00
Francisco Jerez
d7e84cbb0f intel/compiler: Restructure live intervals computation code
This makes the structure of the vec4 live intervals calculation more
similar to the FS back-end liveness analysis code.  The non-CF-aware
start/end computation is moved into the same pass that calculates the
block-local def/use sets, which saves quite a bit of code, while the
CF-aware start/end computation is moved into a separate
compute_start_end() function as is done in the FS back-end.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:46 -08:00
Francisco Jerez
48dfb30f92 intel/compiler: Move all live interval analysis results into vec4_live_variables
This moves the following methods that are currently defined in
vec4_visitor (even though they are side products of the liveness
analysis computation) and are already implemented in
brw_vec4_live_variables.cpp:

> int var_range_start(unsigned v, unsigned n) const;
> int var_range_end(unsigned v, unsigned n) const;
> bool virtual_grf_interferes(int a, int b) const;
> int *virtual_grf_start;
> int *virtual_grf_end;

It makes sense for them to be part of the vec4_live_variables object,
because they have the same lifetime as other liveness analysis results
and because this will allow some extra validation to happen wherever
they are accessed in order to make sure that we only ever use
up-to-date liveness analysis results.

The naming of the virtual_grf_start/end arrays was rather misleading,
they were indexed by variable rather than by vgrf, this renames them
start/end to match the FS liveness analysis pass.  The churn in the
definition of var_range_start/end is just in order to avoid a
collision between the start/end arrays and local variables declared
with the same name.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:44 -08:00
Francisco Jerez
ba73e606f6 intel/compiler: Move all live interval analysis results into fs_live_variables
This moves the following methods that are currently defined in
fs_visitor (even though they are side products of the liveness
analysis computation) and are already implemented in
brw_fs_live_variables.cpp:

> bool virtual_grf_interferes(int a, int b) const;
> int *virtual_grf_start;
> int *virtual_grf_end;

It makes sense for them to be part of the fs_live_variables object,
because they have the same lifetime as other liveness analysis results
and because this will allow some extra validation to happen wherever
they are accessed in order to make sure that we only ever use
up-to-date liveness analysis results.

This shortens the virtual_grf prefix in order to compensate for the
slightly increased lexical overhead from the live_intervals pointer
dereference.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:43 -08:00
Francisco Jerez
3ceb496cdf intel/compiler: Mark virtual_grf_interferes and vars_interfere as const
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:41 -08:00
Francisco Jerez
ab6d792986 intel/compiler: Pass detailed dependency classes to invalidate_analysis()
Have fun reading through the whole back-end optimizer to verify
whether I've missed any dependency flags -- Or alternatively, just
trust that any mistake here will trigger an assertion failure during
analysis pass validation if it ever poses a problem for the
consistency of any of the analysis passes managed by the framework.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:39 -08:00
Francisco Jerez
65080dc8df intel/compiler: Define more detailed analysis dependency classes
I've deliberately separated this from the general analysis pass
infrastructure in order to discuss it independently.  The dependency
classes defined here refer to state changes of several objects of the
program IR, and are fully orthogonal and expected to change less often
than the set of analysis passes present in the compiler back-end.

The objective is to avoid unnecessary coupling between optimization
and analysis passes in the back-end.  By doing things in this way the
set of flags to be passed to invalidate_analysis() can be determined
from knowledge of a single optimization pass and a small set of well
specified dependency classes alone -- IOW there is no need to audit
all analysis passes to find out which ones might be affected by
certain kind of program transformation performed by an optimization
pass, as well as the converse, there is no need to audit all
optimization passes when writing a new analysis pass to find out which
ones can potentially invalidate the result of the analysis.

The set of dependency classes defined here is rather conservative and
mainly based on the requirements of the few analysis passes already
part of the back-end.  I've also used them without difficulty with a
few additional analysis passes I've written but haven't yet sent for
review.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:37 -08:00
Francisco Jerez
d966a6b4c4 intel/compiler: Introduce backend_shader method to propagate IR changes to analysis passes
The invalidate_analysis() method knows what analysis passes there are
in the back-end and calls their invalidate() method to report changes
in the IR.  For the moment it just calls invalidate_live_intervals()
(which will eventually be fully replaced by this function) if anything
changed.

This makes all optimization passes invalidate DEPENDENCY_EVERYTHING,
which is clearly far from ideal -- The dependency classes passed to
invalidate_analysis() will be refined in a future commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:32 -08:00
Francisco Jerez
03eb46f4a7 intel/compiler: Introduce simple IR analysis pass framework
Motivated in detail in the source code.  The only piece missing here
from the analysis pass infrastructure is some sort of mechanism to
broadcast changes in the IR to all existing analysis passes, which
will be addressed by a future commit.  The analysis_dependency_class
enum might seem a bit silly at this point, more interesting dependency
categories will be defined later on.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:30 -08:00
Francisco Jerez
27ae3c1f68 intel/compiler: Reverse inclusion dependency between brw_vec4_live_variables.h and brw_vec4.h
brw_vec4.h (in particular vec4_visitor) is logically a user of the
live variables analysis pass, not the other way around.
brw_vec4_live_variables.h requires the definition of some VEC4 IR data
structures to compile, but those can be obtained directly from
brw_ir_vec4.h without including brw_vec4.h.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:28 -08:00
Francisco Jerez
a6fc88e91b intel/compiler: Reverse inclusion dependency between brw_fs_live_variables.h and brw_fs.h
brw_fs.h (in particular fs_visitor) is logically a user of the live
variables analysis pass, not the other way around.
brw_fs_live_variables.h requires the definition of some FS IR data
structures to compile, but those can be obtained directly from
brw_ir_fs.h without including brw_fs.h.  The dependency of
fs_live_variables on fs_visitor is rather accidental and will be
removed in a future commit, a forward declaration is enough for the
moment.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:26 -08:00
Francisco Jerez
06c5c49646 intel/compiler: Nest definition of live variables block_data structures
When this commit was originally written, these two structures had the
exact same name. Subsequently in commit 12a8f2616a (intel/compiler:
Fix C++ one definition rule violations) they were renamed.

Original commit message:

> These two structures have exactly the same name which prevents the two
> files from being included at the same time and could cause serious
> trouble in the future if it ever leads to a (silent) violation of the
> C++ one definition rule.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:23 -08:00
Francisco Jerez
310aef6b59 intel/compiler: Reverse inclusion dependency between brw_cfg.h and brw_shader.h
This reflects the natural dependency relationship between brw_cfg.h
and brw_shader.h.  brw_cfg.h only requires the base IR definitions
which are now part of a separate header.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:19 -08:00
Francisco Jerez
d46fb2126d intel/compiler: Move base IR definitions into a separate header file
This pulls out the i965 IR definitions into a separate file and leaves
the top-level backend_shader structure and back-end compiler entry
points in brw_shader.h.  The purpose is to keep things tidy and
prevent a nasty circular dependency between brw_cfg.h and
brw_shader.h.  The logical dependency between these data structures
looks like:

 backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h)
    -> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h)

This circular header dependency is currently resolved by using forward
declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h
include brw_shader.h, which seems backwards and won't work at all when
the forward declarations of cfg_t/bblock_t are no longer sufficient in
a future commit.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
2020-03-06 10:20:11 -08:00
Christian Gmeiner
74e4cda64b etnaviv: add etna_constbuf_state object
With this new state object we keep track of enabled pipe_constant_buffer
and only mark them as read when needed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4088>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4088>
2020-03-06 17:48:17 +01:00
Thong Thai
9f5802ad3e st/va: add check for P010 and P016 encode/decode support
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4033>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4033>
2020-03-06 16:10:40 +00:00
Thong Thai
d375803576 radeon: add support for 10-bit HEVC encoding to VCN 2.0
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4033>
2020-03-06 16:10:40 +00:00
Thong Thai
8ab31808fd radeonsi: add 10-bit HEVC encode support for VCN2.0 devices
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4033>
2020-03-06 16:10:40 +00:00
Alejandro Piñeiro
2ba272135a nir/linker: remove reference to just SPIR-V linking
Several files had a initial comment about the purpose of such files,
including a reference that the NIR linker was implemented with just
ARB_gl_spirv in mind.

Since the nice job Timothy is doing to use the NIR linker on GLSL,
that is not true anymore, so let's remove that reference and also
tweak some other comments.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4081>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4081>
2020-03-06 12:28:08 +00:00
Eric Engestrom
d7a70fbb23 bin/gen_release_notes.py: fix commit list command
Fixes: 86079447da ("scripts: Add a gen_release_notes.py script")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4069>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4069>
2020-03-06 11:46:45 +00:00
Eric Engestrom
894e286391 docs: fix typos in the release docs
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4067>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4067>
2020-03-06 11:44:03 +00:00
Pierre-Eric Pelloux-Prayer
771f16cf61 radeonsi: remove AMD_DEBUG=sisched option
sisched is not maintained anymore in LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>
2020-03-06 11:35:12 +01:00
Samuel Pitoiset
913d2dcd23 nir/lower_input_attachments: remove bogus assert in try_lower_input_texop()
It can be a sampler too.

Fixes: 84b08971fb ("nir/lower_input_attachments: lower nir_texop_fragment_{mask}_fetch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2558
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4043>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4043>
2020-03-06 09:13:40 +00:00
Samuel Pitoiset
6dc38cea52 radv/rgp: report correct system ram size
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4023>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4023>
2020-03-06 08:22:02 +00:00
Samuel Pitoiset
eeb09a01e7 radv/rgp: report correct cu_mask info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4023>
2020-03-06 08:22:02 +00:00
Samuel Pitoiset
b3ece36257 ac: add ac_gpu_info::cu_mask to store bitmask of compute units
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4023>
2020-03-06 08:22:02 +00:00
Samuel Pitoiset
c6c661de31 radv/sqtt: abort if SQTT is used on GFX6-GFX7
RGP only supports GFX8+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
14283ddc79 radv/sqtt: add support for GFX8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
d747015935 ac/registers: adjust some definitions for thread trace on GFX8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
0d55732a61 radv/sqtt: add radv_copy_thread_trace_info_regs() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
9baad41469 radv/sqtt: tidy up radv_emit_thread_trace_{start,stop}
Check for GFX10 first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
6c91aa7955 radv/sqtt: fix wrong check in radv_is_thread_trace_complete()
Oops, should be equal actually.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4022>
2020-03-06 08:00:39 +00:00
Samuel Pitoiset
ba29c050a3 radv/winsys: fix missing initializations of shader info in the null device
To avoid divide by zero when computing shader stats.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3999>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3999>
2020-03-06 07:43:31 +00:00
Jason Ekstrand
9d07d59842 iris: Don't skip fast depth clears if the color changed
We depend on BLORP to convert the clear color and write it into the
clear color buffer for us.  However, we weren't bothering to call blorp
in the case where the state is ISL_AUX_STATE_CLEAR.  This leads to the
clear color not getting properly updated if we have back-to-back clears
with different clear colors.  Technically, we could go out of our way to
set the clear color directly from iris in this case but this is a case
we're unlikely to see in the wild so let's not bother.  This matches
what we already do for color surfaces.

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073>
2020-03-06 01:40:02 +00:00
Vinson Lee
382b902a6d swr: Fix non-pod-varargs error.
../src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp:391:24: error: cannot pass object of non-trivial type 'std::string' (aka 'basic_string<char>') through variadic function; call will abort at runtime [-Wnon-pod-varargs]
                       pFunc->getName().str());
                       ^

Fixes: ff8265b64f ("gallium/swr: Fix llvm11 compilation issues")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4008>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4008>
2020-03-06 01:19:50 +00:00
Marek Olšák
ed0bea4495 glthread: fall back if a param size is non-zero and a pointer param is NULL
So that we don't crash. This is a GL error anyway.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
57a9c1ee47 glthread: fix a crash with incorrect glShaderSource parameters
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
c5825b7b6e glthread: add custom marshalling for glNamedBuffer(Sub)DataEXT
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
b8aa5edfc5 glthread: merge glBufferSubData and glNamedBufferSubData into 1 set of functions
This is a big cleanup.
GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD also doesn't sync anymore.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
8eb0332749 glthread: merge glBufferData and glNamedBufferData into 1 set of functions
This is a big cleanup.
GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD also doesn't sync anymore.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
93b2ee18a1 glthread: replace custom glBindBuffer marshalling with generated one
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
85276e2c1b glthread: sync instead of disabling glthread for non-VBO pointers
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
28a2ad7ddf glthread: track for each VAO whether the user has set a user pointer
This commit mainly adds basic infrastructure for tracking vertex array
state.

If glthread gets a non-VBO pointer, this commit delays disabling
glthread until glDraw is called. The next will change that to "sync"
instead of "disable".

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
d510e652d4 glthread: add marshal_call_after and remove custom glFlush and glEnable code
Instead of implementing marshalling manually, this XML property allows us
to insert additional code into code-generated functions.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
4970199d11 glthread: don't insert an empty line after (void) cmd;
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
b9eef27920 glthread: add support for glMemoryObjectParameteriv, glSemaphoreParameterui64v
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
b5c58bbf6c glthread: add support for glCallLists, glPatchParameterfv
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
1668a93903 glthread: add support for glClearNamedFramebuffer, glMaterial, glPointParameter
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
b0a20e7531 glthread: add support for glFog, glLight, glLightModel, glTexEnv, glTexGen
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
59e96bc513 glthread: add support for TexParameteri and SamplerParameteri functions
It's straightfoward except that I had to hack the python scripts to add
"marshal_count", which behaves just like "count" except that "variable_param"
is ignored. ("variable_param" changes the behavior of "count", which I don't
want)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
108fdb54c6 glthread: replace custom ClearBuffer marshalling with generated one
If the count attribute contains "enum", the count is evaluated only once.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
88b5fb18b3 glthread: check the size of all variable params and clean up the code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
358d923c8b glthread: handle complex pointer parameters and support GL functions with strings
The python changes add a local variable that computes the parameter size
only once.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
d00f36ac25 glthread: add/update count and marshal fields for many GL functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
fb95a4693f glthread: add GL_DRAW_INDIRECT_BUFFER tracking and generator support
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
30b6e82364 glthread: don't increment variable_data if it's the last variable-size param
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
19dc528bbf glthread: don't insert _mesa_post_marshal_hook into every function
Let the developer decide that in the python script.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
c920572f60 glthread: simplify repeated function sequences in marshal_generated.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
9dbf5ec9f7 glthread: use int instead of size_t where it's OK
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
313e98fb81 glthread: reduce pointer dereferences in glthread_unmarshal_batch
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
19151e2605 glthread: inline _mesa_unmarshal_dispatch_cmd and convert the switch to a table
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
245f9593b7 glthread: don't prefix variable_data with const
Not all variable data that is constant is declared with const, such as
glDeletePerfMonitorsAMD.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:14 +00:00
Marek Olšák
d93f4faefb glthread: don't generate the sync fallback if the call size is not variable
marshal_generated.c is 12% smaller.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3948>
2020-03-06 01:06:13 +00:00
Dylan Baker
a19c9290f4 docs: update news, calendar, and link release notes for 20.0.1
Also fix a couple of dates that are wrong.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4075>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4075>
2020-03-06 00:24:35 +00:00
Dylan Baker
6b1f94e9f2 docs: Add sha256sums for 20.0.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4075>
2020-03-06 00:24:35 +00:00
Dylan Baker
7c8766402e docs: add relnotes for 20.0.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4075>
2020-03-06 00:24:35 +00:00
Dylan Baker
f1890b7ad8 docs: update releasing to cover updated post_version.py
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2505>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2505>
2020-03-05 15:15:01 -08:00
Dylan Baker
5cdaa06221 bin/post_version.py: Make the git commit as well.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2505>
2020-03-05 15:14:56 -08:00
Dylan Baker
e3d3abb1bc bin/post_version.py: Pretty print the html
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2505>
2020-03-05 15:14:56 -08:00
Dylan Baker
d7ada7d7e0 bin/post_version.py: Update the release calendar as well
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2505>
2020-03-05 15:14:56 -08:00
Dylan Baker
d4cb9ef826 docs: Update release notes with current process
There's a lot of stuff here that's out of date, update it to something
more modern.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4066>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4066>
2020-03-05 22:47:28 +00:00
Dylan Baker
7451eb9a27 docs/submittingpatches: Fix confusing typo + missing pronoun
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4066>
2020-03-05 22:47:28 +00:00
Samuel Pitoiset
42a3d821cb gitlab-ci: add a job that runs Fossilize on RADV/Polaris10
RADV_FORCE_FAMILY forces creating a null device that allows RADV
to be instanced without AMDGPU.

The Fossilize database only contains pipelines from the Sascha
Vulkan triangle demos at the moment. I will add more once this
is merged.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
2020-03-05 20:33:56 +00:00
Samuel Pitoiset
af1cd45858 gitlab-ci: enable building the test image for VK unconditionally
It was diabled because RADV is the only driver that tests Vulkan
and running CTS on my personal machine and without recovery is
not safe enough for CI (too long and too unstable).

Now that we are going to test Fossilize with RADV, it's needed to
build the test image for VK unconditionally. As RADV now supports
creating NULL devices, the fossilize jobs can run everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
2020-03-05 20:33:56 +00:00
Samuel Pitoiset
1cdb6edbe6 gitlab-ci: add Fossilize support to detect compiler regressions
Fossilize is equivalent to vkpipeline-db but it's definitely more
robust. This is based on the CI traces system.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
2020-03-05 20:33:56 +00:00
Samuel Pitoiset
93fcc9ad57 gitlab-ci: build Fossilize in the test image for VK
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
2020-03-05 20:33:56 +00:00
Rhys Perry
b088a4b113 aco: only reserve sgprs for vcc if it's used
pipeline-db (Vega):

Totals:
SGPRS: 5186302 -> 5075616 (-2.13 %)
VGPRS: 3704580 -> 3704580 (0.00 %)
Spilled SGPRs: 144859 -> 144859 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 4124 -> 4124 (0.00 %) dwords per thread
Code Size: 247315944 -> 247315944 (0.00 %) bytes
LDS: 1311 -> 1311 (0.00 %) blocks
Max Waves: 674560 -> 674562 (0.00 %)

Totals from affected shaders:
SGPRS: 536992 -> 426306 (-20.61 %)
VGPRS: 356404 -> 356404 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 8498748 -> 8498748 (0.00 %) bytes
LDS: 8 -> 8 (0.00 %) blocks
Max Waves: 113832 -> 113834 (0.00 %)

There are some small code size changes in a few RotTR shaders and a small
increase in max_waves in two Detroit: Become Human shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3906>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3906>
2020-03-05 20:18:34 +00:00
Rhys Perry
c6e0c062da aco: improve control flow handling in GFX6-9 NOP pass
Fixes Detroit: Become Human hang. Also affects World of Warships.

pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 17168 -> 17168 (0.00 %)
VGPRS: 11296 -> 11296 (0.00 %)
Spilled SGPRs: 1870 -> 1870 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1472628 -> 1473292 (0.05 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 628 -> 628 (0.00 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 17168 -> 17168 (0.00 %)
VGPRS: 11296 -> 11296 (0.00 %)
Spilled SGPRs: 1870 -> 1870 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1409716 -> 1410380 (0.05 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

Max Waves is lower than it should be because of a null winsys bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
2020-03-05 19:37:24 +00:00
Rhys Perry
47b7f104a0 aco: consider non-hazard writes in handle_raw_hazard_internal
I think this helps GFX6 in particular because code like this is common:
s_add_i32       s4, 0x60, s3
s_mov_b32       s5, 0
s_load_dwordx4  s[4:7], s[4:5], 0x0
s_buffer_load_dword s4, s[4:7], 0xcc

pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 1923878 -> 1923878 (0.00 %)
VGPRS: 1528964 -> 1528964 (0.00 %)
Spilled SGPRs: 476 -> 476 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 88723604 -> 88528880 (-0.22 %) bytes
LDS: 241 -> 241 (0.00 %) blocks
Max Waves: 145402 -> 145402 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 428128 -> 428128 (0.00 %)
VGPRS: 353092 -> 353092 (0.00 %)
Spilled SGPRs: 119251 -> 119251 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 57580468 -> 57563964 (-0.03 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 11631 -> 11631 (0.00 %)

piepline-db (Vega):
Totals from affected shaders:
SGPRS: 425016 -> 425016 (0.00 %)
VGPRS: 349588 -> 349588 (0.00 %)
Spilled SGPRs: 117835 -> 117835 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 54890792 -> 54874432 (-0.03 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 54 -> 54 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
2020-03-05 19:37:24 +00:00
Rhys Perry
38743577f8 aco: improve get_wait_states()
pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 21208 -> 21208 (0.00 %)
VGPRS: 22388 -> 22388 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 3278596 -> 3277004 (-0.05 %) bytes
LDS: 19 -> 19 (0.00 %) blocks
Max Waves: 238 -> 238 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 64 -> 64 (0.00 %)
VGPRS: 96 -> 96 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 5200 -> 5192 (-0.15 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 10 -> 10 (0.00 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
2020-03-05 19:37:24 +00:00
Rhys Perry
7f1b537304 aco: add new NOP insertion pass for GFX6-9
This new pass is more similar to the GFX10 pass and should be able to
handle control flow better.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
2020-03-05 19:37:24 +00:00
Jason Ekstrand
ce19681257 iris: Enable HiZ and stencil CCS for blorp blit destinations
Now that blorp blits write to depth and stencil as depth and stencil, we
can leave HiZ and stencil CCS enabled for blorp blit destinations.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Jason Ekstrand
a0d5c7da18 iris: Enable CCS for copies from HiZ+CCS depth buffers
Ever since b274469daa, BLORP is able to sample from whatever the
sampler supports.  In c0c899cf78, we added HiZ support for copies from
HiZ compressed depth buffers but forgot HiZ+CCS.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Jason Ekstrand
83b641a038 anv: Enable HiZ for VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Jason Ekstrand
6cec618e82 blorp: Write to depth/stencil images as depth/stencil when possible
On Gen4 and G45 and earlier, we have to handle weird offsetting to write
to depth and stencil due to a lack of proper depth mipmapping support in
hardware.  On Gen6, we have to deal with strange HiZ and stencil
layouts.  Prior to Gen9, we also had to do crazy things for stencil
writes because we didn't support GL_ARB_shader_stencil_export and
friends in hardware.  However, starting with Gen7 for depth and Gen9 for
stencil, we can easily write out with the "right" hardware.  This allows
us to leave HiZ and other compression enabled for blorp_blit() and
blorp_copy() operations.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Jason Ekstrand
4531f0ffce iris: Allow HiZ on blit sources
Ever since 95cc5438eb, BLORP has been able to read from HiZ-compressed
depth buffers as long as the sampler supports HiZ.  This just makes iris
stop doing the unneeded resolve.

Closes: #2583
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Jason Ekstrand
9f5f4269a6 isl: Set 3DSTATE_DEPTH_BUFFER::Depth correctly for 3D surfaces
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
2020-03-05 18:56:45 +00:00
Dylan Baker
07f1ef5656 docs: Update stable process around using fixes: and gitlab
Currently the docs still recommend using
mesa-stable@lists.freedesktop.org, which is pretty awful. We really
don't want a second mailing list and it's mostly full of junk because of
CC: tags anyway.

This changes the preferred actions to be:
1) use a fixes: tag ahead of time
2) use a Cc tag ahead of time if fixes isn't appropriate
3) Use a gitlab MR against the staging/ branch for post-merge/backport
   nominations

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3056>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3056>
2020-03-05 18:24:14 +00:00
Jonathan Marek
55dac91adc turnip: fix tile->slot calculation
Fixes HW binning cases when the horizontal number of tiles isn't divisible
by the horizontal number of pipes (only happens with more than 32 tiles).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
2020-03-05 12:53:29 -05:00
Jonathan Marek
036230341f turnip: improve binning pipe layout config
The old code looks the same as GL driver, but we get things like
pipe_count = {32, 1}, which seems bad.

This uses similar logic as for tiles which produces a balanced pipe_count
width/height.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
2020-03-05 12:48:12 -05:00
Kristian H. Kristensen
9f9432d56c Revert "spirv: Use a simpler and more correct implementaiton of tanh()"
This reverts commit da1c49171d.

The reduced formula has precision problems on fp16 around 0.  Bring
back the old formula, but make sure to keep the clamping.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
2020-03-05 15:23:31 +00:00
Kristian H. Kristensen
986e92f0ea Revert "glsl: Use a simpler formula for tanh"
This reverts commit 9807f502eb.

The simplified formula doesn't pass the tanh dEQP tests when we lower
to fp16 math.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
2020-03-05 15:23:31 +00:00
Alyssa Rosenzweig
bc5724faf4 pan/bi: Add bi_print_shader
Woot! That's the last of it! IR printing is now complete*

*until the IR gets updated when new shiny things are added.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c152d4c835 pan/bi: Add bi_print_block
Almost there...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c316d1553b pan/bi: Add bi_print_clause
Again for post-sched purposes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
919cdf15b3 pan/bi: Add bi_print_bundle for printing bi_bundle
Post-schedule, nops are significnat here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
bde54cb6d3 pan/bi: Add bi_instruction printing
So we can debug the IR in memory before code emit has happened. We'd
like to have a complete dump of the IR -- neglecting this with Midgard
was one of those mistakes I've regretted so let's get this right for the
first time around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aef0f00cbc pan/bi: Move bi_interp_mode_name to bi_print
Instead of open-coding it in the middle of the disassembler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5d16a8109c pan/bi: Add BIR manipulation routines to bir.c
New file.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5f7a3ba872 pan/bi: Move some print routines out of the disasm
These are generally useful for debug of the compiler IR even prior to
code emit; let's share these.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8ec671801a pan/bi: Add IR iteration macros
Copypaste from Midgard, for the most part.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
0b26cb194c pan/bi: Add quirks system
Modeled after the Midgard system. Already we know of two
compiler-visible differences between G52 and G71, so let's keep track so
we can eventually port the compiler to other Bifrost systems.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
07228a6895 pan/bi: Add high-latency property for classes
This is required to know how to schedule legally, and also influences
some issues relating to RA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
546c301ff6 pan/bi: Add CSEL condition
Along with src_types, this is enough to represent CSEL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
47451bb9f1 pan/bi: Add bi_branch data
For BI_BRANCH, of course. Meshes well with the cfg.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
73c91f14c9 pan/bi: Extract bifrost_branch structure
It's in the disassembler as bitfields, let's extract to a proper
structure so we can see what's there.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
2afddc4433 pan/bi: Add pred/successors to build CFG
We'll want this for analysis passes or something, probably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
d3370bd5a5 pan/bi: Add constants to bi_clause
Scheduling will have to pay attention to this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
cb3cd8aa56 pan/bi: Add EXTRACT, MAKE_VEC synthetic ops
These allow translating between the vector I/O and scalar ALUs,
facilitated by an RA dance to ensured contiguous registers are used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8929fe0c84 pan/bi: Add source type for conversions
We should now be able to unambiguously represent conversions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5896db9578 pan/bi: Add swizzles
Requires a new field on bifrost_instruction, as well as a new class
property and a new class for the dedicated swizzle ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c70a198f24 pan/bi: Clarify special op scheduling
They're encoded on ADD but eat the full cycle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
fba1d12742 pan/bi: Add clause header fields to bi_clause
These will be filled out during scheduling (and possibly RA), to be used
when emitting code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
44ebc275fe pan/bi: Add class-specific ops
For disambiguating things like min and max within the MINMAX class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b5bdd89444 pan/bi: Add constant field to bi_instruction
Now that we can index it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a2c1265dd3 pan/bi: Add special indices
For fixed registers, uniforms, and constants, which bypass the usual SSA
mechanism to map well to the ISA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c42002d26f pan/bi: Add dest_type field to bifrost_instruction
A number of opcodes within a class are disambiguated by type/size, and
whether modifiers make sense or not depends on whether the instruction
acts like a float.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a35854c5ee pan/bi: Add bi_clause, bi_bundle abstractions
These will be used during and after scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
99f3c1f34c pan/bi: Add PAN_SCHED_* flags
Class (mostly) determines scheduling options.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
9643b9dd5b pan/bi: Add bi_load_vary structure
For ld_vary in the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
6a7987aba1 pan/bi: Pull out bifrost_load_var
We're not using this structure yet but we want everything in the ISA
ready for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aa2f12de56 pan/bi: Add bi_load structure
Fills out the class for LD_ATTR, LD_VAR_ADDR

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b93aec6df1 pan/bi: Add bifrost_minmax_mode field
We'll open up a union for class specific data, since this is interesting
only to BI_MINMAX. (And even then...)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
d69bf8db62 pan/bi: Add a bifrost_roundmode field
And a class property signaling it's okay to use.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
bbf41ffb00 pan/bi: Factor out enum bifrost_minmax_mode
We'll want it from the compiler-side.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
34165c7ec0 pan/bi: Add BI_GENERIC property
I don't want to have 20 class-specific structures floating around. So
let's derive them all from a common generic ALU type.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
29acd7bd8e pan/bi: Add modifiers to bi_instruction
Now that we can check if we support them via the class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
7ac62121e0 pan/bi: Add class properties
We need to keep track of what specific classes support. For now just
track floating point modifiers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
230be61f20 pan/bi: Add src/dest fields to bifrost_instruction
...along with some helpers to generate indices. The indexing scheme is
mostly a copypaste from Midgard, except we specifically reserve 0 as the
sentinel (midgard uses ~0 for this which has always been a pain point).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
e7dc2a7b9b pan/bi: Add the control flow graph
We're starting to build up the IR data structures in preparation to get
everything piped through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
eceaea43e3 pan/bi: Stub out new compiler
Just enough to pipe in the NIR shader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
5d3a4e3113 pan/bi: Gut old compiler
We're making some pretty dramatic design pivots so this early on it'll
be easier to start from scratch, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
eb15525ab7 panfrost: Add note about preloaded varyings
There's a magic bit in preload_regs which controls this. It doesn't
appear to be supported on G71 but it is on G52. I'd guess G72 supports
it too but I don't have a way to check this.

Needless to say, we'll need a quirks database for this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
2020-03-05 14:35:37 +00:00
Samuel Pitoiset
7618fe1b48 aco: fix image load/store with lod and 1D images
Make sure to add the lod value if non-null as the 2nd operand.

Fixes dEQP-VK.image.load_store_lod.with_format.1d.* on all gens
except GFX9.

Fixes: 4d49a7ac73 ("aco: handle nir_intrinsic_image_deref_{load,store} with lod")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4060>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4060>
2020-03-05 14:29:27 +01:00
Michel Dänzer
cc9493f78e gitlab-ci: Distribute jobs across more stages
The stages and mapping of jobs to them are somewhat arbitrary; the goal
is to avoid having to scroll through large numbers of jobs.

v2: (Pierre-Eric Pelloux-Prayer)
* Use even more stages for test jobs
* Give somewhat meaningful names to stages

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3995>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3995>
2020-03-05 12:46:51 +01:00
Michel Dänzer
71436f9640 gitlab-ci: Drop "test-" prefix from llvmpipe/softpipe job names
Redundant.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3995>
2020-03-05 12:45:51 +01:00
Marek Olšák
53a22c4b89 vbo: merge draws even when begin==0 or end==0
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:57:22 -05:00
Marek Olšák
ab7209fb83 vbo: merge more primitive types for glBegin/End (v2)
v2: clean it up more

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
d740e3d6ee mesa: deduplicate draw indirect functions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
7700ac3d80 mesa: optimize get_index_size
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
450152f8d8 mesa: remove _mesa_index_buffer::index_size in favor of index_size_shift
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
df3891e74a Revert "mesa: check for z=0 in _mesa_Vertex3dv()"
This reverts commit f04d7439a0.

It no longer helps performance and the current vbo implementation is
faster anyway.

The app that hit this was a CAD program called Spazio3D. It made pretty
terrible use of the OpenGL API and we sent them some tips for improvements.
I'm assuming they've fixed this by now.

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
9c9c314e41 vbo: fold code from vbo_exec_fixup_vertex to vbo_exec_wrap_upgrade_vertex
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
8205042be6 vbo: clean up conditional blocks in ATTR_UNION
Move the A != 0 code to the first block.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:43 -05:00
Marek Olšák
4c6323c49f vbo: handle GS and tess primitive types when splitting Begin/End
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Marek Olšák
f97341a9d6 vbo: clean up vbo_copy_vertices
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Marek Olšák
1be1ea0b8e vbo: deduplicate copy_vertices functions
There are some differences in exec, but those look like bug fixes not ported
to vbo_save.

Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Marek Olšák
fd8eb634fd vbo: don't look at the second draw's count when merging 2 glBegin/End draws
Only the first count needs to be aligned.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Marek Olšák
e92a4f817d mesa: replace some index_size multiplications and divisions with shifts
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Marek Olšák
87085c673d mesa: add index_size_shift = log2(index_size) into _mesa_index_buffer
for faster division

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanic@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4052>
2020-03-04 19:54:42 -05:00
Mauro Rossi
f38ffa4659 android: r600/sfn: Add GDS instructions
Fixes the following building errors:

external/mesa/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp:59: error: undefined reference to 'r600::GDSInstr::GDSInstr(r600::ESDOp, r600::GPRVector const&, std::__1::shared_ptr<r600::Value> const&, std::__1::shared_ptr<r600::Value> const&, std::__1::shared_ptr<r600::Value> const&, int)'
...
external/mesa/src/gallium/drivers/r600/sfn/sfn_emitssboinstruction.cpp:256: error: undefined reference to 'r600::RatInstruction::RatInstruction(r600::ECFOpCode, r600::RatInstruction::ERatOp, r600::GPRVector const&, r600::GPRVector const&, int, std::__1::shared_ptr<r600::Value> const&, int, int, int, bool)'

Fixes: 32d3435a ("r600/sfn: Add GDS instructions")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
2020-03-04 22:25:36 +01:00
Mauro Rossi
88c68c0ac7 android: r600/sfn: fix includes and libmesa_nir dependency
Fixes the following building errors:

In file included from external/mesa/src/gallium/drivers/r600/sfn/sfn_debug.cpp:28:
In file included from external/mesa/src/gallium/drivers/r600/sfn/sfn_debug.h:34:
In file included from external/mesa/src/compiler/nir/nir.h:41:
In file included from external/mesa/src/compiler/nir_types.h:36:
external/mesa/src/compiler/glsl_types.h:38:10: fatal error: 'main/config.h' file not found
#include "main/config.h"
         ^~~~~~~~~~~~~~~
1 error generated.

In file included from external/mesa/src/gallium/drivers/r600/sfn/sfn_debug.cpp:28:
In file included from external/mesa/src/gallium/drivers/r600/sfn/sfn_debug.h:34:
external/mesa/src/compiler/nir/nir.h:50:10: fatal error: 'nir_opcodes.h' file not found
#include "nir_opcodes.h"
         ^~~~~~~~~~~~~~~
1 error generated.

Fixes: f718ac62 ("r600/sfn: Add a basic nir shader backend")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
2020-03-04 22:25:36 +01:00
Mauro Rossi
01778d1e3c android: aco: fix PIPE_FORMAT related building errors
Fixes the following building errors:

In file included from external/mesa/src/amd/compiler/aco_dead_code_analysis.cpp:25:
In file included from external/mesa/src/amd/compiler/aco_ir.h:33:
In file included from external/mesa/src/compiler/nir/nir.h:40:
external/mesa/src/util/format/u_format.h:33:10: fatal error: 'pipe/p_format.h' file not found
#include "pipe/p_format.h"
         ^~~~~~~~~~~~~~~~~
...
In file included from external/mesa/src/amd/compiler/aco_dominance.cpp:31:
In file included from external/mesa/src/amd/compiler/aco_ir.h:33:
In file included from external/mesa/src/compiler/nir/nir.h:40:
external/mesa/src/util/format/u_format.h:33:10: fatal error: 'pipe/p_format.h' file not found
#include "pipe/p_format.h"
         ^~~~~~~~~~~~~~~~~
...
In file included from external/mesa/src/amd/compiler/aco_instruction_selection.cpp:31:
In file included from external/mesa/src/amd/common/ac_shader_util.h:32:
In file included from external/mesa/src/compiler/nir/nir.h:40:
external/mesa/src/util/format/u_format.h:33:10: fatal error: 'pipe/p_format.h' file not found
#include "pipe/p_format.h"
         ^~~~~~~~~~~~~~~~~
3 errors generated.

Fixes: 8d07d661 ("glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
2020-03-04 22:25:36 +01:00
Jason Ekstrand
b20693be41 nir: Flush to zero with OOB low exponents in ldexp
Reviewed-by: Arcady Goldmints-Orlov <agoldmints@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2020-03-04 11:39:50 -06:00
Duncan Hopkins
ec9da89900 zink. Added storage CISto descriptor pool.
Added storage in descriptor pool for combined image samplers as well as uniform buffers.
Stops some shaders from running through a pools storage faster than zinks internal tracking.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4045>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4045>
2020-03-04 15:59:16 +00:00
Andres Gomez
0ac731b1ff gitlab-ci: Add jobs to be able to test Vulkan
Also, adds an example job for radv.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:24:03 +02:00
Andres Gomez
5c65f8b377 gitlab-ci: Add gfxreconstruct traces support
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:24:03 +02:00
Andres Gomez
1d75595da4 gitlab-ci: Change devices format to <api-vendor-deviceId>
In preparation to having "vk" (Vulkan) along "gl" (OpenGL/ES).

This is so it is clearer which traces belong to which API and also for
the build jobs.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:22:04 +02:00
Andres Gomez
f1b7b8c0ee gitlab-ci: build VulkanTools into the Vulkan testing container
In preparation for having automated testing with Vulkan traces.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:21:58 +02:00
Andres Gomez
028ab482bf gitlab-ci: build gfxreconstruct into the Vulkan testing container
In preparation for having automated testing with Vulkan traces.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:21:47 +02:00
Andres Gomez
fc2338dc44 gitlab-ci: add missing popd to the build-deqp-vk.sh script
Since we are at it, replace "cd" with pushd / popd and homogenize how
VK-GL-CTS is built in comparison with other build scripts.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:21:39 +02:00
Andres Gomez
8c5e2ef19f tracie: correct typo
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2020-03-04 15:20:22 +02:00
Christian Gmeiner
83f54e3c54 etnaviv: fix alpha test on GC3000
Store ref_value in PE_STENCIL_CONFIG_EXT as done by blob.

Fixes following piglits:
 spec@ext_framebuffer_object@fbo-alphatest-formats
 spec@ext_packed_float@fbo-alphatest-formats
 spec@ext_texture_srgb@fbo-alphatest-formats

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4028>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4028>
2020-03-04 11:59:47 +00:00
Christian Gmeiner
f95fa3d1ac etnaviv: update headers from rnndb
Update to etna_viv commit 3bc187a.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4028>
2020-03-04 11:59:47 +00:00
Daniel Stone
e5b01183a6 egl/wayland: Don't invalidate buffers on no-op resize
The Wayland platform's resize_callback is invoked from libwayland-egl
when wl_egl_window_resize() is called. The resize call is the only place
for the application to insert dx/dy arguments to wl_surface_attach().

When modifying the cursor hotspot (as in wayland/wayland#148), we want
to set dx/dy, but leave the surface size the same. If we get
wl_egl_window_resize() with the same width and height argument as we
already have, we do not need to invalidate our existing drawable.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4030>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4030>
2020-03-04 11:38:11 +00:00
Andrii Simiklit
311c82e192 Revert "glx: convert glx_config_create_list to one big calloc"
This reverts commit 35fc7bdf0e.

Unfortunately mentioned commit introduced a memory leak because
`driwindowsMapConfigs` and `createDriMode` functions allocate
small memory portions for each element:
 21,576 (232 direct, 21,344 indirect) bytes in 1 blocks are definitely lost in loss record 1,411 of 1,414
    at 0x483A7F3: malloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
    by 0x5D4AA09: createDriMode (dri_common.c:291)
    by 0x5D4ABF5: driConvertConfigs (dri_common.c:310)
    by 0x5D58414: dri3_create_screen (dri3_glx.c:945)
    by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815)
    by 0x5D39C57: __glXInitialize (glxext.c:941)
    by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174)
    by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307)
    by 0x4F83038: glXQueryExtensionsString (in /usr/local/lib/libGL.so.1.7.0)
    by 0x4F2EA6B: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0)
    by 0x4F2A0D7: waffle_display_connect (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.6.0)
    by 0x498F42A: wfl_checked_display_connect (piglit-util-waffle.h:74)

There is one more thing which disallow us to easily fix it are different element sizes
for instance: `glx_config_create_list` allocates memory just for `glx_config`,
`driwindowsMapConfigs` for `driwindows_config` and
`createDriMode` for `__GLXDRIconfigPrivate`.
Yes it is possible but size of such fix
will be more big and complex than original one.
So it make sense only if the malloc overhead
really is a big problem there.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3406>
2020-03-04 10:19:48 +00:00
Vilya Harvey
6ceda48560 zink. Don't set incorrect sType in VkImportMemoryFdInfoKHR struct
imfi.sType was being set to an invalid value, triggering a warning in Clang. The only valid value for imfi.sType is VK_STRUCTURE_TYPE_IMPORT_MEMORY_FD_INFO_KHR which is the value it is being given at initialisation time, a few lines earlier. The incorrect value, VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT, is supposed to be used in imfi.handleType instead - and indeed, handleType *is* being set to this value a few lines later.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4034>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4034>
2020-03-04 08:37:29 +00:00
Hyunjun Ko
3199b8b9e7 turnip: support indirect draw
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3976>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3976>
2020-03-04 01:20:32 +00:00
Mauro Rossi
a933934efb android: gallium/auxiliary: fix "Unused source files" in tesselator
Avoids the following Android Build System error:

FAILED:
build/make/core/binary.mk:1245: error: external/mesa/src/gallium/auxiliary/Android.mk: libmesa_gallium: Unused source files: tessellator/tessellator.hpp
10:24:30 ckati failed with: exit status 1

Fixes: bd0188f ("gallium/auxiliary: add the microsoft tessellator and a pipe wrapper.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2020-03-03 21:32:26 +00:00
Eric Anholt
aea8c9c7b1 ci: Flip db410c back to docker mode.
Turns out there's corporate policy to not deploy AGPL software, so I
have to take down the LAVA lab until we sort out how to do it without
a local server.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4038>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4038>
2020-03-03 12:49:09 -08:00
Rafael Antognolli
5f13996262 intel/gen12+: Disable mid thread preemption.
Fixes a GPU hang in Car Chase.

Cc: mesa-stable@lists.freedesktop.org

v2: Add comment explaining why (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
2020-03-03 19:52:06 +00:00
Krzysztof Raszkowski
42ee6ff706 Revert "gallium/swr: Fix min/max range index draw"
This reverts commit 5e9a2c603f

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4032>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4032>
2020-03-03 19:33:36 +00:00
Chris Lord
291f40a499 vc4: fix vc4_yuv_blit overwriting fragment constant buffer slot 0
vc4_yuv_blit calls util_blitter_restore_constant_buffer_state without
first calling util_blitter_save_fragment_constant_buffer_slot. This causes
subsequent crashes in vc4_write_uniforms when using fragment shaders that
reference YUV textures.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2581
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3997>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3997>
2020-03-03 19:06:03 +00:00
Rhys Perry
2d1ba86382 aco: handle v_add_co_u32_e64 in parse_base_offset()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3902>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3902>
2020-03-03 18:31:06 +00:00
Rhys Perry
215df21dea aco: fix carry-out size for wave32 v_add_co_u32_e64
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: e0bcefc3a0 ('aco/wave32: Use lane mask regclass for exec/vcc.')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3902>
2020-03-03 18:31:06 +00:00
Jan Zielinski
18675363a3 gallium/swr: fix corruptions in Unigine Heaven
Few changes to fix the last corruptions in Heaven:
- fix indirect TCS input when vertex/attribute
  index is not the same for each patch
- use the correct functions to build loops in shader
- fix using vmask for writting TCS output

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3980>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3980>
2020-03-03 17:50:25 +00:00
Satyajit Sahu
0ab5c88a0a st/va: GetConfigAttributes: check profile and entrypoint combination
Added check if profile is supported or not for the entrypoint in
GetConfigAttributes.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3889>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3889>
2020-03-03 17:06:07 +00:00
Rafael Antognolli
cd40110420 intel/isl: Implement D16_UNORM workarounds.
GEN:BUG:14010455700 (lineage 1808121037):

   "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
   Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"

Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501.

GEN:BUG:1806527549:

   "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM."

This one could fix a GPU hang in some workloads.

v2: Implement WA in isl and add another similar WA (Jason).
v3: Add flushes before changing chicken registers (Jason)
v4: Depth flush and stall + end of pipe sync when changing registers
(Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
2020-03-03 16:25:54 +00:00
Rhys Perry
9fea90ad51 aco: keep track of which events are used in a barrier
And properly handle unordered events so that they always wait for 0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3774>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3774>
2020-03-03 15:38:13 +00:00
Thong Thai
3f31c54842 st/va/postproc: reallocate interlaced destination buffer
When the source buffer is progressive source, re-allocate the
destination buffer as progressive if it isn't already - otherwise
transcoding will fail.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1418
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4001>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4001>
2020-03-03 15:17:26 +00:00
Louis-Francis Ratté-Boulianne
2d32248f49 panfrost: fix transform feedback
Fix different use cases for transform feedback by setting:

 - PIPE_CAP_PACKED_STREAM_OUTPUT=0
 - PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED=1
 - PIPE_CAP_PSIZ_CLAMPED=1

This is enough for all dEQP xfb-related test cases to run
successfully.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (Update dEQP expectations)
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
585a21ceca gallium: add PIPE_CAP_PSIZ_CLAMPED
This new capability indicates that the point size has been clamped.
This also means that the gl_PointSize has been modified and that
its value should be lowered for transform feedback, if needed.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
babf7357d2 gallium: add PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED
This new capability indicates that the nir_lower_viewport_transform
pass is enabled. This also means that the gl_Position value is
modified and should be lowered for transform feedback, if needed.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
4ce339e741 gallium: add PIPE_CAP_PACKED_STREAM_OUTPUT
Setting this cap to 0 (default is 1) should disable packing
optimization for stream output (e.g. GL transform feedback captured
variables).

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
82dc149254 glsl/linker: add xfb workaround for modified built-in variables
Some lowering passes modify the value of built-in variables in
order for drivers to work properly. However, modifying such values
will also break transform feedback as the captured value won't
match what's expected.

For example, on some hardware, the vertex shaders are expected to
output gl_Position in screen space. However, the transform
feedback captured value is still supposed to be the world-space
coordinates (see nir_lower_viewport_transform).

To fix that, we create a new variable that contains the
pre-transformation value and use it for transform feedback instead
of the built-in one.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
4a329bea44 glsl/linker: handle array/struct members for DisableXfbPacking
When varying packing is disabled for transform feedback and a xfb
declaration points to an array element or structure member, the
element/member should be aligned to the start of a slot as well.
If that's not the case, a new varying is created and the
element/member value is copied.

There might a way to further optimize the number of slots allocated
or the number of copies necessary if the performance cost is
problematic. For example, in cases where simply padding the top
level variable might correctly align all the captured values.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Louis-Francis Ratté-Boulianne
00746fa2da glsl/linker: add DisableTransformFeedbackPacking workaround
Some drivers (e.g. Panfrost) don't support packing of varyings when
used for transform feedback. This new constant ensures that any
varying used for xfb is aligned at the start of a slot and won't be
packed with other varyings.

Scenarios where transform feedback declarations are related to an
array element or a struct member will be handled in a subsequent
patch.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (Fix order of arguments to varying_matches())
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2433>
2020-03-03 12:28:23 +00:00
Rhys Perry
8b361df9cf spirv: fix memory_barrier_tcs_patch emission
Shouldn't affect any driver, since all currently implement
memory_barrier_tcs_patch as a no-op. It also looks like optimizations are
fine

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4003>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4003>
2020-03-03 11:49:40 +00:00
Rhys Perry
6d839addf9 spirv: improve creation of memory_barrier
It shouldn't check for atomic counters or return in case we also need to
create a TCS output barrier.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4003>
2020-03-03 11:49:40 +00:00
Vasily Khoruzhick
5d713fb66e lima: don't disable tiling if there's linear modifier in list
Instead we should disable it if tiling modifier is not here and we
already do that.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4029>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4029>
2020-03-03 09:43:18 +00:00
Samuel Pitoiset
46a8cab58b ac: rename min_vgpr_alloc to min_wave64_vgpr_alloc
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3975>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3975>
2020-03-03 08:17:00 +01:00
Samuel Pitoiset
33faef6a34 ac: rename vgpr_alloc_granularity to wave64_vgpr_alloc_granularity
And update the value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3975>
2020-03-03 08:17:00 +01:00
Samuel Pitoiset
9432eb3e9c ac: rename lds_size_per_cu to lds_size_per_workgroup
It's more accurate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3975>
2020-03-03 08:16:56 +01:00
Brian Ho
69628ababb turnip: Execute main cs for secondary command buffers
Previously, we only added the secondary command buffer's draw and
draw epilogue command streams to the primary command buffer on
vkCmdExecuteCommands. However, we also need to merge the primary cs
for non-draw operations like vkCmdCopyBuffer and vkCmdBeginQuery.

Fixes dEQP-VK.memory.pipeline_barrier.host_write_transfer_src.*
and various other tests in dEQP-VK.api.command_buffers.*.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3988>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3988>
2020-03-03 02:25:25 +00:00
Brian Ho
5715a61fa9 turnip: Promote tu_cs_get_size/is_empty to header
These will be used in tu_cmd_buffer.c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3988>
2020-03-03 02:25:25 +00:00
Ilia Mirkin
bdf20d324b nvc0: enable EXT_texture_shadow_lod
This passes all the CTS tests for this extension.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4014>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4014>
2020-03-02 20:01:13 -05:00
Ilia Mirkin
11a06dfd4b st/mesa: allow TXB2/TXL2 to work with cube array shadow textures
It's a bit asymmetric, but it's such a contrived use-case, and not a lot
of drivers will support it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4014>
2020-03-02 20:00:52 -05:00
Ilia Mirkin
1d3b0b9088 nv50,nvc0: add newly added PIPE_CAP's to list
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4014>
2020-03-02 19:55:06 -05:00
Paulo Zanoni
62f7197fb5 anv: multiply the scratch space by 4 on gen9-10 like iris and i965
My understanding is that there's no reason for the scratch space
allocation to be different between iris, i965 and anv. Let's make all
the functions behave the same.

I don't know if this fixes any specific gen9 bugs, it it might since
it increases the scratch space.

v2: Rebase.
v3: Rebase.
v4: Remove redundant gen 11 check (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
2020-03-03 00:36:10 +00:00
Paulo Zanoni
aa78801f0a intel/device: bdw_gt1 actually has 6 eus per subslice
Found by inspection, I'm not aware of any bugs caused by this typo.

According to Lionel, it seems we only use this to generate masks
of available EUs for perfromance queries, and it's only used when we
can't query the fused parts of the GPU through DRM_IOCTL_I915_QUERY.
So this patch should help for the corner case where the Kernel is too
old to support the query ioctl.

v2: improve commit message, cc stable (Lionel).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
2020-03-03 00:36:10 +00:00
Paulo Zanoni
9e5ce30da7 intel: fix the gen 12 compute shader scratch IDs
This is the same idea as "intel: fix the gen 11 compute shader scratch
IDs".

The number of EUs on TGL is not the same as ICL, but the
MEDIA_VFE_STATE restrictions stay the same, so adapt the code to it.
Also, consider the base configuration instead of what we read from the
Kernel.

According to Mark, this fixes the following piglit tests on TGL:

    piglit.spec.arb_compute_shader.execution.shared-atomicmax-uint.tglm64
    piglit.spec.arb_compute_shader.execution.shared-atomicmax-int.tglm64
    piglit.spec.intel_shader_atomic_float_minmax.execution.shared-atomicmax-float.tglm64

v2: s/ICL+/Gen11+/ (Jason).

Cc: mesa-stable@lists.freedesktop.org
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
2020-03-03 00:36:10 +00:00
Paulo Zanoni
1efe139cad intel: fix the gen 11 compute shader scratch IDs
Scratch space allocation is based on the number of threads in the base
configuration, and we only have one base configuration for ICL, with 8
subslices.

This fixes an issue with Aztec on Vulkan in a machine with a
configuration that's not the base. The issue looks like a regression
from b9e93db208, but it seems things are broken since forever, just
not easily reproducible.

v2: Reimplement it using the subslices variable. Don't touch TGL.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
2020-03-03 00:36:10 +00:00
Alyssa Rosenzweig
d0c66869c1 pan/bi: Move some definitions from disasm to bifrost.h
These are generally useful outside the disassmbler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
346262ceb6 pan/bi: Structify FMA_FADD
Just to make it easier to work with.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
4fe5b59a96 pan/bi: Squash LD_ATTR ops together
*whistles*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
ee957bc0f3 pan/bi: Combine LOAD_VARYING_ADDRESS instructions by type
It's all a single opcode in fact.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
36fe378f1c pan/bi: Decode ADD_SHIFT properly
Just like FMA_SHIFT, but with some bits shuffled around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
8c79c710d4 pan/bi: Identify extended FMA opcodes
When the top 3 bits of the opcode are 111, it leads to a special
extended opcode mode instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
b51468ed9c pan/bi: Add v4i8 mode to FMA_SHIFT
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
2db454bbab pan/bi: Decode FMA_SHIFT properly
The shift-bitwise ops are fairly configurable, let's decode this the
right way. Choo choo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
67bbaddf7d pan/bi: Move notes on ADD ops to notes file
Again, we'd like to see just the opcode table more clearly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
7c96bd2dc5 pan/bi: Introduce CSEL4 class
All of these "ops" are just variants on the same.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
19a449e425 pan/bi: Move notes on FMA opcodes from disassembler
We're going to be shuffling around the opcode table, so let's get this
moved out first.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
dff83476c4 pan/bi: Add ICMP.GL.NEQ op
A fused not useful to feed into `discard`.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
178d9d4269 pan/bi: Add discard ops
These run on the ADD unit and evidently need to be their own clause
(probably treated as a high-latency instruction). Like csel, they can
either do a float comparison directly or ingest a 0/1 value.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
3044a37a84 pan/decode: Skip analysis for Bifrost tiler structures
We don't understand the Bifrost at all yet, so let's just print and move
on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
acd140c2e2 pan/decode: Fix tiler weights printing
Theoretical - still always zero.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
3f5cd446b2 pan/decode: Restore bifrost sample_locations
Code by Connor Abbott, reverting a part of
254f40fd53 where it was removed during a
Midgard refactor.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
5815f33c6b pan/decode: Calm an assert to a pandecode error
We'd like to see what the problem actually was...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
2020-03-03 00:03:50 +00:00
Rafael Antognolli
b4ddc6139b iris: Wait for the GPU to be idle before invalidating the aux table.
An end of pipe sync seems to satisfy this restriction. It takes care of
GPU hangs seen in dEQP-GLES31.functional.copy_image.* tests.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Rafael Antognolli
a7de6f1321 iris: Split aux map initialization from invalidation.
We can write the aux map address only once during the batch
initialization, and then only invalidate it once we modify it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Rafael Antognolli
43dc842cb9 anv: Wait for the GPU to be idle before invalidating the aux table.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Jason Ekstrand
3ca3050de5 anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stall
v2: Do end-of-pipe sync after clear depth stencil too (Jason).
v3: Also do end-of-pipe sync before clear depth stencil too (Jason).

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Jason Ekstrand
2db471953a anv: Use a proper end-of-pipe sync instead of just CS stall
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Jason Ekstrand
ac8d412ba3 anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
2020-03-02 22:28:11 +00:00
Dave Airlie
bb2287ccdf gallivm/tessellator: use private functions for min/max to avoid namespace issues
Different builds are failing because of namespace collisions here.

Just fix the MS code to avoid it.

Fixes: bd0188f9ea ("gallium/auxiliary: add the microsoft tessellator and a pipe wrapper.")

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2586
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4016>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4016>
2020-03-03 07:30:07 +10:00
Ivan Molodetskikh
c376865f5e egl: allow INVALID format for linux_dmabuf
As per
fb9b2a8731,
the compositor may advertise DRM_FORMAT_MOD_INVALID as a supported
modifier. This patch makes mesa recognize this fact and allow
linux_dmabuf usage with the INVALID modifier in this case.

In case the driver doesn't support modifiers, we can still use
linux-dmabuf protocol instead of the legacy wl_drm interface to create
wl_buffers. This will help compositors to handle these buffers better.

In this commit, the INVALID modifier is allowed to be added to the list
of supported modifiers, and create_wl_buffer will be able to use
linux_dmabuf with an INVALID modifier if the compositor advertised it as
supported.

Signed-off-by: Ivan Molodetskikh <yalterz@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2147>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2147>
2020-03-02 21:09:26 +00:00
Vasily Khoruzhick
646fbb1c4f lima: add RGBA5551 and RGBA4444 formats
We also need to set channel_layout in pp_frame reg (previously known as
foureight) depending on cbuf format.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3972>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3972>
2020-03-02 12:48:44 -08:00
Eric Anholt
ede93a3278 ci: Add a disabled-by-default job for GLES3 testing on db410c.
Now that we have 7 (soon 8) boards available, there's capacity to be
testing GLES 3.0.  However, due to (it looks like) buffer overflows in the
driver, we end up with flaky test results: 1/60 jobs spuriously failed,
and another 6/60 jobs reported flakes.  At 6 jobs per pipeline, that's way
too high of a failure rate to enable for non-freedreno developers.  Leave
the job present but disabled so that we can do manual test runs for
regressions.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3661>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3661>
2020-03-02 11:38:46 -08:00
Eric Anholt
5865944635 ci: Switch testing on db410c over to LAVA.
This should get us better stability of the db410c boards by having a
smaller per-board software stack, with no disks involved (just initramfs).
Additionally, the new cluster is 7 (soon 8) db410cs, while currently the
docker cluster only has 1/4 of its db410cs still running.

Unfortunately, we have to prepare the fastboot boot image during the ARM
drivers build stage, because LAVA relies on publicly available URLs for
the images to load into the bootloaders of the boards, and the only thing
we have for that is gitlab's artifacts.

Note that this testing relies on the boards being freshly flashed with the
linaro v136 firmware to pick up the initramfs size fixes and to stop the
boot at fastboot.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3661>
2020-03-02 11:38:46 -08:00
Gert Wollny
adcb365c1d r600/sfn: Don't try to catch exceptions, the driver doesn't throw any
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3974>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3974>
2020-03-02 20:00:26 +01:00
Gert Wollny
b66170b537 r600/sfn: Use static_cast when type is already known
In all these cases the type was tested before based, so don't use
dynamic_casts.

Closes #2566

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3974>
2020-03-02 20:00:23 +01:00
Gert Wollny
7780b50b7e r600/sfn: Avoid using dynamic_cast to identify type
v2: Fix typo (maurossi)

Related: #2566

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3974>
2020-03-02 20:00:14 +01:00
Alejandro Piñeiro
3503cb4c28 docs/features: add v3d driver
Now that we bumped the GLES version to 3.1, it makes even more sense
to include the driver here.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2507

Reviewed-by: Jose Maria Casanova <jmcasanova@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3810>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3810>
2020-03-02 15:54:40 +01:00
Albert Astals Cid
760fe44e8c aco: pass vars by const &
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3935>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3935>
2020-03-02 13:18:49 +00:00
Daniel Stone
5469221e77 Revert "gitlab-ci: disable panfrost runners"
The infrastructure issues, caused by building electrical works gone
wrong, have been fixed, and the Panfrost LAVA runners are available
again.

This reverts commit a86662c44d.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4019>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4019>
2020-03-02 12:40:31 +00:00
Albert Astals Cid
2521c81c9e aco: Minor optimization in spill_ctx constructor
'register_demand' is passed by value and only copied once; consider moving it to avoid unnecessary copies

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3968>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3968>
2020-03-02 12:21:03 +00:00
Samuel Pitoiset
d555794f30 radv: update entrypoints generation from ANV
It's a massive rework loosely based on ANV. This introduces separate
dispatch tables for the instance, physical device and device objects.

This will help for implementing internal driver layers for SQTT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3930>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3930>
2020-03-02 11:51:43 +00:00
Samuel Pitoiset
79d4d2807f radv/sqtt: add support for GFX10
All SQTT registers were moved to privileged space on GFX10, to emit
them we need a workaround with COPY_DATA.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
2020-03-02 12:23:43 +01:00
Samuel Pitoiset
eea3912451 ac/registers: add definitions for thread trace on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
2020-03-02 12:23:39 +01:00
Samuel Pitoiset
fedbc4c929 radv/sqtt: update SPI_CONFIG_CNTL.EXP_PRIORITY_ORDER value
It should be 3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
2020-03-02 12:23:37 +01:00
Samuel Pitoiset
36768eee9a radv/sqtt: do not assume that the number of shader engines is 4
It's not always 4, for example on RAVEN there is only one.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
2020-03-02 12:23:35 +01:00
Samuel Pitoiset
1b565e56e9 radv/rgp: adjust trace memory/shader clocks to fix frame duration
To report microseconds instead of clocks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4018>
2020-03-02 12:23:33 +01:00
Tapani Pälli
fbd61b3fb6 mesa/st: fix formats required for EXT_texture_norm16
Earlier commit did not take in to account that lists required for
rendering and texturing are parsed separately. This commit simply
removes formats added to the other list.

Fixes: de4eb9a3bb ("mesa/st: toggle EXT_texture_norm16 based on format support")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3961>
2020-03-02 10:53:44 +00:00
Andreas Baierl
e58bb417b5 lima: Add etc1 support
Layer stride has to be divided by 4. We also have to take care of
the array_size when returning the bo_size.

Drop the affected tests from the fails list.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3946>
2020-03-02 10:33:06 +00:00
Uros Bizjak
37a670d76c doc: Update features.txt for r600 with misc supported features
Update features.txt with misc supported features for r600,
as reported by glxinfo for Cypress XT [Radeon HD 5870].

Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4010>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4010>
2020-03-02 08:45:18 +00:00
Lionel Landwerlin
85457e350d intel/tools/dump_gpu: fix getparam values
Don't return the pci_id for all params

Fixes: 76bf38eaf0 ("intel/tools/aub_dump: move aub file initialization to maybe_init()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
2020-03-02 08:24:40 +00:00
Vinson Lee
1e43910aa2 meson: Enable -Wno-deprecated only for bison > 2.3.
Older versions of bison do not support the -W option.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2571
Fixes: 11a1cb2fa8 ("meson: Disable bison's -Wdeprecated since we still support old bison.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3993>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3993>
2020-03-01 18:13:52 -08:00
Ilia Mirkin
5306b662dd mesa: fix _mesa_draw_nonzero_divisor_bits to return nonzero divisors
The bitmask is _EffEnabledNonZeroDivisor, so no need to invert it before
returning.

Fixes: fd6636ebc0 (st/mesa: simplify determination whether a draw needs min/max index)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
2020-03-01 23:16:36 +00:00
Ilia Mirkin
a86662c44d gitlab-ci: disable panfrost runners
They seem to be timing out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4011>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4011>
2020-03-01 15:30:56 -05:00
Samuel Pitoiset
02f3af2ad1 radv: fix size of sqtt_file_chunk_asic_info on 32-bit system
The struct is actually 716 bytes, but on 64-bit systems the compiler
aligns it to 720. Add padding to make sure it's always 720.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
2020-02-29 05:54:54 +00:00
Samuel Pitoiset
33f604a331 radv: fix 32-bit build failure in radv_queue_internal_submit()
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
2020-02-29 05:54:54 +00:00
Timothy Arceri
ad094433b4 glsl: add some error checks to the nir uniform linker
These are optional for spirv but it shouldnt hurt to enable them.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
61dc9354c0 glsl: fix sampler index calculation in nir linker
Here we reset the counter to 0 for each shader stage not each program.
We also make add a flag to stop iterating over indices that have
already been processed.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
ef47069cc3 glsl: reset next_image_index count for each shader stage
This fixes the image index calculation in the nir linker. We need
to reset the counter to 0 for each shader stage not each program.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
e0aa0a839f glsl: fix resizing of the uniform remap table
In the NIR linker we were not resizing the remap table correctly
for explicit locations when it was needed.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
190a1ed170 glsl: set the correct number of images in a shader
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
b232a54df1 glsl: set the correct number of samplers in a shader
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Timothy Arceri
7dafc3050d glsl: fix possible memory leak in nir uniform linker
Use UniformDataSlots for the context of UniformDataDefaults rather
than UniformStorage as in some cause UniformStorage may be NULL.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
2020-02-28 23:48:46 +00:00
Jordan Justen
cf12faef61 intel/compiler: Restrict cs_threads to 64
Our current GPGPU_WALKER code only supports up to 64 threads.

On HSW we could use up to 70 and TGL up to 112, but only if the walker
is adjusted so the width does not exceed 64. Work to support this is
in progress.

Previous to this change, we might try to downgrade to SIMD8 if the
SIMD16 shader spilled. Since HSW and TGL have the max number of
threads above 64, we would then try to emit an invalid GPGPU walker
command.

Fixes: 932045061b ("i965/cs: Emit compute shader code and upload programs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2020-02-28 14:45:43 -08:00
Thong Thai
0932363489 st/va: remove unneeded code
No need to explicitly set the 10-bit buffer format as the correct
buffer format will be allocated later

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
2020-02-28 20:16:38 +00:00
Rob Clark
8cb9f79413 freedreno/ir3: add assert
Catch problems earlier when inputs are not setup correctly.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
ac705edd82 freedreno/ir3: fix assert with getinfo
Fixes:
dEQP-VK.glsl.texture_functions.query.texturesamples.sampler2dms_fixed_vertex

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
c1f4367461 freedreno/ir3: don't precolor unassigned inputs
Fixes crash seen in:
dEQP-VK.glsl.conversions.matrix_to_matrix.mat4_to_mat3x4_vertex

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
4b8e198fd2 freedreno/ir3: fix crash with samgq workaround
Need to list_delinit() before we clone the instruction to split it into
individual samgpN instructions, otherwise we get list corruption.

Tested-by: Eduardo Lima Mitev <elima@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
56565b7bba freedreno/ir3: update SFU delay
1) emperically, 10 seems like a more accurate # than 4
2) push "soft" delay handling into ir3_delayslots(), as
   we should also be using it to calculate the costs
   that the schedulers use

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
2cf4b5f29e freedreno/ir3: track half-precision live values
In schedule live value tracking, differentiate between half vs full
precision.  Half-precision live values are less costly than full
precision.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
4353b3c1c5 freedreno/ir3: don't hide latency when there is none to hide
Current scheduler thresholds try to ensure there are warps available to
switch to when hiding texture fetch latency.  But if there is none to
hide, we should allow scheduler to use more registers to reduce nops.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
9d2aaa589c freedreno/ir3: rewrite regmask to better support a6xx+
To avoid spurious sync flags, we want to, for a6xx+, operate in terms of
half-regs, with a full precision register testing the corresponding two
half-regs that it conflicts with.

And while we are at it, stop open-coding BITSET

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
c02cd8afbd freedreno/ir3: remove regmask_set_if_not()
No longer used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
2fa64729db freedreno: honor FD_MESA_DEBUG=nogrow
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:41 +00:00
Rob Clark
bab9db6c02 freedreno/a6xx: enable SKIP_IB2_ENABLE properly
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Rob Clark
9724a7c105 freedreno/a6xx: don't emit YIELD packet
We don't implement the rest of this.. and it would probably cause bad
things when kernel gains support for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Rob Clark
45771786e4 freedreno/a6xx: whitespace fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Rob Clark
ae3e237db0 freedreno/a6xx: emit LRZ clear in sysmem too
Fixes rendering issues in manhattan with FD_MESA_DEBUG=nogmem

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Rob Clark
6b605804ea freedreno/a6xx: remove unused param
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Rob Clark
141d0d1c25 freedreno/ir3: remove from_tgsi
No longer used, other than in ir3 cmdline compiler, where it can be
replaced with a local variable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
2020-02-28 16:53:40 +00:00
Jonathan Marek
c7ac1bcea0 turnip: increase array sizes in tu_descriptor_map
Pending the descriptor rework, this allows running the follow test:
dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_127

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
d195eef05d turnip: fall back to sysmem when attachments don't fit into gmem
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
de3230e0a5 turnip: remove unnecessary fb size check
Framebuffer with 0 width or height is not valid.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
cf302c9a22 turnip: don't hardcode gmem base for input attachment
Newer a6xx no longer has programmable GMEM base, so we can't rely on the
kernel driver setting it to 0x100000 (GMEM base is 0 on such GPUs).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
6420406f19 turnip: fix srgb MRT
Register packing macros makes this only set the first bit. Set to whole
dword to fix srgb for color attachments >0.

Fixes: 59f29fc8 ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
8f9e1c6047 turnip: fix hw binning + render_area offset interaction
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
de33c23370 turnip: minify image_view extent
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
b18d6575fe turnip: remove unecessary MRT_CONTROL fill
Hardware won't use MRT_CONTROL after mrt_count

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
33b2db5fb9 turnip: move some constant state to tu6_init_hw
Also remove duplicates.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
7d27a9ffb3 turnip: check the right alignment requirement on shader iova
I had some trouble because I assumed this was right, tested that the
alignment requirement is actually 16.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
2020-02-28 14:04:20 +00:00
Jonathan Marek
0f0662a551 turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formats
r5g5b5a1/b5g5r5a1 tiled/ubwc is the same as a1r5g5b5 (in memory), but
linear is read as 1_5_5_5 and written with 5_5_5_1 with swap.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
2020-02-28 12:48:11 +00:00
Jonathan Marek
80ceebcdd1 turnip: rework format table to support r5g5b5a1_unorm/b5g5r5a1_unorm
These formats are an exception that can't be modeled in the current format
table. Switch to a table with only a single a6xx_format per vk format,
and deal with the exceptions separately (currently the only exception is
10_10_10_2_UNORM which has a different color format).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
2020-02-28 12:48:11 +00:00
Jonathan Marek
89c6ef4233 util/format: add missing BC4/BC5 vulkan formats
Enables these formats for turnip.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
2020-02-28 12:48:11 +00:00
Icecream95
339f127f2b panfrost: LogicOp fixes and non 8-bit format support
With the previous LogicOp commit almost half of the blend modes were
broken because the surplus bits were not cleared after an inot.

v2:
 - Remove u8 "fast path" as 8-bit is not well optimised yet
 - Don't mask for 32-bit formats as that triggers an assert

Fixes: 068806c9f6 ("panfrost: LogicOp support")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
2020-02-28 11:52:40 +00:00
Icecream95
574b03eebf nir: Allow nir_format conversions to work on 32-bit values
The constant has to changed to unsigned long long, as shifting a
32-bit value by 32 is undefined behaviour.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
2020-02-28 11:52:40 +00:00
Greg V
cf69b9635a r600: add missing <array> include
Fixes error with clang/libc++:

../src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.h:69:88: error: implicit instantiation of undefined template 'std::__1::array<unsigned char, 3>'
   bool emit_alu_op3(const nir_alu_instr& instr, EAluOp opcode, std::array<uint8_t, 3> reorder={0,1,2});

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
2020-02-28 11:30:39 +00:00
Dave Airlie
eb5227173f llvmpipe: add support for tessellation shaders
This adds the hooks between llvmpipe and draw to enable tessellation shaders.

It also updates the CI results and docs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
a3257ae7be gallium/nir/tgsi: only scan fragment shader inputs for usage_mask
The scanner doesn't work with tess shaders, but we don't need it for those,
in fact only frag shaders need it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
dacf8f5f5c draw: hook up final bits of tessellation
This hooks tessellation into various parts of draw, so the
tessellation shaders are used in the correct places as the
last shader of the pipeline.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
0d02a7b8ca draw: add main tessellation code
This is the bulk of the llvm shader builders and tessellation
execution code.

TCS uses a coroutine launcher like compute shaders to handle
barriers. It executes 4-wide with one input vertex per lane.

Tessellation happens before the TES is run.

TES is just a 4-wide launcher, one per primitive is executed,
with one lane per tessellation coordinate input.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
76daf893ea draw: add JIT context/functions for tess stages.
This adds the initial draw_tess.h with a define needed
for the interfaces. TCS input array doesn't need to handle
patch inputs so can be smaller.

The TCS context has some dummy values to align the textures/images
properly.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
3ecd496117 gallivm/nir: add tessellation i/o support.
This add support for the tessellation i/o callbacks.

Tessellation requires another level of indirect indexing,
and allows fetches from shader outputs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
70a7603b63 gallivm/tgsi/swr: add mask vec to the tcs store
For the nir paths we want to access the mask vector to only
store when the mask allows it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
87359d68a9 gallivm/nir: align store_var param order with load_var
This was ugly so align load/store to have mostly the same
parameter ordering

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
7898e37fb4 gallivm/nir: add support for tess system values
hooks up the tessellation specific system values in the NIR paths

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
c632d806cb gallivm/nir: split out 64-bit splitting code
This just lets it be reused for tess later.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Dave Airlie
bd0188f9ea gallium/auxiliary: add the microsoft tessellator and a pipe wrapper.
This adds the same tessellator code that swr uses, swr should
move to using this copy, unfortunately that wasn't trivial on my first
look.

The p_tessellator wrapper wraps it in a form that is a useful interface
for draw.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
2020-02-28 18:33:34 +10:00
Samuel Pitoiset
bf16ff3172 radv: allow to capture SQTT traces with RADV_THREAD_TRACE=<start_frame>
This is pretty basic (and a bit crappy at the moment). I think we
might want some sort of overlay in the future and also be able to
trigger captures with F12 or whatever.

To record a capture, set RADV_THREAD_TRACE to something greater than
zero (eg. RADV_THREAD_TRACE=100 will capture frame #100). If the
driver didn't crash (or the GPU didn't hang), the capture file
should be stored in /tmp.

To open that capture, use Radeon GPU Profiler and enjoy your
profiling times with RADV! \o/

Note that thread trace support is quite experimental, only GFX9 is
supported at the moment, and a bunch of useful stuff are still missing
(shader ISA, pipelines info, etc). More is comming soon.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:11:11 +01:00
Samuel Pitoiset
ed0c852243 radv: add initial SQTT files generation support
SQTT is also a file format (.rgp extension) that can be consumed
by Radeon GPU Profiler for profiling purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:11:07 +01:00
Samuel Pitoiset
b3ef07db96 radv: emit thread trace markers after every draw/dispatch call
Thread trace markers (also called events in Radeon GPU Profiler)
should be emitted after every draw/dispatch calls to collect data.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:11:02 +01:00
Samuel Pitoiset
768d4f0551 radv: add initial SQ Thread Trace support for GFX9
SQTT is a hardware block that collects thread trace data (like
wave occupancy, timings, etc) for every draw/dispatch calls.

It's only supported on GFX9 at the moment but I will add other
generations support soon.

This is the first step towards profiling with RADV!

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:10:55 +01:00
Samuel Pitoiset
94099ee642 radv: add a small helper that allows to submit internal CS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:10:53 +01:00
Samuel Pitoiset
dbbf49c8f3 ac/registers: add definitions for thread trace
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:10:51 +01:00
Samuel Pitoiset
3de4f6c9f0 ac: add more fields to ac_gpu_info
For RGP traces.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
2020-02-28 08:10:37 +01:00
Eric Anholt
3c7c021ffc ci: Enable -Werror on meson-vulkan and meson-testing.
I want to make sure that I don't introduce warnings in turnip where we
have active work going on, and I also want to make sure that the drivers
we care about testing are warnings-clean.

As with the previous -Werror change, this is for CI only and doesn't
affect end-user builds.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
2020-02-27 21:59:34 -08:00
Eric Anholt
b9773631d3 aco: Fix signed-vs-unsigned warning.
The previous instance of this comparision was 1u to avoid the warning, fix
this one too.

Fixes: dba71de5c6 ("aco: only create parallelcopy to restore exec at loop exit if needed")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
2020-02-27 21:59:31 -08:00
Marek Olšák
2976ae2717 gallium/u_vbuf: silence a warning by using unreachable
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
2020-02-27 22:53:12 -05:00
Marek Olšák
ad192385e3 mesa: fix 11 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
2020-02-27 22:53:12 -05:00
Marek Olšák
6d7b076166 nir: fix 5 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
2020-02-27 22:53:12 -05:00
Marek Olšák
0e25746dde gallivm: fix 5 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
2020-02-27 22:53:12 -05:00
Marek Olšák
d18d07c9d7 nir: replace GCC unroll with an option that works on GCC < 8.0
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
2020-02-27 22:53:12 -05:00
Marek Olšák
1a61a5b1d4 mesa: fix incorrect prim.begin/end for glMultiDrawElements
This has no effect on Gallium, but it affects tnl.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
a1f4023443 mesa: optimize glMultiDrawArrays, call Draw only once (v2)
v2: use the macros

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
e636a062f1 mesa: don't unroll glMultiDrawElements if one count is 0
let the driver skip or submit an empty draw call.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
4c5cd113b8 mesa: clean up glMultiDrawElements code, use alloca for small draw count (v2)
v2: use calloc, add reusable macros

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de> (v1)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
b78ab9c741 mesa: move num_instances and base_instance out of _mesa_prim
They are never used by multi draws and internal draws.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
aaa758d3dd mesa: remove redundant _mesa_prim::is_indexed
Instead, check (ib != NULL) like all other drivers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
0c9850e55d mesa/i965: remove _mesa_prim::indirect_offset
Only i965 was using it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
f55ae2cdbe gallium/u_threaded: convert dividing by index_size to a bit shift
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
28d75fc286 gallium/u_threaded: fix uploading user indices with start != 0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
c9e4dc8d5e gallium: pass cso_velems_state into cso_context instead of pipe_vertex_element
This removes one memcpy from the CSO hashing code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
6c90e39a5b gallium/cso_hash: inline struct cso_hash_data
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
505cd5f12b gallium/cso_hash: pack cso_node better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
950ee0a370 mesa: remove unused "indirect" parameter from Driver.Draw
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Marek Olšák
9556805ac4 i965: stop using "indirect" parameter from Driver.Draw (non-indirect)
The parameter will be removed.

v2: added UNUSED, removed "!!"

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
2020-02-28 00:53:45 +00:00
Caio Marcelo de Oliveira Filho
dab7a4d82c anv: Remove unused field urb.total_size
This was used before the URB calculation functions were shared by GL
and Vulkan.  Also drop the substruct for the remaining, `l3_config` is
a good name on its own.

Also-written-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981>
2020-02-27 14:45:10 -08:00
Alyssa Rosenzweig
0bb25e4713 pan/midgard: Use address analysis for globals, etc
..instead of opencoding for constants and doing the rest as ALU.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
f5401cb886 pan/midgard: Add address analysis framework
Midgard has the ability to calculate addresses as part of the load/store
pipeline. We'd like to make use of this to avoid doing this work on the
ALU pipes. To do so, when emitting globals/SSBOs/shareds, we walk the
tree looking for address arithmetic to try to parse out something the
hardware can work with, letting the original instructions be DCE'd
ideally. This analysis is done at the NIR level to properly account for
some messy details of vectorization which we'd rather not poke at the
backend level. (Originally I wrote this as a MIR pass but I'm fairly
sure it was wrong.)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
658541a745 pan/midgard: Force address alignment
I thought we already had this but... maybe not..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
93ca47e046 pan/midgard: Round up bytemasks when promoting uniforms
Fixes crashes with uniform promotion in certain mixed type
circumstances.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
fd888d351f pan/midgard: Fix load/store argument sizing
The swizzles are as-if they were 32-bit regardless of the bitness of the
operation, but the source sizes can and do change depending on the
flags. Account for this in the analysis.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
ee47ce6ac3 pan/midgard: Add LDST_ADDRESS property
Many load/store ops (used for globals, SSBOs, shared memory, etc) have
the ability to compute addresses directly. Mark off which ones behave
like this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
1a2bb78840 pan/midgard: Extract nir_ssa_index helper
In case we don't have a nir_src.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
4e60dc8f48 pan/midgard: Partially fix 64-bit swizzle alignment
When mixing 32/64-bit, we need to align the 32-bit registers to get the
required alignment. This isn't quite enough yet, though, since user
swizzles could bypass and will need to be lowered to 32-bit moves
(outstanding todo).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
9c59f9f379 pan/midgard: Allow fusing inverted sources for inverted ops
It doesn't make a difference to the actual algorithm, so let's get rid
of them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
21c578027f pan/midgard: Allow inverted inverted ops
We'd like to transform `inand.not` back to `iand` and so forth.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Alyssa Rosenzweig
995e437105 panfrost: Increase SSBO/image limit from 4->8
Fixes an error compiling some shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
2020-02-27 21:02:35 +00:00
Jonathan Marek
1046d73af1 etnaviv: disable INT_FILTER for ASTC
Tested on GC3000: INT_FILTER bit is incompatible with ASTC formats.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3927>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3927>
2020-02-27 20:31:45 +00:00
Caio Marcelo de Oliveira Filho
811990dc1c anv: Remove unused field xfb_used from anv_pipeline
Since we only use xfb_info for GEN >= 8, make the ifdef cover that
local variable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3973>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3973>
2020-02-27 10:44:11 -08:00
Eric Anholt
33f38605e9 ci: Include db410c support in the ARM container.
I'm working on moving the db410c CI from docker to LAVA, which means we
get to boot a custom kernel.  To do that, we need to enable ARCH_QCOM in
the kernel, save the dtb around, and include abootimg in our container so
that we can generate combined kernel/dtb/ramdisk images for fastboot.

LAVA's fastboot support is unable to pack the overlay into an abootimg
image, just a cpio rootfs.  We could flash the cpio rootfs after overlay
addition, but that takes 2 minutes to do, and causes wear on the devices.
Instead, we'll bring up the network at boot and use wget to fetch the
overlay.  We'll want network support anyway, so that we can transfer the
failure xmls back to the gitlab job's artifacts at some point.

Since the msm GPU and realtek network firmware increase our payload by
3MB, add in firmware compression so that it doesn't waste as much RAM on
devices not using it.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
2020-02-27 09:36:26 -08:00
Eric Anholt
20659f1894 ci: Shrink the arm64 kernel build a bit.
No sense building some of these subsystems for just testing the GPU.
Saves some container rebuild time and kernel contents to move around.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
2020-02-27 09:36:24 -08:00
Eric Anholt
9ed6c1be6b ci: Stop disabling ACPI in the LAVA arm64 kernel build.
I can't figure out why, but it's necessary to get QCOM_CLK_APCS_MSM8916
for db410c.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
2020-02-27 09:36:22 -08:00
Eric Anholt
257415863b ci: Remove LLVM from ARM test drivers.
The LLVM libraries were a significant fraction of the entire payload
(55M/250M uncompressed) into the initramfs of the test boards, but
LLVM is only used for the draw module used in select/feedback (which
isn't even tested in CI on ARM yet).

Assume that llvmpipe draw is safe enough for ARM given the coverage on
x86, and disable LLVM for these jobs.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
2020-02-27 09:36:19 -08:00
Rohan Garg
9c0bbba856 ci: Split out radv build-testing on arm64
radv needs libllvm which increases our ramdisk size
significantly. Since this driver is only build tested,
we can split it out into a separate job.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3928>
2020-02-27 09:36:16 -08:00
Tomeu Vizoso
ebfa899089 gitlab-ci: Skip dEQP-GLES3.functional.shaders.derivate.*
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:57 +01:00
Tomeu Vizoso
17d775ca5d gitlab-ci: Remove GLES3 test from Panfrost fails list
Seems to have been fixed recently.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:52 +01:00
Tomeu Vizoso
1fa987ae5e gitlab-ci: Use PAN_MESA_DEBUG=gles3 for Panfrost
We can drop now the GLES version overrides now that we have a DEBUG flag
that enables all what is expected from a GLES 3.0 implementation.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:33 +01:00
Alyssa Rosenzweig
5491a13be9 panfrost: Add PAN_MESA_DEBUG=gles3 option
This enables experimental GLES3.0 support without ES3.1/2 hacks.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:28 +01:00
Alyssa Rosenzweig
f5b6dfcb18 panfrost: Expose PIPE_CAP_PRIMITIVE_RESTART
It works just fine, we just forgot to expose the CAP.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:23 +01:00
Alyssa Rosenzweig
2fea44c636 panfrost: Simplify stack shift calculation
I'm not sure why I never saw smaller values, but here you go.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:17 +01:00
Alyssa Rosenzweig
40fd1f9da4 panfrost: Reserve an extra page for spilling
I'm not sure what this is for, but the blob does it and I'd rather not
poke farther than needed into hardware-internal details.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:11 +01:00
Alyssa Rosenzweig
f37cec3275 panfrost: Default to 256 threads for TLS
I'm not sure where I got the impression 1024 was the right number. From
kbase:

   #define THREAD_MT_DEFAULT 256

(where MT = "max threads" and the threads to allocate for TLS is <= max
threads). Let's cut out memory footprint for spilling by 75% :)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:05 +01:00
Alyssa Rosenzweig
f6ca7ea551 panfrost: Fix param getting
....Oops....

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:32:00 +01:00
Alyssa Rosenzweig
4a10cfab76 panfrost: Don't set shared->unk0
This field controls the size of per-thread temporaries (somehow this is
separate from the regular stack for register spilling..), though I'm not
certain on the details. Regardless this value of 0x1e despite being used
in places by the blob seems wrong and is interfering with correct sizing
of the stack.

We don't use non-spilling scratchpad yet, so this is just here to fix
some details of spilling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:54 +01:00
Alyssa Rosenzweig
febabb0502 panfrost: Update spilling comment framebuffer->shared
All of this should apply equally with compute shaders, as far as I know.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:48 +01:00
Alyssa Rosenzweig
03822a27e6 panfrost: Fix padded_vertex_count generation
These two cases were flipped from the notes, leading to underestimates
of the padded vertex count, manifesting as visual corruption (random
geometry messed up). This issue was raised when noticing the corruption
went away when dramaticlaly oversizing max_index on an instanced indexed
draw, and then checking that padded_count >= vertex_count -- which
turned out *not* to be the case on certain inputs, a clear issue. Hence
looking into this routine...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:42 +01:00
Alyssa Rosenzweig
23c8597172 panfrost: Fix gl_VertexID/InstanceID
Fixes a bunch of tests in dEQP-GLES3.functional.instanced.*.

Fixes: 027944c7c8 ("panfrost: Avoid reading GPU memory when packing
vertices")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:37 +01:00
Alyssa Rosenzweig
a0b90b45a9 pan/midgard: Don't spill near a branch
Fixes
dEQP-GLES2.functional.shaders.indexing.varying_array.vec2_dynamic_loop_write_
static_read with register pressure forced down.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:32 +01:00
Alyssa Rosenzweig
ed52855680 pan/decode: Dump scratchpad size if present
This will help us narrow the size required for thread local storage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>
2020-02-27 16:31:06 +01:00
Alyssa Rosenzweig
d385c5840f panfrost: Implement index buffer cache
For index bufer resources (not user index buffers), we're able to cache
results. In practice, the cache works pretty dang well. It's still
important that the min/max computation is efficient (since when the
cache misses it'll run at draw-time and we don't want jank), but this
can eliminate a lot of computations entirely.

We use a custom data structure for caching. Search is O(N) to the size
but sizes are capped so it's effectively O(1). Insertion is O(1) with
automatic oldest eviction, on the assumption that the oldest results are
the least likely to still be useful. We might also experiment with other
heuristics based on actual usage later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3880>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3880>
2020-02-27 10:30:48 +00:00
Alyssa Rosenzweig
12db69aa3f panfrost: Combine get_index_buffer with bound computation
These operations are intertwined since there are optimizations that will
want to "double dip". In particular for user index buffers we'd want to
upload simultaneous with index computation. For resources we'd like to
keep resource related code together.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3880>
2020-02-27 10:30:48 +00:00
Leo Liu
e272b110bb radeon/jpeg: fix the jpeg dt_pitch with YUYV format
The dt_pitch should be same as NV12 format from decoder views,
and it finally got corrected with gfx9 surface's fixes from MR
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3738

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:35 +01:00
Pierre-Eric Pelloux-Prayer
5bc71e1bac st/va: add support YUY2
YUY2 is a duplicate of YUYV and is used by gstreamer for 4:2:2.

Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:35 +01:00
Pierre-Eric Pelloux-Prayer
d2e715e57a st/va: enable 4:2:2 chroma format
Everything is in place to support them.

Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:35 +01:00
Pierre-Eric Pelloux-Prayer
69aadc4933 radeonsi: fix surf_pitch for subsampled surface
gfx9.surf_pitch is supposed to be in blocks (or elements) but addrlib
returns a pitch in pixels.
This cause a mismatch between surface->bpe and surface.u.gfx9.surf_pitch.

For subsampled formats like uyvy (bpe is 2) this breaks in various places:
 - sdma copy
 - video rendering (see issue https://gitlab.freedesktop.org/mesa/mesa/issues/2363)
   when the vl_compositor_gfx_render method is used

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:31 +01:00
Pierre-Eric Pelloux-Prayer
c4197fbcdd gallium/vl: add 4:2:2 support
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2363
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:31 +01:00
Pierre-Eric Pelloux-Prayer
24f2b0a856 gallium/video: remove pipe_video_buffer.chroma_format
chroma_format depends on buffer_format so use the format_to_chroma_format
helper instead of storing it next to buffer_format.
This avoids bugs where one value is changed without updating the other.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:31 +01:00
Pierre-Eric Pelloux-Prayer
87807298a3 format: add format_to_chroma_format
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:31 +01:00
Pierre-Eric Pelloux-Prayer
fb29f0847f radeonsi: test subsampled format in testdma
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3738>
2020-02-27 10:01:31 +01:00
Samuel Pitoiset
9e5d2a73c5 ac/llvm: flush denorms for nir_op_fmed3 on GFX8 and older gens
The hardware doesn't flush denorms, exactly like fmin/fmax, so
we have to do it manually. This doesn't fix anything known.

Fixes: d6a07732c9 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
2020-02-27 08:04:33 +01:00
Samuel Pitoiset
30ac733680 ac/llvm: fix 16-bit fmed3 on GFX8 and older gens
16-bit med3 is only supported on GFX9+.

Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f16.*.

Fixes: d6a07732c9 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
2020-02-27 08:04:30 +01:00
Samuel Pitoiset
50b8c25274 ac/llvm: fix 64-bit fmed3
Lower 64-bit fmed3 because LLVM doesn't expose an intrinsic.

Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.mid3.f64.*.

Fixes: d6a07732c9 ("ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3962>
2020-02-27 08:04:28 +01:00
Mathias Fröhlich
636656bcd7 mesa: Flush vertices before changing the OpenGL state.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3958>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3958>
2020-02-27 06:58:56 +01:00
Mathias Fröhlich
4a54f8cd2c mesa: Check for OpenGL state change before flushing vertices.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3958>
2020-02-27 06:58:49 +01:00
Dave Airlie
2b155b1086 gallivm/nir: handle mod 0 better.
I haven't seen this crash but TGSI does it so best align with
it to avoid future issues.

Fixes: 44a6b0107b3J (gallivm: add nir->llvm translation (v2))
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3956>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3956>
2020-02-26 23:20:01 +00:00
Dave Airlie
5370c685da gallivm/nir: fix integer divide SIGFPE
Blender was crashing with a SIGFPE even though the divide by 0
logic was kicking in. I'm not sure why TGSI doesn't get into this state.

The problem was is the numerator was INT_MIN we'd replace the div by
0 with a divide by -1, which is an exception for INT_MIN as INT_MIN/-1
== INT_MAX + 1 (too large for 32-bits). Instead for integer divides
just replace the mask values with 0x7fffffff. Also fix up the
result handling so it aligns with TGSI usage. (gives 0)

Fixes: c717ac1247 ("gallivm/nir: wrap idiv to avoid divide by 0 (v2)")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3956>
2020-02-26 23:20:01 +00:00
Dave Airlie
954cf8e86b gallivm/tgsi: fix stream id regression
This broke TGSI GS shaders with llvmpipe, it wasn't looking at the
right immediates and it should be cast to an integer type.

Fixes: 163d5fde06 (gallium/swr: Enable GL_ARB_gpu_shader5: multiple streams)

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Acked-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3949>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3949>
2020-02-26 22:33:18 +00:00
Marek Olšák
4449611ffb mesa: call FLUSH_VERTICES before updating CoordReplace
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3947>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3947>
2020-02-26 22:10:35 +00:00
Marek Olšák
aae09ffb6e mesa: remove leftovers from ARB_shadow_ambient
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3947>
2020-02-26 22:10:35 +00:00
Albert Astals Cid
d988061172 cube_face_index: Use fabsf instead of fabs since we know it's floats
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3933>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3933>
2020-02-26 21:47:01 +00:00
Albert Astals Cid
6db7467b59 cube_face_coord: Use fabsf instead of fabs since we know it's floats
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3933>
2020-02-26 21:47:01 +00:00
Rafael Antognolli
a70a605ad6 iris: Apply the flushes when switching pipelines.
Even though the workaround description says:

   "all the listed commands are non-pipelined and hence flush caused due
   to pipeline mode change must not cause performance issues..."

My understanding is that we still need to have the flushes. Also, the
flushes are required not only to stall the pipeline, but also to clear
caches, so I don't think they can simply be discarded.

Additionally, while doing some testing that increased the number of
surface STATE_BASE_ADDRESS emitted, I got a lot more GPU hangs. Adding
these flushes fixes those hangs.

Fixes: b8fbb39a (iris: Implement Gen12 workaround for non pipelined
                 state)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908>
2020-02-26 21:16:24 +00:00
Marek Olšák
f6d1dd34d7 gallium/hash_table: remove some function wrappers
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
2020-02-26 20:35:50 +00:00
Marek Olšák
502840855a gallium/hash_table: turn it into a wrapper around util/hash_table
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
2020-02-26 20:35:50 +00:00
Marek Olšák
10d235a843 gallium/hash_table: use the same callback signatures as util/hash_table
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
2020-02-26 20:35:50 +00:00
Marek Olšák
76dff2fabe gallium/hash_table: consolidate hash tables with FD keys
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
2020-02-26 20:35:50 +00:00
Marek Olšák
a01a875081 gallium/hash_table: consolidate hash tables with pointer keys
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3722>
2020-02-26 20:35:50 +00:00
Greg V
56f31328f2 amd/addrlib: fix build on non-x86 platforms
regparm(0) attribute does not work on aarch64 (and presumably powerpc64 and others).
Default to not specifying any calling convention on non-amd64/i386 platforms.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3567>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3567>
2020-02-26 20:10:52 +00:00
Marek Olšák
c798aae739 tgsi_to_nir: set num_images and num_samplers with holes correctly
This fixes the copy_uv shader from st/omx, because it uses image 0 and 2
and image 1 isn't declared.

Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3936>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3936>
2020-02-26 19:49:25 +00:00
Jason Ekstrand
349898a967 nir: Drop nir_tex_instr::texture_array_size
It's set by lots of things and we spend a lot of time maintaining it but
no one actually uses the value for anything useful.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3940>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3940>
2020-02-26 18:29:49 +00:00
Eric Anholt
ec2f905ca8 freedreno/computerator: Fix defined-but-not-used warnings from lex/yacc.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3954>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3954>
2020-02-26 17:20:24 +00:00
Eric Anholt
bd53f4f56b turnip: Fix compiler warning about casting a nondispatchable handle.
Fixes: 1c5d84fcae ("turnip: hook up cmdbuffer event set/wait")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3916>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3916>
2020-02-26 16:58:50 +00:00
Tomeu Vizoso
ebd071d8cf gitlab-ci: Move to 5.5 kernel plus fixes for Panfrost
There's two fixes that help with stability when running dEQP on Kevin
Chromebooks.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3876>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3876>
2020-02-26 14:03:04 +01:00
Tomeu Vizoso
ae5e6406df panfrost: Remove some more prints to stdout
They can confuse test runners.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3876>
2020-02-26 14:02:59 +01:00
Tomeu Vizoso
fcd8308b28 gitlab-ci: Run GLES3 tests in dEQP on Panfrost
We are able to run only 1/5th of the tests in around the same time that
dEQP-GLES2 takes, so do that for now while more DUTs are installed.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3876>
2020-02-26 14:02:25 +01:00
Tapani Pälli
de4eb9a3bb mesa/st: toggle EXT_texture_norm16 based on format support
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2556
Fixes: 7f467d4f73 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
2020-02-26 11:12:59 +00:00
Tapani Pälli
200a83a983 i965: toggle on EXT_texture_norm16
Fixes: 7f467d4f73 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
2020-02-26 11:12:59 +00:00
Tapani Pälli
dc531869a9 mesa: introduce boolean toggle for EXT_texture_norm16
Fixes: 7f467d4f73 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
2020-02-26 11:12:59 +00:00
Juan A. Suarez Romero
784c454607 nir/lower_double_ops: add note for lowering mod
Add a note to clarify that while Vulkan allows mod(x,y) to be in [0, y]
range, OpenGL does not allow it, so the lowering ensures the result is
always in [0, y) range, as this lowering is shared by the Vulkan and
OpenGL implementation.

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3315>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3315>
2020-02-26 10:46:06 +00:00
Samuel Pitoiset
d2e4435c20 radv: fix creating null devices if KHR_display is enabled
Found this while replaying pipelines with Fossilize, it worked
fine with vkpipeline-db.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959>
2020-02-26 10:28:46 +00:00
Andreas Baierl
ef0abe5404 gitlab-ci: Add add a set of lima flakes
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3957>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3957>
2020-02-26 10:12:45 +00:00
Samuel Pitoiset
4c03d20396 radv: make use of ac_gpu_info::max_wave64_per_simd
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
9204ad70f2 radv/gfx10: adjust the number of VGPRs used to compute waves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
568f150409 radv/gfx10: adjust the LDS size used to compute waves
It's 128KB per CU in WGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
ea91b15a31 radv/gfx10: adjust SGPRs/VGPRs related info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
a6df3ef6ec radv/gfx10: adjust the number of simd per compute unit
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
09d8726187 ac: add more ac_gpu_info related shader fields
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
974c87e449 ac,radeonsi: add ac_gpu_info::lds_size_per_cu
Both RadeonSI and RADV use the WGP mode, so we can assume 128KB on
GFX10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
2020-02-26 07:58:47 +00:00
Samuel Pitoiset
cd6ec2b1ab radv: implement a dummy winsys for creating devices without AMDGPU
To allow developers to test the compiler backends without having
any AMD GPUs. To create a null device, set eg.
RADV_FORCE_FAMILY=polaris10 in your environment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872>
2020-02-26 08:09:46 +01:00
Mathias Fröhlich
f280c00ba6 egl: Factor out dri2_add_pbuffer_configs_for_visuals {device,surfaceless}.
v2: dri2_add_configs_for_visuals -> dri2_add_pbuffer_configs_for_visuals

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
2020-02-26 06:53:50 +01:00
Mathias Fröhlich
d32c458de7 egl: Fix A2RGB10 platform_{device,surfaceless} PBuffer configs.
The __DRI_IMAGE_FORMAT_* part wants to be handled for the *101010
type formats as well. Factor out a common function for that task.
That again makes the piglit egl_ext_device_base test work again
for hardware drivers.

v2: Factor out a common function for that task.
v3: dri2_pbuffer_visuals -> dri2_pbuffer_visuals

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Fixes: 9acb94b623 "egl: Enable 10bpc EGLConfigs for platform_{device,surfaceless}"
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
2020-02-26 06:53:46 +01:00
Jonathan Marek
87924646db turnip: enable fullDrawIndexUint32/independentBlend/dualSrcBlend/logicOp
These are already implemented but missing from VkPhysicalDeviceFeatures.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
2020-02-26 00:21:45 +00:00
Jonathan Marek
708c3a5ffd turnip: enable sampleRateShading feature
There's still a TODO related to key->sample_shading, but it doesn't look
like it changes anything in ir3, so it works without that.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
2020-02-26 00:21:45 +00:00
Matt Turner
cb166aea24 intel/tools: Do not print type/qualifiers/name for c_literal
External tools may wish to choose their own type, qualifiers, and name,
so do not emit our own.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
5feea40889 intel/tools: Allow i965_disasm to disassemble c_literal input type
Added extra argument named 'type' which can be 'bin' (default if
ommited) or 'c_literal' for input type.

Change 'binary-path' argument name to 'input-path'.

v2:
- Use util_dynarray for assembly (Matt Turner)
- Read data in 8 bytes chunk (Matt Turner)
- Fix help option (Akeem Abodunrin)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
2f83daedb1 intel/tools: Print c_literals 4 byte wide
We already print hex value a byte wide, instead of printing c_literal
byte wide, we can print it 4 byte wide, which gives us 2 different
combinations.

v2: Fix the aliasing issue (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
0b0e958f4f intel/tools: Add test for state register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
31c29f4f55 intel/tools: Add test for address register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
9526e5c359 intel/tools: Set correct address register file and number in i965_asm
We need to use already created brw_reg and set correct file type,
register number and sub register number.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
87d9e78f26 intel/tools: Handle STATE_REG in typed source operand
Also stop using brw_sr0_reg function as it return new brw_reg, we
already created register, all we have to is just set file, register
number and subnr.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Sagar Ghuge
2a75e60365 intel/tools: Handle illegal instruction
Allow assembler to handle illegal instruction even though mesa doesn't
use it but might be required at some point in future.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
2020-02-25 22:23:38 +00:00
Eric Anholt
11a1cb2fa8 meson: Disable bison's -Wdeprecated since we still support old bison.
We can't stop using deprecated keywords because we maintain support for
ancient bison.  Silence the warning so that builds are less noisy.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3868>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3868>
2020-02-25 21:45:06 +00:00
Jason Ekstrand
5dfd83d7a1 anv: Always enable the data cache
Because we set the needs_data_cache bit from the NIR during compilation,
any time a shader was pulled out of the pipeline cache, we wouldn't set
the bit and the data cache was disabled.  Fortunately, on Gen8+, this
bit is ignored because we always use the ALL section in the L3$ config
instead of separate DC and RO sections.  On Gen7, however, this meant
that we were basically never running with the data cache enabled and our
compute performance was suffering massively because of it.  This commit
improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no,
that's not a typo).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
2020-02-25 20:12:10 +00:00
Lionel Landwerlin
d4e7a11bc3 intel/aub_dump: stub the waits when overriding the device
We don't actually want to wait on anything, just complete submitting
the commands as fast as possible.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
2020-02-25 20:56:49 +02:00
Lionel Landwerlin
31461e2379 intel/tools/aub_dump: fix crash when using the default legacy context
When execbuffer->rsvd1 == 0, the legacy context is used. Ensure we
have context created for this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
2020-02-25 20:56:45 +02:00
Lionel Landwerlin
76bf38eaf0 intel/tools/aub_dump: move aub file initialization to maybe_init()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
2020-02-25 20:56:40 +02:00
Icenowy Zheng
3569215d49 lima: expose fragment shader derivatives capability
Support for fragment shader derivatives has landed in the Lima PP
compiler for a long time, but its capability is not exposed yet.

Expose the support now.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3944>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3944>
2020-02-26 01:47:58 +08:00
Jose Maria Casanova Crespo
01496e3d1e v3d: Sync on last CS when non-compute stage uses resource written by CS
When a resource is written by a compute shader and then used by a
non-compute stage we sync on last compute job to guarantee that the
resource has been completely written when the next stage reads resources.

In the other cases how flushes are done guarantee the serialization of
the writes and reads.

To reproduce the failure the following tests should be executed in batch
as last test don't fail when run isolated:

KHR-GLES31.core.shader_image_load_store.basic-allFormats-load-fs
KHR-GLES31.core.shader_image_load_store.basic-allFormats-loadStoreComputeStage
KHR-GLES31.core.shader_image_load_store.basic-allTargets-load-cs
KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray

v2: Use fence dep instead of bo_wait (Eric Anholt)
v3: Rename struct names (Iago Toral)
    Document why is not needed on graphics->compute case. (Iago Toral)
    Follow same code pattern of the other update of in_sync_bcl.
v4: Fixed comments style. (Iago Toral)

Fixes KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
CC: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
2020-02-25 11:41:44 +00:00
Andreas Baierl
5de8bc7c75 gitlab-ci: Enable the lima job again
Flaky tests should be fixed to the best of our knowledge.
Fails and skips lists should be up-to-date again.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
2020-02-25 07:45:53 +00:00
Andreas Baierl
31a8075678 gitlab-ci: lima: Add flaky tests to the skips list
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
2020-02-25 07:45:53 +00:00
Marek Olšák
5ab94df0f6 nir: fix gl_nir_lower_images for bindless images
Fixes: 7342b859af

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3938>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3938>
2020-02-25 02:30:08 +00:00
Rob Clark
26d42645f9 freedreno/computerator: fix build dependency
Ensure the generated register headers are built before computerator uses
them.

Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3939>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3939>
2020-02-25 02:02:06 +00:00
Dave Airlie
84395190ec glx/drisw: fix shm put image fallback
The fallback to the non-shm put path used the wrong width here
as the pixmap is still allocated in a shared segment, so the
width needs to reflect that.

Fixes: 02c3dad0f3 ("Call shmget() with permission 0600 instead of 0777")

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
2020-02-25 01:23:01 +00:00
Dave Airlie
246e4aeaef glx/drisw: return false if shmid == -1
If an attempt to create an shm pixmap in XCreateDrawable fails
then it ends up with the shmid == -1. This means the get image
path needs to fallback so return false in this case to use the
non-shm get image path.

Fixes: 02c3dad0f3 ("Call shmget() with permission 0600 instead of 0777")

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
2020-02-25 01:23:01 +00:00
Dave Airlie
8d0bab8a93 glx/drisw: add getImageShm2 path
This adds return values to the get image path, so the caller can fallback.

Fixes: 02c3dad0f3 ("Call shmget() with permission 0600 instead of 0777")

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
2020-02-25 01:23:01 +00:00
Dave Airlie
466a0b2e49 dri: add another get shm variant.
When Brian in 02c3dad0f3 restricted
the shm permissions it means we hit the fallback paths in some
scenarios we hadn't before.

When you use Xephyr to xdmcp from one user to another the new perms
stop the X server (running as user a) attaching to the SHM segments
from gnome-shell (running as user b).

In this case however only the GLX side of the code had insight into this,
and the dri could was meant of fall back, and it worked for put image
fine but the get image path was broken, since there was no indication
in the broken case of the need to fallback.

This adds a return type to a new interface member that lets the
caller know it has to fallback.

Fixes: 02c3dad0f3 ("Call shmget() with permission 0600 instead of 0777")

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
2020-02-25 01:23:01 +00:00
Eric Anholt
a91067d3f5 ci: Blacklist another freedreno flaky test.
This is the recurring flake from the last week, including spuriously
failing a pipeline once.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3937>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3937>
2020-02-25 01:07:14 +00:00
Jason Ekstrand
6fbe3f40a9 intel/isl: Add isl_aux_info.c to Makefile.sources
This should fix the Android build.

Fixes: 58d4749e56 "isl: Add a module which manages aux resolves"
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934>
2020-02-25 00:41:15 +00:00
Rafael Antognolli
9ab0e92cff intel/blorp: Implement GEN:BUG:1605967699.
v2:
 - Update comments and refactor code (Lionel).
 - Only apply workaround to stencil resolves.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909>
2020-02-25 00:04:36 +00:00
Erik Faye-Lund
36515e295c gallium/util: remove unused debug_print_foo helpers
These are unused, so let's just get rid of them.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
2020-02-24 23:07:57 +00:00
Erik Faye-Lund
dfea933a2a gallium/util: do not use debug_print_format
These are the only two places we use this macro, and it's no longer very
gallium-specific. So let's get rid of this, and just use debug_printf
and util_format_name directly instead.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
2020-02-24 23:07:57 +00:00
Erik Faye-Lund
5f0b984cb8 util: move debug_memory_{begin,end} to os_memory_debug.h
This is where the other debug_memory_* functions are declared, so let's
move it here for symmetry.

This allows us to drop an include of u_debug_gallium.h, which makes us
depend on gallium-headers in non-gallium code.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
2020-02-24 23:07:57 +00:00
Jonathan Marek
31a7815785 hud: add GALLIUM_HUD_SCALE
Scale hud by an integer factor, for high DPI displays.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3931>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3931>
2020-02-24 22:53:09 +00:00
Jonathan Marek
0ee76b90d5 turnip: move tile_load_ib/sysmem_clear_ib into draw_cs
Avoids having to calculate reserved sizes for substream cs, also matches
what the blob does.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:46 +00:00
Jonathan Marek
a410e64b68 turnip: make cond_exec helper easier to use
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:46 +00:00
Jonathan Marek
6ede9749d2 turnip: remove marker seqno
Use robclark's new crashdec/devcoredump thing instead.

Note: not sure this ever really worked because it didn't WFI.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:45 +00:00
Jonathan Marek
cf94124e1c turnip: automatically reserve cmdstream space in emit_pkt4/emit_pkt7
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:45 +00:00
Jonathan Marek
4b2a7dcd93 turnip: add tu_device pointer to tu_cs
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:45 +00:00
Jonathan Marek
a9a990a60b turnip: fix COND_EXEC reserved size in tu_query
Conditionally executed dwords must be in the same bo.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
2020-02-24 21:52:45 +00:00
Rob Clark
2275343ba3 freedreno/computerator: add computerator
A standalone tool to compile and run compute shaders from ir3 assembly.
Mostly to have an easy way to experiment with instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
2020-02-24 21:31:53 +00:00
Rob Clark
568e948d1f freedreno/ir3: allow block->predecessors to be null
This way we can also use ir3_print from computerator, which mostly
bypasses the ir3_block construct (since it doesn't need to do
scheduling, etc)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
2020-02-24 21:31:53 +00:00
Rob Clark
f87d412f08 freedreno/computerator: rename prefix asm->ir3
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
2020-02-24 21:31:53 +00:00
Rob Clark
6ee68d796e freedreno/computerator: polish out some of the rust
Updates for differences between fdre-a3xx's early version of ir3, and
what we have now in mesa.  And updates for instruction name and syntax
changes.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
2020-02-24 21:31:53 +00:00
Rob Clark
3bb340cf4f freedreno/computerator: import parser/lexer from fdre-a3xx
Import the rusty old parser from freedreno.git

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
2020-02-24 21:31:53 +00:00
Icenowy Zheng
6499738d3d lima: remove its hash table entry when invalidating a resource
When a resouce is already invalidated, its hash table entry becomes
useless. In addition, the lima_job_free() function won't remove the hash
table entry for invalidated resource. So the hash entry should be
removed when invalidating the resource, otherwise bogus hash entry might
be left in the table, and when the resource is reused in another job,
the code will find the freed job when invalidating and thus result in crash.

Fixes: c64994433c ("lima: track write submits of context (v3)")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3917>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3917>
2020-02-24 20:53:31 +00:00
Caio Marcelo de Oliveira Filho
956e4b2d37 nir, intel: Move use_scoped_memory_barrier to nir_options
This option will be used later by GLSL, so move to a common struct.

Because nir_options is filled in the compiler instead of the Vulkan
driver, fix that up.  GLSL will ignore that for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
2020-02-24 19:12:11 +00:00
Caio Marcelo de Oliveira Filho
6be766336a nir/tests: Use nir_scoped_memory_barrier() helper
Most of the vars tests already had a local helper, so just drop it in
favor of the one in nir_builder.  Remaining two tests changed to use
the helper.

The load_store_vectorizer tests were using the specific memory
barriers, but since scoped barriers are also handled, prefer that.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
2020-02-24 19:12:11 +00:00
Caio Marcelo de Oliveira Filho
6ff898a653 nir: Add the alias NIR_MEMORY_ACQ_REL
This will help upcoming C++ code that will have to combine those two
semantics.  In C++ it is not possible to do this without a cast or
adding an operator| to the enum.  Since having the short form will
also be convient to C, we picked the former solution.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
2020-02-24 19:12:11 +00:00
Caio Marcelo de Oliveira Filho
424737da3e nir/builder: Add nir_scoped_memory_barrier()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
2020-02-24 19:12:11 +00:00
Eric Anholt
e4baff9081 freedreno: Switch to using lowered image intrinsics.
This cuts out a bunch of deref chain walking that the compiler can do for
us.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
3e16434acd nir: Move intel's intrinsic_image_coordinate_components() to core nir.
This is a query that both Intel and freedreno need to do.  We can simplify
it a lot with the new glsl_get_sampler_dim_coordinate_components()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
a703840320 freedreno/ir3: Fix the arg to ir3_get_num_components_for_image_format()
GLuint worked fine for storing our enum, but it should be an enum
pipe_format since the image-formats merge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
8aa54e6ed0 prog_to_nir: Reuse glsl_get_sampler_dim_coordinate_components().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
b8644349d1 tgsi_to_nir: Reuse glsl_get_sampler_dim_coordinate_components().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
1b7de2d6b8 freedreno/ir3: Reuse glsl_get_sampler_dim_coordinate_components() in tex_info.
Now that we have access to the interior switch statement not going through
the txs special case for coord_components, we can just use it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
d37c6ebd3c spirv_to_nir: Reuse glsl_sampler_dim_coordinate_components().
We just needed to move the SUBPASS_MS case in, and the rest of the cases
match up.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
5072719e66 glsl: Factor out the sampler dim coordinate components switch statement.
I want to reuse this in NIR image intrinsics in backends, which just have
dim/is_array.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
12cf484d02 v3d: Ask the state tracker to lower image accesses off of derefs.
This saves a bunch of hassle in handling derefs in the backend, and would
be needed for reasonable handling of dynamic indexing of image arrays.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
9c90ecf37f gallium: Add a cap for enabling lowering of image load/store intrinsics.
The deref stuff is hard to handle in a backend supporting dynamic
indexing, while the lowering can easily turn that into the same kind of
dynamic indexing we do for textures, UBOs, and SSBOs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
7342b859af nir: Make image lowering optionally handle the !bindless case as well.
iris was doing this internally, but let's rename the function and move the
iris code there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Eric Anholt
cad2d6583c nir: Rename gl_nir_lower_bindless_images.c in preparation for extending it.
The bulk of it can be reused to implement iris's internal non-bindless
image lowering, which I would like to reuse in freedreno, v3d, and
nir-to-tgsi.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
2020-02-24 18:25:02 +00:00
Nanley Chery
b62379ac6f i965: Use isl_aux_state_transition_write()
v2. Dirty shadow miptrees independent of aux. (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Nanley Chery
b9856fbf3b i965: Use ISL's access preparation functions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Nanley Chery
b00e7a6485 iris: Use isl_aux_state_transition_write()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Nanley Chery
af04779410 iris: Use ISL's access preparation functions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Nanley Chery
fec957900d iris: Use isl_aux_usage_has_fast_clear()
Make sure fast-clears aren't attempted or allowed for ISL_AUX_USAGE_MC.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Nanley Chery
58d4749e56 isl: Add a module which manages aux resolves
Provide a generic interface which manages aux resolves in ISL. The
feature differences between this and what's in iris is:
* Support for media compression. ISL_AUX_USAGE_MC behaves differently
  from many other usages of CCS, so it was useful to implement this
  support upfront, while designing the interfaces.
* Optimizations for full-surface writes. For example, after a
  full-surface write occurs with ISL_AUX_USAGE_CCS_E in the PARTIAL_CLEAR
  state, isl_aux_state_transition_write() returns COMPRESSED_NO_CLEAR
  instead of COMPRESSED_CLEAR.

A performance suggestion for main-surface-invalidating/replacing writes
is given as a comment instead of adding a boolean to
isl_aux_prepare_access(). This avoids extra validation and should be
simple enough for the caller to handle.

v2. Add assertions. (Jason)
v3. Use switches in 2 more functions. (Jason)
    Store aux metadata in a static table. (Jason)
    Change prepare and finish function signatures. (Jason)
    Keep isl_aux_state_transition_* functions separate.
v4. (Jason)
    Assert against resolving in AUX_INVALID.
    Rename aux_info struct to aux_usage_info.
    Drop the justification for each aux_usage_info field.
    Split out the NONE case in write function.
    Restructure tests to more easily confirm coverage.
    Rename access_compressed field to compressed.
    Make write behavior less ambiguous.
v5. (Jason)
    Add more detail above WRITES_RESOLVE_AMBIGUATE.
    Add ISL_AUX_USAGE_MC to WritesResolveAmbiguate.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24 18:00:05 +00:00
Kristian H. Kristensen
daa4020948 freedreno/ir3: Lower output precision
This lowers mediump FS outputs to fp16 in the ir3 backend. For now
this is a modest improvement, which mostly helps us whittle down the
full mediump work.  Once the GLSL level support lands, then right hand
side of the store output intrinsics will be fp16 expressions and we'll
cancel out the fp16 -> fp32 -> fp 16 round trip here.

We've had different attempts at implementing this: rewriting stores in
the GLSL IR, lowering GLSL IR outputs to temporaries and inserting
conversions when writing the temporaries to the outputs.  In the end,
GLSL ends up getting in the way a lot and doing it at the nir level is
easier and still possible since we have the output var precisions.

This part of the fp16 work is more of a step on the way towards full
fp16 support and will add a few extra conversion instructions:

total instructions in shared programs: 8151 -> 8163 (0.15%)
instructions in affected programs: 1187 -> 1199 (1.01%)
helped: 4
HURT: 10

total nops in shared programs: 3146 -> 3152 (0.19%)
nops in affected programs: 563 -> 569 (1.07%)
helped: 5
HURT: 10

total non-nops in shared programs: 5005 -> 5011 (0.12%)
non-nops in affected programs: 92 -> 98 (6.52%)
helped: 0
HURT: 3

total dwords in shared programs: 12832 -> 12800 (-0.25%)
dwords in affected programs: 96 -> 64 (-33.33%)
helped: 1
HURT: 0

total last-baryf in shared programs: 118 -> 115 (-2.54%)
last-baryf in affected programs: 21 -> 18 (-14.29%)
helped: 1
HURT: 0

total full in shared programs: 424 -> 417 (-1.65%)
full in affected programs: 15 -> 8 (-46.67%)
helped: 7

HURT: 0
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Kristian H. Kristensen
6c750d9c4d nir/types: Add glsl_float16_type() helper
This returns the float16 version of a float type.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Hyunjun Ko
c822460f85 freedreno/ir3: handle half registers for arrays during register allocation.
So far we only handle full regs of arrays during pre-allocation.
This patch is to handle half regs of arrays and also consider the size
of half regs when finding out conflicts.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Hyunjun Ko
9e8466a866 nir: Add optimization for doing removing f16/f32 conversions
This eliminates conversions between f16 and f32 where possible. We can
always remove an upcast followed by a down cast, that is:

  f2f16 ( f2f32 (a) )  ->  a
  f2fmp ( f2f32 (a) )  ->  a

In the other direction, f2f16 loses precision and can't be undone by a
f2f32.  However, by definition it's always safe to elminate f2fmp:

  f2f32 ( f2fmp (a) )  ->  a

v2. [Neil Roberts (nroberts@igalia.com)]

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Hyunjun Ko
6ee375f68d freedreno/ir3: Add new ir3 pass to fold out fp16 conversions
This pass tries to fold f2f16 conversion into alu instructions.
This will be useful to help reduce the number of instructions once
mesa starts supporting precision lowering.  For example:

  add.f r0.w, r0.w, c0.x
  cov.f32f16 hr2.x, r0.w

to

  add.f hr2.x, r0.w, c0.x

Additionally this pass also tries to fold f2f16 conversion into load_input
instruction:

  bary.f r0.x, 3, r0.w
  cov.f32f16 hr0.x, r0.x

to

  bary.f hr1.x, 3, r0.x

v2: Edit to not fold OPC_MAX_F and OPC_MIN_F, since that's not valid.

v3: Add OPC_ABSNEG_F to the blacklist as well.

v4: Don't remove dead cov instructions, DCE will do that later; don't
iterate through sources when a cov only has one; remove special
handling of IR3_REG_ARRAY and IR3_REG_RELATIV.

v5: Handle folding into u32.u32 movs of floats correctly, don't bail
out on IR3_REG_RELATIV or IR3_REG_ARRAY movs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Neil Roberts
125f867d3d nir/opcodes: Add nir_op_f2fmp
This opcode is the same as the f2f16 opcode except that it comes with
a promise that it is safe to optimise it out if the result is
immediately converted back to a 32-bit float again. Normally this
would be a lossy conversion and so it would be visible to the
application, but if the conversion is generated as part of the mediump
lowering process then this removal doesn’t matter. The opcode is
eventually replaced with a regular f2f16 in the late optimisations so
the backends don’t need to handle it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
2020-02-24 17:24:13 +00:00
Indrajit Kumar Das
18124d7278 glapi/copyimage: Implement CopyImageSubDataNV
Implement CopyImageSubDataNV from NV_copy_image spec.
This is derived out of the existing implementation of CopyImageSubData.
It differs from CopyImageSubData in accordance with the differences
laid down in the ARB_copy_image spec.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3649>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3649>
2020-02-24 16:31:06 +00:00
Chris Wilson
ae7bda27a0 iris: Fix import sync-file into syncobj
When importing a sync-file, the kernel expects to be told which syncobj
to replace with the new fence -- it does not automatically create a new
handle for us. Abide by this rule and create a new syncobj for the
imported sync-file.

Fixes: f459c56be6 ("iris: Add fence support using drm_syncobj")
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3919>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3919>
2020-02-24 15:43:19 +00:00
Alyssa Rosenzweig
3a310fbd0b pan/midgard: Implement load/store_shared
Shared memory is implemented almost identically to global memory from an
ISA perspective, so let's handle the new intrinsics. We include a code
path for constant offsets, which doesn't come up for globals.

Fixes dEQP-GLES31.functional.compute.basic.shared_var_single_invocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
2020-02-24 13:56:59 +00:00
Alyssa Rosenzweig
fcbb3d422e pan/midgard: Implement nir_intrinsic_get_buffer_size
We route it as a sysval. Fixes dEQP-GLES31.functional.compute.basic.ssbo_unsized_arr_single_invocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
2020-02-24 13:56:59 +00:00
Alyssa Rosenzweig
3148937ef7 pan/midgard: Lower SSBOs in NIR
We need to lower SSBOs to globals regardless. Rather than do this in our
backend like we do now, use the common NIR pass, which will support
bounds checking.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
2020-02-24 13:56:59 +00:00
Eduardo Lima Mitev
99f2b6144b turnip/pipeline: Don't assume tu_shader is a valid object
Fixes a crash in tu6_emit_fs_config() when 'shader' argument is
assumed to be non-null, which is possible.

Fixes dEQP test:

dEQP-VK.api.descriptor_set.descriptor_set_layout_lifetime.graphics

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3756>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3756>
2020-02-24 12:20:20 +00:00
Samuel Pitoiset
12a22da683 radv: add the trace BO to the BO list at submit time
Instead of adding it in every command buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891>
2020-02-24 12:43:53 +01:00
Krzysztof Raszkowski
5e9a2c603f gallium/swr: Fix min/max range index draw
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3905>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3905>
2020-02-24 10:27:23 +00:00
Kenneth Graunke
4d57a27504 iris: Set MOCS for constant packets on Gen12+
It seems to be back, and we shouldn't use 0, as that's now considered
an error.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
2020-02-21 16:44:55 -08:00
Kenneth Graunke
4bac2fa3c6 iris: Fix BLORP vertex buffers to respect ISL MOCS settings
Fixes: a4da6008b6 ("iris: Use mocs from isl_dev.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
2020-02-21 16:44:53 -08:00
Kenneth Graunke
1cdf5abdfa iris: Make mocs an inline helper in iris_resource.h
Now that it uses ISL rather than genxml code, there's no need for it to
live as a vtable function inside the state module.  We can just make it
a static inline helper in iris_resource.h so it's available throughout
the codebase.

Fixes: a4da6008b6 ("iris: Use mocs from isl_dev.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
2020-02-21 16:44:38 -08:00
Eric Anholt
f8ab00776c ci: Remove a useless filtering of the lava logs.
We don't print every case any more, so no need to filter them out.  This
makes it so the output form "lavacli jobs logs" gets line-buffered into
"tee" and you can actually see what happened when the job is stuck but
before it times out.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Eric Anholt
7f3f9b2b19 ci: Don't bother generating deqp junit results since we don't present it.
We disabled presentation a while back because it's so expensive for gitlab
to parse it on the other side.  We may have a use for it some day if
gitlab gets better, but for now let's not spend the time processing it.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Eric Anholt
4c372d384a ci: Document how LAVA runners work.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Eric Anholt
994e258122 ci: Make LAVA job fails emit the full list of unexpected test results.
When bringing up a new board or starting a new GLES version, we have a lot
of unexpected fails to document, so we need the full list in the log (not
just deqp-runner.sh's head -n 50) so we can populate the xfail list.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Eric Anholt
54dbb55ea8 ci: Make sure that we have a proper shell prompt for LAVA.
LAVA finds a '#' early in boot and races to emit its shell commands.
Apparently for the current boards those serial commands end up getting
buffered such that things work out, but for db410c and db820c, the buffer
is lost and LAVA gets stuck waiting for the prompt.  By setting a prompt,
we can delay our commands until we're actually supposed to emit them (and
suppress a complaint from the lava dispatcher that we're using a risky
prompt!)

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Eric Anholt
985343e71a ci: prepare-artifacts: Make the indent here match previously in the file
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
2020-02-21 15:28:38 -08:00
Caio Marcelo de Oliveira Filho
89a3856714 anv: Add pipe_state_for_stage() helper
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
2020-02-21 13:09:44 -08:00
Caio Marcelo de Oliveira Filho
7df5d36078 anv: Use intel_debug_flag_for_shader_stage()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
2020-02-21 13:09:44 -08:00
Caio Marcelo de Oliveira Filho
f58b384fbe spirv: Be consistent when checking for Shader/Kernel
Use == and != instead of the ordered comparisons.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
2020-02-21 13:09:44 -08:00
Arcady Goldmints-Orlov
5f3cbbd958 spirv: Remove outdated SPIR-V decoration warnings
spirv_to_nir warns if it encounters XFB decorations and errors if
it encounters a Stream decoration with value other than 0, despite
the fact that these decorations are in fact handled correctly.

Fixes dEQP-VK.transform_feedback.simple.query_1_*
Fixes: cd4a14be06 "spirv: Handle XFB variable decorations"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910>
2020-02-21 20:34:03 +00:00
Jason Ekstrand
1598370aca nir/builder: Return an integer from nir_get_texture_size
It's convenient in a bunch of cases for nir_get_texture_size to return a
float but it's very unexpected.  This fixes a bug in the R600 NIR code.

Fixes: f718ac6268 "r600/sfn: Add a basic nir shader backend"
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3897>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3897>
2020-02-21 18:48:03 +00:00
Jason Ekstrand
265e234e23 nir: Fix the nir_builder include path for nir_builtin_builder
Because it's in double-quotes, it will search the current folder before
any search paths.  Since nir_builder.h and nir_builtin_builder.h are in
the same folder, this guarantees a correct include.  However,
nir/nir_builder.h does not unless the includer's path is set up just
right.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3897>
2020-02-21 18:48:03 +00:00
Michel Dänzer
f5a8958910 util: Change os_same_file_description return type from bool to int
This allows communicating that it wasn't possible to determine whether
the two file descriptors reference the same file description. When
that's the case, log a warning in the amdgpu winsys.

In turn, remove the corresponding debugging output from the fallback
os_same_file_description implementation. It depends on the caller if
false negatives are problematic or not.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3879>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3879>
2020-02-21 17:10:48 +01:00
Michel Dänzer
228cbdfe67 winsys/amdgpu: Make local variable r signed
This is consistent with the return type of the functions whose return
values we assign to it.

No functional change intended.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3879>
2020-02-21 17:09:05 +01:00
Karol Herbst
87365e263e nir/lower_ssbo: handle atomics
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2753>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2753>
2020-02-21 13:06:22 +00:00
Alyssa Rosenzweig
7ab4e4dd96 nir: Add SSBO->global lowering pass
To facilitate lowering SSBOs to globals, we need a load_ssbo_address
intrinsic. This intrinsic takes an SSBO index and loads the address in
global memory of the SSBO (likely implemented via a uniform in the
driver). In the future, we'll support bounds checking, but at the moment
this is not supported (this pass should only be used for trusted
contexts at the moment, i.e. contexts without robustness extensions).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2753>
2020-02-21 13:06:22 +00:00
Alyssa Rosenzweig
b929565ea8 panfrost: Rewrite texture descriptor creation logic
Rather than creating partially within the Gallium create function and
monkeypatching on draw time with code split across N different files
with tight Gallium dependencies, let's streamline everything into a
series of maintainable routines in mesa/src/panfrost with no Gallium
dependencies, doing the entire texture creation in one-shot and thus
adding absolutely zero draw-time overhead (since we can allocate a BO
for the descriptor and upload ahead-of-time, so switching textures is as
cheap as switching pointers).

Was this worth it? You know, I'm not sure :|

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3858>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3858>
2020-02-21 07:27:05 -05:00
Alyssa Rosenzweig
ad44f587a8 panfrost: Move format translation to root
Since PIPE formats are now shared across Mesa we can do this, and the
routines themselves are good enough code that I'm happy to move them
here. We'll use them momentarily.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3858>
2020-02-21 07:27:03 -05:00
Alyssa Rosenzweig
58f14018b4 panfrost: Move pan_afbc.c to root
Now that PIPE formats are shared across Mesa, this well-documented piece
of code is a good fit for root panfrost, let's move it and get a little
closer to taming the mess of resources.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3858>
2020-02-21 07:27:01 -05:00
Alyssa Rosenzweig
5ddf7ad9d2 panfrost: Move checksum routines to root panfrost
These are Gallium-independent and clean code; as is tradition, let's
hoist them up out of the Gallium driver as a bit of yak shaving as we
prepare to untangle the monster that is pan_resource.c

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3858>
2020-02-21 07:26:52 -05:00
Erik Faye-Lund
2e3318b151 util: promote u_debug_memory.c to src/util
When os_memory_debug.h was promoted to src/util, this source-file on
which it depends on when the debug-flag is set on windows was left
out. So let's move this also.

It doesn't seem there's any way of triggering this issue right now, but
it seems better to correct this to avoid this from biting us in the ass
in the future.

Fixes: 88c4680b5a ("util: promote u_memory to src/util")
Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3844>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3844>
2020-02-21 10:32:19 +01:00
Vasily Khoruzhick
8021daeb1f lima: implement PLB PP stream cache
Generating PLB PP stream is expensive. PLB PP stream content depends on
damage, and if damage consists of several rects it's impossible to come
up with a simple key.

Simplify damage to a single bounding box so we have a simple key
and cache PLB PP stream. Cache size is limited to 0.1% of system RAM and
once limit is reached least recently used entries are dropped.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3834>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3834>
2020-02-21 07:20:20 +00:00
Dylan Baker
7edde3d26b docs: Update index, relnotes, and release-calendar for 20.0
This includes the release schedule for 20.0.x. Currently there are four
planned releases, but I assume we'll need more before 20.1.0 is ready.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3896>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3896>
2020-02-20 14:15:37 -08:00
Dylan Baker
0ada39f37a Docs: Add 20.0.0 release notes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3896>
2020-02-20 14:04:20 -08:00
Samuel Pitoiset
740cb3d193 radv: use RADEON_FLAG_ZERO_VRAM when creating the trace BO
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888>
2020-02-20 18:47:34 +01:00
Samuel Pitoiset
37650bf938 radv/winsys: add a new flag that requests zerovram allocations
This introduces RADON_FLAG_ZERO_VRAM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3888>
2020-02-20 18:47:29 +01:00
Roland Scheidegger
7a73446c51 gallivm: fix crash in emit_get_buffer_size
Seems a bit odd we extract a value from a vector in the first place
(as we always extract the first element), but llvm asserts if using
a zero-vector instead of zero as the index element.
Fixes piglit crashes for example in arb_shader_storage_buffer_object-layout-std140-write-shader.

Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3886>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3886>
2020-02-20 17:32:54 +00:00
Roland Scheidegger
1b610aab58 gallivm: fix crash with bptc border color sampling
bptc uses fallback for decoding, but still need to handle border color
properly.

v2: adjust piglit gitlab-ci expectations

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3886>
2020-02-20 17:32:54 +00:00
Rhys Perry
8291d728dc aco: improve GFX9 1D ddx/ddy assertion
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2547
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3890>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3890>
2020-02-20 15:41:26 +00:00
Alyssa Rosenzweig
cc3d29c6e7 pan/midgard: Identify clamp(x, -1.0, 1.0) flag
So *that's* what's .unk2 was about :)

We still need to add an opt pass for it, but we can do that further down
the line.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3892>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3892>
2020-02-20 13:34:18 +00:00
Alyssa Rosenzweig
0263d2793c panfrost: Remove flush_frontbuffer
A relic from software rasterizers. Hardware drivers generally don't need
to implement this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3878>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3878>
2020-02-20 13:04:52 +00:00
Icecream95
068806c9f6 panfrost: LogicOp support
The generated shaders are definitely not optimal, but for a feature
hardly anyone uses, it's probably good enough.

The XScreensaver demos quasicrystal, blitspin, bouboule, crystal and
munch now seem to work, with no obvious problems.

Currently this only works for 8-bit textures.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3887>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3887>
2020-02-20 07:41:54 -05:00
Danylo Piliaiev
5bfd363be4 i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8
We don't support MESA_FORMAT_Z_UNORM16 before Gen8, see
intel_screen_init_surface_formats.

As a consequence disables B5G6R5_UNORM configs with depth
on gen < 6.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2275
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
2020-02-20 11:14:44 +00:00
Alexandros Frantzis
803ab5d6be gitlab-ci: Automated testing with OpenGL traces
Introduce automated testing of Mesa by replaying traces with Renderdoc
or Apitrace.

For now only LLVMPipe is tested, but other drivers can be tested if
there's runners with the necessary hardware.

Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2935>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2935>
2020-02-20 08:06:13 +01:00
Tomeu Vizoso
50f1950ac0 gitlab-ci: Disable the lima job for now
Some dEQP tests have started passing and it's taking a while to update
the expectations and skips list.

Disable for now so CI doesn't fail and stuff can be merged.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2935>
2020-02-20 08:06:08 +01:00
Marek Olšák
f7bfb10c69 util: remove the dependency on kcmp.h
Fixes: f76cbc7901 "util: Add os_same_file_description helper"

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3860>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3860>
2020-02-20 00:15:23 +00:00
Ian Romanick
273b8cd1ca intel/fs: Correctly handle multiply of fsign with a source modifier
The other source of the multiply will be interpreted as a uint32_t in an
XOR instruction.  Any source modifiers with either not be interpreted at
all or will be misinterpreted due to the differing types.

If the other operand of the multiplication has a source modifier, just
emit an extra move to resolve the source modifiers.

The negation source modifier problem is difficult to reproduce due to an
algebraic optimization that changes (-a*b) to -(a*b).  However, changes
in MR !1359 push the negations back down.

On Gen7+ it might be possible to do slightly better for an abs() source
modifier by using BFI2 as a glorified copysign().

On Gen8+ it might be possible to do slightly better for a neg() source
modifier by emitting (~a ^ b).

There were no shader-db changes on any Intel platform, so I think we can
deal with that problem when it arises.

See also piglit!224.

Fixes: 06d2c11641 ("intel/fs: Add a scale factor to emit_fsign")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
2020-02-19 23:51:42 +00:00
Thong Thai
c81aa15d64 gallium/auxiliary/vl: fix bob compute shaders for deint yuv
Scales the Y-axis by 2 when using the Bob deinterlace filter.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2523
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3857>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3857>
2020-02-19 23:23:07 +00:00
Bas Nieuwenhuizen
68d1757420 radeonsi: Fix compute copies for subsampled formats.
We cannot do image stores (or render) to subsampled formats.

Reinterpret as R32_UINT instead.

si_set_shader_image_desc already uses the blockwidth from
the view formats, so the image width adjustments are
already implemented.

This is still icky with mipmapping on GFX9+ though, but
since it is mostly a video format I don't think that will
be much of an issue and broken mipmapping is still better
than broken everything.

Fixes: e5167a9276 "radeonsi: disable SDMA on gfx8 to fix corruption on RX 580"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2535
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3853>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3853>
2020-02-19 22:51:12 +00:00
Jonathan Marek
d795eb207f turnip: add option to force use of hw binning
For running deqp tests which have small render sizes and don't otherwise
get coverage of hw binning / multiple tiles.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3851>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3851>
2020-02-19 22:24:44 +00:00
Dylan Baker
97a590af21 docs: Mark 20.0.0-rc3 as done
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3819>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3819>
2020-02-19 20:05:38 +00:00
Dylan Baker
772d60385c docs: Mark 19.3.4 as done
The calendar had an error, 19.3.4 and 19.3.5 had the same release date.
I've fixed the date for 19.3.5 and removed 19.3.6 which I don't believe
will be needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3819>
2020-02-19 20:05:38 +00:00
Dylan Baker
288e9fd295 docs: Add SHA256 sum for 19.3.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3819>
2020-02-19 20:05:38 +00:00
Dylan Baker
3238f4c3ab docs: Add release notes for 19.3.4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3819>
2020-02-19 20:05:38 +00:00
Chad Versace
d8fe9e045f anv: Drop anv_image.c:get_surface()
It was called exactly once, and even there it returned the wrong surface
in a corner case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3882>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3882>
2020-02-19 19:41:05 +00:00
Ian Romanick
58bdc1c748 nir/search: Use larger type to hold linearized index
"index" is an offset into a linearized 3-dimensional array.  Starting
with fbd5359a0a, the 3-dimensional array can have 43 elements in each
dimension.  43**3 = 79507, and that will overflow the uint16_t.

See also the discussion in MR !3765.

Fixes: fbd5359a0a ("nir/algebraic: Rearrange bcsel sequences generated by nir_opt_peephole_select")
Suggested-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3871>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3871>
2020-02-19 19:07:34 +00:00
Marek Olšák
912ee82521 gallium/util: remove unused u_surfaces.c/h
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3866>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3866>
2020-02-19 18:34:33 +00:00
Kristian H. Kristensen
360ffdf4e2 main/get: Converted type conversion macros to inline functions
Quiet warnings when called with a GLubyte:

  src/mesa/main/get.c:3215:19: warning: result of comparison of constant 32767 with expression of type 'GLubyte' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
      params[0] = INT_TO_FIXED(((GLubyte *) p)[0]);
                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  src/mesa/main/get.c:78:38: note: expanded from macro 'INT_TO_FIXED'
                                 ~~~ ^ ~~~~~~~~

Delete ENUM_TO_INT64, ENUM_TO_FIXED and BOOLEAN_TO_INT64 which aren't
used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3866>
2020-02-19 18:34:33 +00:00
Kristian H. Kristensen
f1dc4c9554 Mark a few static inline helpers with ASSERTED
Quiet warnings in release builds where these look unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3866>
2020-02-19 18:34:33 +00:00
Ian Romanick
d46a5cfe78 mesa/draw: Make sure all the unused fields are initialized to zero
Not initializing prim.indexed caused a few thousand failures on Intel
drivers.

I also compared the generated assembly with this change and before
a6d3158909.  The code is still somewhat improved, which I am assuming
was the original goal. _mesa_DrawArrays, for example, appears to drop an
instruction or two... though the body of the function is only one byte
shorter.

MR !3591 will eventually delete the uninitialized fields.  However, I
believe that explicitly initializing the whole thing is more future
proof.  This ensures that if someone adds fields in the future, they
will also be initialized.  Once the extra fields are removed, the two
implementations should generate idential code.

Fixes: a6d3158909 ("mesa: don't use memset in glDrawArrays")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3870>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3870>
2020-02-19 10:07:47 -08:00
Mathias Fröhlich
6edbb3c6d0 mesa: Fix FLUSH_VERTICES in SubpixelPrecisionBiasNV.
The FLUSH_VERTICES macro is supposed to be called before the current
context state is changed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2020-02-19 15:51:25 +01:00
Alyssa Rosenzweig
d3160a6177 panfrost: Remove old hack
I don't know why I thought this was needed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3855>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3855>
2020-02-19 08:02:03 -05:00
Alyssa Rosenzweig
7f6f419be9 panfrost: Remove old comment
We already handle primitive restart earlier in the function.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3855>
2020-02-19 08:01:59 -05:00
Alyssa Rosenzweig
aed052f703 panfrost: Remove dirty tracking
We never really respected it and it doesn't quite make sense for Mali
the way it was previously setup. The correct solution is to do push as
much code into CSO creation as possible.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3855>
2020-02-19 08:01:46 -05:00
Rhys Perry
fe5c5507bd aco: add some helpers for filling/testing register ranges
We do this a lot

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768>
2020-02-19 12:23:50 +00:00
Rhys Perry
43497e30e2 aco: add RegisterFile
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3768>
2020-02-19 12:23:50 +00:00
Michel Dänzer
7e6010106f st/vdpau: Only call is_video_format_supported hook if needed
Namely only if *is_supported is true, otherwise the hook result can't
affect it.

Avoids

../src/gallium/state_trackers/vdpau/vdpau_private.h:138: FormatYCBCRToPipe: Assertion `0' failed.

with assertions enabled.

Fixes: 5d5b414a7b "st/vdpau: fix chroma_format handling in
                     VideoSurfaceQueryGetPutBitsYCbCrCapabilities"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3848>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3848>
2020-02-19 12:41:08 +01:00
Danylo Piliaiev
72154237fb iris: Do not dereference nullptr with pipe_reference
../src/gallium/drivers/iris/iris_fence.h:54:8: runtime error: member access within null pointer of type 'struct iris_syncpt'

../src/gallium/drivers/iris/iris_fence.c:136:8: runtime error: member access within null pointer of type 'struct pipe_fence_handle'

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d800bcd9b9 glsl/blob: Do not call memcpy if there is nothing to copy
../src/util/blob.c:166:7: runtime error: null pointer passed as argument 2, which is declared to never be null
    #0 0x7fe51bc315df in blob_write_bytes ../src/util/blob.c:166
    #1 0x7fe51c7a7b9a in iris_disk_cache_store ../src/gallium/drivers/iris/iris_disk_cache.c:115
    #2 0x7fe51c7f444d in iris_compile_fs ../src/gallium/drivers/iris/iris_program.c:1693
    #3 0x7fe51c7fdcd9 in iris_create_fs_state ../src/gallium/drivers/iris/iris_program.c:2331
    #4 0x7fe519e871a3 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1275
    #5 0x7fe519e89dd0 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1435
    #6 0x7fe519ed51e1 in st_update_fp ../src/mesa/state_tracker/st_atom_shader.c:163
    #7 0x7fe519eb5d73 in st_validate_state ../src/mesa/state_tracker/st_atom.c:261
    #8 0x7fe519e4e0bf in prepare_draw ../src/mesa/state_tracker/st_draw.c:132
    #9 0x7fe519e4e76e in st_draw_vbo ../src/mesa/state_tracker/st_draw.c:184
    #10 0x7fe51aca5245 in vbo_save_playback_vertex_list ../src/mesa/vbo/vbo_save_draw.c:215
    #11 0x7fe51a25b1cc in ext_opcode_execute ../src/mesa/main/dlist.c:1126
    #12 0x7fe51a2f8d58 in execute_list ../src/mesa/main/dlist.c:11830
    #13 0x7fe51a34b2d0 in _mesa_CallList ../src/mesa/main/dlist.c:14267

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
7685f48ece intel/bufmgr: Cast bitshift to unsigned
../src/mesa/drivers/dri/i965/intel_buffer_objects.c:405:4: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'
    #0 0x7f9404ac4ae1 in brw_map_buffer_range ../src/mesa/drivers/dri/i965/intel_buffer_objects.c:405
    #1 0x7f9405a9cb13 in vbo_save_map_vertex_store ../src/mesa/vbo/vbo_save_api.c:261
    #2 0x7f9405b6a89d in vbo_save_NewList ../src/mesa/vbo/vbo_save_api.c:1774
    #3 0x7f94051aba3d in _mesa_NewList ../src/mesa/main/dlist.c:14172

../src/gallium/drivers/iris/iris_resource.c:1725:61: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'
    #0 0x7fe51c820c8e in iris_map_direct ../src/gallium/drivers/iris/iris_resource.c:1725
    #1 0x7fe51c82322c in iris_transfer_map ../src/gallium/drivers/iris/iris_resource.c:1895
    #2 0x7fe5202628be in u_transfer_helper_transfer_map ../src/gallium/auxiliary/util/u_transfer_helper.c:243
    #3 0x7fe51997c508 in pipe_buffer_map_range ../src/gallium/auxiliary/util/u_inlines.h:344
    #4 0x7fe51997ec8d in u_upload_alloc_buffer ../src/gallium/auxiliary/util/u_upload_mgr.c:221
    #5 0x7fe51997f24f in u_upload_alloc ../src/gallium/auxiliary/util/u_upload_mgr.c:254
    #6 0x7fe51ccf43af in upload_state ../src/gallium/drivers/iris/iris_state.c:323
    #7 0x7fe51d06963a in gen9_init_state ../src/gallium/drivers/iris/iris_state.c:7516
    #8 0x7fe51c7c2ea0 in iris_create_context ../src/gallium/drivers/iris/iris_context.c:294
    #9 0x7fe519dc729b in st_api_create_context ../src/mesa/state_tracker/st_manager.c:921
    #10 0x7fe5198c47ea in dri_create_context ../src/gallium/state_trackers/dri/dri_context.c:161
    #11 0x7fe519898aac in driCreateContextAttribs ../src/mesa/drivers/dri/common/dri_util.c:475

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d5931f285b intel/compiler: Do not qsort zero sized array
../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316:4: runtime error: null pointer passed as argument 1, which is declared to never be null
    #0 0x7f78f5916611 in brw_nir_analyze_ubo_ranges ../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316
    #1 0x7f78f255c189 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:97
    #2 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #3 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #4 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #5 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #6 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #7 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #8 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #9 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #10 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #11 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #12 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d596795d4d brw_fs: Avoid zero size vla
../src/intel/compiler/brw_fs.cpp:2247:46: runtime error: variable length array bound evaluates to non-positive value 0
    #0 0x7f78f5697678 in fs_visitor::assign_constant_locations() ../src/intel/compiler/brw_fs.cpp:2247
    #1 0x7f78f571d29e in fs_visitor::optimize() ../src/intel/compiler/brw_fs.cpp:7361
    #2 0x7f78f574eb84 in fs_visitor::run_fs(bool, bool) ../src/intel/compiler/brw_fs.cpp:8022
    #3 0x7f78f575641b in brw_compile_fs ../src/intel/compiler/brw_fs.cpp:8408
    #4 0x7f78f255c8e4 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:123
    #5 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #6 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #7 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #8 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #9 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #10 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #11 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #12 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #13 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #14 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #15 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Danylo Piliaiev
d4e395a27d brw_nir: Cast bitshift to unsigned
../src/intel/compiler/brw_nir.c:979:40: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
    #0 0x7f78f590d10b in brw_nir_apply_sampler_key ../src/intel/compiler/brw_nir.c:979
    #1 0x7f78f590e07b in brw_nir_apply_key ../src/intel/compiler/brw_nir.c:1057
    #2 0x7f78f5754b45 in brw_compile_fs ../src/intel/compiler/brw_fs.cpp:8347
    #3 0x7f78f255c8e4 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:123
    #4 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608
    #5 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56
    #6 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381
    #7 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119
    #8 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133
    #9 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163
    #10 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134
    #11 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360
    #12 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394
    #13 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169
    #14 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
2020-02-19 12:07:24 +02:00
Samuel Pitoiset
82913bac14 docs/envvars: document RADV_TEX_ANISO
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2524
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3873>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3873>
2020-02-19 08:46:03 +01:00
Eric Anholt
72f7d3d5b0 gallium: Only define PIPE_ALIGNSTACK on x86.
At least arm and arm64 don't respect this attribute, producing compiler
warnings in lp_test_format.c.  The gcc and LLVM docs for the attribute
only talk about them being needed on x86.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
427870abfd llvmpipe: Fix another uninitialized value warning, on init_val.
It's only used in the vote_ieq paths, but gcc doesn't see that.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
81225e1f03 llvmpipe: Silence uninitialized variable warning about "scissor"
nr_planes is only > 3 when scissor is enabled, but gcc doesn't see it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
dc8c5af99b llvmpipe: Silence uninitialized variable warning about "vals"
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
d8d34238a6 llvmpipe: Fix warning about uninitialized "op" in the NIR path.
Similar to TGSI, move the switch statement and use more unreachable().

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
b32bd704c0 llvmpipe: Silence uninitialized variable warning about "chan"
Both arms of an if define it, but gcc doesn't notice.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
ce611935df llvmpipe: Silence "possibly uninitialized value" warning for ssbo_limit.
The condition for the use matches the def, but you can't trust a compiler
to notice.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
45b2ccc6b3 llvmpipe: Fix real uninitialized use of "atype" for SEMANTIC_FACE
Fixes: 502548a09c ("gallivm/llvmpipe: add support for front facing in sysval.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:40:04 -08:00
Eric Anholt
13a276ed3b radv: Squelch possibly-undefined warning
The same condition is used in the def as in the use, but gcc wasn't
figuring it out.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3867>
2020-02-18 15:35:32 -08:00
Eric Anholt
1427f666dc ci: Extend the a630 flake list to reduce spurious failures.
These are the tests I've seen flake twice while logged in to the IRC
channel this year.  Also include fragment_out.random.5 which fully
spuriously failed recently.

Closes: #2516
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3862>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3862>
2020-02-18 22:40:33 +00:00
Marek Olšák
2e05a280b6 mesa: fix immediate mode with tessellation and varying patch vertices
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:47:30 -05:00
Marek Olšák
a6d3158909 mesa: don't use memset in glDrawArrays
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:46:55 -05:00
Marek Olšák
ee549c6766 mesa: document _mesa_prim::begin/end
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:45:50 -05:00
Marek Olšák
c9246282b7 vbo: remove redundant code in vbo_exec_fixup_vertex
Callers of this function also set FLUSH_STORED_VERTICES for attr == 0.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:45:34 -05:00
Marek Olšák
3eeeb86cb0 vbo: remove dead code in vbo_can_merge_prims
This is only used by immediate mode and the values are immutable.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:45:34 -05:00
Marek Olšák
2491a2ddeb st/mesa: try to fix MSVC build failure due to ALWAYS_INLINE
Fixes: 11db8e0e00 ("st/mesa: optimize st_update_array with ALWAYSINLINE")
Tested-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3861>
2020-02-18 16:45:34 -05:00
Rob Clark
06dc280a57 freedreno/registers: cleanup CP_SET_MARKER
1) Name RM6_COMPUTE, and rename RM6_ENDVIS (from RM6_BLIT) to better
   reflect what it actually does
2) Cleanup open-coded mode enum values
3) Removed unused 0x10

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
2020-02-18 20:52:42 +00:00
Rob Clark
7b4d6bb1ec freedreno: quiet INFO_MSG
Probably not useful unless LIBGL_DEBUG is set to something.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
2020-02-18 20:52:42 +00:00
Rob Clark
838ed2885d freedreno/a6xx: few register updates
Nothing used by mesa, but crashdec tool uses a few of these.  And since
the practice is these days to sync mesa->envytools, adding these on the
mesa side first.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
2020-02-18 20:52:42 +00:00
Rob Clark
4fc31e7d33 freedreno/registers: teach gen_header.py about a3xx_regid
This is a builtin type (treated as uint, but with special type-aware
decoding) in envytools/cffdump.  Lets teach gen_header.py about it and
drop the enum hack in the xml so I don't have to keep deleting the enum
when I sync the xml back to the freedreno envytools tree.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
2020-02-18 20:52:42 +00:00
Eric Engestrom
ecca5ef6c3 meson: explicitly disallow unsupported build directory layout
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2512
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3832>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3832>
2020-02-18 20:05:03 +00:00
Caio Marcelo de Oliveira Filho
79788b8f7f intel/gen12: Take into account opcode when decoding SWSB
The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.

This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies.  Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.

Fixes: 6154cdf924 ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c0127 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
2020-02-18 09:17:51 -08:00
Alyssa Rosenzweig
bee5c9b0dc panfrost: Remove enum panfrost_memory_layout
It duplicates mali_texture_layout. Let's use the native hardware enum
and spare a pointless translation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3854>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3854>
2020-02-18 16:20:56 +00:00
Caio Marcelo de Oliveira Filho
28e94e0a94 radv: Advertise VK_KHR_shader_non_semantic_info
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856>
2020-02-18 09:57:17 -06:00
Caio Marcelo de Oliveira Filho
8004cb256a anv: Advertise VK_KHR_shader_non_semantic_info
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856>
2020-02-18 09:57:15 -06:00
Jason Ekstrand
2dae89ac36 vulkan: Update the XML and headers to 1.2.133
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3856>
2020-02-18 09:57:14 -06:00
Alyssa Rosenzweig
7d3c48f131 panfrost: Debitfieldize mali_uniform_buffer_meta
It fits snugly in a u64, just give a macro for direct computation rather
than fudging around with bitfields. Not sure if this actually matters
with well-optimized compilers but it makes the code subjectively cleaner
so it's worth it for that if nothing else.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3838>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3838>
2020-02-18 14:44:08 +00:00
Alyssa Rosenzweig
027944c7c8 panfrost: Avoid reading GPU memory when packing vertices
These occurred unintentionally as a byproduct of bitfields, etc. Whoops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3838>
2020-02-18 14:44:08 +00:00
Alyssa Rosenzweig
4c52e16c9c panfrost: Cleanup transfer_map
A lot of these checks are obsolete since we've started tracking BO
accesses correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3849>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3849>
2020-02-18 14:13:18 +00:00
Alyssa Rosenzweig
308f9cf104 panfrost: Update scoreboarding notes
Our understanding of the set/write value jobs has evolved, so let's
update the rules.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:45:25 -05:00
Alyssa Rosenzweig
88323d1ba0 panfrost: Rewrite scoreboarding routines
Rather than manipulating job descriptor headers as fat pointers (slow)
and using fancy manipulation functions for programatically building the
tree in arbitrary orders (slow and complicated) and then having to do a
topological sort at runtime every frame (slow) which requires traversing
said headers in GPU memory (slow!)... we finally know enough about
the hardware to just get things right the first time, or second for
next_job linking. So rip out all that code and replace it with a much
better routine to create, upload, and queue a job all in one (since now
it's the same operation essentially - which is much better for memory
access patterns, by the way) and most everything falls into place
gracefully according to the rules we've set out. Even wallpapering isn't
*so* terrible if you just... move that one little... giant... hack out
of sight... ahem....

panfrost_scoreboard_link_batch is no longer a bottleneck, mostly because
it no longer exists :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:45:21 -05:00
Alyssa Rosenzweig
070bc883d3 panfrost: Print synced traces to stderr
To match the existing behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:45:18 -05:00
Alyssa Rosenzweig
c46a090942 panfrost: Implement PAN_DBG_SYNC with pandecode/minimal
This way we avoid duplicating job traversal logic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:45:14 -05:00
Alyssa Rosenzweig
5998646125 pan/decode: Cleanup pandecode_jc
Some of this code is, to put it mildly, impossibly ancient horsedropping
crazy cruft.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:45:09 -05:00
Alyssa Rosenzweig
4122f747ac pan/decode: Add minimal mode
We would like a mode to skip decoding job payloads so we can just
inspect for faults.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3836>
2020-02-18 08:44:59 -05:00
Danylo Piliaiev
b684ba6ce7 st/nir: Unify inputs_read/outputs_written before serializing NIR
Otherwise input/output interfaces won't be unified when reading
NIR from a cache.

Fixes piglit test on iris:
  clip-distance-vs-gs-out.shader_test

Fixes: 19ed12af

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3787>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3787>
2020-02-18 09:18:37 +00:00
Erik Faye-Lund
9903f10636 zink: do not convert bools to/from uint
Since bools are the only 1-bit type, we always know if an SSA-def is a
bool or not. So we don't need to marshal it to uint.

So let's simplify the code a bit here.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
Erik Faye-Lund
4d016de250 zink/spirv: uint -> raw
Similarly to the previous commit, the important bit here is the rawness
of these variables, not the uintness. So let's rename these to reflect
this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
Erik Faye-Lund
7c1a2cbcad zink/spirv: unit_value -> raw_value
The point here isn't that the value is uint, but that is't untreated. So
raw seems more fitting as a description.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
Erik Faye-Lund
16339646f0 zink/spirv: rename functions a bit
The code is about to change so the whole uint-story isn't as true as it
used to be. So let's soften up the semantics a bit here; we only care
about if we're doing a typed ot untyped store here, really.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
Erik Faye-Lund
a6211a4247 zink/spirv: prefer store_dest over store_dest_uint
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
Erik Faye-Lund
7e8f7df800 zink/spirv: do not reinvent store_dest
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3763>
2020-02-17 12:46:54 +00:00
luc
692093fbdc zink: confused compilation macro usage for zink in target helpers.
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3831>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3831>
2020-02-17 12:21:01 +00:00
Erik Faye-Lund
b7e966dc7f zink: do not report texture-samplers for unsupported stages
This caused the max combined samplers to be reported as artificially
high.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3826>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3826>
2020-02-17 10:00:18 +00:00
Erik Faye-Lund
4a20db70de zink: fix binding-usage
Rewriting the variable bindings is nasty and error-prone, and this code
triggered an assert when trying to resolve API bindings into Vulkan
bindings.

This code still needs some tweaks, but this makes things much better,
and fixes a few bugs where we incorrectly accounted for the
array-indexes.

Fixes: 1c3f4c0704 ("zink: fixup sampler-usage")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3826>
2020-02-17 10:00:18 +00:00
Samuel Pitoiset
c095b7d5bd radv: add a comment about VK_AMD_mixed_attachment_samples on GFX6-GFX7
There is some CTS failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808>
2020-02-17 08:33:44 +01:00
Samuel Pitoiset
4159b24be7 radv: enable VK_NV_compute_shader_derivatives on GFX6-GFX7
All Crucible tests pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808>
2020-02-17 08:33:42 +01:00
Samuel Pitoiset
83dd0cace6 radv: enable VK_EXT_sampler_filter_minmax on GFX6
Works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808>
2020-02-17 08:33:40 +01:00
Samuel Pitoiset
170c3a8b7b radv: enable shaderStorageImageMultisample on GFX6-GFX7
It was disabled because untested, but CTS is happy with it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3808>
2020-02-17 08:32:26 +01:00
Mathias Fröhlich
c7617d8908 egl: Implement getImage/putImage on pbuffer swrast.
This change adds getImage/putImage callbacks to the swrast pbuffer
loader extension.
This fixes a recent crash with Weston as well as a crashing
test with classic swrast without an official gitlab issue.

v2: Determine bytes per pixel differently and fix non X11 builds.
v3: Plug memory leak and fix crash on out of bounds access.
    (Daniel Stone)
v4: Follow the code structure of the wayland get/put image
    implementation - hopefully being more obvious.
    Handle 64 bits formats.
    Use BufferSize directly.
    (Emil Velikov)
v5: Change pixel size computation.
    (Eric Engestrom)

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2219
Fixes: d6edccee8d "egl: add EGL_platform_device support"
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3711>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3711>
2020-02-17 04:01:37 +00:00
Qiang Yu
6fc0890cd9 lima: rename lima_submit to lima_job
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
57d9a51d45 lima: move dump check to macro for lima_dump_command_stream_print
This can prevent the execution of some function like lima_ctx_buff_va
which is passed in as parameter when no dump case.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
5502bc83b0 lima: enable multi submit optimization
Also provide a debug option to disable it.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
131c505690 lima: optinal flush submit in lima_clear
flush current submit only when there is any draw pending instead of
flush all submits.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
d6ad8e590f lima: use per submit dump file
After multi lima_submit, commands for one lima_submit may not be
flushed when change framebuffer. But we want to track command
stream for one submit, so save dump file for each submit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
d0dde3de25 lima: move framebuffer info to lima_submit
draw code path does not use framebuffer info, only flush
code path use it now.

Use zsbuf/cbuf in submit instead of context.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
ed117ee630 lima: move clear into submit (v2)
clear info is needed when submit flush and may be changed after
framebuffer switch, so we need to move it into submit.

This also fixes 5 dEQP tests as a side effect: clear info is per
submit so clear value when one submit won't affect next submit.

v2:
remove fixed dEQP test from CI list.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
4b93792274 lima: move damage_rect into lima_submit
damage_rect is preserved across draws.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
a4b048c046 lima: move pp_max_stack_size to lima_submit
pp_max_stack_size is preserved across draws.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
6a5b1c62db lima: move resolve into lima_submit
resolve is preserved across draws.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
7e5abc11f4 lima: move plbu/vs_cmd_array into lima_submit
This information is preserved across draws and needed
when task submission.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
c64994433c lima: track write submits of context (v3)
We need to flush submit which write to the FBO before read it as
texture.

v2:
rename lima_flush_previous_write_submit to
lima_flush_previous_submit_writing_resouce.

v3:
delay add submit to hash_table to lima_update_submit_wb when really
know the render target will be written.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
48fc5f841a lima: make lima_submit one time use drop data (v3)
lima_submit is created by lima_submit_get() in draw/clear functions
and freed after submit to kernel.

There is a hash map to find the same lima_submit for color/depth
buffer combination if user switch framebuffer w/o flush the command
then switch back again.

v2:
rename lima_flush_submit to lima_flush_submit_accessing_bo.

v3:
delay flush access submit to lima_update_submit_wb when really know
if this submit will write to the target buffer.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
545988c617 lima: add lima_submit_get
Replace all usage of "ctx->submit" in draw code path with
lima_submit_get(). This function will create new submit
in the following changes.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
0caefb6d9d lima: use lima_submit_create_stream_bo for plbu/vs_cmd and pp_stack
lima_ctx_buff is used cross function calls in draws. But plbu/vs_cmd
and pp_stack are used immediately after create. And we need to get
rid of "ctx->submit" in the flush code path which exists in
lima_ctx_buff.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
ed8837f946 lima: adjust pp_stream to use lima_submit_create_stream_bo
No need to save the bo, just map and va for use in this submit
is enough.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
e90d8b6e4d lima: add lima_submit_create_stream_bo
For creating stream buffer which is used in single submit
and freed after the submit is passed to kernel driver.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
5c78ba6014 lima: pass submit parameter for functions in lima_submic.c (v2)
"ctx->submit" won't be used directly, so remove the usage in
lima_submit.c by directly passing the submit parameter. And
more data in lima_context will be moved to lima_submit, so
"ctx" will be replaced by "submit" in those functions.

v2:
rename lima_submit_flush to lima_do_submit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
21a2ce71b1 lima: move flush code to lima_submit.c
Just code move, no content change.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
29c7235507 lima: put hardware related info to lima_gpu.h
For sharing with multi .c files.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
09127641f4 lima: merge gp/pp submit
Use single lima_submit for the submit operation. This is also
for moving more information in lima_context to lima_submit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
79c65fa56f lima: move syncobj from lima_submit to lima_context
As there will be multi lima_submit per context, move
syncobj out of it.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
b9003111bb lima: add missing resolve check for damage and reload
If color buffer is not touched, we do not need to reload or get
damage region from it.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
47200f5c8d lima: add render target to submit by dirty buffer flags
No need to add un-touched buffer to submit.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
32f1733972 lima: delay plbu head command generation to flush stage (v2)
Prepare for multi submit in which case only know the plb_index when
final flush. Another need for this is proper reload detection: only
when flush stage can we know if need to do reload, because user may
first clear depth, then color individually, so we don't know if need
to pack repload plbu cmd when first clear depth.

v2:
move lima_update_submit_wb before ctx->resolve change for lima_ctx_dirty
to work in lima_submit_wb.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
ccfe5f9d28 lima: delay add plb buffer to submit when flush
Prepare for multi submit in which case plb buffer is known
only when flush.

Keep the write back buffer update which is needed for FB
dirty track.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
92387ca236 lima: pass array as parameter to PLBU and VS command macros
Don't assume the ctx parameter, prepare for moving PLBU and
VS arrary from lima_context to lima_submit and adding new
plbu_cmd_head array.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
c3bbe4f7f8 lima: remove lima_ctx_buff_va submit flags (v2)
We don't have any shared lima_ctx_buff for both GP and PP,
so no need to have these flags.

v2:
still add submit in lima_ctx_buff_va because some bo need
to exist cross flush, so not every submit will call
lima_ctx_buff_alloc.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
9f924c795b lima: always add texture bo to submit
No matter texture desc change, we need to add texture to submit.
Otherwise texture may be freed before submit finish.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
3c4ff27250 lima: use util_copy_framebuffer_state
Use this helper to replace self written code.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Qiang Yu
c8b53d8020 lima: remove definition of lima_is_scanout
There is no implementation of this function.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>
2020-02-17 02:54:15 +00:00
Alyssa Rosenzweig
0c4a70b64d pan/decode: Remove extraneous newline
pandecode_log already does this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:50 -05:00
Alyssa Rosenzweig
8ab0bf1f93 pan/midgard: Use fprintf instead of printf for constants
I was wondering where those constants disappeared to :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 968f36d1fc ("pan/midgard: Support disassembling to a file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:50 -05:00
Alyssa Rosenzweig
6af14d3685 pan/midgard: Don't crash with constants on unknown ops
Just use a dummy name instead.. we can't know a priori what type an
unknown op will consume, but we don't want to dereference a null
pointer.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 24360966ab ("panfrost/midgard: Prettify embedded constant
prints")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:50 -05:00
Alyssa Rosenzweig
5c06ecd2c6 pan/midgard: Identify stack barrier flag
In case thread local storage is used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:49 -05:00
Alyssa Rosenzweig
d3747fb1eb pan/midgard: Set xyzx swizzle for load_compute_arg
Probably harmless but the w component doesn't appear valid so let's
match the blob... one less bit to be nervous about.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:48 -05:00
Alyssa Rosenzweig
f0ee55ad2a pan/midgard: Infer tags entirely
We're so close, again marking off a few edge cases is enough to allow us
to omit this data entirely. Woot!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:48 -05:00
Alyssa Rosenzweig
57a84278fd pan/midgard: Imply next tags
As long as we can disambiguate a few edge cases, we can imply next tags
entirely which cleans up the disassembly a fair bit (though not as much
as implying tags entirely would -- we'll get there!)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
453c64663c pan/midgard: Overhaul tag handling
We unify disparate metadata about tags into a single structure to ensure
information is not left out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
9168e7a65d pan/midgard: Improve barrier disassembly
Just move some state from unknowns to actual keywords.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
d208212f80 pan/midgard: Use dummy tag for empty shaders
Fixes INSTR_INVALID_ENC in dEQP-GLES31.functional.compute.basic.empty

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
b2cab6b6db pan/midgard: Fix 32/64 mixed swizzle packing
Occurs in SSBO address computation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
a55a2e02a5 pan/midgard: Allow jumping out of a shader
This comes up as a `return;` instruction in a compute shader. We need to
use the special tag 1 to signify "break". Fixes numerous
INSTR_INVALID_ENC faults in dEQP-GLES31.functional.compute.basic.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
3f59098d1a pan/midgard: Implement barriers
Barriers execute on the texture pipeline on Midgard, so let's
tentatively handle barrier() as conservatively as possible (forcing
memory barriers of both buffers and shared memory). Implementation isn't
quite there yet -- it doesn't look at interactions of adjacent barriers
like it's supposed to -- but the core is there.

Fixes dEQP-GLES31.functional.compute.basic.ssbo_local_barrier_single_invocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
4f0b928921 pan/midgard: Fix swizzles harder
Just for disassembly for now~

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:47 -05:00
Alyssa Rosenzweig
fbe1fd3de0 pan/midgard: Fix missing prefixes
I was wondering where those were going... :)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: c1952779d6 ("pan/decode: Dump to a file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
521406a069 pan/midgard: Track pressure when scheduling ld/st
Fixes RA failure in
dEQP-GLES31.functional.shaders.builtin_functions.common.modf.* (which
uses multiple indirect SSBO writes)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
9603126b74 panfrost: Allocate RAM backing of shared memory
Unlike other GPUs, Mali does not have dedicated shared memory for
compute workloads. Instead, we allocate shared memory (backed to RAM),
and the general memory access functions have modes to access shared
memory (essentially, think of these modes as adding this allocates base
+ workgroupid * stride  in harder). So let's allocate enough memory
based on the shared_size parameter and supply it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
50138abb5a panfrost: Rename unknown2_8 to padding
It's zero everywhere.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
6d9ee3e65a panfrost: Rename bifrost_framebuffer->mali_framebuffer
(And bifrost_fb_extra to mali_framebuffer_extra, bifrost_render_target
to mali_render_target)

These structures are the norm on midgard t760+, drop the bifrost names,
it's silly... unrelated to the rest of the series but while I'm messing
with pandecode and cleaning up bifrost abstractions, might as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
6dc105555b panfrost: Unify bifrost_scratchpad with mali_shared_memory
It looks like these are the same structure, so this allows us to reuse
mali_shared_memory across architectures, and dispels with the
Bifrost-specific mystery of the scratchpads... nothing so mysterious
after all, just stack.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
254f40fd53 panfrost: Identify mali_shared_memory structure
This small structure is used to configure shared memory and stack for
compute shaders, and is also present at the beginning of framebuffer
descriptors. Let's factor it out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
418ca5dc1a panfrost: Ensure compute shader_meta is zeroed
In theory the hardware doesn't care but it'll make for easier traces.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Alyssa Rosenzweig
058faf5a4b panfrost: Update comment about magic number relating to barriers
It's a complicated story. But from what I can tell, in GL compute
without barriers, the blob is able to redistribute the workgroups in
various ways (that are not yet understood), whereas with barriers it
cannot redistribute anything, which accounts for erratic workgroup
packing without barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
2020-02-16 09:16:46 -05:00
Dave Airlie
8f5a252d35 ci: bump debian image and change llvm deps to 8
v3: remove version in a few places (Michel)

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>
2020-02-15 04:15:00 +00:00
Dave Airlie
e7375e1795 gallivm/s390: fix pass init order on s390 with llvm 8 (v2)
llvm 8 has some missing pass dependencies, fix the s390 case
as well.

v2: add ARM also (Michel)

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>
2020-02-15 04:15:00 +00:00
Kenneth Graunke
a603822b2f iris: Trim "../../src/gallium/drivers/iris/" out of debug dump filenames
Easier to read.

v2: Also trim "/iris/" (Jordan Justen)

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>
2020-02-15 00:55:55 +00:00
Kenneth Graunke
96f247d1b3 iris: Dump frame markers with INTEL_DEBUG=submit
Now you can see which batches go with which frames.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>
2020-02-15 00:55:55 +00:00
Marek Olšák
e395ce03e9 gallium/cso_hash: remove another layer of pointer indirection
Convert this:

    struct cso_hash {
       union {
          struct cso_hash_data *d;
          struct cso_node      *e;
       } data;
    };

to this:

    struct cso_hash {
       struct cso_hash_data data;
       struct cso_node      *end;
    };

1) data is not a pointer anymore.
2) "end" points to "data" and acts as the end of the linked list.
3) This code is still crazy.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:28 -05:00
Marek Olšák
e0bb7b87e2 gallium/cso_hash: cosmetic changes, no behavior changes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:28 -05:00
Marek Olšák
789ed29d59 gallium/cso_hash: remove always constant variable nodeSize
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:28 -05:00
Marek Olšák
a8bbf10540 gallium/cso_hash: make cso_hash declared within structures instead of alloc'd
This removes one level of indirection.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:28 -05:00
Marek Olšák
f8594a06e4 gallium/cso_hash: inline a bunch of functions
I'm probably not getting anything out of this, but it's harmless.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
cf86f522b2 gallium/u_vbuf: adjust the heuristic for unrolling indices
This improves performance in the first subtest of Viewperf11/Catia by 10%.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
55d8baa285 gallium/u_upload_mgr: don't do align twice in the u_upload_alloc fast path
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
19c18d532e gallium/u_upload_mgr: reduce dereferences by adding buffer_size
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
909a2d0ed3 st/mesa: simplify releasing the current attrib buffer
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
6954efce23 st/mesa: make st_setup_current static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
e3617fd00b st/mesa: change some loops from while to do..while in st_atom_array.c
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
fd6636ebc0 st/mesa: simplify determination whether a draw needs min/max index
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
1d93372802 st/mesa: simplify determination whether a draw has user vertex buffers
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
61e4c582e0 st/mesa: always inline the code setting non-64bit vertex elements
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
3c98dccd40 mesa: remove unused _mesa_draw_indirect
All drivers that expose ARB_draw_indirect also set the driver callback.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Marek Olšák
e6448f993b mesa: translate into gallium vertex formats in mesa/main
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
2020-02-14 18:16:27 -05:00
Francisco Jerez
8d3b86e34a intel/fs/gen7+: Implement discard/demote for SIMD32 programs.
At this point this simply involves fixing the initialization of the
sample mask flag register to take the right dispatch mask from the
thread payload, and fixing sample_mask_reg() to return f1.1 for the
second half of a SIMD32 thread.  This improves Manhattan 3.1
performance by 2.4%±0.31% (N>40) on my ICL with SIMD32 enabled
relative to falling back to SIMD16 for the shaders that use discard.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:49 -08:00
Francisco Jerez
04c7d3d4b1 intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.
In SIMD32 programs that don't use discard, the upper 16 bits of the UD
result of sample_mask_reg() don't contain the sample mask of the upper
16 channels as one would expect.  Stop pretending we are returning a
valid 32-bit mask.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:49 -08:00
Francisco Jerez
1c6853a9be intel/fs: Refactor predication on sample mask into helper function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
a792e11f5c intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.
FIND_LIVE_CHANNEL was using f1.0-f1.1 as temporary flag register on
Gen7, instead use f0.0-f0.1.  In order to avoid collision with the
discard sample mask, move the latter to f1.0-f1.1.  This makes room
for keeping track of the sample mask of the second half of SIMD32
programs that use discard.

Note that some MOVs of the sample mask into f1.0 become redundant now
in lower_surface_logical_send() and lower_a64_logical_send().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>x
2020-02-14 14:31:48 -08:00
Francisco Jerez
083fd96a97 intel/fs: Use helper for discard sample mask flag subregister number.
Use it instead of hard-coding f0.1 for the sample mask of programs
that use discard.  This will make the task easier when we replace f0.1
with another flag register location in order to support discard with
SIMD32 shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
a6bc11a789 intel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.
It's only really useful there.  This will avoid confusion with another
helper with a similar purpose I'm about to introduce that will be
useful in multiple files from the FS back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
b84fa0b31e intel/fs/gen11: Work around dual-source blending hangs in combination with SIMD32.
The SIMD8 dual-source blending framebuffer write messages seem to have
trouble releasing the pixel scoreboard dependency in SIMD32 dispatch
mode, which leads to hangs.  I have a better workaround for this which
doesn't involve disabling SIMD32 when dual-source blending is enabled,
but I'm still investigating some issues with it.  Limit the dispatch
width to SIMD16 in such cases for the moment in order to make the CI
happy on ICL with SIMD32 fragment shaders enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
57dee58c82 intel/fs: Set src0 alpha present bit in header when provided in message payload.
Currently the "Source0 Alpha Present to RenderTarget" bit of the RT
write message header is derived from brw_wm_prog_data::replicate_alpha.
However the src0_alpha payload is provided anytime it's specified to
the logical message.  This could theoretically lead to an
inconsistency if somebody provided a src0_alpha value while
brw_wm_prog_data::replicate_alpha was false, as I'm planning to do in
a future commit in order to implement a hardware workaround.

Instead calculate the header bit based on whether a src0_alpha value
was provided to the logical message, which guarantees the same
behavior on pre-ICL and ICL+ (the latter used an extended descriptor
bit for this which didn't suffer from the same issue).  Remove the
brw_wm_prog_data::replicate_alpha flag.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
e14529ff32 intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow.
Together with the fixup_nomask_control_flow() pass introduced in a
previous patch, this implements a less invasive alternative to the
workaround documented in the hardware spec for GEN:BUG:1407528679,
which doesn't involve disabling structured control flow.

Under some conditions Gen12 hardware can end up executing a BB with
all channels disabled, which will lead to the execution of any NoMask
instructions in it, even though any execution-masked instructions will
be correctly shot down.  This could break assumptions of the SWSB pass
if the data computed by a NoMask instruction is synchronized against
by using an SWSB annotation baked into a regular execution-masked
instruction, since the first (NoMask) instruction may be executed
redundantly by the hardware, even though the second will correctly be
shot down, potentially leading to a RaW or WaW hazard if a third
instruction subsequently accesses the destination register of the
first instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
4e4e8d793f intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.
Found by inspection.  Existing code was trying to avoid assuming that
an SBID had been assigned to the virtual instruction, but
synchronizing the header setup with respect to the previous SIMD16
SEND by using SYNC.ALLRD doesn't really seem possible unless the SEND
instruction had been assigned an SBID.  Assert-fail instead if no SBID
has been allocated.

Fixes: 15e3a0d9d2 "intel/eu/gen12: Set SWSB annotations in hand-crafted assembly."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
a8ac0bd759 intel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask control flow.
This is a less invasive alternative to the workaround documented in
the hardware spec for GEN:BUG:1407528679, which doesn't involve
disabling structured control flow (it's unlikely that switching to
GOTO/JOIN would have actually fixed the problem anyway).

Under some conditions Gen12 hardware can end up executing a BB with
all channels disabled, which will lead to the execution of any NoMask
instructions in it, even though any execution-masked instructions will
be correctly shot down.  This may break assumptions of some NoMask
SEND messages whose descriptor depends on data generated by live
invocations of the shader.

This avoids the problem by predicating certain instructions on an ANY
horizontal predicate that makes sure that their execution is omitted
when all channels of the program are disabled.  The shader-db impact
of this patch seems to be minimal:

total instructions in shared programs: 17169833 -> 17169913 (0.00%)
instructions in affected programs: 30663 -> 30743 (0.26%)
helped: 0
HURT: 42

total cycles in shared programs: 336966176 -> 336968568 (0.00%)
cycles in affected programs: 2367290 -> 2369682 (0.10%)
helped: 0
HURT: 13

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
008f95a043 intel/fs: Add virtual instruction to load mask of live channels into flag register.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
b8b509fb92 intel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.
We need to pass a width of 32 since the opcode bashes the whole f1.0
register on IVB.  This is unlikely to have caused problems since f1.0
is largely unused currently.  That's likely to change soon though,
even on platforms other than Gen7.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Francisco Jerez
c9e33e5cbf intel/fs/cse: Make HALT instruction act as CSE barrier.
Found by inspection.  This seems particularly likely to cause problems
with instructions dependent on the current execution mask like
SHADER_OPCODE_FIND_LIVE_CHANNEL or the FS_OPCODE_LOAD_LIVE_CHANNELS
instruction I'm about to introduce, but one could imagine it leading
to data corruption if CSE ever managed to combine two instructions
before and after the FS_OPCODE_PLACEHOLDER_HALT, since the one before
may not be executed for some channels.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
2020-02-14 14:31:48 -08:00
Andreas Baierl
fe1b0b7c50 lima/parser: Extend rsw parsing showing strings instead of numbers
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807>
2020-02-14 21:48:25 +00:00
Marek Olšák
7e2b4bf256 radeonsi: don't wait for shader compilation to finish when destroying a context
This was a hack for glsl_types deinitialization and it predates the proper
fix, which was the addition of glsl_type_singleton_decref.

This fixes a crash when the context is destroyed via the atexit handler.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
2020-02-14 16:19:38 -05:00
Eric Engestrom
7bee388fb5 egl: directly access static members instead of using _egl{Get,Set}ConfigKey()
This function is meant for when the attribute is unknown at compile-time
(eg. user-specified), but in all these cases it is much simpler to just
read/write the member directly.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816>
2020-02-14 18:03:07 +00:00
Jonathan Marek
946eacbafb freedreno/a6xx: document some unknown bits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
2020-02-14 08:22:33 -05:00
Jonathan Marek
75fbe089a6 freedreno: name sysmem color/depth flush events
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
2020-02-14 08:22:33 -05:00
Alyssa Rosenzweig
c57456aab6 panfrost: Simplify swizzle translation
It lines up anyway, and Gallium shouldn't change this. (And if it does,
we'll deal with that then since CI would start failing.)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
2020-02-14 12:53:36 +00:00
Icecream95
f3490a141c panfrost: Inline panfrost_get_default_swizzle
This commit replaces panfrost_get_default_swizzle with an inlined
implementation where the returned values can be determined at compile
time.

According to perf, this previously used about 2% CPU for Openarena.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
2020-02-14 12:53:36 +00:00
Elie Tournier
efda2cfcf9 spirv2nir: Add kernel spirv support
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
2020-02-14 11:14:58 +00:00
Elie Tournier
eeb6d61128 spirv2nir: print nir shader if translation succed
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
2020-02-14 11:14:58 +00:00
Erik Faye-Lund
7e80b03dd1 zink: do not use SpvDimRect
Vulkan doesn't support SpvDimRect. But we don't need to pass this at
all, as we already mark the sampler as un-normalized.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764>
2020-02-14 10:51:46 +00:00
Vasily Khoruzhick
f43a3fc28f lima: handle early-z and pixel kill better
[1] calls bit 12 of aux0 'pixel kill' which is likely forward pixel
kill described in [2]. Blob sets this bit if early-z is enabled and
blending is disabled and colormask is RGBA.

Bit 8 seems to be always enabled with bit 9 (early-z).

Let's mimic blob behavior.

[1] https://web.archive.org/web/20171026123213/http://limadriver.org/Render_State/
[2] https://community.arm.com/developer/tools-software/graphics/b/blog/posts/killing-pixels---a-new-optimization-for-shading-on-arm-mali-gpus

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754>
2020-02-14 10:03:01 +00:00
Michel Dänzer
582d0c5f14 gitlab-ci: Add three more dEQP-GLES31 tests to softpipe skips
These have randomly flipped lately, see e.g.
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/1620056
https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1621374
https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1622156

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
2020-02-14 09:55:48 +01:00
Michel Dänzer
3d16bfc42d gitlab-ci: Sort random failure softpipe skips
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
2020-02-14 09:55:10 +01:00
Samuel Pitoiset
f86bf2e90a docs/new_features: empty the feature list for the 20.1 cycle
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793>
2020-02-14 07:31:20 +00:00
Samuel Pitoiset
886acbe1c5 radv: remove unnecessary RADV_DEBUG=nobatchchain option
It was used in the past but nowadays chained submissions work fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791>
2020-02-14 07:48:14 +01:00
Timothy Arceri
676869e1d4 glsl: fix gl_nir_set_uniform_initializers() for image arrays
The if was incorrectly checking for an image type on what could
be an array of images. Here we change it to use the type stored
in uniform storage which has already been stripped of arrays,
this is what the above code for samplers does also.

Fixes: 2bf91733fc ("nir/linker: Set the uniform initial values")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
2020-02-14 01:37:03 +00:00
Rafael Antognolli
6baeca3689 intel/tools: Update aubinator_error_decode.
"ringbuffer" is now called only "ring" in the error state.

v2: Keep compatible with old error state (Lionel).
v3: Also update "gtt_offset" -> "batch".

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1206
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-02-13 16:53:18 -08:00
Rob Clark
334788d4cc freedreno: allow INVALID modifier
Re-allow INVALID modifier in import path.  The legacy import path
(createImageFromFds()), which is used by android, uses the INVALID
modifier.  Previously we would ignore this and just setup the imported
buffer as linear.  Restore this behavior to unbreak the legacy import
path.

Fixes: 9891062642 freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817>
2020-02-13 19:16:17 +00:00
Sagar Ghuge
3547e19bbd intel/isl: Switch to R8_UNORM format for compatiblity
Gen12 added CCS_E support for A8_UNORM. Intercept A8_UNORM format and
switch to R8_UNORM, as both share the same aux map format encoding so
they are compatible.

Fixes Piglit's ext_framebuffer_multisample-formats all_samples, which
was hitting an assert about A8_UNORM and R8_UINT not being CCS_E
compatible formats.

v2: Add gen check (Kenneth Graunke)

v3: Intercept A8_UNORM and set format to R8_UNORM (Jason Ekstrand)

v4:
- Remove gen check and move block little bit down (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
2020-02-13 18:44:50 +00:00
Sagar Ghuge
207a93bbff intel/isl: Move get_format_encoding function to isl
Move get_format_encoding function to isl and rename to
isl_get_aux_map_format_encoding.

v2:
- Rename isl_get_aux_map_format_encoding to
  isl_format_get_aux_map_encoding (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
2020-02-13 18:44:50 +00:00
Fritz Koenig
2a98cf3b2e Revert "gitlab-ci: disable a630 tests as mesa-cheza is down (again)"
This reverts commit 18657c0c0a

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
2020-02-13 18:13:55 +00:00
Jonathan Marek
5a82273f09 freedreno/a6xx: fix Z24_UNORM_S8_UINT_AS_R8G8B8A8
CI didn't run so missed this.

Note previously had :
   texfmt = TFMT6_Z24_UNORM_S8_UINT
   rbfmt = RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8

which are both now FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8

Fixes: 18786cc7d5 ("freedreno/a6xx: use single format enum")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
2020-02-13 18:13:55 +00:00
Lionel Landwerlin
4151d84323 iris: add support INTEL_blackhole_render
v2: Use a software mechanism to manage blackhole state

v3: s/iris_batchbuffer/iris_batch/ (Ken)

v4: Fixup state transition mistake (Ken/Lionel)

v5: Cleanup iris_batch_flush (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
2020-02-13 17:05:05 +00:00
Lionel Landwerlin
6d35610bd5 st: add support for INTEL_blackhole_render
Adding a new CSO proved to be fairly difficult especially because this
extension affect draw/dispatch/blit alike.

Instead this change passes the state of the noop into the entry points
emitting the operations affected.

v2: Fix assert in default pipe caps

v3: Drop whitespace changes (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
2020-02-13 17:05:05 +00:00
Lionel Landwerlin
5d7e9edba1 i965: enable INTEL_blackhole_render
v2: condition the extension on context isolation support from the
    kernel (Chris)

v3: (Lionel)

    The initial version of this change used a feature of the Gen7+
    command parser to turn the primitive instructions into no-ops.
    Unfortunately this doesn't play well with how we're using the
    hardware outside of the user submitted commands. For example
    resolves are implicit operations which should not be turned into
    no-ops as part of the previously submitted commands (before
    blackhole_render is enabled) might not be disabled. For example
    this sequence :

       glClear();
       glEnable(GL_BLACKHOLE_RENDER_INTEL);
       glDrawArrays(...);
       glReadPixels(...);
       glDisable(GL_BLACKHOLE_RENDER_INTEL);

    While clear has been emitted outside the blackhole render, it
    should still be resolved properly in the read pixels. Hence we
    need to be more selective and only disable user submitted
    commands.

    This v3 manually turns primitives into MI_NOOP if blackhole render
    is enabled. This lets us enable this feature on any platform.

v4: Limit support to gen7.5+ (Lionel)

v5: Enable Gen7.5 support again, requires a kernel update of the
    command parser (Lionel)

v6: Disable Gen7.5 again... Kernel devs want these patches landed
    before they accept the kernel patches to whitelist INSTPM (Lionel)

v7: Simplify change by never holding noop (there was a shortcoming in the test not considering fast clears)
    Only program register using MI_LRI (Lionel)

v8: Switch to software managed blackhole (BDW hangs on compute batches...)

v9: Simplify the noop state tracking (Lionel)

v10: Don't modify flush function (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
2020-02-13 17:05:05 +00:00
Lionel Landwerlin
74ec39f66d mesa: add INTEL_blackhole_render
v2: Implement missing Enable/Disable (Emil)

v3: Drop unused NewIntelBlackholeRender (Ken)

v4: Bring back NewIntelBlackholeRender as i965 implementation uses it
    again (Lionel)

v5: Drop atom (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
2020-02-13 17:05:05 +00:00
Thong Thai
08cff938b7 Revert "st/va: Convert interlaced NV12 to progressive"
This reverts commit 2add63060b.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2454
Fixes: 2add63060b "st/va: Convert interlaced NV12 to progressive"
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815>
2020-02-13 16:43:02 +00:00
Jason Ekstrand
3a2977e7b5 anv: Reject modifiers on depth/stencil formats
6790397346 added code which attempts to reject modifiers on
depth/stencil formats but it was placed after the early return for depth
and stencil aspects.  This commit moves it up so it actually works.

Of course, this doesn't actually matter because the only user of any of
the modifiers stuff is the WSI code and it will never do anything with
depth/stencil.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794>
2020-02-13 15:40:18 +00:00
Krzysztof Raszkowski
5a593bec16 gallium/swr: fix rdtsc debug statistics mechanism
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812>
2020-02-13 15:33:27 +01:00
Rhys Perry
dd16ad107d gitlab-ci: remove load_store_vectorizer from expected s390x test failures
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
2020-02-13 10:53:37 +00:00
Rhys Perry
aca2458d1b nir: fix nir_const_value_as_uint bit size in load/store vectorizer tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
2020-02-13 10:53:37 +00:00
Erik Faye-Lund
0c1ba69a27 Revert "nir: Add a couple trivial abs optimizations"
These were already added in 9fdaeb7776 ("nir: add min/max optimisation"),
and there's no point in doing them twice.

This reverts commit e4d346c86d.

Fixes: e4d346c86d ("nir: Add a couple trivial abs optimizations")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786>
2020-02-13 09:18:27 +00:00
Tapani Pälli
fdd20be324 iris: fix aux buf map failure in 32bits app on Android
Cc: mesa-stable@lists.freedesktop.org
Reported-by: Zhifang Long <zhifang.long@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
2020-02-13 10:54:53 +02:00
Samuel Pitoiset
b9e0947a9e radv: remove unused RADV_HASH_SHADER_IS_GEOM_COPY_SHADER
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
2020-02-13 08:09:13 +00:00
Samuel Pitoiset
b2531370c9 radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched
They are no longer useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
2020-02-13 08:09:13 +00:00
Samuel Pitoiset
fa48e7edc2 radv: remove LLVM sicheduler enable for The Talos Principle
sisched is completely unmaintained, it used to give few more FPS
in the past but with ACO, it's now obsolete. It seems even faster
without sisched now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
2020-02-13 08:09:13 +00:00
Tapani Pälli
f7d1bf075a glsl: fix a memory leak with resource_set
==7265== 248 (120 direct, 128 indirect) bytes in 1 blocks are definitely lost in loss record 1,438 of 1,465
   ==7265==    at 0x483980B: malloc (vg_replace_malloc.c:309)
   ==7265==    by 0x598A2AB: ralloc_size (ralloc.c:119)
   ==7265==    by 0x598F861: _mesa_set_create (set.c:127)
   ==7265==    by 0x599079D: _mesa_pointer_set_create (set.c:570)
   ==7265==    by 0x58BD7D1: build_program_resource_list(gl_context*, gl_shader_program*, bool) (linker.cpp:4026)
   ==7265==    by 0x548231B: st_link_shader (st_glsl_to_ir.cpp:170)
   ==7265==    by 0x54DA269: _mesa_glsl_link_shader (ir_to_mesa.cpp:3119)

Fixes: a6aedc66 ("st/glsl_to_nir: use nir based program resource list builder")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3574>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3574>
2020-02-13 07:47:33 +00:00
Samuel Pitoiset
556c940149 radv: implement VK_EXT_line_rasterization
Only Bresenham lines are supported. GFX9 is currently disabled
because there is some CTS failures for some weird reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>
2020-02-13 08:14:01 +01:00
Samuel Pitoiset
fbcf05382b radv: fix line width range and granularity
The hardware supports wide lines and the granularity is way larger.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>
2020-02-13 08:14:01 +01:00
Connor Abbott
da64c35ff9 tu: Force sysmem with mipmapped non-aligned linear stores
Fixes hangs with
dEQP-VK.api.image_clearing.core.clear_color_image.1d.linear.single_layer.r8g8b8a8_unorm
and many others on a640, and presumably silent corruption with a630.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:37:05 -05:00
Connor Abbott
f026982265 tu: Support input attachments with sysmem
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:37:05 -05:00
Connor Abbott
c1b3f9e832 tu: Support resolve ops with sysmem rendering
Similar to vkCmdClearAttachments(), we use CP_COND_REG_EXEC to
conditionally execute both the gmem and sysmem paths, except for after
the last subpass where it's known whether we're using sysmem rendering
or not.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:37:01 -05:00
Connor Abbott
8647a24a8d tu: Handle vkCmdClearAttachments() with sysmem
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:36:41 -05:00
Connor Abbott
07e07daeae tu: Add helper for CP_COND_REG_EXEC
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:36:41 -05:00
Connor Abbott
6a0c4008bf tu: Sysmem rendering
This has only lightly been tested. It passes dEQP-VK.api.smoke.triangle,
so at least we're able to show a triangle. For now, it's just enabled
under a debug flag. In the future we'll probably want some heuristics
like what freedreno has and another debug flag to disable it except when
it's forced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:36:36 -05:00
Connor Abbott
041783d49d tu: Disable linear depth attachments
Also, disable importing depth/stencil textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:31:57 -05:00
Connor Abbott
ab3db20cb5 tu: Support multisample image clears
We may need shader workarounds for some formats, but for now this seems
to work at least as well as the gmem path for clearing multisample
attachments. And soon we'll start calling this even on the gmem path,
since we leave the final decision of whether to use sysmem or not up
till the end, so we can't have it assert or otherwise working tests
would assert.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:31:57 -05:00
Connor Abbott
a5fb515301 tu/blit: Support blits in secondary cmdstreams
For sysmem rendering we'll have to emit a delayed clear IB to implement
LOAD_OP_*, similar to the existing tile_load_ib.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:31:44 -05:00
Connor Abbott
a94be3da84 tu: Properly set UBWC flags in RB_RENDER_CNTL
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:23:50 -05:00
Connor Abbott
49817cb3ea tu: Don't emit initial render target state in tile_load_ib
Emitting it directly in CmdBeginRenderPass should be around the same,
except that now we can easily share it with the sysmem path.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
2020-02-12 21:23:50 -05:00
Peng Huang
0660cbf426 radeonsi: make si_fence_server_signal flush pipe without work
glSignalSemaphoreEXT sometime doesn't signal the semaphore, it is
because radeonsi doesn't flush if gl context doesn't have pending
work. Fix the porblem by always submit ib.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3779>
2020-02-12 23:51:50 +00:00
Chad Versace
787b56ac0e turnip: Add a618 support
I merely ported a freedreno patch to turnip which
updates some magic regsiter values.

    commit ff6e148a3d
    Author:     Rob Clark <robdclark@chromium.org>
    CommitDate: Tue Oct 29 09:19:34 2019 -0700
    Subject:    freedreno/a6xx: add a618 support

That's all that Rob did for gallium for a618, so I assume that's we need
for turnip also.

Tested manually with:

    dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.*
        pass 300/555
        fail   0/555
        skip 255/555

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3743>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3743>
2020-02-12 23:27:43 +00:00
Chad Versace
ef5da26089 turnip: Add magic register values to tu_physical_device
The value of some magic regsiters differ across chipsets. fd6_context
manages the differences by initializing them at runtime. Let's do the
same.

Add to tu_physical_device a subset of those found in fd6_context:

    RB_UNKNOWN_8E04_blit
    RB_CCU_CNTL_gmem
    PC_UNKNOWN_9805
    SP_UNKNOWN_A0F8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3743>
2020-02-12 23:27:43 +00:00
Jonathan Marek
18786cc7d5 freedreno/a6xx: use single format enum
Loses some information about which formats can be used in which cases, but
we encode that information in the format table anyway.

Important notes:
* RB6_R10G10B10A2_UNORM becomes FMT6_R10G10B10A2_UNORM_DEST
* TFMT6_8_8_8_UNORM becomes FMT6_8_8_8_X8_UNORM (not FMT6_8_8_8_UNORM)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3798>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3798>
2020-02-12 21:59:59 +00:00
Chad Versace
c13202af7a anv: Respect ISL_SURF_USAGE_DISABLE_AUX_BIT in make_surface()
If set, then don't make the aux surface.

Only anv_android.c used the flag, but anv_image.c fully ignored it.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3797>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3797>
2020-02-12 21:34:02 +00:00
Chad Versace
a76fd8b08c anv: Clarify behavior of anv_image_aspect_to_plane()
It returns the aspect's _format_ plane, not its _memory_ plane (using the
vocabulary of VK_EXT_image_drm_format_modifier).

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3796>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3796>
2020-02-12 21:01:45 +00:00
Chad Versace
da2b0c6c19 anv: Delete anv_image::ccs_e_compatible
It was set exactly once, and read exactly once, both times during
anv_image_create().

I found its permanency as a member of anv_image to be distracting while
implementing VK_EXT_image_drm_format_modifier.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3795>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3795>
2020-02-12 20:31:39 +00:00
Rhys Perry
483d4ec57c aco: improve SCC handling in some SALU combines
Add some checks and remove some unnecessary checks.

Found by observation. No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599>
2020-02-12 19:18:45 +00:00
Rhys Perry
d45e9451cf aco: disable some instruction combining if it could change an exec operand
Found by observation. No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3599>
2020-02-12 19:18:40 +00:00
Arcady Goldmints-Orlov
e9f83185a2 Rename nir_lower_constant_initializers to nir_lower_variable_initalizers
This is naming is more clear as nir_variables can be initializes not
just with a nir_constant but with a pointer to another nir_variable.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047>
2020-02-12 15:41:49 +00:00
Arcady Goldmints-Orlov
e459c7f0a1 compiler/spirv: Add support for non-constant initializers
This adds support for OpVariable having an initializer that points to
another variable, rather than a constant. In this case, the variable is
initialized to a pointer to the other variable.

Fixes Vulkan CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.variable_init.private.*

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047>
2020-02-12 15:41:49 +00:00
Arcady Goldmints-Orlov
7acc81056f compiler/nir: Add support for variable initialization from a pointer
Add a pointer_initializer field to nir_variable analogous to
constant_initializer, which can be used to initialize the nir_variable
to a pointer to another nir_variable. Just like the
constant_initializer, the pointer_initializer gets eliminated in the
nir_lower_constant_initializers pass.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047>
2020-02-12 15:41:49 +00:00
Veerabadhran
461c40e0fd radeon/vce: Move global function pointer si_get_pic_param to local encoder structure
Multi gpu use case broken when the function was global

Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3731>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3731>
2020-02-12 13:43:35 +00:00
Chad Versace
286141197d anv: Rename param make_surface::dev to device
Everywhere in anvil, each variable of type anv_device is named 'device',
except this single instance. Rename it for consistency.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3773>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3773>
2020-02-11 13:26:38 -06:00
Chad Versace
84b791a4bb anv: Drop unused anv_image_get_surface_for_aspect_mask()
Replaced by anv_image.c:get_surface() in:

  commit a62a979335
  Author:     Lionel Landwerlin <lionel.g.landwerlin@intel.com>
  CommitDate: Fri Oct 6 16:32:20 2017 +0100
  Subject:    anv: enable multiple planes per image/imageView

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3773>
2020-02-11 13:26:06 -06:00
Michel Dänzer
2303762735 gitlab-ci: Only use gstreamer runners for the s390x job for now
The fdo-packet-* runners keep hitting the (already quite long) timeouts
for some of the tests, taking many times as long for them as the
gstreamer runners.

The fdo-gitlab-gce-runner3 runner would work as well, but it doesn't
have any tags we could use.

Acked-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3760>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3760>
2020-02-11 09:59:08 +01:00
Samuel Pitoiset
8e77280774 nir: do not use De Morgan's Law rules for flt and fge
In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL
to "fge(a, b) || fge(c, d)". These optimizations are unsafe for
apps that rely on NaN behaviour.

pipeline-db (GFX9/LLVM):
Totals from affected shaders:
SGPRS: 3176 -> 3136 (-1.26 %)
VGPRS: 2188 -> 2144 (-2.01 %)
Spilled SGPRs: 227 -> 169 (-25.55 %)
Code Size: 150572 -> 151800 (0.82 %) bytes
Max Waves: 307 -> 310 (0.98 %)

pipeline-db (GFX9/ACO):
Totals from affected shaders:
SGPRS: 18744 -> 18744 (0.00 %)
VGPRS: 15576 -> 15580 (0.03 %)
Spilled SGPRs: 164 -> 164 (0.00 %)
Code Size: 1573012 -> 1576492 (0.22 %) bytes
Max Waves: 1534 -> 1532 (-0.13 %)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2127
Fixes: d1ed4ffe0b ("nir: Use De Morgan's Law on logic compounded comparisons")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
2020-02-11 08:36:00 +01:00
Samuel Pitoiset
ddd767387f aco: fix creating v_madak if v_mad_f32 has two sgpr literals
Do not ignore that src1 can be a sgpr.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2435
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3759>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3759>
2020-02-11 07:17:31 +00:00
Samuel Pitoiset
cd08d9abd7 radv: set the chip name to GCN-NOOP when RADV_FORCE_FAMILY is set
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654>
2020-02-11 07:56:59 +01:00
Samuel Pitoiset
a8024aaaab radv: make sure to not submit any IBs when RADV_FORCE_FAMILY is set
To prevent GPU hangs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3654>
2020-02-11 07:56:55 +01:00
Bas Nieuwenhuizen
5b335e1599 radv: Do not redundantly set the RB+ regs on pipeline switch.
No significant perf changes seen on Bayonetta. (Changes are in the
noise on my Raven Laptop)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3735>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3735>
2020-02-11 04:39:42 +00:00
Vinson Lee
63345a3596 panfrost: Remove unused anonymous enum variables.
This patch fix these build errors with GCC 10.

/usr/bin/ld: src/gallium/drivers/panfrost/libpanfrost.a(pan_resource.c.o):src/panfrost/midgard/midgard_compile.h:52: multiple definition of `pan_sysval'; src/gallium/drivers/panfrost/libpanfrost.a(pan_screen.c.o):src/panfrost/midgard/midgard_compile.h:52: first defined here
/usr/bin/ld: src/gallium/drivers/panfrost/libpanfrost.a(pan_resource.c.o):src/panfrost/midgard/midgard_compile.h:68: multiple definition of `pan_special_attributes'; src/gallium/drivers/panfrost/libpanfrost.a(pan_screen.c.o):src/panfrost/midgard/midgard_compile.h:68: first defined here

Fixes: 7e8de5a707 ("panfrost: Implement system values")
Fixes: 306800d747 ("pan/midgard: Lower gl_VertexID/gl_InstanceID to attributes")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3752>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3752>
2020-02-11 03:26:04 +00:00
Bas Nieuwenhuizen
7792d774e0 radv: Optimize emitting index buffer changes.
Since the direct indexed draw packet has the address/count info
inline, there is no sense in emitting the base and size.

No real significant changes found during benchmarks.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466>
2020-02-11 03:07:11 +00:00
Ian Romanick
1d97d186fb nir: Mark fmin and fmax as commutative and associative
Per the resolution of Khronos GLSL issue 80
(https://github.com/KhronosGroup/GLSL/issues/80).  Spec updates have not
landed yet, but I'll get to it soon. :)

The extra hurt shaders on Gen8+ are a handful of shaders that see things like

    bcsel(fmin(b - a, a - c) >= 0, x, y)

converted to

   bcsel(a >= b && c >= a, x, y)

The former can be generated as a CSEL instruction.  If either b - a or a
- c is used elsewhere in the shader, this saves an instruction.

All Haswell+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14550188 -> 14550048 (<.01%)
instructions in affected programs: 12168 -> 12028 (-1.15%)
helped: 30
HURT: 3
helped stats (abs) min: 1 max: 17 x̄: 4.77 x̃: 2
helped stats (rel) min: 0.05% max: 3.85% x̄: 1.77% x̃: 1.80%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.50% max: 0.50% x̄: 0.50% x̃: 0.50%
95% mean confidence interval for instructions value: -6.15 -2.33
95% mean confidence interval for instructions %-change: -2.00% -1.12%
Instructions are helped.

total cycles in shared programs: 203770286 -> 203771464 (<.01%)
cycles in affected programs: 688466 -> 689644 (0.17%)
helped: 172
HURT: 220
helped stats (abs) min: 1 max: 286 x̄: 12.15 x̃: 6
helped stats (rel) min: 0.03% max: 5.97% x̄: 0.70% x̃: 0.35%
HURT stats (abs)   min: 1 max: 578 x̄: 14.85 x̃: 6
HURT stats (rel)   min: 0.03% max: 32.36% x̄: 1.21% x̃: 0.52%
95% mean confidence interval for cycles value: -0.74 6.75
95% mean confidence interval for cycles %-change: 0.15% 0.59%
Inconclusive result (value mean confidence interval includes 0).

total fills in shared programs: 4525 -> 4523 (-0.04%)
fills in affected programs: 48 -> 46 (-4.17%)
helped: 1
HURT: 0

Ivy Bridge
total instructions in shared programs: 11858995 -> 11858898 (<.01%)
instructions in affected programs: 10822 -> 10725 (-0.90%)
helped: 25
HURT: 13
helped stats (abs) min: 1 max: 17 x̄: 5.32 x̃: 2
helped stats (rel) min: 0.40% max: 5.00% x̄: 2.16% x̃: 1.85%
HURT stats (abs)   min: 1 max: 15 x̄: 2.77 x̃: 2
HURT stats (rel)   min: 0.47% max: 2.90% x̄: 1.83% x̃: 2.15%
95% mean confidence interval for instructions value: -4.66 -0.45
95% mean confidence interval for instructions %-change: -1.54% -0.05%
Instructions are helped.

total cycles in shared programs: 177947023 -> 177946880 (<.01%)
cycles in affected programs: 822075 -> 821932 (-0.02%)
helped: 157
HURT: 175
helped stats (abs) min: 1 max: 164 x̄: 13.17 x̃: 4
helped stats (rel) min: 0.03% max: 6.72% x̄: 0.64% x̃: 0.17%
HURT stats (abs)   min: 1 max: 308 x̄: 11.00 x̃: 4
HURT stats (rel)   min: 0.03% max: 9.76% x̄: 0.70% x̃: 0.18%
95% mean confidence interval for cycles value: -3.86 3.00
95% mean confidence interval for cycles %-change: -0.09% 0.22%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 4185 -> 4188 (0.07%)
spills in affected programs: 146 -> 149 (2.05%)
helped: 0
HURT: 1

total fills in shared programs: 5248 -> 5249 (0.02%)
fills in affected programs: 347 -> 348 (0.29%)
helped: 0
HURT: 1

Sandy Bridge
total instructions in shared programs: 10680224 -> 10680144 (<.01%)
instructions in affected programs: 4702 -> 4622 (-1.70%)
helped: 15
HURT: 3
helped stats (abs) min: 1 max: 17 x̄: 5.53 x̃: 5
helped stats (rel) min: 0.39% max: 4.76% x̄: 2.17% x̃: 1.67%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.52% max: 0.52% x̄: 0.52% x̃: 0.52%
95% mean confidence interval for instructions value: -7.24 -1.65
95% mean confidence interval for instructions %-change: -2.55% -0.89%
Instructions are helped.

total cycles in shared programs: 152988780 -> 152985691 (<.01%)
cycles in affected programs: 1072850 -> 1069761 (-0.29%)
helped: 168
HURT: 145
helped stats (abs) min: 1 max: 592 x̄: 33.90 x̃: 12
helped stats (rel) min: 0.02% max: 10.73% x̄: 0.90% x̃: 0.31%
HURT stats (abs)   min: 1 max: 259 x̄: 17.98 x̃: 6
HURT stats (rel)   min: 0.02% max: 8.17% x̄: 0.77% x̃: 0.19%
95% mean confidence interval for cycles value: -17.95 -1.79
95% mean confidence interval for cycles %-change: -0.34% 0.08%
Inconclusive result (%-change mean confidence interval includes 0).

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8107033 -> 8107025 (<.01%)
instructions in affected programs: 696 -> 688 (-1.15%)
helped: 5
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.60 x̃: 2
helped stats (rel) min: 0.34% max: 7.14% x̄: 3.47% x̃: 4.65%
95% mean confidence interval for instructions value: -2.28 -0.92
95% mean confidence interval for instructions %-change: -7.22% 0.28%
Inconclusive result (%-change mean confidence interval includes 0).

total cycles in shared programs: 188348526 -> 188348404 (<.01%)
cycles in affected programs: 33618 -> 33496 (-0.36%)
helped: 23
HURT: 0
helped stats (abs) min: 2 max: 12 x̄: 5.30 x̃: 6
helped stats (rel) min: 0.05% max: 1.83% x̄: 0.47% x̃: 0.51%
95% mean confidence interval for cycles value: -6.70 -3.91
95% mean confidence interval for cycles %-change: -0.64% -0.30%
Cycles are helped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1359>
2020-02-10 18:37:36 -08:00
Eric Anholt
1886dbfe73 Revert "gallium: Fix big-endian addressing of non-bitmask array formats."
This reverts the functional part of commit
d17ff2f7f1, leaving the unit test for
mesa/pipe agreement on what's an array.

The issue is that the util_channel_desc.shift values on array formats are
not used for bit addressing in memory, they're bit addressing within a
word treating a pixel of the format as a native type, as seen by
llvmpipe's use of the values to do shifts (see
lp_build_unpack_arith_rgba_aos() for example).  This means the values are
nonsensical for 3-byte RGB, but then llvmpipe doesn't expose those formats
so it works out.

I still want to clean up our big-endian format handling at some point, but
let's fix the s390x regression first, sort out our format unit tests in
CI, then be able to refactor with confidence.

Fixes: d17ff2f7f1 ("gallium: Fix big-endian addressing of non-bitmask array formats.")
Closes: #2472
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
2020-02-11 00:53:04 +00:00
Marek Olšák
11db8e0e00 st/mesa: optimize st_update_array with ALWAYSINLINE
The time spent in st_update_array is reduced by 5-10%.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
36cc6b105b mesa: don't use bitfields in _mesa_prim
This is better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
47d7e21619 mesa: remove unused _mesa_prim::is_indirect
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
734654a89c í965: don't use _mesa_prim::is_indirect
the vbo change only affects i965

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
a7d03103f3 vbo: merge use_buffer_objects into vbo_CreateContext to skip the big malloc
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
7575a0a251 vbo: clean up resetting vertex attribs
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
ee5bd8638b vbo: also map the immediate mode buffer for read
because we read from it sometimes and we want cached reads.

We can only do it with the persistent mapping, because the non-persistent
mapping uses incompatible flags.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
27bd241103 vbo: delay flagging FLUSH_STORED_VERTICES until glEnd
Only state changes see this, which can't occur before glEnd.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
ca99fe8a60 vbo: add/update unlikely statements in ATTR_UNION
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
a5f72c91e5 vbo: increase the size of the immediate mode buffer to decrease draw count
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
2fe771f4e9 vbo: use FlushVertices flags properly and clear NeedFlush correctly
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
63a241fa32 vbo: fix resizing 64-bit vertex attributes
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
077a843c27 vbo: optimize resizing vertex attributes during immediate mode
Just move data manually instead of copying all attributes back and forth.

This increases performance by 5% for Viewperf11/Catia - first scene.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
1f6e53e243 vbo: don't store glVertex values temporarily into exec
This improves performance by 4.3% in Viewperf11/Catia, first scene.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
cd7241c4f8 vbo: pass only either uint32_t or uint64_t into ATTR_UNION
This makes the next commit possible.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
afa7f1984a vbo: don't set FLUSH_UPDATE_CURRENT for glVertex
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
f8b98d48bf vbo: keep the immediate mode buffer always mapped for simplicity
It only unmaps when it draws with a non-persistent buffer.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
8c76ef5b59 vbo: don't check ctx->NewState twice in glBegin
_mesa_valid_to_render does it too.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
f2c6de1eec vbo: remove a funky recursive call in glBegin
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
653bd14730 vbo: interleave attrsz, attrtype, and active_sz in memory
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
2b22e33c10 vbo: remove immediate mode code that doesn't do anything and simplify stuff
no change in behavior

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
3e0d612f5e vbo: don't unmap persistent buffer mappings for glBegin/End
This significantly improves performance by lowering CPU overhead.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
03ded3d6ce vbo: skip FlushMappedBufferRange for glBegin/End by using a persistent mapping
This is a preparation for the next commit and just isolates the removal
of GL_MAP_FLUSH_EXPLICIT_BIT and other map flags that don't make sense with
UNSYNCHRONIZED.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
10cf7a5113 vbo: create the immediate mode buffer only in vbo_exec_vtx_map
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
f89ee44ab0 mesa: import PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET handling
This should decrease overhead in st_update_array.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
27dada7ce9 mesa: remove FLUSH_CURRENT calls that have no effect
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
c7c8fe1cc1 mesa: fix incorrect uses of FLUSH_CURRENT
FLUSH_CURRENT is used to copy attributes from the vbo module to
Current.Attrib. It flushes vertices too, but that's a side effect,
not the intent.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3766>
2020-02-11 00:34:57 +00:00
Marek Olšák
01443dc738 glx: print FPS with 2 decimal places
useful if FPS is low.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3590>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3590>
2020-02-10 19:02:33 -05:00
Marek Olšák
1082e6fcb8 radeonsi: don't update states for the DCC MSAA bug on GFX6-7
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
2020-02-10 17:24:09 -05:00
Marek Olšák
fbb27eebc8 radeonsi: fix the DCC MSAA bug workaround
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
2020-02-10 17:24:02 -05:00
Gert Wollny
897a4a0041 r600/sfn: Add some documentation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
7413aab3c8 r600/sfn: Add .editorconfig file
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
110ee7ff93 r600/sfn: Add support for SSBO load and store
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
148f0ad4f9 r600/sfn: Add support for atomic instructions
v2: fix compilation with gcc-6

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
90a7d2e08f r600: Make sure LLVM is not used for DRAW
For some reasone that is not yet clear the piglit
gl-1.0-rendermode-feedback makes use of the LLVM pipe draw module and
fails there with an assertion. Explicietly disabling LLVM fixes this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
37125b7cc2 r600/sfn: Add lowering UBO access to r600 specific codes
r600 reads vec4 from the UBO, but the offsets in nir are evaluated to the component.
If the offsets are not literal then all non-vec4 reads must resolve the component
after reading a vec4 component (TODO: figure out whether there is a consistent way
to deduct the component that is actually read).

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
32d3435a78 r600/sfn: Add GDS instructions
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
5aadd809d0 r600/sfn: Add compute shader skeleton
This adds some very basic compute shader support.

v2: fix compilation with gcc-6

v3: rebase: correct barrier intrinstic

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
7fb5c835f7 r600/sfn: Add VS for TCS shader skeleton
This adds the VS shader type that handles the output to tesselation shaders

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
e17ac0d774 r600/sfn: Add support for geometry shader
v2: fix compilation with gcc-6

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
5c7124e134 r600/sfn: add emitVertex instructions
More preparation for GS support

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
f7ec616bed r600/sfn: Add MemRingOut instructions
Preparing support for Geometry shaders.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
1b17316bf3 r600/sfn: Add a load GDS result instruction
This is required to read results for atomic SSBO  instructions

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
31a4dd6451 r600/sfn: Add lowering arrays to scratch and according instructions
Make use of the scratch space for arrays that are larger then 100 elements.
Since for IO r600 is vector based, there is a bit of a scratch space waste
here for arrays that use types smaller then vec4.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
5c19013904 r600/sfn: add register remapping
Make use of the live range evaluation to merge registers. Since the
live ranges are evaluated for register indices, the algorithm is not
optimal, but for most piglits up to glsl-3.3 it does the job.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
393655d5cb r600/sfn: add live range evaluation for the GPR
The algoritm is basically a copy of the TGSI implementation without the
array bits.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
24f683fe81 r600/sfn: Add the WaitAck instruction
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
e09cdb3f86 r600/sfn: Add the VS in and FS out vectorization
Since the nir default implementation doesn't support vectorizing the VS
inputs and FS outputs, additional lowering passes are added here to do
just that. The work is based on the Timothy Arceri's related work.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
c5d9456d84 r600: enable NIR backend DEBUG flag for supported architectures
When NIR is enabled, a few features that are not yet supported will be
explicitely disabled.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
f718ac6268 r600/sfn: Add a basic nir shader backend
This commit adds support for vertex and fragment shaders from NIR, and
support for most TEX and ALU instructions.

Thanks Dave Airlied for adding support for a number of ALU instructions.

v2: fix compilation with gcc-6
v3: rebase: use mesa/core glsl_type_size function

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
295be0e8df r600: Update state code to accept NIR shaders
v2: Correct commit message (Konstantin Kharlamov)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
51285bf32e r600: Add NIR compiler options
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
27cacd28ac r600: Increase space for IO values to agree with PIPE_MAX_SHADER_IN/OUTPUTS
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:08 +00:00
Gert Wollny
4422ce1b04 r600: force new CF with TEX only if any texture value is written
This works aound splitting the CF when the gradient is set.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3225>
2020-02-10 19:09:07 +00:00
Neha Bhende
144561dc5e svga: Use pipe_shader_state_from_tgsi to set shader state
Use pipe_shader_state_from_tgsi() to set shader state for transformed
shader so that we get all correct data for respective shader state.

This fixes several regressed glretrace, piglit crashes found during merging
upsteam mesa

Fixes: bf12bc2dd7 (draw: add nir info gathering and building support)

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2020-02-10 09:27:11 -08:00
Neha Bhende
470e73e7f8 svga: fix size of format_conversion_table[]
Since we are now using sparse matrix for format_conversion_table,
we have to make sure we have last entry in table which gives the
sense of required size of format_conversion_table

Fixes: 84db6ba7 ("svga: Drop unsupported formats from the format table")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2020-02-10 09:26:49 -08:00
Krzysztof Raszkowski
689817c9df gallium/swr: simplify environmental variabled expansion code
There were 2 versions of code doing the same thing.
Since std::regexp are locale-sensitive better is to leave old
good way to do this.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3761>
2020-02-10 17:10:47 +01:00
Samuel Pitoiset
34fd894e42 aco: fix waiting for scalar stores before "writing back" data on GFX8-GFX9
Seems required also on GFX8-GFX9 to achieve correct behaviour. This
is an undocumented behaviour but it makes real sense to me.

pipeline-db on GFX9:
Totals from affected shaders:
SGPRS: 1018 -> 1018 (0.00 %)
VGPRS: 516 -> 516 (0.00 %)
Code Size: 40516 -> 40636 (0.30 %) bytes
Max Waves: 280 -> 280 (0.00 %)

This fixes some sort of sun flickering with Assassins Creed Origins.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2488
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3750>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3750>
2020-02-10 12:07:25 +00:00
Georg Lehmann
7283c33b98 Vulkan overlay: use the corresponding image index for each swapchain
pImageIndices should be a pointer to the current image index
otherwise every swapchain but the first one could have a wrong image index

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
2020-02-10 11:32:08 +00:00
Erik Faye-Lund
eb0195358c zink: only inspect dual-src limit if feature enabled
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3689>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3689>
2020-02-10 11:01:47 +00:00
Erik Faye-Lund
e365f83740 zink: emit blend-target index
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3689>
2020-02-10 11:01:47 +00:00
Erik Faye-Lund
8736ffae2e zink: replace unset buffer with a dummy-buffer
This fixes a crash in spec@!opengl 1.1@ppgtt_memory_alignment

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3673>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3673>
2020-02-10 10:40:19 +00:00
Samuel Pitoiset
18657c0c0a gitlab-ci: disable a630 tests as mesa-cheza is down (again)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3758>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3758>
2020-02-10 10:34:41 +01:00
Marek Olšák
35961b10da radeonsi: don't report that multi-plane formats are supported
Fixes: a554b45d - st/mesa: don't lower YUV when driver supports it natively
Closes: #2376

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3632>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3632>
2020-02-07 20:42:42 -05:00
Erik Faye-Lund
1c3f4c0704 zink: fixup sampler-usage
It seems I got this stuff all wrong, and looked at driver_location
rather than the binding. But since we mess with the binding, we need to
adjust things a bit to get things right.

This still isn't great as-is, but it seems to work. In the future, we
should move to having samplers always at bindings 0 and up, and just
update the bindings that are used by either of the stages. But this
band-aid should be OK for now.

This fixes 0AD for me.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3668>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3668>
2020-02-07 22:03:00 +00:00
Erik Faye-Lund
fa915a724f zink: lower away fdph
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3668>
2020-02-07 22:03:00 +00:00
Christian Gmeiner
0c36b1c0db etnaviv: enable texture upload memory throttling
Fixes oom-killer during piglit's streaming-texture-upload on a
SolidRun CuBox-i with 2GB of RAM.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3745>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3745>
2020-02-07 18:21:54 +00:00
Hyunjun Ko
7bddaa6136 freedreno/ir3: Fold const only when the type is float
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:53:48 -08:00
Hyunjun Ko
260bd32b58 freedreno/ir3: put the conversion back for half const to the right place.
The previous commit leads to match immed values unexpectedly.

This makes constlen for each shader including bvert wrong.
Also fixes atan2 for mediump deqp tests.

Fixes: cbd1f47433 ("freedreno/ir3: convert back to 32-bit values for half constant registers.")

v2: Move conversion up above fabs/fneg modifier handling as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:53:42 -08:00
Hyunjun Ko
d70192e697 freedreno/ir3: Add cat4 mediump opcodes
v2: Reworked to assign half-opcodes in ir3_ra.c (krh).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:51:25 -08:00
Rob Clark
3eca6d9ce1 freedreno/ir3: fold const conversion into consumer
A sequence like:

  (nop3)cov.f32f16 hr0.x, c0.x
  mul.f hr4.y, hr1.z, hr0.x

can be turned into:

  mul.f hr4.y, hr1.z, hc0.x

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:51:25 -08:00
Hyunjun Ko
5e2012d5c7 freedreno/ir3: fix printing half constant registers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:51:25 -08:00
Kristian H. Kristensen
d55dfef782 freedreno/ir3: Set IR3_REG_HALF flag on src as well in immediate MOV
This lets is_same_type_reg() recognize that the dst and src of the
immediate MOV are the same and unblocks fp16 constant propagation.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
2020-02-07 09:51:25 -08:00
Dylan Baker
fbfc8c3531 docs: Mark 20.0-rc2 as done
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3751>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3751>
2020-02-07 09:02:02 -08:00
Martin Fuzzey
d8bae10bfe freedreno: android: fix build of perfcounters.
Some dependencies were missing on android causing a build failure.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3736>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3736>
2020-02-07 16:34:49 +00:00
Martin Fuzzey
fad9924315 freedreno: android: add a6xx-pack.xml.h generation to android build
The generation of a6xx-pack.xml.h was missing in the android build scripts
leading to a build failure.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3736>
2020-02-07 16:34:49 +00:00
Martin Fuzzey
cad400a59e freedreno: android: fix build failure on android due to python version
The freedreno gen_header.py script now only works under python3.
It contains a "print()" call which prints a blank line under python3
but prints "()" under python2.7.

However the Android build currently uses python2.

This leads to incorrect code generation and a later build error.

.../STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/adreno_common.xml.h:163:2: error: expected identifier or '('
()

Fix this by adding MESA_PYTHON3 and using it for the freedreno scripts.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3736>
2020-02-07 16:34:49 +00:00
Krzysztof Raszkowski
ff8265b64f gallium/swr: Fix llvm11 compilation issues
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3747>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3747>
2020-02-07 15:03:55 +00:00
Georg Lehmann
f239bb8020 Vulkan Overlay: Don't try to change the image layout to present twice
The render pass already does the transition.
The pipeline barrier is still needed to transfer the queue family ownership.

Fixes: 320b0f66c2 ("vulkan/overlay: bounce image back to present layout")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
2020-02-07 14:23:23 +00:00
Samuel Pitoiset
4b978cd950 aco: do not use ds_{read,write}2 on GFX6
According to LLVM, these instructions have a bounds checking bug.
LLVM only uses them on GFX7+.

This fixes broken geometry in Assassins Creed Origins.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2489
Fixes: 4a553212fa ("radv: enable ACO support for GFX6")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3746>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3746>
2020-02-07 14:17:06 +01:00
Tapani Pälli
da76dfb515 intel/vec4: fix valgrind errors with vf_values array
Fixes valgrind errors introduced since commit a8ec4082.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2346
Fixes: a8ec4082 ("nir+vtn: vec8+vec16 support")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3691>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3691>
2020-02-07 09:06:18 +00:00
Andreas Baierl
1572e8f3e1 lima/parser: Change value name in RSW parser
Second value of SHADER_ADDRESS is the length of the first instruction
in the shader, so give it a better name.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3619>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3619>
2020-02-07 09:26:32 +01:00
Andreas Baierl
5802259e54 lima/parser: Extend AUX0 findings
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3619>
2020-02-07 09:26:32 +01:00
Andreas Baierl
cebfb3169c lima/parser: Fix RSW depth test parsing
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3619>
2020-02-07 09:26:32 +01:00
Leandro Ribeiro
eaa0784fd3 i965: remove duplicated comment
Signed-off-by: Leandro Ribeiro <leandrohr@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2416>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2416>
2020-02-07 07:14:20 +02:00
Kristian H. Kristensen
26ab38f144 ci: Drop turnip opt-in option
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3742>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3742>
2020-02-07 01:36:58 +00:00
Dave Airlie
fbc117cba3 llvmpipe: advertise 4 vertex streams
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
7e6690b1a6 draw: don't emit vertex to streams with no outputs
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
72154c9075 draw: emit multiple streams to streamout.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
00c066e5a0 draw/gs: track emitted prims + verts per stream.
This adds tracking of the emitted prims/verts per-stream.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
0c77007c9d draw: change geom shader output to an array of outputs.
Instead of a single output ptr, pass in one per output stream.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
8583fcd8f1 gallivm/nir: add support for multiple vertex streams
This adds support to the nir shader build for multiple vertex streams
we store separate stats for each stream, then write them out in the epilogue.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
b668841313 gallivm/swr: add stream_id to geom epilogue emit
We want to pass a stream in here so we can write out separate
prim/vertex counts for each stream at the end.

This also adds an ignore any stream option so we can stage more code

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Dave Airlie
9d70002744 llvmpipe/query: add support for indexed queries
This adds support for the queries needed for gpu_shader5 vertex streams

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3530>
2020-02-07 00:54:42 +00:00
Eric Anholt
658eb691fc ci: Bump the GLES CTS version to 3.2.6.1.
This brings in the surfaceless fixes so we don't need to check out the
whole repo to cherry pick any more (which was bothering me as I debugged
things late in the painfully slow ARM container build process).

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3662>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3662>
2020-02-06 15:18:24 -08:00
Eric Anholt
b37922dd1e ci: Disable a bunch of tests on freedreno a630.
On a daily basis I've been having to restart people's a630 jobs in the
front couple of pages of /merge_requests due to spurious failures from our
flaky tests, and fielding reports of spurious fails from other developers,
and babysitting my own marge merges that are failing due to our flakes.

Nobody should have to deal with that, especially not non-freedreno
developers, so just scrape the list of flakes reported to #freedreno-ci
for the last month and ban those tests that have failed more than once
until we have a credible fix.

Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3662>
2020-02-06 15:18:15 -08:00
Kristian H. Kristensen
b3063cbd18 turnip: Drop explicit configure opt-in for turnip
We don't need this silly thing anymore. Everthing here is WIP.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3739>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3739>
2020-02-06 13:23:40 -08:00
Eric Anholt
4ca77f347d u_tile: Skip the packed temporary and just store tiles directly.
We were generating a packed copy and then memcpying it, but we can just
pack directly to the destination.  Change on glmark2 -b build:use-vbo=true
is modest: 1.06328% +/- 0.994771% (n=84) but does remove the function that
was .6% of CPU time.

I'm not doing the equivalent "get" path at this time because softpipe's
texture cache has some clipping issues that get revealed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3698>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3698>
2020-02-06 20:48:03 +00:00
Jose Maria Casanova Crespo
68bb26af63 broadcom: Fix implicit declaration of ffs for Android build
Include util/bitscan.h to ensure ffs is available when there is no
glibc like in Android.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1983
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2554>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2554>
2020-02-06 18:31:13 +01:00
Rhys Perry
ce23911b77 aco: gfx10_wave64_bpermute reduce op to print_ir
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683>
2020-02-06 16:43:03 +00:00
Rhys Perry
20eb1acb6f aco: fix gfx10_wave64_bpermute
Since 9254fb4fc7, the pass replaced the SCC clobber with the scalar
identity temporary. Just skip most of the temporary setup, since we don't
need it for gfx10_wave64_bpermute.

Although shuffles are disabled on GFX10, Detroit: Become Human seems to
use them anyway.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 9254fb4fc7 ('aco: don't use a scalar
       temporary for reductions on GFX10')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3683>
2020-02-06 16:43:03 +00:00
Georg Lehmann
1c79afd946 Correctly wait in the fragment stage until all semaphores are signaled
This fixes two issues:
- a crash if the application uses more than one semaphore for presenting because the driver expects one stage per semaphore
- the swapchain image could be not ready yet if the semaphores aren't signaled, #946 is possible related

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
2020-02-06 15:16:47 +00:00
Thomas Hellstrom
451cf228d5 svga: Fix banded DMA upload
A previous commit ("winsys/svga: Limit the maximum DMA hardware buffer
size") made banded DMA transfer kick in when transfering gnome-shell
window contents under gnome-shell / wayland. This uncovered a bug where
we assumed that banded DMA transfers always occur to the top (y=0) of the
surface.
Fix this by taking the destination y offset into account.

Cc: 19.2 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Fixes: 287c94ea49 ("Squashed commit of the following:")
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
2020-02-06 11:26:04 +00:00
Jason Ekstrand
5aec9e84a8 anv: No-op submit and wait calls when no_hw is set
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3734>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3734>
2020-02-06 10:48:33 +00:00
Lionel Landwerlin
f9febfae41 anv: set MOCS on push constants
v2: Also set MOCS on 3DSTATE_CONSTANT_ALL (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 67d2cb3e93 ("anv: Add get_push_range_address() helper.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3732>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3732>
2020-02-06 10:10:11 +00:00
Michel Dänzer
a140ea1ced llvmpipe: Bump test timeout to 180 seconds
120 still wasn't always enough for the s390x cross-build job, see e.g.
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/1551685

Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3715>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3715>
2020-02-06 09:41:28 +00:00
Rafael Antognolli
4aa7af9e9a intel: Load the driver even if I915_PARAM_REVISION is not found.
This param is only available starting on kernel 4.1. Use a default
value of 0 if it is not found instead.

v2: Update commit message (Lionel)

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Fixes: 96e1c945f2 ("i965: Move device info initialization to common
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
2020-02-06 09:46:51 +02:00
Kenneth Graunke
20bcbcd958 isl: Fix the android build.
Fixes: 5bea0cf779 ("intel/isl: Move iris's pipe-to-isl format function to isl.")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
2020-02-05 21:31:40 -08:00
Kenneth Graunke
a92be2fb26 intel/genxml: Drop "reserved" enum
This was adding "#define reserved 2" to genxml includes, which is a
fairly mean lowercase word to redefine.  It ends up breaking the build
on Android, which has __u32 reserved fields in headers.

Defining it also has no purpose.  Just drop it.

Fixes: 5bea0cf779 ("intel/isl: Move iris's pipe-to-isl format function to isl.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
2020-02-05 21:31:27 -08:00
Vinson Lee
deb2bbf57e swr: Fix GCC 4.9 checks.
Fixes: f0a22956be ("swr/rast: _mm*_undefined_* implementations for gcc<4.9")
Fixes: e21fc2c625 ("swr/rast: non-regex knob fallback code for gcc < 4.9")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2020-02-05 19:39:13 -08:00
James Xiong
205ce0bea5 gallium: let the pipe drivers decide the supported modifiers
fixes: ac0219cc5b ("gallium: dmabuf support for yuv formats that are not natively supported")

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3527>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3527>
2020-02-06 00:43:58 +00:00
James Xiong
d8569baaed iris: handle the failure of converting unsupported yuv formats to isl
Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3527>
2020-02-06 00:43:58 +00:00
Eric Engestrom
76f300f2e4 Revert "egl: put full path to libEGL_mesa.so in GLVND json"
This reverts commit 0021f7dc30.

That commit had 2 issues:
- I missed the `.0` from the filename, causing issues on Debian & Ubuntu
  platforms.
- I didn't think about multilib/multi-arch systems, where we'd now need
  a separate json for each arch as they point to different libs.

Reverting this commit for now, I'll try again later.

Requested-by: Michel Dänzer <michel@daenzer.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2466
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2471
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2480
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3726>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3726>
2020-02-06 00:19:13 +00:00
Eric Engestrom
9595b23a45 meson: don't bother trying python2
Meson requires `python3`, so we know it's there, no need to fall back to
python2.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3701>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3701>
2020-02-05 23:17:26 +00:00
Timur Kristóf
4d34abd15c aco/optimizer: Don't combine uniform bool s_and to s_andn2.
Fixes: 8a32f57fff

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3714>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3714>
2020-02-05 22:53:45 +00:00
Eric Anholt
a77c3d5eed nouveau: Reuse tgsi_get_gl_varying_semantic().
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>
2020-02-05 22:26:00 +00:00
Eric Anholt
f4f769c851 nouveau: reuse tgsi_get_gl_frag_result_semantic().
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>
2020-02-05 22:25:59 +00:00
Eric Anholt
f9358f6f76 nouveau: Reuse tgsi_get_sysval_semantic().
It's now in a place accessible from the nouveau driver.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>
2020-02-05 22:25:59 +00:00
Eric Anholt
e25967d6b8 mesa/st: Move the SYSTEM_VALUE -> TGSI_SEMANTIC map to tgsi_from_mesa.
This will let us reuse the table from nir-to-tgsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>
2020-02-05 22:25:59 +00:00
Kristian H. Kristensen
9891062642 freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED
This brings back fd6_fill_ubwc_buffer_sizes() to implement
layout_resource_for_modifier for DRM_FORMAT_MOD_QCOM_COMPRESSED.

Fixes: ecd62ff766 "freedreno: Allow UBWC on textures with multiple mipmap levels."
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
2020-02-05 20:53:32 +00:00
Kristian H. Kristensen
d233c8c914 freedreno: Add layout_resource_for_modifier screen vfunc
This function is responsible for completing the layout for an imported
resource with the given modifier.  Returns 0 on success or -1 If the
modifier is unsupported, invalid or the input parameters are not
compatible with the modifier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
2020-02-05 20:53:32 +00:00
Kristian H. Kristensen
af6fb4f0a9 freedreno: Set up supported modifiers in fd*_resource_screen_init()
Keep the modifier logic together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
2020-02-05 20:53:32 +00:00
Kristian H. Kristensen
d0a7c8f4a8 freedreno/a6xx: Add fd6_resource_screen_init()
We'll move a few things here in the next commits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
2020-02-05 20:53:32 +00:00
Eric Anholt
8d07d66180 glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.
This means you can directly use format utils on it without having to have
your own GL enum to number-of-components switch statement (or whatever) in
your vulkan backend.

Thanks to imirkin for fixing up the nouveau driver (and a couple of core
details).

This fixes the computed qualifiers for EXT_shader_image_load_store's
non-integer sizeNxM qualifiers, which we don't have tests for.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v3d)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
2020-02-05 10:31:14 -08:00
Eric Anholt
5bea0cf779 intel/isl: Move iris's pipe-to-isl format function to isl.
This will get reused in the shader compiler once we switch it over to pipe
formats instead of GL enums.  We can't easily deduplicate i965's
mesa-to-isl mapping because of cases like A32_FLOAT that are mapped
differently.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
2020-02-05 10:31:09 -08:00
Eric Anholt
bb615e5fe3 mesa: Clean up some endianness adapters for shader image formats.
We already had a uint version in formats.h, move the snorm/unorm ones
there, too.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
2020-02-05 10:31:09 -08:00
Jan Zielinski
23c137612b gallium/swr: Fix various asserts and security issues
To improve the robustness of the code, we want to better
detect issues in testing (using asserts) and use more
secure techniques.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3710>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3710>
2020-02-05 16:08:44 +00:00
Alyssa Rosenzweig
7eaf21cb6f pan/midgard: Fix scheduling issue with csel + render target reference
Fixes dEQP-GLES3.functional.shaders.fragdepth.write.dynamic_conditional_write

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Boris Brezillon
38c20696a5 panfrost: Set the MALI_WRITES_{Z,S} flags when needed
In order to make Z/S writes from fragment shaders effective, we need
to set the MALI_WRITES_{Z,S} flags when the shader has a
FRAG_RESULT_{DEPTH,STENCIL} output variable.

Now that shaders can change the S value, we can expose the
STENCIL_EXPORT cap.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Boris Brezillon
8ed94d38b4 panfrost: Add the MALI_WRITES_{Z,S} flags
We discovered 2 new shader flags used when a fragment shader updates
the depth/stencil value through a ZS writeout. If those flags are not
set, the depth/stencil value stored in the depth/stencil tilebuffer
remain unchanged.

While at it, rename unknown2 into flags_hi and rename flags into
flags_lo.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Boris Brezillon
0406ea4856 panfrost: Z24 variants should be sampled as R32UI
Midgard has no dedicated samplers for Z24S8 and Z24X8 formats, and the
GPU expects the depth to be encoded in an IEEE 32-bit float. Turn all
Z24_UNORM variants into R32UI and let the shader do the conversion
using bfe+fmul instructions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Boris Brezillon
e1ba0cd452 pan/midgard: Add nir_intrinsic_store_zs_output_pan support
ZS fragment stores are done like color fragment stores, except it's
using a different RT id (0xFF), the depth and stencil values are stored
in r1.x and r1.y.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
[Fix the scheduling part]

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Boris Brezillon
f5619f5073 pan/midgard: Turn Z/S stores into zs_output_pan intrinsics
Midgard can't write depth and stencil separately. It has to happen in
a single store operation containing both. Let's add a panfrost specific
intrinsic and turn all depth/stencil stores into a packed depth+stencil
one.

Note that this intrinsic is not yet handled in emit_intrinsic(), but
we'll address that later.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
2020-02-05 15:41:55 +00:00
Ian Romanick
59488cbbac intel/fs: Don't count integer instructions as being possibly coissue
Integer instructions don't coissue.  Before e64be391dd
("intel/compiler: generalize the combine constants pass"), this pass
only looked at float sources.  There's no shader-db data in that commit,
so I collected some.  The results are not good:

    Haswell
    total instructions in shared programs: 11898805 -> 11908127 (0.08%)
    instructions in affected programs: 1218680 -> 1228002 (0.76%)
    helped: 2
    HURT: 5171
    helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61
    helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40%
    HURT stats (abs)   min: 1 max: 311 x̄: 1.83 x̃: 1
    HURT stats (rel)   min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70%
    95% mean confidence interval for instructions value: 1.55 2.05
    95% mean confidence interval for instructions %-change: 1.02% 1.08%
    Instructions are HURT.

    total cycles in shared programs: 221664974 -> 221404750 (-0.12%)
    cycles in affected programs: 120012620 -> 119752396 (-0.22%)
    helped: 3464
    HURT: 3159
    helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16
    helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28%
    HURT stats (abs)   min: 1 max: 87846 x̄: 262.54 x̃: 14
    HURT stats (rel)   min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77%
    95% mean confidence interval for cycles value: -224.23 145.65
    95% mean confidence interval for cycles %-change: -0.50% -0.19%
    Inconclusive result (value mean confidence interval includes 0).

    total spills in shared programs: 9804 -> 10047 (2.48%)
    spills in affected programs: 6869 -> 7112 (3.54%)
    helped: 2
    HURT: 41

    total fills in shared programs: 19863 -> 20319 (2.30%)
    fills in affected programs: 17428 -> 17884 (2.62%)
    helped: 2
    HURT: 41

    LOST:   20
    GAINED: 13

This also prevents regressions in "intel/fs: Promote integer constants
after lowering integer multiplication" (note: that patch will probably
not be committed).  When the passes are reorderd, code like

    mul(8)      acc0<1>D    g9<8,8,1>D  -2078209981D    { align1 1Q };

gets turned into

    mov(1)      g23<1>D     2078209981D                 { align1 WE_all 1N };
    ...
    mul(8)      acc0<1>D    g13<8,8,1>D  -g23<0,1,0>D   { align1 1Q compacted };

It's not 100% clear why, but these produce different results.  Note that
-2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) =
0xffff0843.  It seems like the upper 16-bits of the negation should be
ignored.

Fixes: e64be391dd ("intel/compiler: generalize the combine constants pass")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

The shaders with spills or fills hurt are the usual suspects.  A couple
compute shaders in Dirt Showdown and a compute shader in Bioshock
Infinite.  On Haswell, a compute shader (that appears twice in
shader-db) from Aztec Ruins was also hurt for spill and fills.

Haswell
total instructions in shared programs: 11573934 -> 11568335 (-0.05%)
instructions in affected programs: 828623 -> 823024 (-0.68%)
helped: 2825
HURT: 6
helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61%
HURT stats (abs)   min: 1 max: 216 x̄: 81.83 x̃: 56
HURT stats (rel)   min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68%
95% mean confidence interval for instructions value: -2.31 -1.64
95% mean confidence interval for instructions %-change: -0.85% -0.80%
Instructions are helped.

total cycles in shared programs: 187573593 -> 187004633 (-0.30%)
cycles in affected programs: 82816107 -> 82247147 (-0.69%)
helped: 2186
HURT: 1741
helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16
helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90%
HURT stats (abs)   min: 1 max: 6138 x̄: 83.73 x̃: 16
HURT stats (rel)   min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75%
95% mean confidence interval for cycles value: -197.13 -92.64
95% mean confidence interval for cycles %-change: -0.72% -0.33%
Cycles are helped.

total spills in shared programs: 7870 -> 7743 (-1.61%)
spills in affected programs: 2260 -> 2133 (-5.62%)
helped: 31
HURT: 5

total fills in shared programs: 6320 -> 6263 (-0.90%)
fills in affected programs: 3547 -> 3490 (-1.61%)
helped: 31
HURT: 6

LOST:   9
GAINED: 9

Ivybridge
total instructions in shared programs: 11863372 -> 11859793 (-0.03%)
instructions in affected programs: 757183 -> 753604 (-0.47%)
helped: 2236
HURT: 3
helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1
helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48%
HURT stats (abs)   min: 11 max: 301 x̄: 192.33 x̃: 265
HURT stats (rel)   min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62%
95% mean confidence interval for instructions value: -2.01 -1.18
95% mean confidence interval for instructions %-change: -0.77% -0.70%
Instructions are helped.

total cycles in shared programs: 178377378 -> 177946087 (-0.24%)
cycles in affected programs: 76261390 -> 75830099 (-0.57%)
helped: 1635
HURT: 1395
helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16
helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64%
HURT stats (abs)   min: 1 max: 4315 x̄: 81.74 x̃: 18
HURT stats (rel)   min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53%
95% mean confidence interval for cycles value: -197.06 -87.62
95% mean confidence interval for cycles %-change: -0.78% -0.43%
Cycles are helped.

total spills in shared programs: 4188 -> 4182 (-0.14%)
spills in affected programs: 1557 -> 1551 (-0.39%)
helped: 30
HURT: 3

total fills in shared programs: 5056 -> 5245 (3.74%)
fills in affected programs: 2708 -> 2897 (6.98%)
helped: 30
HURT: 3

LOST:   5
GAINED: 1

No shader-db changes on any other Intel platform.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
2020-02-05 15:13:17 +00:00
Connor Abbott
8455648cca tu: Move vsc_data and vsc_data2 allocation into the device
In addition to preparing us for dynamically resizing them, which has to
be controlled by the device, this greatly reduces the memory usage when
allocating large numbers of command buffers, making
dEQP-VK.api.object_management.max_concurrent.command_buffer_primary go
from crash -> pass.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3621>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3621>
2020-02-05 15:27:28 +01:00
Connor Abbott
84bd4da468 freedreno: Fix CP_COND_EXEC
Noticed while looking at a trace of the Vulkan blob.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
2020-02-05 13:14:22 +00:00
Connor Abbott
ed5d1c1c47 freedreno: Add CP_REG_WRITE documentation
Document the first DWORD, which at least for the Vulkan blob on a640
isn't always 2.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
2020-02-05 13:14:22 +00:00
Connor Abbott
65197a3ac1 freedreno: Fix CP_COND_REG_EXEC bit positions
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
2020-02-05 13:14:22 +00:00
Michel Dänzer
8be81f8a2a gitlab-ci: Build radeonsi & RADV in the ppc64el job
This requires cross-building libdrm for ppc64el.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
2020-02-05 10:52:31 +00:00
Michel Dänzer
65610ec774 gitlab-ci: Add ppc64el and s390x cross-build jobs
Using LLVM 8 for ppc64el and 7 for s390x (which hits some coroutine
related issues with LLVM 8).

There are some test failures we need to ignore for now. Also, the
timeout needs to be bumped from the default 30s for some tests, because
they can take longer under emulation.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
2020-02-05 10:52:31 +00:00
Michel Dänzer
a443f81f26 gitlab-ci: Merge ccache and libxml2-utils into main apt-get install
The motivation for this is that we want to make use of the meson cross
files in this script, which have the ccache compiler paths.

We need to remove the ccache directory at the end, it would just waste
space in the image for no benefit.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
2020-02-05 10:52:31 +00:00
Michel Dänzer
a06fc0296d gitlab-ci: Pass -j4 to make
Might speed up x86_build docker image build a little.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
2020-02-05 10:52:31 +00:00
Michel Dänzer
84fefa206c gitlab-ci: Update to latest ci-templates HEAD
Among other things, this increases robustness when copying a docker
image from the main Mesa project to a forked project, avoiding spurious
image rebuilds from scratch.

Also drop the comment about .gitlab-ci/lava-gitlab-ci.yml, it doesn't
include the templates anymore.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
2020-02-05 10:52:31 +00:00
Pierre-Eric Pelloux-Prayer
3da91b3327 radeonsi/ngg: add VGT_FLUSH when enabling fast launch
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2418
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2426
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2434
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3675>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3675>
2020-02-05 10:27:54 +00:00
Eric Engestrom
2799676218 util/disk_cache: check for write() failure in the zstd path
CoverityID: 1458074
Fixes: a8d941091f ("util: Use ZSTD for shader cache if possible")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3672>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3672>
2020-02-05 01:09:04 +00:00
Eric Engestrom
6321e3fb9f dri: delete gen-symbol-redefs.py
Introduced in ba10d79cca but it looks like it was never wired
into anything.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3669>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3669>
2020-02-05 00:46:46 +00:00
Lionel Landwerlin
bcb611361b anv: implement gen12 post sync pipe control workaround
Same as Skylake.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
2020-02-05 00:25:48 +00:00
Lionel Landwerlin
8949d27bb8 anv: implement gen9 post sync pipe control workaround
We've been missing this workaround for a while and since it's required
for Gen12, let's implement it for Gen9 first.

v2: Update comment for Gen9.

v3: Fix clearing of bits... (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
2020-02-05 00:25:48 +00:00
Lionel Landwerlin
19e7bcee17 iris: implement gen12 post sync pipe control workaround
Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a
post-sync operation.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
2020-02-05 00:25:48 +00:00
Rob Clark
2c07e03b79 freedreno: allow ctx->batch to be NULL
This was mostly true already, now that we use `fd_context_batch()` for
first access to batch in draw/clear/grid paths.  So we can drop the old
code in `batch_flush()` that tried to prevent `ctx->batch` from being
NULL.

Fixes a crash with a large number of tabs in chromium.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3700>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3700>
2020-02-04 23:59:33 +00:00
Eric Anholt
22d2cbe685 freedreno: Allow UBWC on textures with multiple mipmap levels.
This is a backport of Jonathan Marek's UBWC work on turnip to GL.

Performance highlights from our trace set (320 frames sampled)
traces/glmark2/texture-texture-filter=mipmap.rdc:    +9.1% +/-   2.2%
traces/android/trex.rdc:                             +8.7% +/-   0.4%
traces/glmark2/desktop-effect=shadow:windows=4.rdc:  +4.2% +/-   2.5%

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
ecd62ff766 freedreno: Disable UBWC on Z24S8 if not TEXTURE_2D.
Fixes two of our three remaining GLES CTS failures, and avoids more
regressions once we enable UBWC mipmaps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
ddb0b35b76 freedreno: Blit all array levels when uncompressing UBWC.
Fixes regressions in GLES CTS's format_reintepret once we enable UBWC
with mipmaps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
6b586d5a48 freedreno: Swap the whole resource layout in shadowing.
Let's not have to worry about whether this unusual code path gets
updated whenever we adjust what is in the layout struct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
f9f5d3eb55 freedreno/a6xx: Disable the core layer-size setup.
This was getting in the way of UBWC mipmap handling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
17312b4a10 freedreno: Rename the UBWC layer size field and store it as bytes.
This makes the field description match its usage in the code, matches tu's
usage of the field, and avoids storing values in surprising units.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
b6b4118bb0 freedreno: Include the layer size in layout debug.
It's been many of my bugs so far.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Eric Anholt
20357dfde8 freedreno: Move the layout debug under FD_MESA_DEBUG=layout.
I keep wanting to turn this on while debugging layout stuff, and I
suspect krh and robclark could use it too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
2020-02-04 23:18:00 +00:00
Bas Nieuwenhuizen
65a6dc5139 radv: Do not set SX DISABLE bits for RB+ with unused surfaces.
The extra bits in CB_SHADER_MASK break dual source blending in
SkQP on a Stoney device. However:

- As far as I can tell, some other dual source blend tests are passing
  before and after the change.
- A hacked around skqp passes on my Vega desktop and Raven laptop
- Getting Skqp to give any useful info or to run it outside of Android
  on ChromeOS is proving difficult.

I have confirmed 3 strategies that seem to work:
- The old radv behavior of setting CB_SHADER_MASK to 0xF
- AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs
  are 0.
- radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE
  bits in SX_BLEND_OPT_CONTROL for CB 1-7.

Let us use the radeonsi solution as that solution also seems like the correct
thing to do for holes. I have tested on my Raven laptop that setting the high
surfaces to not disabled and downconvert to 32_R does not imply a performance
penalty.

Fixes: e9316fdfd4 "radv: fix setting CB_SHADER_MASK for dual source blending"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
2020-02-04 21:22:30 +00:00
Marek Olšák
17303c9851 mesa: implement missing display list functions while switching to the template
The vbo_init_tmp.h template tells us which functions are unimplemented.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
2020-02-04 15:12:05 -05:00
Marek Olšák
56de59b931 vbo: move reusable code from vbo_attrib_tmp.h into vbo_util.h
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
2020-02-04 15:12:03 -05:00
Marek Olšák
052e8f758e vbo: use the template for save GLvertexformat initialization
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
2020-02-04 15:12:01 -05:00
Marek Olšák
9ec5e96ec8 vbo: use the template for noop GLvertexformat initialization
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
2020-02-04 15:12:00 -05:00
Marek Olšák
d447a4888f vbo: move GLvertexformat initialization into a template header file for reuse
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
2020-02-04 15:11:58 -05:00
Eric Engestrom
cae6093266 freedreno/perfcntrs: fix fd leak
CoverityID: 1110568, 1458071
Fixes: 5a13507164 ("freedreno/perfcntrs: add fdperf")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3671>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3671>
2020-02-04 19:26:40 +00:00
Eric Anholt
8a2c507a8a util: Drop unpacking from int signed to unsigned and vice versa.
After all the previous cleanups, it's clear that the callers only ever
ask for SINT->SINT or UINT->UINT.  Cuts 20k of compiled text from
gallium drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
1d367c3aa5 gallium: Refactor some single-pixel util_format_read/writes.
We can use the new row helpers to cut down on the noise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
ab081970e0 gallium: Add and use a helper for packing uc from a color_union.
The same pattern kept coming up, and we don't need to hit
util_format_write_4* to do it when we have util_format_pack_rgba().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
b2a2cf492d softpipe: Refactor pipe_get/put_tile_rgba_* paths.
We always want the same behavior of choosing which unpack to do to
generate our 4x32-bit RGBA values, so just sink that choice down below
the pipe_get/put_tile API.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
8bc56551da softpipe: Drop the raw_to* part of the tile cache interface.
Nothing else uses it, so make it static.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
6cdf523f00 gallium/util: Remove pipe_get_tile_z/put_tile_z.
The previous caller wasn't using it as tiled, just row-at-a-time, and
didn't want the clipping (since copytexsubimage comes in clipped).  If
someone wanted these functions again in the future, they should be
rewritten on u_format_pack/unpack.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
e986f2b7af mesa/st: Use direct util_format_pack/unpack instead of u_tile.
We're doing a row at a time, and don't need u_tile's clipping.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Eric Anholt
c574cda3c6 util: Make helper functions for pack/unpacking pixel rows.
Almost all users of the unpack functions don't have strides to plug in
(and many are only doing one pixel!), and this will help simplify
them.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
2020-02-04 19:02:59 +00:00
Karol Herbst
333c9d5bb0 clover: add trivial clCreateCommandQueueWithProperties implementation
It's not adding 2.0 features, but it's enough to run the 2.0 CTS on top of
clover and probably most CL applications using it.

We just fail if we hit unknown properties and that's probably good enough
until we implement the other bits properly.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2370>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2370>
2020-02-04 18:09:23 +00:00
Eric Anholt
b064697af1 gallium/osmesa: Try to fix the test for big-endian.
Our packed expected values will be byte-swapped for the (mostly) array
formats we're testing.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:08 +00:00
Eric Anholt
dd899fd43e gallium/osmesa: Fill out other format tests.
Move expected values/bpp into the test params, add more formats now that
we've fixed context setup so that they work.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:08 +00:00
Eric Anholt
0a53918f02 gallium/osmesa: Fix MakeCurrent of non-8888 contexts.
OSMesa is weird and you only get the type (byte/ubyte/565/etc.) at
MakeCurrent time, having only a channel order at CreateContext time.  The
code was setting up a visual at CreateContext time, and then at
MakeCurrent it would fail to validate against the visual.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:08 +00:00
Eric Anholt
655394c6ed gallium/osmesa: Fix a typo in the unit test's test names.
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:08 +00:00
Danylo Piliaiev
75c50d0342 osmesa/tests: Cover OSMESA_RGB GL_UNSIGNED_BYTE case
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:08 +00:00
Danylo Piliaiev
d83abf1d37 st/mesa: Handle the rest renderbuffer formats from OSMesa
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2189
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/989
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2036
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
2020-02-04 17:48:07 +00:00
Eric Engestrom
d1165ad18b util/os_socket: fix header unavailable on windows
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2464
Fixes: e62c3cf350 ("util/os_socket: Include unistd.h to fix build error")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
2020-02-04 17:33:49 +00:00
Danylo Piliaiev
36126b6211 i965: Do not set front_buffer_dirty if there is no front buffer
Otherwise there will be a warning:
 "libEGL warning: FIXME: egl/x11 doesn't support front buffer rendering."

Happens with EGL_KHR_surfaceless_context:

 eglMakeCurrent(egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, egl_context)
 eglMakeCurrent(egl_display, egl_surface, egl_surface, egl_context)
 glFlush() // Here will be a warning

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1525
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
2020-02-04 15:41:05 +00:00
Tomeu Vizoso
9afdcd64f2 gitlab-ci: Switch kernel for LAVA jobs to 5.5
All fixes we were carrying in our branch have been merged already.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
2020-02-04 15:46:34 +01:00
Alyssa Rosenzweig
162927e43c panfrost: Use size0 when calculating the offset to a depth level
Previously, we were using cubemap_stride and sometimes overwriting other
BOs such as shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
2020-02-04 15:46:30 +01:00
Tomeu Vizoso
64541dd698 panfrost: Only clamp the LOD to disable mipmapping when needed
Otherwise, we may be incrementing max_lod over the limit, causing a
DATA_INVALID_FAULT.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
2020-02-04 15:46:26 +01:00
Tomeu Vizoso
255227ecec panfrost: Fix decoding of tiled 3D textures
From decoding cmd streams generated by the blob, the pointers in the
payload don't seem to include those that refer to different depth levels
when the texture is in tiled format.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
2020-02-04 15:46:06 +01:00
Erik Faye-Lund
fd27fb5113 st/mesa: use uint-result for sampling stencil buffers
Otherwise, we end up mismatching the result-type and the sampler-type.

Fixes: 642125edd9 ("st/mesa: use uint-samplers for sampling stencil buffers")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3680>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3680>
2020-02-04 07:43:36 +00:00
Alyssa Rosenzweig
9cdd89a34b pan/midgard: Remove unused variable
../src/panfrost/midgard/mir.c: In function ‘mir_bytemask_of_read_components_index’:
../src/panfrost/midgard/mir.c:471:18: warning: unused variable ‘mask’ [-Wunused-variable]
  471 |         uint16_t mask = 0;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>
2020-02-04 08:24:37 +01:00
Alyssa Rosenzweig
0f3eb7989b pan/midgard: Check for null consts
Valid shaders shouldn't hit this, but Coverity doesn't know that.

CID 1458029:    (FORWARD_NULL)
Passing null pointer "consts" to "print_scalar_field", which dereferences it.

Tomeu: Fix name of variable

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>
2020-02-04 08:24:33 +01:00
Alyssa Rosenzweig
8ec4028d40 panfrost: Avoid overlapping copy
CID 1457486:  Memory - corruptions  (OVERLAPPING_COPY)

Assigning "(*attr).extra_flags = (*attr).size = 0U" to "(*attr).stride",
which have overlapping memory +locations.

Coverity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>
2020-02-04 08:24:18 +01:00
Marek Vasut
c32bd325e7 etnaviv: Destroy rsc->pending_ctx set in etna_resource_destroy()
Destroy rsc->pending_ctx set in etna_resource_destroy(), otherwise
the memory is allocated, never free'd, and becomes unreachable. This
fixes a memory leak.

Fixes: 9e672e4d20 ("etnaviv: keep references to pending resources")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
2020-02-04 06:27:19 +00:00
Kristian H. Kristensen
df6a2a7197 turnip: Be explicit about converting vk compare func to a6xx
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
6dd57f0e38 nir: Remove always-true assert
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
e3dfa8f4d6 glsl: Use 'using' to be explicit about visitor overloads
Clang has a warning about overloading virtuals that triggers when a
derived class defines a virtual function that's an overload of
function in the base class.  This kind of thing:

  struct chart; // let's pretend this exists
  struct Base
  {
      virtual void* get(char* e);
  };

  struct Derived: public Base {
      virtual void* get(chart* e); // typo, we wanted to override the same function
  };

The solution is to use

  using Base::get;

to be explicit about the intention to reuse the base class virtual.
We hit this a lot with out glsl ir_hierarchical_visitor visitor
pattern, so let's adds some 'using' to calm down the compiler.

See-also: https://stackoverflow.com/questions/18515183/c-overloaded-virtual-function-warning-by-clang)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
0bc516fceb spirv/opencl: Cast opcode up front to avoid warnings
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
67dd51606c freedreno/fdperf: Cast away some ignored return values
This is developer tool, it can crash and burn if it fails to allocate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
2be81a3bfa nir: Make unroll pragma work on clang
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Kristian H. Kristensen
de856c6170 nir: Delete unused is_var_constant() helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
2020-02-04 06:03:52 +00:00
Fritz Koenig
42f7e124ca Revert "gitlab-ci: disable a630 tests as mesa-cheza is down"
This reverts commit f38851d84c

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3687>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3687>
2020-02-03 21:45:16 +00:00
Jan Vesely
0ccda2ebff clover: Use explicit conversion from llvm::StringRef to std::string
Fixes build after llvm 777180a32b61070a10dd330b4f038bf24e916af1
("[ADT] Make StringRef's std::string conversion operator explicit")

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2020-02-03 21:25:59 +00:00
Erik Faye-Lund
5d83314945 zink: disallow depth-stencil blits with format-change
The Vulkan spec says this about vkCmdBlitImage:

   "No format conversion is supported between depth/stencil images. The
    formats must match."

So yeah, let's stop trying to do this.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>
2020-02-03 21:42:52 +01:00
Erik Faye-Lund
85d4b41f68 zink: be more careful about the mask-check
We currently disallow blits that we can support. Let's be more accurate
when checking the mask.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>
2020-02-03 21:42:49 +01:00
Boris Brezillon
b550b7ef3b panfrost: Fix the damage box clamping logic
When the rendering are is not covering the whole FBO, and the biggest
damage rect is empty, we can have damage.max{x,y} > damage.min{x,y},
which leads to invalid reload boxes.

Fixes: 65ae86b854 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Boris Brezillon
2b089e26bf pan/midgard: Stop leaking instruction objects in mir_schedule_alu()
Allocate those instructions with ralloc() instead of using mem_dup.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Boris Brezillon
c7e68d8625 pan/midgard: Don't check 'branch && branch->writeout' twice in mir_schedule_alu()
There's a writeout bool storing the result of this test. Use it instead
of duplicating the test.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Boris Brezillon
ef89a52fe5 pan/midgard: Lower bitfield extract to shifts
Let's lower bitfield extract to shifts until we figure out if it can be
natively supported.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Boris Brezillon
c68cd39eb3 pan/midgard: Make sure we pass the right RT id to emit_fragment_store()
nir_intrinsic_base() is assigned nir_variable.data.driver_location,
which is assigned a unique ID based on the variable position in the
shader variable list. There's no guarantee that this position will
match the RT id we want to pass to emit_fragment_store().

Add a search_var() helper to retrieve a nir_variable based on its driver
location, so we can pass the right RT value to emit_fragment_store().

We also make sure the shader output is color, since emit_fragment_store()
is not ready for depth/stencil stores yet.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Boris Brezillon
25946be4c4 pan/midgard: Add an enum to describe the render targets
We are about to add a special ZS render target, let's add a enum so we
can easily know which render target we're dealing with.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
2020-02-03 12:53:47 +00:00
Bernd Kuhls
e62c3cf350 util/os_socket: Include unistd.h to fix build error
Fixes

In file included from ../src/util/os_socket.c:8:
../src/util/os_socket.h:26:1: error: unknown type name ‘ssize_t’; did you mean ‘size_t’?
 ssize_t os_socket_recv(int socket, void *buffer, size_t length, int flags);

seen with gcc version 8.3.0 (Buildroot 2019.11) and uClibc 1.0.32.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: ef5266ebd5 ("util/os_socket: Add socket related functions.")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3659>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3659>
2020-02-03 10:55:44 +00:00
Eric Engestrom
f38851d84c gitlab-ci: disable a630 tests as mesa-cheza is down
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3677>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3677>
2020-02-03 10:08:25 +00:00
Ilia Mirkin
a4e6270541 nv50: report max lod bias of 15.0
The blob returns 15, the state creation code clamps it to 15, but since
the dawn of time we've returned 4.0. Setting this to 15 also fixes

GTF-GL33.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_clamp_m_le_M

which is sensitive to these limits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-02-02 22:01:18 -05:00
Eric Engestrom
0021f7dc30 egl: put full path to libEGL_mesa.so in GLVND json
This is useful when installing to a non-standard path.

glvnd_icd.py copied & adapted from src/intel/vulkan/anv_icd.py

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3038>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3038>
2020-02-02 17:46:17 +00:00
Bas Nieuwenhuizen
d5fd8cd46e radv: Allow non-dedicated linear images and buffer.
Requested for virtualized Vulkan as they need to export memory to
map it.

Since radeonsi and the kernel assume an image without metadata is
linear, this should work just fine.

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583>
2020-02-02 17:47:14 +01:00
Alyssa Rosenzweig
38f963226b pan/midgard: Implement mixed-type constant packing
Lot of churn but mostly just specializes types per source instead of per
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>
2020-02-02 15:51:06 +00:00
Alyssa Rosenzweig
a12fe52cbc pan/midgard: Break out one-src read_components
For constant packing, this is interesting to break down further.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>
2020-02-02 15:51:06 +00:00
Icecream95
b74212e701 panfrost: Fix non-debug builds
For non-debug builds, where assertions are compiled out, GCC complains
about the end of the non-void function panfrost_translate_channel_width
being reached.

Fixes: 226c1efe9a ("panfrost: Add more info to some assertions")
Reported-by: Piotr Oniszczuk
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3665>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3665>
2020-02-02 15:33:17 +00:00
Jason Ekstrand
d7fe9af620 anv/blorp: Use the correct size for vkCmdCopyBufferToImage
Now that we're using an uncompressed format for the buffer, we have to
scale down the dimensions we pass into BLORP when doing buffer->image
copies.

Fixes: dd92179a72 "anv: Canonicalize buffer formats for image/buffer..."
Closes: #2452
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
2020-02-02 11:41:09 +00:00
Eric Engestrom
8ff613dc58 VERSION: bump after 20.0 branch point
Closes: #2457
2020-02-02 06:54:14 +00:00
Vinson Lee
02658df152 lima: Fix build with GCC 10.
This patch fixes this build error with GCC 10.

/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_context.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_resource.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_draw.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_bo.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_submit.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_util.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here
/usr/bin/ld: src/gallium/drivers/lima/liblima.a(lima_texture.c.o):src/gallium/drivers/lima/lima_util.h:32: multiple definition of `lima_dump_command_stream'; src/gallium/drivers/lima/liblima.a(lima_screen.c.o):src/gallium/drivers/lima/lima_util.h:32: first defined here

Fixes: d71cd245d7 ("lima: Rotate dump files after each finished pp frame")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2020-01-31 19:18:58 -08:00
Rob Clark
982d61e2cd freedreno/ir3: fix a dirty lie
Lies, damn lies, and leftover hacks!

We no longer hard-code these two, so fix the disasm to print the correct
values.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
752aeb7b3f freedreno/ir3: simplify split from collect
In some cases we need to split components out from what was already a
collect.  That was making it hard to DCE unused components of the
collect.  (Ie. unused components of fragcoord, etc)

So just detect this case and skip the chained collect+split.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
8d0e7d9a4c freedreno/ir3: create fragcoord instructions in input block
This was somehow working to create the instructions in a random block,
and use the value in other blocks, by dumb luck.  But two-pass-RA's
better choice of register assignment causes a couple dEQPs to start
failing without this fix:

dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_1
dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_2

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
fb09020ef2 freedreno/ir3: remove unused tex arg harder
Just killing the SSA link isn't enough.  It confuses RA, legalize,
and postsched to see a bogus unused reg.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
2ffe44ec0a freedreno/ir3: add RA sanity check
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
2f4f46b708 freedreno/a6xx: fix lrz overflow
Running the complete deqp_gles2 seems to trigger an overflow in lrz
cmdstream.  We skip the blit clear fast-path if there have been any
draws (so mid-batch clears of any attached buffer hit the 3d pipe).
Which means it is safe to simply discard any lrz clear rendering.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
3e79c4f0ed freedreno/ir3: two pass register allocation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
b0293af7a5 freedreno/ir3: don't precolor unused inputs
This apparently can happen with gs/tess.  And will cause problems with
two-pass-ra, so lets just skip them.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
ad2587d3c8 freedreno/ir3: add is_tex_or_prefetch()
Some of the aspects of tex prefetch are in common with normal tex
instructions, such as having a wrmask to control which components
are written.  Add a helper for this.

This should result in actually using the prefetch wrmask to avoid
fetching unneeded components.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
4a7a6c9ef0 freedreno/ir3: number instructions from one
ra_block_compute_live_ranges() treats zero as "not yet defined", so
probably best to not let this be a valid instruction #

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
0f78c32492 freedreno/ir3: post-RA sched pass
After RA, we can schedule to increase parallelism (reduce nop's) without
worrying about increasing register pressure.  This pass lets us cut down
the instruction count ~10%, and prioritize bary.f, kill, etc, which
would tend to increase register pressure if we tried to do that before
RA.

It should be more useful if RA round-robin'd register choices.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
3369406e44 freedreno/ir3: fix kill scheduling
kill (and other cat0/flow instructions) do not have a dst register.
Which was mostly harmless before, other than RA thinking it would need
a free register to write.  (But nothing consumed it, so the value would
be immediately dead.)  But this would cause more problems with postsched
which would see a bogus dependency.

Also, post-RA sched *does* need to see the dependency on the predicate
register.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
9a9f78f1f9 freedreno/ir3/ra: make use()/def() functions instead of macros
Originally these were nested functions, which worked nicely, giving us
the function of a local macro that was actual 'c' syntax (ie. not token
pasted macro).  But these were converted to macros because clang doesn't
let us have nice gcc extensions.

Extract these back out into functions, before adding more things and
making the macros even more cumbersome.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
a5f24f966a freedreno/ir3: a bit more optmsgs debug
Also dump where arrays are allocated.  This was useful for debugging.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
300d1181c7 freedreno/ir3: move atomic fixup after RA
A post-RA sched pass will move the extra mov's to the wrong place, so
rework the fixup so it can run after RA (and therefore after postsched)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
304b50c9f8 freedreno/ir3: move block-scheduling into legalize
We want to do this only once.  If we have post-RA sched pass, then we
don't want to do it pre-RA.  Since legalize is where we resolve the
branch/jumps, we might as well move this into legalize.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
093c94456b freedreno/ir3: move nop padding to legalize
This way we can deal with it in one place, *after* all the blocks have
been scheduled.  Which will simplify life for a post-RA sched pass.

This has the benefit of already taking into account nop's that legalize
has to insert for non-delay related reasons.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
c803c662f9 freedreno/ir3: split out delay helpers
We're going to want these also for a post-RA sched pass.  And also to
split nop stuffing out into it's own pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
54c795f829 freedreno/ir3: fix crash when no non-input instructions
This scenario can come up with block-sched and nop-sched moved to after
RA.  So lets fix it first to keep things bisectable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
c1194e10b2 freedreno/ir3: cleanup after lower_locals_to_regs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Rob Clark
f0b792ea06 freedreno/ir3: shuffle a few ir3_register fields
It makes life easier for postsched to always be able to rely on wrmask.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
2020-02-01 02:40:22 +00:00
Anuj Phogat
95831e2f66 intel/gen12+: Set way_size_per_bank to 4
This patch fixes the way_size_per_bank for Gen12+

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
2020-01-31 18:14:54 -08:00
Anuj Phogat
00a84c170a intel/gen12+: Reserve 4KB of URB space per bank for Compute Engine
This patch is required to fix 11K+ vulkan CTS failures we were
getting with way_size_per_bank of 4 (see next patch).

Thanks to Sagar Ghuge and Jordan Justen for all the hard work of
debugging and testing.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
2020-01-31 18:14:54 -08:00
Szymon Andrzejuk
c0d8b373ad virgl: Use align_free for align_malloc allocated buffer
Signed-off-by: Szymon Andrzejuk <s.andrzejuk@samsung.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2020-02-01 00:41:38 +00:00
Rob Clark
d326d30efe freedreno/drm: readonly cmdstream
Noticed that we weren't consistently making cmdstream buffers
gpu-readonly.  Fix that and drop the need to pass flags to
fd_bo_new_ring().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3663>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3663>
2020-01-31 13:01:52 -08:00
Jason Ekstrand
f93dfb509c intel/fs: Write the address register with NoMask for MOV_INDIRECT
This fixes a hang in the following Vulkan CTS test on TGL-LP:

    dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
2020-01-31 17:23:39 +00:00
Jason Ekstrand
9a95abd0f7 intel/tools: Handle strides better when dumping buffers
The old code would only break at stride boundaries if the stride was
less than 32B; otherwise it would just break every 32B.  This commit
makes it break at stride boundaries and 32B boundaries (starting from
the last stride).  This makes reading large vertex buffers in aubinator
much nicer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
2020-01-31 17:23:39 +00:00
Jason Ekstrand
51d7c42165 intel/disasm: SEND has two sources on Gen12+
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
2020-01-31 17:23:39 +00:00
Jason Ekstrand
fa3ef6a837 intel/eu/validate: Don't validate regions of sends
Otherwise, the validator tries to read the type of src1 of a SEND/SENDS
which doesn't actually have a type field.  This prevents validation
issues in the next commit.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
2020-01-31 17:23:39 +00:00
Daniel Schürmann
3b323d6601 aco: fix image_atomic_cmp_swap
Fixes: 71440ba0f5 ('aco: reorder VMEM operands in ACO IR')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3652>
2020-01-31 16:51:46 +00:00
Samuel Pitoiset
0d14f41625 aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
When some unused channels are skipped and that we expand vec3 loads
to vec4 loads, we have to adjust the fourth component.

While we are at it, add an assertion to make sure we don't use
MUBUF for vec3 loads on GFX6.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2450
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2442
Fixes: 6aecc316 ("aco: fix VS input loads with MUBUF on GFX6")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3641>
2020-01-31 13:48:56 +01:00
Krzysztof Raszkowski
d8410fec4e gallium/swr: Fix gcc 4.8.5 compile error
Stop using C++14 feature so it can be compile on default centos7
gcc compiler.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3640>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3640>
2020-01-31 10:40:54 +00:00
Vinson Lee
8dacf5f9d1 swr: Fix build with GCC 10.
GCC 10 added _mm256_storeu2_m128i.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91341

This patch fixes this build error with GCC 10.

In file included from src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.cpp:39:
../src/gallium/drivers/swr/rasterizer/common/os.h:178:20: error: ‘void _mm256_storeu2_m128i(__m128i*, __m128i*, __m256i)’ redeclared inline without ‘gnu_inline’ attribute
  178 | static INLINE void _mm256_storeu2_m128i(__m128i* hi, __m128i* lo, __m256i a)
      |                    ^~~~~~~~~~~~~~~~~~~~
In file included from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:51,
                 from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32,
                 from ../src/gallium/drivers/swr/rasterizer/common/os.h:107,
                 from src/gallium/drivers/swr/rasterizer/codegen/gen_knobs.cpp:39:
/usr/lib/gcc/x86_64-redhat-linux/10/include/avxintrin.h:1580:1: note: ‘void _mm256_storeu2_m128i(__m128i_u*, __m128i_u*, __m256i)’ previously defined here
 1580 | _mm256_storeu2_m128i (__m128i_u *__PH, __m128i_u *__PL, __m256i __A)
      | ^~~~~~~~~~~~~~~~~~~~

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3650>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3650>
2020-01-31 10:18:53 +00:00
Krzysztof Raszkowski
790516db0b gallium/swr: fix gcc warnings
Few changes to make gcc happy.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3629>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3629>
2020-01-31 09:52:27 +00:00
Erik Faye-Lund
8405e1bef0 zink: implement support for derivative-control
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3645>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3645>
2020-01-31 08:56:55 +00:00
Erik Faye-Lund
f12b844e7c zink: implement load_instance_id
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3644>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3644>
2020-01-31 08:40:24 +00:00
Erik Faye-Lund
c0ced1e79b zink: enable texture-buffer objects
This seems to work as-is, and just need enabling. There's a few piglit
failures, but those seems to be problems with the tests, where they
don't handle lacking GL3-support.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3647>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3647>
2020-01-31 08:23:07 +00:00
Zhang, Boyuan
00edb82fde radeonsi: Add support for midstream bitrate change in encoder
BACKPORT: Remove |picture| argument from enc->begin in radeon_vcn_enc.c

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3426>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3426>
2020-01-31 07:47:36 +00:00
Tomeu Vizoso
d902e23d80 panfrost: Use DBG macro to avoid noise in the console
It pollutes the output of programs that use Panfrost and can confuse its
callers, such as test runners.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
2020-01-31 06:02:31 +00:00
Tomeu Vizoso
2504206221 pan/midgard: Handle nir_intrinsic_load_barycentric_centroid
To avoid hitting the assert in the default case, add a nop for this
intrinsic.

dEQP-GLES3.functional.transform_feedback.random.interleaved.lines.3

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
2020-01-31 06:02:31 +00:00
Tomeu Vizoso
226c1efe9a panfrost: Add more info to some assertions
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
2020-01-31 06:02:31 +00:00
Tomeu Vizoso
2d5c433aee panfrost: Print intended field when decoding
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3625>
2020-01-31 06:02:31 +00:00
Jason Ekstrand
8c5fd2942b anv: Always fill out the AUX table even if CCS is disabled
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:31 -06:00
Jason Ekstrand
2ccdf881ab iris: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:30 -06:00
Jason Ekstrand
e6b39850f0 anv: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:28 -06:00
Jason Ekstrand
ce9c45a60e intel/blorp: Plumb deref block size through to 3DSTATE_SF
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:27 -06:00
Jason Ekstrand
fdc0c19328 intel/common: Return the block size from get_urb_config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:26 -06:00
Jason Ekstrand
e340a79b9c anv: Emit URB setup earlier
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:24 -06:00
Jason Ekstrand
e928676b69 iris: Consolodate URB emit
Now that we don't have to carry a URB state emit function for BLORP we
can roll some stuff together and drop a genX helper.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:22 -06:00
Jason Ekstrand
09e4c33085 intel/blorp: Always emit URB config on Gen7+
Previously, i965/iris tried to reuse the currently programmed URB config
if it was good enough for BLORP, rather than reprogramming it each time.
However, this will make some things harder on Gen12+ and we've not seen
any performance impact from emitting URB more frequently in ANV.

This makes the blorp <-> driver interface a bit simpler on Gen7+ because
now all the driver has to do is to provide the L3$ config rather than
trying to hand off URB re-config to blorp.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:20 -06:00
Jason Ekstrand
73a684964b intel: Take a gen_l3_config in gen_get_urb_config
Instead of making each driver pass in the same push constant size and do
it's own L3$ config URB size calculation, just make them pass in their
L3$ configuration.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:18 -06:00
Jason Ekstrand
9d05822cb8 i965: Re-emit l3 state before BLORP executes
If BLORP is the first thing to execute, we may not have set the L3$
config yet.  That's not normally a problem but we're about to add code
to BLORP which will look at brw_context::l3::config and we'd like that
to be initialized.  It's also just good practice.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:16 -06:00
Jason Ekstrand
bff7b3c7bd iris: Use the URB size from the L3$ config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:14 -06:00
Jason Ekstrand
99f3178a24 iris: Store the L3$ configs in the screen
We only calculate them based on device info and never change them so
this seems like a reasonable place to put them.  We could also put them
in the context, but that's not accessible from iris_init_*_context.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:13 -06:00
Jason Ekstrand
6471bac99e iris: Set SLMEnable based on the L3$ config
Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:46:10 -06:00
Jason Ekstrand
73434b665b intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11
SML is no longer in the L3$ on Gen11+.  It's not incredibly clear from
the docs but no Gen11 platforms are in the list of platforms on which
this bit exists.  Also, we've been always setting it false on Gen11 in
ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:45:53 -06:00
Jason Ekstrand
e1bdb127b6 anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+
According to the BSpec, this should prevent hangs when using shaders
with large URB entries.  A more precise fix can be done but it requires
re-arranging URB setup.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:45:52 -06:00
Jason Ekstrand
9da9abf8a7 genxml: Add a new 3DSTATE_SF field on gen12
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
2020-01-30 18:45:49 -06:00
Dylan Baker
21dd0a1514 docs/release-calendar: 20.0.0-rc1 has been released 2020-01-30 14:43:17 -08:00
Brian Ho
58fd26c433 turnip: Fix vkCmdCopyQueryPoolResults with available flag
Previously, calling vkCmdCopyQueryPoolResults with the
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT flag set the query result
field in the buffer to 0 if unavailable and the query result if
available. This was a misunderstanding of the Vulkan spec, and this
commit corrects the behavior to emitting a separate available
result in addition to the query result.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
2020-01-30 20:30:46 +00:00
Brian Ho
1a3e2a7fa8 turnip: Fix vkGetQueryPoolResults with available flag
Previously, calling vkGetQueryPoolResults with the
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT flag set the query result
field in *pData to 0 if unavailable and the query result if
available. This was a misunderstanding of the Vulkan spec, and this
commit corrects the behavior to eriting a separate available result
in addition to the query result.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3560>
2020-01-30 20:30:46 +00:00
Brian Ho
1c3319cf81 turnip: Free event->bo on vkDestroyEvent
Fixes a leak from freeing event but not event->bo.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3639>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3639>
2020-01-30 18:50:06 +00:00
Kenneth Graunke
594cb30356 loader: Fix leak of kernel driver name
This is strdup'd, it needs to be freed.

CID: 1458032
Fixes: f93bb2fb102 ("loader: Check if the kernel driver is i915 before loading iris")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3630>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3630>
2020-01-30 10:08:17 -08:00
Jan Zielinski
f09c466732 docs: Update SWR tessellation support
Update features.txt to reflect ARB_tessellation_shader
support in SWR

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3636>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3636>
2020-01-30 11:18:15 +00:00
Kenneth Graunke
bdba744d70 i965: Use brw_batch_references in tex_busy check
If the batch references the buffer, we will have to flush the batch
immediately before mapping it, at which point it will be busy.

(This bug has existed for a long time...even going back to BLT-era...)

Fixes: 779923194c ("i965/tex_image: Use meta for instead of the blitter PBO TexImage and GetTexImage")
Fixes: d5d4ba9139 ("i965/tex_subimage: use meta instead of the blitter for PBO TexSubImage")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
2020-01-30 10:01:21 +00:00
Christian Gmeiner
d3fa18a1fa etnaviv: drm-shim: add GC400
These are the ETNAVIV_PARAM's returned from a GC400 found on a
STM32MP157C-DK2 Discovery Board running mainline kernel.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3195>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3195>
2020-01-30 04:05:39 +00:00
Qiang Yu
c5e4d28724 lima: add noheap debug option
Disable using heap buffer when set.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
2020-01-30 03:39:21 +00:00
Qiang Yu
b220aec628 lima: create heap buffer with new interface if available
Newly added heap buffer create interface can create a
large enough buffer whose backup memory can increase
dynamically as needed.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
2020-01-30 03:39:21 +00:00
Qiang Yu
92465cc999 lima: sync lima_drm.h with kernel
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3264>
2020-01-30 03:39:21 +00:00
Icenowy Zheng
cd30c4d719 lima: fix lima_set_vertex_buffers()
When setting the vertex buffers, lima calls
util_set_vertex_buffers_mask() to reference and copy buffers. That
function
function adds dst with start_slot internally, so lima should not offset
the destination address again.

This is discovered when comparing with other drivers, and fixed by
removing the extra offset in lima_set_vertex_buffers().

This fixes draws that get translated in u_vbuf, because u_vbuf adds
extra vertex buffers when translating.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3620>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3620>
2020-01-30 07:51:35 +08:00
Jonathan Marek
1c5d84fcae turnip: hook up cmdbuffer event set/wait
Gets some basic tests under "dEQP-VK.synchronization.*event*" passing

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3123>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3123>
2020-01-29 23:13:43 +00:00
Christian Gmeiner
5b5b762475 etnaviv: drop default state for PE_STENCIL_CONFIG_EXT2
It gets emitted when needed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3631>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3631>
2020-01-29 23:31:04 +01:00
Daniel Schürmann
d78e0de772 docs: add new features for RADV/ACO.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>
2020-01-29 22:05:37 +00:00
Samuel Pitoiset
3a3b16a395 radv: refactor physical device properties
Based on ANV. This removes a bunch of duplicated code for properties.

Fixes: 1b8d99e288 ("radv: bump conformance version to 1.2.0.0")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
2020-01-29 21:44:56 +00:00
Rob Clark
5b9fe18485 freedreno: remove flush-queue
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
b3b1fa5e2b freedreno: add gmem_lock
The gmem state is split out now, so it does not require synchronization.
But gmem rendering still accesses vsc state from the context.

TODO maybe there is a better way?  For gen's that don't do vsc resizing,
this is probably easier.. but for a6xx there isn't really a great
position for more fine grained locking.  Maybe it doesn't matter since
in practice the lock shouldn't be contended.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
91f9bb99c5 freedreno: add gmem state cache
Which also has the benefit of getting rid of fd_context::gmem.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
712f8802ee freedreno: get GMEM state from batch
Prep work to reduce churn in next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
4bcc3a0923 freedreno/a2xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
5d442144ae freedreno/a3xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
7236d6dd4c freedreno/a4xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
2d2f4a55eb freedreno/a5xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
637ca78ee2 freedreno/a6xx: constify gmem state
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
82a64af907 freedreno: constify fd_vsc_pipe
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
cbae9f34e9 freedreno: constify fd_tile
In a following patch, when we cache the gmem state, we will want to
treat the gmem state as immuatable.  So start converting things to
const to make this more clear.. fd_tile is a good place to start.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
c7ab8874d0 freedreno: consolidate GMEM state
The tile and vsc_pipe arrays are really part of the GMEM configuration.
So pull these out of fd_context and into fd_gmem_stateobj.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Rob Clark
62c10b395e freedreno: extract vsc pipe bo from GMEM state
Prep work for reorganizing GMEM state and extracting out of fd_context.
The vsc pipe bo was the one thing that doesn't change with GMEM/tile
config.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
2020-01-29 21:19:41 +00:00
Alejandro Piñeiro
d5c32db076 turnip: remove unused descriptor state dirty
It was only used to be initialized to zero. Not even updated as
descriptor sets are bind.

As far as I understand, setting the bit TU_CMD_DIRTY_DESCRIPTOR_SET on
tu_cmd_state.dirty is used instead.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>
2020-01-29 20:52:52 +00:00
Timur Kristóf
e73f604b21 aco: Fix the meaning of is_atomic.
Previously, is_atomic really meant "is not atomic", contrary to its name.
This commit fixes it to mean what one would think it means.

Fixes: 69bed1c918

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>
2020-01-29 20:32:31 +00:00
Kenneth Graunke
ba148813d7 iris: Support multiple chained batches.
There was never much point in artificially limiting chaining to two
batches - we can trivially support arbitrary length chains.

Currently, we should only ever have 1 or 2, but this may change.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
2020-01-29 19:53:22 +00:00
Kenneth Graunke
94f9c5fff6 iris: Make iris_emit_default_l3_config pull devinfo from the batch
No need to pass it, we can just use batch->screen->devinfo.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
2020-01-29 19:53:22 +00:00
Kenneth Graunke
afcb6625e3 iris: Drop 'engine' from iris_batch.
For the moment, everything is I915_EXEC_RENDER, so this isn't necessary.
But even should that change, I don't think we want to handle multiple
engines in this manner.

Nowadays, we have batch->name (IRIS_BATCH_RENDER, IRIS_BATCH_COMPUTE,
possibly an IRIS_BATCH_BLIT for blorp batches someday), which describes
the functional usage of the batch.  We can simply check that and select
an engine for that class of work (assuming there ever is more than one).

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
2020-01-29 19:53:22 +00:00
Eric Anholt
06b13dfed2 tu: Fix binning address setup after pack macros change.
This fixes a regression in "vkcube -m headless" rendering, but upsettingly
none of my CTS tests I've been using.

Fixes: 59f29fc845 ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")
Caught-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
2020-01-29 19:30:09 +00:00
Brian Ho
3d5bdea2cf turnip: Enable occlusionQueryPrecise
This commit enables the occlusionQueryPrecise feature. No additonal
work is required as occlusion queries are already implemented to
track exact sample counts.

Also enables a number of extra tests on the Vulkan CTS.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>
2020-01-29 19:05:23 +00:00
Daniel Schürmann
6f718edced aco: simplify gathering of MIMG address components
This patch has a slight effect on pipelinedb:
Totals from affected shaders:
SGPRS: 23616 -> 21504 (-8.94 %)
VGPRS: 15088 -> 14444 (-4.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 662660 -> 664600 (0.29 %) bytes
LDS: 49 -> 49 (0.00 %) blocks
Max Waves: 3079 -> 3204 (4.06 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
2020-01-29 18:45:23 +00:00
Daniel Schürmann
901f06e9ad aco: simplify adjust_sample_index_using_fmask() & get_image_coords()
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
2020-01-29 18:45:23 +00:00
Daniel Schürmann
99d032f3cd aco: fix register allocation with multiple live-range splits
This patch fixes register allocation if multiple live-range splits
occur to the same variable within one instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
2020-01-29 18:45:23 +00:00
Daniel Schürmann
71440ba0f5 aco: reorder VMEM operands in ACO IR
For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
2020-01-29 18:45:23 +00:00
Caio Marcelo de Oliveira Filho
8548fe19f0 nir: Make nir_deref_path_init skip trivial casts
In a NIR generated using SPIR-V initializers to variables, copy
propagation can end up transforming

    vec1 32 ssa_33 = deref_var &@1 (shared mat2x4)
    vec1 32 ssa_35 = mov ssa_33
    vec1 32 ssa_7 = deref_cast (mat2x4 *)ssa_35 (shared mat2x4)  /* ptr_stride=0 */

into

    vec1 32 ssa_33 = deref_var &@1 (shared mat2x4)
    vec1 32 ssa_7 = deref_cast (mat2x4 *)ssa_33 (shared mat2x4)  /* ptr_stride=0 */

Before the optimization, the "head" of a path of deref that uses ssa_7
will be the cast.  After, it will be the variable in ssa_33.  Since
the types are the same, this is a trivial cast that would be picked up
by nir_opt_deref.

If we need to compare such deref-chain after optimization with another
deref-chain for the same variable, the compare function will get
confused by the cast in the middle.

One alternative would be to add nir_opt_deref to places that compare
derefs, but that might not scale well, so skip the trivial casts when
generating the paths instead.

Motivated by the discussion in
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047#note_383660.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3420>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3420>
2020-01-29 18:25:36 +00:00
Rhys Perry
db19e96c8c aco: fix exec mask consistency issues
There seems to be more, these are just the ones found in
Detroit: Become Human shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
c7d0514168 aco: parallelcopy exec mask before s_wqm
It can be used later and we want any uses to not be fixed to exec, so it's
definition can't be fixed to exec because of how exec masks interact with
register demand calculation.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
517fc3abc4 aco: fill reg_demand with sensible information in add_coupling_code()
process_block() will use this to determine the register demand of the
before the current instruction. Previously, it was filled with zeroes
which could result in process_block() only using the register demand
of after the current instruction.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
26d2511bcb aco: improve assertion at the end of spiller
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
5ea23ba659 aco: set exec_potentially_empty after continues/breaks in nested IFs
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
4e83e05e62 aco: error when block has no logical preds but VGPRs are live at the start
This would have caught the liveness error fixed in the previous commit.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
d282a292ec aco: don't always add logical edges from continue_break blocks to headers
Otherwise, code like this will be broken:
loop {
   if (...) {
      break;
   } else {
      break;
   }
}
The continue_or_break block doesn't have any logical predecessors but it's
a logical predecessor of the header block. This liveness error breaks the
spiller in init_live_in_vars() (under "keep variables spilled on all
incoming paths") and eventually creates garbage reloads.

Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
dba71de5c6 aco: only create parallelcopy to restore exec at loop exit if needed
The operand isn't fixed to exec, which can mess up the spiller. This also
adds a new situation where a phi is needed.

Fixes dEQP-VK.ssbo.layout.random.descriptor_indexing.2 and an assertion
when compiling a Detroit: Become Human shader.

Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
4537b97410 aco: don't update demand in add_coupling_code() for loop headers
We don't need to update it since it won't be used later.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
521525fc0a aco: don't consider loop header blocks branch blocks in add_coupling_code
Loops without continues create header blocks with only 1 predecessor.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Rhys Perry
590c26beab aco: fix target calculation when vgpr spilling introduces sgpr spilling
A shader might require vgpr spilling but not require sgpr spilling. In
that case, the spiller lowers the sgpr target by 5 which could mean sgpr
spilling is then required. Then the vgpr target has to be lowered to make
space for the linear vgprs. Previously, space wasn't make for the linear
vgprs.

Found while testing the spiller on the pipeline-db with a lowered limit

Fixes: a7ff1bb5b9
   ('aco: simplify calculation of target register pressure when spilling')

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
2020-01-29 18:02:27 +00:00
Samuel Pitoiset
a61eff8330 radv/gfx10: re-enable NGG GS
Now that NGG GS queries are implemented, it should be safe enough
to enable NGG GS by default. It can be disabled with RADV_DEBUG=nongg
if necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
2020-01-29 17:40:51 +01:00
Samuel Pitoiset
e4752dafed radv/gfx10: implement NGG GS queries
The number of generated primitives is only counted by the hardware
if GS uses the legacy path. For NGG GS, we need to accumulate that
value in the NGG GS itself. To achieve that, we use a plain GDS
atomic operation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
2020-01-29 17:40:48 +01:00
Samuel Pitoiset
3c1f657f35 radv/gfx10: add a separate flag for creating a GDS OA buffer
For implementing NGG GS queries, we decided to use GDS but GDS OA
is only required for NGG streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
2020-01-29 17:40:46 +01:00
Michel Dänzer
ca6a22305b winsys/amdgpu: Close KMS handles for other DRM file descriptions
When a BO or amdgpu_screen_winsys is destroyed.

Should fix leaking such BOs in other DRM file descriptions.

v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
  Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3a "winsys/amdgpu: Make KMS handles valid for original
                     DRM file descriptor"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
2020-01-29 15:51:01 +00:00
Michel Dänzer
9f2bed49d4 winsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.

v2:
* Adapt to amdgpu_winsys::sws_list_lock.
v3:
* Fix comparison of amdgpu_screen_winsys file descriptions, see
  https://gitlab.freedesktop.org/mesa/mesa/issues/2413 .
* Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in
  amdgpu_winsys_create.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
2020-01-29 15:51:01 +00:00
Jason Ekstrand
f21b40d0bf anv: Rename a variable
The name "desc" shadows another variable.  Name it "desc_data" like all
of the other descriptor data variables in this file.
2020-01-29 09:43:42 -06:00
Jason Ekstrand
e3f1a08c56 anv/block_pool: Ensure allocations have contiguous maps
Because softpin block pools are made up of a set of BOs with different
maps, it was possible for a single state to end up straddling blocks.
To fix this, we pass a contiguous size to anv_block_pool_grow and it
ensures that the next allocation in the pool will have at least that
size.

We also add an assert in anv_block_pool_map to ensure we always get
contiguous maps.  Prior to the changes to anv_block_pool_grow, the unit
tests failed with this assert.  With this patch, the tests pass.

This was causing problems on Gen12 where we allocate the pages for the
AUX table from the dynamic state pool.  The first chunk, which gets
allocated very early in the pool's history, is 1MB which was enough that
it was getting multiple BOs.  This caused the gen_aux_map code to write
outside of the map and overwrite the instruction state pool buffer which
lead to GPU hangs.

Fixes: 731c4adcf9 "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-29 09:43:42 -06:00
Jason Ekstrand
ee4cdef9ae anv: Re-use one old BT block in reset_batch_bo_chain
We intentionally throw away all but one BT block but then we set
cmd_buffer->bt_block to ANV_STATE_NULL instead of the one we hung on to.
This causes the command buffer to immediately re-emit STATE_BASE_ADDRESS
the first time a BT is needed for no good reason.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-29 09:43:42 -06:00
Jason Ekstrand
a2e9dd51b3 anv: Set actual state pool sizes when we have softpin
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-29 09:43:42 -06:00
Rhys Perry
1f72857739 nir/algebraic: add some half packing optimizations
pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 29200 -> 29200 (0.00 %)
VGPRS: 17372 -> 17372 (0.00 %)
Spilled SGPRs: 105 -> 105 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1406576 -> 1389256 (-1.23 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Max Waves: 3976 -> 3976 (0.00 %)

pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 21320 -> 21320 (0.00 %)
VGPRS: 17056 -> 17036 (-0.12 %)
Spilled SGPRs: 22 -> 22 (0.00 %)
Spilled VGPRs: 503 -> 487 (-3.18 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 396 -> 396 (0.00 %) dwords per thread
Code Size: 1441244 -> 1423292 (-1.25 %) bytes
LDS: 463 -> 463 (0.00 %) blocks
Max Waves: 3609 -> 3611 (0.06 %)

v2: add pattern for ishr

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
2020-01-29 14:30:33 +00:00
Rhys Perry
5476d18183 nir/algebraic: add patterns for a >> #b << #b
Fixes compilation of a Battlefront 2 shader with ACO by removing VGPR
spilling. The reassociation makes it worse on LLVM though.

pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 10704 -> 10688 (-0.15 %)
VGPRS: 18736 -> 18528 (-1.11 %)
Spilled SGPRs: 70 -> 70 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 909696 -> 885796 (-2.63 %) bytes
LDS: 225 -> 225 (0.00 %) blocks
Max Waves: 1115 -> 1129 (1.26 %)

pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 8472 -> 8424 (-0.57 %)
VGPRS: 14284 -> 14368 (0.59 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 442 -> 503 (13.80 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 268 -> 396 (47.76 %) dwords per thread
Code Size: 862568 -> 853028 (-1.11 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 971 -> 964 (-0.72 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
2020-01-29 14:30:33 +00:00
Samuel Pitoiset
6aecc316c0 aco: fix VS input loads with MUBUF on GFX6
Only MTBUF supports vec3.

Fixes: 03a0d39366 ("aco: use MUBUF in some situations instead of splitting vertex fetches")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>
2020-01-29 13:58:37 +00:00
Rhys Perry
404818dd28 aco: run p_wqm instructions in WQM
If the p_wqm ends up creating copies, these need to be in WQM. Helps (but
doesn't completely fix) artifacts in Strange Brigade. The actual issue
still exists and is harder to fix.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
2020-01-29 13:23:03 +00:00
Rhys Perry
2d7386a2d0 aco: ensure predecessors' p_logical_end is in WQM when a p_phi is in WQM
We want any copies to be in WQM. I don't know if this fixes any real
application, but I can create a vkrunner test than reproduces the issue.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
2020-01-29 13:23:03 +00:00
Icecream95
9be9fd8591 pan/midgard: Fix a liveness info leak
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>
2020-01-29 12:59:32 +00:00
Jonathan Marek
6346490a2e etnaviv: implement UBOs
At the same time, use pre-HALTI2 to use address register for indirect
uniform loads, since integers/LOAD instruction isn't always available.

Passes all dEQP-GLES3.functional.ubo.* on GC7000L. GC3000 with an extra
flush hack passes most of them, but still fails on some of the cases with
many loads.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
2020-01-29 11:47:34 +00:00
Rob Clark
7ff8ce7a3f freedreno/a6xx: convert blend state to stateobj
And move to new register builders while we are at it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
2020-01-29 11:21:47 +00:00
Rob Clark
f066e3afc7 freedreno/a6xx: remove special handling based on MRT format
Logicop in particular is supposed to work for integer formats.. but
maybe this situation doesn't happen in gles.  The only thing that isn't
required for integer formats is blending.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
2020-01-29 11:21:47 +00:00
Rob Clark
eb281df1a1 mesa/st: random whitespace cleanup
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
2020-01-29 11:21:47 +00:00
Rob Clark
d0e0141526 freedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
This lets us drop a bunch of special handling for xRGB blend.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
2020-01-29 11:21:47 +00:00
Thomas Hellstrom
9ee3ec348e gallium/util: Increase the debug_flush map depth
Some piglit tests trigger a map depth assert when debug_flush is active.
Fix this by increasing the map depth from 16 to 32.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
2020-01-29 10:56:06 +00:00
Thomas Hellstrom
8830e9f0ca svga: Avoid discard DMA uploads
Newer versions of the device code will make discard DMA uploads
sub-optimal. Disable them for guest-backed aware code, where we previously
had them conditionally enabled.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
2020-01-29 10:56:06 +00:00
Thomas Hellstrom
8afe12b212 winsys/svga: Enable transhuge pages for buffer objects
If the kernel supports it, enable transhuge pages for graphics buffer
objects. Except for the syscall itself, this is never expected to cause
any negative performance implications.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
2020-01-29 10:56:06 +00:00
Roland Scheidegger
3b3c2daf3a winsys/svga: use new ioctl for logging
Use the new ioctl for logging (rather than duplicating what the kernel
is doing). This way it's also independent from the actual guest/host
mechanism to do the logging.

Signed-off-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
2020-01-29 10:56:06 +00:00
Samuel Pitoiset
f53b4defad radv: remove the non conformant VK implementation warning on GFX10
It's no longer true.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
2020-01-29 10:35:15 +00:00
Samuel Pitoiset
1b8d99e288 radv: bump conformance version to 1.2.0.0
https://www.khronos.org/conformance/adopters/conformant-products#submission_472
https://www.khronos.org/conformance/adopters/conformant-products#submission_473
https://www.khronos.org/conformance/adopters/conformant-products#submission_474

Fixes dEQP-VK.api.driver_properties.conformance_version.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
2020-01-29 10:35:15 +00:00
Samuel Pitoiset
401bfe0283 radv: implement VK_AMD_shader_explicit_vertex_parameter
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2402
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
663d5c1399 radv: gather which input PS variables use an explicit interpolation mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
3922d95b51 aco: implement VK_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
6f4c300919 ac/llvm: implement VK_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
531a26d5aa spirv: implement SPV_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
cf6cae832c nir: lower interp_deref_at_vertex to load_input_vertex
This introduces a new NIR intrinsic for loading inputs at a specific
vertex index.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
d29f10a7ca nir: add nir_intrinsic_interp_deref_at_vertex
From the SPV_AMD_shader_explicit_vertex_parameter extension:
   "Returns the value of the input <interpolant> without any
    interpolation, i.e. the raw output value of previous shader
    stage."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
687f170311 nir: lower SYSTEM_VALUE_BARYCENTRIC_* to nir_load_barycentric()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
9021b45b35 nir: add nir_intrinsic_load_barycentric_model
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
df8dd12e5b spirv: add support for SpvBuiltInBaryCoord*
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
61d24080bb compiler: add new SYSTEM_VALUE_BARYCENTRIC_*
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
15d53d8294 compiler: add PERSP to the existing barycentric system values
We need the LINEAR versions for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
5c053cc6ec spirv: add support for SpvDecorationExplicitInterpAMD
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Samuel Pitoiset
746e9e5d66 compiler: add a new explicit interpolation mode
This introduces one more interpolation mode INTERP_MODE_EXPLICIT,
which is needed for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
2020-01-29 09:49:50 +00:00
Eduardo Lima Mitev
e6b531af66 turnip: Fix issues in tu_compute_pipeline_create() that may lead to crash
The shader object is destroyed even if its creation failed. It is also
not destroyed if its compilation or upload fails, leading to leaks.

Finally, tu_compute_pipeline_create() should set output var
pPipeline to VK_NULL_HANDLE if it fails.

Avoids crash on
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
2020-01-29 09:25:20 +00:00
Eduardo Lima Mitev
0e11e8ba89 turnip: Remove failed command buffer from pool
When an error condition occurs during tu_create_cmd_buffer(), the
cmd buffer has already been added to a pool, so the cleanup code should
remove it.

Fixes a crash (assert in tu_device::tu_bo_finish()) in dEQP tests:

dEQP-VK.api.object_management.max_concurrent.command_buffer_primary
dEQP-VK.api.object_management.max_concurrent.command_buffer_secondary

due to pool attempting to destroy an invalid command buffer.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
2020-01-29 09:25:20 +00:00
Pierre-Eric Pelloux-Prayer
ab54624d0d radeonsi: stop using the VM_ALWAYS_VALID flag
Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.

Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
  available memory
- disable VM_ALWAYS_VALID entirely

v1 of this patch implemented option 2. v2 (this version) implements option 3.

Related issues:
 - https://gitlab.freedesktop.org/drm/amd/issues/607
 - https://gitlab.freedesktop.org/mesa/mesa/issues/1257

It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2190
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
2020-01-29 09:05:04 +01:00
Samuel Pitoiset
b05ac4b158 radv: enable VK_AMD_shader_fragment_mask on GFX6-GFX7
Works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
2020-01-29 08:08:27 +01:00
Kenneth Graunke
baf9327fa1 loader: Check if the kernel driver is i915 before loading iris
To prevent it from trying to load on say gma500 hardware.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
2020-01-28 15:35:09 -08:00
Jordan Justen
2969012d03 anv: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
2020-01-28 21:57:17 +00:00
Jordan Justen
da03e07cc2 iris: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
2020-01-28 21:57:17 +00:00
Erik Faye-Lund
b175effc72 zink: set compareEnable when setting compareOp
We need to enable compareEnable for compareOp to be valid, and ANV was
recently updated to respect this. So let's update Zink to match.

This fixes the shadow-variants of several piglit regressions, like these:
spec@arb_shader_texture_lod@execution@tex-miplevel-selection
spec@glsl-1.20@execution@tex-miplevel-selection

Fixes: a19cdf989b ("anv: only use VkSamplerCreateInfo::compareOp if enabled")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
2020-01-28 21:04:26 +00:00
Eric Anholt
f6e59911e5 ci: Enable -Werror on the meson-i386 build.
I find warnings to be very disruptive to my workflow (using emacs's "go to
next error" feature), and I periodically have to go clean up other
people's drivers to get back to finding my own warnings in the noise.  I
know I'm not the only one doing something like this.

We don't want to enable -Werror by default in builds, since it means that
end users will have builds spuriously fail based on what compiler version
and opt flags they have compared to what the devs are using.  However, it
is quite easy to have CI ensure that we at least don't introduce warnings
on the compiler version that it uses.

For now I've just enabled it on meson-i386 to cover a bunch of Mesa core
and get us started on ratcheting up warnings-cleanliness in the tree,
without me having to fix up all the drivers at once.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
2020-01-28 12:31:07 -08:00
Eric Anholt
527a8c345b mesa/st: Fix compiler warnings from INTEL_shader_integer_functions.
Fixes: 1d165b0548 ("glsl: Add new expressions for INTEL_shader_integer_functions2")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
2020-01-28 12:31:03 -08:00
Eric Anholt
096921c878 iris: Silence warning about AUX_USAGE_MC.
It was recently introduced and not added to iris yet it looks like.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
2020-01-28 12:30:48 -08:00
Eric Anholt
05e3ccd8a1 vulkan/wsi: Fix compiler warning when no WSI platforms are enabled.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
2020-01-28 12:30:48 -08:00
Dylan Baker
71c6208200 docs: update news, calendar, and link release notes for 19.3.3
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
2020-01-28 11:36:21 -08:00
Dylan Baker
3e49d0efe7 docs: Add SHA 256 sums for 19.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
2020-01-28 11:35:30 -08:00
Dylan Baker
f9ef115927 docs: Add relnotes for 19.3.3 release
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
2020-01-28 11:35:28 -08:00
Jason Ekstrand
997040e4b8 intel/mi_builder: Force write completion on Gen12+
Otherwise, we have no guarantee that the write actually lands before we
move on to other things.  Doing this on every SDI is probably a bit
harsh but it's safe.  We should figure out a good way to avoid this when
we can.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
2020-01-28 18:15:29 +00:00
Jason Ekstrand
06657e1dda anv: Replace one more aux_surface.isl.size_B check
This one was missed in 41bffe0913.

Fixes: 41bffe0913 "anv: Replace aux_surface.isl.size_B checks with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
2020-01-28 18:15:29 +00:00
Jason Ekstrand
f229579c0a intel/blorp: Handle bit-casting UNORM and BGRA formats
In f132e0fddf, I attempted to allow BLORP to do CCS_E copies by using
the UNORM formats instead.  However, the old BLORP bit-cast code could
only handle RGBA formats and asserted on anything other than UINT
formats.  The reason we didn't catch this is because it only comes up on
Gen12 platforms which aren't in our normal CI yet.

Fixes: f132e0fddf "intel/blorp: Add support for CCS_E copies with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
2020-01-28 18:15:29 +00:00
Daniel Schürmann
396be00640 aco: fix combine_salu_not_bitwise() when SCC is used
Previously, we didn't use the SCC bit, and thus, we didn't care about it.
With 'aco: Transform uniform bitwise instructions to 32-bit if possible.'
that changed, so that we have to handle it.

Fixes: 8a32f57fff ('aco: Transform uniform bitwise instructions to 32-bit if possible.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
2020-01-28 18:14:02 +01:00
Drew Davenport
0d99ff54cc radeonsi: Clear uninitialized variable
|view| was not initialized leading to flaky test failures in SkQP
test unitTest_ES2BlendWithNoTexture.

Fixes: 029bfa3d25 "radeonsi: add ability to bind images as image buffers"

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
2020-01-28 16:29:48 +00:00
Brian Ho
815a603889 anv: Handle unavailable queries in vkCmdCopyQueryPoolResults
If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no
special handling of unavailable queries in vkCmdCopyQueryPoolResults,
and anv will write an invalid value for the query result.

This commit updates vkCmdCopyQueryPoolResults for unavailable
queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set
and if not, skip writing altogether.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
2020-01-28 15:17:21 +00:00
Brian Ho
af92ce50a7 anv: Properly fetch partial results in vkGetQueryPoolResults
Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT)
of an unavailable occlusion query via vkGetQueryPoolResults can
return invalid values. anv returns slot.end - slot.begin, but in the
case of unavailable queries, slot.end is still at the initial value
of 0. If slot.begin is non-zero, the occlusion count underflows to
a value that is likely outside the acceptable range of the partial
result.

This commit fixes vkGetQueryPoolResults by always returning 0 if the
query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
2020-01-28 15:17:21 +00:00
Rhys Perry
7edcf4a59d aco: fix rebase error from GS copy shader support
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: f8f7712666 ('aco: implement GS copy shaders')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
2020-01-28 13:50:53 +00:00
Tapani Pälli
dd9bf7d291 anv/android: make format_supported_with_usage static
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
2020-01-28 14:46:38 +02:00
Tapani Pälli
104744f4df anv/android: setup gralloc1 usage from gralloc0 usage manually
This cuts away dependency to libgrallocusage.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
2020-01-28 14:46:25 +02:00
Rhys Perry
03a0d39366 aco: use MUBUF in some situations instead of splitting vertex fetches
Fixes most of the regressions from splitting vertex fetches in an earlier
commit.

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 562696 -> 558344 (-0.77 %)
VGPRS: 395596 -> 393752 (-0.47 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 11600912 -> 11311804 (-2.49 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 101839 -> 102372 (0.52 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:44:52 +00:00
Rhys Perry
21d2799cee aco: value-number MUBUF instructions
We will have to do this when we start creating MUBUF instructions for
load_input because NIR might not be able to tell they are identical since
it doesn't know whether two vertex attributes have the same offset.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:40:22 +00:00
Rhys Perry
d39f5519a1 aco: handle unaligned vertex fetch on GFX10
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 795000 -> 802368 (0.93 %)
VGPRS: 579632 -> 581280 (0.28 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 17208408 -> 17583652 (2.18 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 145731 -> 145279 (-0.31 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:40:10 +00:00
Rhys Perry
d9e357e35b aco: skip unused channels at the start when fetching vertices
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 161320 -> 161224 (-0.06 %)
VGPRS: 153968 -> 149408 (-2.96 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 4331496 -> 4331308 (-0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27814 -> 28594 (2.80 %)

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 161504 -> 161408 (-0.06 %)
VGPRS: 153836 -> 149440 (-2.86 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 4327572 -> 4327604 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27837 -> 28618 (2.81 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:40:01 +00:00
Rhys Perry
525b107347 aco: rework vertex fetching a bit
This will make it easier to skip unused channels at the start and to split
unaligned loads on GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:39:57 +00:00
Rhys Perry
4363a1f75b amd/common,radv: move vertex_format_table to ac_shader_util.{h,c}
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
2020-01-28 11:39:52 +00:00
Jan Zielinski
ab7ac1ffda gallium/swr: fix tessellation state save/restore
Tessellation state should be saved with TCS/TES state
when binding new state and restored if old state
is set again.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
2020-01-28 13:55:47 +01:00
Vasily Khoruzhick
fe5267d322 lima: disable early-z if fragment shader uses discard
We have to disable early-z if fragment shader uses discard,
otherwise we'll get misrendering.

Reported-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
2020-01-27 22:35:43 -08:00
Vasily Khoruzhick
650c680545 lima: ppir: always create move and update ld_tex successors for all blocks
Always create a mov for ld_tex since we can't rely on
ppir_node_has_single_src_succ() if we have multiple blocks. And since
ld_tex successor can be in a different block we have to update their
ppir_src as well.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
2020-01-28 01:45:29 +00:00
Vasily Khoruzhick
4a0f62f1fc lima: ppir: don't delete root ld_tex nodes without successors in current block
We don't clone ld_tex nodes into each block anymore, so ld_tex may have
successors in another block.

Fixes: c8554f849e ("lima/ppir: don't clone texture loads")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
2020-01-28 01:45:29 +00:00
Rob Clark
63af27bc76 freedreno/drm: fix invalid-cmdstream-size with older kernels
A cmdstream of size zero is invalid.  But this can appear in various
places where we emit a pointer to state.  This doesn't show up with
newer kernels (newer than v5.0) which use "softpin", but on earlier
kernels can result in:

  [drm:msm_ioctl_gem_submit [msm]] *ERROR* invalid cmdstream size: 0

Since the pointer value doesn't matter in these cases, the easy solution
is just to not emit a cmds table entry in this case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
2020-01-28 00:09:34 +00:00
Marek Olšák
0c154d9e2d Revert "winsys/amdgpu: Re-use amdgpu_screen_winsys when possible"
This reverts commit b60f5cbc15.

This fixes dmesg errors and X freezes:
[   29.543096] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
[   29.543103] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
2020-01-27 17:48:42 -05:00
Marek Olšák
ba06c7620f Revert "winsys/amdgpu: Close KMS handles for other DRM file descriptions"
This reverts commit 552028c013.

Required by the next reverted commit.
2020-01-27 17:48:25 -05:00
Jason Ekstrand
993f866d2e anv: Insert holes for non-existant XFB varyings
Thanks to optimizations, it's possible for varyings to get deleted but
still leave the variable there for nir_gather_xfb_info to find.  If we
get into this case, insert a hole.

Fixes: 36ee2fd61c "anv: Implement the basic form of..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
2020-01-27 20:26:23 +00:00
Jason Ekstrand
68b3bfaa42 intel/genxml: Make SO_DECL::"Hole Flag" a Boolean
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
2020-01-27 20:26:23 +00:00
Sagar Ghuge
a27542c5dd intel/compiler: Clear accumulator register before EOT
v2: (Francisco Jerez)
- Drop vec4 changes.
- Handle explicit acc0 operand and implicit one.
- Make sure instruction is SIMD16, prediction is off and default mask
  control set to true.

v3: (Francisco Jerez)
- Clear accumulator only when it's written.
- Use BRW_MASK_DISABLE instead of true.
- Use correct width for brw_acc_reg().
- Fix last_inst_offset.

v4: (Francisco Jerez)
- Don't check for last instruction for accummulator write.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
2020-01-27 19:48:11 +00:00
Alyssa Rosenzweig
480cf7d9bf pan/midgard: Remove float_bitcast
Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
2020-01-27 13:37:36 -05:00
Samuel Pitoiset
83e1fa87a7 radv: do not allow sparse resources with multi-planar formats
It's unsupported.

Fixes some fails or hangs with
dEQP-VK.sparse_resources.image_sparse_binding.*

Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
2020-01-27 15:47:49 +00:00
Boris Brezillon
24360966ab panfrost/midgard: Prettify embedded constant prints
Until now, embedded constants were printed as all 32 bits integer or
floats, but the compiler can pack constant from different types if
severa instructions with different reg_mode and native type refer to
the constant register. Let's implement something smarter so users don't
have to do a manual conversion when looking at a trace.

Note that 8-bit constants are not decoded yet, as we're not sure how
the writemask is encoded in that case.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
2020-01-27 15:24:54 +00:00
Boris Brezillon
aa973fc14e panfrost/midgard: Add a condense_writemask() helper
This way we can convert an 8-bit writemask (Midgard specific
representation) into the more common 1-bit/component representation.

8-bit mode is not supported yet, as we're not sure how the writemask is
encoded for this mode.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
2020-01-27 15:24:54 +00:00
Rhys Perry
2dc63d39d3 aco: fix literal application with v_cndmask_b32/v_addc_co_u32/etc
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be7409069 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
2020-01-27 14:50:37 +00:00
Rhys Perry
827681f921 aco: always add sgprs to sgpr_ids when choosing literals
Even if it's a literal, we should add this to sgpr_ids.
No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be7409069 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
2020-01-27 14:50:37 +00:00
Rhys Perry
92970adb4b aco: fix operand to scc when selecting SGPR ufind_msb/ifind_msb
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
2020-01-27 14:50:37 +00:00
Rhys Perry
e6c90e4af9 aco: fix WaR check for >64-bit FLAT/GLOBAL instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 5986e0019 ('aco: improve WAR hazard workaround with >64bit stores')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
2020-01-27 14:50:37 +00:00
Alyssa Rosenzweig
8784062abb pan/midgard: Handle tag 0x4 as texture
Used for barriers which work as texture ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
2020-01-27 13:38:41 +00:00
Alyssa Rosenzweig
5a271df028 pan/midgard: Validate barriers use a barrier tag
...and that non-barriers don't use a barrier tag. It's not clear what
the difference means quite yet, though.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
2020-01-27 13:38:41 +00:00
Alyssa Rosenzweig
c9f4eface3 pan/midgard: Disassemble barrier instructions
We don't need to print all the usual texture noise; just the relevant
fields and the rest can be guarded to zero.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
2020-01-27 13:38:41 +00:00
Alyssa Rosenzweig
556964d927 pan/midgard: Record TEXTURE_OP_BARRIER
It's 0x0B for whatever reason.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
2020-01-27 13:38:41 +00:00
Alyssa Rosenzweig
3993969477 pan/decode: Drop MFBD compute shader stuff
This is triggering all sorts of failures in pandecode and is only mostly
spurious. Let's not overwhelm ourselves with this yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
2020-01-27 13:38:41 +00:00
Icecream95
8004874885 panfrost: Don't copy uniforms when the size is zero
This fixes a crash when using Gallium HUD with QuakeSpasm when gamma
correction shaders (a QuakeSpasm feature, not part of Mesa) are used.

Reviewd-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549>
2020-01-27 13:23:34 +00:00
Florian Will
951083768b radv/winsys: set IB flags prior to submit in the sysmem path
This fixes missing scene objects in ZUSI 3 + dxvk. Index / vertex buffer
upload using thousands of CopyBuffer commands in one huge Vulkan command
buffer, mixed with lots of render pass begin/end and draw calls, failed
for some of the buffers.

radv divides the huge command buffer into 3 IBs, and they had random
flags set because the field was uninitialized. Maybe IBs got discarded
if they had the PREAMBLE bit set.

Signed-off-by: Florian Will <florian.will@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
2020-01-27 11:53:22 +01:00
Pierre-Eric Pelloux-Prayer
90312de551 docs: document AMD_DEBUG variable
See https://gitlab.freedesktop.org/mesa/mesa/issues/2022

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
2020-01-27 09:29:10 +01:00
Pierre-Eric Pelloux-Prayer
a803d41248 radeonsi: move AMD_DEBUG tests to AMD_TEST
AMD_DEBUG env var is stored in a 64 bits int and has 64 different values.
This commit makes some space by moving the test* special values to AMD_TEST.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
2020-01-27 09:29:10 +01:00
Dave Airlie
58ba7b696d gallivm/nir: add missing break for isub.
Pointed out by coverity scan.

Fixes: 3adf74f2ef ("gallivm: pick integer builders for alu instructions.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3571>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3571>
2020-01-27 08:05:27 +10:00
Lionel Landwerlin
8bd92a15cf isl: add gen12 comment about CCS for linear tiling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
2020-01-26 20:46:14 +00:00
Lionel Landwerlin
a3f6db2c4e isl: drop CCS row pitch requirement for linear surfaces
We were applying row pitch constraint of CCS surfaces to linear
surfaces. But CCS is only supported in linear tiling under some
condition (more on that in the following commit). So let's drop that
requirement for now.

Fixes a bunch of crucible assert where the byte size of a linear image
is expected to be similar to the byte size of buffer for the same
extent in the following category :

   func.miptree.r8g8b8a8-unorm.aspect-color.view-2d.*download-copy-with-draw.*

v2: Move restriction to isl_calc_tiled_min_row_pitch()

v3: Move restrinction to isl_calc_row_pitch_alignment() (Jason)

v4: Update message (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 07e16221d9 ("isl: Round up some pitches to 512B for Gen12's CCS")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
2020-01-26 20:46:14 +00:00
Lionel Landwerlin
397ff2976b intel: Implement Gen12 workaround for array textures of size 1
Gen12 does not support RENDER_SURFACE_STATE::SurfaceArray = true &&
RENDER_SURFACE_STATE::Depth = 0. SurfaceArray can only be set to true
if Depth >= 1.

We workaround this limitation by adding the max(value, 1) snippet in
the shaders on the 3 components for texture array sizes.

Tested on Gen9 with the following Vulkan CTS tests :
dEQP-VK.image.image_size.2d_array.*

v2: Drop debug print (Tapani)
    Switch to GEN:BUG instead of Wa_

v3: Fix dEQP-VK.image.image_size.1d_array.* cases (Lionel)

v4: Fix dEQP-VK.glsl.texture_functions.query.texturesize.* cases
    (Missing tex_op handling) (Lionel)

v5: Missing break statement (Lionel)

v6: Fixup comment (Tapani)

v7: Fixup comment again (Tapani)

v8: Don't use sample_dim as index (Jason)
    Rename pass
    Simplify control flow

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v7)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
2020-01-26 22:27:03 +02:00
Jason Ekstrand
4d03e53127 intel/isl: Allow CCS_E on more formats
Now that BLORP supports copies on everything except R11G11B10_FLOAT,
we should be able to support CCS_E those formats.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
2020-01-25 17:48:54 +00:00
Jason Ekstrand
f132e0fddf intel/blorp: Add support for CCS_E copies with UNORM formats
Some of the smaller bit-size formats which support CCS_E don't have a
UINT representative in their compression class.  However, we should be
able to use UNORM just fine and still get bit-exact copies.  We just
have to do a conversion to/from UNORM when we bitcast.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
2020-01-25 17:48:54 +00:00
Erico Nunes
ae0b8ba5d5 lima/ppir: fix src read mask swizzling
The src mask can't be calculated from the dest write_mask.
Instead, it must be calculated from the swizzled operators of the src.
Otherwise, liveness calculation may report incorrect live components for
non-ssa registers.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:55 +01:00
Erico Nunes
ab36523ae7 lima/ppir: split ppir_op_undef into undef and dummy again
Those were renamed/merged some time ago but it turns out that
ppir_op_undef can't be shared.
It was being used for undefined ssa operations and for read-before-write
operations that may happen to e.g. uninitialized registers (non-ssa)
inside a loop.
We really don't want to reserve a register for the undef ssa case, but
we must reserve and allocate register for the unitialized register case
because when it happens inside a loop it may need to hold its value
across iterations.

This dummy node might be eliminated with a code refactor in ppir in case
we are able to emit the write and allocate the ppir_reg before we emit
the read. But a major refactor we need this to keep this code to avoid
apparent regressions with the new liveness analysis implementation.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:55 +01:00
Erico Nunes
4ca3de06ec lima/ppir: fix ssa undef emit
The ssa doesn't need to be manually added to block->comp->reg_list.
Doing so actually causes other registers to be marked as undef=true
later.

This patch alone fixes a few deqp tests that have undefs.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:55 +01:00
Erico Nunes
d6b1917c01 lima/ppir: handle write to dead registers in ppir
nir can output writes to dead registers when expanding vec4 operations
to non-ssa registers. In that case, some components of the vec4 may be
assigned but never read. These are also not currently removed by a nir
dead code elimination pass as they are not ssa.
In order to prevent regalloc from allocating a live register for this
operation, an interference must be assigned to it during liveness
analysis.

This workaround may be removed in the future if the assignments to dead
components can be removed earlier in ppir or nir.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
2020-01-25 14:48:02 +01:00
Marek Olšák
eb7cd575da radeonsi: fix a regression since the addition of si_shader_llvm_vs.c
Fixes: cd5b99c541 - radeonsi: move VS shader code into si_shader_llvm_vs.c
Closes: #2416
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561>
2020-01-25 05:59:24 +00:00
Marek Olšák
688d2901b8 radeonsi: make screen available to shader part compilation
to fix a crash in is_multi_part_shader.

Fixes: 1a0890dcf3 - radeonsi: change prototypes of si_is_multi_part_shader & si_is_merged_shader
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561>
2020-01-25 05:59:24 +00:00
Jason Ekstrand
07a441d53f anv: Rework CCS memory handling on TGL-LP
The previous way we were attempting to handle AUX tables on TGL-LP was
very GL-like.  We used the same aux table management code that's shared
with iris and we updated the table on image create/destroy.  The problem
with this is that Vulkan allows multiple VkImage objects to be bound to
the same memory location simultaneously and the app can ping-pong back
and forth between them in the same command buffer.  Because the AUX
table contains format-specific data, we cannot support this ping-pong
behavior with only CPU updates of the AUX table.

The new mechanism switches things around a bit and instead makes the aux
data part of the BO.  At BO creation time, a bit of space is appended to
the end of the BO for AUX data and the AUX table is updated in bulk for
the entire BO.  The problem here, of course, is that we can't insert the
format-specific data into the AUX table at BO create time.

Fortunately, Vulkan has a requirement that every TILING_OPTIMAL image
must be initialized prior to use by transitioning the image from
VK_IMAGE_LAYOUT_UNDEFINED to something else.  When doing the above
described ping-pong behavior, the app has to do such an initialization
transition every time it corrupts the underlying memory of the VkImage
by using it as something else.  We can hook into this initialization and
use it to update the AUX-TT entries from the command streamer.  This way
the AUX table gets its format information, apps get aliasing support,
and everyone is happy.

One side-effect of this is that we disallow CCS on shared buffers.
We'll need to fix this for modifiers on the scanout path but that's a
task for another patch.  We should be able to do it with dedicated
allocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
b29cf7daf3 anv: Make anv_vma_alloc/free a lot dumber
All they do now is take a size, align, and flags and figure out which
heap to allocate in.  All of the actual code to deal with the BO is in
anv_allocator.c.  We want to leave anv_vma_alloc/free in anv_device.c
because it deals with API-exposed heaps so it still makes sense to have
it there.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
fd0f9d1196 anv: Make AUX table invalidate a PIPE_* bit
This commit moves it in with all the other cache invalidation operations
as if it were done by PIPE_CONTROL even though it's a pair of register
writes.  This means we only have to write the GFX_AUX_TABLE_BASE_ADDR
register once at device initialization instead of every invalidate.
Invalidates are now a single LRI instead of two.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
658dc9ca50 anv: Add another align_down helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
64ca8a3272 isl: Add a helper for calculating subimage memory ranges
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
4793116036 anv: Delete a redundant calculation
We compute the same thing with the same variable name at the top of the
function.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
a1e9adc9ce intel/aux-map: Factor out some useful helpers
This breaks add_mapping() into three pieces:

    1. get_aux_entry() adds AUX-TT pages as needed and returns the
       L1 entry index, L1 entry address, and L1 entry map.

    2. gen_aux_map_format_bits_for_isl_surf() computes the format-
       specific information that goes in the AUX-TT entry.

    3. add_mapping() is a lot dumber function that now just adds the
       requested mapping with the requested format bits.

This lets us break out some additional helpers in the API which we want
to use for more direct AUX-TT management in ANV.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Jason Ekstrand
bea62ea566 intel/aux-map: Add some #defines
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
2020-01-25 02:18:33 +00:00
Marek Olšák
0366c8c5b7 radeonsi: expose shader cache stats to the HUD
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Marek Olšák
c046551e60 radeonsi: print shader cache stats with AMD_DEBUG=cache_stats
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Marek Olšák
2fd3bb23ab radeonsi: restructure si_shader_cache_load_shader
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Marek Olšák
0db74f479b radeonsi: use the live shader cache
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Marek Olšák
4bb919b0b8 gallium/util: add a cache of live shaders for shader CSO deduplication
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Marek Olšák
f36f85d958 util/simple_mtx: add a missing include to get ASSERTED
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
2020-01-24 20:29:29 -05:00
Caio Marcelo de Oliveira Filho
6a0dda63dd intel/compiler: Add names for SHADER_OPCODE_[IU]SUB_SAT
Fixes: 58907568ec ("intel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-ops")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3558>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3558>
2020-01-24 23:52:30 +00:00
Caio Marcelo de Oliveira Filho
c1a2ac2abe anv: Always initialize target_stencil_layout
Pass down stencil data from the subpass attachment like we do
elsewhere.  Only stencil attachments will make use of it.

Fixes warnings like

    ../src/intel/vulkan/genX_cmd_buffer.c: In function ‘cmd_buffer_begin_subpass’:
    ../src/intel/vulkan/genX_cmd_buffer.c:4656:41: warning: ‘target_stencil_layout’ may be used uninitialized in this function [-Wmaybe-uninitialized]
     4656 |       att_state->current_stencil_layout = target_stencil_layout;
          |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3557>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3557>
2020-01-24 14:01:38 -08:00
Jason Ekstrand
41bffe0913 anv: Replace aux_surface.isl.size_B checks with aux_usage checks
Now that aux_usage has a unified meaning, aux_usage == NONE if and only
if aux_surface.isl.size_B > 0.  In most of these cases, the question
we're asking is "does have compression?" and not "have we allocated an
aux surface for compression?".

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3556>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3556>
2020-01-24 21:07:26 +00:00
Jason Ekstrand
e693a57232 anv: Rework the meaning of anv_image::planes[]::aux_usage
Previously, we set aux_usage=ISL_AUX_USAGE_NONE when we really meant
CCS_D.  This sort-of made sense before we had anv_layout_to_aux_usage
but now that we have that helper.  However, in our more modern aux
tracking model, all aux usage goes through anv_layout_to_* and we're
better off making the meaning of anv_image::planes[]::aux_usage be
AUX_USAGE_NONE if and only if there is no compression.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3556>
2020-01-24 21:07:26 +00:00
Samuel Pitoiset
de64719024 radv: print NIR shaders after lowering FS inputs/outputs
This is confusing otherwise.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3553>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3553>
2020-01-24 19:54:58 +00:00
Jason Ekstrand
17e225ee1e intel/isl: Add a hack for the Gen12 A0 texture buffer bug
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
2020-01-24 19:18:27 +00:00
Jason Ekstrand
4cd23420bd intel/isl: Plumb devinfo into isl_genX(buffer_fill_state_s)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
2020-01-24 19:18:27 +00:00
Jason Ekstrand
98aab272a8 intel/disasm: Properly disassemble indirect SENDs
Instead of emitting g[a0]UD for the indirect descriptor, emit a0<0>UD.
This is more correct because there is no GRF involved.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
2020-01-24 19:18:27 +00:00
Jason Ekstrand
3b2eafbea9 intel/fs: Don't unnecessarily fall back to indirect sends on Gen12
The instruction encoding for SENDS changed on Gen12 and it now supports
embedding the entire extended message descriptor in the instruction if
it's an immediate.  Stop falling back to doing an indirect SEND just
because we had something in [15:12] of ex_desc.ud.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
2020-01-24 19:18:27 +00:00
Jason Ekstrand
c70a786c77 anv: Improve BTI change cache flushing
This commit makes two changes:

 1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly
    for the flush at the end of cmd_buffer_begin_subpass.

 2. Because BLORP ops such as vkCmdClearAttachments may come in the
    middle of a render pass, we have to also flag the need for a cache
    flush after the blorp op.

Fixes: 185630c6bc "anv/blorp: Do the gen11 BTI flush"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
2020-01-24 19:18:26 +00:00
Alyssa Rosenzweig
e39c52787e panfrost: Fix 32-bit warning for indices
../src/gallium/drivers/panfrost/pan_context.c: In function ‘panfrost_draw_vbo’:
../src/gallium/drivers/panfrost/pan_context.c:1551:70: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
                 ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = (u64) NULL;
                                                                      ^

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Icecream95 <ixn@keemail.me>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
2020-01-24 18:53:31 +00:00
Alyssa Rosenzweig
58aa2b8cfc pan/decode: Remove SHORT_SLIDE indirection
../src/panfrost/pandecode/decode.c: In function ‘pandecode_compute_fbd’:
../src/panfrost/pandecode/decode.c:789:35: warning: taking address of packed member of ‘struct mali_compute_fbd’ may result in an unaligned pointer value [-Waddress-of-packed-member]
  789 |         pandecode_u32_slide(num, s->unknown ## num, ARRAY_SIZE(s->unknown ## num))
      |                                  ~^~~~~~~~~
../src/panfrost/pandecode/decode.c:800:9: note: in expansion of macro ‘SHORT_SLIDE’
  800 |         SHORT_SLIDE(1);
      |         ^~~~~~~~~~~

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
2020-01-24 18:53:31 +00:00
Alyssa Rosenzweig
7d52b3a18b pan/midgard: Remove pack_color define
Unused at the moment.

../src/panfrost/midgard/midgard_compile.c:124:29: warning: ‘m_pack_colour’ defined but not used [-Wunused-function]
  124 |  static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
      |                             ^~
../src/panfrost/midgard/midgard_compile.c:145:22: note: in expansion of macro ‘M_LOAD_STORE’
  145 | #define M_LOAD(name) M_LOAD_STORE(name, false)
      |                      ^~~~~~~~~~~~
../src/panfrost/midgard/midgard_compile.c:213:1: note: in expansion of macro ‘M_LOAD’
  213 | M_LOAD(pack_colour);
      | ^~~~~~

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
2020-01-24 18:53:31 +00:00
Alyssa Rosenzweig
6c95ea6bd7 pan/decode: Remove last_size
Fixes ../src/panfrost/pandecode/decode.c: In function ‘pandecode_jc’:
../src/panfrost/pandecode/decode.c:2859:14: warning: variable ‘last_size’ set but not used [-Wunused-but-set-variable]
 2859 |         bool last_size;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
2020-01-24 18:53:31 +00:00
Alyssa Rosenzweig
d126515a16 panfrost: Don't use implicit mali_exception_status enum
Fixes ../src/panfrost/pandecode/public.h:53:33: warning: ‘enum mali_exception_access’ declared inside parameter list will not be visible outside of this definition or declaration

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
2020-01-24 18:53:31 +00:00
Samuel Pitoiset
4a553212fa radv: enable ACO support for GFX6
CTS should pass, as well as Crucible and the few number of Piglit tests.

List of game benchmarks tested:
- Dawn of War 3
- Serious Sam 2017
- Shadow of The Tomb Raider
- The Talos Principle
- Thrones of Britannia
- Total Warhammer 2
- Total War: Three Kingdoms

Note that F12017 hangs with or without ACO on GFX6 at the moment.

My whole pipelinedb (~30 games) doesn't trigger any compiler crashes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2401
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
2020-01-24 18:34:27 +00:00
Samuel Pitoiset
d4b4f40595 aco: copy the literal offset of SMEM instructions to a temporary
GFX6 only supports up to 8-bit for the literal offset, so make sure
it's copied to a temporary SGPR before emitting a SMEM instruction.
The optimizer will propagate the literal offset if possible anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
2020-01-24 18:34:27 +00:00
Samuel Pitoiset
1ac49ba908 aco: fix a hazard with v_interp_* and v_{read,readfirst}lane_* on GFX6
It's required to insert 1 wait state if the dst VGPR of any v_interp_*
is followed by a read with v_readfirstlane or v_readlane to fix GPU
hangs on GFX6. Note that v_writelane_* is apparently not affected.
This hazard isn't documented anywhere but AMD confirmed it.

This fixes a GPU hang with the texturemipmapgen Sascha demo on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
2020-01-24 18:34:27 +00:00
Samuel Pitoiset
b9cc50fbce aco: fix a hardware bug for MRTZ exports on GFX6
GFX6 (except OLAND and HAINAN) has a bug that it only looks at
the X writemask component.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
2020-01-24 18:34:27 +00:00
Brian Ho
f55e215b8c turnip: Implement vkCmdCopyQueryPoolResults for occlusion queries
Use CP_COND_EXEC and CP_COND_WRITE to conditionally copy the results
of a query to a buffer based off the query's availability.

Fixes: #2238
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
9a3656b9fd turnip: Implement vkCmdResetQueryPool
Clears the available bit for each requested query on the GPU.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
97fa4cb3dc turnip: Implement vkGetQueryPoolResults for occlusion queries
Implements fetching the results of a query pool with the
VK_QUERY_RESULT_WAIT_BIT, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT,
and VK_QUERY_RESULT_PARTIAL_BIT flags.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
24b95485dc turnip: Update query availability on render pass end
Unlike on an immidiate-mode renderer, Turnip only renders tiles on
vkCmdEndRenderPass. As such, we need to track all queries that were
active in a given render pass and defer setting the available bit
on those queries until after all tiles have rendered.

This commit adds a draw_epilogue_cs to tu_cmd_buffer that is
executed as an IB at the end of tu_CmdEndRenderPass. We then emit
packets to this command stream that update the availability bit of a
given query in tu_CmdEndQuery.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
f750dd2ab8 turnip: Implement vkCmdEndQuery for occlusion queries
Mostly a translation of freedreno's implementation of glEndQuery for
GL_SAMPLES_PASSED query objects with a slight modification to set the
availability bit of the query bo (slot->available) if the query was
not ended inside a render pass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
5824a59ee2 turnip: Implement vkCmdBeginQuery for occlusion queries
Mostly a translation of freedreno's implementation of glBeginQuery for
GL_SAMPLES_PASSED query objects with special logic for handling tiled
render passes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
78dea40b1c turnip: Implement vkCreateQueryPool for occlusion queries
General structure is inspired by anv's implementation in genX_query.c.
We define a packed struct that tracks sample count at the beginning of
the query and at the end; the result of the occlusion query is then
slot->end - slot->begin.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Brian Ho
a155ab93a3 turnip: Update tu_query_pool with turnip-specific fields
tu_query_pool was forked from radv_query_pool, but we will need a
different set of fields to implement queries in turnip.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
2020-01-24 18:14:01 +00:00
Jason Ekstrand
0aa13245c1 anv: Allow HiZ in read-only depth layouts
This improves the performance of Aztec Ruins by 5% on ICL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
bf3a262a80 anv: Add a usage parameter to anv_layout_to_aux_usage
Most places we actually know the usage and can provide it.  There are
two exceptions to this:

 1. We pass 0 into get_blorp_surf_for_anv_image when we use
    ANV_IMAGE_LAYOUT_EXPLICIT_AUX because anv_layout_to_aux_usage is
    never actually called so it doesn't matter.

 2. We pass 0 into anv_layout_to_aux_usage in transition_color_buffer.
    However, the coming commits which will begin using the usage
    parameter only care about depth.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
f8a4de6316 anv: Use isl_aux_state for HiZ resolves
Rather than looking at the aux usage, we look at the isl_aux_state which
provides us with more detailed information.  This commit adds a couple
helpers to isl which let us quickly determine if we have valid depth/hiz
on the initial layout and if we need valid depth/hiz for the final
layout.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
9a1232a745 anv: Add a layout_to_aux_state helper
This new helper maps VkImageLayout enums to isl_aux_state enums which
are the hardware's concept of image layouts.  We can then use the aux
state to get the fast clear type and the aux usage.  This should yield
no functional change in driver behavior.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
769d6ba200 anv: Use TRANSFER_SRC_OPTIMAL for depth/stencil MSAA resolves
As of 52ad1712ed, TRANSFER_SRC_OPTIMAL and SHADER_READ_ONLY_OPTIMAL
are now identical for depth buffers so there's no reason why we need to
use the "wrong" layout.  Technically, according to Vulkan, blits and
MSAA resolves are transfer ops so we should use the transfer layout now
that we can.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
2020-01-24 17:42:36 +00:00
Jason Ekstrand
71c0f9e76d intel/blorp: resize src and dst surfaces separately
When copying to an RGB surface, we treat it as an R only one of three
times the width, which may end up being larger than the maximum size
supported by the hardware and so it hits the shrink path. This forced
both source and destination surfaces to be shrunk, even though it's not
necessary for the former, and may even hit some assertions in some
cases, such as the surface being compressed.

Fixes several tests under dEQP-VK.api.copy_and_blit.core.image_to_image.dimensions.*

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422>
2020-01-24 17:02:40 +00:00
Samuel Pitoiset
918f00eef8 aco: combine MRTZ (depth, stencil, sample mask) exports
Instead of emitting up to 3 for each different components (depth,
stencil and sample mask). This is needed to fix a hw bug on GFX6.

Totals from affected shaders:
SGPRS: 34728 -> 35056 (0.94 %)
VGPRS: 26440 -> 26476 (0.14 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1346088 -> 1344180 (-0.14 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 3922 -> 3915 (-0.18 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538>
2020-01-24 16:42:15 +00:00
Timur Kristóf
c787b8d2a1 aco/gfx10: Fix VcmpxExecWARHazard mitigation.
The SOPP instruction shouldn't have a definition, and its block
should be set to -1 in order to prevent it from being recognized
as a branch.
Also fix a typo in the readme.

Fixes: d6dfce02d0
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
2020-01-24 16:21:08 +00:00
Timur Kristóf
8a32f57fff aco: Transform uniform bitwise instructions to 32-bit if possible.
This allows removing superfluous s_cselect instructions
that come from turning booleans into 64-bit vector condition.

v2 by Daniel Schürmann:
- Make the code massively simpler
v3 by Timur Kristóf:
- Fix regressions, make it work in wave32 mode
- Eliminate extra moves by not always using the SCC definition
- Use s_absdiff_i32 for uniform XOR
- Skip the transformation for uncommon or invalid instructions

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450>
2020-01-24 14:40:45 +00:00
Martin Fuzzey
d1925fec53 etnaviv: update Android build files
etnaviv no longer builds on Android, fix this.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
2020-01-24 14:03:28 +00:00
Rhys Perry
b046f55086 aco: use nir_move_copies
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
72e9a23443 radv/aco: use ACO for GS copy shaders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
f8f7712666 aco: implement GS copy shaders
v5: rebase on float_controls changes
v7: rebase after shader args MR and load/store vectorizer MR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
de4ce66f5c aco: remove needs_instance_id
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
e192e268de aco: explicitly mark end blocks for exports
For GS copy shaders, whether we want to do exports is conditional. By
explicitly marking the end blocks, we can mark an IF's then branch as an
export block and ensure that's where the assembler inserts null exports.

v6: only fixup exports in the end block, like before
v8: simplify some code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
d46a54ecff radv/aco: allow ACO for GS
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
8bad100f83 aco: implement GS on GFX7-8
GS is the same on GFX6, but GFX6 isn't fully supported yet.

v4: fix regclass
v7: rebase after shader args MR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
40bb81c9dd radv/aco,aco: implement GS on GFX9+
v2: implement GFX10
v3: rebase
v7: rebase after shader args MR
v8: fix gs_vtx_offset usage on GFX9/GFX10
v8: use unreachable() instead of printing intrinsic
v8: rename output_state to ge_output_state
v8: fix formatting around nir_foreach_variable()
v8: rename some helpers in the scheduler
v8: rename p_memory_barrier_all to p_memory_barrier_common
v8: fix assertion comparing ctx.stage against vertex_geometry_gs

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
70f63c1988 aco: improve support for s_sendmsg
In particular, the messages needed for GS.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Rhys Perry
0da7b3b18b radv: move gs copy shader creation before other variants
ACO lowers output derefs which breaks the shader_info pass used by gs copy
shader creation.

v3: rebase

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
2020-01-24 13:35:07 +00:00
Timur Kristóf
23edcf6490 aco: Make a better guess at which instructions need the VCC hint.
Previously, bool_to_vector_condition would always set the VCC hint
on its result. This commit improves it by having the optimizer set
the VCC hint only when the result really needs to be in the VCC.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451>
2020-01-24 13:14:23 +00:00
Jan Zielinski
83f24b0587 gallium/swr: implementation of tessellation shaders compilation
TCS and TES shaders compilation mechanisms in SWR and state
management implementation.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
2020-01-24 11:38:03 +00:00
Bas Nieuwenhuizen
0890482969 radv: Allow DCC & TC-compat HTILE with VK_IMAGE_CREATE_EXTENDED_USAGE_BIT.
I misunderstood the flag when initially disabling. But this flag
only does something with mutable formats. If we have DCC and
mutable formats, the formats are close enough that the allowed
usage flags are not meaningfully different nor used during
allocation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424>
2020-01-24 11:16:39 +00:00
Bas Nieuwenhuizen
1b447bd2e6 radv: Expose VK_KHR_swapchain_mutable_format.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2354
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425>
2020-01-24 10:47:07 +00:00
Connor Abbott
b103157a0e freedreno: Document CP_INDIRECT_BUFFER_CHAIN
This will let us use batch chaining instead of growing batches on a5xx
and a6xx.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
2020-01-24 10:03:08 +00:00
Connor Abbott
f58242b56e freedreno: Document CP_UNK_A6XX_55
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
2020-01-24 10:03:08 +00:00
Connor Abbott
3cf1d6b8db freedreno: Document CP_COND_REG_EXEC more
The vulkan blob uses the RENDER_MODE mode to condition a blit on the
render mode in traces of a dEQP triangle test.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
2020-01-24 09:23:27 +00:00
Samuel Pitoiset
a31bcf2be6 ac/llvm: fix missing casts in ac_build_readlane()
Because ac_build_optimization_barrier() overwrites the original
src_type, we have to keep track of it before emitting that barrier.
Otherwise, wrong conversions are expected for pointers or small
bitsizes.

By doing this, we no longer need to do the cast dance in
ac_build_readlane_no_opt_barrier(), it was just necessary for
ac_build_optimization_barrier().

This fixes a bunch of crashes with subgroups related tests when
RADV_DEBUG=checkir is enabled, and it also fixes a compiler crash
with The Surge 2.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2395
Fixes: 0f45d4dc2b ("ac: add ac_build_readlane without optimization barrier")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535>
2020-01-24 07:40:07 +01:00
Jason Ekstrand
8a135ff6e5 anv/apply_pipeline_layout: Initialize the nir_builder before use
Fixes: #2410
Fixes: 3c754900b5 "nir: don't emit ishl in _nir_mul_imm() if backend doesn't support bitops"
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548>
2020-01-23 19:35:39 -08:00
Kenneth Graunke
adaa3583f5 meson: Prefer 'iris' by default over 'i965'.
This changes the default driver for Intel Gen8-11 hardware to be
the newer 'iris' driver rather than the older 'i965' driver.  To
continue using i965, pass -Dprefer-iris=false when building.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3540>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3540>
2020-01-23 15:34:54 -08:00
Adam Jackson
2fc11e8a05 drisw: Cache the depth of the X drawable
This is not always ->rgbBits, because there are cases where that could
be 32 but we're (legally) bound to a depth-24 pixmap. The important
thing to have match here is the actual server-side notion of depth.  You
can look this up (at modest expense) from the xlib visual info if the
fbconfig has a visual. But it might not, so if not, fetch it (at
slightly greater expense) from XGetGeometry. Do this at GLX drawable
creation so you don't have to do it on the SwapBuffers path.

Apparently this fixes glx/glx-swap-singlebuffer, which is unintentional
but quite pleasant.

Fixes: mesa/mesa#2291
Fixes: 90d58286 ("drisw: Fix and simplify drawable setup")
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3305>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3305>
2020-01-23 23:03:13 +00:00
Eric Anholt
59f29fc845 turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.
There are only a couple of hard cases left using pkt4, where the register
number to write is computed.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
d67100519e turnip: Convert renderpass setup to the new register packing macros.
This gets a lot of the hard code converted over to the new macros,
resulting in (I feel) much more readable code with
LESS_SHOUTING_ABOUT_THE_REG().  I decided to consistently put the reg on
its own line, so that all the register names line up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
08837ea3d2 turnip: Port krh's packing macros from freedreno to tu.
This introduces some minor unpacking of the temporary fd_reg_pair structs
to code that previously was packing a whole register field.

In the pack wrapper in tu_cs.h, I added some explanatory docs, dropped the
relocs handling since we don't need it, and removed the extra regs[] in
the __ONE_REG() macro (which was causing gcc's optimizer to fall on its
face in my release build).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
d4bc3c93ea freedreno: Fix OUT_REG() on address regs without a .bo supplied.
Sometimes you want to zero out an address by supplying a NULL BO, but
without this we would end up only emitting one dword.  Increases size of
fd6_gmem.o by .8%, though it's not clear to me why (no obvious terrible
codegen happening)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Eric Anholt
c1327bc283 freedreno: Add some missing a6xx address declarations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
2020-01-23 22:46:09 +00:00
Ian Romanick
4b7de92e5f relnotes: Add GL_INTEL_shader_integer_functions2 and VK_INTEL_shader_integer_functions2
Suggested-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-23 13:36:14 -08:00
Vasily Khoruzhick
beab31b9bb lima: use imul for calculations with intrinsic src
It's source is supposed to be int, so we have to use integer
multiplication otherwise we'll get undefined result.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
2020-01-23 21:16:22 +00:00
Vasily Khoruzhick
3c754900b5 nir: don't emit ishl in _nir_mul_imm() if backend doesn't support bitops
Otherwise we'll have to lower it later.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
2020-01-23 21:16:22 +00:00
Icecream95
cf2c5a56a1 pan/decode: Rotate trace files
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
c1952779d6 pan/decode: Dump to a file
The file name is taken from the environment variable
PANDECODE_DUMP_FILE, defaulting to pandecode.dump if it is not set.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
be22c0789f pan/decode: Support dumping to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
20a8957397 pan/bifrost: Support disassembling to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
968f36d1fc pan/midgard: Support disassembling to a file
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Icecream95
7b525ba02b pan/midgard: Fix a memory leak in the disassembler
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
2020-01-23 20:46:38 +00:00
Eric Anholt
fbd9b4ce08 turnip: Fix execution of secondary cmd bufs with nothing in primary.
We want to finish off cmd emission in the primary CS and add its entry to
the IB, but regardless of whether there had been anything in the primary
CS to emit, we still need a reserved CS entry for the loop below.

Fixes crashes in dEQP-VK.binding_model.shader_access.secondary_cmd_buf.*
and many more in dEQP-VK.renderpass*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3524>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3524>
2020-01-23 20:27:26 +00:00
Alyssa Rosenzweig
d6d6ef2862 panfrost: Drop mysterious zero=0xFFFF field
It doesn't seem to affect any results and it's not at all clear if/why
the blob sometimes(?) sets it? So let's clean this up since this
solution isn't correct anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513>
2020-01-23 19:59:58 +00:00
Icecream95
f8eb4441ae pan/midgard: Fix bundle dynarray leak
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3496>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3496>
2020-01-23 19:35:09 +00:00
Marek Olšák
43d9bac6f2 radeonsi: separate LLVM compilation from non-LLVM code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
1a0890dcf3 radeonsi: change prototypes of si_is_multi_part_shader & si_is_merged_shader
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
7ce84b256e radeonsi: make si_compile_shader return bool
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
be772182e0 radeonsi: make si_compile_llvm return bool
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
bd19d144a1 radeonsi: move more LLVM functions into si_shader_llvm.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
9a66f3d3e2 radeonsi: fold si_shader_context_set_ir into si_build_main_function
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
beacb414b9 radeonsi: move si_nir_build_llvm into si_shader_llvm.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
1c73d598eb radeonsi: minor cleanup in si_shader_internal.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
ab33ba987a radeonsi: move si_shader_llvm_build.c content into si_shader_llvm.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
cd5b99c541 radeonsi: move VS shader code into si_shader_llvm_vs.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
d1c42e2c6a radeonsi: move non-LLVM code out of si_shader_llvm.c
There was also some redundant code in si_shader_nir.c

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Marek Olšák
594f085cfa radeonsi: use ctx->ac. for types and integer constants
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
2020-01-23 19:10:21 +00:00
Jonathan Marek
8aa5d96864 turnip: simplify tu_physical_device_get_format_properties
Fixes the "bad VkImageTiling" error when tiling is
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3485>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3485>
2020-01-23 18:34:07 +00:00
Jonathan Marek
b7e22b7a35 vulkan/wsi: remove unused image_get_modifier
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3485>
2020-01-23 18:34:07 +00:00
Jonathan Marek
e8afd40758 turnip: set linear tiling for scanout images
Fixes: 210e6887 "vulkan/wsi: Use the interface from the real modifiers extension"

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3485>
2020-01-23 18:34:07 +00:00
Jonathan Marek
11f6fba1c9 turnip: hook up GetImageDrmFormatModifierPropertiesEXT
Fixes: 210e6887 "vulkan/wsi: Use the interface from the real modifiers extension"

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3485>
2020-01-23 18:34:07 +00:00
Guido Günther
c5334d2943 freedreno/drm: Don't miscalculate timeout
The current code overflows (s * 1000000000) for s >= 5 but that is
e.g. used in msm_bo_cpu_prep.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3514>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3514>
2020-01-23 18:07:13 +00:00
Eric Anholt
b327501dbf turnip: Add support for fine derivatives.
This does appear to be the required instruction sequence (dsxpp_1 dst src;
dsxpp_1.p dst src) as dropping either instruction fails the testsuite.

Fixes dEQP-VK.glsl.derivate.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3494>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3494>
2020-01-23 17:38:29 +00:00
Eric Anholt
876824908d freedreno/ir3: Plumb the ir3_shader_variant into legalize.
legalize is computing a lot of state that goes in the variant, let's just
store it directly instead of passing pointers around.  This leaves
max_bary in place, which is doing some surprising work (overwriting the
original total_in in some cases).

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3494>
2020-01-23 17:38:29 +00:00
Anthony Pesch
f77369086c util/hash_table: update users to use new optimal integer hash functions
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
2020-01-23 17:06:57 +00:00
Anthony Pesch
1496cc92f6 util/hash_table: added hash functions for integer types
A few hash_table users roll their own integer hash functions which
call _mesa_hash_data to perform the hashing which ultimately calls
into XXH32 with a dynamic key length. When using small keys with a
constant size the hash rate can be greatly improved by inlining
XXH32 and providing it a constant key length, see:
https://fastcompression.blogspot.com/2018/03/xxhash-for-small-keys-impressive-power.html

Additionally, this patch removes calls to _mesa_key_hash_string and
makes them instead call _mesa_has_string directly, matching the new
integer hash functions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
2020-01-23 17:06:57 +00:00
Anthony Pesch
931388ceca util/hash_table: replace _mesa_hash_data's fnv1a hash function with xxhash
For most key sizes, xxhash outperforms fnv1a's hash rate substantially (bug
2153). In particular, the V3D driver hashes multiple ~200 byte keys as part
of the shader cache lookup which can easily eat up 10-20% of the runtime on
the Raspberry Pi. Swapping over to xxhash drops this to ~1% of the runtime.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
2020-01-23 17:06:57 +00:00
Anthony Pesch
032f8807f7 util: move fnv1a hash implementation into its own header
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
2020-01-23 17:06:57 +00:00
Anthony Pesch
17fac0e32d util: import xxhash
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3475>
2020-01-23 17:06:57 +00:00
Michel Dänzer
552028c013 winsys/amdgpu: Close KMS handles for other DRM file descriptions
When a BO or amdgpu_screen_winsys is destroyed.

Should fix leaking such BOs in other DRM file descriptions.

v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
  Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3a "winsys/amdgpu: Make KMS handles valid for original
                     DRM file descriptor"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:39:34 +01:00
Michel Dänzer
b60f5cbc15 winsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.

v2:
* Adapt to amdgpu_winsys::sws_list_lock.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:39:34 +01:00
Michel Dänzer
f76cbc7901 util: Add os_same_file_description helper
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:39:34 +01:00
Michel Dänzer
c6468f66c7 winsys/amdgpu: Only re-export KMS handles for different DRM FDs
When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys
(which is always the case for the first amdgpu_screen_winsys), we can
just use bo->u.real.kms_handle.

v2:
* Also only create the kms_handles hash table if the
  amdgpu_screen_winsys fd is different from the amdgpu_winsys one.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:39:34 +01:00
Michel Dänzer
24075ac60f winsys/amdgpu: Keep track of retrieved KMS handles using hash tables
The assumption being that KMS handles are only retrieved for relatively
few BOs, so hash tables should be efficient both in terms of performance
and memory consumption.

We use the address of struct amdgpu_winsys_bo as the key and its
kms_handle field (the KMS handle valid for the DRM file descriptor
passed to amdgpu_device_initialize) as the hash value.

v2:
* Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric
  Pelloux-Prayer)
v3:
* Protect kms_handles hash table with amdgpu_winsys::sws_list_lock
  mutex.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:24:00 +01:00
Michel Dänzer
f4010a6da9 winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsys
v2:
* Add dedicated mutex for the list.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3202>
2020-01-23 17:23:32 +01:00
Samuel Pitoiset
8d5203dad2 aco: implement nir_op_f2i64/nir_op_f2u64 on GFX6
V_TRUNC_F64 and V_FLOOR_F64 needs to be lowered on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:48 +01:00
Samuel Pitoiset
4d92601715 aco: implement 64-bit nir_op_ffloor on GFX6
GFX6 doesn't have V_FLOOR_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Introduce a new function because it will be useful for some other
64-bit operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:45 +01:00
Samuel Pitoiset
fbd169e421 aco: implement 64-bit nir_op_fround_even on GFX6
GFX6 doesn't have V_RNDNE_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:42 +01:00
Samuel Pitoiset
87588801d3 aco: implement 64-bit nir_op_fceil on GFX6
GFX6 doesn't have V_CEIL_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:38 +01:00
Samuel Pitoiset
aad5176c58 aco: implement 64-bit nir_op_ftrunc on GFX6
GFX6 doesn't have V_TRUNC_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Introduce a new function because it will be useful for some other
64-bit operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:34 +01:00
Samuel Pitoiset
36e7a5f5b9 aco: implement nir_intrinsic_global_atomic_* on GFX6
GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:30 +01:00
Samuel Pitoiset
22d8822683 aco: implement nir_intrinsic_load_global on GFX6
GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:27 +01:00
Samuel Pitoiset
d6af7571c2 aco: implement nir_intrinsic_store_global on GFX6
GFX6 doesn't have FLAT instructions, use MUBUF instructions instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:24 +01:00
Samuel Pitoiset
01f0bef71e aco: fix wrong IR in nir_intrinsic_load_barycentric_at_sample
Only GFX6 was affected, my mistake. The total number of SGPR operands
should be 4 when we want to create a vec4.

Fixes: dbdf3b3ef9 ("aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
2020-01-23 14:40:21 +01:00
Lionel Landwerlin
d101907de9 anv/iris: warn gen12 3DSTATE_HS restriction
This should never happen but better off documenting it in case someone
plays with max threads numbers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3489>
2020-01-23 15:06:59 +02:00
Krzysztof Raszkowski
bf74a7f092 gallium/swr: add option for static link
Set swr-shared to 'false' to link SWR statically into Mesa.
Only one swr arch can be specified if swr-shared is set to false.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3510>
2020-01-23 12:20:24 +00:00
Samuel Pitoiset
54e54ec3e8 aco: fix printing assembly with CLRXdisasm on GFX6
We thought that CLRXdisasm allowed gfx600 as well as gfx700 but
it actually doesn't. Use the family for GFX6 chips instead.

Fixes: 0099f85232 ("aco: print assembly with CLRXdisasm for GFX6-GFX7 if found on the system")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3531>
2020-01-23 11:34:37 +00:00
Pierre Moreau
dda542e912 clover/meson: Define OpenCL header macros
Rather than defining the macros any time right before including an
OpenCL header, set Meson to define them for the whole clover project.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
2020-01-23 11:12:33 +00:00
Pierre Moreau
dd756b704f clover: Use the dispatch table type from the OpenCL headers
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2243

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
2020-01-23 11:12:33 +00:00
Pierre Moreau
cd1c661cfc include/CL: Update OpenCL headers to latest
This latest update contains a new header that defines the dispatch table
structure in order to avoid OpenCL implementations having to define it
themselves.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3137>
2020-01-23 11:12:33 +00:00
Samuel Pitoiset
12fe19ba3b radv: advertise VK_AMD_shader_fragment_mask
Only for GFX8+ because it's untested on older generations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
e030aef32c aco: add support for nir_texop_fragment_{mask}_fetch
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
9e477d79b7 ac/nir: add support for nir_texop_fragment_{mask}_fetch
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
84b08971fb nir/lower_input_attachments: lower nir_texop_fragment_{mask}_fetch
These instructions are allowed to fetch from multisampled
subpass input attachments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
76a34f5d3f spirv: add support for SpvOpFragment{Mask}FetchAMD operations
nir_tex_src_ms_index is re-used for the fragment index with
nir_texop_fragment_fetch to avoid introducing a new texture source type.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
603e6ba972 nir: add two new texture ops for multisample fragment color/mask fetches
This introduces:
   - nir_texop_fragment_mask_fetch (fetch a fragment mask from a
     compressed multisampled color surface)
   - nir_texop_fragment_fetch (fetch a color fragment for a
     particular sample at corresponding fragment mask index).

These two texture operations are necessary for implementing
SPV_AMD_shader_fragment_mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
dea29b3818 spirv: add SpvCapabilityFragmentMaskAMD
This new capability is for SPV_AMD_shader_fragment_mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3304>
2020-01-23 10:48:02 +00:00
Samuel Pitoiset
e60de08547 radv: handle missing implicit subpass dependencies
When a subpass doesn't declare an explicit dependency from/to
VK_SUBPASS_EXTERNAL, Vulkan says there is an implicit dependency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
2020-01-23 11:25:41 +01:00
Samuel Pitoiset
0d2da2a8c0 radv: add explicit external subpass dependencies to meta operations
No functional changes because a subpass dependency with dstStageMask
set to VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT is a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3330>
2020-01-23 11:25:38 +01:00
Dave Airlie
48ab21109c gallivm: fix find lsb
the GLSL return value is different than the llvm intrinsic.

Fixes arb gpu shader5 tests

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
2020-01-23 13:48:16 +10:00
Dave Airlie
1e433c398e galllivm: fix gather offset casting
cast texture offsets to 32-bit integers

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
2020-01-23 13:48:16 +10:00
Dave Airlie
fc9d67394d llvmpipe: fix some integer instruction lowering.
We want to lower to shifts for bitfields, and lower ifind_msb.

Fixes a bunch of gpu shader5 tests.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
2020-01-23 13:48:16 +10:00
Dave Airlie
6c88c81df9 gallivm: fix gather component handling.
Fixes the extended gather test for gpu shader5

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3528>
2020-01-23 13:48:16 +10:00
Eric Anholt
65e432695d turnip: Add support for uniform texel buffers.
Pretty straightforward: Port texture descriptor code from freedreno, fill
in alignment limits from closed vk, and tu_cmd_buffer.c was already
uploading the texture descriptor.

This doesn't implement storage texel buffers (required in the compute
pipeline) yet, since those will need an IBO descriptor for the store path.
Still, making the load path be connected to the texture descriptor won't
hurt.

Part of #2237

Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_texel_buffer.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3522>
2020-01-23 02:40:09 +00:00
Kenneth Graunke
8dc0540a17 intel: Fix aux map alignments on 32-bit builds.
ALIGN() brilliantly uses uintptr_t, making it unsafe for use with 64-bit
GPU addresses in 32-bit builds of the driver.  Use align64() instead,
which uses uint64_t.

Fixes assertion failures when running any 32-bit program on Tigerlake.

Fixes: 2e6a7ced4d ("iris/gen12: Write GFX_AUX_TABLE base address register")
Fixes: 0d0290bb3f ("intel/common: Add surface to aux map translation table support")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
2020-01-23 02:16:50 +00:00
Matt Turner
4413537c80 util: Remove tmp argument from BITSET_FOREACH_SET macro
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
2020-01-23 01:52:43 +00:00
Matt Turner
d3eb2a0951 util: Explain BITSET_FOREACH_SET params
__size, in particular, makes this macro rather confusing to understand
how to use. Hopefully this comment saves future users the headache.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
2020-01-23 01:52:42 +00:00
Vasily Khoruzhick
60f9b45802 lima: implement invalidate_resource()
We don't need to resolve invalidated resources, so it should
improve performance for applications that are doing this hint.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3476>
2020-01-23 01:26:23 +00:00
Timothy Arceri
bf830250a7 glsl_to_nir: update interface type properly
Since 76ba225184 the member variable types were being redefined
but we assigned the old interface type to the variable.

In a following patch series we will use the types to check if we
are dealing with an interface instance when apply GLSL linking
rules.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
2020-01-23 01:02:25 +00:00
Timothy Arceri
d3a4d1775e glsl: count uniform components and storage better in nir linking
This helps avoid incorrect validation error when linking glsl
shaders and avoids assigning uniform storage slots that will
never be used.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
2020-01-23 01:02:25 +00:00
Timothy Arceri
e5b3cf433e glsl: fix check for matrices in blocks when using nir uniform linker
We need to stripe any arrays before checking the type. Here we
just use the uniform type which has already be stripped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
2020-01-23 01:02:25 +00:00
Timothy Arceri
55e4410b34 glsl: remove bogus assert in nir uniform linking
I'm not sure why this was first added but it causes an assert
on any uniform matrix.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3468>
2020-01-23 01:02:25 +00:00
Ian Romanick
b065d8fb8c nir/algebraic: Optimize some 64-bit integer comparisons involving zero
I noticed that we can do better for these kinds of comparisons while
working on the lowering for iadd_sat@64 and isub_sat@64.  This
eliminated 11 instruction from the fs-addSaturate-int64.shader_test.

My hope is that this will improve the run-time of int64 tests on Ice
Lake.  I have no data to support or refute this.

Unsurprisingly, no changes on shader-db.

v2: Condition the min and max patterns with nir_lower_minmax64.
Suggested by Caio.  Very long discussion in the MR. :)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
c57338b924 anv: Enable SPV_INTEL_shader_integer_functions2 and VK_INTEL_shader_integer_functions2
Currently only implemented in the scalar backend, so only enable for
Gen8+.  If support for the other opcodes is added to the vec4 backend,
Gen7 could be supported.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
76970940a6 iris: Enable INTEL_shader_integer_functions2
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
b14e718e68 gallium: Add a cap bit for integer multiplication between 32-bit and 16-bit
Driver supports integer multiplication between a 32-bit integer and a
16-bit integer.  If the second operand is 32-bits, the upper 16-bits are
ignored, and the low 16-bits are possibly sign extended as necessary.

Iris will eventually enable this.  Not sure about other drivers.

v2: Add default value to u_screen.c.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
9db20748fd gallium: Add a cap bit for OpenCL-style extended integer functions
Iris will eventually enable this.  Looking at the header files, it looks
like Midgard could also enable it.  Basically, any GPU that fully
supports OpenCL can.

v2: Add default value to u_screen.c.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
4e9079d0c7 i965: Enable INTEL_shader_integer_functions2 on Gen8+
v2: Use new lower_hadd64 and lower_usub_sat64 flags.

v3: Enable SPIR-V capability.

v4: Move lowering options to COMMON_SCALAR_OPTIONS.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
4fcddb55f2 spirv: Add support for IntegerFunctions2INTEL capability
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
aa56934e2a spirv: Silence a bunch of unused parameter warnings
The change to get_uniform_nir_atomic_op make it look like the other
get_*_nir_atomic_op functions.  The rest just add UNUSED or ASSERTED
to parameters required for some of the interfaces.

src/compiler/spirv/spirv_to_nir.c: In function ‘struct_member_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:673:47: warning: unused parameter ‘val’ [-Wunused-parameter]
                             struct vtn_value *val, int member,
                                               ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘struct_member_matrix_stride_cb’:
src/compiler/spirv/spirv_to_nir.c:778:50: warning: unused parameter ‘val’ [-Wunused-parameter]
                                struct vtn_value *val, int member,
                                                  ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘type_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:805:61: warning: unused parameter ‘ctx’ [-Wunused-parameter]
                     const struct vtn_decoration *dec, void *ctx)
                                                             ^~~
src/compiler/spirv/spirv_to_nir.c: In function ‘spec_constant_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:1359:70: warning: unused parameter ‘v’ [-Wunused-parameter]
 spec_constant_decoration_cb(struct vtn_builder *b, struct vtn_value *v,
                                                                      ^
src/compiler/spirv/spirv_to_nir.c: In function ‘handle_workgroup_size_decoration_cb’:
src/compiler/spirv/spirv_to_nir.c:1407:43: warning: unused parameter ‘data’ [-Wunused-parameter]
                                     void *data)
                                           ^~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_function_call’:
src/compiler/spirv/spirv_to_nir.c:1806:55: warning: unused parameter ‘opcode’ [-Wunused-parameter]
 vtn_handle_function_call(struct vtn_builder *b, SpvOp opcode,
                                                       ^~~~~~
src/compiler/spirv/spirv_to_nir.c:1807:54: warning: unused parameter ‘count’ [-Wunused-parameter]
                          const uint32_t *w, unsigned count)
                                                      ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘get_uniform_nir_atomic_op’:
src/compiler/spirv/spirv_to_nir.c:2548:47: warning: unused parameter ‘b’ [-Wunused-parameter]
 get_uniform_nir_atomic_op(struct vtn_builder *b, SpvOp opcode)
                                               ^
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_atomics’:
src/compiler/spirv/spirv_to_nir.c:2633:48: warning: unused parameter ‘count’ [-Wunused-parameter]
                    const uint32_t *w, unsigned count)
                                                ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_barrier’:
src/compiler/spirv/spirv_to_nir.c:3197:48: warning: unused parameter ‘count’ [-Wunused-parameter]
                    const uint32_t *w, unsigned count)
                                                ^~~~~
src/compiler/spirv/spirv_to_nir.c: In function ‘vtn_handle_execution_mode’:
src/compiler/spirv/spirv_to_nir.c:3618:68: warning: unused parameter ‘data’ [-Wunused-parameter]
                           const struct vtn_decoration *mode, void *data)
                                                                    ^~~~

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
44471a76e9 nir/spirv: Translate SPIR-V to NIR for new INTEL_shader_integer_functions2 opcodes
v2: Rebase on 272e927d0e ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add missing SpvOpUCountTrailingZerosINTEL case to switch in
vtn_handle_body_instruction. Remove stray semicolon in
vtn_nir_alu_op_for_spirv_opcode. Use umin instead of umax for
SpvOpUCountTrailingZerosINTEL "lowering" in vtn_handle_alu.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
de6c0f8487 intel/fs: Implement support for NIR opcodes for INTEL_shader_integer_functions2
v2: Remove smashing type to D for nir_op_irhadd.  Caio noticed it was
odd, and removing it fixes an assertion failure in the crucible
func.shader.averageRounded.int64_t test (because the source should be
W).

v3: Emit BRW_OPCODE_MUL directly for nir_op_umul_32x16 and
nir_op_imul_32x16.  Suggested by Curro.

v4: Smash types of MUL instruction generated for nir_op_umul_32x16 and
nir_op_imul_32x16.  With this change, I get the same assembly now as I
did with v2.

v5: Remove support for pre-Gen7.  The integer multiply path was
incorrect, and, since the extension isn't enabled pre-Gen7, there's no
way to test it.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
58907568ec intel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-ops
v2: Add a big comment explaining the [IU]SUB_SAT lowering.  Suggested by
Caio.

v3: Use get_fpu_lowered_simd_width in get_lowered_simd_width.  Suggested
by Ken on IRC.

v4: Fix a typo in a comment.  Noticed by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
74cd0964d6 intel/fs: Don't lower integer multiplies that don't need lowering
v2: Move the check to fs_visitor::lower_integer_multiplication.
Previously the cases where lowering was skipped, the original
instruction was removed by fs_visitor::lower_integer_multiplication.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
db649fd582 compiler: Translate GLSL IR to NIR for new INTEL_shader_integer_functions2 expressions
v2: Rebase on 272e927d0e ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
d3d970166c nir/algebraic: Add lowering for 64-bit iadd_sat and isub_sat
v2: Rearranged and expand the comment about the optimizations applied to
the lowering.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
dcadbd2dd2 nir/algebraic: Add lowering for 64-bit uadd_sat
Fixes piglit fs-addsaturate-uint64 and vs-addsaturate-uint64 on Ice
Lake.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
1bdfc6d7cb nir/algebraic: Add lowering for 64-bit usub_sat
v2: Rebase on 272e927d0e ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add a new lower_usub_sat64 flag that only applies to the 64-bit
version of the nir_op_usub_sat instruction.

v4: Also enable the lowering when nir_lower_iadd64 is set.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
a483771045 nir/algebraic: Add lowering for 64-bit hadd and rhadd
v2: Rebase on 272e927d0e ("nir/spirv: initial handling of OpenCL.std
extension opcodes")

v3: Add a new lower_hadd64 flag that only applies to the 64-bit versions
of the instructions.

v4: Also enable the lowering when nir_lower_iadd64 is set.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
ea435560ee nir/algebraic: Add lowering for uabs_usub and uabs_isub
v2: Remove some rebase failures noticed by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
21f0d020fe nir: Add new instructions for INTEL_shader_integer_functions2
uctz isn't added because it will implemented in the GLSL path and the
SPIR-V path using other pre-existing instructions.

v2: Avoid signed integer overflow for uabs_isub(0, INT_MIN).  Noticed by
Caio.

v3: Alternate fix for signed integer overflow for abs_sub(0, INT_MIN).
I tried the previous methon in a small test program with -ftrapv, and it
failed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
cb518df775 glsl: Add built-in functions for INTEL_shader_integer_functions2
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
5eda9f5832 glsl_types: Add function to get an unsigned base type from a signed type
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
1d165b0548 glsl: Add new expressions for INTEL_shader_integer_functions2
v2: Re-write iadd64_saturate and isub64_saturate to avoid undefined
overflow behavior.  Also fix copy-and-paste bug in isub64_saturate.
Suggested by Caio.

v3: Avoid signed integer overflow for abs_sub(0, INT_MIN).  Noticed by
Caio.

v4: Alternate fix for signed integer overflow for abs_sub(0, INT_MIN).
I tried the previous methon in a small test program with -ftrapv, and it
failed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Ian Romanick
20d34c4ebf mesa: Extension boilerplate for INTEL_shader_integer_functions2
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
2020-01-23 00:18:57 +00:00
Matt Turner
88a0523bd2 intel/compiler: Move Gen4/5 rounding to visitor
Gen4/5's rounding instructions operate differently than later Gens'.
They all return the floor of the input and the "Round-increment"
conditional modifier answers whether the result should be incremented by
1.0 to get the appropriate result for the operation (and thus its
behavior is determined by the round opcode; e.g., RNDZ vs RNDE).

Since this requires a second instruciton (a predicated ADD) that
consumes the result of the round instruction, the round instruction
cannot write its result directly to the (write-only) message registers.
By emitting the ADD in the generator, the backend thinks it's safe to
store the round's result directly to the message register file.

To avoid this, we move the emission of the ADD instruction to the NIR
translator so that the backend has the information it needs.

I suspect this also fixes code generated for RNDZ.SAT but since
Gen4/5 don't support GLSL 1.30 which adds the trunc() function, I
couldn't write a piglit test to confirm. My thinking is that if x=-0.5:

      sat(trunc(-0.5)) = 0.0

But on Gen4/5 where sat(trunc(x)) is implemented as

      rndz.r.f0  result, x             // result = floor(x)
                                       // set f0 if increment needed
      (+f0) add  result, result, 1.0   // fixup so result = trunc(x)

then putting saturate on both instructions will give the wrong result.

      floor(-0.5) = -1.0
      sat(floor(-0.5)) = 0.0
      // +1 increment would be needed since floor(-0.5) != trunc(-0.5)
      sat(sat(floor(-0.5)) + 1.0) = 1.0

Fixes: 6f394343b1 ("nir/algebraic: i2f(f2i()) -> trunc()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2355
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3459>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3459>
2020-01-22 23:47:02 +00:00
Samuel Thibault
2fd85105c6 meson: Do not require libdrm for DRI2 on hurd
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3231>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3231>
2020-01-22 23:15:05 +00:00
Samuel Thibault
4f52425159 util: Do not fail to build on unknown pthread_setname_np
This is only used for debugging, so better making porting on various systems
less hard.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3229>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3229>
2020-01-22 22:39:57 +00:00
Samuel Thibault
e45dc93136 loader: #define PATH_MAX when undefined (eg. Hurd)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3228>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3228>
2020-01-22 22:10:29 +00:00
Eric Engestrom
d60b8fd3cb util/atomic: fix return type of p_atomic_add_return() fallback
Fixes: 385d13f26d ("util/atomic: Add a _return variant of p_atomic_add")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3012>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3012>
2020-01-22 21:42:52 +00:00
James Xiong
ac0219cc5b gallium: dmabuf support for yuv formats that are not natively supported
V2 (Kenneth Graunke):
   added a helper function to check if every format is supported

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2846>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2846>
2020-01-22 21:18:49 +00:00
Emmanuel Gil Peyrot
5f78524d9b intel/compiler: Return early if read() failed
This was the only warning I could see while compiling Iris.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2821>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2821>
2020-01-22 20:52:47 +00:00
Alan Coopersmith
8490b7d917 intel/perf: adapt to platforms like Solaris without d_type in struct dirent
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
[Eric: factor out the is_dir_or_link() check and fix a bug in v1]
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
v3: include directory path when lstat'ing files
v4: fix inverted check in enumerate_sysfs_metrics()

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2258>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2258>
2020-01-22 20:23:51 +00:00
Eric Engestrom
8f140422ed llvmpipe: drop LLVM < 3.4 support
We don't support < 3.9 anymore, so this code is dead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2760>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2760>
2020-01-22 11:21:13 -08:00
Eric Engestrom
7d7d1da1ac egl: drop confusing mincore() error message
A user came to me asking how to fix this error, but it's entirely
expected that `get_wl_surface_proxy()` on recent enough wayland
compositors will always print it.
Let's just remove the message altogether, it is basically never useful.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3219>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3219>
2020-01-22 17:55:26 +00:00
Rhys Perry
15a1cc00d3 aco: fix off-by-one error when initializing sgpr_live_in
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2394
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3511>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3511>
2020-01-22 17:23:30 +00:00
Samuel Pitoiset
bd51538d28 radv: fix double free corruption in radv_alloc_memory()
If the driver fails to allocate memory for some reasons, it shouldn't
free the 'mem' object twice.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2302
Fixes: 825ddfee59 ("radv: Handle device memory alloc failure with normal free.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3508>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3508>
2020-01-22 17:01:16 +00:00
Michel Dänzer
5a6a88f58c gitlab-ci: Use single if for manual job rules entry
I thought multiple ifs would all need to match, but looks like only the
last one (or either one?) does.

This should prevent a manual pipeline from getting created after merging
changes which can't affect the pipeline.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>
2020-01-22 16:42:11 +00:00
Michel Dänzer
2dd0cc60f1 gitlab-ci: Set GIT_STRATEGY to none for the dummy job
It doesn't need anything from the Git repository.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3474>
2020-01-22 16:42:11 +00:00
X512
eb40c0adfc util/u_thread: Fix build under Haiku 2020-01-22 16:21:54 +00:00
Alexander von Gluck IV
49d2a066c2 haiku/hgl: Fix build via header reordering 2020-01-22 16:21:54 +00:00
Rhys Perry
3f96a1ed86 aco: fix operand kill flags when a temporary is used more than once
Helps create v_mac_f32 from v_mad_f32(b, a, b)

Totals from affected shaders:
SGPRS: 35824 -> 35824 (0.00 %)
VGPRS: 33460 -> 33456 (-0.01 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 2187264 -> 2180976 (-0.29 %) bytes
LDS: 127 -> 127 (0.00 %) blocks
Max Waves: 3802 -> 3802 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3486>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3486>
2020-01-22 15:55:00 +00:00
Boris Brezillon
5b810c7de3 panfrost/midgard: Add missing lowering passes for type/size conversion ops
Replace the manual type/size conversion lowering description by one
that's automatically generated and covers all type/size conversions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
fcceeaffae panfrost/midgard: Add 64 bits float <-> int converters
The 64 bit converter cases were missing, add them now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
fe5fbadd46 panfrost/midgard: Fix mir_print_instruction() for branch instructions
Branch instructions should not be treated as regular ALUs.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
e1f9e8d60b panfrost/midgard: Add f2f64 support
So we can convert floats into doubles.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
f53a0799c7 panfrost/midgard: Factorize f2f and u2u handling
Those size conversion operations work the same way apart from f2f
using an fmov op code and u2u using an imov. Let's handle them in the
same case block to avoid code duplication.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
6548d01b3d panfrost/midgard: Make sure promote_fmov() only promotes 32-bit imovs
mir_constant_float() assumes we're dealing with 32-bit integers/floats,
which is only the case if reg_mode is equal to midgard_reg_mode_32.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
9566f26ed4 panfrost/midgard: Rework mir_adjust_constants() to make it type/size agnostic
Right now, constant combining is not supported in 16 bit mode, and 64
bit mode is simply ignored. Let's rework the function to make it
type/bit-size agnostic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Boris Brezillon
15c92d158c panfrost/midgard: Use a union to manipulate embedded constants
Each instruction bundle can contain up to 16 constant bytes. The meaning
of those byte is instruction dependent: it depends on the instruction
native type (int, uint or float) and the instruction reg_mode (8, 16, 32
or 64 bit). Those different layouts can be exposed as a union to
facilitate constants manipulation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
2020-01-22 15:31:28 +00:00
Lionel Landwerlin
63461cb7e1 anv: ensure prog params are initialized with 0s
As a result of 9baa33cef0 our backend compiler leaves params pretty
much untouched. So in order to avoid storing uninitialized values in
the shader cache blobs, just 0 out this array.

I've considered not even allocating this array which works on gen8+
but the vec4 backend still makes a copy of this array and so it
crashes on memcpy on HSW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9baa33cef0 ("anv: Rework push constant handling")
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3516>
2020-01-22 16:47:55 +02:00
Alyssa Rosenzweig
4936120230 panfrost: Fix crash in compute variant allocation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: d8a3501f1b ("panfrost: Dynamically allocate shader variants")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3515>
2020-01-22 13:48:24 +00:00
Guido Günther
d817f2c696 etnaviv: drm: Don't miscalculate timeout
The current code overflows (s * 1000000000) for s >= 5 but that is
e.g. used in etna_bo_cpu_prep.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3509>
2020-01-22 13:22:47 +00:00
Alexander van der Grinten
047162d99c egl: Fix _eglPointerIsDereferencable w/o mincore()
On platforms without mincore(), _eglPointerIsDereferencable()
currently just checks whether p != NULL. This is not sufficient:
In the Wayland platform code (i.e., in get_wl_surface_proxy()),
_eglPointerIsDereferencable() is called on the version field
of `struct wl_egl_window` which is 3 on current versions of
Wayland. This causes a segfault when trying to dereference p.

Fix this behavior by assuming that the first page of the
process is never dereferencable.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3103>
2020-01-22 12:55:05 +00:00
Tapani Pälli
39e7492d33 egl/android: fix buffer_count for applications setting max count
Problem with previous solution was that it did not take account that
some applications may set a max count for buffers. Therefore we need to
query both min and max and clamp our setting based on that.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2373
Fixes: be08e6a449 ("egl/android: Restrict minimum triple buffering for android color_buffers")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3480>
2020-01-22 10:37:04 +00:00
Timur Kristóf
1c9ecb2123 aco: Fix signedness compare warning.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
2020-01-22 11:09:17 +01:00
Timur Kristóf
533a20dbd5 aco: Fix maybe-uninitialized warnings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
2020-01-22 11:09:14 +01:00
Timur Kristóf
6fb3df2786 aco: Fix -Wstringop-overflow warnings in aco_span.
GCC does not understand how aco_span works.
This patch fixes it by casting the aco_span's this pointer
to uintptr_t rather than to a char pointer, effectively
telling GCC not to try to figure it out.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3483>
2020-01-22 11:09:10 +01:00
Timur Kristóf
75e5720e1a radeon: Fix multiple definition error with radeon_debug
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
2020-01-22 09:36:28 +01:00
Timur Kristóf
8e22df3aec gallium: Fix a couple of multiple definition warnings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
2020-01-22 09:36:25 +01:00
Timur Kristóf
a134ac5ee9 r600: Move get_pic_param to radeon_vce.c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
2020-01-22 09:36:23 +01:00
Timur Kristóf
b7f9759809 radeon: Move si_get_pic_param to radeon_vce.c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3488>
2020-01-22 09:36:16 +01:00
Timur Kristóf
e45ea781f8 intel/compiler: Fix array bounds warning on GCC 10.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-22 08:35:18 +01:00
Eric Anholt
3abfde13be turnip: Add support for non-zero (still constant) UBO buffer indices.
This was actually all ready to go at this point, and just needed to
increment by the value.

Fixes dEQP-VK.binding_model.shader_access.primary_cmd_buf.uniform_buffer.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3504>
2020-01-22 02:13:38 +00:00
Jonathan Marek
5f791df0d0 turnip: fix array/matrix varyings
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
2020-01-21 20:36:08 -05:00
Jonathan Marek
c171765223 turnip: remove tu_sort_variables_by_location
nir_assign_io_var_locations already does sorting.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
2020-01-21 20:36:08 -05:00
Jonathan Marek
1736447f27 freedreno/ir3: allow inputs with the same location
turnip can have multiple inputs with the same location, and different
location_frac.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3109>
2020-01-21 20:36:08 -05:00
Matt Turner
17c9ec94f5 gitlab-ci: Skip ext_timer_query/time-elapsed
This test's result is unpredictable, so it may occasionally pass when we
expect it to fail, thus causing the CI pipeline to fail.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3498>
2020-01-22 00:53:48 +00:00
Matt Turner
68cfc65ccb intel/compiler: Test compaction on Gen <= 12
With the previous commits we can now enable the unit test on Gen <= 12.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
22462ba242 intel/compiler: Validate fuzzed instructions
... before giving them to the instruction compactor.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
72cf63cfc6 intel/compiler: Add unit tests for new EU validation checks
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
5f4eacaeda intel/compiler: Validate some instruction word encodings
Specifically, execution size, register file, and register type. I did
not add validation for vertical stride and width because I don't believe
it's possible to have an otherwise valid instruction with an invalid
vertical stride or width, due to all of the other regioning
restrictions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
0fc490cdee intel/compiler: Factor out brw_validate_instruction()
In order to fuzz test instructions, we first need to do some sanity
checking first. Factoring out this function allows us an easy way to
validate a single instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
40f0ade68e intel/compiler: Handle invalid compacted immediates
16-bit immediates need to be replicated through the 32-bit immediate
field, so we should never see one that isn't.

This does happen however in the fuzzer unit test, so returning false
allows the fuzzer to reject this case.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
205cb8a139 intel/compiler: Handle invalid inputs to brw_reg_type_to_*()
Necessary to handle these cases when we test fuzzed instructions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
741cf9a104 intel/compiler: Split hw_type tables
Previously we were sharing tables between generations that were nearly
identical (i.e., Gen8 3-src adds HF support) and used a small bit of
code to handle the differences. This is kind of a mess if you want to
reject 64-bit types on platforms that don't support 64-bit types, so
split the tables, allowing each generation's table to list exactly what
it supports.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:21 +00:00
Matt Turner
0b70d46f7a intel/compiler: Add a INVALID_{,HW_}REG_TYPE macros
Since the enum brw_reg_type is packed, comparisons with -1 don't work
directly, necessitating the cast. Add a macro to avoid this confusion.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
ab7c25b9aa intel/compiler: Add NF some more places
Necessary to handle these cases when we test fuzzed instructions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
8634286c5d intel/compiler: Limit compaction unit tests to specific gens
Two of the tests emit instructions with MRF destinations, and MRFs
aren't present on Gen7+. I think we were just lucky that this didn't
cause a problem earlier since we were running the tests on Gen7-9.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
713c123bfa intel/compiler: Don't disassemble align1 3-src operands on Gen < 10
Since the platforms don't support align1 3-src instructions, the
contents of these operands are not going to be meaningful. Just don't
print them to avoid hitting some assertions in brw_inst functions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
49c21802cb intel/compiler: Split has_64bit_types into float/int
Gen7 has 64-bit floats but not 64-bit ints.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
bb47aa2124 intel/compiler: Extract GEN_* macros into separate file
Will be used by the instruction compaction unit test.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Matt Turner
c69f3ece61 intel/compiler: Use ARRAY_SIZE()
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
2020-01-22 00:19:20 +00:00
Caio Marcelo de Oliveira Filho
45164fc8c5 intel/fs: Don't emit control barrier if only one thread is used
When there's only one hardware thread (i.e. the dispatch width greater
or equal to the workgroup size), there's no need to use a barrier to
ensure all the invocations reach the same point in the shader, because
they are already running lock-step.

Results for SKL running Iris for shader-db tests with compute shaders

    total sends in shared programs: 18361 -> 18339 (-0.12%)
    sends in affected programs: 904 -> 882 (-2.43%)
    helped: 9
    HURT: 0
    helped stats (abs) min: 1 max: 5 x̄: 2.44 x̃: 2
    helped stats (rel) min: 0.84% max: 21.43% x̄: 7.82% x̃: 2.67%
    95% mean confidence interval for sends value: -3.31 -1.58
    95% mean confidence interval for sends %-change: -14.67% -0.97%
    Sends are helped.

Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped.

Results for ICL and TGL are similar to SKL.

Results for BDW are similar to SKL except for DeusEx shader that has a
workgroup size 16 but in BDW picks the SIMD8.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
2020-01-21 23:41:35 +00:00
Caio Marcelo de Oliveira Filho
4f431e870c intel/fs: Don't emit fence for shared memory if only one thread is used
When there's only one hardware thread (i.e. the dispatch width greater
or equal to the workgroup size), there's no need to synchronize shared
memory access (SLM) since all the requests from a single thread are
already synchronized.  In such case, we just add a scheduling fence.

To be able to identify that case for all platforms, move the handling
of platforms prior to Gen11 (which don't have a separate SLM fence)
after the optimization.

Results for SKL running Iris for shader-db tests with compute shaders

    total sends in shared programs: 18395 -> 18361 (-0.18%)
    sends in affected programs: 938 -> 904 (-3.62%)
    helped: 9
    HURT: 0
    helped stats (abs) min: 1 max: 5 x̄: 3.78 x̃: 4
    helped stats (rel) min: 1.56% max: 26.32% x̄: 10.33% x̃: 2.60%
    95% mean confidence interval for sends value: -4.85 -2.71
    95% mean confidence interval for sends %-change: -19.12% -1.54%
    Sends are helped.

Shaders from Aztec Ruins, Car Chase, Manhattan and DeusEx are helped.

Results for ICL and TGL are similar to SKL.

Results for BDW are similar to SKL except for DeusEx shader that has a
workgroup size 16 but in BDW picks the SIMD8.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
2020-01-21 23:41:35 +00:00
Caio Marcelo de Oliveira Filho
ff5b74ef32 intel/fs: Add workgroup_size() helper
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
2020-01-21 23:41:35 +00:00
Caio Marcelo de Oliveira Filho
18e72ee210 intel/fs: Add FS_OPCODE_SCHEDULING_FENCE
Like a SHADER_OPCODE_MEMORY_FENCE but doesn't doesn't generate any
assembly code.

Will be used when the compiler shouldn't reorder certain instructions
but there's no need to generate code for the HW to do it -- as the
ordering will be guaranteed by other means.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3226>
2020-01-21 23:41:35 +00:00
Dongwon Kim
9d964da19f gallium: check all planes' pipe formats in case of multi-samplers
Current code only checks whether first plane's format is supported
in case YUV format sampling is done by sampling each plane separately.
It would be safer to check other planes' as well.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2863>
2020-01-21 23:04:33 +00:00
Kenneth Graunke
d3a0d3a80b anv: Drop some workarounds that are no longer necessary
These workarounds are no longer required by 10th Gen hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
2020-01-21 13:58:42 -08:00
Kenneth Graunke
311cab27e2 iris: Drop some workarounds which are no longer necessary
These workarounds are no longer required by 10th Gen hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3495>
2020-01-21 13:58:40 -08:00
Eric Anholt
d1166a3b3a turnip: Disable UBWC on images used as storage images.
The closed GL driver doesn't use UBWC on any storage images.  It does tile
mostly (skipping tiling on writeonly images, it seems), but for freedreno
we've been enabling tiling in all cases and it's fine.  We do need to
disable UBWC, as tests fail otherwise and just plugging in the equivalent
UBWC regs like we were setting up a texture isn't enough.

Fixes dEQP-VK.image.atomic_operations.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
2020-01-21 19:29:59 +00:00
Eric Anholt
e5ce365cde turnip: Add limited support for storage images.
So far this doesn't handle the texture state-based storage image access
loads, and doesn't support descriptor arrays (same as SSBOs).  The texture
side is more tricky, since we have another remapping table to work around.

This is enough to get some of dEQP-VK.image.atomic_operations.* working.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
2020-01-21 19:29:59 +00:00
Eric Anholt
85e424c591 turnip: Refactor the intrinsic lowering.
Too many things in one function, split them out based on the intrinsic.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
2020-01-21 19:29:59 +00:00
Eric Anholt
3ac662e8df turnip: Fix some whitespace around binary operators.
Conforms to mesa style and the rest of turnip.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3433>
2020-01-21 19:29:59 +00:00
Eric Anholt
6c10af95c7 radeonsi: Drop PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS.
Now that we don't expose TGSI, we can stop exposing the flag.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
2020-01-21 19:04:22 +00:00
Eric Anholt
609a67461d r300: Remove a bunch of default handling of pipe caps.
u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.
The exception is the texel/gather offsets and stream output
components, which will not be exposed since we don't expose the
corresponding GLSL version.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
2020-01-21 19:04:22 +00:00
Eric Anholt
e7e034e1de r600: Remove a bunch of default handling of pipe caps.
u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
2020-01-21 19:04:22 +00:00
Eric Anholt
3e1dd99adc radeonsi: Remove a bunch of default handling of pipe caps.
u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
2020-01-21 19:04:22 +00:00
Lionel Landwerlin
e618951322 anv: don't report error with other vendor DRM devices
Enumeration should just skip unsupported DRM devices.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 34c8621c3b ("anv: Allow enumerating multiple physical devices")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2386
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3481>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3481>
2020-01-21 18:36:26 +00:00
Eric Anholt
fb6fca0037 freedreno: Stop scattered remapping of SSBOs/images to IBOs.
Just make it be all SSBOs then all storage images.  The remapping table
was there to make it so that the big gap present from gallium's atomic
lowering would get cleaned up, but that's no longer case.  The table has
made it very hard to support Vulkan storage images, so it's time for it to
go.

This does mean that an SSBO/IBO that is only loaded (or size-queried) will
now occupy a slot in the table where it wouldn't before.  This seems like
a minor cost compared to being able to drop this much logic.

With the remapping table gone, SSBO array handling for turnip just falls
out.

Fixes many array cases of
dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_buffer.*

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca> (turnip)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Eric Anholt
7558b5da13 compiler: Add a note about how num_ssbos works in the program info.
These numbers are always confusing, and it's particularly so for this
field where it has a different meaning in different info structs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Eric Anholt
d0975bfc4a nir: Drop the ssbo_offset to atomic lowering.
The arguments passed in were:
- prog->info.num_ssbos
- prog->nir->info.num_ssbos
- arbitrary values for standalone compilers

The num_ssbos should match between the prog's info and prog->nir's info
until this lowering happens.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Eric Anholt
d5a3971457 gallium: Pack the atomic counters just above the SSBOs.
We carve out half the SSBO space for atomics, and we were just binding
them way up there.  freedreno was then using a remapping table to map the
sparse buffer index back down, since space in the descriptor array is a
shared resource that may limit parallelism.  That remapping table
generated inside of the ir3 compiler is getting thoroughly in the way of
implementing vulkan descriptor sets.

We will be able to get rid of the freedreno's remapping table, and
hopefully save shared resources on other hardware, by packing the atomics
tightly above the SSBOs (like i965 does).  We already rebind the shader
buffers on program change if either the old or new program has SSBOs or
ABOs, so this doesn't necessarily increase the program state change cost
(the only cost increase I can come up with is if you're using the same
atomic counter without rebinding it across changes of programs with
varying SSBO counts, meaning it would now bounce around index space).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Eric Anholt
10dc4ac4c5 mesa: Make atomic lowering put atomics above SSBOs.
Gallium arbitrarily (it seems) put atomics below SSBOs, resulting in a
bunch of extra index management, and surprising shader code when you would
see your SSBOs up at index 16.  It makes a lot more sense to see atomics
converted to SSBOs appear as magic high numbers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Eric Anholt
2dc2055157 turnip: Refactor linkage state setup.
As I touch this for descriptor set reworks, I don't want to have to update
it twice.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
2020-01-21 10:06:23 -08:00
Timur Kristóf
28eb481bc2 nouveau/nvc0: add extern keyword to nvc0_miptree_vtbl.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2020-01-21 17:36:36 +01:00
Tapani Pälli
5fede43fe0 anv: initialize clear_color_is_zero_one
Fixes following valgrind warning:

   ==12508== Conditional jump or move depends on uninitialised value(s)
   ==12508==    at 0x2CCD8B79: cmd_buffer_begin_subpass (genX_cmd_buffer.c:4599)
   ==12508==    by 0x2CCDA72B: gen9_CmdBeginRenderPass (genX_cmd_buffer.c:5275)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3487>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3487>
2020-01-21 17:47:30 +02:00
Boris Brezillon
9134f22df2 panfrost/midgard: Print the actual source register for store operations
Store operation use r26/r27 but have a word->reg set to 0 or 1 (base is
r26). Let's take this base offset into account in
print_load_store_instr().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3482>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3482>
2020-01-21 14:57:12 +00:00
Alyssa Rosenzweig
14b37ebd44 panfrost: Add pandecode entries for ASTC/ETC formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:23 -05:00
Icecream95
31bd3b5279 panfrost: Add ASTC texture formats
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:23 -05:00
Icecream95
960fe9daea panfrost: Add ETC1/ETC2 texture formats
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:23 -05:00
Alyssa Rosenzweig
2091d311c9 panfrost: Rework linear<--->tiled conversions
There's a lot going on here (it's a ton of commits squashed together
since otherwise this would be impossible to review...)

1. We have a fast path for linear->tiled for whole (aligned) tiles, but we
have to use a slow path for unaligned accesses. We can get a pretty
major win for partial updates by using this slow path simply on the
borders of the update region, and then hit the fast path for the
tile-aligned interior. This does require some shuffling.

2. Mark the LUTs constant, which allows the compiler to inline them,
which pairs well with loop unrolling (eliminating the memory accesses
and just becoming some immediates.. which are not as immediate on
aarch64 as I'd like..)

3. Add fast path for bpp1/2/8/16. These use the same algorithm and we
have native types for them, so may as well get the fast path.

4. Drop generic path for bpp != 1/2/8/16, since these formats are
generally awful and there's no way to tile them efficienctly and
honestly there's not a good reason too either. Lima doesn't support any
of these formats; Panfrost can make the opinionated choice to make them
linear.

5. Specialize the unaligned routines. They don't have to be fully
generic, they just can't assume alignment. So now they should be nearly
as fast as the aligned versions (which get some extra tricks to be even
faster but the difference might be neglible on some workloads).

6. Specialize also for the size of the tile, to allow 4x4 tiling as well
as 16x16 tiling. This allows compressed textures to be efficiently tiled
with the same routines (so we add support for tiling ASTC/ETC textures
while we're at it)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:19 -05:00
Alyssa Rosenzweig
f2d876b2b2 panfrost,lima: De-Galliumize tiling routines
There's an implicit dependence on Gallium here that will add more
complexity than needed when testing/optimizing out of driver as well as
potentially Vulkanizing. We don't need a full pipe_box, just the x/y/w/h
properties directly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:16 -05:00
Alyssa Rosenzweig
0ca7ab1c97 panfrost: Compile tiling routines with -O3
These are major hot spots for panfrost and lima; better let the compiler
do its thing even on debug builds.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> #lima on Mali400
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3414>
2020-01-21 08:35:01 -05:00
Bas Nieuwenhuizen
bd4380c63c radv: Remove syncobj_handle variable in header.
I strongly suspect it was supposed to be a typedef. However, used
nowhere, we should remove it.

Fixes: eaa56eab6d "radv: initial support for shared semaphores (v2)"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2385
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3479>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3479>
2020-01-21 12:28:00 +00:00
Neil Armstrong
dc594c95dd gitlab-ci/lava: add pipeline information in the lava job name
In order to have more informations in the LAVA jobs list, add the
current pipeline URL and commit ref name in the LAVA job name.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2337>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2337>
2020-01-21 11:29:36 +00:00
Jan Zielinski
a24b3b228a gallium/gallivm: enable linking lp_bld_printf function with C++ code
To enable linking functions declared in lp_bld_printf.h file with C++,
we need to add appropriate macros to the header.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3470>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3470>
2020-01-21 11:00:18 +00:00
Danylo Piliaiev
3f9a6011a6 iris: Fix value of out-of-bounds accesses for vertex attributes
Having VERTEX_BUFFER_STATE.BufferSize greater than the size of
a bound vertex buffer allows shader to read uninitialized vertex
attributes from BO, instead of allowing hardware to return zeroes
on out-of-bounds access.

OpenGL spec "6.4 Effects of Accessing Outside Buffer Bounds" says:

"Robust buffer access can be enabled by creating a context with robust access
 enabled through the window system binding APIs. When enabled, any command
 unable to generate a GL error as described above, such as buffer object accesses
 from the active program, will not read or modify memory outside of the data
 store of the buffer object and will not result in GL interruption or termination.
 Out-of-bounds reads may return values from within the buffer object or zero
 values."

Fixes three webgl tests:
 conformance/rendering/out-of-bounds-array-buffers.html
 conformance2/rendering/out-of-bounds-index-buffers-after-copying.html
 conformance2/rendering/element-index-uint.html

See #1996

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3427>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3427>
2020-01-21 09:52:40 +00:00
Vasily Khoruzhick
e470116aac ci: Re-enable CI for lima on mali450
Amend fails and skips lists basing on lists from Andreas Baierl,
shard mali400 job across two devices since it takes close to 10min
and rename jobs to lima-mali400-test and lima-mali450-test.

Also don't set MESA_GLES_VERSION_OVERRIDE=3.0 for lima since we don't support
GLES 3.0 and lower DEQP_PARALLEL to 3 for jobs on H3.

Keep mali400 jobs disabled atm since they take too much time to complete
and we also get some unexplicable failures in dEQP-GLES2.functional.default_vertex_attrib.*

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
2020-01-21 09:33:57 +00:00
Vasily Khoruzhick
5e5b5348f6 ci: lava: pass CI_NODE_INDEX and CI_NODE_TOTAL to lava jobs
deqp-runner.sh uses it to determine whether we split job across multiple
devices and if we do what's the node index.

With this change we now can set 'parallel: N' in job description if we want
to split the job.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3163>
2020-01-21 09:33:57 +00:00
Hyunjun Ko
26d93a7495 turnip: fix invalid VK_ERROR_OUT_OF_POOL_MEMORY
When VK_DESCRIPTOR_TYPE_SAMPLER is provided, it doesn't need to be
counted as a buffer count. Otherwise it leads to mismatch of allocated
buffer size, hitting VK_ERROR_OUT_OF_POOL_MEMORY finally.

Fixes: c39afe68f0

Also fixes amber tests:
./tests/cases/address_modes_float.amber
./tests/cases/address_modes_int.amber
./tests/cases/magfilter_linear.amber
./tests/cases/magfilter_nearest.amber

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-21 10:29:16 +01:00
Jan Vesely
87e1f8eca5 clover: Initialize Asm Parsers
Fixes piglits that use ADMGCN inline assembly:
	program@execute@calls
	program@execute@amdgcn-mubuf-negative-vaddr

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
2020-01-21 01:39:08 +00:00
Jason Ekstrand
34c8621c3b anv: Allow enumerating multiple physical devices
Instead of having a single physical device in anv_instance, have a
linked list of them.  What we have now works today because we our GPUs
are build into the CPU and so you're guaranteed to only ever have one of
them.  One day, that will change and we want ANV to be ready.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
e963e151d8 anv: Re-arrange physical_device_init
This commit simply moves fetching the device info and checking if ANV
supports the device a bit higher up.  This way we fail earlier and it'll
make error checking easier in the next commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
3ecfba388a anv: Drop separate chipset_id fields
This already exists in gen_device_info.  There's no reason to keep
duplicate copies.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
02044be23f anv: Move the physical device dispatch table to anv_instance
We don't actually have genX versions of any physical device level
commands so we don't need the trampoline versions and we don't need to
have a separate table per physical device.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
78ff747408 anv: Drop the instance pointer from anv_device
There are very few times when we actually want to fetch the instance
from the anv_device.  We can put up with a bit of pain there in exchange
for strongly discouraging people from doing this in general.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
f0519c9cf9 anv: Stop allocating WSI event fences off the instance
Fixes: 16eb390834 "anv: add VK_EXT_display_control to anv driver [v5]"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
1ec84bd208 anv: Take a device in anv_perf_warn
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
cb6ea77045 anv: Take an anv_device in vk_errorf
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Jason Ekstrand
70e8064e13 anv: Add an anv_physical_device field to anv_device
Having to always pull the physical device from the instance has been
annoying for almost as long as the driver has existed.  It also won't
work in a world where we ever have more than one physical device.  This
commit adds a new field called "physical" to anv_device and switches
every location where we use device->instance->physicalDevice to use the
new field instead.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3461>
2020-01-20 22:08:52 +00:00
Marek Olšák
735a3ba007 radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
Only non-indexed triangle lists and strips are supported. This increases
performance if there is something to cull.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
c377f45c18 radeonsi/gfx10: rewrite late alloc computation
- Use conservative late alloc when the number of CUs <= 6.
- Move the late alloc GS register to the GS shader state, so that it can be
  tuned for NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
4e4b2d13f0 ac: add helper ac_build_triangle_strip_indices_to_triangle
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
8db00a51f8 radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
aa2d846604 radeonsi/gfx10: move GE_PC_ALLOC setting to shader states
The value is not changed. I just use a different way to compute it.

The value will vary with NGG culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
41fef6fc09 radeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough
v2: TES doesn't use the GS PrimitiveID

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
943d131e7d radeonsi/gfx10: merge main and pos/param export IF blocks into one if possible
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
a966729c84 radeonsi/gfx10: export primitives at the beginning of VS/TES
This decreases VGPR usage and will allow us to merge some IF blocks
in shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
5a0fcf11f0 radeonsi/gfx10: move s_sendmsg gs_alloc_req to the beginning of shaders
This will allow us to merge some IF blocks in shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
cf9f8d1ea2 radeonsi/gfx10: correct VS PrimitiveID implementation for NGG
We didn't use the correct LDS pointer, though it probably doesn't matter,
because I think that nothing else is using LDS here.

This commit makes it consistent with all other esgs_ring use.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
b2326a7549 radeonsi/gfx10: update comments and remove invalid TODOs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
0f45d4dc2b ac: add ac_build_readlane without optimization barrier
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
77393cf39b ac: add prefix bitcount functions
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
679b6244e1 radeonsi: turn an assertion into return in si_nir_store_output_tcs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 15:40:13 -05:00
Marek Olšák
27cc7703d3 radeonsi: fix doubles and int64
Fixes: 57bd73e229 - radeonsi: remove llvm_type_is_64bit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 15:40:10 -05:00
Marek Olšák
df34fa14bb radeonsi: don't invoke decompression inside internal launch_grid
Decompress resources properly but don't do it inside launch_grid
to prevent recursion.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
2020-01-20 15:40:08 -05:00
Marek Olšák
58c929be0d radeonsi: clean up how internal compute dispatches are handled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
2020-01-20 15:40:07 -05:00
Marek Olšák
d69483270e Revert "radeonsi: unbind image before compute clear"
This reverts commit 3a527eda7c.

It's incorrect.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 15:40:05 -05:00
Samuel Pitoiset
dbdf3b3ef9 aco: implement nir_intrinsic_load_barycentric_at_sample on GFX6
GFX6 doesn't have FLAT instructions which means we have to emit
a 64-bit MUBUF load.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
2020-01-20 16:24:55 +00:00
Samuel Pitoiset
9e2fde84fc aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
According to the different ISA docs (and to LLVM), this bit seems
to only exists on GFX6-GFX7.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
2020-01-20 16:24:55 +00:00
Samuel Pitoiset
fe9157a700 aco: do not use the vec3 variant for loads on GFX6
GFX6 only supports vec3 with load/store format.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
2020-01-20 16:24:55 +00:00
Samuel Pitoiset
1b5bb204d9 aco: do not use the vec3 variant for stores on GFX6
GFX6 only supports vec3 with load/store format.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
2020-01-20 16:24:55 +00:00
Samuel Pitoiset
b8abfafe86 aco: fix constant folding of SMRD instructions on GFX6
SMRD instructions have an 8-bit dword offset on SI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
2020-01-20 16:24:55 +00:00
Jason Ekstrand
dd92179a72 anv: Canonicalize buffer formats for image/buffer copies
Some formats, in particular YCbCr formats and ASTC have additional
restrictions.  We already whack ASTC formats to RGBA32_UINT because the
hardware doesn't allow LINEAR with ASTC.  However, we need to fix YCbCr
formats as well because they come with alignment restrictions that we
can't guarantee are satisfied.  We're using blorp_copy to do the copies
so we may as well just stomp formats for everything.

Fixes: b24b93d584 "anv: enable VK_KHR_sampler_ycbcr_conversion"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3460>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3460>
2020-01-20 16:08:17 +00:00
Jason Ekstrand
14c6e665f7 anv/blorp: Rename buffer image stride parameters
The new names fit better with the Vulkan names and don't pretend to be
an actual image extent.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3460>
2020-01-20 16:08:17 +00:00
Daniel Stone
cf5fccb0d9 Revert "gallium: add st_context_iface::flush_resource to call FLUSH_VERTICES"
This reverts commit bec9c90b5e.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3472>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3472>
2020-01-20 12:33:29 +00:00
Daniel Stone
32d45733ae Revert "st/dri: do FLUSH_VERTICES before calling flush_resource"
This reverts commit 3ba16d36c9.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3472>
2020-01-20 12:33:22 +00:00
Rhys Perry
29bfe18abd aco: fix fall-through test in try_remove_simple_block() with back-edges
3bca0af2 enhanced empty block determination which exposed this bug and
created an infinite loop in a Guild Wars 2 shader.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 3bca0af25d
     ('aco: ignore parallelcopies to the same register on jump threading')

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2364
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3452>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3452>
2020-01-20 11:51:45 +00:00
Krzysztof Raszkowski
afb75e71e0 docs/GL4: update gallium/swr features
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2020-01-20 11:37:16 +00:00
Rhys Perry
e151398de6 aco: fix stack buffer overflow in apply_sgprs()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: cef7879719 ('aco: rewrite apply_sgprs()')
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2361
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3442>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3442>
2020-01-20 11:13:11 +00:00
Tapani Pälli
9b2ccd6a0e anv: add assert for isl_mod_info in choose_isl_tiling_flags
CID: 1457859
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3469>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3469>
2020-01-20 12:12:29 +02:00
Tapani Pälli
8eebdd594b anv: fix assert in GetImageDrmFormatModifierPropertiesEXT
CID: 1457861
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3469>
2020-01-20 12:11:43 +02:00
Tapani Pälli
31feae1c21 isl/gen12: add reminder comment about missing WA with 3D surfaces
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3441>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3441>
2020-01-20 08:06:19 +02:00
Icecream95
d8a3501f1b panfrost: Dynamically allocate shader variants
This fixes a crash in LZDoom where over 16 shader variants are needed
for a few shaders in some maps, and should also save a few kilobytes
of RAM as most of the time only one or two variants of the 8 previously
allocated are actually needed.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-18 11:47:34 -05:00
Alyssa Rosenzweig
bef716b56c panfrost: Expose some functionality with dEQP flag
These features are stable enough that they don't need to be hidden.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3464>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3464>
2020-01-18 14:57:52 +00:00
Alyssa Rosenzweig
4af8d5b064 pan/midgard: Fix recursive csel scheduling
Corner case causing invalid scheduling on shaders with nested csels,
i.e. GLSL code resembling:

   (foo ? bool1 : bool2) ? x : y

By explicitly disallowing csels this is fixed.

Fixes INSTR_INVALID_ENC on a glamor shader (noticeable with slowdown and
visual corruption when scrolling "too far" on GTK apps).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3463>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3463>
2020-01-18 14:40:05 +00:00
Alyssa Rosenzweig
564a782ff7 panfrost: Identify un/pack colour opcodes
We still need to identify formats in the disassembler, but this will at
least get the opcode name clear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3462>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3462>
2020-01-18 14:18:48 +00:00
Alyssa Rosenzweig
13c32e5fed pan/midgard: Bytemasks should round up, not round down
Otherwise we'll lost components in DCE.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3462>
2020-01-18 14:18:48 +00:00
Icecream95
5e8386c606 panfrost: Compact the bo_access readers array
Previously, the array bo_access->readers was only cleared when there
were no unsignaled fences, which in some situations never happened.

That resulted in the array having thousands of NULL pointers, but only
a handful of active readers.

With this patch, all the unsignaled readers are moved to the front of
the array, effectively building a new array only containing the active
readers in-place. This results in the readers array usually only having
a couple of elements.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3419>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3419>
2020-01-18 13:58:43 +00:00
Erik Faye-Lund
c0ba9000d2 zink: support arrays of samplers
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
a9023ec566 zink: support sampling non-float textures
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
3e1acff560 zink: store image-type per texture
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
5fc1562a72 zink: avoid incorrect vector-construction
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
8112240d29 zink: support offset-variants of texturing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
f1a5bcdc16 zink: implement nir_texop_txs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3275>
2020-01-18 10:45:38 +00:00
Erik Faye-Lund
7ee94d1b21 docs: fixup indentation
The most canonical indentation-style here is two spaces, which is what
the standard boilerplate in all documents use. So let's normalize to
that.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:32 +01:00
Erik Faye-Lund
2ef989473a docs: remove pointless, stray newline
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:29 +01:00
Erik Faye-Lund
199572b65b docs: use [1] instead of asterisk for footnote
While we're at it, make it a link as well.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:25 +01:00
Erik Faye-Lund
063a28642e docs: remove trailing newlines
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:22 +01:00
Erik Faye-Lund
9954120b38 docs: remove leading spaces
There's no good reason to have leading space in these pre-formatted
blocks. It looks strange, so let's get rid of it.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:18 +01:00
Erik Faye-Lund
c871862744 docs: remove trailing header
This header has been there since the document was added, but contains
nothing. So let's get rid of it.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:14 +01:00
Erik Faye-Lund
37daddd3e4 docs: use figure/figcaption instead of tables
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:39:07 +01:00
Erik Faye-Lund
f5983a6eed docs: do not use definition-list for sub-topics
The dl-tag isn't a neat tool for defining sub-headings, it's a semantic
tool for defining definitions and their meaning. Let's insetad use
normal sub-headings instead.

To make the last few paragraphs stand out from the above, let's add a
sub-heading for those as well.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3443>
2020-01-18 11:38:56 +01:00
Rob Clark
95187083c4 freedreno/a6xx: add PROG_FB_RAST stateobj
For the handful of registers that depend on the union of program/
framebuffer/rasterizer state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Rob Clark
6dc9b292d0 freedreno/a6xx: move dynamic program state to streaming stateobj
Move the program state which we can't pre-bake to a streaming state
object, rather than emitting directly in the draw cmdstream.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Rob Clark
d2fd6469c3 freedreno/a6xx: drop a few more per-draw registers
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Rob Clark
4d8f42c851 freedreno/a6xx: separate rast stateobj for prim restart
This lets us move PC_PRIMITIVE_CNTL into the rasterizr stateobj, rather
than unconditionally emitting it directly in the cmdstream on every
draw.

This also starts adding some tracking about previous draw state, so that
following patches can limit some of the register writes we currently
emit on every draw.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Rob Clark
0e063b3079 freedreno/a6xx: cleanup rasterizer state
All but one of the reg values is only used in the stateobj, so we can
inline the register value setup and stateobj construction.  While we
are at it, switch over to the new register builders.

Prep work for next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Rob Clark
fba7e6f896 freedreno/a6xx: limit scratch/debug markers to debug builds
The overhead does seem to matter when you have a high enough # of draw
calls that effect few bins/pixels, because these writes would happen
unconditionally (ie. not part of a state-group).

Possibly we could keep these if we moved them into a state-group so the
register writes would be no-ops on bins with no geometry.  OTOH I
usually end up adding in a WFI when using them scratch reg values to
track down a crash.  (So add a WFI to mitigate the annoyance of needing
to use a debug build to get scratch regs to locate the position of a
crash/hang in the cmdstream.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3435>
2020-01-17 15:43:51 -08:00
Jordan Justen
5d7381c645 iris: Fix some indentation in iris_init_render_context
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2020-01-17 15:28:07 -08:00
C Stout
c1104e4cee util/vector: Fix u_vector_foreach when head rolls over
Also add unit tests for u_vector.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3453>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3453>
2020-01-17 22:21:00 +00:00
Francisco Jerez
b54b67e067 intel/fs: Switch to standard vector layout for barycentrics at optimization time.
This involves permuting the registers of barycentric vectors to have
the standard X[0-n] Y[0-n] layout at NIR translation time.
Barycentrics are converted to the format expected by the PLN
instruction in the lower_barycentrics() pass run after the
optimization loop.

Main reason is correctness of SIMD32 fragment shaders.  The
shuffle_from_pln_layout() and shuffle_to_pln_layout() helpers used
during NIR translation are busted for SIMD32.  This leads to serious
corruption at present with INTEL_DEBUG=do32, especially on Gen11+
where these helpers are hit more frequently due to the lack of a
hardware PLN instruction.

Of course one could have chosen to fix those helpers instead, but
there is another far more subtle issue that was reported during review
of the SIMD32 fragment shader codegen changes: The SIMD splitting pass
currently handles SIMD32 barycentric vectors as if they had the
standard X[0-n] Y[0-n] layout, even though they are interleaved for
the PLN instruction, which causes incorrect execution masks to be
applied to the MOVs unzipping barycentric vectors in cases where a
LINTERP instruction occurs under non-uniform control flow.

I'm not aware of any conformance regressions due to the latter issue
at present, but for our peace of mind let's move the conversion to the
PLN layout into the lower_barycentrics() pass run after
lower_simd_width().

This leads to the following shader-db improvements (including SIMD32
shaders) in combination with the previous back-end preparation changes
-- Without them (especially the copy propagation changes) this would
lead to a massive number of regressions.  On ICL:

   total instructions in shared programs: 20662316 -> 20466903 (-0.95%)
   instructions in affected programs: 10538474 -> 10343061 (-1.85%)
   helped: 68775
   HURT: 6

   total spills in shared programs: 8938 -> 8748 (-2.13%)
   spills in affected programs: 376 -> 186 (-50.53%)
   helped: 9
   HURT: 5

   total fills in shared programs: 8965 -> 8663 (-3.37%)
   fills in affected programs: 965 -> 663 (-31.30%)
   helped: 9
   HURT: 6

   LOST:   146
   GAINED: 43

On SKL:

   total instructions in shared programs: 18725867 -> 18614912 (-0.59%)
   instructions in affected programs: 3876590 -> 3765635 (-2.86%)
   helped: 27492
   HURT: 2

   LOST:   191
   GAINED: 417

On SNB:

   total instructions in shared programs: 14573613 -> 13980646 (-4.07%)
   instructions in affected programs: 5199074 -> 4606107 (-11.41%)
   helped: 29998
   HURT: 0

   LOST:   21
   GAINED: 30

Results are somewhat less impressive but still significant without
SIMD32 fragment shaders enabled.  On ICL:

   total instructions in shared programs: 16148728 -> 16061659 (-0.54%)
   instructions in affected programs: 6114788 -> 6027719 (-1.42%)
   helped: 42046
   HURT: 6

   total spills in shared programs: 8218 -> 8028 (-2.31%)
   spills in affected programs: 376 -> 186 (-50.53%)
   helped: 9
   HURT: 5

   total fills in shared programs: 8953 -> 8651 (-3.37%)
   fills in affected programs: 965 -> 663 (-31.30%)
   helped: 9
   HURT: 6

   LOST:   0
   GAINED: 3

On SKL:

   total instructions in shared programs: 14927994 -> 14926738 (-0.01%)
   instructions in affected programs: 168850 -> 167594 (-0.74%)
   helped: 711
   HURT: 2

On SNB:

   total instructions in shared programs: 10770538 -> 10734403 (-0.34%)
   instructions in affected programs: 2702172 -> 2666037 (-1.34%)
   helped: 17818
   HURT: 0

All of the hurt shaders are either spilling slightly more or emitting
additional NOP instructions due to the SIMD16 POW workaround for
Gen8-9 combined with differences in scheduling.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:23:12 -08:00
Francisco Jerez
79bd252d6e intel/fs: Introduce barycentric layout lowering pass.
The goal is to represent barycentrics with the standard vector layout
during optimization and particularly SIMD lowering.  Instead of
emitting the barycentric layout conversions at NIR translation time,
do it later as a lowering pass.  For the moment this is only applied
to PI messages, but we'll give the same treatment to LINTERP
instructions too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:59 -08:00
Francisco Jerez
44d7d66adc intel/fs: Split fetch_payload_reg() into separate helper for barycentrics.
We're about to change the layout of barycentric vectors, which will
involve permuting the GRFs of barycentrics fetched from the thread
payload.  Make room for this in a function separate from the generic
fetch_payload_reg(), since the permutation will only be applicable to
barycentric vectors.  This allows simplifying fetch_payload_reg(),
since there was no need for handling multiple-component payload
registers except for barycentrics.

This causes some minor shader-db noise due to the new helper emitting
a LOAD_PAYLOAD instruction unconditionally, but it will be cleaned up
shortly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:51 -08:00
Francisco Jerez
9c9e80103c intel/fs/gen6: Use SEL instead of bashing thread payload for unlit centroid workaround.
This prevents regressions on SNB due to the redundant MOVs lying
around in cases where fetch_payload_reg() returns a VGRF (currently
only in SIMD32 but soon in pretty much all cases).  The MOVs can't be
register-coalesced due to their source being a FIXED_GRF, and they
can't be copy-propagated either due to the unlit centroid workaround
partial writes.  They can be copy-propagated just fine into a SEL
instruction though.

On SNB this prevents the following shader-db regressions (including
SIMD32 programs) in combination with the interpolation rework part of
this series:

   total instructions in shared programs: 13996898 -> 14001982 (0.04%)
   instructions in affected programs: 197461 -> 202545 (2.57%)
   helped: 0
   HURT: 1251

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:39 -08:00
Francisco Jerez
0dd18d70ae intel/fs/gen6: Generalize aligned_pairs_class to SIMD16 aligned barycentrics.
This is mainly meant to avoid shader-db regressions on SNB as we start
using VGRFs for barycentrics more frequently.  Currently the
aligned_pairs_class is only useful in SIMD8 mode, because in SIMD16
mode barycentric vectors are typically 4 GRFs.  This is not a problem
on Gen4-5, because on those platforms all VGRF allocations are
pair-aligned in SIMD16 mode.  However on Gen6 we end up using either
the fast or the slow path of LINTERP rather non-deterministically
based on the behavior of the register allocator.

Fix it by repurposing aligned_pairs_class to hold PLN-aligned
registers of whatever the natural size of a barycentric vector is in
the current dispatch width.

On SNB this prevents the following shader-db regressions (including
SIMD32 programs) in combination with the interpolation rework part of
this series:

   total instructions in shared programs: 13983257 -> 14527274 (3.89%)
   instructions in affected programs: 1766255 -> 2310272 (30.80%)
   helped: 0
   HURT: 11608

   LOST:   26
   GAINED: 13

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:34 -08:00
Francisco Jerez
0db4455c1f intel/fs/gen6: Constrain barycentric source of LINTERP during bank conflict mitigation.
This avoids regressions on SNB due to the bank conflict mitigation
pass moving a VGRF-allocated barycentric vector to a misaligned
location, which would prevent the PLN instruction from being used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:29 -08:00
Francisco Jerez
369aef851d intel/fs/gen4-6: Allocate registers from aligned_pairs_class based on LINTERP use.
Previously we would hardcode fs_visitor::delta_xy barycentrics to be
allocated from aligned_pairs_class on hardware with PLN source
alignment restrictions (pre-Gen7).  Instead allocate any registers
consumed by LINTERP from aligned_pairs_class, even if some barycentric
vector had ended up in a temporary.

On SNB this prevents the following shader-db regressions (including
SIMD32 programs) in combination with the interpolation rework part of
this series:

   total instructions in shared programs: 13983257 -> 14527274 (3.89%)
   instructions in affected programs: 1766255 -> 2310272 (30.80%)
   helped: 0
   HURT: 11608

   LOST:   26
   GAINED: 13

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:20 -08:00
Francisco Jerez
54b1b71e73 intel/fs: Allow limited copy propagation of a LOAD_PAYLOAD into another.
This is particularly useful in cases where register coalaesce is
unlikely to succeed because the LOAD_PAYLOAD isn't a plain copy --
E.g. when a LOAD_PAYLOAD is shuffling the contents of a barycentric
vector in order to transform it into the PLN layout.

This prevents the following shader-db regressions (including SIMD32
programs) in combination with the interpolation rework part of this
series.  On SKL:

   total instructions in shared programs: 18596672 -> 18976097 (2.04%)
   instructions in affected programs: 7937041 -> 8316466 (4.78%)
   helped: 39
   HURT: 67427

   LOST:   466
   GAINED: 220

On SNB:

   total instructions in shared programs: 13993866 -> 14202963 (1.49%)
   instructions in affected programs: 7611309 -> 7820406 (2.75%)
   helped: 624
   HURT: 52943

   LOST:   6
   GAINED: 18

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:22:09 -08:00
Francisco Jerez
8eb4f2092a intel/fs: Add support for copy-propagating a block of multiple FIXED_GRFs.
In cases where a LOAD_PAYLOAD instruction copies a single block of
sequential GRF registers into the destination (see
is_identity_payload()), splitting the block copy into a number of ACP
entries (one for each LOAD_PAYLOAD source) is undesirable, because
that prevents copy propagation into any instructions which read
multiple components at once with the same source (the barycentric
source of the LINTERP instruction is going to be the overwhelmingly
most common example).

Technically it would also be possible to do this for VGRF sources, but
there is little benefit from that since register coalesce already
covers many of those cases -- There is no way for a block of
FIXED_GRFs to be coalesced into a VGRF though.

This prevents the following shader-db regressions (including SIMD32
programs) in combination with the interpolation rework part of this
series.  On SKL:

   total instructions in shared programs: 18595160 -> 18828562 (1.26%)
   instructions in affected programs: 13374946 -> 13608348 (1.75%)
   helped: 7
   HURT: 108977

   total spills in shared programs: 9116 -> 9106 (-0.11%)
   spills in affected programs: 404 -> 394 (-2.48%)
   helped: 7
   HURT: 9

   total fills in shared programs: 8994 -> 9176 (2.02%)
   fills in affected programs: 898 -> 1080 (20.27%)
   helped: 7
   HURT: 9

   LOST:   469
   GAINED: 220

On SNB:

   total instructions in shared programs: 13996898 -> 14096222 (0.71%)
   instructions in affected programs: 8088546 -> 8187870 (1.23%)
   helped: 2
   HURT: 66520

   total spills in shared programs: 2985 -> 2961 (-0.80%)
   spills in affected programs: 632 -> 608 (-3.80%)
   helped: 2
   HURT: 0

   total fills in shared programs: 3144 -> 3128 (-0.51%)
   fills in affected programs: 1515 -> 1499 (-1.06%)
   helped: 2
   HURT: 0

   LOST:   0
   GAINED: 4

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:21:41 -08:00
Francisco Jerez
e328fbd9f8 intel/fs: Add partial support for copy-propagating FIXED_GRFs.
This will be useful for eliminating redundant copies from the FS
thread payload, particularly in SIMD32 programs.  For the moment we
only allow FIXED_GRFs with identity strides in order to avoid dealing
with composing the arbitrary bidimensional strides that FIXED_GRF
regions potentially have, which are rarely used at the IR level
anyway.

This enables the following commit allowing block-propagation of
FIXED_GRF LOAD_PAYLOAD copies, and prevents the following shader-db
regressions (including SIMD32 programs) in combination with the
interpolation rework part of this series.  On ICL:

   total instructions in shared programs: 20484665 -> 20529650 (0.22%)
   instructions in affected programs: 6031235 -> 6076220 (0.75%)
   helped: 5
   HURT: 42073

   total spills in shared programs: 8748 -> 8925 (2.02%)
   spills in affected programs: 186 -> 363 (95.16%)
   helped: 5
   HURT: 9

   total fills in shared programs: 8663 -> 8960 (3.43%)
   fills in affected programs: 647 -> 944 (45.90%)
   helped: 5
   HURT: 9

On SKL:

   total instructions in shared programs: 18937442 -> 19128162 (1.01%)
   instructions in affected programs: 8378187 -> 8568907 (2.28%)
   helped: 39
   HURT: 68176

   LOST:   1
   GAINED: 4

On SNB:

   total instructions in shared programs: 14094685 -> 14243499 (1.06%)
   instructions in affected programs: 7751062 -> 7899876 (1.92%)
   helped: 623
   HURT: 53586

   LOST:   7
   GAINED: 25

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:21:33 -08:00
Francisco Jerez
5153d06d92 intel/fs: Extend copy propagation dataflow analysis to copies with FIXED_GRF source.
This involves indexing the ACP tables used internally by
fs_copy_prop_dataflow::setup_initial_values() by reg_space() instead
of register number.  Both are nearly equivalent for virtual GRFs
(barring the single bit of entropy lost in the hash), and this makes
handling FIXED_GRFs straightforward.

Because we're only going to support FIXED_GRFs for the source of a
copy, this change is only strictly necessary during the second pass
that checks for source interference, but we also apply the same change
to the first pass for consistency.

Note that this shouldn't change the behavior of the copy propagation
pass until we start inserting FIXED_GRF entries into the ACP.  Even
then FIXED_GRF writes are extremely rare so this change will hardly
ever have an effect, but they aren't completely non-existing so we
need to handle them for correctness.

No functional nor shader-db changes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:21:27 -08:00
Francisco Jerez
ab0d1b3b3d intel/fs: Rework fs_inst::is_copy_payload() into multiple classification helpers.
This reworks the current fs_inst::is_copy_payload() method into a
number of classification helpers with well-defined semantics.  This
will be useful later on in order to optimize LOAD_PAYLOAD instructions
more aggressively in cases where we can determine it's safe to do so.

The closest equivalent of the present fs_inst::is_copy_payload()
method is the is_coalescing_payload() helper introduced here.

No functional nor shader-db changes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:21:19 -08:00
Francisco Jerez
1873202f44 intel/fs: Generalize fs_reg::is_contiguous() to register files other than VGRF.
No functional nor shader-db changes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:20:59 -08:00
Francisco Jerez
d9a57c85cc intel/fs: Try to vectorize header setup in lower_load_payload().
In cases where LOAD_PAYLOAD is provided a pair of contiguous registers
as header sources, try to use a single SIMD16 instruction in order to
initialize them.  This is unlikely to affect the overall cycle count
of the shader, since the compressed instruction has twice the issue
time, except due to the reduced pressure on the instruction cache.

Main motivation is avoiding instruction-count regressions in
combination with the following copy propagation improvements, which
will allow the SIMD16 g0-1 header setup emitted for framebuffer writes
to be copy-propagated into its LOAD_PAYLOAD, leading to the emission
of two SIMD8 MOV instructions instead of a single SIMD16 MOV.

Reverting this commit on top of the copy propagation changes would
lead to the following shader-db regressions on SKL and other
platforms:

 total instructions in shared programs: 14926738 -> 14935415 (0.06%)
 instructions in affected programs: 1892445 -> 1901122 (0.46%)
 helped: 0
 HURT: 8676

Without the following copy propagation changes this doesn't have any
effect on shader-db on Gen7+, because we would typically set up the FB
write header with a separate SIMD16 MOV that isn't currently
copy-propagated into the LOAD_PAYLOAD, so the individual SIMD8 MOVs
result of LOAD_PAYLOAD lowering would get register-coalesced away
under normal circumstances.  However that wasn't the case for MRF
LOAD_PAYLOAD destinations on Gen6 and earlier, because register
coalesce only kicks in for GRFs, leaving a number of redundant SIMD8
MOVs lying around.  On SNB this leads to the following shader-db
improvements:

 total instructions in shared programs: 10770538 -> 10734681 (-0.33%)
 instructions in affected programs: 2700655 -> 2664798 (-1.33%)
 helped: 17791
 HURT: 0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-17 13:20:46 -08:00
Marek Olšák
3ba16d36c9 st/dri: do FLUSH_VERTICES before calling flush_resource 2020-01-17 15:04:35 -05:00
Marek Olšák
bec9c90b5e gallium: add st_context_iface::flush_resource to call FLUSH_VERTICES 2020-01-17 15:04:35 -05:00
Lionel Landwerlin
ddb80f9276 anv: enable VK_KHR_swapchain_mutable_format
Enable new tests in dEQP-VK.image.swapchain_mutable.*

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
4bdf8547f4 vulkan/wsi: Implement VK_KHR_swapchain_mutable_format
This is only the core WSI code for the extension.  It adds the image
format list and the flags to vkCreateImage as well as handling things
properly in the modifier queries.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
a218f13278 vulkan/wsi: Filter modifiers with ImageFormatProperties
Just because a modifier is returned for the given format, that doesn't
mean it works with all usages and flags.  We need to filter the list by
calling vkGetPhysicalDeviceImageFormatProperties2.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
210e68874b vulkan/wsi: Use the interface from the real modifiers extension
The anv implementation still isn't quite complete, but we can at least
start using the structs from the real extension.

v2: Fix circular pNext list (Lionel)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
c78926b84d vulkan/wsi: Move the ImageCreateInfo higher up
Future changes will be easier if we can modify it based on whether or
not we're using modifiers.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
6790397346 anv: Support modifiers in GetImageFormatProperties2
Images with modifiers come with restrictions:

 1. They have to be simple 2D images right now

 2. They need to have a sensible format (not compressed, multi-plane, or
    non-power-of-two)

 3. If a CCS modifier is being requested, they have to actually support
    CCS_E and be CCS-compatible with any other formats the client may
    wish to use for image views.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Jason Ekstrand
44f5a92c0b anv: Drop some VK_IMAGE_TILING_OPTIMAL checks
The DRM format modifiers extension adds a TILING_DRM_FORMAT_MODIFIER
which will be used for modifiers so we can no longer use OPTIMAL to
indicate tiled inside the driver.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3434>
2020-01-17 18:27:29 +00:00
Samuel Pitoiset
0099f85232 aco: print assembly with CLRXdisasm for GFX6-GFX7 if found on the system
LLVM only supports GFX8+. Using CLRXdisasm works most of the time,
so it's useful to add support for it.

Original patch by Daniel Schürmann.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3439>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3439>
2020-01-17 17:41:32 +00:00
Andres Rodriguez
51de5d5ac6 vulkan/wsi: disable the hardware cursor
Ensure the hardware cursor is disabled when we set the mode for a
VkDisplayKHR object. The extension doesn't expose any mechanisms to
program the hardware cursor, so we need to ensure it is hidden.

Currently, it seems like X is responsible for disabling the cursor
before handing over the lease. But that seems a little frail, and we
should be disabling the cursor ourselves so it works correctly
independently of how the lease was prepared for us.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1922>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1922>
2020-01-17 17:15:52 +00:00
Krzysztof Raszkowski
ad820d5aca gallium/swr: Disable showing detected arch message.
When swr driver is in use it print detected architecture
message to std::err. It can be harmfull when swr is using
in multinodes environments.
It can be enabled setting env var SWR_PRINT_INFO to 1.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2020-01-17 16:41:53 +00:00
Samuel Pitoiset
b9b393f0ce aco: fix emitting slc for MUBUF instructions on GFX6-GFX7
Same as GFX10, only GFX8/GFX9 moved that bit near the opcode.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3437>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3437>
2020-01-17 16:56:04 +01:00
Boris Brezillon
6af63c939b panfrost/midgard: Fix swizzle for store instructions
The current logic considers that the nir_intrinsic_component(store_intr)
encodes the source components start, but it actually encodes the
destination one. Source component offset adjustment is taken care of in
install_registers_instr(), when offset_swizzle() is called.

This fixes dEQP-GLES2.functional.shaders.random.all_features.fragment.45
when PAN_MESA_DEBUG=deqp (looks like exposing GLES3 features has an
impact on the varyings layout).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3429>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3429>
2020-01-17 12:54:31 +00:00
Erik Faye-Lund
be95c816a7 docs: do not double-close link tag
Fixes: f8148d0cc1 "docs: remove mailing list as way of submitting patches"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:19:16 +01:00
Erik Faye-Lund
b009a7644b docs: remove double-closed definition-list
Fixes: bc17ac5866 "docs: add documentation for building with meson"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:19:10 +01:00
Erik Faye-Lund
b387f68f49 docs: move paragraph closing tag
The pre-tag right before is a block-level tag, which means it implicitly
terminates the paragraph. So there's no paragraph to close after this.
Instead, move the paragraph-closing before the pre-tag, to explicitly
close the paragraph.

Fixes: 41b3eb08d9 "docs: update meson docs for windows"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:19:03 +01:00
Erik Faye-Lund
a370cfd96e docs: use code-tags instead of pre-tags
Similar to the previous two commits, it seems more appropriate to use
code-tags here than pre-tag.

Fixes: 9af6c38def "docs: Add use of Closes: tag for closing gitlab issues"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:52 +01:00
Erik Faye-Lund
1de361e56b docs: use code-tags instead of pre-tags
Similar to the previous commit, code-tags seems more appropriate than
pre-tags here. So let's change it.

Fixes: ca0c1e69ca "docs: update releasing process to use new scripts and gitlab"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:48 +01:00
Erik Faye-Lund
36e0275275 docs: use code-tag instead of pre-tag
It's unlikely the author meant to use <pre>-here, as that starts a whole
new block. Instead, the inline code-tag seems more appropriate here.

Fixes: 41b3eb08d9 "docs: update meson docs for windows"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:42 +01:00
Erik Faye-Lund
f0677086a1 docs: open paragraph before closing it
Fixes: 44c5e634a5 "docs: update meson docs for windows"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:36 +01:00
Erik Faye-Lund
a0d25c4d87 docs: fix paragraphs
Paragraphs are terminated by pre-tags, so the latter one closes a new,
empty one. Let's split the paragraph in two around the pre-tag instead.

Fixes: c0dfe8c6df "docs: do not use div for line-breaking"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:25 +01:00
Erik Faye-Lund
750d664226 docs: fix typo in html tag name
Fixes: 5d11a828e1 "docs: update install docs for meson"
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3431>
2020-01-17 13:18:06 +01:00
Pierre-Eric Pelloux-Prayer
5b1c4e1b75 util: call bind_sampler_states before setting sampler_views
Fixes the following valgrind error:

    Invalid read of size 16
       at 0x28F458A1: si_set_sampler_view_desc (in radeonsi_drv_video.so)
       by 0x28F4657E: si_set_sampler_views (in radeonsi_drv_video.so)
       by 0x28D62BF5: util_compute_blit (in radeonsi_drv_video.so)
       by 0x28D3A944: vlVaHandleVAProcPipelineParameterBufferType (in radeonsi_drv_video.so)
       by 0x28D34EE1: vlVaRenderPicture (in radeonsi_drv_video.so)
       by 0x4B2582B: vaRenderPicture (in libva.so.2.500.0)
     Address 0x18142a10 is 0 bytes inside a block of size 48 free'd
       at 0x48369AB: free (vg_replace_malloc.c:540)
       by 0x28D62D51: util_compute_blit (in radeonsi_drv_video.so)
       by 0x28D3A944: vlVaHandleVAProcPipelineParameterBufferType (in radeonsi_drv_video.so)
       by 0x28D34EE1: vlVaRenderPicture (in radeonsi_drv_video.so)
       by 0x4B2582B: vaRenderPicture (in libva.so.2.500.0)
     Block was alloc'd at
       at 0x4837B65: calloc (vg_replace_malloc.c:762)
       by 0x28EFB2EC: si_create_sampler_state (in radeonsi_drv_video.so)
       by 0x28D62C30: util_compute_blit (in radeonsi_drv_video.so)
       by 0x28D3A944: vlVaHandleVAProcPipelineParameterBufferType (in radeonsi_drv_video.so)
       by 0x28D34EE1: vlVaRenderPicture (in radeonsi_drv_video.so)
       by 0x4B2582B: vaRenderPicture (in libva.so.2.500.0)

Fixes: 69430d7e59 ("va: use a compute shader for the blit")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2321
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3428>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3428>
2020-01-17 10:14:57 +01:00
Eric Anholt
d55573aac6 nir: Fix printing of ~0 .locations.
I kept wondering what "429" meant in variable declarations, when it was
just a truncated ~0 snprintf.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3423>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3423>
2020-01-16 23:29:10 +00:00
Eric Engestrom
65641e0c7a meson: use github URL for wraps instead of completely unreliable wrapdb
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3391>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3391>
2020-01-16 23:06:43 +00:00
Dylan Baker
d7cef7c67b docs: Update release calendar for 20.0
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3417>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3417>
2020-01-16 22:41:55 +00:00
Andreas Baierl
2ebfc6db16 lima: Fix alpha blending
Introduce separate helper functions to set the blendfactor bits.

Lima uses bits 0-2 for the type, bit 3 sets the inverted function
and bit 4 is set if alpha is used.
alpha_src_factor and alpha_dst_factor don't need the alpha bit, so
they are masked with 0xf. There is only place for 4 bits anyway.
If alpha_src_factor is PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE, we need
to change it to PIPE_BLENDFACTOR_ONE first.
This is exactly what the blob does and we pass all
dEQP-GLES2.functional.fragment_ops.blend.* tests now.
Better than the blob btw...

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3411>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3411>
2020-01-16 16:43:41 +00:00
Daniel Schürmann
3bca0af25d aco: ignore parallelcopies to the same register on jump threading
The more conservative lowering to CSSA inserts unnecessary parallelcopies
which might get coalesced and can be ignored on jump threading.

v2: outline is_empty_block() check.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3385>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3385>
2020-01-16 16:01:59 +01:00
Daniel Schürmann
427e5eeb02 aco: handle phi affinities transitively through parallelcopies
This can coalesce most unnecessarily inserted parallelcopies
from lowering to CSSA.

v2: refactor loop a bit to make it more efficient and readable.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3385>
2020-01-16 16:01:59 +01:00
Daniel Schürmann
d098024c40 aco: rework lower_to_cssa()
This patch changes lower_to_cssa to be much more conservative
about assumptions which phi operands might interfere.
Previously, this pass wasn't exhaustive and could miss some corner cases.

v2: remove optimizations to find better insertion points as it's hard
to guarantee that they are always correct and have overall no benefit.

Fixes: 0b8216b2cd ('aco: Lower to CSSA')

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3385>
2020-01-16 16:01:59 +01:00
Samuel Pitoiset
300f8dec76 aco: implement stream output with vec3 on GFX6
GFX6 doesn't support vec3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
2020-01-16 14:06:06 +00:00
Samuel Pitoiset
a445cb35bd aco: do not combine additions of DS instructions on GFX6
The offset field doesn't work as expected on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
2020-01-16 14:06:06 +00:00
Samuel Pitoiset
923005bf54 aco: do not select 96-bit/128-bit variants for ds_read/ds_write on GFX6
Only GFX7 and later support large ds_read/ds_write.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
2020-01-16 14:06:06 +00:00
Lionel Landwerlin
44ffeb4fee intel/perf: report query split for mdapi
Also forgotten in the initial implementation.

v2: Report begin timestamp scaled by the timestamp frequency (Windows
    behavior)

v3: Rename split to disjoint to match GL terminology (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112>
2020-01-16 15:29:40 +02:00
Lionel Landwerlin
3bb8a4bfec intel/perf: expose timestamp begin for mdapi
This was forgotten in the initial implementation.

v2: ensure the value is written for both GL & Vulkan queries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3112>
2020-01-16 15:29:28 +02:00
Tapani Pälli
630cbb45ac anv: set depth stall enabled when depth flush enabled on gen12
This implements HW workaround #1409600907 for anv driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
2020-01-16 14:05:54 +02:00
Tapani Pälli
3cec148455 iris: set depth stall enabled when depth flush enabled on gen12
This implements HW workaround #1409600907 for iris driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
2020-01-16 14:05:54 +02:00
Lionel Landwerlin
308efbf2f3 anv: implement another workaround for non pipelined states
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
2020-01-16 11:51:30 +02:00
Lionel Landwerlin
9eca823cce iris: implement another workaround for non pipelined states
v2: add comment (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
2020-01-16 11:51:22 +02:00
Lionel Landwerlin
e6e5cbac04 iris: handle new PIPE_CONTROL field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
2020-01-16 11:48:11 +02:00
Lionel Landwerlin
31f0af5568 genxml: add new Gen11+ PIPE_CONTROL field
PIPE_CONTROL gained a new field in its first DWORD on Gen11. We had no
use for it so far, but we start using it on Gen12.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
2020-01-16 11:48:04 +02:00
Kenneth Graunke
e3405f177b st/mesa: Allocate full miplevels if MaxLevel is explicitly set
Some applications explicitly call glTex[ture]Parameteri[v] to set
GL_TEXTURE_MAX_LEVEL and GL_TEXTURE_BASE_LEVEL before uploading any
texture data.  Core Mesa initializes MaxLevel to 1000, so if it isn't
that, we know they've set it.  (We check for < TEXTURE_MAX_LEVELS to
avoid hardcoding that value, however.)

If MaxLevel - BaseLevel > 0, then the app is trying to tell us that
this texture is going to have multiple miplevels.  In that case, go
ahead and allocate the space for it.

Avoids many resource_copy_region calls at texture finalization time
in the Civilization VI benchmark.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3401>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3401>
2020-01-16 00:06:54 -08:00
Samuel Pitoiset
68abc07317 aco: fix emitting SMEM instructions with no operands on GFX6-GFX7
Like s_memtime.

Fixes dEQP-VK.glsl.shader_clock.* on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3407>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3407>
2020-01-16 08:18:18 +01:00
Vasily Khoruzhick
e5226cff75 lima: fix handling of reverse depth range
Looks like we need to handle cases when near > far and near == far.
In first case we just need to swap near and far, and in second we
need subtract epsilon from near if it's not zero.

Fixes 10 tests in dEQP-GLES2.functional.depth_range.*

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3400>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3400>
2020-01-16 01:57:05 +00:00
Ilia Mirkin
784b84d308 nvc0: disable xfb's which don't have a stride
No stride / no attributes means that nothing is being written to the
buffer. However it might still prevent primitives from being written out
to the other buffers. Disabling it entirely seems to fix it.

Fixes GTF-GL45.gtf30.GL3Tests.transform_feedback.transform_feedback_overflow

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-01-15 19:53:18 -05:00
Erico Nunes
9bf210ba98 lima/ppir: implement full liveness analysis for regalloc
The existing liveness analysis in ppir still ultimately relies on a
single continuous live_in and live_out range per register and was
observed to be the bottleneck for register allocation on complicated
examples with several control flow blocks.
The use of live_in and live_out ranges was fine before ppir got control
flow, but now it ends up creating unnecessary interferences as live_in
and live_out ranges may span across entire blocks after blocks get
placed sequentially.

This new liveness analysis implementation generates a set of live
variables at each program point; before and after each instruction and
beginning and end of each block.
This is a global analysis and propagates the sets of live registers
across blocks independently of their sequence.
The resulting sets optimally represent all variables that cannot share a
register at each program point, so can be directly translated as
interferences to the register allocator.

Special care has to be taken with non-ssa registers. In order to
properly define their live range, their alive components also need to be
tracked. Therefore ppir can't use simple bitsets to keep track of live
registers.

The algorithm uses an auxiliary set data structure to keep track of the
live registers. The initial implementation used only trivial arrays,
however regalloc execution time was then prohibitive (>1minute on
Cortex-A53) on extreme benchmarks with hundreds of instructions,
hundreds of registers and several spilling iterations, mostly due to the
n^2 complexity to generate the interferences from the live sets. Since
the live registers set are only a very sparse subset of all registers at
each instruction, iterating only over this subset allows it to run very
fast again (a couple of seconds for the same benchmark).

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3358>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3358>
2020-01-15 22:55:31 +00:00
Erico Nunes
7e2765fded lima/ppir: remove orphan load node after cloning
There are some cases in shades using control flow where the varying load
is cloned to every block, and then the original node is left orphan.
This is not harmful for program execution, but it complicates analysis
for register allocation as there is now a case of writing to a register
that is never read.
While ppir doesn't have a dead code elimination pass for its own
optimizations and it is not hard to detect when we cloned the last load,
let's remove it early.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3358>
2020-01-15 22:55:31 +00:00
Kristian H. Kristensen
a3a73d116c iris: Print warning and return *out = NULL when fd to syncobj fails
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-15 14:47:46 -08:00
Kristian H. Kristensen
1ac138694b iris: Advertise PIPE_CAP_NATIVE_FENCE_FD
Enables EGL_ANDROID_native_fence_sync.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-15 14:47:46 -08:00
Kenneth Graunke
e9f9a944d3 iris: Fix export of fences that have already completed.
After flushing batches, iris_fence_flush() asks the kernel whether
each batch's last_syncpt has already signalled or not.  (The idea is
that either the compute or render batch may not have actually had any
work queued up, so last_syncpt there might have been signalled a long
time ago.)  If it's already completed, we don't bother to record it.

A strange corner is the case of repeated flushes.  For example, we
might flush for some reason, and hit a glFlush(), and hit SwapBuffers.
It's possible for all the batches to have been flushed previously, -and-
for them to have actually completed.  In this case, we'll see that there
are no syncobj's to wait on, and record fence->count == 0.

This works fine internally - fence_finish can see count == 0 and realize
that it doesn't need to wait, for example.  But when working with native
FDs, we may be asked to export a fence with count == 0.  So we need an
actual synchronization primitive we can hand off.  Because all of the
relevant batches had been signalled when creating the fence, we want the
new dummy fence to be signalled as well.

So we just make a signalled syncobj and export it.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2020-01-15 14:47:46 -08:00
Robert Foss
6b9fce5d9e android: Fix whitespace issue
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-15 22:30:17 +00:00
Robert Foss
62adb6522b panfrost: Prefix schedule_program to prevent collision
Currently the schedule_program implementation being used is picked
at compile time, which on the Android platform means that the
bifrost compiler & scheduler is used for all targets, including
midgard based hardware.

This commit disambiguates between the two schedule_program functions.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-15 22:30:17 +00:00
Marek Olšák
c4daf2b485 radeonsi: merge si_compile_llvm and si_llvm_compile functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
68586bdd21 radeonsi: remove useless #includes
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
30b14ba67e radeonsi: move code for shader resources into si_shader_llvm_resources.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
da2c12af4b radeonsi: move geometry shader code into si_shader_llvm_gs.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
57bd73e229 radeonsi: remove llvm_type_is_64bit
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
194449a405 radeonsi: move tessellation shader code into si_shader_llvm_tess.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
d7c86b106c radeonsi: move si_insert_input_* functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
2020-01-15 21:54:55 +00:00
Marek Olšák
8ff8e68e42 radeonsi: work around an LLVM crash when using llvm.amdgcn.icmp.i64.i1
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
2020-01-15 20:17:23 +00:00
Marek Olšák
af3fbb410c radeonsi: fix si_build_wrapper_function for compute-based primitive culling
Fixes: 3b143369a5 "ac/nir, radv, radeonsi: Switch to using ac_shader_args"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
2020-01-15 20:17:23 +00:00
Marek Olšák
6d4993c942 radeonsi/gfx10: separate code for determining the number of vertices for NGG
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 15:06:34 -05:00
Marek Olšák
7a25521f92 radeonsi/gfx10: separate code for getting edgeflags from the gs_invocation_id VGPR
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 15:06:33 -05:00
Marek Olšák
cf65c6f0d2 radeonsi: move VS_STATE.LS_OUT_PATCH_SIZE a few bits higher to make space there
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 15:06:31 -05:00
Marek Olšák
34ef0c5083 radeonsi: make si_insert_input_* functions non-static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 15:06:29 -05:00
Marek Olšák
eeb4a11c11 ac/cull: don't read Position.Z if it's not needed for culling
It could be NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 15:06:20 -05:00
Marek Olšák
8070402a30 radeonsi: separate code computing info for small primitive culling
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 14:59:11 -05:00
Kenneth Graunke
0a1c47074b intel/compiler: Fix illegal mutation in get_nir_image_intrinsic_image
get_nir_image_intrinsic_image() was incorrectly mutating the value held
by the register which holds the intrinsic's first source (image index).

If this happened to be the register for an SSA def which is also used
elsewhere in the program, this meant that we would clobber that value
in subsequent uses.

Note that this only affects i965, because neither anv nor iris use the
binding table start sections, so nothing is ever added here.

Fixes KHR-GL46.compute_shader.resources-max on i965 with Eric Anholt's
MR !3240 applied.  That MR reorders SSBOs and ABOs, so that test uses
image 0 and SSBO 0, causing this code to brilliantly add binding table
index 45 to both the image (correct) and the SSBO (bzzt, wrong!).

Fixes: 09f1de97a7 ("anv,i965: Lower away image derefs in the driver")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404>
2020-01-15 19:25:35 +00:00
Rob Clark
b706a157c5 gitlab-ci: fix missing caselist.css/xsl
My best guess is that this was broken by d62dd8b0

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3413>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3413>
2020-01-15 19:03:56 +00:00
Jason Ekstrand
af6c2f4193 relnotes: Add Vulkan 1.2 2020-01-15 09:25:51 -06:00
Samuel Pitoiset
7f5462e349 radv: enable Vulkan 1.2
This bumps the Vulkan version to 1.2.128.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
68d6bead78 radv: implement Vulkan 1.2 features and properties
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
b3033198a8 radv: implement Vulkan 1.1 features and properties
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
a09ab76828 radv: update VK_KHR_timeline_semaphore for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
fab0aa9182 radv: update VK_KHR_uniform_buffer_standard_layout for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
3ff8d12458 radv: update VK_KHR_shader_subgroup_extended_types for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
af25c8d57b radv: update VK_KHR_shader_float_controls for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
5335bb6c39 radv: update VK_KHR_shader_float16_int8 for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
a73d01b1db radv: update VK_KHR_shader_atomic_int64 for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
83d1773a57 radv: update VK_KHR_imageless_framebuffer for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
b3bdb4e6ff radv: update VK_KHR_image_format_list for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
a80229941f radv: update VK_KHR_driver_properties for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
af883bf3dc radv: update VK_KHR_draw_indirect_count for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
b537be4368 radv: update VK_KHR_depth_stencil_resolve for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
5993f13b27 radv: update VK_KHR_create_renderpass2 for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
b2be00fbc1 radv: update VK_KHR_buffer_device_address for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
0eb26aae1c radv: update VK_KHR_8bit_storage for Vulkan 1.2
Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
b4eed4e548 radv: update VK_EXT_scalar_block_layout for Vulkan 1.2
Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
efdf9d8969 radv: update VK_EXT_sampler_filter_minmax for Vulkan 1.2
Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
65e215e6f3 radv: update VK_EXT_host_query_reset for Vulkan 1.2
Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Samuel Pitoiset
95ec0c050b radv: update VK_EXT_descriptor_indexing for Vulkan 1.2
Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-15 08:42:25 -06:00
Iván Briano
4ef3f7e3d3 anv: Enable Vulkan 1.2 support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-15 08:34:57 -06:00
Jason Ekstrand
c616627f63 anv: Implement the new core version property queries
Vulkan 1.2 introduces some new structures to get the properties and
features of a device from extensions that were promoted to core in 1.1
and 1.2.  This commit implements the new property queries and makes all
of the corresponding extension queries map to them.

Reviewed-by: Iván Briano <ivan.briano@intel.com>
2020-01-15 08:34:57 -06:00
Jason Ekstrand
a47152c622 anv: Implement the new core version feature queries
Vulkan 1.2 introduces some new structures to get the properties and
features of a device from extensions that were promoted to core in 1.1
and 1.2.  This commit implements the new feature queries and makes all
of the corresponding extension queries map to them.

Reviewed-by: Iván Briano <ivan.briano@intel.com>
2020-01-15 08:34:57 -06:00
Jason Ekstrand
721666e52a anv,nir: Lower quad_broadcast with dynamic index in NIR
This is required for the subgroupBroadcastDynamicId feature that was
added in Vulkan 1.2.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-15 08:34:57 -06:00
Jason Ekstrand
7e3e2ce702 anv: Bump the patch version to 131 2020-01-15 08:34:57 -06:00
Samuel Pitoiset
f33a68af63 vulkan/overlay: Fix for Vulkan 1.2
v2 (Jason Ekstrand):
 - Add duplicate hooks for both the 1.2 and KHR versions of
   vkCmdDraw[Indexed]IndirectCount.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-15 08:34:57 -06:00
Jason Ekstrand
75755e0eba turnip: Pretend to support Vulkan 1.2
It doesn't really support any Vulkan properly yet so why not claim 1.2?
This was an easier way of fixing the build than trying to roll it
forward to a later version of ANV's entrypoint generator scripts.
2020-01-15 08:34:57 -06:00
Jason Ekstrand
ac0c7ad2c2 vulkan: Update the XML and headers to 1.2.131
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-01-15 08:07:04 -06:00
Michel Dänzer
8775b742ea gitlab-ci: Stop using manual jobs for merge requests
They were causing trouble with Marge Bot: The project settings require
that the pipeline succeeds before a merge request (MR) can be merged,
otherwise Marge doesn't wait for the pipeline to succeed before merging
an MR assigned to her. But Marge can't start manual jobs, so she would
always time out waiting for pipelines with manual jobs.

To avoid this, use these rules:
* Run the pipeline by default for MRs and main project branches changing
  any files affecting it.
* For other MRs, run a single dummy job which always succeeds.
* Don't run any jobs for main project branch changes (e.g. from an MR
  having been merged) not affecting the pipeline.
* Allow jobs to be started manually on branches of forked projects, as
  before.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>
2020-01-15 10:31:01 +00:00
Pierre-Eric Pelloux-Prayer
7b0b085c94 radeonsi: drop the negation from fmask_is_not_identity
This change eases code reading ("fmask_is_identity = true" is clearer than
"fmask_is_not_identity = false").
Initialization is not changed so fmask_is_identity is false when a texture is
created.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
3a527eda7c radeonsi: unbind image before compute clear
It's not used and avoid infinite recursion when used from si_compute_expand_fmask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
c2df5389bb radeonsi: make sure fmask expand is done if needed
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2248
Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Pierre-Eric Pelloux-Prayer
b5e748b49b radeonsi: fix fmask expand compute shader
'coord' variable was using TGSI_WRITEMASK_XYZ so subsequent uses of
TGSI_WRITEMASK_W were dropped.
The result for a 2 samples program was:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  2: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  3: END

instead of the expected:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: MOV TEMP[0].w, IMM[0].yyyy
  2: LOAD TEMP[1], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  3: MOV TEMP[0].w, IMM[0].zzzz
  4: LOAD TEMP[2], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  5: MOV TEMP[0].w, IMM[0].yyyy
  6: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  7: MOV TEMP[0].w, IMM[0].zzzz
  8: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  9: END

This fixes half of https://gitlab.freedesktop.org/mesa/mesa/issues/2248

Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
2020-01-15 10:10:15 +00:00
Nataraj Deshpande
be08e6a449 egl/android: Restrict minimum triple buffering for android color_buffers
The patch restricts triple buffering as minimum at driver for android
color_buffers in order to fix onscreen performance hit for T-Rex and
Manhattan.

v2: Update min_buffer check condition (Tapani Pälli)
v3: further code cleanup (Eric Engestrom)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2332
Fixes: 0661c357c6 ("egl/android: Update color_buffers querying for buffer age")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>
2020-01-15 09:42:08 +00:00
Lionel Landwerlin
a014105498 anv: fix pipeline switch back for non pipelined states
Setting state base address can happen even before pipeline is
selected. Also we must ensure it is set to 3D for Gen12, we can't
switch back to an invalid pipeline value (UINT32_MAX).

v2: Reuse helpers (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b34422db5e ("anv: Implement Gen12 workaround for non pipelined state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
2020-01-15 11:14:43 +02:00
Samuel Pitoiset
fce28a7341 radv/gfx10: simplify some duplicated NGG GS code
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
2020-01-15 07:45:29 +00:00
Samuel Pitoiset
53b50be35c radv/gfx10: enable all CUs if NGG is never used
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
2020-01-15 07:45:29 +00:00
Samuel Pitoiset
5ff12322c9 radv: only use VkSamplerCreateInfo::compareOp if enabled
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
2020-01-15 08:16:15 +01:00
Iago Toral Quiroga
3f3ec07be5 v3d: fix bug when checking result of syncobj fence import
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
2020-01-15 07:53:58 +01:00
Jonathan Marek
222e127e39 st/mesa: run st_nir_lower_tex_src_plane for lowered xyuv/ayuv
Has the effect of removing the nir_tex_src_plane for these formats too.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
2020-01-15 02:20:00 +00:00
Jonathan Marek
a554b45d73 st/mesa: don't lower YUV when driver supports it natively
This fixes YUYV support on etnaviv.

Fixes: 7404833c "gallium: add handling for YUV planar surfaces"

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
2020-01-15 02:20:00 +00:00
Bas Nieuwenhuizen
4e3c81517b radv: Disable VK_EXT_sample_locations on GFX10.
Workaround for https://gitlab.freedesktop.org/mesa/mesa/issues/2163

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
2020-01-15 01:54:27 +00:00
Gurchetan Singh
6c978b1362 st/mesa: implement EGLImageTargetTexStorage
We can now support this extension.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
2020-01-15 01:18:54 +00:00
Gurchetan Singh
2f1032f8f2 st/mesa: refactor egl image binding a bit
We'll need it for egl image tex storage.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
2020-01-15 01:18:54 +00:00
Gurchetan Singh
be347863ba st/dri: track if image is created by a dmabuf
Will be used by EXT_EGL_image_storage later.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
2020-01-15 01:18:54 +00:00
Rob Clark
2629cb627c freedreno/ir3: rename instructions
Turns out this range of opcodes are more general purpose if/else/endif
instructions.

We should re-work tess to create a basic block and use normal flow
control.  And possibly (for a6xx+) optimize cases to use if/else/endif
when appropriate.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
2020-01-15 00:56:24 +00:00
Elie Tournier
22c5c54a4f nir/algebraic: sqrt(x)*sqrt(x) -> fabs(x)
total instructions in shared programs: 12840840 -> 12839341 (-0.01%)
instructions in affected programs: 122581 -> 121082 (-1.22%)
helped: 559
HURT: 0

total cycles in shared programs: 302505756 -> 302490031 (<.01%)
cycles in affected programs: 2022900 -> 2007175 (-0.78%)
helped: 1090
HURT: 130

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
2020-01-15 00:30:52 +00:00
Elie Tournier
6f394343b1 nir/algebraic: i2f(f2i()) -> trunc()
total instructions in shared programs: 12840968 -> 12840784 (<.01%)
instructions in affected programs: 17886 -> 17702 (-1.03%)
helped: 77
HURT: 0

total cycles in shared programs: 302508917 -> 302505592 (<.01%)
cycles in affected programs: 249964 -> 246639 (-1.33%)
helped: 70
HURT: 7

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
2020-01-15 00:30:52 +00:00
Eric Anholt
3d9a3d0be0 i965: Reuse the new core glsl_count_dword_slots().
The only difference I could see was treating interfaces like structs.
Maintain that case.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
2020-01-14 23:55:00 +00:00
Eric Anholt
bc4f089d01 mesa/st: Move the dword slot counting function to glsl_types as well.
To implement NIR-to-TGSI, we need to be able to get the size of the
uniform variable for the TGSI declaration, not just the
.driver_location.  With its location in mesa/st, drivers couldn't link
to it from nir-to-tgsi.

This feels like a common enough function to want, so let's share it in
the core compiler.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
2020-01-14 23:55:00 +00:00
Eric Anholt
4cabd4812a mesa/prog: Reuse count_vec4_slots() from ir_to_mesa.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
2020-01-14 23:55:00 +00:00
Eric Anholt
74ee3f76de mesa/st: Move the vec4 type size function into core GLSL types.
The only bit that gallium varied on was handling of bindless.  We can
retain previous behavior for count_attribute_slots() by passing in
"true" (though I suspect this is just giving a silly answer to a silly
question), and delete our recursive function from mesa/st.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
2020-01-14 23:55:00 +00:00
Eric Anholt
b807f7a43a mesa/st: Deduplicate the NIR uniform lowering code.
Just a little refactor as I go looking at the type size functions.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
2020-01-14 23:55:00 +00:00
Marek Olšák
8832a88434 radeonsi: move PS LLVM code into si_shader_llvm_ps.c
This is an attempt to clean up si_shader.c.

v2: don't move code that is not specific to LLVM

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
2020-01-14 18:46:07 -05:00
Marek Olšák
9b60b3ce93 radeonsi: remove always constant ballot_mask_bits from si_llvm_context_init
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
37916a66b1 radeonsi: fold si_create_function into si_llvm_create_func
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
42112010a3 radeonsi: rename si_shader_create -> si_create_shader_variant for clarity
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
63b5d85baa radeonsi: rename si_compile_tgsi_main -> si_build_main_function
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
f4ba457e1e radeonsi: clean up si_shader_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
03950473df radeonsi: merge si_tessctrl_info into si_shader_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
5fa2ab831e radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
18aaceae8d radeonsi: rename si_shader_info -> si_shader_binary_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
7f4a54d5bd radeonsi: remove TGSI from comments
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
b1badf4ad6 radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIR
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
b144d4be74 radeonsi: don't adjust depth and stencil PS output locations
this was for compatibility with TGSI

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Caio Marcelo de Oliveira Filho
3cc501be69 nir: Add missing nir_var_mem_global to various passes
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
2020-01-14 14:42:12 -08:00
Caio Marcelo de Oliveira Filho
d8440a3d2f spirv: Handle PhysicalStorageBuffer in memory barriers
PhysicalStorageBuffer is lowered to nir_var_mem_global, and
SPIR-V 1.5rev1 in section "3.25. Memory Semantics <id>" says

    UniformMemory

    Apply the memory-ordering constraints to StorageBuffer,
    PhysicalStorageBuffer, or Uniform Storage Class memory.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
2020-01-14 14:42:12 -08:00
Caio Marcelo de Oliveira Filho
1ec0d4fdff spirv: Drop EXT for PhysicalStorageBuffer symbols
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
2020-01-14 14:42:12 -08:00
Timur Kristóf
dfaa3c0af6 aco: Flip s_cbranch / s_cselect to optimize out an s_not if possible.
When possible, get rid of an s_not when all it does is invert the SCC,
and its successor s_cbranch / s_cselect can be inverted instead.

Also modify some parts of instruction_selection to take advantage of
this feature.

Example:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
s2: %3902 = s_cselect_b64 -1, 0, %3900:scc
s2: %407,  s1: %3903:scc = s_not_b64 %3902
s2: %3906,  s1: %3905:scc = s_and_b64 %407, %0:exec
p_cbranch_z %3905:scc
Can now be optimized to:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
p_cbranch_nz %3900:scc

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-14 21:21:06 +01:00
Timur Kristóf
c0f82165a7 aco: Optimize out s_and with exec, when used on uniform bitwise values.
Previously all booleans needed an s_and with exec when they were turned
into a scalar condition. However, this is not needed for uniform booleans.

v2 by Daniel Schürmann:
- Make the code more readable
v3 by Timur Kristóf:
- Fix regressions, make it work in wave32 mode

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-14 21:21:06 +01:00
Timur Kristóf
1c44129db3 aco: Don't skip combine_instruction when definitions[1] is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-14 21:21:06 +01:00
Timur Kristóf
338d03090f aco: Allow optimizing vote_all and nir_op_iand.
By adding an extra instruction, we can replace the operands of
the s_cselect_b64, which allows it to get picked up by the
optimizer when it looks for uniform booleans.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-14 21:21:06 +01:00
Timur Kristóf
d962bbd895 aco: Implement 64-bit constant propagation.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-14 21:21:06 +01:00
Alyssa Rosenzweig
6bd9c4dc57 panfrost: Fix linear depth textures
As pointed out by Boris, what we were calling PAN_LINEAR depth textures
was in fact u-interleaved tiled (!), but we never noticed since we
flipped the flag used for sampling, leading to all sorts of fun bugs
when attempting to directly acess depth textures from the CPU. Which
begs the question -- if what we called LINEAR was tiled, how do we
actually render linear depth textures? It turns out the flags for AFBC
form a mali_block_format 2-bit code just like their render-target
counterparts, so we can render to any of the above.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
2020-01-14 19:42:20 +00:00
Jason Ekstrand
7c16a1ae4e vulkan/wsi: Add a driconf option to force WSI to advertise BGRA8_UNORM first
The Aztec Ruins benchmark just grabs the first format in the list and
SRGB causes it to render washed out.  With this workaround, it renders
the same as OpenGL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
2020-01-14 19:27:13 +00:00
Caio Marcelo de Oliveira Filho
edf6a40cb2 intel/fs: Only use SLM fence in compute shaders
Fixes: b390ff3517 ("intel/fs: Add support for SLM fence in Gen11")
Fixes: e142061399 ("intel/fs: Implement scoped_memory_barrier")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-14 10:55:48 -08:00
Marek Olšák
9e699ae690 radeonsi: actually enable VBOs in user SGPRs
Fixes: 363b4027fc - radeonsi: put up to 5 VBO descriptors into user SGPRs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-14 13:42:36 -05:00
Marek Olšák
f341db3e17 radeonsi: fix assertion and other failures in si_emit_graphics_shader_pointers
The assertion was failing.

Fixes: 363b4027fc - radeonsi: put up to 5 VBO descriptors into user SGPRs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-14 13:42:36 -05:00
Rhys Perry
cc3ef3643a nir/algebraic: a & ~(a >> 31) -> imax(a, 0)
Found in some Doom shaders

Totals from affected shaders:
SGPRS: 30056 -> 30064 (0.03 %)
VGPRS: 28024 -> 28024 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 4278648 -> 4270852 (-0.18 %) bytes
Max Waves: 1476 -> 1476 (0.00 %)
Instructions: 835287 -> 833338 (-0.23 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089>
2020-01-14 17:54:40 +00:00
Marco Felsch
1607123ae7 etnaviv: Fix assert when try to accumulate an invalid fd
Check if it is a valid fd before merging it to the context's fd.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
2020-01-14 17:40:10 +00:00
Afonso Bordado
22217f24ec pan/midgard: Fix midgard_compile.h includes
We now use enum mali_format which is defined in panfrost-job.h

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243>
2020-01-14 17:16:11 +00:00
Lionel Landwerlin
a19cdf989b anv: only use VkSamplerCreateInfo::compareOp if enabled
The spec says nothing about the validity of the compareOp field when
compareEnable is false.

v2: use vulkan enum to pick default value (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>
2020-01-14 16:40:16 +00:00
Rhys Perry
d8e05edbd9 nir/sink,nir/move: move/sink nir_op_mov
Can uncover opportunities to move other instructions. This can increase
register usage, but that doesn't seem to actually happen.

This optimizes a pattern of a load_per_vertex_input followed by several
moves and then a store_output in a different block.

v2: add nir_move_copies to make it optional

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Acked-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
2020-01-14 13:56:45 +00:00
Rhys Perry
04fac72ec7 nir/sink,nir/move: move/sink load_per_vertex_input
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
2020-01-14 13:56:45 +00:00
Tomeu Vizoso
22d976454f gitlab-ci: Consolidate container and build stages for LAVA
Use the normal build job to also prepare the artifacts for LAVA jobs.

For that, the build container needs to also build the test suites,
kernel, ramdisk, etc.

Then the build job will place the just-built Mesa in the ramdisk and the
test job can generate a LAVA job and point to those artifacts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295>
2020-01-14 13:17:24 +00:00
Rhys Perry
f978e0e516 aco: add integer min/max to can_swap_operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
f92a89a979 aco: improve readfirstlane after uniform LDS loads
Totals from affected shaders:
SGPRS: 976 -> 968 (-0.82 %)
VGPRS: 580 -> 584 (0.69 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 106032 -> 103076 (-2.79 %) bytes
Max Waves: 237 -> 237 (0.00 %)
Instructions: 19452 -> 18740 (-3.66 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
92ace0bb31 aco: replace extract_vector with copies
Helps a small number of small shaders with situations like this:
a = p_create_vector ...
b = p_extract_vector a, 3
and copy propagation can't be done

Totals from affected shaders:
SGPRS: 14304 -> 14416 (0.78 %)
VGPRS: 8716 -> 6592 (-24.37 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 184664 -> 176888 (-4.21 %) bytes
Max Waves: 6260 -> 6260 (0.00 %)
Instructions: 35561 -> 33617 (-5.47 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
20d869079d aco: allow input modifiers on v_cndmask_b32
Totals from affected shaders:
SGPRS: 594099 -> 594019 (-0.01 %)
VGPRS: 441016 -> 441124 (0.02 %)
Spilled SGPRs: 101 -> 101 (0.00 %)
Spilled VGPRs: 18 -> 18 (0.00 %)
Code Size: 30266652 -> 30125256 (-0.47 %) bytes
Max Waves: 67044 -> 67057 (0.02 %)
Instructions: 5753097 -> 5726607 (-0.46 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
f9405ceb8a aco: don't move literal to reg when making an instruction VOP3 on GFX10
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 163398 -> 163398 (0.00 %)
VGPRS: 143820 -> 143820 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 13065744 -> 13044308 (-0.16 %) bytes
Max Waves: 18921 -> 18921 (0.00 %)
Instructions: 2514644 -> 2509285 (-0.21 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
e686e4765e aco: add min(-max(), ) and max(-min(), ) optimization
No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
fa8357eb70 aco: improve clamp optimization
Not sure why it checked the use count, it doesn't apply the constants.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 269409 -> 269745 (0.12 %)
VGPRS: 238120 -> 238132 (0.01 %)
Spilled SGPRs: 305 -> 305 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 22908584 -> 22904672 (-0.02 %) bytes
Max Waves: 20217 -> 20217 (0.00 %)
Instructions: 4275312 -> 4263869 (-0.27 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 155409 -> 155233 (-0.11 %)
VGPRS: 153072 -> 153072 (0.00 %)
Spilled SGPRs: 269 -> 269 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 14650824 -> 14650396 (-0.00 %) bytes
Max Waves: 9609 -> 9609 (0.00 %)
Instructions: 2762802 -> 2755517 (-0.26 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
edc888ccb1 aco: fix clamp optimization
We can't do the optimization if there are neg/abs in-between.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
f664cb01ec aco: improve creation of v_madmk_f32/v_madak_f32
Using needs_vop3 check was flawed because it would only combine the
literal if the first operand is the literal. If the second or third
operand is the literal, then needs_vop3 will be true and the literal will
not be combined.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 782051 -> 782051 (0.00 %)
VGPRS: 630048 -> 630048 (0.00 %)
Spilled SGPRs: 195 -> 195 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 54743740 -> 54585548 (-0.29 %) bytes
Max Waves: 67340 -> 67340 (0.00 %)
Instructions: 10182030 -> 10182030 (0.00 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 701990 -> 699590 (-0.34 %)
VGPRS: 566632 -> 566784 (0.03 %)
Spilled SGPRs: 218 -> 218 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 49173564 -> 49007856 (-0.34 %) bytes
Max Waves: 59650 -> 59612 (-0.06 %)
Instructions: 9315135 -> 9293330 (-0.23 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
15e25da3e5 aco: take advantage of GFX10's constant bus limit and VOP3 literals
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 2397159 -> 2392494 (-0.19 %)
VGPRS: 1756036 -> 1753920 (-0.12 %)
Spilled SGPRs: 461 -> 470 (1.95 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 110287304 -> 109946304 (-0.31 %) bytes
Max Waves: 318341 -> 318475 (0.04 %)
Instructions: 21019327 -> 20533618 (-2.31 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
Max Waves: 0 -> 0 (0.00 %)
Instructions: 0 -> 0 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
9c2d37308f aco: allow an extra SGPR with multiple uses to be applied to VOP3
This is in a separate patch from the apply_sgprs() rewrite so that the
rewrite can be more easily tested.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 3056 -> 3056 (0.00 %)
VGPRS: 1632 -> 1632 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 156468 -> 156304 (-0.10 %) bytes
Max Waves: 288 -> 288 (0.00 %)
Instructions: 29510 -> 29469 (-0.14 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 2984 -> 2984 (0.00 %)
VGPRS: 1616 -> 1616 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 156132 -> 155968 (-0.11 %) bytes
Max Waves: 289 -> 289 (0.00 %)
Instructions: 29426 -> 29385 (-0.14 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
f4c2c90e1a aco: allow applying two sgprs to an instruction
We could create VALU instructions which read two sgprs, but only if isel
created an instruction which already read one of them.

This change is in a separate patch from the apply_sgprs() rewrite so that
it can be tested if the rewrite affected anything.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 216 -> 216 (0.00 %)
VGPRS: 64 -> 64 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 1756 -> 1708 (-2.73 %) bytes
Max Waves: 120 -> 120 (0.00 %)
Instructions: 312 -> 300 (-3.85 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 216 -> 216 (0.00 %)
VGPRS: 64 -> 64 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 1784 -> 1736 (-2.69 %) bytes
Max Waves: 120 -> 120 (0.00 %)
Instructions: 319 -> 307 (-3.76 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
7da07ca3e4 aco: follow through temporary when merging tests into constant comparisons
This can happen with v_mov_b32(s_mov_b32(literal))

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 632 -> 632 (0.00 %)
VGPRS: 492 -> 492 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 77488 -> 76928 (-0.72 %) bytes
Max Waves: 67 -> 67 (0.00 %)
Instructions: 14426 -> 14332 (-0.65 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 632 -> 632 (0.00 %)
VGPRS: 492 -> 492 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 77512 -> 76952 (-0.72 %) bytes
Max Waves: 67 -> 67 (0.00 %)
Instructions: 14432 -> 14338 (-0.65 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
dc6c35e1c3 aco: be more careful with literals in combine_salu_{n2,lshl_add}
No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
fcf52eb42d aco: add check_vop3_operands()
This will be useful when taking advantage of GFX10 features.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
cef7879719 aco: rewrite apply_sgprs()
This will make it easier to apply two different sgprs (for GFX10) or apply
the same sgpr twice (just remove the break).

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
0be7409069 aco: rewrite literal combining
Should make taking advantage of GFX10's increased constant bus limit and
VOP3 literals easier.

No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
84b9f3786b aco: improve can_use_VOP3()
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
3cb98ed939 aco: combine two sgprs into a VALU if they're the same
This was supposed to be done before but it wasn't done correctly and
everywhere.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 784680 -> 786128 (0.18 %)
VGPRS: 574012 -> 573892 (-0.02 %)
Spilled SGPRs: 461 -> 461 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 45477088 -> 45478172 (0.00 %) bytes
Max Waves: 81294 -> 81277 (-0.02 %)
Instructions: 8657970 -> 8622483 (-0.41 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 780664 -> 782072 (0.18 %)
VGPRS: 573880 -> 573760 (-0.02 %)
Spilled SGPRs: 629 -> 629 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 45445244 -> 45448340 (0.01 %) bytes
Max Waves: 81178 -> 81161 (-0.02 %)
Instructions: 8649902 -> 8614918 (-0.40 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
c240c1aecf aco: apply literals to split mads
Removing the return is also needed to apply literals to mads (which can be
done on GFX10).

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 368787 -> 367555 (-0.33 %)
VGPRS: 312436 -> 312448 (0.00 %)
Spilled SGPRs: 461 -> 461 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 26113388 -> 26098260 (-0.06 %) bytes
Max Waves: 35982 -> 35982 (0.00 %)
Instructions: 5038670 -> 5028941 (-0.19 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 369843 -> 368659 (-0.32 %)
VGPRS: 317224 -> 317196 (-0.01 %)
Spilled SGPRs: 629 -> 629 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 26310540 -> 26295156 (-0.06 %) bytes
Max Waves: 36324 -> 36326 (0.01 %)
Instructions: 5073957 -> 5064164 (-0.19 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:28 +00:00
Rhys Perry
8f10e48745 aco: update IR validator
GFX10 increased the constant bus limit and allowed literals on VOP3

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
2020-01-14 12:56:27 +00:00
Rhys Perry
1ffacc3ce1 nir/lower_gs_intrinsics: add option for per-stream counts
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422>
2020-01-14 12:11:14 +00:00
Rhys Perry
9fb0c2e033 nir/divergence: handle load_primitive_id in GS
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2323>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2323>
2020-01-14 11:29:44 +00:00
Erik Faye-Lund
9aab36b6eb mesa/st: use float literals
This removes a warning on MSVC.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2020-01-14 12:01:29 +01:00
Erik Faye-Lund
fcdd3c866b gallium: fix a warning
On some platforms (like Win64), unsigned long is 32-bit, so the first
cast doesn't do anything, and the compiler complains about an implicit
cast to a smaller type. So let's cast to an uintptr_t instead first,
as that's large enough on all platforms.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2020-01-14 12:01:05 +01:00
Erik Faye-Lund
1a1e5a763a st/wgl: eliminate implicit cast warning
I get warnings on MSVC for these implicit casts. Let's use explicit
casts instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2020-01-14 12:01:00 +01:00
Erik Faye-Lund
d5c0fbfd78 util: initialize float-array with float-literals
We currently initialize this float-array with double-literals. Some
compilers generate warnings for this, so let's switch these to
float-literals instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2020-01-14 12:00:27 +01:00
Lionel Landwerlin
b34422db5e anv: Implement Gen12 workaround for non pipelined state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
2020-01-14 11:52:36 +02:00
Lionel Landwerlin
b8fbb39ab2 iris: Implement Gen12 workaround for non pipelined state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
2020-01-14 11:52:36 +02:00
Vasily Khoruzhick
55b0aa436e lima: add new findings to texture descriptor
Lower 8 bits of unknown_1_3 seems to be min_lod,
rest of 4 bits + miplevels are max_lod and min_mipfilter seems to be
lod bias. All are in fixed format with 4 bit integer and 4 bit fraction,
lod_bias also has sign bit.

Blob also seems to do some magic with lod_bias if min filter is nearest --
it adds 0.5 to lod_bias in this case. Same story when all filters are
nearest and mipmapping is enabled, but in this case it subtracts 1/16
from lod_bias.

Fixes 134 dEQP tests in dEQP-GLES2.functional.texture.*

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
2020-01-13 22:50:36 -08:00
Kenneth Graunke
a9bd0668d5 intel: Use similar brand strings to the Windows drivers
This updates our product name strings to match the ones reported
by the Windows driver, which is typically the marketing name.

We retain a platform abbreviation and GT level in parenthesis so that
we're able to distinguish similar parts more easily, helping us better
understand at a glance which GPU a bug reporter has.

Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
2020-01-13 19:42:35 -08:00
Kenneth Graunke
f63d6260d1 iris: Simplify iris_get_renderer_string()
We use gen_get_device_name() instead of PCI ID list munging.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
2020-01-13 19:42:30 -08:00
Kenneth Graunke
44bad9c31a i965: Simplify brw_get_renderer_string()
This stops using driGetRendererString() in favor of a simple snprintf().
This should have the same functionality on 64-bit systems, but drops
a "x86/MMX/SSE2" suffix on 32-bit systems.  (People shouldn't be using
the GL_RENDERER string to check for CPU features...)

We also use gen_get_device_name() instead of PCI ID list munging.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
2020-01-13 19:42:22 -08:00
Kenneth Graunke
50c47ba49e Revert "nir: assert that nir_lower_tex runs after lowering derefs"
This reverts commit 4cda61f11e for now,
as it appears to break i965 CI (32,000+ failures).  Rob and I suspect
we need to do the equivalent of 1c6a2efa06
on i965 - we are doing nir_lower_tex and brw_nir_lower_resources in the
wrong order and that's likely triggering this condition.  Once we fix
that, we should put this patch back.
2020-01-13 17:37:40 -08:00
Erik Faye-Lund
09b37ba65f zink: fixup initialization of operand_mask / num_extra_operands
This doesn't change behavior, but makes the code a bit easier to read.
Both values are zero, but I somehow swapped the logical meaning of them
when initializing.
2020-01-14 01:06:59 +00:00
Eric Anholt
3be4b89c03 mesa: Fix detection of invalidating both depth and stencil.
Fixes an extra 1024x1024x4 MSAA Z/S store on WebGL fishtank on cheza.

Reported-by: Dave Airlie <airlied@redhat.com>
Fixes: db2ae51121 ("mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3370>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3370>
2020-01-13 23:37:54 +00:00
Rob Clark
1c6a2efa06 mesa/st: lower samplers before nir_lower_tex
Fixes incorrect lowering of YUV samplers when there are non-yuv
samplers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
2020-01-13 23:19:49 +00:00
Rob Clark
4cda61f11e nir: assert that nir_lower_tex runs after lowering derefs
It isn't going to do the right thing, because texture_index/
sampler_index defaults to zero.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
2020-01-13 23:19:49 +00:00
Gurchetan Singh
d72f178753 i965: support EXT_EGL_image_storage
i965 can support this.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:36 -08:00
Gurchetan Singh
b1c266d5fa i965: refactor intel_image_target_texture_2d
intel_image_target_texture_tex_storage can reuse much of this
code.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:32 -08:00
Gurchetan Singh
34fe560cd6 i965: track if image is created by a dmabuf
Will be used by EXT_EGL_image_storage later.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:27 -08:00
Gurchetan Singh
bf576772ab dri_util: add driImageFormatToSizedInternalGLFormat function
This is needed to implement the EXT_EGL_image_storage spec:

"If <target> is GL_TEXTURE_2D, then the resultant texture must have a
sized internal format which is colorspace and size compatible with the
dma-buf.  If the GL is unable to determine such a format, the error
INVALID_OPERATION is generated."

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:22 -08:00
Gurchetan Singh
b68ff2b873 glapi / teximage: implement EGLImageTargetTexStorageEXT
Check various parts of the EXT_EGL_image_storage spec, and add a
new vfunc for drivers implementing it.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:18 -08:00
Gurchetan Singh
1fe23d0e22 teximage: split out helper from EGLImageTargetTexture2DOES
The major differences between EXT_EGL_image_storage and
EGLImageTargetTexture2DOES are:

(1) The texture target is made immutable
(2) EXT_EGL_image_storage supports non-2D targets.

We can reuse EGLImageTargetTexture2D and FreeTextureImageBuffer
for (1) pretty easily.  For (2), let's just not support the
complicated targets.  Let's reuse aspects of the
EGLImageTargetTexture2DOES implementation.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-13 14:57:07 -08:00
Jason Ekstrand
7978f2401b anv: Memset array properties
This is probably better than possibly leaving those bytes uninitialized
even if the app will theoretically not use them.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
2020-01-13 22:33:55 +00:00
Jason Ekstrand
d36eed3e69 anv: Don't over-advertise descriptor indexing features
We should only advertise sub-features if we advertise the extension.

Fixes: 6e230d7607 "anv: Implement VK_EXT_descriptor_indexing"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
2020-01-13 22:33:55 +00:00
Jason Ekstrand
d7ff137445 intel/blorp: Fill out all the dwords of MI_ATOMIC
This makes us valgrind clean again.

Fixes: 9175c7058e "intel/blorp: Make blorp update the clear color..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
2020-01-13 21:48:00 +00:00
Tomeu Vizoso
40dd418e14 gitlab-ci: Upgrade kernel for LAVA jobs to v5.5-rc5
Some fixes got in that should prevent hangs in lima jobs.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3363>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3363>
2020-01-13 21:26:11 +00:00
Daniel Schürmann
05c81875d7 aco: fix unconditional demote_to_helper
This patch fixes an out-of-bounds access on p_exit_early
and binds the exec register to the correct operand.

Fixes: 2ea9e59e8d ('aco: move s_andn2_b64 instructions out of the p_discard_if')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3347>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3347>
2020-01-13 21:08:41 +00:00
Marek Olšák
2bb88b2fdc radeonsi: don't enable VBOs in user SGPRs if compute-based culling can be used
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
363b4027fc radeonsi: put up to 5 VBO descriptors into user SGPRs
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs

We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.

Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
220d00314f ac,radeonsi: increase the maximum number of shader args and return values
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
ef253c6789 radeonsi: simplify si_set_vertex_buffers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
312e04689a radeonsi: don't allow draw calls with uninitialized VS inputs
These always hang, because vertex buffer descriptors are not set up.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
c278c73f13 radeonsi: add si_context::num_vertex_elements
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
1e03b63b3b radeonsi: rename desc_list_byte_size -> vb_desc_list_alloc_size
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Lionel Landwerlin
2cc14bd7b8 anv: set stencil layout for input attachments
If an input attachment has a stencil format, we need to set this.

v2: Fish out VkAttachmentReferenceStencilLayoutKHR from
    VkAttachmentReference2KHR::pNext (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: c1c346f166 ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891>
2020-01-13 21:57:33 +02:00
Jason Ekstrand
21bc16a723 anv: Drop an unused variable 2020-01-13 12:20:48 -06:00
Jason Ekstrand
d3737002ee nir/lower_atomics_to_ssbo: Also lower barriers
This is more correct for a pass which is supposed to completely lower
away atomic counters.  It also lets us stop supporting atomic counter
barriers in most of the drivers.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
e40b11bbcb nir: Rename nir_intrinsic_barrier to control_barrier
This is a more explicit name now that we don't want it to be doing any
memory barrier stuff for us.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
bd3ab75aef intel/nir: Stop adding redundant barriers
Now that both GLSL and SPIR-V are adding shared and tcs_patch barriers
(as appropreate) prior to the nir_intrinsic_barrier, we don't need to do
it ourselves in the back-end.  This reverts commit
26e950a5de01564e3b5f2148ae994454ae5205fe.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
ba43b66dc9 nir/glsl: Emit memory barriers as part of barrier()
The GLSL barrier() intrinsic does an implicit shared memory barrier in
compute shaders and an implicit TCS patch output barrier in tessellation
control shaders.  We'd like NIR's barrier intrinsic to just be a control
flow barrier and not have memory implications.  To satisfy this, we need
to add an extra memory barrier in front of each nir_intrinsic_barrier.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
a4125b4d26 spirv: Add output memory semantics to OpControlBarrier in TCS
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
2365520c9d spirv: Add a workaround for OpControlBarrier on old GLSLang
As per the Vulkan memory model, the proper translation of GLSL barrier()
is an OpControlBarrier with a scope of Workgroup and semantics of
Acquire, Release, and WorkgroupMemory.  Older versions of GLSLang gave
an OpControlBarrier with semantics of None so we need to patch it up on
those versions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
60097cc840 nir: Add a new memory_barrier_tcs_patch intrinsic
Right now, it's implemented as a no-op for everyone.  For most drivers,
it's a switch case in the NIR -> whatever which just breaks.  For ir3,
they already have code to delete tessellation barriers so we just add a
case to also delete memory_barrier_tcs_patch.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:47 +00:00
Jason Ekstrand
f2eece773c llmvpipe: No-op implement more barriers
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:46 +00:00
Jason Ekstrand
3498ab98f5 nir: Handle barriers with more granularity in combine_stores
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:46 +00:00
Jason Ekstrand
f09db0bed5 nir: Handle more barriers in dead_write and copy_prop
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:46 +00:00
Jason Ekstrand
ada49bae5e intel/vec4: Support scoped_memory_barrier
Fixes: 06aecb14c0 "anv: Implement VK_KHR_vulkan_memory_model"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
2020-01-13 17:23:46 +00:00
Andreas Baierl
40aef2bf3e lima: Add stencil support
This re-enables and fixes support for stencil buffer.

It fixes 365 stencil related deqp tests. All tests that use INCR, INCR_WRAR,
DECR and DECR_WRAP as a stencil op still fail, but they also fail with the
blob, so we may ignore that for now.
We still have dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked
failing, which is strange because it's the only one out of the
depth_stencil_clear.* set.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-13 16:11:37 +00:00
Andreas Baierl
2ce71494f1 lima/parser: Make rsw alpha blend parsing more readable
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-13 16:11:37 +00:00
Boris Brezillon
440b0d6eec panfrost: Remove unneeded phi nodes
Add a pass to remove unneeded phi nodes as done in other drivers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3294>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3294>
2020-01-13 14:09:47 +00:00
Rhys Perry
809c8feb92 aco: check if multiplication/clamp is live when applying output modifier
It's possible that a multiplication/clamp is dead code and the single use
is from a different user.

Fixes portal rendering in Path of Exile when global illumination is
enabled.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
ef8abfa790 aco: disable add combining for ds_swizzle_b32
ds_bpermute_b32/ds_permute_b32 are fine, I think

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
69bed1c918 aco: don't DCE atomics with return values
We don't create atomics with definitions if they are not used in NIR, but
our own DCE can remove the uses if an export turns out to be null.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
8f291dc146 aco: set exec_potentially_empty for demotes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
21eafe30df aco: better handle neg/abs of sgprs
isel/label_instruction currently doesn't create these but we should
probably check anyway.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
f29a5a205c aco: check usesModifiers() when identifying a neg/abs
This was fine because a literal used to mean that it didn't use modifiers,
but now VOP3 can take a literal on GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
46fb341b8d aco: handle omod successors with the constant in the first operand
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
7ce244b7d1 aco: handle VOP3 modifiers when combining a constant comparison's NaN test
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:26:43 +00:00
Rhys Perry
bbac52873f aco: fix uninitialized data in the binary
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:25:32 +00:00
Rhys Perry
fcd6d83245 aco: fix imageSize()/textureSize() with large buffers on GFX8
Tested on Navi by using dEQP-VK.image.image_size.buffer.* and the GFX8
path with the size multipled by the stride.
dEQP-VK.image.image_size.buffer.* was also run with the tests modified to
use a 96bit format.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:25:32 +00:00
Rhys Perry
49bcd06f97 aco: set vm for pos0 exports on GFX10
RADV's LLVM backend and radeonsi does the same thing.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
2020-01-13 13:25:32 +00:00
Daniel Ogorchock
632885741f panfrost: Fix headers and gpu_headers memory leak
The per-batch headers/gpu_headers dynarrays need to be freed during the
batch cleanup to prevent leaking.

Signed-off-by: Daniel Ogorchock <daniel.ogorchock@garmin.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
2020-01-13 09:11:35 +00:00
Daniel Ogorchock
2848edc0ef panfrost: Fix panfrost_bo_access memory leak
The bo access needs to be freed prior to removing it from its hash
table. This prevents leaking them over time.

Signed-off-by: Daniel Ogorchock <daniel.ogorchock@garmin.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
2020-01-13 09:11:35 +00:00
Samuel Pitoiset
ecace26853 radv/gfx10: improve performance for TES using PrimID but not exporting it
This field is for the primitive ID export to the fragment shader.
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-13 08:14:47 +01:00
Samuel Pitoiset
1db276ba23 radv/gfx10: add support for NGG passthrough mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-13 08:14:45 +01:00
Samuel Pitoiset
471738e97b radv/gfx10: do not declare LDS for NGG if useless
Only needed for NGG without passthrough mode or for NGG streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-13 08:14:43 +01:00
Samuel Pitoiset
0758f645d0 radv/gfx10: determine if a pipeline is eligible for NGG passthrough
It can't be enabled for geometry shaders, for NGG streamout and
for vertex shaders that export the primitive ID. NGG passthrough
requires that LDS isn't used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-13 08:14:40 +01:00
Samuel Pitoiset
c65015f83c radv/gfx10: disable vertex grouping
RadeonSI and AMDVLK does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-13 08:14:38 +01:00
Ilia Mirkin
201b88a93b nvc0: treat all draws without color0 broadcast as MRT
Per the semi-recently-released NVIDIA docs, when this bit is not
enabled, then the result for RT[0] will be used. So if e.g. only a
single RT is drawn to and it's not RT[2], the results will not be
visible. Fixes
GTF-GL45.gtf33.GL3Tests.explicit_attrib_location.explicit_attrib_location_pipeline
which was failing due to a frag shader outputting only to location=2.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-01-12 12:11:16 -05:00
Ilia Mirkin
3e9aacb139 gm107/ir: avoid combining geometry shader stores at 0x60
This corresponds to gl_PrimitiveID and gl_Layer. When both of these are
stored in a single AST.64 or AST.128 operation, then it appears as
though the whole store fails. Fixes the recently extended
glsl-1.50-transform-feedback-builtins piglit, and also
gtf30.GL3Tests.transform_feedback.transform_feedback_builtins.

The issue was reproduced on GM107 and GP108 but not GK208 nor GK104.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-01-12 12:11:16 -05:00
Ilia Mirkin
3be708eb31 nvc0: add dummy reset status support
Perhaps in a future implementation, such events could be passed back to
the driver, or queried directly. However for now, this is required for
GL 4.3 robustness contexts.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-01-12 12:11:16 -05:00
Ilia Mirkin
838118462e nv50,nvc0: fix destination coordinates of blit
The fix was found by Karol Herbst a long time ago, but it was unclear
why it helped or if it would create additional problems. This change
adds a comment that explains what's going on, and in the process also
normalizes the nv50 implementation to match.

The coordinates which are fed to gl_Position map directly to pixel
coordinates, since the viewport transform is disabled. If the
framebuffer is MSAA, then that doesn't affect the pixel coordinates at
all, it's just that each pixel has multiple samples.

Note that this makes it really clear that this approach is inappropriate
for EXT_framebuffer_multisample_blit_scaled, and also the 3d path will
fail terribly for direct copies. Thankfully the 2d path normally takes
care of this.

Fixes KHR-GL43.packed_depth_stencil.blit.depth32f_stencil8 as well as
scaling issues in a number of EXT_framebuffer_multisample-related piglit
tests (although they continue to fail due to inaccuracies).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2020-01-12 12:11:16 -05:00
Bas Nieuwenhuizen
bfd9e7ff24 radv: Use new scanout gfx9 metadata flag.
This updates for the new metadata ABI in radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3244>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3244>
2020-01-12 14:01:59 +01:00
Vasily Khoruzhick
f06be79457 lima: fix PIPE_CAP_* to mark features that aren't supported yet
lima doesn't support alpha test, flat shading, two-sided color nor
clip planes. We can enable these caps when corresponding hw features
are implemented in the driver.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-12 00:10:04 -08:00
Vasily Khoruzhick
8a421135fa lima: implement polygon offset
Fixes some of dEQP-GLES2.functional.polygon_offset.* tests and shadows in Q3A.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-12 00:10:04 -08:00
Vasily Khoruzhick
b936b1f9b4 lima: fix viewport clipping
Apparently Mali4x0 doesn't do viewport clipping, so anything rendered beyond viewport
is still rendered. Looks like we need to use scissors to do clipping.

Fixes most of dEQP-GLES2.functional.clipping.*, 6 out of 7 remaining failures
fail on blob as well. Remaining [1] fails on many other gallium drivers.

[1] dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z

Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-12 00:10:04 -08:00
Vasily Khoruzhick
997a30d709 lima: fix PLBU_CMD_PRIMITIVE_SETUP command
Apparently it doesn't depend on primitive type, the value
only depends on whether we specify point size via PLBU command --
bit 12 is set in this case

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-12 00:10:04 -08:00
Timothy Arceri
6bafd230e3 glsl: fix potential bug in nir uniform linker
The state value of main_uniform_storage_index will be wrong for
add_parameter() when find_and_update_previous_uniform_storage()
finds a uniform if there is more than 1 uniform used in
multiple shader stages.

The new code is also simpler.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-12 11:02:20 +11:00
Christian Gmeiner
db7967ef9f etnaviv: add deqp debug option
This new debug option will fake some driver CAPs to be able to run dEQP
for GLES3.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351>
2020-01-11 22:05:35 +00:00
Timur Kristóf
44a6b17df7 aco/wave32: Set the definitions of v_cmp instructions to the lane mask.
The output of v_cmp instructions is s1 (a single SGPR) in wave32 mode,
as opposed to s2 (an SGPR-pair) in wave64 mode.
A couple of cases where this should have been fixed were omitted from
the previous patch by mistake.

Fixes: e0bcefc3a0
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-11 20:15:53 +01:00
Alyssa Rosenzweig
59d30fd4bc pan/midgard: Support indirect UBO offsets
...in case we have arrays in a UBO block that we'd like to access
indirectly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3352>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3352>
2020-01-10 17:48:42 -05:00
Francisco Jerez
c20dc9b836 intel/fs: Make implied_mrf_writes() an fs_inst method.
This will be convenient in a later commit enabling SIMD32 fragment
shaders, and happens to fix the calculation for MATH instructions
which is currently inaccurate for SIMD-lowered instructions on Gen4-5
platforms (all of them on Gen4 in SIMD16 mode), since it was based on
the shader's dispatch width rather than on the actual execution size
of the instruction.

This causes some shader-db noise on Gen4 due to the more compact
register allocation interacting with the SEND dependency workarounds,
but otherwise no major changes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-10 11:02:30 -08:00
Francisco Jerez
591f146fd2 intel/fs/cse: Fix non-deterministic behavior due to inaccurate liveness calculation.
The liveness calculation done by the local CSE pass in order to prune
AEB entries whose sources are no longer live is currently inaccurate,
because the live intervals are calculated once at the beginning of the
pass, so they don't take into account any of the copy instructions
inserted by the CSE pass as it makes progress.  However the IP counter
used in that calculation is based on the start_ip of the basic block,
which is updated automatically whenever any instructions are inserted
into the CFG.  This causes the IP counter and liveness intervals to
get out of sync in programs with multiple basic blocks, causing the
CSE pass to toss AEB entries prematurely, which can lead to missed
optimization opportunities rather non-deterministically.

On BDW this leads to the following shader-db changes:

 total instructions in shared programs: 14952488 -> 14951763 (-0.00%)
 instructions in affected programs: 45416 -> 44691 (-1.60%)
 helped: 40
 HURT: 4

 total spills in shared programs: 20989 -> 20970 (-0.09%)
 spills in affected programs: 103 -> 84 (-18.45%)
 helped: 3
 HURT: 0

 total fills in shared programs: 24981 -> 24926 (-0.22%)
 fills in affected programs: 127 -> 72 (-43.31%)
 helped: 3
 HURT: 0

In addition it avoids a number of regressions in combination with some
of the optimization changes I'm working on for SIMD32, which would
have made CSE more effective...  Causing it to be less effective
elsewhere in the program astonishingly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-10 11:02:06 -08:00
Francisco Jerez
cc0ea482ad intel/fs: Fix nir_intrinsic_load_barycentric_at_sample for SIMD32.
For uniform sample ID, only the first channel of msg_data will be
initialized.  We need to pass that component only to the SEND message
for SIMD lowering to unzip the descriptor source correctly.

Fixes several dozens of conformance test failures with SIMD32 fragment
shaders enabled, including:

dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.dynamic_sample_number.*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-10 11:01:52 -08:00
Francisco Jerez
0703eab012 intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT message payload.
The problem occured when the return payload of a SIMD8 SEND
instruction was re-used as source payload of an EOT SEND message.  In
such cases the interference edge added by that workaround between the
payload and grf127_send_hack_node would have no effect, because the
payload would be allocated to a fixed range of registers containing
r127 by the special handling of EOT message payloads in the same
function.  This would cause things to blow up if the source payload of
the first SIMD8 message ended up being allocated to a range which
happened to overlap the destination.

Fix it by avoiding r127 altogether in the allocation of EOT message
payloads.

The problem can be reproduced on ICL with the fp-indirections2 Piglit
test-case in combination with the other optimizer changes of this
series.

Fixes: 232ed89802 "i965/fs: Register allocator shoudn't use grf127 for sends dest"
Cc: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-10 11:00:42 -08:00
Francisco Jerez
0a6e46d44d intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
Prevents invalid code from being emitted for ROR/ROL instructions in
SIMD32 shaders.

The problem can be reproduced with the following tests while forcing
SIMD32 to be used for fragment shaders:

 piglit.shaders.glsl-rotate-left
 piglit.shaders.glsl-rotate-right

However the issue could occur in production already with compute
shaders and a workgroup size large enough to trigger SIMD32 dispatch.

Fixes: 83fdec0f0d "intel/compiler: Enable the emission of ROR/ROL instructions"
Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-10 11:00:24 -08:00
Francisco Jerez
a30bb25a7a glsl: Fix software 64-bit integer to 32-bit float conversions.
The current implementation was broken for any integers between 2^24
and 2^30 (it would return zero for me on ICL).  The reason is that for
such integers we wouldn't take the 'if (0 <= shiftCount)' early return
path, however 'shiftCount + 7' would be positive, leading to a
negative 'count' argument passed to __shift64RightJamming(), which
would give undefined results.

This reworks the affected conversion functions to use either
__shortShift64Left() or __shift64RightJamming() based on the sign of
the final shift count, which should avoid the problem.  In addition
this should qualify as a clean-up/optimization -- This implementation
of the conversion functions translates to 7 instructions less than the
original on Intel hardware.

This fixes the 'KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot'
conformance tests on soft fp64 hardware with large enough subgroup
size (>16).

Fixes: d5cf6e92b4 "glsl: Add built-in functions to do uint64_to_fp32(uint64_t)"
Fixes: c9d333a6b7 "glsl: Add built-in functions to do int64_to_fp32(int64_t)"
Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
2020-01-10 10:51:58 -08:00
Daniel Schürmann
8b7a42d6d0 aco: compact aco::span<T> to use uint16_t offset and size instead of pointer and size_t.
This reduces the size of the Instruction base class
from 40 bytes to 16 bytes. No pipelinedb changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>
2020-01-10 17:49:18 +00:00
Daniel Schürmann
ffb4790279 aco: compact various Instruction classes
No pipelinedb changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>
2020-01-10 17:49:18 +00:00
Andrii Simiklit
ebaab89761 mesa/st: fix a memory leak in get_version
This patch prevents memory leak in get_version function in st_manager.c
This issue was found by valgrind:
16 bytes in 1 blocks are definitely lost in loss record 6 of 1,418
   at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
   by 0x63D9476: st_init_extensions (st_extensions.c:1679)
   by 0x63B803B: get_version (st_manager.c:1271)
   by 0x63B8124: st_api_query_versions (st_manager.c:1289)
   by 0x63266EF: dri_init_screen_helper (dri_screen.c:583)
   by 0x6321B12: dri2_init_screen (dri2.c:2110)
   by 0x631AACC: driCreateNewScreen2 (dri_util.c:155)
   by 0x5D58192: dri3_create_screen (dri3_glx.c:897)
   by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815)
   by 0x5D39C57: __glXInitialize (glxext.c:941)
   by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174)
   by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307)

Fixes: eca8032f20 ("gallium: Add ARB_gl_spirv support")
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345>
2020-01-10 17:27:39 +00:00
Lasse Lopperi
3de2774dcb freedreno/drm: Fix memory leak in softpin implementation
Free the memory allocated for cmds/reloc_bos array when destoying the
associated ringbuffer.

For similar fix for the non-softpin implementation see:
d014af98b7

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2324

Fixes: f3cc0d2 ("freedreno: import libdrm_freedreno + redesign submit")

Signed-off-by: Lasse Lopperi <lasse.lopperi@ge.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342>
2020-01-10 16:21:35 +00:00
Rhys Perry
b5c9688516 aco: limit register usage for large work groups
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2020-01-10 12:10:37 +00:00
Timur Kristóf
eccac46cdc ac/llvm: Fix ac_build_reduce in wave32 mode.
Previously, when cluster_size was set to 0, it always worked as if
the cluster size was 64. This commit fixes it in wave32 mode by
changing to work as if the cluster size was set to 32.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-01-10 12:30:44 +01:00
Pierre-Eric Pelloux-Prayer
a5fe84aefb radeonsi: release saved resources in si_compute_do_clear_or_copy
Fixes: 9b331e462e ("radeonsi: use compute shaders for clear_buffer & copy_buffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:40 +01:00
Pierre-Eric Pelloux-Prayer
6912149ee5 radeonsi: release saved resources in si_compute_clear_12bytes_buffer
Fixes: 6c901f0675 ("radeonsi: use compute shader for clear 12-byte buffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:38 +01:00
Pierre-Eric Pelloux-Prayer
1acf714d57 radeonsi: release saved resources in si_compute_copy_image
Fixes: 1b25d340b7 ("radeonsi: use compute for resource_copy_region when possible")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:35 +01:00
Pierre-Eric Pelloux-Prayer
e1e87466ae radeonsi: release saved resources in si_compute_clear_render_target
Fixes: 984fd73515 ("radeonsi: use compute for clear_render_target when possible")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:33 +01:00
Pierre-Eric Pelloux-Prayer
6c019e28ca radeonsi: release saved resources in si_compute_expand_fmask
Fixes: 095a58204d ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:31 +01:00
Pierre-Eric Pelloux-Prayer
9211cbe07a radeonsi: release saved resources in si_retile_dcc
Fixes: 1f21396431 ("radeonsi: add support for displayable DCC for multi-RB chips")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2330
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-10 08:41:19 +01:00
Samuel Iglesias Gonsálvez
39c1892dd8 main: fix coverity error in _mesa_program_resource_find_name()
We did not take into account if name is NULL, so we could dereference
a NULL pointer in strncmp() call.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 08:40:00 +01:00
Icecream95
f2f1277624 panfrost: Add negative lod bias support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-10 06:51:42 +00:00
Gurchetan Singh
daf1d5ad4c virgl/drm: update UAPI
This seems to compile. Header copied over from drm-misc-next
7da5492739db.

Acked-by: Eric Engestrom <eric@engestrom.ch>
2020-01-10 04:12:40 +00:00
Vasily Khoruzhick
438c677859 lima: drop support for R8G8B8 format
We can only sample from 24-bit packed format and can't render into it and
it causes chromium-based browsers to fail when they create FBO with GL_RGB
format. Drop R8G8B8 alltogether so mesa can promote it to RGBX format.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-09 18:46:08 -08:00
Jason Ekstrand
9b71171442 anv: Re-use flush_descriptor_sets in flush_compute_state
There's no reason to hand-roll all of the memory re-allocation fall-back
code for compute shaders.  It's  just duplicated complexity.  This also
makes it more clear in flush_compute_state where the
MEDIA_INTERFACE_DESCRIPTOR_LOAD command gets emitted relative to other
packets in the command stream.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-09 19:45:00 -06:00
Jason Ekstrand
ae72d1238c anv: Flag descriptors dirty when gl_NumWorkgroups is used
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-09 19:45:00 -06:00
Jason Ekstrand
ca6b3b11af anv: Don't add dynamic state base address to push constants on Gen7
Because Gen7 push constants are already relative to dynamic state base
address, they aren't really an address.  It's deceptive to return an
address from the helper function.  Instead, let's leave it as a
special-case in the gen7-11 helper; we don't need the helper for code
de-duplication for Gen7 anyway.

Fixes: 67d2cb3e93 "anv: Add get_push_range_address() helper"
Closes: #2323
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-09 19:44:06 -06:00
Vasily Khoruzhick
044da65f52 lima: add debug flag to disable tiling
Add debug flag to disable tiling. Note that it prevents lima from creating
tiled buffers, but it's still able to import them if modifier is specified

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-10 01:13:47 +00:00
Vasily Khoruzhick
a533d1d4c6 lima: use linear layout for shared buffers if modifier is not specified
Use linear layout for shared buffers if modifier is not specified
and use linear layout when importing buffers with invalid modifier.

Fixes: 01a451b04d ("lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-10 01:13:47 +00:00
Timothy Arceri
87e0dd68f5 glsl: call calculate_subroutine_compat() from the nir linker
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Timothy Arceri
726e8f24c6 glsl: move calculate_subroutine_compat() to shared linker code
We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Timothy Arceri
c60d0bd92f glsl: call uniform resource checks from the nir linker
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Timothy Arceri
05c1f7a154 glsl: move uniform resource checks into the common linker code
We will call this from the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Timothy Arceri
b85985dd51 glsl: call check_subroutine_resources() from the nir linker
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Timothy Arceri
a6fd1c7752 glsl: move check_subroutine_resources() into the shared util code
We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-10 00:41:20 +00:00
Jason Ekstrand
3dec68e682 genxml: Remove a non-existant HW bit 2020-01-09 18:40:20 -06:00
Kristian H. Kristensen
f9d35ea55b ir3: Set up full/half register conflicts correctly
Setting up transitive conflicts between a full register and its two
half registers (eg r0.x and hr0.x and hr0.y) will make the half
registers conflict.  They don't actually conflict and this prevents us
from using both at the same time.

Add and use a new ra helper that sets up transitive conflicts between
a register and its subregisters, except it carefully avoids the
subregister conflict.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2020-01-09 16:03:25 -08:00
Dave Airlie
85eed5def3 llvmpipe: add ARB_derivative_control support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2020-01-10 08:43:40 +10:00
Marek Olšák
269953e779 radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9
Fixes: 69ea473 "amd/addrlib: update to the latest version"
Closes: #2325

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-09 16:28:28 -05:00
Lionel Landwerlin
60e0db3bfb anv: fix intel perf queries availability writes
The availability is not written at the location changed in
ee6fbb95a74d...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ee6fbb95a7 ("anv: Properly handle host query reset of performance queries")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-09 20:42:36 +02:00
Dylan Baker
da2fe9c15e docs: Add release notes for 19.3.2, update calendar and home page 2020-01-09 10:33:49 -08:00
Dylan Baker
2d46a7f26d docs: add SHA256 sums for 19.3.2 2020-01-09 10:32:18 -08:00
Dylan Baker
d4f237dcce docs: Add release notes for 19.3.2 2020-01-09 10:32:14 -08:00
Satyajit Sahu
4e3a09db25 radeon/vcn: Handle crop parameters for encoder
Set proper cropping parameter if frame cropping is enabled

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Boyuan Zhang boyuan.zhang@amd.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
2020-01-09 15:43:18 +00:00
Daniel Schürmann
cd31da4587 nir: fix printing of var_decl with more than 4 components.
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: a8ec4082a4 ('nir+vtn: vec8+vec16 support')
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
2020-01-09 10:31:26 +01:00
Samuel Pitoiset
e298e78a01 radv: advertise VK_AMD_shader_image_load_store_lod
This extension allows to use LOD with image read/write operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-09 07:58:34 +01:00
Samuel Pitoiset
4d49a7ac73 aco: handle nir_intrinsic_image_deref_{load,store} with lod
Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-09 07:58:33 +01:00
Samuel Pitoiset
e77ff89914 amd/llvm: handle nir_intrinsic_image_deref_{load,store} with lod
Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-09 07:58:33 +01:00
Samuel Pitoiset
1b808d208f spirv,nir: add new lod parameter to image_{load,store} intrinsics
SPV_AMD_shader_image_load_store_lod allows to use a lod parameter
with OpImageRead, OpImageWrite and OpImageSparseRead.

According to the specification, this parameter should be a 32-bit
integer. It is initialized to 0 when no lod parameter is found
during SPIR-V->NIR translation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-09 07:58:33 +01:00
Samuel Pitoiset
37bfd854c7 spirv: add SpvCapabilityImageReadWriteLodAMD
New SPIR-V capability for SPV_AMD_shader_image_load_store_lod.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-09 07:58:33 +01:00
Tapani Pälli
1e29ff7b3d mesa: create program resource hash in a single place
This is a cleanup but also a fix for commit dd09f1d806. In case of
i965 we did not actually create hash for cached shader programs.

Fixes: dd09f1d806 "mesa/st/i965: add a ProgramResourceHash for quicker resource lookup"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-09 07:28:13 +02:00
Dave Airlie
ee9879335e llvmpipe: add support for ARB_indirect_parameters.
This just adds support for getting the draw count from the
indirect buffer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
2020-01-09 10:35:44 +10:00
Dave Airlie
315fa2e5c9 llvmpipe: enable driver side multi draw indirect
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
2020-01-09 10:35:40 +10:00
Dave Airlie
d10a3d528f gallium/util: add multi_draw_indirect to util_draw_indirect.
ARB_indirect_parameters needs drivers to deal with mutli_draw_indirect
themselves.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
2020-01-09 10:35:36 +10:00
Thong Thai
3a4f8c8158 mesa: Prevent _MaxLevel from being less than zero
When decoding using VDPAU, the _MaxLevel value becomes -1 due to
NumLevels being equal to 0 at a certain point, and decoding fails
due to an assertion later on.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
2020-01-08 16:44:20 -05:00
Marek Olšák
9b71041627 ac: add ac_build_s_endpgm
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 16:03:48 -05:00
Marek Olšák
1c44480538 ac: add 128-bit bitcount
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 16:00:41 -05:00
Marek Olšák
d7b565365e ac/gpu_info: add pc_lines and use it in radeonsi
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 16:00:40 -05:00
Marek Olšák
d1c8aeb24f ac: unify primitive export code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 16:00:38 -05:00
Marek Olšák
1c77a18cc2 ac: unify build_sendmsg_gs_alloc_req
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 16:00:36 -05:00
Marek Olšák
fd84e422b6 radeonsi: clean up messy si_emit_rasterizer_prim_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:49 -05:00
Marek Olšák
b64a3240c2 radeonsi: determine accurately if line stippling is enabled for performance
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:47 -05:00
Marek Olšák
79cc7e6ff0 radeonsi: test polygon mode enablement accurately
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:43 -05:00
Marek Olšák
898c9cb797 radeonsi: fix context roll tracking in si_emit_shader_vs
probably harmless, because we don't need to track context rolls on gfx10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:39 -05:00
Marek Olšák
4249a90f5d radeonsi: fix monolithic pixel shaders with two-sided colors and SampleMaskIn
They are never used except for testing AMD_DEBUG=mono.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:35 -05:00
Marek Olšák
186335d17d ac/gpu_info: always use distributed tessellation on gfx10
This might fix a hang on Navi14.

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:32 -05:00
Marek Olšák
eb1e10d0be gallium: bypass u_vbuf if it's not needed (no fallbacks and no user VBOs)
This decreases CPU overhead, because u_vbuf is completely bypassed
in those cases.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-08 13:40:59 -05:00
Marek Olšák
9f6020abc6 gallium/cso_context: move non-vbuf vertex buffer and element code into helpers
These will be reused.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-08 13:40:59 -05:00
Marek Olšák
ce648b913f gallium: put u_vbuf_get_caps return values into u_vbuf_caps
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-08 13:40:59 -05:00
Jonathan Marek
472593e9cf etnaviv: remove unnecessary vertex_elements_state_create error checking
PIPE_CAP_MAX_VERTEX_BUFFERS already sets the maximum vertex_buffer_index.

There's no need to error on num_elements == 0 (if that can even happen).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-08 12:27:35 -05:00
Jonathan Marek
76d93b437b etnaviv: implement gl_VertexID/gl_InstanceID
Fixes:
dEQP-GLES3.functional.instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-08 12:27:35 -05:00
Jonathan Marek
93ff6f5919 etnaviv: HALTI2+ instanced draw
Fixes:
dEQP-GLES3.functional.draw.draw_arrays_instanced.*
dEQP-GLES3.functional.draw.draw_elements_instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-08 12:27:34 -05:00
Jonathan Marek
ea608ae23b etnaviv: update headers from rnndb
Update to etna_viv commit 46af5f1d.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-08 12:27:34 -05:00
Lionel Landwerlin
4578d4ae52 anv: don't close invalid syncfd semaphore
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-08 18:20:50 +02:00
Krzysztof Raszkowski
7d33203b44 gallium/swr: Fix glVertexPointer race condition.
Sometimes using user buffer (not VBO) e.g. glVertexPointer
one thread could free memory before other thread used it.
Instead of copying this memory to driver simplier thing is
to block until draw finish.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2020-01-08 15:42:03 +00:00
Jason Ekstrand
b788cccfe2 intel/disasm: Fix decoding of src0 of SENDS
There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
2020-01-08 14:14:16 +00:00
Yevhenii Kolesnikov
8dcff01c8b meta: Add cleanup function for Bitmap
Buffer object and temporary texture were never freed, causing memory leaks.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-08 15:34:03 +02:00
Juan A. Suarez Romero
ad4fb7ea04 nir/spirv: skip unreachable blocks in Phi second pass
Only the blocks that are reachable are inserted with an end_nop
instruction at the end.

When handling the Phi second pass, if the Phi has a parent block that
does not have an end_nop then it means this block is unreachable, and
thus we can ignore it, as the Phi will never come through it.

Fixes dEQP-VK.graphicsfuzz.uninit-element-cast-in-loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-08 11:32:24 +01:00
Pierre-Eric Pelloux-Prayer
5f8daae4d8 radeonsi: check ctx->sdma_cs before using it
e5167a9276 disabled SDMA for gfx8.
This caused 3 piglit arb_sparse_buffer tests (basic, buffer-data
and commit) to crash on GFX8.

Reported-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5167a9276 ("radeonsi: disable SDMA on gfx8 to fix corruption on RX 580")
2020-01-08 09:31:35 +01:00
Samuel Pitoiset
e565fd4255 radv: do not fill keys from fragment shader twice
radv_fill_shader_info() already does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2020-01-08 08:59:04 +01:00
Yevhenii Kolesnikov
ed43dd62ac main: allow external textures for BindImageTexture
From issue 10 of the OES_EGL_image_external_essl3:

  A limited set of use-cases is enabled by making glBindImageTexture
  accept external textures. Shaders can access such external textures
  using the existing <image2D> sampler type.

Fixes: 02a6d901ee ("mesa: add OES_EGL_image_external_essl3 support")

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-08 09:21:39 +02:00
Jason Ekstrand
803fad43c3 intel/nir: Add a memory barrier before barrier()
Our barrier instruction does not implicitly do a memory fence but the
GLSL barrier() intrinsic is supposed to.  The easiest back-portable
solution is to just add the NIR barriers.  We'll sort this out more
properly in later commits.

Cc: mesa-stable@lists.freedesktop.org
Closes: #2138
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-07 21:52:19 -06:00
Bas Nieuwenhuizen
7cc0702bbb radv: Emit a BATCH_BREAK when changing pixel shaders or CB_TARGET_MASK.
Fixes a hang on Raven with Resident Evil 2.

I did not find anything more restricted to fix it:

- Setting persistent_states_per_bin to 1 fixes it too,
  but likely does an internal break on any descriptor set changes
  too.
- Only breaking the batch when cb_target_mask changes does not fix
  it (and looking at AMDVLK comments, I suspect the code in radeonsi
  should really be doing a FLUSH_DFSM).
- Always doing a FLUSH_DFSM on shader switch helps, but that is more
  often than this and I don't think we should be doing that when DFSM
  is disabled.
- Also emitting the existing break on framebuffer change when DFSM is
  disabled does not fix the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2315
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2020-01-07 22:44:31 +01:00
Tapani Pälli
dd09f1d806 mesa/st/i965: add a ProgramResourceHash for quicker resource lookup
Many resource APIs require searching by name, add a hash table to make
this faster. Currently we traverse the whole resource list for name
based queries, this change makes all these cases use the hash.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2203
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3254>
2020-01-07 10:48:41 +00:00
Michel Dänzer
5f0ff004ca gitlab-ci: Test against LLVM / clang 9 on x86
They're not available for Debian buster yet, so we have to use upstream
snapshot packages again.

In contrast to earlier, we now store the LLVM APT repository key in Git
instead of re-downloading it every time.
2020-01-07 11:00:16 +01:00
Alyssa Rosenzweig
4cd3dc94ad panfrost: Don't double-flip Z/W for 2D arrays
We need to mindful that we don't clobber the shadow comparator.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texture.sampler2darrayshadow_*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-07 08:54:52 +01:00
Alyssa Rosenzweig
bc4c853b49 pan/midgard: Account for z/w flip in texelFetch
Required for proper txf of 2D arrays.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*2darray*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-07 08:54:47 +01:00
Alyssa Rosenzweig
4152d45d38 panfrost: Adjust for mismatch between hardware/Gallium in arrays/cube
The hardware separates face selection and array indexing, it looks like,
whereas Gallium smushes them together with some modulus fun. Let's fix
it so mipmapped 2D arrays work without regressing cubemaps.

Fixes dEQP-GLES3.functional.texture.filtering.2d_array.* among others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-07 08:54:40 +01:00
Alyssa Rosenzweig
0b714f3fa3 panfrost: Respect constant buffer_offset
Fixes dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.* among
others

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-07 08:54:23 +01:00
Timothy Arceri
3bd4bcd418 glsl: use nir version of check_image_resources() for nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 09:53:51 +11:00
Timothy Arceri
feffd1fa65 glsl: add check_image_resources() for the nir linker
This is adapted from the GLSL IR code but doesn't need to
iterate over the IR. I believe this also fixes a potential bug in
the GLSL IR code which potentially counts the same output twice.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 09:53:51 +11:00
Timothy Arceri
a853de0c95 glsl: use nir linker to link atomics
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 09:50:57 +11:00
Timothy Arceri
8f2cab7767 mesa: add new UseNIRGLSLLinker constant
This will be used to disable some GLSL IR passes in following
patches.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 08:39:47 +11:00
Timothy Arceri
4caf3fc8df glsl: reorder link_and_validate_uniforms() calls
This is required for the following commit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 08:39:34 +11:00
Timothy Arceri
ed325ac4dd glsl: add new gl_nir_link_glsl() helper
This will allow us to do some linking in NIR that was previously
done by the GLSL IR linker. To start with this just has calls for
linking atomics.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 08:39:16 +11:00
Timothy Arceri
0e60ea1d67 glsl: add gl_nir_link_check_atomic_counter_resources()
This is pretty much a copy of link_check_atomic_counter_resources()
updated to work with the NIR linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 08:38:52 +11:00
Timothy Arceri
432ed13dec glsl: rename gl_nir_link() to gl_nir_link_spirv()
A NIR based glsl linking function will be too different to the
spirv version to bother attempting any sharing. So lets change
the name to be explicit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2020-01-07 08:38:41 +11:00
Kristian H. Kristensen
6c1c13e90e st/mesa: Lower vars to ssa and constant prop before gl_nir_lower_buffers
The gl_nir_lower_buffers pass relies on recognizing the same literal
constants as the GLSL compiler so that constant buffer array indices
are constant in nir as well.  Without this, get_block_array_index()
would see

  vec1 32 ssa_723 = deref_var &const_temp@1 (function_temp int)
  vec1 32 ssa_724 = load_const (0x00000001 /* 0.000000 */)
  ...
  vec1 32 ssa_5 = deref_var &const_temp@1 (function_temp int)
  vec1 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */
  vec1 32 ssa_7 = deref_var &blockB (ssbo BlockB[1])
  vec1 32 ssa_8 = deref_array &(*ssa_7)[ssa_6] (ssbo BlockB) /* &blockB[ssa_6] */

instead of a literal 1, and ultimately generate the block name
BlockB[0].  That used to work, since we before the previous commits
we'd compact the block binding points and names. Thus, there would
always be a BlockB[0].

Now, if an entry in a block array isn't used, we don't generate that
block name, which means that if entry 0 isn't used BlockB[0] isn't
present and then get_block_array_index() fails to find the block.

In most cases we would have dealt with this in the call to
st_nir_opts() in st_nir_link_shaders(), but in the num_shaders == 1
case (for example, compute) we would call gl_nir_lower_buffers()
before we lowered GLSL constants.  Move that corner case up next to
where we call st_nir_link_shaders() so we call st_nir_opts() at the
same point in the flow for all shaders.

Fixes: dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.18

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-06 13:01:19 -08:00
Andrii Simiklit
be6d51e1e3 glsl/nir: do not change an element index to have correct block name
When SSBO array is used with packed layout, both IR tree
and as a result, NIR tree will be incorrect.
In fact, the SSBO dereference indices won't
match the array size in some cases like the following:

"layout(packed, binding=1) buffer SSBO { vec4 a; } ssbo[3];
 out vec4 color;
 void main() {
   color = ssbo[2].a;
 }"

After linking the IR and then NIR will have an SSBO array
definition with size 1 but dereference still will have index 2
and linked_shader->Program->sh.ShaderStorageBlocks
will contain just SSBO with name "SSBO[2]"

So this line should be removed at least as a workaround for now
to avoid error like:
Failed to find the block by name "SSBO[0]"

Fixes: 810dde2a "glsl/nir: Add a pass to lower UBO and SSBO access"
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2020-01-06 13:01:19 -08:00
Andrii Simiklit
4beb0a2308 glsl: fix a binding points assignment for ssbo/ubo arrays
This is needed to be in agreement with spec requirements:
https://github.com/KhronosGroup/OpenGL-API/issues/46

Piers Daniell:
   "We discussed this in the OpenGL/ES working group meeting
    and agreed that eliminating unused elements from the interface
    block array is not desirable. There is no statement in the spec
    that this takes place and it would be highly implementation
    dependent if it happens. If the application has an "interface"
    in the shader they need to match up with the API it would be
    quite confusing to have the binding point get compacted.
    So the answer is no, the binding points aren't affected by
    unused elements in the interface block array."

v2: - 'original_dim_size' field moved above to keep
      the struct packed better on 64-bit
    - added a comment for 'total_num_array_elements' field
    - fixed a binding point calculations for SSBOs array of arrays
          ( Ian Romanick <ian.d.romanick@intel.com> )
    - fixed binding point calculations for non-packed SSBOs
v3:
    - rename 'total_num_array_elements' to 'aoa_size'
          ( Jason Ekstrand <jason@jlekstrand.net> )
    - rename 'boffset' to 'binding_stride'
          ( Alejandro Piñeiro <apinheiro@igalia.com> )

Fixes: 8cf1333b "glsl: link uniform block arrays of arrays"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532
Reported-By: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Fritz Koenig <frkoenig@google.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2020-01-06 13:01:19 -08:00
Andrii Simiklit
a3c9a2881e glsl: fix an incorrect max_array_access after optimization of ssbo/ubo
This is needed to fix these tests:
piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_frag
piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_comp

Fixes: 8cf1333b "glsl: link uniform block arrays of arrays"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532
Reported-By: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Fritz Koenig <frkoenig@google.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2020-01-06 13:01:19 -08:00
Marek Olšák
420fe1e7f9 radeonsi: remove TGSI
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-06 15:57:20 -05:00
Marek Olšák
e5167a9276 radeonsi: disable SDMA on gfx8 to fix corruption on RX 580
Closes: #1399
Closes: #1889

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:36 -05:00
Marek Olšák
991328498b radeonsi: move SI and CIK+ SDMA code into 1 common function for cleanups
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:35 -05:00
Marek Olšák
3c265c2586 radeonsi: rename dma_cs -> sdma_cs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:33 -05:00
Marek Olšák
cd6a4f7631 radeonsi: add AMD_DEBUG=nodmacopyimage for debugging
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:32 -05:00
Marek Olšák
0c9e7a67f9 radeonsi: add AMD_DEBUG=nodmaclear for debugging
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:30 -05:00
Marek Olšák
4110e6e564 radeonsi: remove broken and unused SI SDMA image copy code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:28 -05:00
Marek Olšák
503bd821fa radeonsi: rename SDMA debug flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:11 -05:00
Tomeu Vizoso
d62dd8b0cb gitlab-ci: Switch LAVA jobs to use shared dEQP runner
Take one step towards sharing code between the LAVA and non-LAVA jobs,
with the goals of reducing maintenance burden and use of computational
resources.

The env var DEQP_NO_SAVE_RESULTS allows us to skip the procesing of the
XML result files, which can take a long time and is not useful in the
LAVA case as we are not uploading artifacts anywhere at the moment.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2020-01-06 14:27:36 +01:00
Tomeu Vizoso
f5c2807ff2 gitlab-ci: Update kernel for LAVA to 5.5-rc1 plus fixes
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2020-01-06 14:27:21 +01:00
Alyssa Rosenzweig
b3ff83c107 panfrost: Handle PIPE_FORMAT_R10G10B10A2_USCALED
Same format code as UINT... might be different in how it's fed into a
shader but we'll deal with that when we get there.

Fixes dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.usigned_int2_10_10_10.components4_vec2_quads1

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:50:00 -05:00
Alyssa Rosenzweig
5c71547c68 panfrost: Report MSAA 4x supported for dEQP
Fixes dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64

We'll have to actually implement multisampling next, but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:58 -05:00
Alyssa Rosenzweig
32851ff715 panfrost: Cleanup tiling selection logic
Make it a lot more obvious what we're doing and fix more than a few
corner cases in the process.

Fixes
dEQP-GLES3.functional.buffer.map.write.render_as_index_array.pixel*, and
likely others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:53 -05:00
Alyssa Rosenzweig
dadfca3775 panfrost: Implement sRGB blend shaders
We use the lowering in nir_format_convert. There are native ops for this
so this is far from optimal and not remotely efficient but as with most
blend shader things right now, it's hard enough to get it working, so
let's focus on that for now. We'll make it fast later (once we have
GLES3 stable, we can start optimizing these things).

Fixes dEQP-GLES3.functional.fragment_ops.blend.fbo_srgb.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:48 -05:00
Alyssa Rosenzweig
ef00849877 panfrost: Support rendering to non-zero Z/S layers
Fixes abort in STK's shadow implementation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:42 -05:00
Alyssa Rosenzweig
ef8c2ebee1 panfrost: Texture from Z32F_S8 as R32F
Z32F_S8 becomes Z32F in texturing, which in turn just becomes R32F.

Fixes dEQP-GLES3.functional.texture.format.sized.*.depth32f_stencil8*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:33 -05:00
Danylo Piliaiev
f3ca47d9f3 iris/query: Implement PIPE_QUERY_GPU_FINISHED
Implementation is similar to radeonsi in 5f1cef76

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-06 12:43:14 +02:00
Erik Faye-Lund
642125edd9 st/mesa: use uint-samplers for sampling stencil buffers
Otherwise, we end up mismatching the sampler types when rendering.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-06 09:23:43 +01:00
Samuel Pitoiset
09ea2de2b8 ac/surface: use uint16_t for mipmap level pitches
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-06 07:59:50 +01:00
Jonathan Marek
680d806950 etnaviv: fix incorrectly failing vertex size assert
Changes the assert to match the comment above.

This assert was failing in some cases while running darkplaces.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-05 17:04:39 +00:00
Vasily Khoruzhick
c5ae64ebc7 lima: fix PP stream terminator size
PP stream terminator size seems to be 4 words, it worked with full PP
stream because we align stream beginning to 32 bytes and BO is
initialized with zeroes. But with partial PP stream it sometimes break
if for new PP stream we reuse BO that has non-zero value at this place.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:39 -08:00
Vasily Khoruzhick
4f5bfe2a5e lima: don't reload and redraw tiles that were not updated
We don't need to reload and redraw some tiles if framebuffer was not
cleared and scissor test was enabled for some of draws. This simple
optimization fixes cursor lag in X11

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:36 -08:00
Vasily Khoruzhick
83abdf8e45 lima: postpone PP stream generation
This commit postpones PP stream generation till job is submitted.
Doing that this late allows us to skip reloading and redrawing tiles
that were not updated.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:33 -08:00
Andreas Baierl
7ad1896ab8 lima/parser: Fix VS cmd stream parser
prefetch is int, not bool.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-05 03:08:01 +00:00
Andreas Baierl
af7dc4675d lima/parser: Fix rsw parser
Drop assert as it is not necessary and used wrong anyway.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-05 03:08:01 +00:00
Kenneth Graunke
defb3a9465 anv: Only enable EWA LOD algorithm when doing anisotropic filtering.
Updated documentation renames "Anisotropic Algorithm" to "LOD Algorithm"
and adds a note for Gen9+ saying "The EWA Algorithm should only be
enabled for Anisotropic Filtering modes." and indicating that the extra
accuracy shouldn't be necessary for other modes, and comes at a cost.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-04 14:27:22 -08:00
Kenneth Graunke
c0c899cf78 iris: Allow HiZ for copy_region sources
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-04 12:25:55 -08:00
Jason Ekstrand
7d75bf4f3f i965: Allow HiZ for glCopyImageSubData sources
v2 (Ken): Handle platforms without sampler support for HiZ

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v2 changes]
2020-01-04 12:25:55 -08:00
Jason Ekstrand
52ad1712ed anv: Allow HiZ in TRANSFER_SRC_OPTIMAL on Gen8-9
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand
b274469daa intel/blorp: Use the source format when using blorp_copy with HiZ
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand
ea7446ba82 i965/blorp: Don't resolve HiZ unless we're reinterpreting
This eliminates 50% of pixels (2M) rendered for a blit in GS:GO.  This
accounts for 3% of pixels rendered in the game.  Total GPU clocks for
the first 900 frames of CSGO improves by 1%.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand
95cc5438eb blorp: Allow reading with HiZ
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand
4a1093005c blorp: Stop whacking Z24 depth to BGRA8
The shader code required to do this is int(sat(x) * UINT24_MAX) which
isn't really worth all the effort to avoid.  Doing the format
conversion, on the other hand, prevents us from sampling with HiZ which
is something that we very much want on gen8-9 where we can.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Christian Gmeiner
a597a64ae2 etnaviv: move descriptor based texture structs
This moves the descriptor based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-04 20:44:36 +01:00
Christian Gmeiner
7c687d221d etnaviv: move state based texture structs
This moves the state based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-04 20:44:36 +01:00
Roman Stratiienko
ed0fa78b46 panfrost: Fix Android build
Include missing `encoder/pan_props.c` into the build.

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-04 16:54:38 +00:00
Gert Wollny
9162e2f03f mesa/st: glsl_to_nir: don't lower atomics to SSBOs if driver supports HW atomics
At least on r600 HW atomic operations are way less expensive than SSBO atomic
operations.

v2: use st->has_hw_atomics (Erik Anholt)

v3: remove second invocation of atomic to ssbo lowering (Erik Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
b119f8b4a0 r600: Delete vertex buffer only if there is actually a shader state
Fixes: gl-2.0-vertexattribpointer
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
32bb5f2941 r600: Make SID and unsigned value
The value is never negative, and makeing it unsigned fixes some
warnings

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
e8559ae448 r600: Fix maximum line width
There are only 13 bits available to store the line width, hence
it can't be larger than 8191

v2: Add Fixes tag

v3: - Unify value since for all r600 archs (Konstantin Kharlamov)
    - Correct the value the line width value is emitted as a 12.4
      fixed point value of 1/2 line width on r600-r700 and as
      8 * line width on Evergreen and newer.

Fixes: 06bfb2d28f
    r600: fork and import gallium/radeon

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
829107819d r600/sb: Correct SB disassambler for better debugging
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
bfbdaf9a46 r600: Make it possible to include r600_asm.h in a C++ file
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
23c5ba8baa r600: Add functions to dump the shader info
This will be helpful to compare TGSI and NIR code path,

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
570a6c6c79 gallium: tgsi_from_mesa - handle VARYING_SLOT_FACE
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
6c9495b392 nir: make nir_get_texture_size/lod available outside nir_lower_tex
This functions can be useful in other places.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny
f69bf7fe8c gallium/tgsi_from_mesa: Add 'extern "C"' to be able to include from C++
The r600/nir backend is in C++ and needs to include this file.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Bas Nieuwenhuizen
96c9483ccf spirv: Fix glsl type assert in spir2nir.
Fixes: 624789e370 "compiler/glsl: handle case where we have multiple users for types"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-04 15:53:24 +00:00
Christian Gmeiner
b178262cb9 etnaviv: use a better name for FE_VERTEX_STREAM_UNK14680
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-04 14:15:36 +01:00
Bas Nieuwenhuizen
17741a0a05 radv: Only use the gfx mipmap level offset/pitch for linear textures.
The tiled-case is non-sensical for non-base mips, but Vulkan requires
that this function handles it but at the same time does not require
returning anything useful. So we can basically return anything.

Correct tiled pitch and offset are still required for our own WSI and
in the future getting the layouts of images with DRM format modifiers.
Both don't have to deal with images with more than 1 level though.

Fixes: 824bd0830e "radv: return the correct pitch for linear mipmaps on GFX10"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-04 13:04:40 +01:00
Bas Nieuwenhuizen
f0ed67b770 Revert "amd/common: Always initialize gfx9 mipmap offset/pitch."
This reverts commit 973181c06c.

Requested by Marek.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-04 13:04:40 +01:00
Kenneth Graunke
645b195312 iris: Delete remnants of the unimplemented ASTC 5x5 workaround
I copy and pasted some of the boilerplate but never the implementation.
For now, ASTC 5x5 is disabled and faked via uncompressed RGBA; let's
delete these remnants until such a time when we implement it properly.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-03 18:06:38 -08:00
Kenneth Graunke
e858321f09 iris: Disable ASTC 5x5 support on Gen9 for now.
Intel Gen9 hardware has some nasty restrictions where ASTC 5x5 formats
and color compression can't both live in the sampler cache at the same
time.  To properly support it, we have to track which of those exist
in the cache and flush ASTC out or resolve away compression.

As far as I'm aware, very little uses ASTC 5x5 textures, so instead
of replicating all that for iris, we simply turn it off and rely on
the Gallium fallback mechanism to fake it via uncompressed RGBA.

This should avoid GPU hangs any time people use ASTC 5x5 with CCS.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-03 18:06:38 -08:00
Kenneth Graunke
8e6308363b st/mesa: Allow ASTC5x5 fallbacks separately from other ASTC LDR formats.
This patch allows us to fake ASTC 5x5 specifically, while leaving the
other ASTC LDR formats with native support.  I plan to use this in iris,
at least for the time being.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-03 18:06:35 -08:00
Erik Faye-Lund
56fc791b31 etnaviv: use nir_lower_clip_halfz instead of open-coding
We already have a helper for this, so let's use that instead of rolling
our own version.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Paul Cercueil <paul@crapouillou.net>
2020-01-03 22:48:19 +00:00
Erik Faye-Lund
d9ff5f0414 nir/zink: move clip_halfz-lowering to common code
Etnaviv also does the same thing, so let's try to avoid repetition here,
and use the same for it code as well.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Paul Cercueil <paul@crapouillou.net>
2020-01-03 22:48:19 +00:00
Erik Faye-Lund
5c2376af63 zink: remove unused code-path in lower_pos_write
This code is never reached, because we don't call nir_lower_io before
lowering this. So let's get rid of it.
2020-01-03 22:48:19 +00:00
Erik Faye-Lund
87b3d8dce5 zink: use nir_fmul_imm
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Paul Cercueil <paul@crapouillou.net>
2020-01-03 22:48:19 +00:00
Erik Faye-Lund
e51bf4914c zink: implement load_vertex_id
Not 100% sure if this matches the semantics, but it seems to pass the
tests, so it seems like an improvement.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-03 22:20:12 +00:00
Erik Faye-Lund
1b2731f268 zink: factor out builtin-var creation
This is useful so we can reuse it for the next patch

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-03 22:20:12 +00:00
Erik Faye-Lund
ce1ea6e9c2 zink: simplify front-face type
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-03 22:20:12 +00:00
Caio Marcelo de Oliveira Filho
75a19186b2 anv: Ignore some CreateInfo structs when rasterization is disabled
According to the description of VkGraphicsPipelineCreateInfo(),
pViewportState, pMultisampleState, pDepthStencilState and
pColorBlendState must be ignored when rasterization is not enabled.

This avoids potentially invalid pointers being dereferenced when
rasterization is disabled.  Tested with `demos_x64 VK_Parameter_Zoo`
from Renderdoc repository.

v2: Don't store the `raster_enabled` as part of anv_pipeline, just
    query it from the create info.  This avoids storing a state that's
    only used during pipeline creation. (Jason)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2258
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch> [v1]
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-03 13:57:31 -08:00
Caio Marcelo de Oliveira Filho
6755b6315b anv: Drop unused function parameter
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-03 13:29:49 -08:00
Marek Olšák
66483ee017 radeonsi: remove the "display_dcc_offset == 0" assertion
I think it's not needed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-03 15:07:19 -05:00
Marek Olšák
bfddfd12b6 radeonsi: ignore PIPE_BIND_SCANOUT for imported textures
It's obtained from the BO metadata.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-03 15:07:17 -05:00
Marek Olšák
ba10fb3f7f radeonsi: preserve the scanout flag for shared resources on gfx9 and gfx10
Closes: #2195
Closes: #2294

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-03 15:07:11 -05:00
Vasily Khoruzhick
1de06e540a lima: fix allocation of GP outputs storage for indexed draw
For indexed draw number of VS invocations is (ctx->max_index - ctx->min_index + 1),
so we have to use this number when calculating space for varyings, gl_Position and
gl_PointSize.

Fixes dEQP-GLES2.functional.buffer.write.use.index_array.array and
dEQP-GLES2.functional.buffer.write.use.index_array.element_array

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-03 18:57:36 +00:00
Jason Ekstrand
9bd8000c6c anv: Drop unneeded struct keywords
All VkFoo structs are typedef'd to not need the struct keyword.  Leaving
it in there is just extra characters and breaks Vulkan's aliasing when
stuff gets promoted to core versions.  It's better to just never use
struct for VkFoo.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2020-01-03 11:32:34 -06:00
Thong Thai
8dc7c467e6 r600: Remove HEVC related code since HEVC is not supported
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
2020-01-03 16:30:22 +00:00
Thong Thai
466001a226 radeon: Use P010 for decoding of 10-bit videos
Previously, P016 was used for the decoding of 10-bit HEVC/H.265 encoded
videos, which worked fine for mpv and ffmpeg. GStreamer specifically looks
for P010, so this patch sets the default buffer type to P010 for HEVC
decoding.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
2020-01-03 16:30:22 +00:00
Thong Thai
68881af435 st/va: Add support for P010, used for 10-bit videos
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
2020-01-03 16:30:22 +00:00
Thong Thai
f3569f215d gallium: Add PIPE_FORMAT_P010 support
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
2020-01-03 16:30:22 +00:00
Thong Thai
ee8344bdcf util/format: Add the P010 format used for 10-bit videos
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
2020-01-03 16:30:22 +00:00
Erik Faye-Lund
98885e9f61 zink: implement some more trivial opcodes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-03 17:16:18 +01:00
Erik Faye-Lund
8c18331afe zink: implement txf
texelFetch is a requirement for OpenGL 3.0, so this gets us a step
closer to GL 3.0 support.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-03 15:28:27 +01:00
Samuel Pitoiset
7b70502a5d radv: implement VK_AMD_mixed_attachment_samples
With VK_AMD_mixed_attachment_samples, the number of depth/stencil
samples isn't always equal to the number of color samples. Adjust
the number of Z samples when it's different but make sure to have
a consistent sample count if there are no depth/stencil attachments.

Also adjust the number of samples used for fragment shaders which is
the number of color samples if mixed attachment samples are used.

Only enabled on GFX8+ because it's untested on previous chips.

All dEQP-VK.pipeline.multisample.mixed_attachment_samples.* now pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3018>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3018>
2020-01-03 12:31:53 +00:00
Samuel Pitoiset
7bbf497b68 radv: record number of color/depth samples for each subpass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3018>
2020-01-03 12:31:53 +00:00
Christian Gmeiner
8d50ab5395 etnaviv: gc400 does not support any vertex sampler
On STM32MP1 fixes the dEQPs below and changes the dEQP run statistics to:

-  Passed:        16856/17346 (97.2%)
-  Failed:        236/17346 (1.4%)
-  Not supported: 199/17346 (1.1%)
+  Passed:        16780/17346 (96.7%)
+  Failed:        86/17346 (0.5%)
+  Not supported: 425/17346 (2.5%)
   Warnings:      55/17346 (0.3%)

dEQP-GLES2.functional.shaders.struct.uniform.sampler_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_in_function_arg_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_in_array_function_arg_vertex
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2d
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2dproj_vec3
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2dproj_vec4
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2dlod
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2dprojlod_vec3
dEQP-GLES2.functional.shaders.texture_functions.vertex.texture2dprojlod_vec4
dEQP-GLES2.functional.shaders.texture_functions.vertex.texturecube
dEQP-GLES2.functional.shaders.texture_functions.vertex.texturecubelod
dEQP-GLES2.functional.shaders.random.texture.vertex.0
dEQP-GLES2.functional.shaders.random.texture.vertex.1
dEQP-GLES2.functional.shaders.random.texture.vertex.2
dEQP-GLES2.functional.shaders.random.texture.vertex.3
dEQP-GLES2.functional.shaders.random.texture.vertex.4
dEQP-GLES2.functional.shaders.random.texture.vertex.5
dEQP-GLES2.functional.shaders.random.texture.vertex.6
dEQP-GLES2.functional.shaders.random.texture.vertex.7
dEQP-GLES2.functional.shaders.random.texture.vertex.8
dEQP-GLES2.functional.shaders.random.texture.vertex.9
dEQP-GLES2.functional.shaders.random.texture.vertex.10
dEQP-GLES2.functional.shaders.random.texture.vertex.11
dEQP-GLES2.functional.shaders.random.texture.vertex.12
dEQP-GLES2.functional.shaders.random.texture.vertex.13
dEQP-GLES2.functional.shaders.random.texture.vertex.14
dEQP-GLES2.functional.shaders.random.texture.vertex.16
dEQP-GLES2.functional.shaders.random.texture.vertex.17
dEQP-GLES2.functional.shaders.random.texture.vertex.18
dEQP-GLES2.functional.shaders.random.texture.vertex.19
dEQP-GLES2.functional.shaders.random.texture.vertex.20
dEQP-GLES2.functional.shaders.random.texture.vertex.22
dEQP-GLES2.functional.shaders.random.texture.vertex.23
dEQP-GLES2.functional.shaders.random.texture.vertex.24
dEQP-GLES2.functional.shaders.random.texture.vertex.26
dEQP-GLES2.functional.shaders.random.texture.vertex.28
dEQP-GLES2.functional.shaders.random.texture.vertex.29
dEQP-GLES2.functional.shaders.random.texture.vertex.31
dEQP-GLES2.functional.shaders.random.texture.vertex.34
dEQP-GLES2.functional.shaders.random.texture.vertex.37
dEQP-GLES2.functional.shaders.random.texture.vertex.38
dEQP-GLES2.functional.shaders.random.texture.vertex.39
dEQP-GLES2.functional.shaders.random.texture.vertex.40
dEQP-GLES2.functional.shaders.random.texture.vertex.42
dEQP-GLES2.functional.shaders.random.texture.vertex.43
dEQP-GLES2.functional.shaders.random.texture.vertex.44
dEQP-GLES2.functional.shaders.random.texture.vertex.45
dEQP-GLES2.functional.shaders.random.texture.vertex.48
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_nearest_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_nearest_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_mirror
dEQP-GLES2.functional.fbo.api.attach_names
dEQP-GLES2.functional.uniform_api.info_query.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.info_query.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.info_query.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.info_query.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.info_query.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.info_query.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.info_query.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.info_query.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.info_query.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.info_query.unused_uniforms.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.info_query.unused_uniforms.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.get_uniform.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.render.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.initial.render.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.initial.render.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.initial.render.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.initial.render.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.initial.render.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_array_first_elem_without_brackets.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_array_first_elem_without_brackets.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.get_uniform.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_array_first_elem_without_brackets.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_array_first_elem_without_brackets.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.get_uniform.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic.samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic.samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.basic_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.struct_in_array.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.struct_in_array.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_full.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_full.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_full.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_full.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_partial.basic_array.sampler2D_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_partial.basic_array.sampler2D_both
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_partial.array_in_struct.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.basic_array_assign_partial.array_in_struct.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.value.assigned.unused_uniforms.sampler2D_samplerCube_vertex
dEQP-GLES2.functional.uniform_api.value.assigned.unused_uniforms.sampler2D_samplerCube_both
dEQP-GLES2.functional.uniform_api.random.0
dEQP-GLES2.functional.uniform_api.random.3
dEQP-GLES2.functional.uniform_api.random.6
dEQP-GLES2.functional.uniform_api.random.11
dEQP-GLES2.functional.uniform_api.random.14
dEQP-GLES2.functional.uniform_api.random.21
dEQP-GLES2.functional.uniform_api.random.22
dEQP-GLES2.functional.uniform_api.random.24
dEQP-GLES2.functional.uniform_api.random.25
dEQP-GLES2.functional.uniform_api.random.29
dEQP-GLES2.functional.uniform_api.random.30
dEQP-GLES2.functional.uniform_api.random.32
dEQP-GLES2.functional.uniform_api.random.33
dEQP-GLES2.functional.uniform_api.random.37
dEQP-GLES2.functional.uniform_api.random.41
dEQP-GLES2.functional.uniform_api.random.49
dEQP-GLES2.functional.uniform_api.random.51
dEQP-GLES2.functional.uniform_api.random.55
dEQP-GLES2.functional.uniform_api.random.61
dEQP-GLES2.functional.uniform_api.random.69
dEQP-GLES2.functional.uniform_api.random.72
dEQP-GLES2.functional.uniform_api.random.78
dEQP-GLES2.functional.uniform_api.random.79
dEQP-GLES2.functional.uniform_api.random.82
dEQP-GLES2.functional.uniform_api.random.87
dEQP-GLES2.functional.uniform_api.random.88
dEQP-GLES2.functional.uniform_api.random.94
dEQP-GLES2.functional.uniform_api.random.95
dEQP-GLES2.functional.uniform_api.random.96

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-01-03 09:23:41 +01:00
Christian Gmeiner
46b8273eb1 etnaviv: check if MSAA is supported
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-03 08:31:02 +01:00
Iago Toral Quiroga
2271a187c2 u_vbuf: don't try to delete NULL driver CSO
Since 18a8c3f7f1 we don't create a driver CSO if there are any
incompatible elements, so only ask backends to delete it if it exists.

Fixes multiple CTS crashes in V3D.

Fixes: 18a8c3f7f1 ("u_vbuf: Only create driver CSO if no incompatible elements")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-03 07:58:35 +01:00
Kenneth Graunke
d0d28c783d iris: Set nir_shader_compiler_options::unify_interfaces.
This is technically enabling the option in the common intel backend
code, but only the st/nir linker uses the option, so it's iris-only.

Fixes Piglit's spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out

Closes: #2274
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3249>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3249>
2020-01-03 00:41:50 +00:00
Kenneth Graunke
19ed12afd1 st/nir: Optionally unify inputs_read/outputs_written when linking.
i965 and iris use inputs_read/outputs_written for a shader stage to
determine the layout of input and output storage.  Adjacent stages must
agree on the layout, so adjacent input/output bitfields must match.

This patch adds a new nir_shader_compiler_options::unify_interfaces
flag which asks the linker to unify the input/output interfaces between
adjacent stages.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3249>
2020-01-03 00:41:50 +00:00
Kenneth Graunke
7a9c0fc0d7 intel: Drop Gen11 WaBTPPrefetchDisable workaround
This isn't needed on production Icelake hardware.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3250>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3250>
2020-01-03 00:20:17 +00:00
Jordan Justen
ed17baab5f intel: Remove unused Tigerlake PCI ID
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2020-01-02 15:18:18 -08:00
Alyssa Rosenzweig
3759b84926 pan/midgard: Use upper ALU tags for MFBD writeout
It's not clear yet what the distinction is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 17:27:23 -05:00
Alyssa Rosenzweig
2d1e18ee83 pan/midgard: Identity ld_color_buffer as 32-bit
I'm not sure why I mistakenly identified it as an 8-bit op before.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
5063ab6a9c pan/midgard: Remove old comment
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
5bc62af2a0 pan/midgard: Generate MRT writeout loops
They need a very particular form; the naive way we did before is not
sufficient in practice, it doesn't look like. So let's follow the rough
structure of the blob's writeout since this is fixed code anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
db879b034a pan/midgard: Generalize IS_ALU and quadword_size
There are more ALU tags, let's do some cleanup while we're at it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
66f98ffab0 pan/midgard: Use better heuristic for shader termination
This still may not be perfect (in the sense that legal shaders might
still get cut off) but this fits how writeout is done with both Panfrost
and the blob, so it's good enough for what we need and allows MRT
shaders to be sanely disassembled.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
c298f25c4e pan/midgard: Fix memory corruption in constant combining
It's a long story... but we'd try to insert constants that weren't there
and end up clobbering fields in the bundle following the constant
array...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
d58600c0e0 panfrost: Pack MRT blend shaders into a single BO
Blend shader size and location in memory is considerably constrained,
probably to facilitate optimizations (my guess is that blend shaders are
run strictly out of i-cache). We need to pack the blend shaders for each
RT of a single framebuffer together. The easiest way to do this is at
draw time which is not terribly efficient but will hold us over for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Alyssa Rosenzweig
1b86e0927d panfrost: Handle RGB16F colour clear
We don't handle this format yet, but we will soon, and the abort in
pan_pack_color is possible even without exposing the format... Handling
this gracefully might not be required by the spec but let's not crash.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 15:20:55 -05:00
Tomeu Vizoso
829f338a59 panfrost: Store internal format
It's needed by u_transfer_helper to know when the depth+stencil buffer
has been split.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 12:41:17 -05:00
Tomeu Vizoso
14bc4c7cce panfrost: Map with size of first layer for 3D textures
As that's what Gallium expects in transfer.layer_stride.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 12:41:15 -05:00
Tomeu Vizoso
ed3eede296 panfrost: Dynamically allocate array of texture pointers
With 3D textures we can have lots of layers, so better allocate it
dynamically at runtime.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-02 12:41:02 -05:00
Bas Nieuwenhuizen
c1a1a86658 meson: Enable -Werror=int-conversion.
I think implicit conversions here are almost always wrong:

1) wrong argument position ptr vs. int
2) will often have issues with 32-bit platforms.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2570>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2570>
2020-01-02 11:47:02 +00:00
Bas Nieuwenhuizen
b72182fcfa turnip: Use VK_NULL_HANDLE instead of NULL.
Only occurrence of implicitly converting pointer->int.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2570>
2020-01-02 11:47:02 +00:00
Bas Nieuwenhuizen
973181c06c amd/common: Always initialize gfx9 mipmap offset/pitch.
The WSI expects pitch to be meaningful even for tiled
textures.

(It is used for the pitch in modesetting and X11)

Fixes: 824bd0830e "radv: return the correct pitch for linear mipmaps on GFX10"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3245>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3245>
2020-01-02 11:25:51 +00:00
Bas Nieuwenhuizen
59c4fb9d72 nir: print non-uniform tex fields.
To ease debugging in the future.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3246>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3246>
2020-01-02 11:42:33 +01:00
Bas Nieuwenhuizen
69bdc1c5fc nir: Add clone/hash/serialize support for non-uniform tex instructions.
These were missed when the fields got added. Added it everywhere where
texture_index got used and it made sense.

Found this in "The Surge 2", where the inliner does not copy the fields,
resulting in corruption and hangs.

Fixes: 3bd5457641 "nir: Add a lowering pass for non-uniform resource access"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1203
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3246>
2020-01-02 11:41:33 +01:00
Afonso Bordado
525cbe85ef pan/midgard: Optimize branches with inverted arguments
Remove the invert on arguments to branches, and invert the branch
condition instead. This saves one instruction per inverted argument.

Closes #2088

Signed-off-by: Afonso Bordado <afonsobordado@az8.co>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-31 20:01:16 +00:00
Afonso Bordado
0e83688f47 pan/midgard: Move midgard_is_branch_unit to helpers
Signed-off-by: Afonso Bordado <afonsobordado@az8.co>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-31 20:01:12 +00:00
Marek Vasut
5e9106f7af etnaviv: Do not filter out PIPE_FORMAT_S8_UINT_Z24_UNORM on pre-HALTI2
The format PIPE_FORMAT_S8_UINT_Z24_UNORM is supported even on pre-HALTI
hardware like GCnano. Do not report it as unsupported format.

This fixes the following dEQP on GCnano:
dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.depth_stencil_unsigned_int_24_8

Fixes: 64c7cdcae5 ("etnaviv: add missing formats")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3200>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3200>
2019-12-31 15:12:49 +00:00
Marek Vasut
a812cb57e5 etnaviv: Report correct number of vertex buffers
The GCnano has only 4 vertex buffers instead of 16. This information
can be extracted from the GPU status registers and is already stored
in screen->specs.stream_count. Use PIPE_CAP_MAX_VERTEX_BUFFERS to
report this information and permit u_vbuf to reorganize the shaders
to fit.

This fixes the following dEQP on GCnano:
dEQP-GLES2.functional.shaders.conversions.vector_combine.float_float_float_float_to_vec4_vertex

This fixes all the other dEQP-GLES2.functional.shaders.conversions.*
which used to fail on GCnano.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3241>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3241>
2019-12-31 14:55:04 +00:00
Timur Kristóf
11e62a9734 aco: Fix uniform i2i64.
Fixes 240 failing test cases in dEQP-VK.spirv_assembly which
were failing due to a bad s_ashr_i32 instruction. This commit
fixes the instruction format along with the definitions of the
instruction.

Fixes: 11f43caaec
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-31 14:22:31 +01:00
Robert Foss
182679e7c5 android: Fix u_format_table.c being generated twice
Two competing rules for defining u_format_table.c exists,
which is an error.

Additionally the more general rule lacks the inclusion of
format/u_format.csv.

Fixes: 882ca6dfb0 ("util: Move gallium's PIPE_FORMAT utils to /util/format/")

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-12-31 14:06:02 +01:00
Alyssa Rosenzweig
a0d65d860d pan/midgard: Remove prepacked_branch
It's an ugly hack that's no longer used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-31 03:26:24 +00:00
Alyssa Rosenzweig
02f503ef00 pan/midgard: Convert fragment writeout to proper branches
This eliminates the only use of prepacked_branch, which is a such a
hack anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-31 03:26:24 +00:00
Marek Olšák
84b82f8cd1 winsys/radeon: initialize pte_fragment_size
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>

Closes: #2179

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-30 20:20:59 -05:00
Marek Olšák
5c9dcbea77 Revert "u_vbuf: Regard non-constant vbufs with non-instance elements as free"
This reverts commit c6ef79c488.

It broke torcs.
2019-12-30 18:41:24 -05:00
Alyssa Rosenzweig
3909b16000 panfrost: Respect glPointSize()
We have native support for this somehow. Fixes the mesa demo `points`

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
8f4b15636b panfrost: Remove MRT indirection in blend shaders
Since we have a separate blend shader for each render target, let's
simplify this structure and reduce the options memory footprint by 88%
or something goofy like that.

Should also enable separate blending per render target.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
67fe2afa51 panfrost: Implement integer varyings
We need to actually work out the varying format on demand, rather than
assuming rgba32f.

Fixes dEQP-GLES3.functional.fragment_out.basic.int.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
62d056d8e3 panfrost: Disable some CAPs we want lowered
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
71df7c69bc panfrost: Identify glProvokingVertex flag
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
c17a441666 pan/midgard: Implement flat shading
We need to shuffle around some lowerings but it's just a flag.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
66c2696fda pan/midgard: Use type-appropriate st_vary
We would like to store (u)ints as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
3996fd7b90 pan/midgard: Promote tilebuffer reads to 32-bit
Fixes (among others)
dEQP-GLES3.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgba16f

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-30 17:11:08 -05:00
Alyssa Rosenzweig
ddc5a371b3 glsl: Set .flat for gl_FrontFacing
It is a boolean.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3237>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3237>
2019-12-30 19:54:50 +00:00
Samuel Pitoiset
824bd0830e radv: return the correct pitch for linear mipmaps on GFX10
On GFX9, the pitch of a level is always the pitch of the entire image
but not on GFX10.

This fixes graphics glithes with Halo - The Master Chief Collection.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2188
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-30 14:17:45 +01:00
Yevhenii Kolesnikov
b318bc2072 meta: Cleanup function for DrawTex
Buffer object was never freed, causing memory leaks.

Fixes: 76cfe2bc44 ("meta: Don't pollute the buffer object namespace in _mesa_meta_DrawTex")
CC: Ian Romanick <ian.d.romanick@intel.com>

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1390>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1390>
2019-12-30 12:41:52 +02:00
Jan Zielinski
7040d6c197 gallium/gallivm/tgsi: enable tessellation shaders
Tessellation Control and Evaluation shaders are implementing
tessellation and require special handling of their inputs
and outputs.

TCS can write out not only per-vertex, but also per-patch
(per-primitive) attributes and tessellation factor values
that control the tessellator.

TES can read TCS outputs, plus must be feeded with new
system values (tessellation coordinates) that are
outputs of the tessellator fixed function.

TCS can also contain calls to barrier() function (similar
to compute shaders).

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-12-30 11:32:47 +01:00
Dave Airlie
26c5ae80f0 llvmpipe: enable ARB_shader_group_vote.
This just adds the NIR paths for shader group vote.

v2: drop feq for now. (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3213>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3213>
2019-12-30 05:30:30 +00:00
Bas Nieuwenhuizen
88f567b5ce amd/common: Handle alignment of 96-bit formats.
addrlib doesn't quite do it right, so do it ourselves.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2162
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-30 00:02:46 +01:00
Caio Marcelo de Oliveira Filho
b0203b561c panfrost: Fix Makefile.sources
Add missing `\`.  Fixes Android build.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: de077c2078 ("panfrost: Remove mali_alt_func")
2019-12-28 12:31:41 -08:00
Eric Engestrom
a6873a8df2 mesa: avoid returning a value in a void function
Fixes: 1d1722e910 ("mesa: add EXT_dsa NamedProgram functions")
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-28 11:58:37 +00:00
Eric Engestrom
dcba7731e6 meson: simplify install_megadrivers.py invocation
Note: `find_program()` needs a shebang on scripts.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-27 22:43:34 +00:00
Eric Engestrom
ff3a2576a4 nine: fix empty-body-issues
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2019-12-27 22:09:16 +00:00
Eric Engestrom
51569e525a amd: fix empty-body issues
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2019-12-27 22:09:00 +00:00
Eric Engestrom
7a4a75a185 u_format: move format tests to util/tests/
Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-27 21:04:44 +00:00
Eric Engestrom
da9937d09b util/format: add trivial srgb<->linear conversion test
This would've caught 8829f9ccb0 ("u_format: add ETC2 to
util_format_srgb/util_format_linear").

Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-27 21:04:43 +00:00
Eric Engestrom
8f4d4c808b util/format: add PIPE_FORMAT_ASTC_*x*x*_SRGB to util_format_{srgb,linear}()
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-27 21:04:43 +00:00
Eric Engestrom
cc7a64f101 util/format: remove left-over util_format_description_table declaration
Fixes: 3c45c4bc44 ("util: Cope with the fact that formats in u_format.csv are not ordered.")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-27 21:04:43 +00:00
Dave Airlie
baa064f0f5 gallivm: fixup const int64 builder.
Pointed out by Ilia.

Fixes: 84ba008774 (gallivm: add 64-bit const int creator.)
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-28 05:44:31 +10:00
Marek Olšák
e79f55ff86 radeonsi/gfx10: improve performance for TES using PrimID but not exporting it
This field is really for the primitive export to the pixel shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
Marek Olšák
aa3df12fc2 radeonsi/gfx10: enable NGG passthrough for eligible shaders
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
Marek Olšák
17164d4e27 radeonsi/gfx10: don't declare any LDS for NGG if it's not used
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
Alyssa Rosenzweig
65e5c1942a panfrost: Remove 32-bit next_job path
It has been unused for a while; let's just remove the abstraction.
Technically the hardware does support 32-bit job descriptors, but we
don't and we can't keep them from breaking so let's not pretend they
work.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-12-27 13:03:22 -05:00
Alyssa Rosenzweig
95ba661b49 panfrost; Update comment about work/uniform_count
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 13:01:17 -05:00
Alyssa Rosenzweig
de077c2078 panfrost: Remove mali_alt_func
There's only one way to encode comparison functions in the command
stream, not two. It's just that the semantics for texture comparisons
are flipped from the semantics of stencil comparison. We can factor out
that flip to common Panfrost code, rather than tying it to a second
Gallium routine.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:58:00 -05:00
Alyssa Rosenzweig
bc1fc29e21 panfrost: Add missing #include in common header
Fixes way back when...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:58:00 -05:00
Alyssa Rosenzweig
330e9b154e panfrost: Add pan_attributes.c to Android.mk
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 31305e1b28 ("panfrost: Move instancing routines to encoder/")
2019-12-27 12:58:00 -05:00
Alyssa Rosenzweig
5fe58271b2 panfrost: Implement remaining texture wrap modes
Somehow we have native hardware for all of these. Suspected by staring
at the bit pattern; confirmed by poking in various texture wrap modes
into the textures mesa demo and seeing what happens.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:58:00 -05:00
Alyssa Rosenzweig
4ccd42e0bc panfrost: Inline away MALI_NEGATIVE
It's an awfully fancy way to add one...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:16:09 -05:00
Alyssa Rosenzweig
76519b216b panfrost: Remove MALI_ATTR_INTERNAL
It's a relic from before we understood the varying builtins. It should
never actually come up if the builtins are decoded correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:11:37 -05:00
Alyssa Rosenzweig
5f8376101d panfrost: Update information on fixed attributes/varyings
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:10:24 -05:00
Alyssa Rosenzweig
9bde6e551d panfrost: Remove MALI_SPECIAL_ATTRIBUTE_BASE defines
These are conventions by the blob (a convention we happent to follow).
They are not at all intrinsic to the hardware, so now that the
convention is implemented within the Midgard stack, these defines are
wholly unused. Remove them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-27 12:08:45 -05:00
Alyssa Rosenzweig
8c188722d9 pan/midgard: Fix minor typo
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-12-27 12:07:45 -05:00
Mauro Rossi
563bd61fee android: radv: build radv_shader_args.c
Updates radv Makefile.sources and fixes the following building error:

external/mesa/src/amd/vulkan/radv_shader.c:1122:
error: undefined reference to 'radv_declare_shader_args'

Fixes: 3b14336 ("ac/nir, radv, radeonsi: Switch to using ac_shader_args")
Fixes: 66c703b ("radv: Move argument declaration out of nir_to_llvm")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-27 09:20:54 +01:00
Mauro Rossi
962b70c259 android: radeonsi,ac: fix building error due to ac changes
Updates amd Makefile.sources and fixes the following building errors:

external/mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:338: error: undefined reference to 'ac_add_arg'
external/mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:340: error: undefined reference to 'ac_add_arg'
external/mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:341: error: undefined reference to 'ac_add_arg'
external/mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:342: error: undefined reference to 'ac_add_arg'

Fixes: 9885af3 ("ac: Add a shared interface between radv, radeonsi, LLVM and ACO")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-27 09:20:49 +01:00
Mauro Rossi
ad1c65e322 android: radv: fix vk_format_table.c generated source build
RADV Android build rules are now getting the wrong vk_format.h
from src/vulkan/util include, the simplest way to fix is to add
src/amd/vulkan include prior to src/vulkan/util include

Fixes the following building errors:

out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_radv_common_intermediates/vk_format_table.c:39:4:
 error: use of undeclared identifier 'VK_FORMAT_LAYOUT_PLAIN'
...
out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_radv_common_intermediates/vk_format_table.c:131:8:
error: use of undeclared identifier 'VK_FORMAT_TYPE_UNSIGNED'; did you mean 'UTIL_FORMAT_TYPE_UNSIGNED'?
      {VK_FORMAT_TYPE_UNSIGNED, true, false, false, 4, 0},      /* x = a */
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.

Fixes: 3a28281 ("util: Add a mapping from VkFormat to PIPE_FORMAT.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-27 09:20:44 +01:00
Mauro Rossi
13ef793770 android: util: Add a mapping from VkFormat to PIPE_FORMAT.
Updates Makefile.sources and fixes the following building error:

In file included from external/mesa/src/vulkan/util/vk_format.c:24:
In file included from external/mesa/src/vulkan/util/vk_format.h:28:
external/mesa/src/util/format/u_format.h:33:10: fatal error: 'pipe/p_format.h' file not found
#include "pipe/p_format.h"
         ^~~~~~~~~~~~~~~~~
1 error generated.

Fixes: 3a28281 ("util: Add a mapping from VkFormat to PIPE_FORMAT.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-27 09:20:40 +01:00
Mauro Rossi
200be80858 android: nir: add a load/store vectorization pass
Fixes the following aco building error:

external/mesa/src/amd/compiler/aco_instruction_selection_setup.cpp:846:
error: undefined reference to 'nir_opt_load_store_vectorize'

Fixes: ce9205c ("nir: add a load/store vectorization pass")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-27 09:20:35 +01:00
Dave Airlie
c8042c289e llvmpipe: add debug option to enable OpenCL support.
LP_DEBUG=cl will enable CL support for now.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
29784bb49c gallivm/nir: add vec8/16 support
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
5be1ea7d79 gallivm/nir: lower packing
This fixes some CL upsample tests, which lower into packing that needs
lowering.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
31e0e8a51b llvmpipe: lower hadd/add_sat
Fixes some CL piglits.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
0a73eafdbe gallivm: handle non-32 bit undefined
other sized undefs caused llvm asserts

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
b16fd4d9e9 llvmpipe/nir: use nir_max_vec_components in more places
This is prep work for when vec8/16 have landed.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
073734ca7f llvmpipe: add support for compute shader params
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
22d631e235 llvmpipe: handle serialized nir as a shader type.
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
264663d55d gallivm/llvmpipe: add support for global operations.
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:33 +10:00
Dave Airlie
9630c2ddd8 gallivm/llvmpipe: add support for block size intrinsic
We have to pass the main block size into the coroutine
and into the shader.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:32 +10:00
Dave Airlie
336954f7e7 gallivm/llvmpipe: add support for work dimension intrinsic.
We have to pass the work_dim given by the user into the shader.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:32 +10:00
Dave Airlie
b8d403c03f tgsi/mesa: handle KERNEL case
Translate to compute for now.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:32 +10:00
Dave Airlie
dac8cb981f gallivm/nir: allow 8/16-bit conversion and comparison.
This adds the convert to 8/16 and support for 8/16 comparsions

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:32 +10:00
Dave Airlie
3adf74f2ef gallivm: pick integer builders for alu instructions.
This allows these to be used with non 32-bit types.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:26:32 +10:00
Dave Airlie
df3e0fe9d8 gallivm: add support for 8-bit/16-bit integer builders
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:22:43 +10:00
Dave Airlie
258b9bc02e llvmpipe/gallivm: add kernel inputs
compute shaders need kernel input support

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:22:40 +10:00
Dave Airlie
84ba008774 gallivm: add 64-bit const int creator.
Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-12-27 13:22:35 +10:00
Dave Airlie
41c77dbc1e nir: sanitize work group intrinsics to always be 32-bit.
This saves handling them in the backend later.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-12-27 13:22:34 +10:00
Bas Nieuwenhuizen
a435f002c4 radv: Expose all sample counts for integer formats as well.
Things work the same between float and integer.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2261
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-26 10:48:29 +01:00
Alyssa Rosenzweig
be691ca22d panfrost: Route gl_VertexID through cmdstream
It shows up as a special (magic?) attribute. We could try to be clever
and only include the extra record if gl_VertexID is actually read, but
honestly that's just extra complexity for no good reason. Might as well
just always include it; this won't be a real bottleneck, I don't think.

Fixes dEQP-GLES3.functional.shaders.builtin_variable.vertex_id.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:55:04 -05:00
Alyssa Rosenzweig
8781378224 panfrost: Extend attribute_count for vertex builtins
They stretch beyond the usual limit for attributes so are included
implicitly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:55:04 -05:00
Alyssa Rosenzweig
306800d747 pan/midgard: Lower gl_VertexID/gl_InstanceID to attributes
We have special records for these, put in a fixed location by convention
per the blob.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:55:04 -05:00
Alyssa Rosenzweig
6e68890fd6 pan/midgard: Factor out emit_attr_read
We will load attributes directly for gl_VertexID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:55:04 -05:00
Alyssa Rosenzweig
695b35605b panfrost: Unset vertex_id_zero_based
We don't want the lowering; we have native gl_VertexID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:55:04 -05:00
Alyssa Rosenzweig
3b3d9653a7 pan/decode: Handle gl_VertexID/gl_InstanceID
Just like varyings have special records for point coordinates (etc),
attributes have special records for vertex/instance ID. We can parse
these fairly easily, although they don't line up exactly with normal
attribute records.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:54:58 -05:00
Alyssa Rosenzweig
d36ca7c0a3 panfrost: Remove pan_shift_odd
Padded counts are numbers of the form:

   n = (2k + 1) * 2^s

for k, s integers. Rather than explicitly store k and s separately and
then compute this formula on demand, it's much cleaner to store the
padded number itself, which is what you manipulate most of the time.
When you do need k,s it is easy to factor by noticing the bitwise
representation:

   s = ctz(n)
   k = n >> (s + 1)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:42:07 -05:00
Alyssa Rosenzweig
62ce9001c2 panfrost: Slight cleanup of Gallium's pan_attribute.c
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:42:07 -05:00
Alyssa Rosenzweig
385a4f773f pan/decode: Fix reference computation for invocations
Slight bug with instancing. No harm done but let's get rid of the
pandecode warning, it's just noise.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:42:07 -05:00
Alyssa Rosenzweig
9c249d3e6b panfrost: Fix off-by-one in pan_invocation.c
When instance_count=2, the packing code was broken. Fixes a dEQP test.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:42:07 -05:00
Alyssa Rosenzweig
467ae0d39d panfrost: Factor out panfrost_compute_magic_divisor
The algorithm doesn't need to be tangled up in details about the
attribute records themselves. We'll need to compute magic divisors for
gl_InstanceID in a second.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 22:42:07 -05:00
Alyssa Rosenzweig
31305e1b28 panfrost: Move instancing routines to encoder/
Nothing Gallium specific or stateful about them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:48:57 -05:00
Alyssa Rosenzweig
8a57672673 panfrost: Factor batch/resource out of instancing routines
They don't need them; this will allow us to move the code into encoder/
which in turn will make the messy Gallium code less scary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:48:57 -05:00
Alyssa Rosenzweig
ddcd68f52b panfrost: Rename pan_instancing.c -> pan_attributes.c
Let's follow the naming convention that panfrost command stream code is
organized by command stream structure.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:48:57 -05:00
Alyssa Rosenzweig
a0e75adabb pan/midgard: Compute destination override
We shift over the mask in this case.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:23:02 -05:00
Alyssa Rosenzweig
9a5d462480 pan/midgard: Add mir_upper_override helper
Checks if we should emit a dest_override=upper, given a mask.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:23:02 -05:00
Alyssa Rosenzweig
fc4193d0c7 pan/midgard: Support loads from R11G11B10 in a blend shader
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:22:54 -05:00
Alyssa Rosenzweig
3af5a398f3 pan/midgard: Enable lower_(un)pack_* lowering
These show up in some blend shaders. Let's use the shared lowering and
remove our own.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 19:21:52 -05:00
Tomeu Vizoso
843a6db6bb panfrost: Increase PIPE_SHADER_CAP_MAX_OUTPUTS to 16
GL ES 3.0 requires it to be higher, and stuff seems to work just fine.

Fixes: dEQP-GLES3.functional.implementation_limits.max_vertex_output_components

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-24 19:21:52 -05:00
Tomeu Vizoso
f107059bb2 panfrost: Handle Z24_UNORM_S8_UINT as MALI_Z32_UNORM
Fixes dEQP-GLES3.functional.texture.format.sized.2d.depth24_stencil8_pot

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-24 19:21:52 -05:00
Alyssa Rosenzweig
6b7243f28f pan/midgard: Implement shadow cubemaps
We need to reshuffle to sync up the shadow coordinate temporary with the
cubemap coordinate temporary. Once that's in place, it's simple enough
(we load the shadow coordinate into .z like 2D).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:23 +00:00
Alyssa Rosenzweig
9e5a1412ed pan/midgard: Generalize temp coordinate to non-2D
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:23 +00:00
Alyssa Rosenzweig
1bce7fdecd pan/midgard: Do witchcraft on texture offsets
My latest divination spell has uncovered a pattern in the aether.
Although the swizzle is unaligned, its format is otherwise standard.
Document this, removing the old incorrect understanding of the swizzle
(which coincided on common special swizzles only).

Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetchoffset.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:23 +00:00
Alyssa Rosenzweig
4ec1f95d76 pan/midgard: Fix fallthrough from offset to comparator
Fixes: ccbc9a4e67 ("pan/midgard: Implement textureOffset for 2D textures")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:22 +00:00
Alyssa Rosenzweig
64b2fe9626 pan/midgard: Expand swizzle for texelFetch
We zero the extra components anyway. Fixes
dEQP-GLES3.functional.shaders.texture_functions.texelfetch.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:22 +00:00
Alyssa Rosenzweig
72e5749a63 pan/midgard: Clamp LOD register swizzle
Fixes register allocation failures with textureLodOffset.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:22 +00:00
Alyssa Rosenzweig
06df977c1c pan/midgard: Extend IS_VEC4_ONLY to arguments
I think both need to be aligned at least for ld_cubemap_coords.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:22 +00:00
Alyssa Rosenzweig
4e75d75724 pan/midgard: Bounds check lcra_restrict_range
We may call it with sentinel values (~0 in particular) corresponding to
unused arguments; ignore these.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 23:46:22 +00:00
Rob Clark
0c32063794 freedreno/ir3: fix flat shading again
These days `ctx->inputs` is the split scalar input components and
`ir->inputs` is the full vecN.  This got fixed in the load_input case,
but the load_interpolated_input case was missed.

Fixes: bdf6b7018c ("freedreno/ir3: re-work shader inputs/outputs")
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-24 17:16:31 +00:00
Alyssa Rosenzweig
a8beef332d pan/midgard: Fix disassembler cycle/quadword counting
Due to the succeeding break we would fall into some off-by-one errors.
These should be resolved now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 16:55:46 +00:00
Alyssa Rosenzweig
0cc6e33537 pan/decode: Append 0:0 spills:fills to blobber-db
At the moment there's no need to actually count these but we do need a
placeholder for report.py to be happy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 16:55:46 +00:00
Alyssa Rosenzweig
6a74934e7a pan/decode: Prefix blobberdb with MESA_SHADER_*
We use these prefixes in panfrost shader-db and they need to match for
shader-db to be happpy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 16:55:46 +00:00
Alyssa Rosenzweig
ead35f586c pan/decode: Skip COMPUTE in blobber-db
The blob uses COMPUTE jobs for some internal purposes. These are
essentially free but panfrost doesn't use them, so it messes up the
numbering. Just filter them out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 16:55:46 +00:00
Alyssa Rosenzweig
09671c8d68 panfrost: Decode shader types in pantrace shader-db
We see some COMPUTE jobs that were mistakenly identified as VERTEX.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-24 16:55:46 +00:00
Jason Ekstrand
ac70442ce1 anv: Properly advertise sampledImageIntegerSampleCounts
We support the same set of samples for integer color formats as for
non-integer.  We've been advertising it wrong since before the initial
Vulkan 1.0 release. :-(

Fixes: d689745303 "vk/0.210.0: Rework device features and limits"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-24 08:31:44 -06:00
Roman Stratiienko
c411d4896c Android: Fix build issue without LLVM
Some of the latest changes are causing the following build error on Android:

```
external/mesa3d/src/gallium/auxiliary/nir/nir_to_tgsi_info.c:403:6:
error: redefinition of 'nir_tgsi_scan_shader'
void nir_tgsi_scan_shader(const struct nir_shader *nir,
     ^
external/mesa3d/src/gallium/auxiliary/nir/nir_to_tgsi_info.h:37:20:
note: previous definition is here
static inline void nir_tgsi_scan_shader(const struct nir_shader *nir,
                   ^
```

Include nir_to_tgsi_info.c and nir_to_tgsi_info.h into the build
only if LLVM is enabled.

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2978>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2978>
2019-12-23 10:22:02 +02:00
Kenneth Graunke
97e9de1795 iris: Avoid replacing backing storage for buffers with no contents
We might get asked to pitch the storage on a buffer that already has
no meaningful contents.  In this case, the existing buffer is as good
as a new one.
2019-12-22 16:18:30 -08:00
Kenneth Graunke
c96c1141fb iris: Fix shader recompile debug printing
I was passing iris keys to brw_debug_key_recompile, leading to out of
bounds memory reads.

Fixes: 2e654db27a ("iris: Create smaller program keys without legacy features")
2019-12-22 16:18:30 -08:00
Kenneth Graunke
1ef4514c5b iris: Make helper functions to turn iris shader keys into brw keys.
We'll need to use these in recompile debugging in the next commit.

Fixes: 2e654db27a ("iris: Create smaller program keys without legacy features")
2019-12-22 16:18:30 -08:00
Vinson Lee
2d971cc1ca swr: Fix build with llvm-10.0.
Fix build error after llvm-10 commit 5d986953c8b9 ("[IR] Split out
target specific intrinsic enums into separate headers").

../src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp:78:37: error: ‘x86_bmi_bextr_32’ is not a member of ‘llvm::Intrinsic’
         {"meta.intrinsic.BEXTR_32", Intrinsic::x86_bmi_bextr_32},
                                     ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-12-21 16:36:27 -08:00
Eric Engestrom
bc943d00aa travis: autodetect python version instead of hard-coding it
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-21 20:23:08 +00:00
Marek Vasut
45e1443fd8 etnaviv: tgsi: Fix gl_FrontFacing support
The GPU presents the state of the hardware front_face in internal
register 0 (i0), the range of which is 0.0f..1.0f.

This patch assigns the fragment shader input to this internal register.
Moreover, based on the internal front_ccw state, the value of the i0
register is inverted accordingly using SET.EQ/SEQ.NE instruction before
being further processed in the shader. This mimics the operation of the
NIR compiler.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2868>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2868>
2019-12-21 20:17:27 +01:00
Paul Cercueil
63b33120b7 u_vbuf: Return true in u_vbuf_get_caps if nb of vbufs is below minimum
Return true in u_vbuf_get_caps if the number of vertex buffers is below
the minimum required for proper OpenGL 2.0.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Paul Cercueil
c6ef79c488 u_vbuf: Regard non-constant vbufs with non-instance elements as free
In the case of unroll_indices, we can regard all non-constant
vertex buffers with only non-instance vertex elements as incompatible
and thus free.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Wladimir J. van der Laan
87a6029ccf u_vbuf: use single vertex buffer if it's not possible to have multiple
Put CONST, VERTEX and INSTANCE attributes into one vertex buffer if
necessary due to hardware constraints.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Paul Cercueil
18a8c3f7f1 u_vbuf: Only create driver CSO if no incompatible elements
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Paul Cercueil
88d041a6b9 u_vbuf: Mark vbufs incompatible if more were requested than HW supports
More vertex buffers are used than the hardware supports.  In
principle, we only need to make sure that less vertex buffers are
used, and mark some of the latter vertex buffers as incompatible.
For now, mark all vertex buffers as incompatible.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Wladimir J. van der Laan
5f37e38b81 u_vbuf: add logic to use a limited number of vbufs
Make it possible to limit the number of vertex buffers as there exist
GPUs with less then 32 supported vertex buffers.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
Christian Gmeiner
5bd6a5c41b gallium: add PIPE_CAP_MAX_VERTEX_BUFFERS
Add PIPE_CAP_MAX_VERTEX_BUFFERS param, which defaults to 16.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2807>
2019-12-21 18:29:30 +00:00
David Heidelberg
5343124932 .mailmap: use correct email address
Signed-off-by: David Heidelberg <david@ixit.cz>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3190>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3190>
2019-12-21 17:50:01 +00:00
Paul Cercueil
2bbf8ebadc kmsro: Extend to include ingenic-drm
This enables Mesa to work with Ingenic SoCs through the use of the
ingenic-drm modesetting driver along with the render-only drivers,
such as Etnaviv on the JZ4770 SoC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-21 18:27:51 +01:00
Stephan Gerhold
4da46a1c3c kmsro: Add "mcde" entry point
ST-Ericsson Ux500 boards use a Mali 400 GPU together with MCDE
("Multi Channel Display Engine"), which is supported by the "mcde"
DRM driver.

Adding an entry point for it in kmsro seems to be enough to make
Lima work - at least kmscube is working correctly.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3139>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3139>
2019-12-21 16:43:35 +00:00
Rhys Perry
afe1a8ff5b aco: fix vgpr alloc granule with wave32
We still need to increase the number of physical vgprs

Totals from affected shaders:
SGPRS: 671976 -> 675288 (0.49 %)
VGPRS: 550112 -> 562596 (2.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 27621660 -> 27606532 (-0.05 %) bytes
Max Waves: 81083 -> 87833 (8.32 %)
Instructions: 5391560 -> 5389031 (-0.05 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-21 12:38:42 +01:00
Rhys Perry
01ccd7839c aco: improve jump threading with wave32
Totals from affected shaders:
SGPRS: 748746 -> 748746 (0.00 %)
VGPRS: 636984 -> 636984 (0.00 %)
Spilled SGPRs: 387 -> 387 (0.00 %)
Spilled VGPRs: 15 -> 15 (0.00 %)
Code Size: 61138824 -> 60928620 (-0.34 %) bytes
Max Waves: 48602 -> 48602 (0.00 %)
Instructions: 11967660 -> 11915084 (-0.44 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-21 12:38:42 +01:00
Rhys Perry
6ff92f3d68 aco/wave32: fix comparison optimizations
Previously, they weren't done in wave32.

Totals from affected shaders:
SGPRS: 507726 -> 508006 (0.06 %)
VGPRS: 450340 -> 450268 (-0.02 %)
Spilled SGPRs: 298 -> 298 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 39689708 -> 39384488 (-0.77 %) bytes
Max Waves: 39631 -> 39636 (0.01 %)
Instructions: 7865919 -> 7793650 (-0.92 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-21 12:38:42 +01:00
Karol Herbst
4dd08b710b nv50ir/nir: support vec8 and vec16
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-12-21 11:00:17 +00:00
Rob Clark
a8ec4082a4 nir+vtn: vec8+vec16 support
This introduces new vec8 and vec16 instructions (which are the only
instructions taking more than 4 sources), in order to construct 8 and 16
component vectors.

In order to avoid fixing up the non-autogenerated nir_build_alu() sites
and making them pass 16 src args for the benefit of the two instructions
that take more than 4 srcs (ie vec8 and vec16), nir_build_alu() is has
nir_build_alu_tail() split out and re-used by nir_build_alu2() (which is
used for the > 4 src args case).

v2 (Karol Herbst):
  use nir_build_alu2 for vec8 and vec16
  use python's array multiplication syntax
  add nir_op_vec helper
  simplify nir_vec
  nir_build_alu_tail -> nir_builder_alu_instr_finish_and_insert
  use nir_build_alu for opcodes with <= 4 sources
v3 (Karol Herbst):
  fix nir_serialize
v4 (Dave Airlie):
  fix serialization of glsl_type
  handle vec8/16 in lowering of bools
v5 (Karol Herbst):
  fix load store vectorizer

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-21 11:00:17 +00:00
Karol Herbst
b35e583c17 aco: use NIR_MAX_VEC_COMPONENTS instead of 4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-21 11:00:16 +00:00
Karol Herbst
c83b1a4560 nir/serialize: cast swizzle before shifting
fixes undefined behaviour with enabled vec16

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-21 11:00:16 +00:00
Dave Airlie
e6b2af56cb llvmpipe: switch to NIR by default
Add LP_DEBUG=tgsi_ir (tgsi already taken) to fallback to TGSI paths.

Disable NIR_VALIDATE in CI (Michel/Eric acked)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>
2019-12-21 13:07:17 +10:00
Dave Airlie
c717ac1247 gallivm/nir: wrap idiv to avoid divide by 0 (v2)
This code is taken from the TGSI paths, and should fix the regression
seens with GLES2

v2: use the udiv path which has d3d10 defined return.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2303>
2019-12-21 13:06:58 +10:00
Marek Olšák
7d65614422 ac/surface: fix an assertion failure on gfx9 in CMASK computation
addrlib only allows the 2D resource type with CMASK.

Fixes: 69ea473eeb "amd/addrlib: update to the latest version"

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3187>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3187>
2019-12-20 22:57:08 +00:00
Afonso Bordado
3e1e4ad13d pan/midgard: Optimize comparisions with similar operations
Optimizes comparisions by removing the invert flag on operands
which we can prove to be equal without the invert.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3036>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3036>
2019-12-20 22:36:06 +00:00
Erico Nunes
8e9e94d084 lima: set shader caps to optimize control flow
With these new caps, nir is able to unroll loops and optimize
conditionals much more efficiently in both gpit and ppir.
panfrost and vc4 were used as reference for the values.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>
2019-12-20 20:59:15 +01:00
Erico Nunes
4322656dee lima/ppir: remove assert on ppir_emit_tex unsupported feature
This assert causes testing tools such as shaderdb to abort on some test
cases. This is an unsupported feature and not a compiler bug. The
compilation error is already propagated correctly, so we can remove the
assert to allow testing tools to run to completion.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3176>
2019-12-20 20:58:50 +01:00
Erico Nunes
d56710ab82 lima/ppir: fix lod bias src
ppir has some code that operates on all ppir_src variables, and for that
uses ppir_node_get_src.
lod bias support introduced a separate ppir_src that is inaccessible by
that function, causing it to be missed by the compiler in some routines.
Ultimately this caused, in some cases, a bug in const lowering:

  .../pp/lower.c:42: ppir_lower_const: Assertion `src != NULL' failed.

This fix moves the ppir_srcs in ppir_load_texture_node together so they
don't get missed.

Fixes: 721d82cf06 lima/ppir: add lod-bias support

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3185>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3185>
2019-12-20 19:39:55 +00:00
Andreas Baierl
1b0743dbb6 lima: Fix dump file creation
Otherwise lima_dump_file_next() always opens a new file and creates the
dumps regardless of what the environment variables say.

Fixes d71cd245d7 ('lima: Rotate dump files after each finished pp frame')

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3179>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3179>
2019-12-20 17:44:12 +01:00
Pierre-Eric Pelloux-Prayer
9c2a3b4e75 radeon/vcn2: enable rate control for hevc encoding
Based on b0626c1f30 ("radeon/vcn: enable rate control for hevc encoding").

Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225
Fixes: 587b9c5dae ("radeon/vcn: implement vcn 2.0 encode")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
2019-12-20 16:51:53 +01:00
Samuel Pitoiset
02dd1fb859 radv: rely on pipeline layout when creating push descriptors with template
descriptorSetLayout should be ignored for push descriptors. While
we are it, also ignore pipelineBindPoint.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2210
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3180>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3180>
2019-12-20 13:41:29 +01:00
Marek Vasut
f51ee564f5 etnaviv: Replace bitwise OR with logical OR
The test here is testing whether either variable is non-zero.
While currently the test works fine, it's fragile. Replace it
with logical OR to avoid the fragility.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-20 13:15:37 +01:00
Christian Gmeiner
6e75f2172b etnaviv: update resource status after flushing
Currently piglit spec@arb_occlusion_query@occlusion_query_conform
spins for ever as the resource status is never reset. See
etna_hw_get_query_result(..) for more details.

Fixes: 1456aa61cc ("etnaviv: Rework resource status tracking")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marek Vasut <marex@denx.de>
2019-12-20 12:43:23 +01:00
Ross Zwisler
cabcbb4db0 intel: limit shader geometry on BDW GT1
Similar to the SKL GT1 fix introduced here:

b1ba7ffdbd

we need to limit the .urb.max_entries[MESA_SHADER_GEOMETRY] on BDW GT1
to address failures in these two tests:

dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d
dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_2d_array

The value 690 was found via bisection.  691 is the actual max on the
hardware I'm using, but 690 seemed like a nice round number.

Signed-off-by: Ross Zwisler <zwisler@google.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3173>
2019-12-20 10:47:52 +00:00
Alyssa Rosenzweig
c57337bbd3 pan/midgard: Lower txd with lower_tex
This is a hack since we do have native gradient stuff, but for the
moment I'm more interested in conformance and the lowered code is good
enough. Fixes
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler2d_fixed_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>
2019-12-20 09:10:39 +01:00
Alyssa Rosenzweig
da73651da4 pan/midgard: Fix crash with txs
This regressed since we implemented RECT textures natively, oops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>
2019-12-20 09:10:36 +01:00
Alyssa Rosenzweig
ccbc9a4e67 pan/midgard: Implement textureOffset for 2D textures
Fixes dEQP-GLES3.functional.shaders.texture_functions.textureoffset.sampler2d_fixed_fragment.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3169>
2019-12-20 09:10:26 +01:00
Samuel Pitoiset
2eef9e050f radv: ignore pColorBlendState if rasterization is disabled
Or if the subpass has no color attachments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:21:02 +01:00
Samuel Pitoiset
021c7b5309 radv: tidy up radv_pipeline_init_blend_state()
This is needed for the next commit because pColorBlendState can
actually be NULL but some fields might have to be initialized
(eg. alpha to coverage with no color attachments).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:20:58 +01:00
Samuel Pitoiset
ebc7a77869 radv: ignore pDepthStencilState if rasterization is disabled
Or if the subpass has no depth stencil attachment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:20:55 +01:00
Samuel Pitoiset
ce67e41535 radv: ignore pTessellationState if the pipeline doesn't use tess
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:20:52 +01:00
Samuel Pitoiset
7735f314b7 radv: ignore pMultisampleState if rasterization is disabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:20:49 +01:00
Samuel Pitoiset
589bfcbde3 radv: init a default multisample state for the resolve FS path
pMultisampleState must be a valid pointer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3167>
2019-12-20 08:20:44 +01:00
Caio Marcelo de Oliveira Filho
4fbc99c124 spirv: Implement SPV_KHR_non_semantic_info
Do nothing for OpExtInst from extended instruction sets that name
start with "NonSemantic.".

Since they can be used within the "preamble" to annotate global
decorations, also don't stop iterating when one of them is found.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3154>
2019-12-19 22:49:39 -08:00
Jonathan Marek
13adce2845 turnip: disable B8G8R8 vertex formats
Looks like swap doesn't work as expected on these, disable them.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3170>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3170>
2019-12-19 19:03:02 -05:00
Jonathan Marek
54f72c83d6 util/format: add missing vulkan formats
Add some missing vulkan formats to util/format, this solves all the missing
pipe format cases for the formats that turnip supports.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3170>
2019-12-19 19:03:02 -05:00
Jonathan Marek
b9d4c10e4b turnip: minor warning fixes
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3177>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3177>
2019-12-19 23:21:01 +00:00
Andreas Baierl
d71cd245d7 lima: Rotate dump files after each finished pp frame
This rotates the dump files like the mali-syscall-tracker does.

After each finished pp frame a new file is generated. They are
numbered like lima.dump.0000, lima.dump.0001 ...
The filename and path can be given with the new environment
variable LIMA_DUMP_FILE.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3175>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3175>
2019-12-19 23:53:22 +01:00
Vasily Khoruzhick
039f3f6adb lima: drop suballocator
Since we're using a separate per-draw BO for GP outputs we don't
need suballocator anymore.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3158>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3158>
2019-12-19 14:28:32 -08:00
Vasily Khoruzhick
9f72d7195a lima: use single BO for GP outputs
Varyings, gl_Position and gl_PointSize are all GP outputs, so we
can use a single BO for them all. Also that allows us to get rid
of suballocator.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3158>
2019-12-19 14:28:32 -08:00
Jonathan Marek
06ae0674fd nir: fix assign_io_var_locations for vertex inputs
Also fixes fragment inputs using the wrong "base" value (which was working
only because FRAG_RESULT_DATA0 is less than VARYING_SLOT_VAR0)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3108>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3108>
2019-12-19 21:26:52 +00:00
Jonathan Marek
e9a32af3bf turnip: implement secondary command buffers
Uses a new "tu_cs_add_entries" function because tu_cs_emit_call doesn't
work inside draw_cs (which is already called by tu_cs_emit_call).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3075>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3075>
2019-12-19 20:42:08 +00:00
Jonathan Marek
85fff42d08 turnip: compute gmem offsets at renderpass creation time
This makes it easier to implement secondary command buffers, since we no
longer need to know the render area to set the gmem offsets for input
attachments and CmdClearAttachments.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3075>
2019-12-19 20:42:08 +00:00
Jonathan Marek
f81c41a812 turnip: emit_compute_driver_params fixes
Offset was wrong, it is in vec4 not dwords.

There's a hole between DP_NUM_WORK_GROUPS_Z and DP_LOCAL_GROUP_SIZE_X so
use the IR3 enums.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
2019-12-19 15:13:40 -05:00
Jonathan Marek
bb134c5316 turnip: emit base instance vs driver param
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
2019-12-19 15:13:40 -05:00
Jonathan Marek
a3a70588c0 freedreno/ir3: support load_base_instance
Not supported by hardware, uses same mechanism as base vertex.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
2019-12-19 15:13:40 -05:00
Jonathan Marek
5c17d9b9ca freedreno/registers: document vertex/instance id offset bits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
2019-12-19 15:13:40 -05:00
Neha Bhende
83ad2e5084 st/mesa: release tgsi tokens for shader states
Since we are using st_common_variant while creating variant for vertext
program, we can release tokens created in st_create_vp_variant which
are already stored in respective states.
This fix memory leak found with piglit tests

Fixes bc99b22a30 ('st/mesa: use a separate VS variant for the draw module')

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-12-19 14:40:08 -05:00
Juan A. Suarez Romero
7f821289cb Revert "nir/lower_double_ops: relax lower mod()"
This reverts commit 8172b1fa03.

This commit was done taking in account Vulkan spec, but did not realize
it was affecting OpenGL too.

Closes: #2252
2019-12-19 20:01:16 +01:00
Kristian H. Kristensen
a4db9a1512 freedreno/a6xx: Set up multisample sysmem MRTs correctly
We had an extra factor of num_samples in the stride.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
e688a16e2b freedreno/a6xx: Rewrite compressed blits in a helper function
Similar to how we handle zs blits.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
f8c0ea61e4 freedreno/a6xx: Move handle_rgba_blit() up
If we move this function up, we don't have to forward declare it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
183d482f7f freedreno/a6xx: Handle srgb blits on the blitter
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
3a18e5d420 freedreno/a6xx: Use A6XX_SP_2D_SRC_FORMAT_MASK macro
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
e4c2bb6a93 freedreno/a6xx: RB6_R8G8B8 is actually 32 bit RGBX
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
8089fb2e62 freedreno/a6xx: Use blitter for resolve blits
We have a SAMPLES_AVERAGE bit that does what we need for resolving
multisample buffers - let's use it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
1d7267fc91 freedreno/a6xx: Add fd_resource_swap() helper
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
e0ebaa819d freedreno/a6xx: Pick blitter swap based on resource tiling
The linear levels in a tiled resource are stored in the canonical
swap, WZYX.  We need to pick the swap based on whether or not the
resource is tiled, not whether the the level in question is tiled.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
b59222640e freedreno/a6xx: Program sampler swap based on resource tiling
It doesn't matter whether or not the level in question is linear.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
a2f6c44a1c freedreno: Add debug flag for forcing linear layouts
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Kristian H. Kristensen
d908a2ab18 freedreno/a6xx: Make DEBUG_BLIT_FALLBACK only dump fallbacks
Use new macro, DEBUG_BLIT, for dumping all blits.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
2019-12-19 09:56:05 -08:00
Jonathan Marek
fe4a8df9a8 freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs
The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the
second part for sysvals.

The sysvals don't need to be pre-assigned since the state for those isn't
shared between binning / nonbinning shaders.

Fixes assert failures in cases where the sysvals didn't end up in the same
registers for binning / nonbinning.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
2019-12-19 11:31:12 -05:00
Thong Thai
2add63060b st/va: Convert interlaced NV12 to progressive
In vlVaDeriveImage, convert interlaced NV12 buffers to progressive.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1193
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3157>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3157>
2019-12-19 15:49:09 +00:00
Alyssa Rosenzweig
5710250074 pan/midgard: Add uniform/work heuristic
Uniform/work registers are partitioned on a shader-by-shader basis as
determined by the compiler. We add a simple heuristic here running
before scheduling that prioritizes mitigating spilling at all costs.

A more sophisticated heuristic should run *after* scheduling, doing a
dry run of the register allocator itself to determine spilling. Fitting
this into our current scheduling model is difficult, so while this
heuristic does hurt some shaders, overall the results are acceptable:

total instructions in shared programs: 50065 -> 38747 (-22.61%)
instructions in affected programs: 37187 -> 25869 (-30.44%)
helped: 59
HURT: 77
helped stats (abs) min: 1 max: 757 x̄: 198.46 x̃: 151
helped stats (rel) min: 0.48% max: 62.89% x̄: 32.95% x̃: 36.27%
HURT stats (abs)   min: 1 max: 9 x̄: 5.08 x̃: 6
HURT stats (rel)   min: 0.92% max: 14.29% x̄: 6.71% x̃: 4.60%
95% mean confidence interval for instructions value: -111.15 -55.29
95% mean confidence interval for instructions %-change: -14.33% -6.67%
Instructions are helped.

total bundles in shared programs: 30606 -> 19157 (-37.41%)
bundles in affected programs: 23907 -> 12458 (-47.89%)
helped: 58
HURT: 74
helped stats (abs) min: 6 max: 757 x̄: 203.09 x̃: 152
helped stats (rel) min: 5.19% max: 77.00% x̄: 49.38% x̃: 53.79%
HURT stats (abs)   min: 1 max: 9 x̄: 4.46 x̃: 5
HURT stats (rel)   min: 1.85% max: 26.32% x̄: 11.70% x̃: 9.57%
95% mean confidence interval for bundles value: -115.46 -58.01
95% mean confidence interval for bundles %-change: -20.87% -9.41%
Bundles are helped.

total quadwords in shared programs: 31305 -> 32027 (2.31%)
quadwords in affected programs: 20471 -> 21193 (3.53%)
helped: 0
HURT: 133
HURT stats (abs)   min: 1 max: 9 x̄: 5.43 x̃: 5
HURT stats (rel)   min: 0.76% max: 15.15% x̄: 5.47% x̃: 4.65%
95% mean confidence interval for quadwords value: 5.00 5.86
95% mean confidence interval for quadwords %-change: 4.85% 6.08%
Quadwords are HURT.

total registers in shared programs: 2256 -> 2545 (12.81%)
registers in affected programs: 708 -> 997 (40.82%)
helped: 0
HURT: 95
HURT stats (abs)   min: 1 max: 8 x̄: 3.04 x̃: 3
HURT stats (rel)   min: 12.50% max: 100.00% x̄: 39.41% x̃: 37.50%
95% mean confidence interval for registers value: 2.64 3.45
95% mean confidence interval for registers %-change: 34.62% 44.19%
Registers are HURT.

total threads in shared programs: 1776 -> 1709 (-3.77%)
threads in affected programs: 134 -> 67 (-50.00%)
helped: 0
HURT: 67
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.

total spills in shared programs: 3868 -> 2 (-99.95%)
spills in affected programs: 3868 -> 2 (-99.95%)
helped: 60
HURT: 0

total fills in shared programs: 6456 -> 4 (-99.94%)
fills in affected programs: 6456 -> 4 (-99.94%)
helped: 60
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>
2019-12-19 15:22:39 +00:00
Samuel Pitoiset
13b4e9adcf ac: declare an enum for the OOB select field on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>
2019-12-19 15:15:32 +01:00
Samuel Pitoiset
f3cccd05d9 radv/gfx10: fix the out-of-bounds check for vertex descriptors
When stride is 0, it should check against the offset not the index.

This fixes black character models with Beat Saber and missing snow
with Dragon Quest.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2233
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1975
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>
2019-12-19 15:15:30 +01:00
Juan A. Suarez Romero
8172b1fa03 nir/lower_double_ops: relax lower mod()
Currently when lowering mod() we add an extra instruction so if
mod(a,b) == b then 0 is returned instead of b, as mathematically
mod(a,b) is in the interval [0, b).

But Vulkan spec has relaxed this restriction, and allows the result to
be in the interval [0, b].

This commit takes this in account to remove the extra instruction
required to return 0 instead.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>
2019-12-19 12:36:30 +00:00
Erik Faye-Lund
af65bfb38f zink: implement nir_texop_txd
This lets us enable PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, which in turns
gives us ARB_shader_texture_lod.

Still fails one piglit test on ANV, namely
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,
but with 33 new passing tests, I think this is worth it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>
2019-12-19 13:14:29 +01:00
Erik Faye-Lund
b31d1b73bc zink: enable PIPE_CAP_MIXED_COLORBUFFER_FORMATS
This just works in Vulkan, there's no work neeed to enable it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>
2019-12-19 10:08:13 +01:00
Jonathan Marek
5785bcc8a0 turnip: don't set SP_FS_CTRL_REG0_VARYING if only fragcoord is used
Fixes artifacts in the subpasses demo, which has a shader using fragcoord
without any varyings. It looks like setting this bit when there are no
varyings can cause weirdness in some cases (without this change, if the
previous shader had <= 8 varyings it would work, but with 9 varyings it
would have artifacts).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>
2019-12-18 19:03:37 -05:00
Jonathan Marek
4a59bc6df2 turnip: add cache invalidate to fix input attachment cases
Fixes artifacts in the subpasses demo.

Workaround texture cache with input attachments from GMEM by adding a cache
invalidate between subpasses.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>
2019-12-18 19:03:37 -05:00
Lionel Landwerlin
fc2552b644 loader: fix close on uninitialized file descriptor value
Using a drm syscall layer faking a kernel driver :

  ==581460== Conditional jump or move depends on uninitialised value(s)
  ==581460==    by 0x48A4C2B: close (drm-hooks.cpp:185)
  ==581460==    by 0x5A815F1: dri3_alloc_render_buffer (loader_dri3_helper.c:1469)
  ==581460==    by 0x5A82050: dri3_get_buffer (loader_dri3_helper.c:1827)
  ==581460==    by 0x5A82662: loader_dri3_get_buffers (loader_dri3_helper.c:2028)
  ==581460==    by 0x6C78109: intel_update_image_buffers (brw_context.c:1870)
  ==581460==    by 0x6C77805: intel_update_renderbuffers (brw_context.c:1499)
  ==581460==    by 0x6C7789D: intel_prepare_render (brw_context.c:1520)
  ==581460==    by 0x6C773D4: intelMakeCurrent (brw_context.c:1341)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 069fdd5f9f ("egl/x11: Support DRI3 v1.1")
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>
2019-12-19 00:51:36 +02:00
Connor Abbott
648cc22afb freedreno: Fix CP_MEM_TO_REG flag definitions
These actually mean something completely different, at least on A5xx
and A6xx. The only other usage of the old flags on something older than
A6xx was a typo, so I don't know if it was always this way, but at the
same time it means that we don't have to worry too much about that.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
2019-12-18 23:09:05 +01:00
Connor Abbott
4c5ac156c3 freedreno: Use new macros for CP_WAIT_REG_MEM and CP_WAIT_MEM_GTE
Similar to the existing usage for CP_COND_WRITE5, this makes it clear
what each of the magic parameters are for.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
2019-12-18 23:09:00 +01:00
Connor Abbott
cfa1fb895a a6xx: Add more CP packets
And add fields uncovered by looking at the firmware. I think this covers
all the memory, register, and scratch manipulation opcodes that exist on
A6xx, plus one additional nice find for Vulkan and describing a
previously unknown opcode and documenting CP_WAIT_REG_MEM.

Note that the bits for the CP_REG_TO_MEM count, as well as the formula
for computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG,
are changed because the A630 SQE firmware actually does something
different. I haven't investigated older microcodes to see whether this
extends back to A5xx and A4xx, but the only non-A6xx uses of this
field result in the same bit-pattern when using the A6xx bit range and
formula, so it should be safe to change the definition universally.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
2019-12-18 23:08:55 +01:00
Bas Nieuwenhuizen
a9a3108be7 radv: Limit workgroup size to 1024.
Fixes a hang with geekbench.

The existence of RX 580 and NAVI10 results shows that the generations
before and after this do not have the issue. (They show up on the
website). So this is likely a GFX9 only issue.

This is not something weird like LDS size since none of the shaders
seem to use LDS.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>
2019-12-18 20:41:18 +00:00
Dylan Baker
69decdb28a docs: Add release notes, news, and update calendar for 19.2.8 2019-12-18 11:25:32 -08:00
Dylan Baker
7017f69a64 docs/relnotes/19.2.8: Add SHA256 sum 2019-12-18 11:24:46 -08:00
Dylan Baker
2f724d2202 docs: add relnotes for 19.2.8 2019-12-18 11:24:44 -08:00
Dylan Baker
d32e1257c0 docs: Add release notes, update calendar, and add news for 19.3.1 2019-12-18 10:58:54 -08:00
Dylan Baker
636175da6d dcos: add releanse notes for 19.3.1 2019-12-18 10:57:54 -08:00
Lionel Landwerlin
afdc0121b5 i965/iris/perf: factor out frequency register capture
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>
2019-12-18 14:23:17 +02:00
Jonathan Marek
072e95e07a freedreno/ir3: update prefetch input_offset when packing inlocs
If the input location changes then prefetch input_offset needs to change.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>
2019-12-17 16:41:13 -05:00
Eric Anholt
62998f6e2d ci: Fix caselist results archiving after parallel-deqp-runner rename.
Noticed while reviewing some lava parallel-deqp-runner changes.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3138>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3138>
2019-12-17 20:13:10 +00:00
Kristian H. Kristensen
9aaa23fbad freedreno/a6xx: Document the CP_SET_DRAW_STATE enable bits
There are bits for binning, gmem and sysmem.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>
2019-12-17 11:45:20 -08:00
Caio Marcelo de Oliveira Filho
c61ad77cd2 anv/gen12: Temporarily disable VK_KHR_buffer_device_address (and EXT)
For the sake of our testing infrastructure, disable this extension
for TGL until we can sort out a hang in Vulkan CTS.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-17 11:07:41 -08:00
Caio Marcelo de Oliveira Filho
766fdeccf9 intel/vec4: Fix lowering of multiplication by 16-bit constant
Existing code was ignoring whether the type of the immediate source
was signed or not.  If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).

Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for older
platforms that don't support MUL with 32x32 types and use vec4.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-17 10:45:22 -08:00
Caio Marcelo de Oliveira Filho
2137be22fa intel/fs: Fix lowering of dword multiplication by 16-bit constant
Existing code was ignoring whether the type of the immediate source
was signed or not.  If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).

Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for platforms
that don't support MUL with 32x32 types, including ICL and TGL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2186
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-17 10:45:22 -08:00
Alyssa Rosenzweig
66013cb1be pan/midgard: Set Z to shadow comparator for 2D
We still need to generalize for other types of (non-2D / array) shadow
samplers, but this is enough for sampler2DShadow to work with initial
dEQP tests passing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
1a53bed41c pan/midgard: Set .shadow for shadow samplers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
d183f84585 pan/midgard: Hoist temporary coordinate for cubemaps
We'll reuse some of this code for shadow samplers, which are represented
by a distinct source in NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
96df5f1fbf pan/midgard: Use a reg temporary for mutiple writes
Bug in texelfetch implementation from inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
bf5d8cfd28 panfrost: Handle empty shaders
I didn't realize this was in spec, but it fixes a crash in shaderdb.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
35418f6770 panfrost: Let precompile imply shaderdb
This cuts down the number of random environmental variables we need
flying around; now PAN_MESA_DEBUG=precompile is sufficient and
MIDGARD_MESA_DEBUG=shaderdb will be implied.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Alyssa Rosenzweig
271726eaca panfrost: Add PAN_MESA_DEBUG=precompile for shader-db
We would like to use run.c for shader-db runs (rather than capturing in
real-time, which is limiting).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
2019-12-17 17:42:57 +00:00
Lionel Landwerlin
2c8742ed85 mesa: avoid triggering assert in implementation
When tearing down a GL context with an active performance query, the
implementation can be confused by a query marked active when it's
being deleted.

This shouldn't happen in the implementation because the context will
already be idle.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2235
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>
2019-12-17 12:52:04 +00:00
Samuel Pitoiset
d399f4f414 radv/gfx10: fix ngg_get_ordered_id
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3133>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3133>
2019-12-17 12:34:18 +00:00
Neil Armstrong
089c8f0b8d ci: Remove T820 from CI temporarily
Our lab will have continuous programmed power cuts until the 6th January 2020,
so it's safer to disable the T820 CI running on the BayLibre kernelCI lab
to avoid breaking CI.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3135>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3135>
2019-12-17 11:40:07 +01:00
Tapani Pälli
75caae2268 i965: expose MESA_FORMAT_B8G8R8X8_SRGB visual
Patch adds BGRX sRGB visuals, required format translation information
to the __DRI_IMAGE_FOURCC_SXRGB8888 format and makes all BGRX visuals
sRGB capable just like is done with BGRA.

squashed patches from Yevhenii Kolesnikov:
  dri: Add __DRI_IMAGE_FOURCC_SXRGB8888 conversion
  i965: force visuals without alpha bits to use sRGB

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1501
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
2019-12-17 09:28:25 +00:00
Tapani Pälli
8b6b5ce669 dri: add __DRI_IMAGE_FORMAT_SXRGB8
Add format definition and required plumbing to create images.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
2019-12-17 09:28:25 +00:00
Gert Wollny
cffa7bb990 virgl: Increase the shader transfer buffer by doubling the size
With only linearly increasing the size of the shader transfer buffer
the transfer of very large shaders may fail, so with each attempt double
the size of the buffer.

CTS:
  dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.48
  for VTK-GL-CTS b5dcfb9c5 and newer

virglrenderer bug:
  https://gitlab.freedesktop.org/virgl/virglrenderer/issues/150

Fixes: a8987b88ff
    virgl: add driver for virtio-gpu 3D (v2)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>
2019-12-17 08:07:51 +00:00
Eric Anholt
2da68c8649 turnip: Fix support for immutable samplers.
We were setting up the hardware sampler state when updating a combined
image sampler, but never looking at the immutable sampler for in the
separate case.

Fixes failures in
dEQP-VK.binding_model.shader_access.primary_cmd_buf.sampler_immutable.fragment.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3127>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3127>
2019-12-16 19:51:27 -08:00
Jonathan Marek
edfc4daab8 turnip: don't set LRZ enable at end of renderpass
Fixes hanging with cases that use more than one renderpass.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3122>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3122>
2019-12-17 00:59:00 +00:00
Jonathan Marek
c7c5a84cf3 freedreno/ir3: lower pack/unpack ops
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>
2019-12-16 19:20:07 -05:00
Jonathan Marek
004797002f nir: add option to lower half packing opcodes
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>
2019-12-16 19:20:07 -05:00
Eric Anholt
2d3182b429 turnip: Add support for descriptor arrays.
I had a bigger rework I was working on, but this is simple and gets tests
passing.

Fixes 36 failures in
dEQP-VK.binding_model.shader_access.primary_cmd_buf.sampler_mutable.fragment.*
(now all passing)

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>
2019-12-16 23:57:22 +00:00
Eric Anholt
02d764b96a turnip: Drop unused variable.
We really need -Werror in CI.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>
2019-12-16 23:57:22 +00:00
Alyssa Rosenzweig
0eb84eb702 panfrost: Don't double-create scratchpad
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 4f7fddbd71 ("panfrost: Pass size to panfrost_batch_get_scratchpad")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>
2019-12-16 23:32:07 +00:00
Alyssa Rosenzweig
73bd9fe20c panfrost: Simplify sampler upload condition
Makes it more obvious what's going on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>
2019-12-16 23:32:06 +00:00
Icecream95
37bc028367 gallium/auxiliary: Handle count == 0 in u_vbuf_get_minmax_index_mapped
This makes u_vbuf_get_minmax_index_mapped return min = 0 / max = 0
when info->count == 0.

That should never happen anyway, but this commit makes it at least
return a sane value that callers expect, and also allows us - and
GCC - to assume count != 0 for optimization purposes.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>
2019-12-16 22:57:35 +00:00
Icecream95
80aca96803 gallium/auxiliary: Reduce conversions in u_vbuf_get_minmax_index_mapped
With this patch, GCC generates vectorized code that does the comparisons
without converting the indices to 32-bit first.

This optimization makes the aforementioned function almost twice as fast
for ARM NEON, and should speed up vectorised code on other platforms.

Without vectorisation, the function is still a percent or two faster,
but slightly larger.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>
2019-12-16 22:57:35 +00:00
Marek Olšák
69ea473eeb amd/addrlib: update to the latest version
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-16 17:04:57 -05:00
Jonathan Marek
a3ea4805aa turnip: remove duplicate A6XX_SP_CS_CONFIG_NIBO
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
2019-12-16 21:04:42 +00:00
Jonathan Marek
2d3492bc62 turnip: change emit_ibo to be like emit_textures
Adds missing alignment and error checking.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
2019-12-16 21:04:42 +00:00
Jonathan Marek
718bd4f8b4 turnip: fix emit_ibo
Based on the GL driver:
-Compute needs different opcode (this fixes a GPU hang problem)
-REG_A6XX_SP_IBO_LO/REG_A6XX_SP_CS_IBO_LO were swapped

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
2019-12-16 21:04:42 +00:00
Jonathan Marek
65007d438c turnip: remove compute emit_border_color
Current tu6_emit_border_color doesn't work for compute and there's no
example from the GL driver to base it on, so replace it with a finishme.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
2019-12-16 21:04:42 +00:00
Jonathan Marek
c9b12c71d7 turnip: fix emit_textures for compute shaders
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
2019-12-16 21:04:42 +00:00
Rafael Antognolli
ed43d01dec utils/os_socket: Define ssize_t on windows.
Fixes: ef5266ebd5 ("util/os_socket: Add socket related functions.")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-16 20:35:22 +00:00
Marek Olšák
43f05e0421 radeonsi/gfx10: fix ngg_get_ordered_id
This could have caused issues with NGG streamout.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
8edf3df3e4 radeonsi: reset more fields in si_llvm_context_set_ir to fix reusing ctx
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
1436c261e9 radeonsi: fix determining whether the VS prolog is needed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
378444ce90 radeonsi: allow generating VS prologs with 0 inputs
If "ls_vgpr_fix" is set, we use a prolog, but it can have 0 inputs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
4846aeaf57 radeonsi/gfx10: don't insert NGG streamout atomics if they are never used
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
de4a4595f6 radeonsi: don't wrap the VS prolog in if (ES thread) .. endif
We can execute it unconditionally and the values computed for disabled
threads won't be used anyway.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
db67e51903 radeonsi: set is_monolithic for VS prologs when the shader is really monolithic
This fixes a bug with NGG that is probably harmless.

Basically, !is_monolithic makes the VS prolog emit
llvm.amdgcn.init.exec.from.input, which sets the EXEC mask to only enable
ES threads. In the NGG non-GS case, the GS threads <= ES threads, so it was
never an issue.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
451bc91158 radeonsi: disallow compute-based culling if polygon mode is enabled
Polygon mode can generate thick points or lines.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
1a07df840e radeonsi: deduplicate ES and GS thread enablement code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
f90cbd18ff ac: fix the return value in cull_bbox when bbox culling is disabled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Marek Olšák
e5e3ffa6b9 ac: fix ac_get_i1_sgpr_mask for Wave32
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
2019-12-16 20:06:07 +00:00
Alyssa Rosenzweig
5386b7e011 panfrost: Remove asserts in panfrost_pack_work_groups_compute
It's a hot routine and these are exceedingly unlikely to break.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>
2019-12-16 19:48:28 +00:00
Alyssa Rosenzweig
6378797a6d panfrost: Pack invocation_shifts manually instead of a bit field
gcc generates exceptionally bad code for panfrost_pack_work_groups_fused
otherwise ... although that routine is somehow still hot ...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>
2019-12-16 19:48:28 +00:00
Iván Briano
a649bbffee anv: Export VK_KHR_buffer_device_address only when really supported
Fixes: 1b6991ba1d ("anv: Implement VK_KHR_buffer_device_address")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>
2019-12-16 19:24:46 +00:00
Iván Briano
0fd93b9589 anv: Export filter_minmax support only when it's really supported
Fixes: bea4d4c78c ("anv: add VK_EXT_sampler_filter_minmax support")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>
2019-12-16 19:24:46 +00:00
Jonathan Marek
b936143327 freedreno/ir3: lower mul_2x32_64
lower_mul_2x32_64 generates mul_high opcodes, and lower_mul_high is done by
nir_lower_alu, so call nir_lower_alu after nir_opt_algebraic.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-16 13:37:09 -05:00
Jonathan Marek
d4676d7a16 turnip: implement CmdFillBuffer/CmdUpdateBuffer
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-16 13:13:53 -05:00
Jonathan Marek
8d893a2071 turnip: don't require src image to be set for clear blits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-16 13:13:53 -05:00
Jonathan Marek
f78c4251f1 turnip: use common blit path for buffer copy
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-16 13:13:53 -05:00
Jonathan Marek
d6c8aa2b72 turnip: use single substream cs
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-16 13:13:53 -05:00
Alyssa Rosenzweig
8959364937 panfrost: Remove fbd_type enum
Just use the MALI_MFBD tag directly; it's clean.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
2019-12-16 12:51:03 -05:00
Alyssa Rosenzweig
5408700a12 ci: Reinstate Panfrost CI
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
2019-12-16 12:51:03 -05:00
Alyssa Rosenzweig
caf55e7bfd panfrost: Fix FBD issue
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: b0e915b4e6 ("panfrost: Emit SFBD/MFBD after a batch, instead of before")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
2019-12-16 12:50:26 -05:00
Lionel Landwerlin
bc36160ccb vulkan/wsi: error out when image fence doesn't signal
If for some reason the fence associated with an image doesn't signal,
we're likely in a device lost scenario, we should report that error.

We can't really wait for a given amount of time because we could get a
timeout and that is not a valid error to report for vkQueuePresentKHR,
so just wait forever.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/830
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-12-16 14:59:10 +02:00
Lionel Landwerlin
c056193288 anv: drop unused parameter from apply layout pass
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-16 14:35:25 +02:00
Lionel Landwerlin
7c223cf316 anv: constify pipeline layout in nir passes
Was hoping to find potential issues but nothing. Still probably a good
idea.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-16 14:35:22 +02:00
Alyssa Rosenzweig
e7721d8775 pan/midgard: Set r1.w magic
I'm honestly unsure what this is for, but it's needed on MFBD systems
for unknown reasons, at least when MRT is actually in use and then
sometimes without MRT (it fixes a blend shader issue on T760?)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
2019-12-16 09:10:33 +00:00
Alyssa Rosenzweig
3448b2641a pan/midgard: Fix liveness analysis with multiple epilogues
Epilogues are special fixed-function blocks, so they need special
handling for liveness analysis to work completely. This in turns fixes
RA issues for many shaders using MRT.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
2019-12-16 09:10:33 +00:00
Alyssa Rosenzweig
60396340f5 pan/midgard: Writeout per render target
The flow is considerably more complicated. Instead of one writeout loop
like usual, we have a separate write loop for each render target. This
requires some scheduling shenanigans to get right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
2019-12-16 09:10:33 +00:00
Alyssa Rosenzweig
281cc6f9a6 pan/midgard: Add schedule barrier after fragment writeout
This is a branch, like discard, so we need a barrier to make it safe.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
2019-12-16 09:10:33 +00:00
Alyssa Rosenzweig
a2d5503b68 panfrost: Pass blend RT number through
We have to key the blend shader for the render target number due to
writeout silliness.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>
2019-12-16 09:10:33 +00:00
Pierre-Eric Pelloux-Prayer
2c1983aefe gallium: refuse to create buffers larger than UINT32_MAX
pipe_resource.width0 is 32 bits and hardware support for bigger buffer is
limited (eg: AMD hardware doesn't support buffer shader resources bigger
than 4GB).

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2053
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2948>
2019-12-16 09:30:14 +01:00
Pierre-Eric Pelloux-Prayer
0e286f6cbf radeonsi: disable dcc for 2x MSAA surface and bpe < 4
This fixes a series of dEQP tests on Raven platforms:
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgba4
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb5_a1
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb565
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rg8
  - dEQP-GLES3.functional.fbo.msaa.2_samples.r16f

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>
2019-12-16 08:08:08 +00:00
Iago Toral Quiroga
4202cf8bf1 v3d: expose OES_geometry_shader
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
ba7bc83dd5 v3d: support precompiling geometry shaders
At present, this is only relevant for shader-db.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
7cee56b1df v3d: disable lowering of indirect inputs
V3D can do indirect inputs so we don't need it. Also, the lowering
produces horrible if-ladder code that is particularly bad for geometry
shaders where inputs are always arrays and shader bodies usually have
a loop indexing into them.

This fixes a couple of geometry shader tests in CTS that would fail to
register allocate otherwise.

There are no changes in shader-db.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
a1b7c0844d v3d: fix primitive queries for geometry shaders
With geometry shaders the number of emitted primitived is decided
at run time, so we cannot precompute it in the CPU and we need to
use the PRIMITIVE_COUNTS_FEEDBACK commands to have the GPU provide
the number like we do for the number of primitives written to
transform feedback. This may have a performance impact though, since
it requires a sync wait for the draw to complete, so we only do
it when geometry shaders are present.

v2: remove '> 0' comparison for ponter type (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
6c7a2b69f8 v3d: handle writes to gl_Layer from geometry shaders
When geometry shaders write a value to gl_Layer that doesn't correspond to
an existing layer in the target framebuffer the rendering behavior is
undefined according to the spec, however, there are CTS tests that trigger
this scenario on purpose, probably to ensure that nothing terrible happens.

For V3D, this situation is problematic because the binner uses the layer
index to select the offset to write into the tile state data, and we only
allocate tile state for MAX2(num_layers, 1), so we want to make sure we
don't produce values that would lead to out of bounds writes. The simulator
has an assert to catch this, although we haven't observed issues in actual
hardware it is probably best to play safe.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
45bc61add0 v3d: move layer rendering to a separate helper
This helps with reducing nesting level after adding the loop
to handle layered rendering.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
74a59fdc6e v3d: support rendering to multi-layered framebuffers
When doing layered rendering the binning stage will prepare per-tile
lists for each layer in the framebuffer, so we need to make sure
we allocate enough space for them .

We also need to emit the NUMBER_OF_LAYERS packet. This is required
even when the number of layers is only 1, otherwise the simulator
detects buffer overflows in the tile_state BO during some CTS test
cases involving layered FBOs.

When rendering, we need to emit commands for each layer of the
framebuffer separately and make sure we address the correct layers for
each one.

v2: fixed typo in comment (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
a0c94c70ee v3d: do not limit new CL space allocations with branch to 4096 bytes
For layered rendering we need to emit per layer rendering commands
lists so we we can end up requiring a fairly large buffer for this
if the number of layers is large enough.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
56ba6f42e2 v3d: remove obsolete assertion
OES_geometry_shader introduced the concept of layered framebuffers.
Removing this assertion gets a bunch of CTS tests to pass. We will
also need layered images to implement layered rendering with geometry
shaders.

v2: fix typo in commit message (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
e054fe0167 v3d: support transform feedback with geometry shaders
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
e54cf64939 v3d: save geometry shader state for blitting
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
a6b318ef52 v3d: predicate geometry shader outputs inside non-uniform control flow
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
b636d4ebc7 v3d: don't try to render if shaders failed to compile
This is the same we do in the compute path to avoid crashes
at draw time.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
e2f2263433 v3d: add support for adjacency primitives
v2: remove obsolete comment (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
a07d70c54b v3d: we always have at least one output segment
If we program an output size of 0 the simulator asserts. This was
not a problem until now because our VS would always have to
emit fixed function outputs, however, now that it can be paired
with a GS we can end up with a VS shader that no longer emits
any outputs.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
76fc8c8bb1 v3d: compute appropriate VPM memory configuration for geometry shader workloads
Geometry shaders can output many vertices and thus have higher VPM memory
pressure as a result. It is possible that too wide geometry shader dispatches
exceed the maximum available VPM output allocated, in which case we need
to reduce the dispatch width until we can fit the VPM memory requirements.
Supported dispatch widths for geometry shaders are 16, 8, 4, 1.

There is a limit in the number of VPM output sectors that can be used by a
geometry shader that we can meet by lowering the dispatch width at compile
time, however, at draw time we need to revisit this number and, together with
other elements that can contribute to total VPM memory requirements, decide
on a configuration that can fit the program into the available VPM memory.
Ideally, we also want to aim for not using more than half of the available
memory so we that we can run a pair of bin and render programs in parallel.

v2: fixed language in comment and typo in commit log. (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
76f4c83815 v3d: add 1-way SIMD packing definition
According to the documentation, the 1-way dispatch width is only supported
with geometry shaders.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
4f5fbd6490 v3d: implement geometry shader instancing
v2:
 - Remove unused field uses_iid from v3d_gs_prog_data (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
8a81ac2eed v3d: emit geometry shader state commands
This is good enough to get basic GS workloads working, later patches will
improve this by adding instancing support, proper SIMD configuration, etc.

Notice that most of the TESSELLATION_GEOMETRY_SHADER_PARAMS fields are only
relevant when tessellation shaders are present. We do not support tessellation
yet, but we still need to fill in these tessellation state with default values
since our packing functions require some of these to have non-zero values.

v2:
 - Add a comment in the code explaining why we fill in
   tessellation fields (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
0934bd4460 v3d: fix packet descriptions for geometry and tessellation shaders
Every code address starts at bit 3 (addresses must be 64-bit aligned),
with the first 3 bits used to specify threading and NaN propagation
parameters for the shader program.

We generally skip "reserved" bits, however, doing this when the
reserved field is the last in a struct and it is large enough can
make us compute incorrect (smaller) struct sizes which can
lead to corrupt CLs. In particular, the "Tess/Geom Common Params"
struct has a reserved field at the end that is 8-bit, so if we
don't include this we compute a packet size that is 1 byte smaller
than it shold, making the next packet we emit start 1 byte
earlier and therefore leading to incorrect CL data from that point
forward.

The name of one of the fields was not correct.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
5d578c27ce v3d: add initial compiler plumbing for geometry shaders
Most of the relevant work happens in the v3d_nir_lower_io. Since
geometry shaders can write any number of output vertices, this pass
injects a few variables into the shader code to keep track of things
like the number of vertices emitted or the offsets into the VPM
of the current vertex output, etc. This is also where we handle
EmitVertex() and EmitPrimitive() intrinsics.

The geometry shader VPM output layout has a specific structure
with a 32-bit general header, then another 32-bit header slot for
each output vertex, and finally the actual vertex data.

When vertex shaders are paired with geometry shaders we also need
to consider the following:
  - Only geometry shaders emit fixed function outputs.
  - The coordinate shader used for the vertex stage during binning must
    not drop varyings other than those used by transform feedback, since
    these may be read by the binning GS.

v2:
 - Use MAX3 instead of a chain of MAX2 (Alejandro).
 - Make all loop variables unsigned in ntq_setup_gs_inputs (Alejandro)
 - Update comment in IO owering so it includes the GS stage (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
f63750accf v3d: remove unused variable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
52cbef0039 v3d: enable debug options for geometry shader dumps
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
d6b0786a38 v3d: add debug assert
While lowering vpm outputs we look for the NIR variables matching
particular store output instructions and we expect to find a match,
so assert on that.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Iago Toral Quiroga
6e68f74395 v3d: add missing plumbing for VPM load instructions
We will need to use LDVPMG_IN specifically to read VPM inputs
in geometry shaders.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-16 08:42:37 +01:00
Eric Anholt
f58ef5d481 turnip: Lower usub_borrow.
Fixes dEQP-VK.glsl.builtin.function.integer.usubborrow.uvec2_mediump_fragment.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2986>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2986>
2019-12-16 04:52:09 +00:00
Caio Marcelo de Oliveira Filho
c06ba83589 intel/fs: Lower 64-bit MOVs after lower_load_payload()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3070>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3070>
2019-12-14 21:12:21 +00:00
Bas Nieuwenhuizen
b53856aca3 amd/common: Always use addrlib for HTILE tc-compat.
Even without depth+stencil addrlib can (correctly!) decide to
disable tc compatible HTILE.

One example is 8x sampling with 32-bit depth on Stoney. The row size
on Stoney is 1024, while the tile size is 2048, which results in
tile splits which are not supported with tc-compat.

On Stoney, this fixes
dEQP-VK.glsl.builtin_var.fragdepth.*_list_d32_sfloat_multisample_8

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
2019-12-14 20:39:29 +00:00
Bas Nieuwenhuizen
e197fb1c2f amd/common: Fix tcCompatible degradation on Stoney.
addrlib sometimes returns smaller sizes for tcCompat as it does
not seem to take into account the depth+stencil matching config
gymnastics with tcCompat.

This fixes
dEQP-VK.pipeline.render_to_image.core.2d_array.huge.height.r8g8b8a8_unorm_d32_sfloat_s8_uint

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
2019-12-14 20:39:29 +00:00
Denis Pauk
6bf14e9c47 docs/features: mark GL_ARB_texture_compression_bptc as done for llvmpipe, softpipe, swr
Signed-off-by: Denis Pauk <pauk.denis@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: Marek Olšák <maraeo@gmail.com>
CC: Rhys Perry <pendingchaos02@gmail.com>
CC: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Matt Turner <mattst88@gmail.com>
2019-12-14 20:02:10 +00:00
Denis Pauk
3acc15f4f0 gallium/swr: Enable support bptc format.
Reuse Code from:
f69bc797e1 gallium/auxiliary: Add helper support for bptc format compress/decompress

Signed-off-by: Denis Pauk <pauk.denis@gmail.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: Marek Olšák <maraeo@gmail.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
2019-12-14 20:02:10 +00:00
Rob Clark
1bf3837395 freedreno/a6xx: fix OUT_REG() vs growable cmdstream
BEGIN_RING() could decide we can't fit the next packet in the current
cmdstream segment, and grow a new segment.  So we need to grab ring->cur
*after* BEGIN_RING(), otherwise we are writing cmdstream past the end of
the previous segment.

Fixes: bdd98b892f ("freedreno: New struct packing macros")
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-14 09:12:39 -08:00
Erico Nunes
ce52b49348 lima: split draw calls on 64k vertices
The Mali400 only supports draws with up to 64k vertices per command.
To handle this, break the draw_vbo call into multiple commands.
Indexed drawing is left to a separate code path.
This implementation was ported from vc4_draw_vbo.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
2019-12-14 07:44:43 +01:00
Erico Nunes
6d46d0e82b vc4: move the draw splitting routine to shared code
This can also be useful for other hardware which has similar limitations
on vertex count per single draw.
The Mali400 has a similar limitation and can reuse this.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
2019-12-14 07:44:43 +01:00
Erico Nunes
2d7be5f01f lima: refactor indexed draw indices upload
As of this commit this is just a refactor in preparation to enable
support for more than 64k vertices.
To support splitting the draw_vbo call, indices shouldn't be re-uploaded
every time.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
2019-12-14 07:44:43 +01:00
Erico Nunes
270c282a43 lima: allocate separate bo to store varyings
The current strategy using the suballocator with fixed size doesn't
scale and causes some programs with large number of vertices (like some
glmark2 scenes) to crash.
Change it to dynamically allocate a separate bo to accomodate for
arbitrary number of vertices.
This also fixes the buffer read/write flags for gp.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
2019-12-14 07:44:43 +01:00
Erico Nunes
8bf2b5db78 gallium/util: add alignment parameter to util_upload_index_buffer
At least on Mali Utgard, index buffers need to be aligned on 0x40.
To avoid duplicating this, add an alignment parameter.
Keep the previous default for the other existing users.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2445>
2019-12-14 07:44:43 +01:00
Kenneth Graunke
9fb45c5bbd drirc: Final Fantasy VIII: Remastered needs allow_higher_compat_version
This gets it running on i965 with Mesa master.  (The game won't start
without GL 3.3 compatibility, but uses 1.20 with GL_EXT_gpu_shader4
for shaders.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3076>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3076>
2019-12-13 17:58:42 -08:00
Timothy Arceri
7564c5fc6d st/glsl_to_nir: fix SSO validation regression
Fixes: b77907edb554 ("st/glsl_to_nir: use nir based program resource list builder")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2216

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-13 23:09:57 +00:00
Alyssa Rosenzweig
46f0b9ecc5 ci: Remove T760/T860 from CI temporarily
I feel really bad about this but this one test is flaking. I don't want
to do a mass revert (and bisection is extremely difficult with
nondeterministic/Heisenbugs), but it's Friday night and master needs to
pass. This commit should be reverted asap (once the flake is solved)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 22:52:39 +00:00
Rafael Antognolli
59de5d9b6a iris: Implement WA for push constants.
v2: Apply WA to gen11+ instead of gen12+ (Jordan).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-12-13 14:15:04 -08:00
Andreas Baierl
8adeeaa7f2 lima/parser: Add texture descriptor parser
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2980>
2019-12-13 22:02:03 +00:00
Andreas Baierl
5456916309 lima/parser: Add RSW parsing
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2980>
2019-12-13 22:02:03 +00:00
Andreas Baierl
31ed081ca3 lima/parser: Some fixes and cleanups
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2980>
2019-12-13 22:02:03 +00:00
Rafael Antognolli
6a3b8811ea vulkan/overlay: Update docs.
Add mention to overlay control socket.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Rafael Antognolli
56ccea58ae vulkan/overlay: Add basic overlay control script.
This can be used to start/stop statistics capturing from the command
line.

v3:
 - Install script (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Rafael Antognolli
a94fa1da93 vulkan/overlay: Add a command to start capturing data to a file.
By default, if an output_file is specified, the overlay layer will start
capturing data immediately. After this commit, when a control socket is
used, the capture starts disabled by default, and is only enabled when a
command ":capture=1;" is received.

when the capture is enabled, we might have already accumulated some
stats. To avoid capturing such noise, we discard and reset the fps and
stats, updating the display and capturing only data from that point on.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Rafael Antognolli
606dff1b73 vulkan/overlay: Add support for a control socket.
Add support for socket from which the overlay layer can receive
commands. This control socket can be useful to allow setting options
once the application is already running. For instance, triggering the
capture of fps data at a certain point.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Rafael Antognolli
e87d7fea8a vulkan/overlay: Add a control socket.
v2: Use a socket instead of named pipe.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Rafael Antognolli
ef5266ebd5 util/os_socket: Add socket related functions.
v3:
 - Add os_socket.c/h into Makefile.sources (Lionel)
 - Add empty non-linux implementation to public functions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-13 20:53:44 +00:00
Eric Engestrom
c327245257 anv: drop unused #include
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-13 20:42:40 +00:00
Eric Engestrom
1a837e803b util/simple_mtx: don't set the canary when it can't be checked
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-13 20:20:21 +00:00
Eric Engestrom
d600b19640 intel/compiler: replace 0 pointer with NULL
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-13 20:16:20 +00:00
Eric Engestrom
8074f68b3b intel/compiler: add ASSERTED annotation to avoid "unused variable" warning
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-13 20:16:20 +00:00
Kenneth Graunke
91efae4f80 iris: Alphabetize source files after iris_perf.c was added 2019-12-13 11:03:13 -08:00
Rob Clark
3b8feefd9c freedreno/ir3: add iterator macros
So many open coded list iterators were getting annoying.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-13 09:25:40 -08:00
Rob Clark
ad92aa36ac freedreno/ir3: add scheduler traces
Add some infrastructure to trace scheduler decisions.  The next patch
will add some more traces, just splitting this out to reduce clutter.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-13 09:25:40 -08:00
Rob Clark
dd34ccb2c5 freedreno/ir3: add last-baryf shaderdb stat
Sometimes sched changes that are a win in terms of instruction count
and/or register pressure, are worse in real life, due to keeping varying
storage locked for too long.  Add a shader-db stat to give this more
visibility.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-13 09:25:40 -08:00
Alejandro Piñeiro
2865d79a33 nir/opt_peephole_select: remove unused variables
To avoid "unused variable" warnings.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-12-13 17:14:58 +01:00
Alyssa Rosenzweig
7c972eba40 panfrost: Report GPU name in es2_info
We can prettify the ID.

Closes #2093

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
09a2c74cfd panfrost: Add panfrost_model_name helper
This gives us a string representation of a GPU ID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
a215289176 panfrost: Move property queries to _encoder
We'll want these in non-Gallium devices.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
102789886c panfrost: Move nir_undef_to_zero to Midgard compiler
Nothing Gallium about it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
ddbbb2db48 pandecode: Add cast
Fixes minor coverity warning about the format specifier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
4f7fddbd71 panfrost: Pass size to panfrost_batch_get_scratchpad
We'll compute the size with the new scratchpad helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
bc887e8281 panfrost: Calculate maximum stack_size per batch
We'll need this so we can allocate a stack for the batch large enough
for all the jobs within it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
a337bf319c pan/midgard: Handle misc. cppcheck warnings
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
f204791cd6 pan/midgard: Remove unused ld/st packing hepers
Identified by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
709d8c29cd panfrost: Handle minor cppcheck issues
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
b0e915b4e6 panfrost: Emit SFBD/MFBD after a batch, instead of before
The size of the scratchpad (as well as some tiler details) depend on the
contents of the batch, so we need to wait to defer filling out the FBD
until after all draws are queued.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Alyssa Rosenzweig
7597015b85 panfrost: Route stack_size from compiler
We'll need it in pan_context.c

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 10:26:35 -05:00
Jonathan Marek
440cd835de etnaviv: add missing vs_needs_z_div handling to NIR backend
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:31:40 -05:00
Jonathan Marek
64c7cdcae5 etnaviv: add missing formats
Add missing texture/render formats supported by hardware.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:10:29 -05:00
Jonathan Marek
d30499a3c8 etnaviv: remove swizzle from format table
The only format that needs swizzle is R8 emulated with L8, so we can get
rid of the SWIZ(X, Y, Z, W) everywhere.

Note: R8G8 also had a swizzle, but it wasn't necessary.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:10:28 -05:00
Jonathan Marek
017cbab5b0 etnaviv: disable integer vertex formats on pre-HALTI2 hardware
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:10:28 -05:00
Jonathan Marek
d34705c891 etnaviv: update INT_FILTER choice for GLES3 formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:09:08 -05:00
Jonathan Marek
15e9704ccb etnaviv: set output mode and saturate bits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:09:08 -05:00
Jonathan Marek
b7730c54a9 etnaviv: sRGB render target support
Note: no srgb render target support before HALTI3

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:09:08 -05:00
Jonathan Marek
39349e629a etnaviv: remove sRGB formats from format table
This supports all sRGB formats, without having them in the format table.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 09:09:08 -05:00
Tomasz Pyra
b62217780a gallium/swr: Fix arb_transform_feedback2
Added support for pause/resume transform feedback.
Fixed DrawTransformFeedback.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
2019-12-13 10:58:36 +00:00
Samuel Pitoiset
b37c91c12e radv: handle unaligned vertex fetches on GFX6/GFX10
The Vulkan spec doesn't have any words for vertex attributes alignment.

Fixes a test failure on GFX6 and a GPU hang on GFX10 with:
dEQP-VK.spirv_assembly.instruction.spirv1p4.entrypoint.tess_con_pc_entry_point

vkpipeline-db results on GFX10:
Totals from affected shaders:
SGPRS: 463772 -> 472972 (1.98 %)
VGPRS: 343208 -> 343752 (0.16 %)
Spilled SGPRs: 323 -> 336 (4.02 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 13806200 -> 14164472 (2.60 %) bytes
Max Waves: 84021 -> 83755 (-0.32 %)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2161
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-13 09:54:07 +00:00
Lionel Landwerlin
bd888bc1d6 i965/iris: perf-queries: don't invalidate/flush 3d pipeline
Our current implementation of performance queries is fairly harsh
because it completely flushes and invalidates the 3d pipeline caches
at the beginning and end of each query. An argument can be made that
this is how performance should be measured but it probably doesn't
reflect what the application is actually doing and the actual cost of
draw calls.

A more appropriate approach is to just stall the pipeline at
scoreboard, so that we measure the effect of a draw call without
having the pipeline in a completely pristine state for every draw
call.

v2: Use end of pipe PIPE_CONTROL instruction for Iris (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-13 11:27:22 +02:00
Lionel Landwerlin
a575b3cd5c intel/perf: drop batchbuffer flushing at query begin
This was initially intended to fix issues with the query timings going
occassionally high.

It turns out there was a bug in the attribution of OA reports to our
context when parsing the OA data. This led to reports flagged with
other context IDs to be included in our queries results.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-13 11:27:17 +02:00
Iago Toral Quiroga
ca475d5fba v3d: actually root the first BO in a command list in the job
We were passing cl->bo, which is NULL, so v3d_job_add_bo was a no-op.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-13 08:58:10 +00:00
Christian Gmeiner
06db271a6c etnaviv: drop compiled_rs_state forward declaration
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 08:11:03 +00:00
Christian Gmeiner
5f7c5f5dd2 etnaviv: remove not used etna_bits_ones(..)
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-12-13 08:11:03 +00:00
Vinson Lee
8d20b5cba5 swr: Fix build with llvm-10.0.
Fix build error after llvm-10.0 commit ("1b2842bf902a [Alignment][NFC]
CreateMemSet use MaybeAlign").

../src/gallium/drivers/swr/swr_shader.cpp: In member function ‘void (* BuilderSWR::CompileGS(swr_context*, swr_jit_gs_key&))(HANDLE, HANDLE, SWR_GS_CONTEXT*)’:
../src/gallium/drivers/swr/swr_shader.cpp:738:65: error: no matching function for call to ‘BuilderSWR::MEMSET(llvm::Value*&, llvm::Constant*, int, long unsigned int)’
       MEMSET(pStream, C((char)0), VERTEX_COUNT_SIZE + CONTROL_HEADER_SIZE, sizeof(float) * KNOB_SIMD_WIDTH);
                                                                 ^
In file included from ../src/gallium/drivers/swr/rasterizer/jitter/builder.h:163:0,
                 from ../src/gallium/drivers/swr/swr_shader.cpp:43:
src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:51:11: note: candidate: llvm::CallInst* SwrJit::Builder::MEMSET(llvm::Value*, llvm::Value*, uint64_t, llvm::MaybeAlign, bool, llvm::MDNode*, llvm::MDNode*, llvm::MDNode*)
 CallInst* MEMSET(Value *Ptr, Value *Val, uint64_t Size, MaybeAlign Align, bool isVolatile = false, MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr)
           ^
src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:51:11: note:   no known conversion for argument 4 from ‘long unsigned int’ to ‘llvm::MaybeAlign’
In file included from ../src/gallium/drivers/swr/rasterizer/jitter/builder.h:163:0,
                 from ../src/gallium/drivers/swr/swr_shader.cpp:43:
src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:56:11: note: candidate: llvm::CallInst* SwrJit::Builder::MEMSET(llvm::Value*, llvm::Value*, llvm::Value*, llvm::MaybeAlign, bool, llvm::MDNode*, llvm::MDNode*, llvm::MDNode*)
 CallInst* MEMSET(Value *Ptr, Value *Val, Value *Size, MaybeAlign Align, bool isVolatile = false, MDNode *TBAATag = nullptr, MDNode *ScopeTag = nullptr, MDNode *NoAliasTag = nullptr)
           ^
src/gallium/drivers/swr/rasterizer/jitter/gen_builder.hpp:56:11: note:   no known conversion for argument 4 from ‘long unsigned int’ to ‘llvm::MaybeAlign’

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-12-12 23:43:38 -08:00
Jonathan Marek
828f8f5531 turnip: implement subpass input attachments
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
3b4b5f549f turnip: CmdClearAttachments fixes
Partial depth/stencil clear and skipping unused attachments.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
aac7d6c1dc turnip: subpass rework
A renderpass is a tile load/store cycle.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
4322cf34c4 turnip: add dirty bit for push constants
Fixes push constants not updating in some cases.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
27d2174508 turnip: no 8x msaa on 128bpp formats
We don't have an entry for cpp 128 in the tile_alignment table, but I don't
think the HW supports this at all (blob driver just doesn't have 8x msaa).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
5fd9fd3516 turnip: fix VK_IMAGE_ASPECT_STENCIL_BIT image view
Use a special format which allows sampling the stencil and set the correct
swizzle.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
e71f79f6c6 turnip: set FRAG_WRITES_SAMPMASK bit
GPU hangs if SAMPMASK_REGID is used without this bit.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
99a4f7c79f turnip: set load_layer_id to zero
We don't have layered rendering and ir3 doesn't support this intrinsic, so
just set it to zero for now.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
7bbcf7deff turnip: update tile_align_w/tile_align_h
It looks like the actual tile alignment requirement is less than 32x32, but
in some cases input attachment texture needs 64 alignment.

Reduced the h alignment to 16 to compensate and it seems to work fine.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
402bc111fc turnip: fix tile layout logic
Use DIV_ROUND_UP and stop trying to increase the tile_count width/height
once tile_align_w/tile_align_h are reached.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
14cbe2dea5 turnip: fix hw binning render area
Fix a mistake in the y2 coordinate.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
029322c100 freedreno/registers: add a6xx texture format for stencil sampler
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
2db03867f6 freedreno/ir3: add GLSL_SAMPLER_DIM_SUBPASS to tex_info
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:17 -05:00
Jonathan Marek
ab54aceaa8 turnip: fix incorrectly failing assert
pColorBlendState is allowed to be NULL if subpass has >0 color attachments
but they are all unused.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-12 20:33:16 -05:00
Alyssa Rosenzweig
07d8b98b54 panfrost: Query core count and thread tls alloc
This is supported only on newer kernels.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 00:47:23 +00:00
Alyssa Rosenzweig
315324614e panfrost: Factor out panfrost_query_raw
We would like to query properties other than product ID.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-13 00:47:23 +00:00
Timothy Arceri
a6aedc662e st/glsl_to_nir: use nir based program resource list builder
Here we use the NIR based builder to add everything to the resource
list execpt for SSO packed varyings. Since the details of those
varyings get lost during packing we leave the special handing to
the GLSL IR pass for now. In order to do this we add some bools
to the build resource list functions.

Using the NIR based resource list builder gets us a step closer to
using a native NIR based linker. It should also be faster than the
GLSL IR builder, one because the NIR optimisations should mean we
add less entries due to better optimisations, and two because nir
gives us better lists to work with and we don't need to walk the
entire IR to find the resources.

Ack-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
144f54e483 st/glsl_to_nir: call gl_nir_lower_buffers() a little later
In a following commit we will use a NIR based builder to build the
OpenGL resource list, so we want to delay this call a little.

Ack-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
d0259f4159 glsl: add subroutine support to nir_build_program_resource_list()
This is required so we can use the NIR linker to link GLSL in
addition to spirv.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
46f9f74c57 glsl: add support for named varyings in nir_build_program_resource_list()
This adds support for adding names of varying to the resource list
which is required for us to use this function with the glsl linker.
Support for names is optional for spirv which is why it had not been
added yet.

This is mostly a copy of the GLSL IR code adapted to nir.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
3c364f90fd glsl: copy the new data fields when converting to nir
These fields added in the previous commit will be used to make use
of a NIR based GLSL linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
56c25b938c nir: add some fields to nir_variable_data
These will be used to provide NIR linking functionality to GLSL.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
89b2b0f767 glsl: copy the how_declared field when converting to nir
This is needed to make use of nir_build_program_resource_list().

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Timothy Arceri
c3823d2d29 glsl: move nir_remap_dual_slot_attributes() call out of glsl_to_nir()
In order to be able to implement a NIR based glsl linker we need to
build the program resource list with NIR. This change delays the
remaping so that a later commit can call the NIR based resource
list builder.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-13 00:07:19 +00:00
Dylan Baker
e37115c912 docs: Update release notes, index, and calendar for 19.3.0 2019-12-12 12:05:00 -08:00
Dylan Baker
941aa31572 docs/19.3.0: Add SHA256 sums 2019-12-12 11:57:54 -08:00
Dylan Baker
2ab4c2bc22 docs: add release notes for 19.3.0 2019-12-12 11:57:53 -08:00
Jason Ekstrand
fa4d981f6f i965: Enable GL_EXT_gpu_shader4 on Gen6+
It's already enabled for all gallium drivers that support GLSL 1.40 or
above and we already support everything in our compiler on SNB+

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-12-12 18:43:17 +00:00
Samuel Pitoiset
eda1b77cc2 radv: enable SpvCapabilityImageMSArray
The Vulkan spec says that StorageImageMultisample and ImageMSArray
SPIRV-V capabilities must be enabled if the
shaderStorageImageMultisample feature is supported.

This fixes a warning with RenderDoc.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2212
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-12 18:52:08 +01:00
Alyssa Rosenzweig
eac9247b2d panfrost: Add routines to calculate stack size/shift
These implement the aforementioned formulas.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
e6f8ef93ca panfrost: Split stack_shift nibble from unk0
It's conceptually independent from the upper part (which is not yet
understood, but for spilling generally remains equal to 0x1e).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
6c6372770c panfrost: Rename unknown_address_0 -> scratchpad
It's the analogue pointer in SFBD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
8b290bb13d panfrost: Describe thread local storage sizing rules
Deeply nested powers-of-two, basically :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
2b4da476f4 pan/midgard: Fix shift for TLS access
Due to this issue we were using 4x the memory we should have for TLS,
which was messing up the size calculations. Oops!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
05b839f354 pan/midgard: Simplify and fix vector copyprop
Fixes a regression in QuakeSpasm. See
https://gitlab.freedesktop.org/mesa/mesa/issues/2169 for apitrace.

Closes #2169

Fixes: f72873e6aa ("pan/midgard: Copypropagate vector creation")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Icecream95
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
4308d75281 pan/midgard: Don't try to free NULL in LCRA
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 12e393bacf ("panfrost: add lcra_free() to free lcra state")
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
5e75eb547f pan/midgard: Force alignment for csel_v
The swizzle on the conditional gets lost.

Fixes "horizontal mirroring" in godot. See
https://gitlab.freedesktop.org/mesa/mesa/issues/2108 which has attached
apitrace.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: d3b3daa9d3 ("pan/midgard: Use new scheduler")
Reported-by: Icecream95
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
8c79467a0d pan/midgard: Don't use no_spill for memory spill src
I'm not totally sure why this would *break* things, but it's certainly
not necessary and it does break things. Somehow this gives the RA more
freedom, fixing some spill issues.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
d48c195acf pan/midgard: Use no_spill bitmask
We would like no_spill decisions to be class-specific -- spilling from
special register to a work register doesn't preclude also spilling that
work register to stack.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
08b16fb321 pan/midgard: Dynamically allocate r26/27 for spills
This allows us to spill two 128-bit values in the same bundle, since we
have two registers we can spill with. This improves the
register allocation flexibility in programs with heavy spilling, though
unfortunately it isn't sufficient (theoretically, 3.5 128-bit values can
be spilled from 3 vector units and 2 scalar units).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:07 -05:00
Alyssa Rosenzweig
8e7f2b9ae3 pan/midgard: Remove code marked "TODO: remove me"
It's a fossil, how cute :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
b6d1b32d58 pan/midgard: Remove consecutive_skip code
This has been unused since the beginning since it's broken. Let's toss
it so it doesn't get in the way of further fixes. Bigger to fish to fry.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
3c0f1ea58c pan/midgard: Move bounds checking into LCRA
This simplifies the cost calculation code a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
e985ae25a6 pan/midgard: Remove spill cost heuristic
We do need some sort of a cost heuristic, but this one is just causing
spilling to behave worse on shaders I'm looking at, and I don't need
more noise in the spill implementation right now.

Get it working first. We can optimize this later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
cacb4bc022 pan/midgard: Simplify spillability test
Let's not worry about spilling twice in a bundle; that's too
restrictive. We'll need to change the schedule itself -- unfortunately,
this can have second-order effects due to pipeline registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
7cf5bee5aa pan/midgard: Split spill node selection/spilling
Instead of having a giant function for both, split into the two
subtasks so we can handle errors better.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Alyssa Rosenzweig
9dc3b18e49 pan/midgard: Move spilling code out of scheduler
We move it to the register allocator itself. It doesn't belong in
midgard_schedule.c!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 11:42:06 -05:00
Tomeu Vizoso
88f9522f83 st/mesa: Don't access members of NULL pointers
Should be harmless, but UBSAN complains about it and fills the logs with
noise.

../src/mesa/state_tracker/st_manager.c:523:27: runtime error: member access within null pointer of type 'struct st_framebuffer'"}
    #0 0xaad4e89c in st_framebuffer_reference ../src/mesa/state_tracker/st_manager.c:523"}
    #1 0xaad4e89c in st_api_make_current ../src/mesa/state_tracker/st_manager.c:1091"}
    #2 0xaab69e0e in dri_make_current ../src/gallium/state_trackers/dri/dri_context.c:301"}
    #3 0xaab48fd2 in driBindContext ../src/mesa/drivers/dri/common/dri_util.c:581"}
    #4 0xb682a122 in dri2_make_current ../src/egl/drivers/dri2/egl_dri2.c:1625"}
    #5 0xb67f95a4 in eglMakeCurrent ../src/egl/main/eglapi.c:884"}
    #6 0x4c2b0e in tcu::surfaceless::EglRenderContext::EglRenderContext(glu::RenderConfig const&, tcu::CommandLine const&) (/deqp/modules/gles2/deqp-gles2+0x29b0e)"}
    #7 0x4c3302 in tcu::surfaceless::ContextFactory::createContext(glu::RenderConfig const&, tcu::CommandLine const&, glu::RenderContext const*) const (/deqp/modules/gles2/deqp-gles2+0x2a302)"}
    #8 0x73a9b0 in glu::createRenderContext(tcu::Platform&, tcu::CommandLine const&, glu::RenderConfig const&, glu::RenderContext const*) (/deqp/modules/gles2/deqp-gles2+0x2a19b0)"}
    #9 0x73ad86 in glu::createDefaultRenderContext(tcu::Platform&, tcu::CommandLine const&, glu::ApiType) (/deqp/modules/gles2/deqp-gles2+0x2a1d86)"}
    #10 0x4c6a78 in deqp::gles2::Context::Context(tcu::TestContext&) (/deqp/modules/gles2/deqp-gles2+0x2da78)"}
    #11 0x4c3ba0 in deqp::gles2::TestPackage::init() (/deqp/modules/gles2/deqp-gles2+0x2aba0)"}
    #12 0x852fd8 in tcu::TestHierarchyIterator::next() (/deqp/modules/gles2/deqp-gles2+0x3b9fd8)"}
    #13 0x829660 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x390660)"}
    #14 0x810aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #15 0x4c1d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #16 0xb64b6aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

../src/mesa/state_tracker/st_atom.c:115:8: runtime error: member access within null pointer of type 'struct st_program'"}
    #0 0xaae11a58 in check_program_state ../src/mesa/state_tracker/st_atom.c:115"}
    #1 0xaae128f6 in st_validate_state ../src/mesa/state_tracker/st_atom.c:192"}
    #2 0xaadc58c2 in prepare_draw ../src/mesa/state_tracker/st_draw.c:132"}
    #3 0xaadc58c2 in st_draw_vbo ../src/mesa/state_tracker/st_draw.c:184"}
    #4 0xabc4f924 in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:816"}
    #5 0xabc50240 in _mesa_DrawElements ../src/mesa/main/draw.c:970"}
    #6 0x73ebd2 in glu::CallLogWrapper::glDrawElements(unsigned int, int, unsigned int, void const*) (/deqp/modules/gles2/deqp-gles2+0x2d4bd2)"}
    #7 0x6d86b2 in deqp::gls::FragOpInteractionCase::iterate() (/deqp/modules/gles2/deqp-gles2+0x26e6b2)"}
    #8 0x494d16 in deqp::gles2::TestCaseWrapper::iterate(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x2ad16)"}
    #9 0x7f9cf2 in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x38fcf2)"}
    #10 0x7fa5f0 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x3905f0)"}
    #11 0x7e1aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #12 0x492d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #13 0xb64b9aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:58 +01:00
Tomeu Vizoso
99d4c71f7e panfrost: Don't lose bits!
UBSAN complained that when alpha was 255 and we shifted it 24 positions
to the left, it didn't fit in a signed int. That's because bitwise
operations automatically promote to signed int.

../src/gallium/drivers/panfrost/pan_job.c:1130:64: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'"}
    #0 0xacf953d6 in pan_pack_color ../src/gallium/drivers/panfrost/pan_job.c:1130"}
    #1 0xacf953d6 in panfrost_batch_clear ../src/gallium/drivers/panfrost/pan_job.c:1204"}
    #2 0xaae3226a in st_Clear ../src/mesa/state_tracker/st_cb_clear.c:513"}
    #3 0x4c3d0e in deqp::gles2::TestCaseWrapper::iterate(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x2ad0e)"}
    #4 0x828cf2 in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x38fcf2)"}
    #5 0x8295f0 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x3905f0)"}
    #6 0x810aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #7 0x4c1d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #8 0xb64b6aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:54 +01:00
Tomeu Vizoso
165cb0a5fe util: Don't access members of NULL pointers
Should be harmless, but UBSAN complains about it and fills the logs with
noise.

../src/gallium/auxiliary/util/u_inlines.h:110:8: runtime error: member access within null pointer of type 'struct pipe_surface'"}
    #0 0xaaccf186 in pipe_surface_reference ../src/gallium/auxiliary/util/u_inlines.h:110"}
    #1 0xaaccf186 in util_copy_framebuffer_state ../src/gallium/auxiliary/util/u_framebuffer.c:105"}
    #2 0xaabfb60e in cso_set_framebuffer ../src/gallium/auxiliary/cso_cache/cso_context.c:723"}
    #3 0xaae195ce in st_update_framebuffer_state ../src/mesa/state_tracker/st_atom_framebuffer.c:207"}
    #4 0xaae12316 in st_validate_state ../src/mesa/state_tracker/st_atom.c:261"}
    #5 0xaae31302 in st_Clear ../src/mesa/state_tracker/st_cb_clear.c:438"}
    #6 0x4c3d0e in deqp::gles2::TestCaseWrapper::iterate(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x2ad0e)"}
    #7 0x828cf2 in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x38fcf2)"}
    #8 0x8295f0 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x3905f0)"}
    #9 0x810aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #10 0x4c1d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #11 0xb64b6aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:50 +01:00
Tomeu Vizoso
fb579b0347 nir: Don't copy empty array
It's undefined behavior UBSAN complains about, so fixing this will
reduce the noise a bit.

../src/compiler/nir/nir_clone.c:710:4: runtime error: null pointer passed as argument 2, which is declared to never be null"}
    #0 0xac781be4 in clone_function ../src/compiler/nir/nir_clone.c:710"}
    #1 0xac781be4 in nir_shader_clone ../src/compiler/nir/nir_clone.c:740"}
    #2 0xacf99442 in panfrost_shader_compile ../src/gallium/drivers/panfrost/pan_assemble.c:54"}
    #3 0xacf6b268 in panfrost_bind_shader_state ../src/gallium/drivers/panfrost/pan_context.c:1960"}
    #4 0xaae326bc in set_fragment_shader ../src/mesa/state_tracker/st_cb_clear.c:135"}
    #5 0xaae326bc in clear_with_quad ../src/mesa/state_tracker/st_cb_clear.c:335"}
    #6 0xaae326bc in st_Clear ../src/mesa/state_tracker/st_cb_clear.c:518"}
    #7 0x494d0e in deqp::gles2::TestCaseWrapper::iterate(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x2ad0e)"}
    #8 0x7f9cf2 in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x38fcf2)"}
    #9 0x7fa5f0 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x3905f0)"}
    #10 0x7e1aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #11 0x492d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #12 0xb64b9aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:45 +01:00
Tomeu Vizoso
47a73888f5 pan/midgard: Remove undefined behavior
As found by UBSAN, it should be harmless but it's good to remove any UB
so the tool's output is useful.

../src/panfrost/midgard/midgard_schedule.c:1094:9: runtime error: index -1 out of bounds for type 'midgard_instruction *[6]'"}
    #0 0xad047872 in schedule_block ../src/panfrost/midgard/midgard_schedule.c:1094"}
    #1 0xad04d41a in schedule_program ../src/panfrost/midgard/midgard_schedule.c:1116"}
    #2 0xad031f98 in midgard_compile_shader_nir ../src/panfrost/midgard/midgard_compile.c:2588"}
    #3 0xacf9874e in panfrost_shader_compile ../src/gallium/drivers/panfrost/pan_assemble.c:68"}
    #4 0xacf6b268 in panfrost_bind_shader_state ../src/gallium/drivers/panfrost/pan_context.c:1960"}
    #5 0xaae2596e in st_update_fp ../src/mesa/state_tracker/st_atom_shader.c:168"}
    #6 0xaae12316 in st_validate_state ../src/mesa/state_tracker/st_atom.c:261"}
    #7 0xaadc58c2 in prepare_draw ../src/mesa/state_tracker/st_draw.c:132"}
    #8 0xaadc58c2 in st_draw_vbo ../src/mesa/state_tracker/st_draw.c:184"}
    #9 0xabc4f924 in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:816"}
    #10 0xabc50240 in _mesa_DrawElements ../src/mesa/main/draw.c:970"}
    #11 0x73ebd2 in glu::CallLogWrapper::glDrawElements(unsigned int, int, unsigned int, void const*) (/deqp/modules/gles2/deqp-gles2+0x2d4bd2)"}
    #12 0x6d86b2 in deqp::gls::FragOpInteractionCase::iterate() (/deqp/modules/gles2/deqp-gles2+0x26e6b2)"}
    #13 0x494d16 in deqp::gles2::TestCaseWrapper::iterate(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x2ad16)"}
    #14 0x7f9cf2 in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) (/deqp/modules/gles2/deqp-gles2+0x38fcf2)"}
    #15 0x7fa5f0 in tcu::TestSessionExecutor::iterate() (/deqp/modules/gles2/deqp-gles2+0x3905f0)"}
    #16 0x7e1aac in tcu::App::iterate() (/deqp/modules/gles2/deqp-gles2+0x377aac)"}
    #17 0x492d4c in main (/deqp/modules/gles2/deqp-gles2+0x28d4c)"}
    #18 0xb64b9aa8 in __libc_start_main (/lib/arm-linux-gnueabihf/libc.so.6+0x1aaa8)"}

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:40 +01:00
Tomeu Vizoso
5dfe41239c panfrost: Hold a reference to sampler views
Before we were just copying, but we need to hold a reference as well.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-12 16:26:35 +01:00
Jan Zielinski
bd5077ae1d gallium/swr: Fix Windows build
Tessellator defines own fmin/fmax functions that conflict
with those defined in cmath header. Need to use legacy math.h
which was originally used in MS code.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
2019-12-12 14:35:23 +01:00
Samuel Pitoiset
a0f1a5fa05 ac/nir: fix out-of-bound access when loading constants from global
Global load/store instructions can't know if the offset is
out-of-bound because they don't use descriptors (no range).

Fix this by clamping the offset for arrays that are indexed
with a non-constant offset that's greater or equal to the array
size.

This fixes VM faults and GPU hangs with Dead Rising 4.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2148
Fixes: 71a6794200 ("ac/nir: Enable nir_opt_large_constants")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-12 10:12:56 +00:00
Lionel Landwerlin
2c5eb1df68 anv: fix assumptions about temporary fence payload
Since f9a3d9738b temporary BO_WSI are definitely a thing so we have
an assert wrong.

Take that opportunity to expand a bit on an existing comment.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f9a3d9738b ("anv: Use BO fences/semaphores for AcquireNextImage")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
2019-12-12 10:10:48 +00:00
Lionel Landwerlin
52bc235f2a anv: fix fence underlying primitive checks
We appear to have got lucky that the only type of temporary fence
payload we could have was a syncobj and that would only happen when
the type of the permanent payload was also a syncobj.

This code was broken if that assumption changed and it did in commit
f9a3d9738b.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
2019-12-12 10:10:48 +00:00
Dave Airlie
790bc9a17e vtn/opencl: add shuffle/shuffle support
This adds nir encoding for these, generating them from libclc
was very expensive, and this is a lot simpler.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-12-12 19:40:58 +10:00
Dave Airlie
5471ef7532 vtn: convert vload/store to single value loops
There is an alignment issue doing this the other way, the
spec clearly says vload/store don't require alignment.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-12-12 19:40:15 +10:00
Kenneth Graunke
dcb4230e5e iris: Default to X-tiling for scanout buffers without modifiers
Neither Mutter nor KWin's wayland compositors appear to use modifiers.
In the non-modifier case, iris was still trying to use Y-tiling for
scan-out surfaces, leading to this error:

(gnome-shell:7247): mutter-WARNING **: 09:23:47.787: meta_drm_buffer_gbm_new failed: drmModeAddFB failed: Invalid argument

We now fall back to the historical X-tiling for scanout buffers, which
ought to work everyone, at lower performance.  To regain that, we need
to ensure modifiers are actually supported in environments people use.

Fixes: fbf3124771 ("iris: Rework tiling/modifiers handling")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-11 22:03:48 -08:00
Dave Airlie
3cd903a6c3 llvmpipe: enable ARB_shader_draw_parameters.
All the bits should be in place for this now.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 10:29:43 +10:00
Dave Airlie
75f21895de gallivm: fixup base_vertex support
base vertex should be 0 for non-indexed draws according to the
piglit tests.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 10:16:19 +10:00
Dave Airlie
73f5e2d7ef gallivm/draw: add support for draw_id system value.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 10:16:19 +10:00
Dave Airlie
22a40dd1c1 gallivm: add base instance sysval support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 10:16:19 +10:00
Karol Herbst
20d0ae464c nv50/ir: implement global atomics and handle it for nir
TGSI doesn't have any concept of global memory right now.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Karol Herbst
70c6bff2f0 nir: handle nir_deref_type_ptr_as_array in rematerialize_deref_in_block
I forgot why that was required, but it still is the correct thing to do.

Hit it at some point when working on implementing more CL features.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Rob Clark
ddb9701a3c spirv: add OpLifetime*
These are just hints so we can ignore them.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-12-11 23:54:39 +00:00
Karol Herbst
acc0658942 clover/spirv: allow Int64 Atomics for supported devices
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Karol Herbst
dba8bf1169 clover/nir: set spirv environment to OpenCL
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Karol Herbst
6d08f034ce clover/nir: treat UniformConstant as global memory
Just like we already do in the llvm backend. The current constant buffer code
seems fundamentally flawed and right now we are thinking on how we want to
reimplement all of that.

But until that happens, just treat is as global memory and go on.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Karol Herbst
2402232c90 spirv: handle UniformConstant for OpenCL kernels
The caller is responsible for setting up the ubo_addr_format value as
contrary to shared and global, it's not controlled by the spirv.

Right now clovers implementation of CL constant memory uses a 24/8 bit format
to encode the buffer index and offset, but that code is dead as all backends
treat constants as global memory to workaround annoying issues within OpenCL.

Maybe that will change, maybe not. But just in case somebody wants to look at
it, add a toggle for this inside vtn.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-11 23:54:39 +00:00
Dave Airlie
123f90cf36 gallivm/nir: copy compare ordering code from tgsi
This fixes some isinf/isnan tests copying what the tgsi code
paths do for float compares

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 09:16:41 +10:00
Dave Airlie
8f56ba5da4 gallivm/nir: cleanup code and call cmp wrapper
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 09:16:37 +10:00
Dave Airlie
63b3d38a50 gallivm: fix perspective enable if usage_mask doesn't have 0 bit set
The current code looks like a typo, and fails if the usage_mask
is for a y/z enabled input.

Fixes piglit ext_transform_feedback-immediate-reuse-index-buffer
with llvmpipe/nir

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 09:16:33 +10:00
Dave Airlie
bf29040103 gallivm: fix transpose for when first channel isn't created
The previous fix worked when the second channel wasn't exposed, but
a couple of piglit tests have inputs with just the y/z chans, no x/w.

Partly Fixes piglit ext_transform_feedback-immediate-reuse-index-buffer
with llvmpipe/nir

Fixes: 5363cda52b ("gallivm: add swizzle support where one channel isn't defined.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 09:16:28 +10:00
Dave Airlie
e35b2c37cd llvmpipe/nir: handle texcoord requirements
Switch to using texcoord intrinsic support.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-12 09:16:24 +10:00
Kristian H. Kristensen
b6f8c42846 freedreno/a6xx: Silence warning for unused perf counters
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
9b09776846 freedreno/a6xx: Convert some tile setup to OUT_REG()
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
8a4b0d852c freedreno/a6xx: Convert gmem blits to OUT_REG()
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
201caa7281 freedreno/a6xx: Convert VSC pipe setup to OUT_REG()
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
c71348f84a freedreno/a6xx: Convert emit_zs() to OUT_REG()
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
ffa7d9cbeb freedreno/a6xx: Convert emit_mrt() to OUT_REG()
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
781b2dd63b freedreno/a6xx: Include fd6_pack.h in a few files
Including non-functional changes to get the value from the fd_reg_pair
in places.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
9783f6bc5d freedreno/a6xx: Drop stale include
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
9b05466144 freedreno/registers: Add 64 bit address registers
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
bdd98b892f freedreno: New struct packing macros
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Kristian H. Kristensen
b27b0e8550 freedreno/registers: Remove duplicate register definitions
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 22:25:47 +00:00
Timothy Arceri
f8148d0cc1 docs: remove mailing list as way of submitting patches
All developers now use gitlab, don't confuse newcomers by suggesting
they might use the mailing list. We want everyone to use gitlab so
that patches get run through basic CI before they are merged.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-12 09:09:50 +11:00
Jason Ekstrand
776cfde699 anv: Bump the advertised patch version to 129
We've been keeping up with the spec updates.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-11 18:52:08 +00:00
Jason Ekstrand
5f5f5019bd anv: Unconditionally advertise Vulkan 1.1
Vulkan 1.1 requires VK_KHR_external_fence which requires syncobj support
to be actually usable.  However, it doesn't strictly require that we
support any external handle types.  We should be able to advertise 1.1
even on old kernels that don't have syncobj support.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-11 18:52:08 +00:00
Jason Ekstrand
98a83d0fce anv: Flush the queue on DeviceWaitIdle
When we have syncobj_wait, we can trust in WAIT_FOR_SUBMIT but when we
don't, we only have BO waits and those aren't quite as nice.  This
commit adds a flag to _anv_queue_submit to wait for the queue to drain
before returning.  This gives us the behavior we need to implement
DeviceWaitIdle.

Fixes: 246261f0ad "anv: prepare the driver for delayed submissions"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-11 18:52:08 +00:00
Karol Herbst
0bafde717d nir/tests: MSVC build fix
Fixes: 11f736a6f9 "nir/tests: add serializer tests"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-11 17:12:48 +00:00
Jan Zielinski
ab55708200 swr/rasterizer: Add tessellator implementation to the rasterizer
This is initial commit on the way to implement ARB_tessellation_shader
extension in OpenSWR. It introduces tessellator implementation
taken from Microsoft GitHub (published under MIT license):

https://github.com/microsoft/DirectX-Specs/blob/master/d3d/archive/images/d3d11/tessellator.cpp
https://github.com/microsoft/DirectX-Specs/blob/master/d3d/archive/images/d3d11/tessellator.hpp

It also adds some glue code that connects the tessellator
to the internals of SWR rasterizer.

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviwed-by: Alok Hota <alok.hota@intel.com>
2019-12-11 16:54:37 +00:00
Samuel Pitoiset
ff2e11b210 gitlab-ci: set RADV_DEBUG=checkir for RADV test jobs
This is used to validate if the driver emits correct LLVM IR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-11 15:44:40 +00:00
Eric Engestrom
b2dac806f8 intel: add mi_builder_test for gen12
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-11 15:38:19 +00:00
Rohan Garg
2129b4152c gitlab-ci: Use lavacli from packages
lavacli 0.9.8 is now available in Debian Testing.
Ref: https://tracker.debian.org/news/1066828/lavacli-098-1-migrated-to-testing/
Fixes: 555c0de ("gitlab-ci: Move LAVA-related files into top-level ci dir")

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-11 15:19:43 +00:00
Erico Nunes
7701b7b7ee lima/ppir: enable lower_fdph
Otherwise we may lower some fdot to fdph which is not implemented in pp.

Fixes #2126

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-12-11 15:55:48 +01:00
Karol Herbst
11f736a6f9 nir/tests: add serializer tests
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-12-11 13:00:44 +01:00
Karol Herbst
676232d76f nir/serialize: fix vec8 and vec16
Nir serializes uses nir_ssa_alu_instr_src_components in a few places to
determine how many components a src has, but that's not what this function
returns. It simply returns how many channels are used, which is still fine
for most of the code.

This was breaking code like this:

vec16 32 ssa_1 = intrinsic load_global
vec1  32 ssa_2 = fmax ssa_1.a, ssa_2.b

v2: make the 16bit encoding work for identify swizzles again

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-12-11 13:00:44 +01:00
Bas Nieuwenhuizen
2e44bfc14f radv: Fix RGBX Android<->Vulkan format correspondence.
This is correct per the Vulkan spec format equivalence table.

Fixes: f36b52740a "radv/android: Add android hardware buffer queries."
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-11 11:40:13 +01:00
Tomeu Vizoso
63ae9e61c1 panfrost: Add PAN_MESA_DEBUG=sync
Sometimes it's useful to get information about GPU faults in the
console, so it's synchronized with other messages.

This commit will cause Mesa to wait for completion and check if there
are any faults raised by the GPU.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-11 08:01:20 +01:00
Kenneth Graunke
2e654db27a iris: Create smaller program keys without legacy features
A lot of the brw_*_prog_key fields are for emulating features on legacy
hardware that iris doesn't support.  In particular, all of the texture
swizzle fields take up a lot of space.  These dead fields make hashing
the shader keys more expensive than it ought to be.

We introduce iris-specific keys with only the information we need, and
translate them to brw keys when actually compiling new variants.  This
way, key comparisons can use the small keys.  The size reductions are:

   VS:  328 bytes ->  8 bytes
   TCS: 312 bytes -> 24 bytes
   TES: 304 bytes -> 24 bytes
   GS:  284 bytes ->  8 bytes
   FS:  304 bytes -> 16 bytes
   CS:  280 bytes ->  4 bytes

Scores for the Piglit drawoverhead microbenchmark case with a shader
program change improve by roughly 30%.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-10 22:25:41 -08:00
Pierre Moreau
8ccd3f48a0 compiler/spirv: Fix uses of gnu struct = {} extension
Fixes: a24d6fbae6 ("meson: Add -Werror=gnu-empty-initializer to MSVC compat args")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
2019-12-11 06:03:22 +00:00
Vinson Lee
9661fc9cdb util/u_thread: Restrict u_thread_get_time_nano on macOS.
macOS does not have pthread_getcpuclockid.

src/util/u_thread.h:156:4: error: implicit declaration of function 'pthread_getcpuclockid' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   pthread_getcpuclockid(thread, &cid);
   ^

Fixes: 4913215d14 ("util/u_thread: don't restrict u_thread_get_time_nano() to __linux__")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2171
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-12-10 21:35:47 -08:00
Eric Anholt
8bf590b46b tu: Move UBWC layout into fdl6_layout() and use that function.
This gets us shared non-UBWC layout code between gallium and turnip.
Until I fix up the rest of gallium to handle UBWC mipmapping, we do the
single-level UBWC setup in gallium as a fixup after layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Eric Anholt
de619d7503 freedreno: Switch the 16-bit workaround to match what turnip does.
Prevents regressions on argb1555 and rgb565 when making turnip use
freedreno's layout.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Eric Anholt
d9cf3e76bd freedreno: Move a6xx's setup_slices() to a shareable helper function.
We pass in all the parameters for setting up the layout, though freedreno
still sets a few of them up early (since it uses layout helpers in making
some decisions about the layout setup parameters that will be cleaned up
once krh's blitter work lands).
2019-12-11 04:24:18 +00:00
Eric Anholt
67258a44d2 tu: Move our image layout into a freedreno_layout struct.
This lets us start using some of the fdl_* helpers and have more obviously
matching code between gallium and turnip.  We can't yet use the fdl_* UBWC
helpers, since the gallium driver doesn't do UBWC mipmaps (which I'm
working on in another branch).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Eric Anholt
ea7631a9a6 freedreno: Move UBWC layout into a slices array like the non-UBWC slices.
This is a little refactor in preparation for UBWC mipmapping support.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Eric Anholt
bbe84c6c31 freedreno: Refactor the UBWC flags registers emission.
It's the same logic for each of these being emitted, and I was about to
change the rsc->layout.* for UBWC.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Eric Anholt
97be9503bb freedreno: Drop the extra offset field for mipmap slices.
We can just bake the UBWC-goes-first delta into the slices at setup time.
I did have to fix up the resource shadowing swap path to swap the slice
fields, as it was missing and regressed the format reinterpets otherwise.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-11 04:24:18 +00:00
Kenneth Graunke
69d7782b15 intel/decoder: Make get_state_size take a full 64-bit address and a base
i965 wants to use an offset from a base because everything is in a
single buffer whose address may be relocated, and all base addresses
are set to the start of that buffer.

iris wants to use a full 64-bit address, because state lives in separate
buffers which may be in the shader, surface, and dynamic memory zones,
where addresses grow downward from the top of a 4GB zone,  So it's very
possible for a 32-bit offset to exist relative to multiple bases,
leading to the wrong state size.
2019-12-10 19:10:49 -08:00
Dongwon Kim
8a8534a698 iris: INTEL performance query implementation
low-level implementation of INTEL-performance-query APIs in
Intel iris driver. Most of functions and procedures defined here
are adopted from i965 driver (brw_performance_query.c)

v2: - replace genX_init_performance_query with
      iris_init_perfquery_functions which is gen's version agnositic
    - general code clean-up

v3: include gen_perf_gens.h as some of defines were moved to this new
    header file

v4: - checking for kernel 4.13+ won't be needed here as Iris won't be
      loaded anyway without DRM_SYNCOBJ that is enabled after Kernel
      4.13.

    - checking whether gen < 8 or is_cherryview won't be required as
      well because those cases are screened in iris_screen_create.

v5: remove genX(init_performance_query)

v6: - remove oa_metrics_kernel_support as iris works only with kernel
    4.18 and newer.

    - use perf functions defined in separate file, iris_perf.h/c

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-10 17:02:58 -08:00
Mark Janes
ca2dd99bf6 iris: separating out common perf code
The configuration of the gen_perf vtable will be the same for
INTEL_performance_query and AMD_performance_monitor.
Initialize the table in a single routine that can be called from both
implementations.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-10 17:02:58 -08:00
Dongwon Kim
106054ef79 gallium: enable INTEL_PERFORMANCE_QUERY
new state tracker APIs added for INTEL_performance_query
This extension is enabled if all vendor specific functions for it
exist.

v2: add st_cb_perfquery.* to the list of sources in Makefile
v3: minor code clean-up
v4: - add driver hooks for intel-performance-query apis
    - add PIPE level performance counter and type enums that
      match to OpenGL enums
    - do conversion of pipe_perf_counter_type and
      pipe_perf_counter_data_type enums to GL defines in state_tracker

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-10 17:02:58 -08:00
Dylan Baker
d0eebda990 meson/broadcom: libbroadcom_cle also needs zlib
Fixes: 1ae8018a6a
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-11 00:49:44 +00:00
Kenneth Graunke
0f2f561a10 anv: Enable Gen11 Color/Z write merging optimization
TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-10 16:19:46 -08:00
Kenneth Graunke
5cc7636993 iris: Enable Gen11 Color/Z write merging optimization
TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Improves performance in Manhattan 3.0 by 6% on ICL 8x8 at a fixed
frequency, according to Felix Degrood.  I didn't see any improvements
at out-of-the-box power management settings, however.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-10 16:19:43 -08:00
Kenneth Graunke
0b74f85870 intel/genxml: Add a partial TCCNTLREG definition
TCCNTLREG contains additional cache programming settings.  In
particular, there are several write combining controls we'd like to use.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-10 16:19:33 -08:00
Kenneth Graunke
74665eaf3a util: Detect use-after-destroy in simple_mtx
This makes simple_mtx_destroy set the counter to an invalid canary
value and then makes lock/unlock assert that the value is legal.

That way, calling lock/unlock after destroy will assert fail,
rather than deadlocking or potentially even working.

This has caught real deadlocks in dEQP multithreaded tests (in st/mesa
shader variant zombie list handling), which have since been fixed.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-12-10 23:48:40 +00:00
Rob Clark
fc97643c57 freedreno/a6xx: enable LRZ by default
Now that dEQP should be happy, lets flip the switch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-10 22:55:21 +00:00
Rob Clark
1b4c12d3ee freedreno/a6xx: fix LRZ logic
In particular, we need to invalidate the LRZ state when we cannot be
confident in what the Z state would be during rendering:

1) depth test modes not supported by LRZ
2) stencil test, which would require full rasterization and stencil
   test in the binning pass (whereas LRZ normally just needs to
   determine the min and max z value in an 8x8 quad)

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-10 22:55:21 +00:00
Rob Clark
3c479849c5 freedreno/a6xx: fix LRZ layout
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-10 22:55:21 +00:00
Rob Clark
6cf101402d freedreno/a5xx+a6xx: split LRZ layout to per-gen
Seems to be a bit different for a6xx, so let's split this out.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-10 22:55:21 +00:00
Rob Clark
3b074a2e53 freedreno/a6xx: disable LRZ when blending
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-10 22:55:21 +00:00
Marek Olšák
a305543c8d radeonsi: don't rely on CLEAR_STATE to set PA_SC_GENERIC_SCISSOR_*
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 16:32:37 -05:00
Marek Olšák
aced18aa61 radeonsi/gfx10: simplify the tess_turns_off_ngg condition
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 16:32:36 -05:00
Marek Olšák
42f921387b radeonsi/gfx10: disable vertex grouping
based on PAL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 16:32:34 -05:00
Marek Olšák
75ce078a0a radeonsi: enable NIR by default and document GL 4.6 support
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 15:48:58 -05:00
Marek Olšák
42b28e7ac3 st/dri: assume external consumers of back buffers can write to the buffers
This was reverted needlessly because if was part of another series.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
2019-12-10 15:37:37 -05:00
Jason Ekstrand
41691ac016 ANV: Stop advertising smoothLines support on gen10+
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
2019-12-10 20:13:56 +00:00
Dylan Baker
85a9698ac3 meson/broadcom: libbroadcom_cle needs expat headers
Fixes: 1ae8018a6a
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-10 10:48:38 -08:00
Lionel Landwerlin
5fdea9f401 anv: fix incorrect VMA alignment for CCS main surfaces
Maybe finer way of dealing with this requirement would be to increase
the number of pdevice->memory.types[] to add a category for special
alignment cases.

Meanwhile this fixes the problem of CCS surface alignment and it's
probably not going to cause issues given the size of our address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6af8a4acc4 ("anv: Add aux-map translation for gen12+")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-10 16:06:54 +00:00
Lionel Landwerlin
dcfe1903c3 anv: fix missing gen12 handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 181be14d43 ("anv: Build for gen12")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-12-10 16:06:54 +00:00
Eric Engestrom
865f4b193f docs: reword a bit and list HTTPS before FTP
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-12-10 15:21:23 +00:00
Eric Engestrom
d90e656fa7 meson: drop intel_ prefix on imgui_core
Again, no real effect, just the name of a temporary build file.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-10 15:16:02 +00:00
Eric Engestrom
2b0e3e9fd1 meson: drop duplicate lib prefix on libiris_gen*
This has no real effect other than the names of the temporary files in
the build folder.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-10 15:16:02 +00:00
Samuel Pitoiset
e4c8491bdf radv: implement VK_KHR_separate_depth_stencil_layouts
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 13:16:17 +01:00
Samuel Pitoiset
48ee62178f radv: initialize HTILE for separate depth/stencil aspects
It either clears the whole HTILE buffer or part of it depending
on the HTILE mask parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 13:09:29 +01:00
Samuel Pitoiset
41cebfc9c1 radv: do not init HTILE as compressed state when dst layout allows it
I don't think this makes much differences and a potential clear
following the initialization will overwrite HTILE anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 13:09:26 +01:00
Samuel Pitoiset
b603cc8c84 radv: synchronize after performing a separate depth/stencil fast clears
For depth+stencil images, the driver might use an optimized path
if only one aspect is cleared. It either clears the depth or the
stencil part of HTILE. Because the two separate aspects might use
the same HTILE memory we have to synchronize.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 13:09:22 +01:00
Michel Dänzer
dadd609664 gitlab-ci: Don't exclude any piglit quick_shader tests
Now that we're running these with process isolation enabled, their
results will hopefully be stable.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-10 11:19:11 +00:00
Krzysztof Raszkowski
cfe00a52f0 gallivm: add TGSI bit arithmetic opcodes support
Add TGSI_OPCODE_BFI, TGSI_OPCODE_POPC, TGSI_OPCODE_LSB,
TGSI_OPCODE_IMSB, TGSI_OPCODE_UMSB, TGSI_OPCODE_IBFE,
TGSI_OPCODE_UBFE, TGSI_OPCODE_BREV support.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-12-10 10:34:18 +00:00
Samuel Pitoiset
008fe909ca radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast
PA_SC_AA_CONFIG might be updated when conversative rasterization is
enabled. Because the driver only re-emits the multisample state if
the number of samples is different, that register value might not
be updated correctly.

Found by inspection, doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 11:04:43 +01:00
Samuel Pitoiset
4f659224c8 radv: move emission of two PA_SC_* registers to the pipeline CS
They don't have to be updated dynamically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-10 11:04:40 +01:00
Pierre-Eric Pelloux-Prayer
87f7ec8a2c st/dri: use st->flush callback to flush the backbuffer
Previously the flush was done before the call to st->flush but
could lead to problems as FLUSH_VERTICES could push some work
that would change the backbuffer (or modify it).

With this commit, all the backbuffer flushing code is executed
right before the call to st_flush.

Closes: https://gitlab.freedesktop.org/drm/amd/issues/842
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205049

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 09:25:28 +01:00
Pierre-Eric Pelloux-Prayer
cc0d0afe3b st/mesa: add a notify_before_flush callback param to flush
The new callback is called right before the flush is done to allow
users of st->flush to do some work after all the previous work has
been flushed.

This will be used by dri_flush in the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 09:25:28 +01:00
Pierre-Eric Pelloux-Prayer
f5c1cb2383 radeonsi: dcc dirty flag
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 09:25:28 +01:00
Pierre-Eric Pelloux-Prayer
e3e91cebcd radeonsi: fix multi plane buffers creation
When using 3 planes, the sequence produces this chain:
  plane0 -> plane2
This commit fixes this to produce:
  plane0 -> plane1 -> plane2

Fixes: 86e60bc265 ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2193
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 08:52:16 +01:00
Pierre-Eric Pelloux-Prayer
ff0f108666 radeonsi: use gfx9.surf_offset to compute texture offset
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2177
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 08:52:07 +01:00
Sonny Jiang
6c901f0675 radeonsi: use compute shader for clear 12-byte buffer
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 23:25:57 -05:00
Marek Olšák
38e9eb9561 st/mesa: release the draw shader properly to fix driver crashes (iris)
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 22:41:41 -05:00
Marek Olšák
41118246c6 draw, st/mesa: generate TGSI for ffvp/ARB_vp if draw lacks LLVM
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
a3de63fbb3 st/mesa: don't generate VS TGSI if NIR is enabled
it's no longer needed

Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
a90f4453fe st/mesa: remove struct st_vp_variant in favor of st_common_variant
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
6299b90fd4 st/mesa: remove st_vp_variant::num_inputs
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
bc99b22a30 st/mesa: use a separate VS variant for the draw module
instead of keeping the IR indefinitely in st_vp_variant.

This trivially fixes Selection/Feedback/RasterPos for NIR.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
17e8839a2f st/mesa: support shader images for Selection/Feedback/RasterPos
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
b7393f1115 st/mesa: support SSBOs for Selection/Feedback/RasterPos
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
e91b044bd8 st/mesa: support samplers for Selection/Feedback/RasterPos
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
2891c4b2e2 st/mesa: save currently bound vertex samplers and sampler views in st_context
for st_draw_feedback.c

Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
226e7aee70 st/mesa: support UBOs for Selection/Feedback/RasterPos
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
60db75cb77 gallivm: implement LOAD with CONSTBUF but don't enable it for llvmpipe
This is already used in st_draw_feedback.c, because it uses shaders
generated for drivers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-09 21:09:28 -05:00
Marek Olšák
525c8b90c7 llvmpipe: implement TEX_LZ and TXF_LZ opcodes
gallivm receives these opcodes anyway because st_draw_feedback.c uses
shaders that were assembled for drivers, not llvmpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-09 21:09:28 -05:00
Gurchetan Singh
3c8ddc8f4b drirc: set allow_higher_compat_version for Faster Than Light
With 781a78 ("mesa: enable ARB_direct_state_access in compat for
GL3.1+), it's possible to have DSA with GL3.1+.

FTL creates a GL3.1 compat context, but fails the
_mesa_has_geometry_shaders(..) check in frame_buffer_texture.

Bump the compat version to pass the check.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:27:02 -08:00
Roland Scheidegger
23f1b78e8f util/atomic: Fix p_atomic_add for unlocked and msvc paths
Braces mismatch (flagged by CI, untested).

Fixes: 385d13f26d "util/atomic: Add a _return variant of p_atomic_add"

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 15:02:58 -08:00
Eric Anholt
0470a03769 freedreno: Track the set of UBOs to be uploaded in UBO analysis.
We were iterating over the entire 32-entry array each time, when we
can just use a bitset to know that we're only uploading from the first
entry normally.

Knocks ir3_emit_user_consts down from ~.5% of CPU to .1% on WebGL
fishtank.

Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-12-09 14:13:50 -08:00
Eric Anholt
10da0a9d18 freedreno: Stop forcing ALLOW_MAPPED_BUFFERS_DURING_EXEC off.
The default is to not throw GL errors when drawing with mapped
buffers, but we were forcing it on for unclear reasons.  Internally we
keep all our buffers mapped anyway, so it should be a no-op other than
reducing CPU overhead (.23% in a perf report for WebGL fishtank)

Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-12-09 14:13:47 -08:00
Rob Clark
dc791d3c68 freedreno/fdperf: use drmOpen()
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-09 13:09:58 -08:00
Alyssa Rosenzweig
a37822f5f7 gallium/util: Support POLYGON in u_stream_outputs_for_vertices
u_decomposed_prims_for_vertices cannot support POLYGON, but POLYGON is
trivial to support as a special case directly (since we have the number
of vertices directly).

Fixes aborts in Panfrost in apps using GL_POLYGON.

Fixes: e881aa8c12 ("gallium/util: Add u_stream_outputs_for_vertices helper")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Revewied-by: Eric Anholt <eric@anholt.net>
2019-12-09 21:09:05 +00:00
Anuj Phogat
1a32fbd48c intel: Add pci-ids for Jasper Lake
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-09 12:22:57 -08:00
Anuj Phogat
11fdd5f52c intel: Add device info for 1x4x6 Jasper Lake
Also removing the FIXME comments after matching the numbers with
updated documentation.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-09 12:22:56 -08:00
Vasily Khoruzhick
9f5fa496cb lima: expose tiled format modifier in query_dmabuf_modifiers()
Fixes: 8c12f4e5f2 ("lima: enable tiling")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-12-09 15:21:55 +00:00
Vasily Khoruzhick
01a451b04d lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()
Assume that resource is tiled if we get DRM_FORMAT_MOD_INVALID
in resource_from_handle() and we don't have RO.

Fixes: 8c12f4e5f2 ("lima: enable tiling")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-12-09 15:21:55 +00:00
Jonathan Marek
9d78cf4584 turnip: add hw binning
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-09 08:22:18 -05:00
Samuel Pitoiset
86dfe92bd0 radv: do not use VK_TRUE/VK_FALSE
For consistency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-09 09:21:26 +01:00
Dave Airlie
d7dc14628a gallivm: add bitfield reverse and ufind_msb
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
2019-12-09 06:05:02 +10:00
Roland Scheidegger
1c7693e3bd gallium/scons: fix graw_gdi build
Fixes: 44a6b0107b (gallivm: add nir->llvm translation (v2))
Reviewed-by: Dave Airlie <Airlied@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-12-07 17:50:53 +01:00
Daniel Schürmann
8259c97b2d aco: propagate temporaries into expanded vectors
Gives a very slight decrease in code size:
Totals from affected shaders:
Code Size: 1708488 -> 1702768 (-0.33 %) bytes
Max Waves: 2858 -> 2855 (-0.10 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
df3e674fb3 aco: improve readfirstlane after uniform ssbo loads on GFX7
pipeline-db changes for GFX7:

80310 shaders in 40472 tests
Totals:
SGPRS: 3655900 -> 3643916 (-0.33 %)
VGPRS: 2678324 -> 2686324 (0.30 %)
Spilled SGPRs: 1730 -> 1634 (-5.55 %)
Spilled VGPRs: 14 -> 21 (50.00 %)
Scratch size: 15540 -> 15536 (-0.03 %) dwords per thread
Code Size: 136106120 -> 135457616 (-0.48 %) bytes
LDS: 1259 -> 1259 (0.00 %) blocks
Max Waves: 601014 -> 600206 (-0.13 %)

Totals from affected shaders:
SGPRS: 307832 -> 295848 (-3.89 %)
VGPRS: 267864 -> 275864 (2.99 %)
Spilled SGPRs: 770 -> 674 (-12.47 %)
Spilled VGPRs: 14 -> 21 (50.00 %)
Scratch size: 16 -> 12 (-25.00 %) dwords per thread
Code Size: 22007488 -> 21358984 (-2.95 %) bytes
LDS: 65 -> 65 (0.00 %) blocks
Max Waves: 28668 -> 27860 (-2.82 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
0837471463 aco: use soffset for MUBUF instructions on SI/CI
pipeline-db changes for GFX7:

80310 shaders in 40472 tests
Totals:
SGPRS: 3655300 -> 3655900 (0.02 %)
VGPRS: 2677732 -> 2678324 (0.02 %)
Spilled SGPRs: 1730 -> 1730 (0.00 %)
Spilled VGPRs: 14 -> 14 (0.00 %)
Scratch size: 15540 -> 15540 (0.00 %) dwords per thread
Code Size: 136488364 -> 136106120 (-0.28 %) bytes
LDS: 1259 -> 1259 (0.00 %) blocks
Max Waves: 601039 -> 601014 (-0.00 %)

Totals from affected shaders:
SGPRS: 316312 -> 316912 (0.19 %)
VGPRS: 273844 -> 274436 (0.22 %)
Spilled SGPRs: 770 -> 770 (0.00 %)
Spilled VGPRs: 14 -> 14 (0.00 %)
Scratch size: 16 -> 16 (0.00 %) dwords per thread
Code Size: 22724904 -> 22342660 (-1.68 %) bytes
LDS: 114 -> 114 (0.00 %) blocks
Max Waves: 30861 -> 30836 (-0.08 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
7b38d95b32 radv: Enable ACO on GFX7 (Sea Islands)
This patch also disables AMD_shader_ballot on GFX7 by default if ACO is used.
Note that shader_ballot works correctly, but performance seems inferior.
To enable shader_ballot use RADV_PERFTEST=shader_ballot.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
28c95cc402 aco: return to loop_active mask at continue_or_break blocks
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
0f9447ccb0 radv: disable Youngblood app profile if ACO is used
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
746165e540 aco: implement exclusive scan for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
7ae227effd aco: implement inclusive_scan for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
f895a8b1df aco: implement (clustered) reductions for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
9254fb4fc7 aco: don't use a scalar temporary for reductions on GFX10
This patch also adds the scalar temporary for scans on SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
8ad43d8838 aco: flush denorms after fmin/fmax on pre-GFX9
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
21f67a3bdc radv: only flush scalar cache for SSBO writes with ACO on GFX8+
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
79ce6c1b33 aco: disable disassembly for SI/CI due to lack of support by LLVM
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
1c4afe38f2 aco: implement 64bit ine/ieq for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
1e1356b2ad aco: implement 64bit i2b for SI /CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
da7ff58835 aco: make 1/2*PI a literal constant on SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
90fad7360d aco: implement 64bit VGPR shifts for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
6a586a6006 aco: split read/writelane opcode into VOP2/VOP3 version for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
23319add93 aco: fix disassembly of writelane instructions.
ACO writes an unused 3rd operand for internal usage
which makes LLVM recoginize it as illegal instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
6fc9ddfef8 aco: recognize SI/CI SMRD hazards
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
3eed4d2be5 aco: implement quad swizzles for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
bde9c1e3a1 aco: move buffer_store data to VGPR if needed
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
a8195bdf2e aco: implement nir_op_isign on SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
b8783973cd aco: only use scalar loads for readonly buffers on SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
f27783a667 aco: implement nir_op_fquantize2f16 for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
caea4bbfdc aco: fix SMEM offsets for SI/CI
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
8aab92b393 aco: SI/CI - fix sampler aniso
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Dave Airlie
9b533a2ca3 aco: handle gfx7 int8/10 clamping on exports
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
0d42e4d7a0 aco: Initial GFX7 Support
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Daniel Schürmann
3177346bfc aco: refactor visit_store_fs_output() to use the Builder
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-12-07 11:23:11 +01:00
Jason Ekstrand
0f60aa4037 anv: Re-emit all compute state on pipeline switch
It's a very odd case to hit in the real world.  However, there are some
CTS tests which switch back and forth between dispatch and clear without
changing the pipeline.

Fixes: bc612536eb "anv: Emit a dummy MEDIA_VFE_STATE before switching..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-07 04:03:35 +00:00
Jason Ekstrand
bce1c3c668 anv: Re-capture all batch and state buffers
When we moved from allocating BOs directly to using the BO cache, we
lost the EXEC_OBJECT_CAPTURE flag on all our state buffers.

Fixes: 3119b96bdf "anv: Allocate block pool BOs from the cache"
Fixes: ee77938733 "anv: Allocate batch and fence buffers from..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-07 04:03:35 +00:00
Jason Ekstrand
865ffe4e02 anv: Return VK_ERROR_OUT_OF_DEVICE_MEMORY for too-large buffers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 22:32:05 +00:00
Eric Anholt
e3b249f166 freedreno: Enable texture upload memory throttling.
Fixes oom-killer during streaming-texture-upload, which I found while
trying to enable piglit in CI.

Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-12-06 14:03:50 -08:00
Fritz Koenig
c496d44284 freedreno: reorder format check
With the addition of the planar formats helper, the
planar formats no longer have a valid block.bits field.
Calling util_format_get_blocksize therefore asserts.

Reorder the check to see if the format is supported
before doing the query to get the blocksize.

Fixes: 20f132e5ef ("gallium/util: add planar format layouts and helpers")

Signed-off-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-12-06 21:27:10 +00:00
Nanley Chery
21376cffb3 iris: Fix import of multi-planar surfaces with modifiers
Multi-planar surfaces are allowed to have modifiers. Don't require
DRM_FORMAT_MOD_INVALID in order to create a surface for each plane
defined by the format.

Fixes: 246eebba4a ("iris: Export and import surfaces with modifiers that have aux data")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-06 20:31:48 +00:00
Nanley Chery
51ee8fff9b gallium: Store the image format in winsys_handle
This format will be used to properly handle planar images with modifiers
in iris.

Fixes: 246eebba4a ("iris: Export and import surfaces with modifiers that have aux data")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-06 20:31:48 +00:00
Nanley Chery
d5c857837a gallium/dri2: Fix creation of multi-planar modifier images
The commit noted below assumed and enforced that DRM_MOD_INVALID was the
only valid modifier for multi-planar imported images. Due to that, it
required that modifier on multi-planar images to:

   1. Allow multiple planes.
   2. Perform YUV format lowering and extent adjustments.
   3. Use buffer_index to correctly map the given planes.

Fix these issues by removing or updating the code built on that
assumption.

Fixes: 2066966c10 ("gallium/dri2: Support creating multi-planar modifier images")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-06 20:31:48 +00:00
Kenneth Graunke
ab016a6a2d meson: Include iris in default gallium-drivers for x86/x86_64
We build i965 by default on x86/x86_64 platforms; let's build iris too.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-06 12:27:26 -08:00
Jason Ekstrand
f9a3d9738b anv: Use BO fences/semaphores for AcquireNextImage
Instead of doing a dummy submit on the command buffer for the fence or a
dummy semaphore and trusting in implicit sync, this commit moves us to
take advantage of implicit sync and just use the WSI image BO as the
fence.  Both semaphores and fences require a tiny bit of extra plumbing
to do this but the result is that we can get rid of a bunch of the extra
synchronization we're doing today.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:07 +00:00
Jason Ekstrand
ecc119a96e anv: Add a fence_reset_reset_temporary helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:07 +00:00
Jason Ekstrand
ccb7d606f1 anv: Use submit-time implicit sync instead of allocate-time
In 83b943cc2f, we started making all VkDeviceMemory BOs resident all
the time.  One unfortunate side-effect of this is that every
vkQueueSubmit sets EXEC_OBJECT_WRITE on every WSI memory object which
means that X server or Wayland compositor, instead of waiting on the
last vkQueueSubmit to actually write the buffer, now waits on the last
vkQueueSubmit to from that driver instance relative to whenever the
compositor's GL driver instance calls execbuf.  This potentially leads
to a lot of extra synchronization that we didn't intend to have.

Instead, this commit makes it so that we leave WSI memory objects with
EXEC_OBJECT_ASYNC most of the time and only unset EXEC_OBJECT_ASYNC and
set EXEC_OBJECT_WRITE in the dummy execbuf that we do as part of
vkQueuePresent.  This should hopefully result in tighter integration
with the compositor, lower latency, and better performance.

Testing with DOOM 2016, this seems to reduce latency by at least a frame
if not two and makes the game much more responsive.  Testing was,
however, subjective, so we don't have any hard data on that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:07 +00:00
Jason Ekstrand
6ebf677cfd anv: Always add in EXEC_OBJECT_WRITE when specified in extra_flags
Otherwise, we're trusting in the execbuf_add_bo which sets
EXEC_OBJECT_WRITE to to always be the first one that gets called.  This
is likely true for fences but it seems somewhat fragile.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:07 +00:00
Jason Ekstrand
778b51f491 vulkan/wsi: Add a hooks for signaling semaphores and fences
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:07 +00:00
Jason Ekstrand
48e23a6406 vulkan/wsi: Provide the implicitly synchronized BO to vkQueueSubmit
This lets us treat the implicit synchronization that we need for X11 and
Wayland like a semaphore.  Instead of trusting the driver to somehow
figure out when that memory object needs to be signaled, we provide an
explicit point where the driver can set EXEC_OBJECT_WRITE and signal the
dma_fence on the BO.  Without this, we have to somehow track inside the
driver when WSI buffers are actually used to avoid extra synchronization
dependencies.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-06 19:58:06 +00:00
Urja Rannikko
d07ed0c9c9 panfrost: free spill cost table in mir_spill_register
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 15:26:13 +00:00
Urja Rannikko
12e393bacf panfrost: add lcra_free() to free lcra state
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 15:26:13 +00:00
Urja Rannikko
5b6108834b panfrost: free allocations in schedule_block
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 15:26:13 +00:00
Urja Rannikko
e2dbea683c panfrost: free last_read/write tables in mir_create_dependency_graph
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 15:26:13 +00:00
Alyssa Rosenzweig
adf716dc7f panfrost: Rename SET_VALUE to WRITE_VALUE
See
https://lists.freedesktop.org/archives/dri-devel/2019-December/247601.html

Write value emphasises that it's just a generic write primitive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 14:37:17 +00:00
Alyssa Rosenzweig
9eae950342 panfrost: Update SET_VALUE with information from igt
It's not a tiler specific initialization; it's a generic GPU-side write
primitive that may be used for tiler reset on midgard.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-06 14:37:17 +00:00
Samuel Pitoiset
c1a362722f gitlab-ci: add a job that runs Vulkan CTS with RADV conditionally
Only Polaris10 is tested at the moment, and I disabled a TON of
tests to keep a CTS run within 5 minutes because my local runner
is a bit slow. A full CTS run takes more than 1h, which means it
will hit the timeout.

RADV CI can only be triggered manually on personal branches to
avoid breaking the world because one runner is definitely not
enough. This will allow us to test it until it's stable enough
to be enabled by default.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:58:03 +01:00
Samuel Pitoiset
40c6a56751 gitlab-ci: build RADV in meson-testing
This requires to bump LLVM to 8 because it's the minimum supported
version by RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:58:00 +01:00
Samuel Pitoiset
f32bf4f1e2 gitlab-ci: configure the Vulkan ICD export with VK_DRIVER
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-06 10:57:57 +01:00
Samuel Pitoiset
16b999b7d1 gitlab-ci: allow to run dEQP Vulkan with DEQP_VER
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:55 +01:00
Samuel Pitoiset
0b246d3558 gitlab-ci: add a new base test job for VK
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:54 +01:00
Samuel Pitoiset
35a7ec79db gitlab-ci: build dEQP VK 1.1.6 in the x86 test image for VK
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:52 +01:00
Samuel Pitoiset
4bbb1d3b06 gitlab-ci: build cts_runner in the x86 test image for VK
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:50 +01:00
Samuel Pitoiset
f2a594f384 gitlab-ci: add a new job that builds a base test image for VK
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:48 +01:00
Samuel Pitoiset
520a77d486 gitlab-ci: add a gl suffix to the x86 test image and all test jobs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:46 +01:00
Samuel Pitoiset
7e0ab6aae0 gitlab-ci: rename build-deqp.sh to build-deqp-gl.sh
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-06 10:57:45 +01:00
Michel Dänzer
41797a1fed gitlab-ci: Overhaul job run policy
Use new rules: instead of only:

For container stage jobs:

* In the main Mesa project, run them by default.

* In merge requests, run them by default if any files affecting pipeline
  results are changed.

* In all other cases (in particular branches in personal projects),
  don't run them by default but allow triggering them manually.

build & test stage jobs are left at the default (when: on_success), so
they will run automatically once all their dependencies are satisified.
(Using the same rules as above would require these jobs to be manually
triggered as well, which is only possible once all dependency jobs have
passed) Please be considerate of CI runner resources and cancel unneeded
jobs on personal branches with no corresponding merge requests (this can
be done before the jobs start running).

In summary: No more special branch names. Unnecessary job runs are
avoided by default, but jobs which don't run by default can be triggered
manually.

v2:
* Split out LAVA changes to separate commit
* Clarify commit log a little, in particular WRT build/test stage jobs

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> # v1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> # v1
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> # v1
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-06 10:02:01 +01:00
Michel Dänzer
ebd1309fef gitlab-ci: Use the common run policy for LAVA jobs as well again
Having different policies could have some weird results, e.g. changes
only touching documentation (where the intention is not to run the
pipeline by default) would still create a pipeline with the LAVA jobs
running by default.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-06 09:39:40 +01:00
Jonathan Marek
0796e7e70d turnip: implement border color
Fixes the deqp fails in:
dEQP-VK.pipeline.sampler.*border*
(minus 1d array/d24 cases which fail for other reasons)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-05 22:12:30 -05:00
Jonathan Marek
095d35eff8 turnip: improve emit_textures
Two things:
* Texture/sampler pointers aligned to the size of texture/sampler state
* Returning errors instead of crashing on OOM

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-05 22:12:30 -05:00
Jonathan Marek
3ab4f99461 turnip: add function to allocate aligned memory in a substream cs
To use with texture states that need alignment (texconst, sampler, border)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-05 22:12:29 -05:00
Timothy Arceri
1abca2b3c8 glsl/nir: iterate the system values list when adding varyings
Iterate the system values list when adding varyings to the program
resource list in the NIR linker. This is needed to avoid CTS
regressions when using the NIR to build the GLSL resource list in
an upcoming series. Presumably it also fixes a bug with the current
ARB_gl_spirv support.

Fixes: ffdb44d3a0 ("nir/linker: Add inputs/outputs to the program resource list")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-12-05 22:04:31 +00:00
Dave Airlie
201ed4b4e7 llvmpipe: enable support for primitives generated outside streamout
This enables the draw support when the queries are enabled.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-06 06:48:30 +10:00
Dave Airlie
5f8af9731e draw: add support for collecting primitives generated outside streamout
GL/gallium require gathering primitives generated outside streamout
stats. This introduces the draw interfaces to enabling collecting this.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-06 06:48:30 +10:00
Dave Airlie
f137672197 llvmpipe: disable occlusion queries when requested by state tracker
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-06 06:48:30 +10:00
Dave Airlie
3b8e1b3ee4 llvmpipe: add queries disabled flag
This flag is set when the state tracker request queries
be disabled for meta operations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-12-06 06:48:30 +10:00
Kenneth Graunke
ef893db468 main: Change u_mmAllocMem align2 from bytes (old API) to bits (new API)
The main and Gallium implementations were recently merged, and the
align2 parameter in the Gallium one is in bits.  execmem.c expected
bytes still.  This led to every call here asserting.

Fixes: b6fd679a9e("mesa/main/util: moving gallium u_mm to util, remove main/mm")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
2019-12-05 21:07:09 +01:00
Eric Anholt
3097efe5f0 ci: Disable egl_ext_device_drm tests in piglit.
If the runner has a HW device that would be supported, even without
/dev/dri forwarded into the container, it will be enumerated and the tests
on llvmpipe fail with (for example):

libEGL warning: Not allowed to force software rendering when API explicitly selects a hardware device.
libEGL warning: MESA-LOADER: failed to open i965 (search paths /builds/anholt/mesa/install/lib/dri)

Given that we can't necessarily control the DRI devices present on the
runners (particularly for developers bringing their own runners to reduce
the demands on fd.o's shared resources), just skip these tests in CI.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-12-05 18:06:10 +00:00
Jason Ekstrand
752196a493 util/atomic: Add p_atomic_add_return for the unlocked path
Fixes: 385d13f26d "util/atomic: Add a _return variant of p_atomic_add"
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-12-05 11:55:21 -06:00
Jason Ekstrand
1b6991ba1d anv: Implement VK_KHR_buffer_device_address
The primary difference between the KHR and EXT versions of the extension
is that the KHR provides the address at AllocateMemory time for replay
so we can replay it safely without moving to a sparse address model.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
4428cd9127 anv: Use a pNext loop in AllocateMemory
This function has a lot of possible extensions and some of them we can
easily handle on-the-fly so it's easier to just have a loop than to find
each structure manually.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
a8e59b3708 anv: Add allocator support for client-visible addresses
When a BO is flagged as having a client visible address, we put it in
its own heap.  We also support the client explicitly specifying an
address in said heap.  If an address collision happens, we return false
from anv_vma_alloc which turns into a VK_ERROR_OUT_OF_DEVICE_MEMORY.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
96e3328ac2 util/vma: Add a function to allocate a particular address range
This new function lets you request to remove a specific address range
from the allocator.  It returns true on success and leaves the allocator
unmodified and returns false on failure.  It doesn't need to return an
offset because, if it succeeds, the offset passed in is the allocated
offset.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
782fb5407d util/vma: Factor out the hole splitting part of util_vma_heap_alloc
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
03450e9cfc anv: Add an explicit_address parameter to anv_device_alloc_bo
We already have a mechanism for specifying that we want a fixed address
provided by the driver internals.  We're about to let the client start
specifying addresses in some very special scenarios as well so we want
to pass this through to the allocation function.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
597fdb9e21 anv: Stop advertising two heaps just for the VF cache WA
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
b47bc0202a anv: Set up VMA heaps independently from memory heaps
Our VMA allocations are really independent from the memory heaps we
expose via the API.  The only thing that really matters is the GTT size
so we can make the high heap the right size.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
1037b52cf4 anv: Stop tracking VMA allocations
util_vma_heap_alloc will already return 0 if it doesn't have enough
space.  The only thing the vma_*_available tracking was doing was
preventing us from allocating too much on any given heap.  Now that
we're tracking that in the heap itself, we can drop these.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
a4e3d8f0db anv: Disallow allocating above heap sizes
We're already tracking the amount of memory used in each heap.  This
commit just makes us start rejecting memory allocations if the heap
would grow too large.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
385d13f26d util/atomic: Add a _return variant of p_atomic_add
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
0a36fafa95 anv: Don't leak when set_tiling fails
Fixes: a44744e01d "anv: Require a dedicated allocation for..."
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
46af0ecc1d anv: Use PIPE_CONTROL flushes to implement the gen8 VF cache WA
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
1b5cb92b62 anv: Apply cache flushes after setting index/draw VBs
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
7ce39a55c1 anv: Always invalidate the VF cache in BeginCommandBuffer
I think the reason why we only do this for primaries is that we didn't
expect to have blorp calls in secondaries.  However, you are allowed to
have a full render pass in a secondary command buffer so resolves and
clears can end up in there.  We should just always invalidate.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
a500a6b7f1 blorp: Pass the VB size to the VF cache workaround
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
c142a40a92 anv: Add a has_softpin boolean
This separates "has" from "use" which will make the next commit a bit
cleaner.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:59:10 -06:00
Jason Ekstrand
0bba88081b anv: Drop bo_flags from anv_bo_pool
In ee77938733, we started using the BO cache for anv_bo_pool and
stopped using the bo_flags parameter.  However, we never dropped it from
the struct or the init function.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 10:58:14 -06:00
Michel Dänzer
f6a913bb95 glsl/tests: Use splitlines() instead of strip()
strip() removes leading and trailing newlines, but leaves newlines
between multiple lines in the string. This could cause failures when
comparing the output of cross-compiled Windows binaries (producing
Windows-style newlines) to the expected output with Unix-style newlines.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-12-05 12:31:17 +01:00
Mauro Rossi
96aef08dc6 android: radeonsi: fix build after vl refactoring (v2)
vl functions moved from radeonsi to gallium/auxiliary/vl have left
android build of radeonsi in broken state.

libmesa_galliumvl static is need to build readeonsi,
gallium_dri building rules are reworked to avoid multiple symbols
and libmesa_galliumvl static dependency is needed in radeonsi.

Here is the changelog:
- android: gallium/auxiliary: add libmesa_galliumvl static
- android: gallium_dri: move libmesa_gallium to static to prevent multiple symbols
- android: radeonsi: fix build after vl refactoring

Fixes the following building error:

external/mesa/src/gallium/drivers/radeonsi/si_uvd.c:47:
error: undefined reference to 'vl_video_buffer_create_as_resource'
clang.real: error: linker command failed with exit code 1 (use -v to see invocation)

Fixes: 86e60bc ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-05 08:08:23 +00:00
Tapani Pälli
32ebd4207a intel/compiler: force simd8 when dual src blending on gen8
Patch introduces option to force simd8 and uses it as a workaround for
dual source blending issues seen with skqp (skia testsuite) on gen8.

Fixes following Piglit test on gen8 platforms:
   arb_blend_func_extended-dual-src-blending-issue-1917

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
c: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 09:42:50 +02:00
Tapani Pälli
f6004bac1f intel/compiler: add newline to limit_dispatch_width message
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-05 08:13:58 +02:00
Eric Anholt
c3efeac4c6 turnip: Add support for compute shaders.
Since compute shares the FS state with graphics, we have to re-upload the
pipeline state when switching between compute dispatch and graphics draws.
We could potentially expose graphics and compute as separate queues and
then we wouldn't need pipeline state management, but the closed driver
exposes a single queue and consistency with them is probably good.

So far I'm emitting texture/ibo state as IBs that we jump to.  This is
kind of silly when we could just emit it directly in our CS, but that's a
refactor we can do later.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
ccf8230547 turnip: Move pipeline BO list adding to BindPipeline.
We only need to do it once when we bind, rather than having to check at
every draw call.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
e26962f756 turnip: Sanity check that we're adding valid BOs to the list.
I tripped over this during CS enabling when my program BO wasn't set up.
Easier to debug this way than the kernel telling us a 0 handle is invalid.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
4365e955d8 turnip: Add a helper function for getting tu_buffer iovas.
Easier than remembering to add all 3 offsets.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
70d6428be5 turnip: Refactor the graphics pipeline create implementation.
The loop over the pipelines to create (and the failure handling) was
noisy, and the stub for compute setup looked nicer to me.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
e46da7dbea turnip: Add basic SSBO support.
This is enough to pass
dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_buffer.fragment.single_descriptor.*
with fragmentStoresAndAtomics set, and thus to be able to start working on
compute.  I haven't enabled that flag yet, because it also implies image
load/store support, which I haven't filled in.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
1f4e8f3c46 turnip: Reuse tu6_stage2opcode() more.
A bit of cleanup for adding more stages later.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
5b23671f6a turnip: Drop redefinition of VALIDREG now that it's in ir3.h.
Fixes: 937b905569 ("freedreno/ir3: fix neverball assert in case of unused VS inputs")

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Eric Anholt
bb49f19c1b turnip: Fix unused variable warnings.
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-12-04 20:32:15 -08:00
Timothy Arceri
1b1b436fa7 glsl: make use of active_shader_mask when building resource list
This allows us to avoid walking the entire IR looking for used
uniforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-12-05 13:18:30 +11:00
Timothy Arceri
f0cb0fe1c0 glsl: don't set uniform block as used when its not
The spec requires unused uniform block to be set as active in the
program resource list. To support this we tell opt dead code not to
remove them. However we can mark them as unused internally and
avoid unnecessarily state changes.

This change is also required for the folowing clean-up patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-12-05 13:18:23 +11:00
Timothy Arceri
50dc4b77f6 glsl: move calculate_array_size_and_stride() to link_uniforms.cpp
This is where all the other uniform values are populated so it
makes much more sense here. Moving it will also allow us to better
share code between the NIR and GLSL IR resource list builders.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-12-05 13:18:02 +11:00
Ian Romanick
c9acf0739f anv: Fix error message format string
See also 246261f0ad

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
CID: 1455892
Fixes: 246261f0ad ("anv: prepare the driver for delayed submissions")
2019-12-04 15:34:03 -08:00
Ian Romanick
7840985609 mesa: Silence unused parameter warning
Unused since e4da8b9c33 ("mesa/compiler: rework tear down of
builtin/types").

src/mesa/main/context.c: In function ‘_mesa_free_context_data’:
src/mesa/main/context.c:1321:54: warning: unused parameter ‘destroy_compiler_types’ [-Wunused-parameter]
 1321 | _mesa_free_context_data(struct gl_context *ctx, bool destroy_compiler_types)
      |                                                      ^

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-12-04 15:34:03 -08:00
Ian Romanick
a7e607641a mesa: Silence 'left shift of negative value' warning in BPTC compression code
src/util/format/../../mesa/main/texcompress_bptc_tmp.h:830:31: warning: left shift of negative value [-Wshift-negative-value]
  830 |       value |= (~(int32_t) 0) << n_bits;
      |                               ^~

v2: Rewrite to just shift left then shift right.  Based on conversation
with Neil in
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2792#note_320272,
this should be fine.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> [v1]
Reviewed-by: Neil Roberts <nroberts@igalia.com>
2019-12-04 15:34:03 -08:00
Ian Romanick
668635abd2 intel/compiler: Fix 'comparison is always true' warning
Without looking at the assembly or something, I'm not sure what the
compiler does here.  The brw_reg_type enum is marked packed, so I'm
guess that it gets represented as a uint8_t.  That's the only reason I
could think that comparing with -1 would be always true.

This patch adds the same cast that exists in brw_hw_type_to_reg_type.
It might be better to add a #define outside the enum for
BRW_REGISTER_TYPE_INVALID as (enum brw_reg_type)-1.

src/intel/compiler/brw_eu_compact.c: In function ‘has_immediate’:
src/intel/compiler/brw_eu_compact.c:1515:20: warning: comparison is always true due to limited range of data type [-Wtype-limits]
 1515 |       return *type != -1;
      |                    ^~
src/intel/compiler/brw_eu_compact.c:1518:20: warning: comparison is always true due to limited range of data type [-Wtype-limits]
 1518 |       return *type != -1;
      |                    ^~

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
CID: 1455194
Fixes: 12d3b11908 ("intel/compiler: Add instruction compaction support on Gen12")
Cc: @mattst88
2019-12-04 15:34:03 -08:00
Dylan Baker
5b3d6979a6 docs: Update mesa 19.3 release calendar 2019-12-04 14:42:41 -08:00
Dylan Baker
953d20e6f5 docs: update calendar, add news item and link release notes for 19.2.7 2019-12-04 14:42:41 -08:00
Dylan Baker
bd518aa208 docs: Add SHA256 sums for 19.2.7 2019-12-04 14:42:41 -08:00
Dylan Baker
26aa024cdf docs: Add release notes for 19.2.7 2019-12-04 14:42:41 -08:00
Jonathan Marek
ec28714b78 turnip: allow writes to draw_cs outside of render pass
This is for state commands like CmdSetViewport that can be used outside of
a renderpass. Accumulating those into draw_cs outside of the renderpass
should have the desired effect.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 17:35:18 -05:00
Rob Clark
372ed42d22 nir/lower_clip: Fix incorrect driver loc for clipdist outputs
Somehow adjusting maxloc based on existing outputs got lost, resulting
in the clipdist varying clobbering the position varying.  Causing a
shader that had no position output in freedreno/ir3, which triggers GPU
hangs in neverball.

Fixes: d0f746b645 ("nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-04 13:08:52 -08:00
Rob Clark
937b905569 freedreno/ir3: fix neverball assert in case of unused VS inputs
The logic to ensure VS and BS inputs are aligned wasn't accounting for
unused inputs in VS.  This *usually* doesn't happen, but it seems it
can in the case of ARB programs?

Fixes assert:
```
fd6_program_create: Assertion `bs->inputs[i].regid == vs->inputs[i].regid' failed.
```

Fixes: 882d53d8e3 ("freedreno/ir3+a6xx: same VBO state for draw/binning")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-04 13:08:52 -08:00
Rob Clark
4e47c205b9 freedreno/ir3: remove store_output lowered to store_shared_ir3
Fixes crashes that were unnoticed in CI because debug_assert() was not
enabled (but become real crashes after the next patch):

dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_highp_geometry
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_lowp_geometry
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_mediump_geometry
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_highp_geometry
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_lowp_geometry
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec2_mediump_geometry

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-12-04 13:08:52 -08:00
Rafael Antognolli
50f60d69e4 iris: Add restriction to 3DSTATE_CONSTANT_ packets.
The following programming note shows up in all 3DSTATE_CONSTANT_*
packets:

   "The sum of all four read length fields must be less than or equal to
   the size of 64."

The backend compiler should guarantee this for us, so let's just add a
check here.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
d3e339364f anv: Use 3DSTATE_CONSTANT_ALL when possible.
Use this new instruction introduced in Gen12. The instruction itself is
smaller, and it also allows us to emit a single instruction to all
stages that have the same push constant buffers (e.g. when they don't
have constant buffers).

There's one restriction to use this instruction, though: the length
field is only 5 bits long, so we need to check whether we can use it,
and fallback to the old 3DSTATE_CONSTANT_XS if that field is >= 32.

v2:
 - Rebased on top of the lasted changes from Jason.
 - Added review suggestions by Caio.
 - Removed struct push_bos and merged some code into
 anv_nir_compute_push_layout().

v3:
 - Remove code churn due to gen8+ workaround in
 anv_nir_compute_push_layout(). This code has been removed in an earlier
 commit, and implemented in cmd_buffer_emit_push_constant().

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
7d5da53d27 anv: Move code for emitting push constants into its own function.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
67d2cb3e93 anv: Add get_push_range_address() helper.
Add a helper function to get the push range address. Once we have a
separate function for emitting gen12 push constants, we can use this
helper and avoid duplicating code.

v3: Do not add range->start to the address in gen7 (Caio).
v4: Do not drop range->start from gen7 (Caio, Jason).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
c0225a728e anv: Move gen8+ push constant packet workaround.
Store push_ranges in ascending order, and only "shift" them to the end
of the array during state packet emission.

We don't need this workaround with the new 3DSTATE_CONSTANT_ALL packet.
So instead of applying the workaround here just for GEN < 12 (which
requires and extra loop through all the ranges to figure out if we
should shift them or not), we simply move the whole logic to the state
emission code. At that point, in a later commit, we are already looping
through all of the ranges anyway to check which packet we will be using,
so we might as well implement the workaround there, where it is going to
be used.

v3: Move gen8+ workaround to the state emission code (Caio).
v4: Add explanation of why we moved the workaroudn (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
06438ea7fa iris: Use 3DSTATE_CONSTANT_ALL when possible.
Use this new instruction introduced in Gen12. The instruction itself is
smaller, and it also allows us to emit a single instruction to all
stages that have the same push constant buffers (e.g. when they don't
have constant buffers).

There's one restriction to use this instruction, though: the length
field is only 5 bits long, so we need to check whether we can use it,
and fallback to the old 3DSTATE_CONSTANT_XS if that field is >= 32.

v2 (Suggestions from Caio):
 - use max_length instead of large_buffers.
 - remove UNUSED and use #if GEN_GEN >= 12 instead.
 - inline "buffers" and drop BITSET_RANGE() usage.
 - add assert(n <= max_pointers)
 - move emit to outside of the loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
1ba9a18911 iris: Rework push constants emitting code.
Split into a function the logic to gather the push constant buffers,
which now stores them in struct push_bos. Another function is added to
emit the packet, using data from the push_bos struct.

This will be useful when adding a new function for emitting push
constants for newer platforms.

v2 (Suggestions from Caio):
   - rename 'n' -> 'buffer_count'
   - remove large_buffers (for now)
   - initialize push_bos
   - remove assert
   - change for() condition (i <= 3 -> i < 4)
v3:
   - Add comment about size limit.
   - Rework "shift" logic and 'for' loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
9db044792f intel/blorp: Use 3DSTATE_CONSTANT_ALL to setup push constants.
In blorp, all the push constants are disabled, so we only need to emit a
single 3DSTATE_CONSTANT_ALL with the bitmask for stage update
appropriately set.

v2: Update comment (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
8983622995 intel/aubinator: Decode 3DSTATE_CONSTANT_ALL.
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-04 20:48:25 +00:00
Rafael Antognolli
2d127614a2 intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-12-04 20:48:25 +00:00
Jonathan Marek
1576ff5fbb turnip: MSAA resolve directly from GMEM
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 14:39:06 -05:00
Jonathan Marek
abaaf0b2e7 turnip: don't set unused BLIT_DST_INFO bits for GMEM clear
These bits are ignored when clearing so don't bother setting them.

Note: MSAA samples when clearing comes from other registers (tu6_emit_msaa)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 14:39:06 -05:00
Jonathan Marek
4babdc7381 turnip: implement CmdClearAttachments
Passes these deqp tests: dEQP-VK.api.image_clearing.core.*attach*single*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 14:39:06 -05:00
Jonathan Marek
1dfa2e6c99 turnip: don't skip unused attachments when setting up tiling config
This makes it easier to find the gmem_offset associated with an attachment.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 14:39:06 -05:00
Vasily Khoruzhick
8c12f4e5f2 lima: enable tiling
Now that we have tiled format modifier merged into linux we can enable tiling.

That should improve overall performance and also workaround broken mipmapping
for linear textures since now we prefer tiled textures.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-12-04 08:20:56 -08:00
Tapani Pälli
272ef5d39a glsl: additional interface redeclaration check for SSO programs
Patch adds additional linker check for SSO programs to make sure they
are redeclaring built-in blocks as required by the desktop spec.

This fixes following Piglit tests:
   arb_separate_shader_objects/linker/pervertex-*

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-12-04 15:27:41 +00:00
Tapani Pälli
2d26cc077d gitlab-ci: bump piglit checkout commit
Commit also updates the Piglit quick_gl.txt, list modifications happened
due to following Piglit commits: c248bf201,c acff58ca, 5603e2e60.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-12-04 15:27:41 +00:00
Rhys Perry
3e67aa2e4e nir/load_store_vectorize: fix combining stores with aliasing loads between
v2: add test

Fixes: ce9205c03b ('nir: add a load/store vectorization pass')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v2)
2019-12-04 12:21:40 +00:00
Timur Kristóf
637c5a1dd9 aco/wave32: Fix reductions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
21db083504 aco/wave32: Allow setting the subgroup ballot size to 64-bit.
Previously, it would only work when the ballot size was set to the
lane mask. This patch makes is possible to set the ballot size
to either 32-bit or 64-bit for wave32 mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
ed815d503e aco/wave32: Use wave_size for barrier intrinsic.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
b8f2edb452 aco/wave32: Fix load_local_invocation_index to support wave32.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
e0bcefc3a0 aco/wave32: Use lane mask regclass for exec/vcc.
Currently all usages of exec and vcc are hardcoded to use s2 regclass.
This commit makes it possible to use s1 in wave32 mode and
s2 in wave64 mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
b4efe179ed aco/wave32: Add wave size specific opcodes to aco_builder.
Several places in ACO we use SOP1 or SOP2 instructions to operate over the
exec mask or VCC, and these need to be adapted to the new size in wave32
mode.

This commit adds a way to deal with this problem in aco_builder: the caller
can specify a wave size specific opcode and the builder will translate that
to the correct opcode based on the current wave size.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
c44af6cbc7 aco/wave32: Introduce emit_mbcnt which takes wave size into account.
This is relevant because in wave32 mode the v_mbcnt_hi_u32_b32
instruction is superfluous.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
07754a9c9e aco/wave32: Replace hardcoded numbers in spiller with wave size.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
c0dbf42a03 aco/wave32: Change uniform bool optimization to work with wave32.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
dd9dad731b aco: Optimize load_subgroup_id to one bit field extract instruction.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
753670e902 aco: Remove lower_linear_bool_phi, it is not needed anymore.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
0d2d672020 aco: Remove superfluous argument from emit_boolean_logic.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Timur Kristóf
9a43d26b74 aco: Fix operand of s_bcnt1_i32_b64 in emit_boolean_reduce.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-04 10:36:01 +00:00
Michel Dänzer
5585b8eadd gitlab-ci: Run piglit glslparser & quick_shader tests separately
And only use --process-isolation false for the quick_gl tests.

This will hopefully avoid variance in the test results that we've been
seeing lately. But even if it doesn't, it should at least help narrow
down the cause of the variance.

Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-04 10:36:33 +01:00
Lionel Landwerlin
ddacd3d43b intel/perf: fix improper pointer access
This expression was unused by the macro, probably why it didn't
register in the compilation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 09:21:15 +00:00
Lionel Landwerlin
8c0b058263 intel/perf: simplify the processing of OA reports
This is a more accurate description of what happens in processing the
OA reports.

Previously we only had a somewhat difficult to parse state machine
tracking the context ID.

What we really only need to do to decide if the delta between 2
reports (r0 & r1) should be accumulated in the query result is :

   * whether the r0 is tagged with the context ID relevant to us

   * if r0 is not tagged with our context ID and r1 is: does r0 have a
     invalid context id? If not then we're in a case where i915 has
     resubmitted the same context for execution through the execlist
     submission port

v2: Update comment (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 09:21:15 +00:00
Lionel Landwerlin
b364e920bf intel/perf: take into account that reports read can be fairly old
If we read the OA reports late enough after the query happens, we can
get a timestamp in the report that is significantly in the past
compared to the start timestamp of the query. The current code must
deal with the wraparound of the timestamp value (every ~6 minute). So
consider that if the difference is greater than half that wraparound
period, we're probably dealing with an old report and make the caller
aware it should read more reports when they're available.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 09:21:15 +00:00
Lionel Landwerlin
9d0a5c817c intel/perf: set read buffer len to 0 to identify empty buffer
We always add an empty buffer in the list when creating the query.
Let's set the len appropriately so that we can recognize it when we
read OA reports up to the end of a query.

We were using an 0 timestamp value associated with the empty buffer
and incorrectly assuming this was a valid value. In turn that led to
not reading enough reports and resulted in deltas added to our counter
values which should have been discarded because those would be flagged
for a different context.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 09:21:15 +00:00
Lionel Landwerlin
acea59dbf8 intel/perf: fix invalid hw_id in query results
Accumulation happens between 2 reports, it can be between a start/end
report from another context. So only consider updating the hw_id of
the results when it's not already valid and that we have a valid value
to put in there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 41b54b5faf ("i965: move OA accumulation code to intel/perf")
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 09:21:15 +00:00
Pierre-Eric Pelloux-Prayer
a7bbebcfb9 radeonsi: display cs blit count for AMD_DEBUG=testdma
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-04 09:08:28 +01:00
Pierre-Eric Pelloux-Prayer
082d1c1686 radeonsi: implement sdma for GFX9
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-04 09:08:28 +01:00
Samuel Pitoiset
4cacba0c86 radv/gfx10: fix the vertex order for triangle strips emitted by a GS
My fix wasn't totally correct as pointed out by Marek.
Ported from RadeonSI.

Fixes: deafe4cc58 ("radv/gfx10: fix primitive indices orientation for NGG GS")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-04 08:28:57 +01:00
Samuel Pitoiset
dac6bd29ae radv: simplify a check in radv_fixup_vertex_input_fetches()
The number of loaded channels should always be > 0 now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-04 08:04:05 +01:00
Samuel Pitoiset
3b51259f06 radv: remove dead shader input/output variables
No pipeline-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-04 08:04:05 +01:00
Jason Ekstrand
0604768ae4 iris: Stop setting up fake params
In d1c4e64a69, we added a parameter to tell the back-end compiler to
ignore the param array and just push however many constants you ask it
to push.  Iris doesn't want to push anything so it gives a bogus number
of parameters and trusts the back-end compiler to dead-code all of them.
Now that we can tell the back-end compiler to stop re-arranging things,
delete the hack and enable the new simpler code path.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-12-04 04:52:20 +00:00
Dave Airlie
713636766d gallium/scons: fix graw-xlib build on OSX.
Fixes: 44a6b0107b (gallivm: add nir->llvm translation (v2))

Tested-by: Vinson Lee <vlee@freedesktop.org>
2019-12-04 13:24:44 +10:00
Dave Airlie
3263c9824e llvmpipe: enable texcoord semantics
To make NIR transitioning easier, move the driver to using
texcoord semantics.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-04 12:08:14 +10:00
Jason Ekstrand
178a2946c0 anv: Respect the always_flush_cache driconf option
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-03 17:10:51 -06:00
Krzysztof Raszkowski
07adc47460 gallium/swr: Fix crash when use GL_TDFX_texture_compression_FXT1 format.
Reject the new formats in swr to prevent crashes because it doesn't
know how to handle the new formats.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-12-03 16:51:24 +00:00
Rob Clark
b31637c453 gitlab-ci: disable junit results for deqp
They don't seem to be hugely useful, and seem to be bogging down gitlab.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-12-03 08:46:39 -08:00
Jason Ekstrand
b1f37688ba anv: Set up SBE_SWIZ properly for gl_Viewport
gl_Viewport is also in the VUE header so we need to whack the read
offset to 0 and emit a default (no overrides) SBE_SWIZ entry in that
case as well.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-12-03 16:20:50 +00:00
Michel Dänzer
0c88d5952a gitlab-ci: Update to current ci-templates master
Fixes skopeo copy failures.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-03 16:03:31 +01:00
Samuel Pitoiset
f63a3132e8 ac/llvm: fix atomic var operations if source isn't a deref
Fixes some CTS regressions.

Fixes: e61a826f39 ("ac/llvm: fix pointer type for global atomics")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-03 09:41:33 +01:00
Neil Armstrong
dde734030b Add support for T820 CI Jobs
Tomeu: - Small rebase fixups

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-03 06:44:08 +01:00
Dave Airlie
502548a09c gallivm/llvmpipe: add support for front facing in sysval.
This wires up the front facing value as a sysval, I'd like to
remove the other facing code but I'd need to confirm VMware
don't use it first.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-03 15:29:04 +10:00
Dave Airlie
f52cdaa517 llvmpipe/images: handle undefined atomic without crashing
just return 0 for unbound atomic operations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-03 15:29:04 +10:00
Alyssa Rosenzweig
71dd52e056 panfrost: Remove blend shader hack
This is no longer used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Tomeu Vizoso
c707b4d0f9 gitlab-ci: Test Panfrost on T720 GPUs
Now that the Mali T720 GPU is supoprted at the same level as the T760,
test it on PINE64 H64 boards.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Alyssa Rosenzweig
6d05e38a96 gitlab-ci: Remove non-default skips from Panfrost
During the past months, Panfrost has matured considerably and several
tests stopped being flaky or failing at all.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Tomeu Vizoso
b655be7252 panfrost: White list the Mali T720
Support for this GPU is equal now to that of T760, so whitelist it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Alyssa Rosenzweig
8555bffafd pan/midgard: Splatter on fragment out
Make sure that the fragment is complete when writing it out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-03 04:25:04 +00:00
Tomeu Vizoso
ab81a23d36 panfrost: Simplify shader patching
We need to always upload anyway.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Alyssa Rosenzweig
6ddaa5558a panfrost: Simplify draw_flags
Fixes dEQP-GLES3.functional.primitive_restart.*. Note the 0x18000 value
is accidentally somehow enabling primitive restart for some reason.
I'm not sure where this value came from but let's not.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-03 04:25:04 +00:00
Alyssa Rosenzweig
9fb0904712 panfrost: Implement pan_tiler for non-hierarchy GPUs
The algorithm is as described. Nothing fancy here, just need to add some
new code paths depending on which model we're running on.

Tomeu:
- Also disable tiling when !hierarchy and !vertex_count
- Avoid creating polygon lists smaller than the minimum when
  vertex_count > 0 but tile size smaller than 16 byte
- Take into account tile size when calculating polygon list size for
  !hierarchy
- Allow 0-sized tiles in a single dimension

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-03 04:25:04 +00:00
Alyssa Rosenzweig
63cd5b8198 panfrost: Add information about T720 tiling
We've figured out most of the big pieces, and though it looks faintly
like other Midgards, it's much simpler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-12-03 04:25:04 +00:00
Tomeu Vizoso
6887ff4e79 panfrost: Add quirks system to cmdstream
Similarly to how it's already done in the compiler, add a way to express
differences between GPU models that need to be taken into account when
assembling the cmdstream.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-12-03 04:25:04 +00:00
Ian Romanick
fbd5359a0a nir/algebraic: Rearrange bcsel sequences generated by nir_opt_peephole_select
Reviewed-by: Matt Turner <mattst88@gmail.com>

All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14660366 -> 14653437 (-0.05%)
instructions in affected programs: 316166 -> 309237 (-2.19%)
helped: 905
HURT: 10
helped stats (abs) min: 1 max: 36 x̄: 7.67 x̃: 6
helped stats (rel) min: 0.13% max: 18.75% x̄: 4.28% x̃: 3.60%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.10% max: 1.33% x̄: 0.70% x̃: 0.97%
95% mean confidence interval for instructions value: -7.91 -7.23
95% mean confidence interval for instructions %-change: -4.46% -3.99%
Instructions are helped.

total cycles in shared programs: 228571646 -> 228549759 (<.01%)
cycles in affected programs: 56239919 -> 56218032 (-0.04%)
helped: 681
HURT: 216
helped stats (abs) min: 1 max: 5156 x̄: 45.49 x̃: 10
helped stats (rel) min: <.01% max: 10.45% x̄: 1.29% x̃: 0.65%
HURT stats (abs)   min: 1 max: 320 x̄: 42.09 x̃: 14
HURT stats (rel)   min: <.01% max: 37.04% x̄: 1.38% x̃: 0.49%
95% mean confidence interval for cycles value: -41.51 -7.29
95% mean confidence interval for cycles %-change: -0.80% -0.49%
Cycles are helped.

LOST:   1
GAINED: 0
2019-12-02 16:46:20 -08:00
Ian Romanick
780b5c1037 nir/algebraic: Simplify some Inf and NaN avoidance code
Since a is non-negative, neither fsqrt nor frsq should return NaN.  frsq
should only return Inf when fsqrt returns 0.

The changes are pretty small, but this turns a few hundred hurt shaders
in the next patch into helped shaders.

An alternative to the intBitsToFloat is to import numpy and do
np.finfo(np.float32).max.  That's more explicit, but we may also want to
have specific bit encodings of float values later.  I could be convinced
either way, but intBitsToFloat(0x7f7fffff) was what I implemented first.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

All Gen7+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14661140 -> 14661104 (<.01%)
instructions in affected programs: 7520 -> 7484 (-0.48%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.32% max: 0.61% x̄: 0.49% x̃: 0.52%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.52% -0.47%
Instructions are helped.

total cycles in shared programs: 228585416 -> 228584806 (<.01%)
cycles in affected programs: 56321 -> 55711 (-1.08%)
helped: 32
HURT: 0
helped stats (abs) min: 2 max: 98 x̄: 19.06 x̃: 10
helped stats (rel) min: 0.08% max: 6.41% x̄: 1.09% x̃: 0.65%
95% mean confidence interval for cycles value: -28.32 -9.80
95% mean confidence interval for cycles %-change: -1.63% -0.54%
Cycles are helped.

Sandy Bridge
total cycles in shared programs: 152991077 -> 152991075 (<.01%)
cycles in affected programs: 11525 -> 11523 (-0.02%)
helped: 2
HURT: 2
helped stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.07% max: 0.11% x̄: 0.09% x̃: 0.09%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.08% max: 0.08% x̄: 0.08% x̃: 0.08%
95% mean confidence interval for cycles value: -5.27 4.27
95% mean confidence interval for cycles %-change: -0.16% 0.15%
Inconclusive result (value mean confidence interval includes 0).

No changes on Iron Lake or GM45.
2019-12-02 16:46:20 -08:00
Ian Romanick
d15344c0f5 intel/compiler: Increase nir_opt_peephole_select threshold
I tried 2, 4, 6, 8, and 10.  8 seemed to be the sweet spot across all
Intel platforms.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

All Gen7+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14736141 -> 14661140 (-0.51%)
instructions in affected programs: 2272413 -> 2197412 (-3.30%)
helped: 8416
HURT: 140
helped stats (abs) min: 1 max: 1152 x̄: 8.99 x̃: 6
helped stats (rel) min: 0.13% max: 42.55% x̄: 4.15% x̃: 3.20%
HURT stats (abs)   min: 1 max: 140 x̄: 4.73 x̃: 1
HURT stats (rel)   min: 0.03% max: 3.44% x̄: 0.87% x̃: 0.60%
95% mean confidence interval for instructions value: -9.36 -8.17
95% mean confidence interval for instructions %-change: -4.14% -3.99%
Instructions are helped.

total cycles in shared programs: 231560416 -> 228585416 (-1.28%)
cycles in affected programs: 126536021 -> 123561021 (-2.35%)
helped: 7092
HURT: 1898
helped stats (abs) min: 1 max: 419320 x̄: 519.02 x̃: 159
helped stats (rel) min: <.01% max: 77.25% x̄: 13.52% x̃: 11.77%
HURT stats (abs)   min: 1 max: 14518 x̄: 371.91 x̃: 36
HURT stats (rel)   min: <.01% max: 103.23% x̄: 5.92% x̃: 2.55%
95% mean confidence interval for cycles value: -514.34 -147.50
95% mean confidence interval for cycles %-change: -9.69% -9.14%
Cycles are helped.

total spills in shared programs: 5763 -> 5848 (1.47%)
spills in affected programs: 1797 -> 1882 (4.73%)
helped: 13
HURT: 13

total fills in shared programs: 17163 -> 16931 (-1.35%)
fills in affected programs: 7214 -> 6982 (-3.22%)
helped: 22
HURT: 19

total sends in shared programs: 730410 -> 730246 (-0.02%)
sends in affected programs: 2705 -> 2541 (-6.06%)
helped: 114
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 1.44 x̃: 1
helped stats (rel) min: 0.60% max: 20.00% x̄: 7.26% x̃: 5.88%
95% mean confidence interval for sends value: -1.55 -1.33
95% mean confidence interval for sends %-change: -7.90% -6.62%
Sends are helped.

LOST:   4
GAINED: 0

Sandy Bridge
total instructions in shared programs: 10760511 -> 10724637 (-0.33%)
instructions in affected programs: 961305 -> 925431 (-3.73%)
helped: 3734
HURT: 110
helped stats (abs) min: 1 max: 151 x̄: 9.66 x̃: 8
helped stats (rel) min: 0.14% max: 41.21% x̄: 4.93% x̃: 3.95%
HURT stats (abs)   min: 1 max: 20 x̄: 1.68 x̃: 1
HURT stats (rel)   min: 0.12% max: 5.41% x̄: 0.88% x̃: 0.52%
95% mean confidence interval for instructions value: -9.76 -8.91
95% mean confidence interval for instructions %-change: -4.90% -4.63%
Instructions are helped.

total cycles in shared programs: 153359411 -> 152991077 (-0.24%)
cycles in affected programs: 11615401 -> 11247067 (-3.17%)
helped: 2725
HURT: 1138
helped stats (abs) min: 1 max: 2844 x̄: 164.27 x̃: 80
helped stats (rel) min: 0.02% max: 48.60% x̄: 7.47% x̃: 3.91%
HURT stats (abs)   min: 1 max: 4351 x̄: 69.69 x̃: 25
HURT stats (rel)   min: 0.02% max: 40.00% x̄: 3.39% x̃: 1.47%
95% mean confidence interval for cycles value: -103.18 -87.52
95% mean confidence interval for cycles %-change: -4.57% -3.97%
Cycles are helped.

total sends in shared programs: 584038 -> 583855 (-0.03%)
sends in affected programs: 3512 -> 3329 (-5.21%)
helped: 157
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 1.17 x̃: 1
helped stats (rel) min: 2.38% max: 25.00% x̄: 6.52% x̃: 6.06%
95% mean confidence interval for sends value: -1.26 -1.07
95% mean confidence interval for sends %-change: -7.17% -5.87%
Sends are helped.

LOST:   23
GAINED: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8122617 -> 8111592 (-0.14%)
instructions in affected programs: 380503 -> 369478 (-2.90%)
helped: 912
HURT: 86
helped stats (abs) min: 1 max: 129 x̄: 12.19 x̃: 9
helped stats (rel) min: 0.30% max: 39.21% x̄: 3.69% x̃: 2.57%
HURT stats (abs)   min: 1 max: 2 x̄: 1.05 x̃: 1
HURT stats (rel)   min: 0.12% max: 3.64% x̄: 0.54% x̃: 0.36%
95% mean confidence interval for instructions value: -12.00 -10.10
95% mean confidence interval for instructions %-change: -3.56% -3.10%
Instructions are helped.

total cycles in shared programs: 188509780 -> 188534398 (0.01%)
cycles in affected programs: 7211542 -> 7236160 (0.34%)
helped: 859
HURT: 132
helped stats (abs) min: 2 max: 690 x̄: 46.59 x̃: 16
helped stats (rel) min: 0.01% max: 26.76% x̄: 1.53% x̃: 0.33%
HURT stats (abs)   min: 2 max: 1592 x̄: 489.67 x̃: 618
HURT stats (rel)   min: 0.03% max: 185.92% x̄: 23.35% x̃: 6.26%
95% mean confidence interval for cycles value: 9.58 40.10
95% mean confidence interval for cycles %-change: 0.65% 2.93%
Cycles are HURT.
2019-12-02 16:46:20 -08:00
Ian Romanick
e342d6970b nir/opt_peephole_select: Don't count some unary operations
In many cases, fsat, fneg, fabs, ineg, and iabs will get folded into
another instruction as either source or destination modifiers.
Counting them as instructions means that some if-statements won't get
converted to selects.  For example,

        vec1 32 ssa_25 = flt32 ssa_0, ssa_23.x
        /* succs: block_1 block_2 */
        if ssa_25 {
                block block_1:
                /* preds: block_0 */
                vec1 32 ssa_26 = fabs ssa_24
                vec1 32 ssa_27 = fneg ssa_26
                vec1 32 ssa_28 = fabs ssa_20
                vec1 32 ssa_29 = fneg ssa_28
                vec1 32 ssa_30 = fmul ssa_27, ssa_29
                vec1 32 ssa_31 = fsat ssa_30
                /* succs: block_3 */
        } else {
                block block_2:
                /* preds: block_0 */
                /* succs: block_3 */
        }
        block block_3:
        /* preds: block_1 block_2 */

block_1 isn't really 6 instructions, but it will be counted that way.

Most callers of the peephole_select pass use either 1 or 8.  It's very
easy to blow way past either of these limits with things that are really
only one or two actual instructions.

I also tried some fancier things like making sure the fsat was of
another SSA def from the same block, but the simple test was actually
better.

The i965 back-end SEL peephole pass still helps ~700 shaders in
shader-db with this change.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

All Gen6+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 14743694 -> 14738910 (-0.03%)
instructions in affected programs: 156575 -> 151791 (-3.06%)
helped: 1204
HURT: 0
helped stats (abs) min: 1 max: 27 x̄: 3.97 x̃: 3
helped stats (rel) min: 0.15% max: 19.57% x̄: 5.15% x̃: 4.55%
95% mean confidence interval for instructions value: -4.12 -3.82
95% mean confidence interval for instructions %-change: -5.35% -4.95%
Instructions are helped.

total cycles in shared programs: 231749141 -> 231602916 (-0.06%)
cycles in affected programs: 2818975 -> 2672750 (-5.19%)
helped: 876
HURT: 322
helped stats (abs) min: 2 max: 788 x̄: 180.99 x̃: 220
helped stats (rel) min: <.01% max: 43.82% x̄: 20.75% x̃: 19.44%
HURT stats (abs)   min: 1 max: 1188 x̄: 38.27 x̃: 20
HURT stats (rel)   min: 0.09% max: 102.67% x̄: 5.17% x̃: 1.70%
95% mean confidence interval for cycles value: -130.47 -113.64
95% mean confidence interval for cycles %-change: -14.85% -12.72%
Cycles are helped.

total sends in shared programs: 730495 -> 730491 (<.01%)
sends in affected programs: 46 -> 42 (-8.70%)
helped: 2
HURT: 0

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8122757 -> 8122617 (<.01%)
instructions in affected programs: 14716 -> 14576 (-0.95%)
helped: 46
HURT: 1
helped stats (abs) min: 1 max: 8 x̄: 3.07 x̃: 3
helped stats (rel) min: 0.36% max: 10.00% x̄: 2.54% x̃: 1.06%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.59% max: 1.59% x̄: 1.59% x̃: 1.59%
95% mean confidence interval for instructions value: -3.42 -2.54
95% mean confidence interval for instructions %-change: -3.28% -1.62%
Instructions are helped.

total cycles in shared programs: 188510100 -> 188509780 (<.01%)
cycles in affected programs: 58994 -> 58674 (-0.54%)
helped: 32
HURT: 1
helped stats (abs) min: 2 max: 96 x̄: 10.06 x̃: 6
helped stats (rel) min: 0.05% max: 15.29% x̄: 1.37% x̃: 0.31%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.68% max: 0.68% x̄: 0.68% x̃: 0.68%
95% mean confidence interval for cycles value: -16.34 -3.06
95% mean confidence interval for cycles %-change: -2.46% -0.15%
Cycles are helped.
2019-12-02 16:46:19 -08:00
Jordan Justen
e277009d8d iris: Allow max dynamic pool size of 2GB for gen12
Reworks:
 * Adjust comment to list the state packets that curro found to be
   affected.

Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake")
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2019-12-02 16:34:12 -08:00
Marek Olšák
7730d583c2 radeonsi/gfx10: fix the vertex order for triangle strips emitted by a GS
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-02 18:22:27 -05:00
Marek Olšák
91da6a98e7 radeonsi/gfx10: simplify some duplicated NGG GS code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-02 18:22:25 -05:00
Jonathan Gray
4913215d14 util/u_thread: don't restrict u_thread_get_time_nano() to __linux__
pthread_getcpuclockid() and clock_gettime() are also available on at least
OpenBSD, FreeBSD, NetBSD, DragonFly, Cygwin.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-12-02 17:23:49 -05:00
Jonathan Gray
c91997b6c4 util/futex: use futex syscall on OpenBSD
Make use of the futex syscall added in OpenBSD 6.2.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-12-02 17:23:49 -05:00
Kenneth Graunke
dbe923bff9 meson: Add a "prefer_iris" build option
Enabling this option makes Intel Gen8-11 hardware load the 'iris'
driver by default instead of the older 'i965' driver.

Regardless of how this option is set, users can still override which
driver the loader selects via two methods.  The first is to create a
~/.drirc or /etc/drirc file with the following snippet:

   <driconf>
     <device driver="loader" kernel_driver="i915">
       <option name="dri_driver" value="i965" />
     </device>
   </driconf>

The other option is to set an environment variable:

   export MESA_LOADER_DRIVER_OVERRIDE=i965

For now, "prefer_iris" defaults to i965 (the historical choice).
A separate future patch will change the default driver to iris.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1893
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-02 12:56:27 -08:00
Jonathan Marek
bebfb17a2b turnip: fix display wsi fence timing out
Fixes: df9f2adf ("turnip: add display wsi")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-02 14:29:47 -05:00
Rhys Perry
5404b7aaa3 nir/lower_io_to_vector: don't create arrays when not needed
Some backends require that there are no array varyings.

If there were no arrays in the input shader, the pass shouldn't have to
create new ones.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2103
Fixes: bcd14756ee ('nir/lower_io_to_vector: add flat mode')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-12-02 17:45:01 +00:00
Rhys Perry
01cacdb71e aco: fix block_kind_discard s_andn2 definition to exec
Improves generated code of dEQP-VK.graphicsfuzz.disc-and-add-in-func-in-loop
because a loop exit phi can then be fixed to exec, removing copies and
improving jump threading.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-02 16:56:24 +00:00
Rhys Perry
0e8da9f607 aco: handle loop exit and IF merge phis with break/discard
ACO considers discards jumps and creates edges in the CFG for them but NIR
does neither of these.

This can be fixed instead by keeping track of whether a side of an IF had
a break/discard, but this doesn't solve the issue with discards affecting
loop exit phis. So this reworks phi handling a bit.

Fixes these tests:
dEQP-VK.graphicsfuzz.disc-and-add-in-func-in-loop
dEQP-VK.graphicsfuzz.loop-call-discard
dEQP-VK.graphicsfuzz.complex-nested-loops-and-call

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-02 16:56:19 +00:00
Rhys Perry
06fc83989c aco: validate the CFG
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-12-02 16:56:05 +00:00
Alejandro Piñeiro
b6fd679a9e mesa/main/util: moving gallium u_mm to util, remove main/mm
Right now there are two copies of mm:
   * mesa/main/mm.[ch]
   * gallium/auxiliary/util/u_mm.[ch]

At some point they splitted, and from the commit message it was not
clear why it was not possible to have only one copy at a common place.

Taking into account that was several years ago, Im assuming that it
was not possible then.

This change would allow to have one copy of the same code, and also
being able to use that code out of mesa/main or gallium, if needed.

This commit moves u_mm and removes mm, as u_mm has slightly more
changes.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-12-02 13:59:28 +01:00
Rhys Perry
35fab1ba33 radv: set writes_memory for global memory stores/atomics
Fixes: 13ab63bb62 ('radv: Implement VK_EXT_buffer_device_address.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-12-02 11:47:12 +00:00
Rhys Perry
a814f3d8a7 ac/llvm: improve sync scope for global atomics
Stronger ordering is implemented in SPIRV->NIR with barriers.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-02 10:48:27 +00:00
Rhys Perry
e61a826f39 ac/llvm: fix pointer type for global atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-12-02 10:48:18 +00:00
Kenneth Graunke
1d416ffd09 iris: Map FXT1 texture formats
This exposes GL_TDFX_texture_compression_FXT1 support.  It's ancient,
only Intel GPUs appear to support it, and I seriously doubt anybody
uses it.  But i965 supports it, and it's trivial to do, so we may as
well support it in the new iris driver as well.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-12-01 22:55:56 -08:00
Kenneth Graunke
1bdd342b60 st/mesa: Add GL_TDFX_texture_compression_FXT1 support
Eric recently added PIPE_FORMAT_FXT1_RGB[A] as part of his format
unification work.  This was really most of the work of implementing
the extension.  We just need to handle it in a couple of places and
expose the extension.

v2: Reject the new formats in llvmpipe_is_format_supported to prevent
    crashes because it doesn't know how to handle the new formats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
2019-12-01 22:55:21 -08:00
Dave Airlie
3e21e17b2f nir/samplers: don't zero samplers_used/txf.
This allows this pass to be run multiple times and the results are
just or'ed together.

It fixes on test on llvmpipe nir, and regresses none.

Suggested by Kenneth

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-02 09:15:55 +10:00
Samuel Pitoiset
0eb78a078e aco: drop useless lowering of deref operations for shared memory
Moved to RADV. No pipeline-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 21:58:25 +01:00
Samuel Pitoiset
c105e6169c radv,ac/nir: lower deref operations for shared memory
This shouldn't introduce any functional changes for RadeonSI
when NIR is enabled because these operations are already lowered.

pipeline-db (NAVI10/LLVM):
SGPRS: 9043 -> 9051 (0.09 %)
VGPRS: 7272 -> 7292 (0.28 %)
Code Size: 638892 -> 621628 (-2.70 %) bytes
LDS: 1333 -> 1331 (-0.15 %) blocks
Max Waves: 1614 -> 1608 (-0.37 %)

Found this while glancing at some F12019 shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-29 21:58:18 +01:00
Daniel Schürmann
b690543851 aco: fix a couple of value numbering issues
Fixes: 3a20ef4a32 'aco: refactor value numbering'

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-29 21:54:27 +01:00
Daniel Schürmann
8861a82be7 aco: don't split live-ranges of linear VGPRs
Fixes: 93c8ebfa78 'aco: Initial commit of independent AMD compiler'

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-29 21:54:27 +01:00
Rhys Perry
73783ed389 aco: implement global atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:02 +00:00
Rhys Perry
389ee819c0 aco: improve FLAT/GLOBAL scheduling
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:02 +00:00
Rhys Perry
cc742562c1 aco: don't enable store_global for helper invocations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:02 +00:00
Rhys Perry
31e68e230f aco: fix SADDR with FLAT on GFX10
The reference guide is incorrect and SADDR is actually used with FLAT on
GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
082e3a68fa aco: fix assembly of FLAT/GLOBAL atomics
They can take both a definition and data operand

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
f1381e6715 aco: fix GFX10 opcodes for some global/flat atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
5986e00194 aco: improve WAR hazard workaround with >64bit stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
a9fc81b098 aco: add v_nop inbetween exec write and VMEM/DS/FLAT
LLVM and the proprietary compiler seem to do this

Fixes: b01847bd9 ("aco/gfx10: Fix mitigation of VMEMtoScalarWriteHazard.")
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
54742e157d aco: fix incorrect cast in parse_wait_instr()
s_waitcnt is SOPP, not SOPK

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
11f43caaec aco: fix i2i64
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:46:01 +00:00
Rhys Perry
ff70ccad16 aco: propagate p_wqm on an image_sample's coordinate p_create_vector
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2156
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-29 17:19:52 +00:00
Christian Gmeiner
1be220833c etnaviv: remove dead code
ptiled is always NULL so the if statement is useless.

CoverityID: 1415572
Fixes: b962776530 ("etnaviv: rework compatible render base")
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-29 16:22:40 +01:00
Christian Gmeiner
1dfe6a3e9a etnaviv: handle integer case for GENERIC_ATTRIB_SCALE
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-29 15:06:18 +01:00
Christian Gmeiner
5361ea2a9b etnaviv: fix R10G10B10A2 vertex format entries
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-29 15:06:18 +01:00
Christian Gmeiner
06d7071bca etnaviv: use NORMALIZE_SIGN_EXTEND
The blob driver does something like this for all vertex formats:

if (normalize) {
   if (OPENGL_ES30)
      val = VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND;
   else
      val = VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON;
} else {
   val = VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF;
}

As there is no way to get to that information in gallium we always
assume OPENGL_ES30.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-29 15:06:18 +01:00
Christian Gmeiner
ca6c73f335 etnaviv: fix integer vertex formats
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-29 15:06:18 +01:00
Jonathan Gray
34dda0ca65 i965: update Makefile.sources for perf changes
brw_performance_query_metrics.h was removed in
134e750e16 and
brw_performance_query.h was removed in
8ae6667992

remove reference to these files from Makefile.sources

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Fixes: 134e750e16 ("i965: extract performance query metrics")
Fixes: 8ae6667992 ("intel/perf: move query_object into perf")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-29 13:20:55 +00:00
Vinson Lee
0d21fe5397 scons: Bump C standard to gnu11 on macOS 10.15.
Fix build error on macOS 10.15 Catalina.

src/util/u_queue.c:179:7: error: implicit declaration of function 'timespec_get' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
      timespec_get(&ts, TIME_UTC);
      ^

timespec_get needs C11 starting with macOS 10.15.

/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/time.h
   193	#if (__DARWIN_C_LEVEL >= __DARWIN_C_FULL) && \
   194	        ((defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \
   195	        (defined(__cplusplus) && __cplusplus >= 201703L))
   196	/* ISO/IEC 9899:201x 7.27.2.5 The timespec_get function */
   197	#define TIME_UTC	1	/* time elapsed since epoch */
   198	__API_AVAILABLE(macosx(10.15), ios(13.0), tvos(13.0), watchos(6.0))
   199	int timespec_get(struct timespec *ts, int base);
   200	#endif

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-11-29 12:38:29 +00:00
Boris Brezillon
c6e2096c47 panfrost: Make sure we reset the damage region of RTs at flush time
We must reset the damage info of our render targets here even though a
damage reset normally happens when the DRI layer swaps buffers. That's
because there can be implicit flushes the GL app is not aware of, and
those might impact the damage region: if part of the damaged portion
is drawn during those implicit flushes, you have to reload those areas
before next draws are pushed, and since the driver can't easily know
what's been modified by the draws it flushed, the easiest solution is
to reload everything.

Reported-by: Carsten Haitzler <raster@rasterman.com>
Fixes: 65ae86b854 ("panfrost: Add support for KHR_partial_update()")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-29 10:20:29 +01:00
Boris Brezillon
b196e1a8cf gallium: Fix the ->set_damage_region() implementation
BACK_LEFT attachment can be outdated when the user calls
KHR_partial_update() (->lastStamp != ->texture_stamp), leading to a
damage region update on the wrong pipe_resource object.
Let's delay the ->set_damage_region() call until the attachments are
updated when we're in that case.

Reported-by: Carsten Haitzler <raster@rasterman.com>
Fixes: 492ffbed63 ("st/dri2: Implement DRI2bufferDamageExtension")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-29 10:20:29 +01:00
Erik Faye-Lund
5fcb503c73 zink: silence coverity error
Coverity doesn't know that we always have coordinates if we have lod. To
avoid annoying errors, let's just zero-initialize this.

CoverityID: 1455202
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
7a63124a06 zink: error-check right variable
That's not the value we just allocated...

CoverityID: 1455177
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
c8769ff8dd zink: avoid NULL-deref
Same story as the previous two commits; these functions dereference the
memory they are pointed at. We can't do that.

CoverityID: 1455180
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
e54240f153 zink: avoid NULL-deref
Similar to the previous commit, pipe_resource_reference also dereference
the memory pointed at. Let's avoid it.

CoverityID: 1455198
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
bda64440e4 zink: avoid NULL-deref
zink_render_pass_reference will dereference the memory 'dst' points at,
which can't really go well. All we want to do here is to increase the
reference-count, so let's use a different helper for that instead.

CoverityID: 1455200
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
8e1dca35ab zink: handle calloc-failure
In case we fail to allocate the context, we should notice and fail
gracefully.

CoverityID: 1455193
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
8772d95d40 zink: do not try to destroy NULL-fence
destroy_fence doesn't handle NULL-pointers gracefully. So let's avoid
hitting that code-path, by simply returning NULL early here instead.

CoverityID: 1455179
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
49f53ee336 zink: delete query rather than allocating a new one
It seems I had some fat fingers when writing this function, and I
accidentally ended up allocating a new query and immediately trying to
delete an uninitialized pool instead of just deleting the pool of the
query that was passed.

CoverityID: 1455196
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:54:25 +01:00
Erik Faye-Lund
f2188e58ce zink: fix crash when restoring sampler-states
When I changed to heap-allocated sampler-objects, I missed the code-path
that restores sampler-states after the blitter; it needs an array of
pointers, not an array of VkSampler objects to behave.

This fixes spec@arb_texture_cube_map@copyteximage for me.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 5ea787950f ("zink: heap-allocate samplers objects")
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 09:19:54 +01:00
Erik Faye-Lund
655b9aa711 zink: reject invalid sample-counts
Vulkan only allows power-of-two sample counts. We already kinda checked
for this, but forgot to validate the result in the end. Let's check the
result and error properly.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 08:58:05 +01:00
Erik Faye-Lund
927363e0b9 zink: use true/false instead of TRUE/FALSE
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-11-29 08:57:33 +01:00
Erik Faye-Lund
c7c0bd9f1e st/mesa: unmap pbo after updating cache
Unmapping first leads to accessing an invalid pointer. So let's switch
these lines around.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-29 07:45:06 +00:00
Vinson Lee
de2e5f6f54 panfrost: Fix gnu-empty-initializer build errors.
Fixes: a24d6fbae6 ("meson: Add -Werror=gnu-empty-initializer to MSVC compat args")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-28 16:12:38 -08:00
Timothy Arceri
9d2d609cce docs: update source code repository documentation
This drops all the old documentaion around applying for push access.

Also this removes the documentation stating that you can push
directly to mesa rather than using merge requests.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1969

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-29 11:09:00 +11:00
Bas Nieuwenhuizen
48fc65413c radv: Fix timeline semaphore refcounting.
Was totally broken ...

Removed two if(point) {} because point is always non-NULL and we
were counting on that already for counting, since we NULL our
references to semaphores without active point earlier.

Fixes: 4aa75bb3bd "radv: Add wait-before-submit support for timelines."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2137
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-28 23:46:09 +01:00
Jonathan Gray
3fe3bde4f2 winsys/amdgpu: avoid double simple_mtx_unlock()
pthread_mutex_unlock() when unlocked is documented by posix as
being undefined behaviour.  On OpenBSD pthread_mutex_unlock() will call
abort(3) if this happens.

This occurs in amdgpu_winsys_create() after
cb446dc0fa
winsys/amdgpu: Add amdgpu_screen_winsys

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-11-28 15:03:59 -05:00
Marek Olšák
5e81fbf44a util/driconfig: print ATTENTION if MESA_DEBUG=silent is not set
unix-bytebenchmark refuses to run if the driver prints ATTENTION to stderr.

Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-11-28 14:36:32 -05:00
Tapani Pälli
d61a21f439 glsl: handle max uniform limits with lower_const_arrays_to_uniforms
Fixes arb_tessellation_shader-large-uniforms Piglit test.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-28 14:11:46 +02:00
Bas Nieuwenhuizen
4cde0e04e3 radv: Unify max_descriptor_set_size.
They were out of sync. Besides syncing, lets ensure they never diverge
again.

Fixes: 8d2654a419 "radv: Support VK_EXT_inline_uniform_block."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-28 12:06:44 +01:00
Bas Nieuwenhuizen
e09426ad6b amd/llvm: Refactor ac_build_scan.
Split out the logic for exclusive scans into a separate function
that makes clear what it does instead of having this opaque 60
line if.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-28 11:35:11 +01:00
Samuel Pitoiset
d347f2805d radv: add more constants to avoid using magic numbers
Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-28 10:59:14 +01:00
Samuel Pitoiset
52aadbfd04 ac/llvm: convert src operands to pointers if necessary
To avoid generating invalid LLVM IR when both operands don't have
the same type. This might happen when performing pointer comparisons
with SPIRV 1.4.

Fixes invalid LLVM IR for:
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrequal.variable_pointers_ssbo_equal
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrnotequal.variable_pointers_ssbo_not_equal

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-28 08:26:51 +01:00
Dave Airlie
18f896e55d llvmpipe: add initial nir support
This adds the hooks between llvmpipe and the gallivm NIR
code, for compute and fragment shaders.

NIR support is hidden behind LP_DEBUG=nir for now until
all the intergration issues are solved

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:49:23 +10:00
Dave Airlie
5363cda52b gallivm: add swizzle support where one channel isn't defined.
NIR doesn't always define all output channels
relies on outputs being memset to 0

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:49:16 +10:00
Dave Airlie
3eb27cfccd gallium: add nir lowering passes for the draw pipe stages. (v2)
This transforms the NIR shaders like the TGSI transforms worked.

v2: fix some nir info requirements, use 32-bit bools

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:49:05 +10:00
Dave Airlie
bf12bc2dd7 draw: add nir info gathering and building support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:56 +10:00
Dave Airlie
44a6b0107b gallivm: add nir->llvm translation (v2)
This add the initial implementation of the NIR->LLVM conversion
for llvmpipe NIR support.

v2: lower bool to int32 in nir not llvm

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:44 +10:00
Dave Airlie
18ed09d449 gallivm: add selection for non-32 bit types
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:38 +10:00
Dave Airlie
9461f2b5df gallivm: add cttz wrapper
this will be used to write find_lsb support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:32 +10:00
Dave Airlie
1a608901cc gallivm: add popcount intrinsic wrapper
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:25 +10:00
Dave Airlie
3b9950098b gallivm: nir->tgsi info convertor (v2)
This is a port of the old radeonsi code to be used for llvmpipe NIR support.

Once we remove TGSI support from llvmpipe (I can dream? :-), then
we should be able to refine most of this down and remove it.

v2: port to later radeonsi code for vertex inputs and sampler/io parsing.

Acked-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:48:11 +10:00
Dave Airlie
c879efec09 gallivm: split out the flow control ir to a common file.
We can share a bunch of flow control handling between NIR and TGSI.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-28 14:47:54 +10:00
Marek Olšák
754c7b8939 radeonsi: enable SPIR-V and GL 4.6 for NIR
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:35 -05:00
Marek Olšák
cf240ea6a5 radeonsi/nir: support interface output types to fix SPIR-V xfb piglits
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:34 -05:00
Marek Olšák
1b45da15a9 radeonsi/nir: fix location_frac handling for TCS outputs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:32 -05:00
Marek Olšák
268e42e4f8 radeonsi/nir: don't rely on data.patch for tess factors
GLCTS SPIR-V tests have this issue.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:30 -05:00
Marek Olšák
59daac686d radeonsi/nir: validate is_patch because SPIR-V doesn't set it for tess factors
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:29 -05:00
Marek Olšák
272f1369ec radeonsi: simplify get_tcs_tes_buffer_address_from_generic_indices
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:28 -05:00
Marek Olšák
1e3aab4cd0 radeonsi: simplify the interface of get_dw_address_from_generic_indices
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:26 -05:00
Marek Olšák
756fc9f1bb radeonsi/nir: implement subgroup system values for SPIR-V
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:23 -05:00
Marek Olšák
42318f9197 ac/nir: don't rely on data.patch for tess factors
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-27 19:28:10 -05:00
Kenneth Graunke
51cc380894 drirc: Set vs_position_always_invariant for Shadow of Mordor on Intel
When drawing the main character in Shadow of Mordor, the game appears
to draw Talion with one vertex shader, and the Wraith with another.
If the compiler optimizes those in different ways which lead to slight
imprecisions, then the resulting positions may not line up, leading to
Z-fighting occurring as the game decides which of the two are in front.

brw_nir_opt_peephole_ffma looks at usages of multiply adds across the
entire shader, and may make different decisions between the two, leading
to such imprecisions and Z-fighting.  This started happening recently
after a NIR change to eliminate unnecessary MOVs (7025dbe7), but that
change simply exposed the existing problem.

Improves performance on Skylake GT4e by 1.22945% +/- 0.398672% (n=3),
likely due to the fixed rendering.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1985
Fixes: 7025dbe794 ("nir: Skip emitting no-op movs from the builder.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-11-27 18:48:04 +00:00
Kenneth Graunke
9b577f2a88 driconf, glsl: Add a vs_position_always_invariant option
Many applications use multi-pass rendering and require their vertex
shader position to be computed the same way each time.  Optimizations
may consider, say, fusing a multiply-add based on global usage of an
expression in a shader.  But a second shader with the same expression
may have different code, causing that optimization to make the other
choice the second time around.

The correct solution is for applications to mark their VS outputs
'invariant', indicating they need multiple shaders to compute that
output in the same manner.  However, most applications fail to do so.

So, we add a new driconf option - vs_position_always_invariant - which
forces the gl_Position output in vertex shaders to be marked invariant.

Fixes: 7025dbe794 ("nir: Skip emitting no-op movs from the builder.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-11-27 18:48:04 +00:00
Eric Anholt
424d5e4e11 turnip: Disable timestamp queries for now.
They're not implemented, and not critical to bring up immediately.  Avoids
failures in the CTS when nothing gets written to the query.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-27 10:05:59 -08:00
Jonathan Marek
080c92e7d4 freedreno/perfcntrs/fdperf: add missing a2xx case in select_counter
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-27 12:11:57 -05:00
Jonathan Marek
98d7125b36 freedreno/perfcntrs/fdperf: add missing a20x compatible
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-27 12:11:57 -05:00
Jonathan Marek
24cde37e8d freedreno/perfcntrs/fdperf: fix u64 print on 32-bit builds
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-27 12:11:57 -05:00
Jonathan Marek
baab4017b9 freedreno/perfcntrs: add a2xx MH counters
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-27 12:11:57 -05:00
Jonathan Marek
0d0c8a9e82 freedreno/registers: add missing MH perfcounter enum for a2xx
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-11-27 12:11:57 -05:00
Michel Dänzer
a3b3d3bfcc gitlab-ci: Put HTML summary in artifacts for failed piglit jobs
This will make it easier to look at details of failed / skipped tests.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-27 10:20:31 +01:00
Michel Dänzer
07c1346113 gitlab-ci: Stop storing piglit test results as JUnit
Since we're not reporting test results as JUnit anymore, we can use the
default JSON format.

This affects how test results are summarized, update the reference files
accordingly.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-27 10:19:22 +01:00
Michel Dänzer
c9cdb7cef0 gitlab-ci: Stop reporting piglit test results via JUnit
It was basically useless in this form, and processing the JUnit data in
the GitLab backend was pretty expensive.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-27 10:18:33 +01:00
Iago Toral Quiroga
18a09e788d v3d: fix indirect BO allocation for uniforms
We were always ensuring a minimum size of 4 bytes for uniforms
for the case where we don't have any, to account for hardware pre-fetching
of the uniform stream, however, pre-fetching could also lead to to out
of bounds reads when have read the last uniform in the stream, so we
probably want to have the extra 4 bytes to prevent the kernel from
observing invalid memory accesses when the uniform stream sits right at
the end of a page.

This seems to fix MMU exceptions reported with a Linux 5.4 kernel.

Credit goes to Phil Elwell for identifying the problem and narrowing
it down to memory accesses in the uniform stream.

Reported-by: Phil Elwell <phil@raspberrypi.org>
Tested-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-27 08:43:13 +01:00
Samuel Pitoiset
a24f1c8f7f radv: enable VK_KHR_shader_subgroup_extended_types on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-27 07:42:44 +01:00
Samuel Pitoiset
0812dbd403 ac: add 8-bit and 16-bit supports to ac_build_permlane16()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-27 07:42:42 +01:00
Samuel Pitoiset
c9aa843961 radv/gfx10: fix implementation of exclusive scans
This implementation is loosely based on ROCm.
https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/ockl/src/wfredscan.cl

This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive* on GFX10.

Fixes: 227c29a80d ("amd/common/gfx10: implement scan & reduce operations")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-27 07:39:26 +01:00
Samuel Pitoiset
86a5fbfd4a radv: fix enabling sample shading with SampleID/SamplePosition
When a fragment shader includes an input variable decorated with
SampleId or SamplePosition, sample shading should be enabled
because minSampleShadingFactor is expected to be 1.0.

Cc: 19.2, 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-27 07:22:54 +01:00
Jonathan Marek
62ff90cc5e turnip: fix integer render targets
Add missing required bits.  Fixes at least:

dEQP-VK.pipeline.render_to_image.dedicated_allocation.1d.small.r16g16_sint_d24_unorm_s8_uint
dEQP-VK.pipeline.render_to_image.dedicated_allocation.2d.mipmap.r16g16_sint_d24_unorm_s8_uint
dEQP-VK.renderpass.dedicated_allocation.attachment.4.401
dEQP-VK.renderpass2.suballocation.formats.r16_uint.load.draw
dEQP-VK.synchronization.op.single_queue.barrier.write_draw_read_copy_image_to_buffer.image_128x128_r16_uint

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-26 16:01:19 -08:00
Jason Ekstrand
a8965c076b anv: Push constants are relative to dynamic state on IVB
Fixes: aecde2351 "anv: Pre-compute push ranges for graphics pipelines"
Closes: #2136
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-26 22:15:54 +00:00
Dylan Baker
a24d6fbae6 meson: Add -Werror=gnu-empty-initializer to MSVC compat args
Only clang has this argument (at least as of clang 8 and gcc 9), which
errors when using the gcc empty initializer syntax in C:

```C
struct foo f = {};
```

GCC has a warning for this, but only when using -Wpedantic, which is a
lot of noise to lose useful warnings in.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-26 12:48:11 -08:00
Dylan Baker
25e58e3718 gallium/auxiliary: Fix uses of gnu struct = {} extension
Most of these will never actually be compiled by windows, but in the
interest of being able to make using struct foo = {}; an error and
avoiding breaking windows removing a handful of safe uses seems like a
good trade off.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-26 12:48:11 -08:00
Marek Olšák
ed1ff99da7 st/mesa: add st_variant base class to simplify code for shader variants
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
b8772a559a st/mesa: don't use ** in the st_nir_link_shaders signature
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
adbba2142d st/mesa: simplify looping over linked shaders when linking NIR
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
8567e06046 st/mesa: propagate gl_PatchVerticesIn from TCS to TES before linking for NIR
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
e8f0a39d45 st/mesa: don't call ProgramStringNotify in glsl_to_nir
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
5a714531f7 st/mesa: don't use redundant stp->state.ir.nir
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Marek Olšák
6cf011fcc8 st/mesa: don't serialize all streamout state if there are no SO outputs
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-26 15:14:10 -05:00
Kenneth Graunke
3fdf2bb313 iris: Disable VF cache partial address workaround on Gen11+
The vertex cache uses the full 48-bit address on Gen11+.  See the
documentation for 3DSTATE_VERTEX_BUFFERS, which describes the
workaround and lists it as pre-Icelake.

Interestingly, the docs don't mention index buffers as needing a
workaround at all.  So either we've been overzealous, or the docs
never got updated to record that.  Which begs the question of whether
the issue there was fixed, if there was one...

Cuts 40% of the PIPE_CONTROLs from Civilization VI's benchmark; appears
that it improves performance by about 1-2% on Icelake 8x8 (not frequency
locked).
2019-11-26 12:13:34 -08:00
Rob Clark
8d9f5a28e3 freedreno: switch to layout helper
The slices table and most of the other layout fields in the
freedreno_resource moves into fdl_layout.

v2: Changes by anholt to not have duplicate fields, which was introducing
    a surprising behavior change in resource layout (using the
    level_linear helper before the setup of the shadowed fields)

Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:08 +00:00
Eric Anholt
997b8d4749 freedreno/a6xx: Log the tiling mode in resource layout debug.
This was important for figuring out what went wrong with the layout
refactor.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Eric Anholt
2e62a622e7 freedreno: Convert the slice struct to the new resource header.
This gets the worst of the sed required for shared resource layout out of
the way.  The texture layout comment is dropped now that we're referencing
the shared header, which has a more complete description.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Eric Anholt
930432577f freedreno: Introduce a resource layout header.
This will be used for sharing resource layout code between freedreno and
tu.  Mostly copied from a commit by Rob, with a new location and the slice
struct renamed for consistency.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Eric Anholt
2ec420b264 freedreno: Introduce a fd_resource_tile_mode() helper.
Multiple places were doing the same thing to get the tile mode of a level,
so refactor it out.  This will make the shared resource helper transition
cleaner.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Eric Anholt
6b09227ede freedreno: Introduce a fd_resource_layer_stride() helper.
This factors out a bit of duplicated code, but will also make the shared
resource layout transition process clearer.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Rob Clark
9e9a26c768 freedreno: use rsc->slice accessor everywhere
This will make it easier to extract the slice table out into a layout
helper.

Acked-by: Rob Clark <robdclark@chromium.org>
2019-11-26 18:46:07 +00:00
Eric Anholt
d845dca0f5 nir: Make algebraic backtrack and reprocess after a replacement.
The algebraic pass was exhibiting O(n^2) behavior in
dEQP-GLES2.functional.uniform_api.random.3 and
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 (along with
other code-generated tests, and likely real-world loop-unroll cases).
In the process of using fmul(b2f(x), b2f(x)) -> b2f(iand(x, y)) to
transform:

result = b2f(a == b);
result *= b2f(c == d);
...
result *= b2f(z == w);

->

temp = (a == b)
temp = temp && (c == d)
...
temp = temp && (z == w)
result = b2f(temp);

nir_opt_algebraic, proceeding bottom-to-top, would match and convert
the top-most fmul(b2f(), b2f()) case each time, leaving the new b2f to
be matched by the next fmul down on the next time algebraic got run by
the optimization loop.

Back in 2016 in 7be8d07732 ("nir: Do opt_algebraic in reverse
order."), Matt changed algebraic to go bottom-to-top so that we would
match the biggest patterns first.  This helped his cases, but I
believe introduced this failure mode.  Instead of reverting that, now
that we've got the automaton, we can update the automaton's state
recursively and just re-process any instructions whose state has
changed (indicating that they might match new things).  There's a
small chance that the state will hash to the same value and miss out
on this round of algebraic, but this seems to be good enough to fix
dEQP.

Effects with NIR_VALIDATE=0 (improvement is better with validation enabled):

Intel shader-db runtime -0.954712% +/- 0.333844% (n=44/46, obvious throttling
  outliers removed)
dEQP-GLES2.functional.uniform_api.random.3 runtime
  -65.3512% +/- 4.22369% (n=21, was 1.4s)
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 runtime
  -68.8066% +/- 6.49523% (was 4.8s)

v2: Use two worklists, suggested by @cwabbott, to cut out a bunch of
    tricky code.  Runtime of uniform_api.random.3 down -0.790299% +/-
    0.244213% compred to v1.
v3: Re-add the nir_instr_remove() that I accidentally dropped in v2,
    fixing infinite loops.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-26 10:13:46 -08:00
Eric Anholt
90ad6304bf nir: Refactor algebraic's block walk
My motivation was to clarify the changes in the following commit, but
incidentally, it reduces runtime of
dEQP-GLES2.functional.uniform_api.random.3 (an algebraic-heavy
testcase) by -5.39524% +/- 2.21179% (n=15)

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-26 10:13:40 -08:00
Connor Abbott
305d1300f9 nir: Maintain the algebraic automaton's state as we work.
In order to have nir_opt_algebraic be able to do further algebraic
work on the output of a replacement, we need to maintain the
automaton's state.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-26 10:13:19 -08:00
Jonathan Marek
2da4a58ed9 etnaviv: support 3d/array/integer formats in texture descriptors
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-26 19:07:04 +01:00
Jonathan Marek
7806e058c9 etnaviv: blt: fix partial ZS clears with TS
If not all bits are cleared, then BLT needs to be given the current clear
value and not the new one.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-26 19:04:51 +01:00
Daniel Schürmann
7cd548d352 aco: don't value-number instructions from within a loop with ones after the loop.
Fixes:
Wolfenstein:Youngblood (w/o shader_ballot)
dEQP-VK.descriptor_indexing.combined_image_sampler_in_loop_with_lod

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-26 14:39:27 +00:00
Rhys Perry
46420dd294 aco: set dlc/glc correctly for image loads
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2019-11-26 14:39:27 +00:00
Rhys Perry
37843e454e aco: allow constant offsets for global/scratch instructions on GFX10
I don't think the bug applies for global/scratch instructions and
load_barycentric_at_sample selection expects this feature to work.

Fixes various dEQP-VK.pipeline.multisample_interpolation.* tests on GFX10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2019-11-26 14:39:27 +00:00
Bas Nieuwenhuizen
02375b8436 radv: Enable VK_KHR_buffer_device_address.
Still no capture/replay or multi device support.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-26 11:59:52 +00:00
Samuel Pitoiset
34dd4251e2 radv: fix reporting subgroup size with VK_KHR_pipeline_executable_properties
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-26 10:48:48 +01:00
Bas Nieuwenhuizen
25bc9102d8 radv: Allocate cmdbuffer space for buffer marker write.
Fixes: 946193ae00 "radv: add support for VK_AMD_buffer_marker"
Reviewed-by:  Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-26 09:35:02 +00:00
Gert Wollny
e41958e344 r600: Disable eight bit three channel formats
Commit 0899bf55 made some deqp-gles3 tests related to RGB8 PBOs fail
on R600 because it exposed PIPE_FORMAT_R8G8B8_UNORM and R600 doesn't
propely handle this. Disabling this format also for buffers fixes the
issue.

In addition, disabling also the related RGB8 integer formats for buffers
fixes some deqp-gles3 tests:

  dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgb8ui_cube
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_2d
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_cube
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_2d
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_cube
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_2d_array
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_3d
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_2d_array
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_3d
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_2d_array
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_3d
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_2d_array
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_3d

Fixes: 0899bf55
  st/mesa: Map MESA_FORMAT_RGB_UNORM8 <-> PIPE_FORMAT_R8G8B8_UNORM

Closes #2118

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-26 09:28:52 +01:00
Samuel Pitoiset
f6770b9726 ac/llvm: fix warning in ac_build_canonicalize()
../src/amd/llvm/ac_llvm_build.c: In function ‘ac_build_canonicalize’:
../src/amd/llvm/ac_llvm_build.c:4567:9: warning: ‘intr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
 4567 |  return ac_build_intrinsic(ctx, intr, type, params, 1,
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 4568 |       AC_FUNC_ATTR_READNONE);
      |       ~~~~~~~~~~~~~~~~~~~~~~
../src/amd/llvm/ac_llvm_build.c:4567:9: warning: ‘type’ may be used uninitialized in this function [-Wmaybe-uninitialized]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-26 08:35:10 +01:00
Tapani Pälli
5d58fea660 mapi: add GetInteger64vEXT with EXT_disjoint_timer_query
From EXT_disjoint_timer_query spec:

   "Interaction: This extension adds GetInteger64vEXT if
    OpenGL ES 3.0 is not supported"

See https://github.com/KhronosGroup/OpenGL-Registry/issues/326.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-26 07:41:24 +02:00
Jason Ekstrand
200a3301e2 vulkan: Update the XML and headers to 1.1.129
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-26 02:48:42 +00:00
Jason Ekstrand
854859fefa anv/entrypoints: Better handle promoted extensions
In the case of promoted extensions we can end up with an entrypoint that
we support being an alias of an entrypoint we do not support.  For
instance, if an extension gets promoted from EXT to KHR, the EXT entry-
points may be aliases of the KHR ones.  We want to leave everything as
EXT until we get around to advertising the KHR so that we don't break
things when we update the XML and headers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-26 02:48:42 +00:00
Jason Ekstrand
121551bfdb vulkan/enum_to_str: Handle out-of-order aliases
The current code can only handle enum aliases if the original enum is
declared first followed by the alias as we walk the XML in a linear
fashion.  This commit allows us to handle aliases where the alias
declaration comes before the thing it's aliasing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-26 02:48:42 +00:00
Kenneth Graunke
f6aa51103b iris: Update SURFACE_STATE addresses when setting sampler views
We may have replaced the backing storage for a texture buffer while it
was unbound, at which point iris_rebind_buffer would not have caught it
and updated it.  We need to ensure that the current resource's address
matches the one our SURFACE_STATE points at.  If not, update addresses
and re-upload the SURFACE_STATE.

Shader images and buffers do not suffer from this problem because we
re-stream the surface state on every set call, since there isn't a
created CSO object for those with a saved SURFACE_STATE.  Constant
buffers are also currently re-streamed (we pitch the SURFACE_STATE
on every set_constant_buffer call).  Surfaces would need this
treatment (as they're created CSOs) except that we never swap out
their backing storage today (we only do it for buffers), so it's OK
for now.

Fixes misrendering in Unreal 4 demos (Elemental, Matinee Fight Scene).
Huge thanks to Andrii Simiklit for tracking down the problem - it was
quite difficult to find!  Also fixes Andrii's new Piglit test for the
bug, 'arb_texture_buffer_object-re-init'.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1365
2019-11-25 15:54:54 -08:00
Kenneth Graunke
060a2c52fa iris: Maintain CPU-side SURFACE_STATE copies for views and surfaces.
When replacing the backing storage for texture buffers, image buffers,
and so on, we may need to update the "Surface Base Address" field in
any corresponding SURFACE_STATE.  This is easier to accomplish if we
have a copy on the CPU - we can just compare the current field, update
it, and re-upload.

This patch adds a CPU-side copy to the new iris_surface_state wrapper
struct, and reworks allocation and upload to fill things out on the
CPU copy first, then upload that to the GPU when finished.

This will be necessary to fix iris_invalidate_resource bugs shortly.

Technically, we never replace the backing storage for pipe_surfaces
(render targets), so we don't need to make this change there.  However,
it's nice to have surfaces, sampler views, and image views handled
similarly.  Plus, if we ever wanted to swap out backing storage for
busy textures, we'd need this infrastructure.

v2: Properly free memory (caught by Andrii Simiklit)
2019-11-25 15:54:54 -08:00
Kenneth Graunke
2b09e818dc iris: Create an "iris_surface_state" wrapper struct
Today, we only have a state reference to the GPU buffer containing our
uploaded SURFACE_STATEs.  However, we're going to want a CPU-side copy
soon.  Making a wrapper struct means we can talk about both together,
and also put both in the field called "surface_state".
2019-11-25 15:54:54 -08:00
Kenneth Graunke
4c1f81ad62 iris: Drop 'old_address' parameter from iris_rebind_buffer
We can just compare the VERTEX_BUFFER_STATE address field to the
current BO's address.  When calling rebind, we've already updated
the resource to the new buffer, but the state will have the old
address.
2019-11-25 15:54:54 -08:00
Kenneth Graunke
518be59c1a iris: Stop mutating the resource in get_rt_read_isl_surf().
Mutating fields of global resources is generally not safe, and the only
reason we were doing it was to avoid passing an extra parameter to
the fill_surface_state helper.
2019-11-25 15:54:54 -08:00
Marek Olšák
b02e0d2604 radeonsi/nir: don't run si_nir_opts again if there is no change
0.3% less overhead

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-25 16:48:27 -05:00
Marek Olšák
4675cb2019 radeonsi: initialize the per-context compiler on demand
This takes a noticable amount of time in piglit and some tests don't
need it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-25 16:48:27 -05:00
Marek Olšák
f671cc4d95 ac: set swizzled bit in cache policy as a hint not to merge loads/stores
LLVM now merges loads and stores for all opcodes, so this must be set.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 16:48:27 -05:00
Eric Anholt
8afab607ac nir: Add a scheduler pass to reduce maximum register pressure.
This is similar to a scheduler I've written for vc4 and i965, but this
time written at the NIR level so that hopefully it's reusable.  A notable
new feature it has is Goodman/Hsu's heuristic of "once we've started
processing the uses of a value, prioritize processing the rest of their
uses", which should help avoid the heuristic otherwise making such
systematically bad choices around getting texture results consumed.

Results for v3d:

total instructions in shared programs: 6497588 -> 6518242 (0.32%)
total threads in shared programs: 154000 -> 152828 (-0.76%)
total uniforms in shared programs: 2119629 -> 2068681 (-2.40%)
total spills in shared programs: 4984 -> 472 (-90.53%)
total fills in shared programs: 6418 -> 1546 (-75.91%)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (v2)

v2: Use the DAG datastructure, fold in the scheduling-for-parallelism
    patch, include SSA defs in live values so we can switch to bottom-up
    if we want.
v3: Squash in improvements from Alejandro Piñeiro for getting V3D to
    successfully register allocate on GLES3.1 dEQP.  Make sure that
    discards don't move after store_output.  Comment spelling fix.
2019-11-25 21:12:21 +00:00
Jonathan Marek
5159db60fc etnaviv: implement 64bpp clear
At the same time, update etna_clear_blit_pack_rgba to work with integer
formats.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-25 20:23:22 +01:00
Jonathan Marek
2214f99c07 etnaviv: avoid using RS for 64bpp formats
At the same time, this change allows using BLT for 8bpp formats

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-25 20:22:43 +01:00
Christian Gmeiner
92d5e3c692 etnaviv: add support for extended pe formats
Use the extended format if an such a format was passed.

v1 -> v2:
 - set FORMAT_MASK bit when using ext PE format as suggested
   by Wladimir J. van der Laan

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-11-25 20:12:52 +01:00
Christian Gmeiner
396818fd9d etnaviv: handle 8 byte block in tiling
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-11-25 20:11:30 +01:00
Samuel Pitoiset
2af39c719e radv: select the depth decompress path based on the aspect mask
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 16:29:23 +01:00
Samuel Pitoiset
905c005561 radv: create decompress pipelines for separate depth/stencil layouts
No functional changes as the driver still uses the depth+stencil
pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 16:29:21 +01:00
Samuel Pitoiset
faa58201f3 radv: rework creation of decompress/resummarize meta pipelines
This refactoring will help for creating more decompress pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 16:29:18 +01:00
Samuel Pitoiset
8f0fb38825 radv: set the image view aspect mask before resolves
No functional changes, but it will be used to decompress
separate depth/stencil aspects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 16:29:16 +01:00
Samuel Pitoiset
9dec90b7bc radv: set the image view aspect mask during subpass transitions
No functional changes because the aspect mask is still not used
during image transitions but it will be needed for the separate
depth/stencil aspects logic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 16:29:13 +01:00
Rhys Perry
459bc77763 aco: enable load/store vectorizer
Totals from affected shaders:
SGPRS: 1890373 -> 1900772 (0.55 %)
VGPRS: 1210024 -> 1215244 (0.43 %)
Spilled SGPRs: 828 -> 828 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 252 -> 252 (0.00 %) dwords per thread
Code Size: 81937504 -> 74608304 (-8.94 %) bytes
LDS: 746 -> 746 (0.00 %) blocks
Max Waves: 230491 -> 230158 (-0.14 %)

In NeiR:Automata and GTA V, the code decrease is especially large: -13.79%
and -15.32%, respectively.

v9: rework the callback function
v10: handle load_shared/store_shared in the callback

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v9)
2019-11-25 13:59:11 +00:00
Rhys Perry
0a759c3be6 nir: add load/store vectorizer tests
v7: run nir_opt_algebraic
v9: rework the callback function
v9: update alignment on all loads/stores, even if they're not vectorized
v10: add tests for 64-bit offsets
v10: add tests for signed offsets

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v9)
2019-11-25 13:59:11 +00:00
Rhys Perry
ce9205c03b nir: add a load/store vectorization pass
This pass combines intersecting, adjacent and identical loads/stores into
potentially larger ones and will be used by ACO to greatly reduce the
number of memory operations.

v2: handle nir_deref_type_ptr_as_array
v3: assume explicitly laid out types for derefs
v4: create less deref casts
v4: fix shared boolean vectorization
v4: fix copy+paste error in resources_different
v4: fix extract_subvector() to pass
    nir_load_store_vectorize_test.ssbo_load_intersecting_32_32_64
v4: rebase
v5: subtract from deref/offset instead of scheduling offset calculations
v5: various non-functional changes/cleanups
v5: require less metadata and preserve more
v5: rebase
v6: cleanup and improve dependency handling
v6: emit less deref casts
v6: pass undef to components not set in the write_mask for new stores
v7: fix 8-bit extract_vector() with 64-bit input
v7: cleanup creation of store write data
v7: update align correctly for when the bit size of load/store increases
v7: rename extract_vector to extract_component and update comment
v8: prevent combining of row-major matrix column acceses
v9: rework process_block() to be able to vectorize more
v9: rework the callback function
v9: update alignment on all loads/stores, even if they're not vectorized
v9: remove entry::store_value, since it will not be updated if it's was
    from a vectorized load
v9: fix bug in subtract_deref(), causing artifacts in Dishonored 2
v9: handle nir_intrinsic_scoped_memory_barrier
v10: use nir_ssa_scalar
v10: handle non-32-bit offsets
v10: use signed offsets for comparison
v10: improve create_entry_key_from_offset()
v10: support load_shared/store_shared
v10: remove strip_deref_casts()
v10: don't ever pass NULL to memcmp
v10: remove recursion in gcd()
v10: fix outdated comment
v11: use the new nir_extract_bits()
v12: remove use of nir_src_as_const_value in resources_different
v13: make entry key hash function deterministic
v13: simplify mask_sign_extend()
v14: add comment in hash_entry_key() about hashing pointers

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v9)
2019-11-25 13:59:11 +00:00
Rhys Perry
b3a3e4d1d2 radv: set alignment for load_ssbo/store_ssbo in meta shaders
Otherwise, nir_intrinsic_align() will assert when called on the intrinsics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 13:59:11 +00:00
Rhys Perry
c14f823ee5 nir: add nir_num_variable_modes and nir_var_mem_push_const
These will be useful in the upcoming load/store vectorizer.

v11: rebase

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-25 13:59:11 +00:00
Connor Abbott
01eb6ef870 aco: Make unused workgroup id's 0
It shouldn't matter, but the 1 was leftover from when it was handled
together with workgroup_size and num_work_groups.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
bb78f9b4e4 aco: Use common argument handling
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
e7f4cadd02 radv: Replace supports_spill with explict_scratch_args
The former was always true and hence dead code. We will want to
explicitly declare the ring offset register with ACO, but we also want
to declare the scratch offset too, and we can't try to disable it since
ACO also supports spilling and the determination of whether spilling has
to happen occurs well after setting up registers. So replace
supports_spill with something that will actually be used for ACO.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 14:17:51 +01:00
Connor Abbott
4d6676d78a aco: Make num_workgroups and local_invocation_ids one argument each
To match the LLVM argument setup code.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
a7f1c63442 aco: Split vector arguments at the beginning
Due to how LLVM works we have to make some of the FS inputs become
vectors, and therefore have to split them early so that they don't take
up extra register pressure due to how RA currently works.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
b45c54ff8d aco: Use radv_shader_args in aco_compile_shader()
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
680b086db1 aco: Constify radv_nir_compiler_options in isel
It's already const for everything else.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-25 14:17:51 +01:00
Connor Abbott
66c703b3e8 radv: Move argument declaration out of nir_to_llvm
Now it's executed for ACO too.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 14:17:51 +01:00
Connor Abbott
3b143369a5 ac/nir, radv, radeonsi: Switch to using ac_shader_args
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
2019-11-25 14:17:10 +01:00
Connor Abbott
9885af3bdf ac: Add a shared interface between radv, radeonsi, LLVM and ACO
ac_shader_args will be similar to ac_shader_abi, except for being free
from LLVM-specific concepts and therefore capable of being shared
between LLVM and ACO. This will help us accomplish a few different
things:

- Decouple setting up SGPR and VGPR arguments from translating to LLVM,
so that we can reference these arguments in NIR lowering passes, which
will let us lower e.g. descriptor sets in NIR.

- Stop using radv-specific structures for things like determining the
chip generation in ACO.

In the end, we should replace ac_shader_abi with this structure +
driver-specific lowering passes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 14:12:46 +01:00
Connor Abbott
43da33c169 radv: Rename ac_arg_regfile
We'll duplicate this in a header file in the next commit, and then
remove the original enum. Just rename it temporarily so that things
keep building.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-25 14:12:46 +01:00
Danylo Piliaiev
29081c671f drirc: Add glsl_zero_init workaround for GpuTest
GiMark benchmark from GpuTest has such code in VS:

 out vec4 lightDir0;
 out vec4 lightDir1;

 ...

 lightDir0.xyz = lp0 - vVertex.xyz;
 lightDir1.xyz = lp1 - vVertex.xyz;

In FS:

 float distSqr = dot(lightDir0, lightDir0);

So due to the usage of uninitialized .w channel in the dot product,
distSqr may become undefined which results in many black dots
in the test on Iris.

In https://www.geeks3d.com/forums/index.php/topic,6242.0.html
developer stated that this benchmark most likely won't be updated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1919
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-25 12:22:37 +02:00
Samuel Pitoiset
d6db858771 meson: only build imgui when needed
Only required for Intel tools or the Vulkan overlay layer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-25 07:51:56 +00:00
Samuel Pitoiset
bfb307aea9 ac/llvm: fix the local invocation index for wave32
Fixes dEQP-VK.compute.builtin_var.local_invocation_index with
RADV_PERFTEST=cswave32.

My initial fix was to lower it but Rhys suggested the shift-right
and it's much better like this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 07:25:48 +00:00
Samuel Pitoiset
b99295fb33 radv: disable subgroup shuffle operations on GFX10
They are broken like on GFX6-GFX7. It seems better to disable them
instead of enabling a broken feature.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-25 08:03:24 +01:00
Dave Airlie
1c5dc4eaf9 docs: add llvmpipe to ARB_query_buffer_object. 2019-11-25 12:37:58 +10:00
Dave Airlie
506e51b856 llvmpipe: initial query buffer object support. (v2)
This fails a couple of piglits due to other bugs in llvmpipe,
but it adds support for the feature properly.

v2: don't reset pipestats, just recalc, fix CI expectation
2019-11-25 12:37:32 +10:00
Timothy Arceri
f54c4e85ce radv: create a fresh fork for each pipeline compile
In order to prevent a potential malicious pipeline tainting our
secure compile process and interfering with successive pipelines
we want to create a fresh fork for each pipeline compile.

Benchmarking has shown that simply forking on each pipeline
creation doubles the total time it takes to compile a fossilize db
collection. So instead here we fork the process at device creation
so that we have a slim copy of the device and then fork this
otherwise idle and untainted process each time we compile a
pipeline. Forking this slim copy of the device results in only a
20% increase in compile time vs a 100% increase.

Fixes: cff53da3 ("radv: enable secure compile support")
2019-11-25 10:10:14 +11:00
Timothy Arceri
1663bb1f77 radv: add a secure_compile_open_fifo_fds() helper
This will be used to create a communication pipe between the user
facing device and a freshly forked (per pipeline compile) slim copy
of that device.

We can't use pipe() here because the fork will not be a direct fork
of the user facing process. Instead we use a previously forked
copy of the process that was forked at device creation in order to
reduce the resources required for the fork and avoid performance
issues.

Fixes: cff53da374 ("radv: enable secure compile support")
2019-11-25 10:10:14 +11:00
Timothy Arceri
ef54f15da9 radv: add some infrastructure for fresh forks for each secure compile
In the following commits we want to be able to fork an existing lightweight
fork created at device creation time. In order for the user facing process
to communicate with this new fresh fork we create some members here to hold
FIFO file descriptors and a unique id.

Here we also add a new fork enum that we use to tell the lightweight
process to create a fresh fork.

For more information on why we create a fresh fork see the following
commits.
2019-11-25 10:10:14 +11:00
Brian Paul
a2689ebcd6 nir: no-op C99 _Pragma() with MSVC
This fixes a build failure on MSVC.

BTW, it looks like clang supports _Pragma() but I don't know if it
understands the "gcc unroll N" directive.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-11-23 10:34:24 -07:00
Michel Zou
95fdde5a60 Meson: Add llvm>=9 modules
Fixes build with MinGW, with shared LLVM and lto
/tmp/opengl32.dll.BxiIYm.ltrans59.ltrans.o:<artificial>:(.text+0x1674): undefined reference to `LLVMAddInstructionCombiningPass'

See also scons/llvm.py

Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-23 16:09:52 +00:00
Michel Zou
02d63ee5a4 disk_cache_get_function_timestamp: check for dladdr
instead of dlopen

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-23 12:01:11 +01:00
Michel Zou
bfd9f3201e Meson: Check for dladdr with MinGW
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-23 12:01:11 +01:00
Marek Olšák
ad40715f35 nir/serialize: support any num_components for remaining instructions
Only NPOT vectors greater than vec4 use the extra uint32.

This is for instructions that share the dest code.
load_const and undef already support 1-16 in the header.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
c028449c01 nir/serialize: use 3 unused bits in intrinsic for packed_const_indices
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
3d44aed09e nir/serialize: don't serialize redundant nir_intrinsic_instr::num_components
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
a2df670b14 nir/serialize: serialize writemask for vec8 and vec16
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
a5c5388234 nir/serialize: serialize swizzles for vec8 and vec16
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
f1a48d54ea nir/serialize: reuse the writemask field for 2 src X swizzles of SSA ALU
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
487a495cc0 nir/serialize: remove up to 3 consecutive equal ALU instruction headers
vec4 scalarized ALUs typically have 4 equal instruction headers, so remove
the last 3.

There are no bits left in the ALU header for more flags, so future
extensions of NIR will have to use something like instr_type == 15
to describe more complex ALU instructions.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
c3fa9de2a9 nir/serialize: try to pack both deref array src into 32 bits
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
ed6b01d5e0 nir/serialize: cleanup - fold nir_deref_type_var cases into switches
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
a0cd67d292 nir/serialize: try to put deref->var index into the unused bits of the header
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
ca201bfe70 nir/serialize: don't serialize mode for deref non-cast instructions
It can be derived from src and var. This frees 10 bits in the header
that will be used later.

"mode" is moved in the structure, because those bits will be used for
something else later.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
2286340fde nir/serialize: don't store deref types if not needed
- type_cast: deduplicate types if the last one is the same
- derive the type from the parent for other derefs

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
70a7f85149 nir/serialize: try to pack two alu srcs into 1 uint32
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
ef4630cf4f nir/serialize: pack nir_intrinsic_instr::const_index[] better
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
d3346b275a nir/serialize: pack 1-component constants into 20 bits if possible
The majority of constants can be packed like this.

v2: - use enum for the packing encoding,
    - trim packed_value to 20 bits add 1 bit to last_component,
      which simplifies a later commit

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
75f7c38863 nir/serialize: pack load_const with non-64-bit constants better
v2: use blob_write_uint8/16

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
a572ba673b nir/serialize: try to store a diff in var data locations instead of var data
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
c8314678ee nir/serialize: deduplicate serialized var types by reusing the last unique one
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
545415f45f nir/serialize: don't serialize var->data for temporaries
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
c358c2b2bf nir/serialize: pack src better and limit the object count to 1M from 1G
We need to limit the object count to 1M to free 10 bits for the src
modifiers.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
35655865cb nir/serialize: pack instructions better
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Marek Olšák
4fe1d7822b util/blob: add 8-bit and 16-bit reads and writes
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-23 00:02:10 -05:00
Eric Anholt
59b489f44b ci: Use a tag from the parallel-deqp-runner repo.
If the repo continues development, we don't want to accidentally pick
up potentially breaking changes on our next container rebuild.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 15:37:04 -08:00
Rob Clark
215866523b gitlab-ci/freedreno/a6xx: remove most of the flakes
xfb + lines/points still flakes too frequently (and the problem isn't
even related to xfb), but we can add the rest back into this mix now.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-22 13:48:29 -08:00
Rob Clark
9f422cbe1c gitlab-ci/deqp: generate junit results
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
415d565d96 gitlab-ci/deqp: generate xml results for fails/flakes
Extract .qpa for the individual unexpected results and flakes, and
translate to xml, preserved with the artifacts.  This allows easy
browsing of the test logs for fails/flakes, for easier debugging.

The # of logs to preserve is capped at 50 to avoid saving 100s of
megabytes of logs in case someone pushes a change that breaks
everything.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
8af7551a9e gitlab-ci: bump arm test container
To pick up updated cts_runner and netcat for the flake reporting.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
fdaf777076 gitlab-ci/deqp: detect and report flakes
If there are a small number of fails, re-run to determine if they are
flakes, and optionally (if `$FLAKES_CHANNEL` configured) report the
flakes.

This way flakes don't interfere with developers working on other
drivers, but get logged so that the developers working on the flaking
driver can monitor the situation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
cc6484f164 gitlab-ci/deqp: preserve caselists for blocks with fails
Bump cts_runner to pick up the change to preserve .qpa and caselist .txt
files for blocks of tests that contain fails, and preserve the caselist
files.  To reproduce fails that depend on order of running tests, these
are useful.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
59ed90fc74 gitlab-ci/deqp: preserve full list of unexpected results
The log only shows the first 50, but preserve the full list for easier
browsing.

(Also move return of exit code to end which makes later patches in the
series easier)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Rob Clark
5fa397a0d9 gitlab-ci: update deqp build so we can generate xml
Update the deqp build to preserve testlog-to-xml and stylesheets, so
deqp runner can extract .qpa for failed/flaked tests, and convert to
xml.  With this, will be able to browse output from failed tests
directly from the artifacts.

The main motiviation is to give better visibility into what happens with
flaked tests, when it is difficult/impossible to reproduce the flake
locally (ie. when it happens once out of N million tests).  But this
should also make it easier to debug regressions that a MR triggers,
especially when it is on hw that you don't have.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-22 13:48:29 -08:00
Markus Wick
dba903ed0b drirc: Enable glthread for dolphin/citra/yuzu.
Dolphin: 75 fps -> 88 fps - Super Mario Galaxy
Citra:   81 fps -> 91 fps - A Link Between Worlds
Yuzu:    21 fps -> 27 fps - Super Mario Odyssey

Dolphin still has many syncs because of glFenceSync and glClientWaitSync.
Moving them to the dispatcher thread might yield another speedup.

Yuzu uses a compatible profile by default. This benchmark used the variable
MESA_GL_VERSION_OVERRIDE=4.5FC to overwrite this behavior.

This profilation was done on a mobile i7-8550U CPU with i965.

Signed-off-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-22 15:29:29 -05:00
Markus Wick
f4c61d422d mesa/glthread: Implement ARB_multi_bind.
Signed-off-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-22 15:29:07 -05:00
Rhys Perry
517728477c aco: fix waitcnts for barriers at block ends
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: d1b9deee ('aco: improve waitcnt insertion around loops')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-22 19:56:31 +00:00
Zebediah Figura
a3c8bc10aa Revert "draw: revert using correct order for prim decomposition."
This reverts commit f97b731c82.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/250

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-22 20:37:42 +01:00
Kenneth Graunke
acd36e488d iris: Change keybox parenting
For temporary lookups, just allocate out of the NULL ralloc context,
so we don't have to edit the linked list of ralloc children to add it
and then immediately remove it again.

When uploading a new shader, allocate the keybox off the shader, so
if we delete the shader the keybox also goes away.  Less manual cleanup.
2019-11-22 09:50:59 -08:00
Ian Romanick
ca353285cb nir/range_analysis: Make sure the table validation only occurs once
All of the tables are static const, so they only need to be validated
once.  As noted in the previous commit, the compiler should be able to
eliminate all of this code when the assertions would pass.  Even with
the help of the previous commit, this does not always occur.

-Og: -95.688 +/- 3.91935 (-24.9562% +/- 1.0222%) N=5
-O1: No difference proven at 95.0% confidence. N=5
-O2: -1.962 +/- 0.85001 (-0.860013% +/- 0.372589%) N=5

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-22 08:16:06 -08:00
Ian Romanick
ccefce46cb nir/range-analysis: Add pragmas to help loop unrolling
I was pretty liberal with these assertions when I wrote this code
because I had assumed that GCC would unroll the loops, inline the look ups
of static const arrays with now constant indices, and then elmininate
all the actuall assertions.  It seems none of this happens even at -O3.

Adding the pragmas helps encourage loop unrolling at some optimization
levels.  I tested by running shader-db with NIR_VALIDATE=false on a Core
i7 Haswell desktop system.

-Og: No difference proven at 95.0% confidence. N=5
-O1: -48.304 +/- 1.221 (-16.3343% +/- 0.412888%) N=5
-O2: -49.94 +/- 1.23521 (-17.9634% +/- 0.444303%) N=5

v2: Add a _Pragma to an inner loop that was accidentally dropped during
a rebase.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-22 08:16:06 -08:00
Danylo Piliaiev
25a00b449f glsl: Add varyings to "zero-init of uninitialized vars" workaround
Varyings are similar to already handled cases. And "glsl_zero_init"
name of the workaround already looks like it should include varyings.

The issue was observed in GiMark subtest from GpuTest.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-22 15:25:56 +00:00
Alyssa Rosenzweig
4c43b354c3 pan/midgard: Use lower_tex_without_implicit_lod
Just a bit of cleanup. lower_tex can do this lowering for us, which
should also eliminate some special cases (one less thing to fix if we
ever need texturing in tess/geom/etc, perhaps?)

Closes #2133

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 08:38:57 -05:00
Christian Gmeiner
47c7c4263c etnaviv: use a more self-explanatory param name
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-22 10:47:13 +00:00
Christian Gmeiner
a949fa9d5d etnaviv: drop not used config_out function param
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-22 10:47:13 +00:00
Samuel Pitoiset
6f7ec6ee39 gitlab-ci: reduce the number of scons build
It seems overkill to me to build scons 7x for every pipeline.
Scons is now build with the oldest llvm version in scons-old-llvm
and with the newest llvm version in scons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-22 10:39:21 +01:00
Alyssa Rosenzweig
2e14fe6490 panfrost: Add lcra.c to Android.mk
This was forgotten.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Alyssa Rosenzweig
bda2bb31b1 pan/midgard: Enable LOD lowering only on buggy chips
T720 and earlier need this workaround, so check the quirk before
lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Alyssa Rosenzweig
68c2c7962a pan/midgard: Describe quirk MIDGARD_BROKEN_LOD
Corresponds to errata #10471, applies to T6xx and T720. Fixed in T760.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Alyssa Rosenzweig
d32d4acf68 pan/midgard: Add LOD bias/clamp lowering
We fetch the info with the new intrinsic and lower with ALU ops for txl
instructions, which seemingly correspond to "TEXGRD" instructions (what
we call textureLod).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Alyssa Rosenzweig
4e07e7b232 pan/midgard: Implement load_sampler_lod_paramaters_pan
We can stuff this information in as parametrized system values, like we
currently do texture size and SSBO addresses.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Alyssa Rosenzweig
deaebc82a7 nir: Add load_sampler_lod_paramaters_pan intrinsic
This loads in the <min_lod, max_lod, lod_bias> settings for a given
sampler, which is necessary for lowering clamps/biases on certain
Midgard chips.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-22 05:07:19 +00:00
Markus Wick
b1156ecdf2 mapi/glapi: Generate sizeof() helpers instead of fixed sizes.
Generating a source code with a fixed size leads to issues with plattform dependent types.
We either hard code 4 or 8 bytes there, and both are wrong on the other plattform.
So this patch solves this issue by generating eg sizeof(GLsizeiptr), which is valid both
on 32 and on 64 bit plattforms.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-11-21 22:52:55 -05:00
Ian Romanick
e51eda99df intel/fs: Disable conditional discard optimization on Gen4 and Gen5
The CMP instruction on Gen4 and Gen5 generates one bit (the LSB) of
valid data and 31 bits of junk.  Results of comparisons that are used as
Boolean values need to have a fixup applied to generate the proper 0/~0
values.

Calling fs_visitor::nir_emit_alu with need_dest=false prevents the fixup
code from being generated.  This results in a sequence like:

        cmp.l.f0.0(16)  g8<1>F          g14<8,8,1>F     0x0F  /* 0F */
        ...
        cmp.l.f0.0(16)  g4<1>F          g6<8,8,1>F      0x0F  /* 0F */
(+f0.1) or.z.f0.1(16) null<1>UD g4<8,8,1>UD     g8<8,8,1>UD

instead of

        cmp.l.f0.0(16)  g8<1>F          g14<8,8,1>F     0x0F  /* 0F */
        ...
        cmp.l.f0.0(16)  g4<1>F          g6<8,8,1>F      0x0F  /* 0F */
        or(16) g4<1>UD g4<8,8,1>UD     g8<8,8,1>UD
(+f0.1) and.z.f0.1(16) null<1>UD g4<8,8,1>UD     1UD

I examined a couple of the shaders hurt by this change, and ALL of them
would have been affected by this bug. :(

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1836
Fixes: 0ba9497e66 ("intel/fs: Improve discard_if code generation")

Iron Lake
total instructions in shared programs: 8122757 -> 8122957 (<.01%)
instructions in affected programs: 8307 -> 8507 (2.41%)
helped: 0
HURT: 100
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.84% max: 6.67% x̄: 2.81% x̃: 2.76%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.58% 3.03%
Instructions are HURT.

total cycles in shared programs: 188510100 -> 188510376 (<.01%)
cycles in affected programs: 76018 -> 76294 (0.36%)
helped: 0
HURT: 55
HURT stats (abs)   min: 2 max: 12 x̄: 5.02 x̃: 4
HURT stats (rel)   min: 0.07% max: 3.75% x̄: 0.86% x̃: 0.56%
95% mean confidence interval for cycles value: 4.33 5.71
95% mean confidence interval for cycles %-change: 0.60% 1.12%
Cycles are HURT.

GM45
total instructions in shared programs: 4994403 -> 4994503 (<.01%)
instructions in affected programs: 4212 -> 4312 (2.37%)
helped: 0
HURT: 50
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.84% max: 6.25% x̄: 2.76% x̃: 2.72%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.45% 3.07%
Instructions are HURT.

total cycles in shared programs: 128928750 -> 128928982 (<.01%)
cycles in affected programs: 67442 -> 67674 (0.34%)
helped: 0
HURT: 47
HURT stats (abs)   min: 2 max: 12 x̄: 4.94 x̃: 4
HURT stats (rel)   min: 0.09% max: 3.75% x̄: 0.75% x̃: 0.53%
95% mean confidence interval for cycles value: 4.19 5.68
95% mean confidence interval for cycles %-change: 0.50% 1.00%
Cycles are HURT.
2019-11-21 16:40:50 -08:00
Dylan Baker
bba44ef176 docs: update calendar, add news item and link release notes for 19.2.6 2019-11-21 16:34:00 -08:00
Dylan Baker
3531d74e82 docs: Add SHA256 sum for 19.2.6 2019-11-21 16:32:35 -08:00
Dylan Baker
f8070577a4 docs: Add release notes for 19.2.6 2019-11-21 16:32:34 -08:00
Marek Olšák
0b1452ffdd nir/serialize: do ctx = {0} instead of manual initializations
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-21 18:49:57 -05:00
Marek Olšák
ff71fae440 nir: strip as we serialize to remove the nir_shader_clone call
Serializing stripped NIR is faster now.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-21 18:49:57 -05:00
Christian Gmeiner
8acaab1aa7 etnaviv: add drm-shim
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-21 22:56:04 +00:00
Eric Engestrom
609a6ae23e vk_util: drop duplicate formats in vk_format_map[]
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-21 22:52:40 +00:00
Jonathan Marek
773d640efa turnip: implement UBWC
This enables UBWC for everything except 3D textures.

It breaks many image_to_image copies but those aren't important and it can
be worked around later (image_to_image copy needs to be done in two steps,
decode from the source format and then encode to the destination format).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-21 22:21:57 +00:00
Jonathan Marek
91fd83d142 freedreno/regs: update UBWC related bits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-21 22:21:57 +00:00
Vinson Lee
6613a4a029 swr: Fix build with llvm-10.0.
Fix build error after llvm-10.0 commit 1dfede3122ee ("Move
CodeGenFileType enum to Support/CodeGen.h").

../src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp: In member function ‘void JitManager::DumpAsm(llvm::Function*, const char*)’:
../src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp:428:45: error: ‘CGFT_AssemblyFile’ is not a member of ‘llvm::TargetMachine’
             *pMPasses, filestream, nullptr, TargetMachine::CGFT_AssemblyFile);
                                             ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-11-21 13:20:08 -08:00
Rhys Perry
29d131d619 aco: fix copy+paste error
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-21 20:28:57 +00:00
Rhys Perry
d1b9deeea8 aco: improve waitcnt insertion around loops
Do this by repeating processing of loops until no progress is made.

Totals from affected shaders:
SGPRS: 162576 -> 162576 (0.00 %)
VGPRS: 145228 -> 145228 (0.00 %)
Spilled SGPRs: 668 -> 668 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 15778640 -> 15771336 (-0.05 %) bytes
LDS: 146 -> 146 (0.00 %) blocks
Max Waves: 6087 -> 6087 (0.00 %)

v2: use block_kind_loop_header/block_kind_loop_exit to repeat at the end
    of loops instead of at each continue

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-21 20:28:57 +00:00
Rob Clark
1a8c49d76c freedreno/perfctrs/fdperf: periodically restore counters
When GPU is idle and suspends, the currently selected countables
will all reset to the first one.  So periodically restore the selected
countables.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
5a13507164 freedreno/perfcntrs: add fdperf
Port from the envytools tree, but converted to use the .c tables for
describing the perfcounter groups/countables, rather than using rnndec
to get this at runtime from the register xml.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
b2338a5b00 freedreno/perfcntrs/a6xx: remove RBBM counters
Currently this are getting blocked by the kernel.. these counters don't
seem to be the most useful ones, and to use them we'd have to somehow
probe the kernel by submitting cmdstream to write the selector regs and
see if that triggers a GPU fault.  So let's just skip them.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
6a517b3079 freedreno/perfctrs/a2xx: move CP to be first group
fdperf expects this, to find the ALWAYS_COUNT counter

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
e35c4e6ad2 freedreno/perfcntrs: add accessor to get per-gen tables
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
b21f03ae7e freedreno/perfcntrs: move to shared location
This should eventually be useful for VK_KHR_performance_query as well.
And in the more near term, for fdperf.

Attempt to not break android build is best-effort and untested.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:03 +00:00
Rob Clark
6727114cba freedreno/perfcntrs: remove gallium dependencies
Prep work to move to a shared location.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:02 +00:00
Rob Clark
3fb6aaf42e freedreno/perfcntrs: small cleanup
When we had one gen supporting performance counters, it made sense to
have these builder macros in the .c file with the table.  But time has
come to de-duplicate.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 20:01:02 +00:00
Dave Airlie
cce07ea835 nir: fix deref offset builder
Use the correct bit size

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:41 +10:00
Dave Airlie
7325f6ac98 vtn/opencl: add clz support
This is needed for OpenCL

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:41 +10:00
Dave Airlie
e3b21dfcb1 nouveau: request ufind_msb64 lowering in the frontend.
This passes the piglit CL builtin-ulong-clz-1.0.generated.cl
test.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-11-22 04:37:41 +10:00
Dave Airlie
d0d96053e6 nir: add 64-bit ufind_msb lowering support. (v2)
This adds the option to lower 64-bit ufind_msb opcodes.

v2: use split_x/y removes component loops (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:37 +10:00
Dave Airlie
12913bcf86 spirv/nir/opencl: handle some multiply instructions.
This adds support for some missing 24-bit and hi multiply
variants.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:25 +10:00
Dave Airlie
5375c30234 spirv: get the correct type for function returns.
This needs to be derived from the address format, not always 1/32.

Suggested by Jason

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:25 +10:00
Dave Airlie
b62a925ad1 spirv: don't store 0 to cs.ptr_size for non kernel stages.
cs is a union so storing this there is wrong.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-22 04:37:25 +10:00
Jonathan Marek
1496e1164f util: add missing R8G8B8A8_SRGB format to vk_format_map
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-21 17:46:27 +00:00
Elie Tournier
72b44d148d docs: fix ascii html representation
v2 (Eric): Use more readable ascii version

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-21 16:51:18 +00:00
Elie Tournier
64d7bd96b8 Docs: remove duplicate meson docs for windows
This block is duplicated, we already have the windows instruction above.

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-21 16:51:18 +00:00
Eric Anholt
dd76a6f198 ci: Move freedreno's parallelism to the runner instead of gitlab-ci jobs.
I set the runners to concurrency=1, so they serve only one gitlab-ci job
at at time.  Swap over to using the parallel runner now to keep the
runners busy, more efficiently than spawning many docker containers and
downloading artifacts multiple times, and producing easier-to-understand
results for browsing on the web.

This bumps the a306 runners to 4x parallel instead of 2x like before, but
cheza gles3 drops from 6 to 4.  Current rough timings of the jobs (if no
container download):

db410c-gles2: 5:00
a630-gles2: 1:30
a630-gles3: 6:00
a630-gles31: 5:30

a630-gles3 is a bit longer than I like, but it should come back down once
I can sort out the NIR algebraic rewinding.
2019-11-21 05:48:17 -08:00
Iago Toral Quiroga
c573b50179 glsl: add missing initialization of the location path field
This was apparently missed in 67b32190f3, which added support
for ARB_shading_language_include to #line, including the 'path'
field for the location.

Fixes crashes in CTS with all drivers as they attempt to access
an uninitialized path string during parsing.

Fixes: 67b32190f3 ("glsl: add ARB_shading_language_include support to #line")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2132
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jose Maria Casanova <jmcasanova@igalia.com>
2019-11-21 12:55:15 +01:00
Rhys Perry
1a0500cd04 docs: update features.txt for RADV
[skip ci]

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-21 11:00:50 +00:00
Michel Dänzer
32618ee719 gitlab-ci: Directly use host-mapped directory for ccache
Use hardcoded /cache/mesa/ccache for the cache, so it will be shared by
all jobs of all Mesa projects running on the same runner host. This
should increase the hit rate and decrease the worst case storage used.

Further benefits of directly using a host-mapped directory:

* Saves up to ~1 minute per job for restoring and saving the cache
  contents via the GitLab CI cache mechanism
* Cache contents generated by failed jobs are no longer lost
* Jobs running in parallel on the same runner host can get hits from
  each other

Also enable compression, so the default maximum cache size of 5G might
be sufficient.

v2:
* Move CCACHE_DIR variable to the .build-linux template

Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
2019-11-21 10:13:43 +01:00
Samuel Pitoiset
0d1085ac4a gitlab-ci: remove now useless meson-swr-glvnd build job
All things are already part of meson-main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:35:05 +01:00
Samuel Pitoiset
7362176cfe gitlab-ci: build GLVND in meson-clang
Building GLVND in meson-main doesn't work because this disables
libEGL and it's needed for running shader-db.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:35:05 +01:00
Samuel Pitoiset
e6d26d77a3 gitlab-ci: build swr in meson-main
Now that debugoptimized isn't set and that all test jobs depend on
meson-testing, enabling swr shouldn't slowdown the CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:35:05 +01:00
Samuel Pitoiset
6cf9b53fa2 gitlab-ci: do not build with debugoptimized for meson-main
This should reduce compile time because optimizations are costly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:35:05 +01:00
Samuel Pitoiset
66b5627074 gitlab-ci: add a job that only build things needed for testing
For turnip and RADV testing, we will need a debugoptimized build
without UBSAN. This introduces meson-testing which builds only the
things that are needed by the test stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:35:04 +01:00
Samuel Pitoiset
eab328fbe9 gitlab-ci: fix ldd check for Vulkan drivers
The 'dri' directory isn't created when building Vulkan drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:34:08 +01:00
Samuel Pitoiset
24dd730efc gitlab-ci: move building piglit into a separate script
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-21 09:33:39 +01:00
Samuel Pitoiset
8fc8e8e8be pipe-loader: check that the pointer to driconf_xml isn't NULL
This happens when mesa is built with only swrast. The default
driver being kmsro and the default driconf file being v3d,
it's NULL and then strdup crashes.

This fixes a crash with piglit spec/egl_mesa_query_driver/conformance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-21 07:34:20 +01:00
Alyssa Rosenzweig
046097c092 panfrost: Add the lod_bias field
Enough trial and error ... just think even *more* Midgard about where
this field might be!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-21 06:05:12 +00:00
Timothy Arceri
cd6322366d compiler: move build definition of pp_standalone_scaffolding.c
This should fix android build issues while still allowing scons to
build the standalone compiler.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2129

Reviewed-by: Mark Janes <mark.a.janes@intel.com>
2019-11-21 16:07:08 +11:00
Karol Herbst
5934a53bfe nir/validate: validate num_components on registers and intrinsics
also make 8 and 16 compoments invalid. We will enable that later again
when we actually support it.

v2: fix validation of nir_intrinsic_instr::num_components
    correct validation of instr->num_components

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-21 01:10:24 +01:00
Mark Janes
eae8dfef58 Revert "st/mesa: keep serialized NIR instead of nir_shader in st_program"
This reverts commit db0c89d4bf.

Gitlab: mesa/mesa#2128
Acked-by: Marek Olšák <maraeo@gmail.com>
2019-11-20 15:22:32 -08:00
Mark Janes
f1f19b6445 Revert "st/mesa: call nir_serialize only once per shader"
This reverts commit 3a8d686889.

Acked-by: Marek Olšák <maraeo@gmail.com>
2019-11-20 15:22:32 -08:00
Arno Messiaen
721d82cf06 lima/ppir: add lod-bias support
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-11-20 22:24:00 +00:00
Jason Ekstrand
2fca325ea6 Revert "i965/fs: Merge CMP and SEL into CSEL on Gen8+"
This reverts commit 52c7df1643.  The pass,
while clearly useful for some shaders, has at least three bugs that I
was able to find fairly quickly:

 1. It doesn't work for type-converting MOVs because f > 0 is not the
    same as f2i(f) > 0

 2. CSEL is a 3src instruction and only supports one source type; it
    doesn't take this into account and tries to create instructions
    which do a F compare and a D select.  This is especially nasty to
    debug because you don't see that in the dumped assembly because we
    don't properly assert that types are the same in codegen.

 3. While you can handle 2, in theory, by reinterpreting types, you
    can't do that in the presence of source modifiers.  This pass
    doesn't even attempt to detect that.

Those are just the ones I found with the one almost trival shader I was
debugging.  There very likely may be more and.  Best thing to do for now
is just shut it off until someone has the time to figure out how to do
this properly and write tests to ensure it's correct.

Fixes: 3cb085e6d61a "i965/fs: Merge CMP and SEL into CSEL on Gen8+"
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-11-20 20:47:32 +00:00
Daniel Schürmann
8d7621a53f radv: Enable Subgroup Arithmetic and Clustered for SI
This patch also allows to enable VK_AMD_shader_ballot on SI.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-20 20:31:45 +00:00
Daniel Schürmann
0cbcfc071e amd/llvm: Add Subgroup Scan functions for SI
The idea of this implementation is taken from the ROCm Device Libs:
https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/ockl/src/wfredscan.cl

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-20 20:31:45 +00:00
Andreas Baierl
fca2d3ce3f lima/streamparser: Add findings introduced with gl_PointSize
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2019-11-20 19:24:12 +00:00
Andreas Baierl
804c295039 lima/streamparser: Fix typo in vs semaphore parser
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2019-11-20 19:24:12 +00:00
Yevhenii Kolesnikov
9af22ccddc meson: Fix linkage of libgallium_nine with libgalliumvl
Do not link libgallium_nine with libgalliumvl_stub if it's already
linked with libgalliumvl. Linking with stub leads to "duplicate
symbol" errors.

Fixes: 6b4c7047d5
       ("meson: build gallium nine state_tracker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2040

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-20 19:16:20 +00:00
Dylan Baker
bcfc9c0fec docs/release-calendar: Update for extended 19.3 rc period 2019-11-20 09:57:05 -08:00
Dylan Baker
ff21acc91c docs: update calendar, add news item and link release notes for 19.2.5 2019-11-20 09:22:29 -08:00
Dylan Baker
d35429239b docs/relnotes/19.2.5: Add SHA256 sum 2019-11-20 09:19:02 -08:00
Dylan Baker
6567b2daa9 docs: Add relnotes for 19.2.5 2019-11-20 09:19:00 -08:00
Rhys Perry
ca2de7ae9c nir/large_constants: use nir_index_vars and nir_variable::index
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-20 15:05:42 +00:00
Rhys Perry
9f92e8b721 nir: add nir_variable::index and nir_index_vars
This will be useful as a deterministic identifier/index for the variable.

v2: fix comment style

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v1)
2019-11-20 15:05:42 +00:00
Rhys Perry
45a0b53490 nir: make nir_variable::{num_members,num_state_slots} a uint16_t
Doesn't shrink it (at least, on x86-64) and leaves space for more members.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-20 15:05:42 +00:00
Samuel Pitoiset
645332f3f5 docs: add missing new features for RADV
[skip ci]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-20 16:04:15 +01:00
Hyunjun Ko
02f4c39b8d freedreno/ir3: enable half precision for pre-fs texture fetch
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Hyunjun Ko
407f8c71d3 freedreno/ir3: fixup when changing to mad.f16
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Hyunjun Ko
d0f38394b1 freedreno/ir3: fix printing output registers of FS.
Fixes: cea39af2fb ("freedreno/ir3: Generalize ir3_shader_disasm()")

Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
37f5395783 freedreno/ir3: Enabling lowering 16-bit flrp
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Hyunjun Ko
35124b0311 freedreno: support 16b for the sampler opcode
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
b934716bd8 freedreno/ir3: Implement f2b16 and i2b16
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
030b046df8 freedreno/ir3: Add implementation of nir_op_b16csel
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
f0a046024d freedreno/ir3: Support 16-bit comparison instructions
v2. [Hyunjun Ko (zzoon@igalia.com)]
Avoid using too much open code like "instr->regs[n]->flags |= FOO"

v3. [Hyunjun Ko (zzoon@igalia.com)]
Remove redundant code for both 16b and 32b operations.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Hyunjun Ko
138542499f freedreno/ir3: cleanup by removing repeated code
Prep-work for the corresponding patch.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
f6b5abe91a nir/lower_alu_to_scalar: Support lowering 8- and 16-bit reduce ops
Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
634eb9c04b nir: Add a 8-bit bool type
Adds nir_type_bool8 as well as 8-bit versions of all the bool
opcodes.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
0f5640c577 nir: Add a 16-bit bool type
Adds nir_type_bool16 as well as 16-bit versions of all the bool
opcodes.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
2ec97e78a9 nir/opcodes: Add a helper function to generate reduce opcodes
Adds binop_reduce_all_sizes which generates both 1-bit and 32-bit
versions of the reduce operation. This reduces the code duplication a
bit and will make it easier to later add 16-bit versions as well.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 14:09:43 +01:00
Neil Roberts
9a96afb97e nir/opcodes: Add a helper function to generate the comparison binops
Adds binop_compare_all_sizes which generates both 1-bit and 32-bit
versions of the comparison operation. This reduces the code
duplication a bit and will make it easier to later add 16-bit versions
as well.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 14:09:43 +01:00
Samuel Pitoiset
7ecd8a3471 radv: enable VK_KHR_shader_subgroup_extended_types on GFX6-GFX7
Most of DEQP-VK.subgroups are skipped because 16-bit float aren't
supported but others pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-20 11:09:58 +00:00
Alejandro Piñeiro
b4bc59e37e v3d: adds an extra MOV for any sig.ld*
Specifically when we are in non-uniform control flow, as we would need
to set the condition for the last instruction. If (for example) a
image atomic load stores directly their value on a NIR register,
last_inst would be a nop, and would fail when set the condition.

Fixes piglit test:
spec/glsl-es-3.10/execution/cs-ssbo-atomic-if-else-2.shader_test

Fixes: 6281f26f06 ("v3d: Add support for shader_image_load_store.")

v2: (Changes suggested by Eric Anholt)
   * Cover all sig.ld* signals, not just ldunif and ldtmu, as all of
     them have the same restriction.
   * Update comment explaining why we add a MOV in that case
   * Tweak commit message.

v3:
   * Drop extra set of parens (Eric)
   * Add missing ld signal to is_ld_signal to fix shader-db regression.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-20 11:21:16 +01:00
Jose Maria Casanova Crespo
d983055184 v3d: Fix predication with atomic image operations
Fixes dEQP test:
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.image_atomic_multiple_interleaved_write_read

Fixes piglit test:
spec/glsl-es-3.10/execution/cs-image-atomic-if-else.shader_test

Fixes: 6281f26f06 ("v3d: Add support for shader_image_load_store.")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-20 11:20:55 +01:00
Tomeu Vizoso
36b099a7b0 panfrost: Don't print the midgard_blend_rt structs on SFBD
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 08:04:25 +01:00
Tomeu Vizoso
2dc720cb2c gitlab-ci: Fix dir name for VK-GL-CTS sources
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 08:03:44 +01:00
Tomeu Vizoso
409f6c40ca panfrost: Rework buffers in SFBD
Support cases such as depth-only renders and only set stencil buffers
when needed, to match the blob's behaviour.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 08:03:36 +01:00
Tomeu Vizoso
697f02c2a1 panfrost: Just print tiler fields as-is for Tx20
The tiler unit in these GPUs is quite different and we haven't reverse
engineered enough of it yet to validate and pretty print it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-20 08:00:41 +01:00
Alyssa Rosenzweig
fcf144d96a pan/midgard: Introduce quirks checks
Rather than open-coding checks on gpu_id in the compiler, let's track
quirks applying to whatever we're compiling for, to allow us to manage
the complexity of many heterogenous GPUs in the compiler.

It was discovered that a workaround used on T720 is also required on
T820 (and presumably T830), so let's fix this. This will also decrease
friction as we continue improving T720 support.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-20 07:41:39 +01:00
Timothy Arceri
614fba0ce1 gitlab-ci: update for arb_shading_language_include 2019-11-20 05:05:56 +00:00
Timothy Arceri
530d3b2900 gitlab-ci: bump piglit checkout commit 2019-11-20 05:05:56 +00:00
Timothy Arceri
af432be538 mesa: enable ARB_shading_language_include
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/999

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
49cdbba9f6 mesa: implement glCompileShaderIncludeARB()
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
bad2c77aa8 mesa: add shader include lookup support for relative paths
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
1201d3377e mesa: add support cursor support for relative path shader includes
This will allow us to continue searching the current path for
relative shader includes.

From the ARB_shading_language_include spec:

   "If it is quoted with double quotes in a previously included
   string, then the first search point will be the tree location
   where the previously included string had been found."

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
db5197cec5 glsl: delay compilation skip if shader contains an include
If the shader contains an include when need to first run the
preprocessor before deciding if we can skip compilation based
on the shader cache.

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
17df8f8b5d glsl: add can_skip_compile() helper
We will reuse this in the following commit.

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:56 +00:00
Timothy Arceri
5327b756bf glsl: error if #include used while extension is disabled
In other words make sure the shader does this:

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
13a1426b97 glsl: add preprocessor #include support
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
e0fd2fa689 glsl: pass gl_context to glcpp_parser_create()
This is a small tidy up and will be useful in the following commit.

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
67b32190f3 glsl: add ARB_shading_language_include support to #line
From the ARB_shading_language_include spec:

   "#line must have, after macro substitution, one of the following
    forms:

       #line <line>
       #line <line> <source-string-number>
       #line <line> "<path>"

    where <line> and <source-string-number> are constant integer
    expressions and <path> is a valid string for a path supplied in the
    #include directive. After processing this directive (including its
    new-line), the implementation will behave as if it is compiling at
    line number <line> and source string number <source-string-number>
    or <path> path. Subsequent source strings will be numbered
    sequentially, until another #line directive overrides that
    numbering."

Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
2497c51717 mesa: implement glDeleteNamedStringARB()
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
f2d01cac7e mesa: split _mesa_lookup_shader_include() in two
The new local function lookup_shader_include() will be used by
glDeleteNamedStringARB() in the following patch.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
ae2e41841f mesa: implement glGetNamedStringivARB()
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
575137e613 mesa: implement glIsNamedStringARB()
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
fafda32127 mesa: make error checking optional in _mesa_lookup_shader_include()
This will be usefull when implementing glIsNamedStringARB() which
doesn't do error checking, it just returns false for invalid
lookups instead.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
a47bfbe189 mesa: implement glGetNamedStringARB()
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
fc573c9816 mesa: add glNamedStringARB() support
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
628d34fddd mesa: add copy_string() helper
This will be used by the various ARB_shading_language_include
functions in the following patches.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
8acab84f93 mesa: add _mesa_lookup_shader_include() helper
This will be used both by the glsl compiler and the GL API.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
643a533fc2 mesa: add helper to validate tokenise shader include path
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
06f33d82ca mesa: add ARB_shading_language_include infrastructure to gl_shared_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
35108caa71 glsl: add infrastructure for ARB_shading_language_include
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Timothy Arceri
906f1a2933 mesa: add ARB_shading_language_include stubs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-11-20 05:05:55 +00:00
Bas Nieuwenhuizen
4eb2a1dc6f radv: Do not change scratch settings while shaders are active.
When the scratch ringbuffer settings are changed, the shader unit has
to be idle or we will have shaders using old and new settings.

That combination is not supported on the HW (likely the offset is
ringbuffer idx * WAVESIZE * 1024).

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-20 01:18:36 +00:00
Eric Anholt
bdf03b738d turnip: Drop the copy of the formats table.
Now that we can (mostly) generate a pipe format for a VkFormat, use that
to answer queries about formats.  This will let us refactor the freedreno
format table surface layout code to be shared between gallium and vulkan.

This causes us to expose fewer formats for now (on a 1/100 CTS run I'm
doing, skips go from 3671 to 3835 out of 5145 tests).  Fails stay about
the same (478 -> 434, but the run is pretty flaky and we're doing fewer
tests now).

v2: Rebase on master, throw a finishme on missing vk-to-pipe formats that
    tu used to support.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (v1)
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-11-19 15:35:52 -08:00
Eric Anholt
3a28281bf8 util: Add a mapping from VkFormat to PIPE_FORMAT.
I'm planning on using this from radv and tu for queries about formats.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-11-19 15:35:52 -08:00
Marek Olšák
36c055c9b7 winsys/amdgpu: detect noop dependencies on the same ring correctly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:32:56 -05:00
Marek Olšák
e7fb9c73a7 ac: fill num_rings for remaining IPs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:31:53 -05:00
Marek Olšák
e9cc4f670f ac: add radeon_info::num_rings and move ring_type to amd_family.h
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:31:53 -05:00
Marek Olšák
654efd38bb nir: don't use GLenum16 in nir.h
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-19 18:20:12 -05:00
Marek Olšák
ec7d37c9c0 nir: move data.descriptor_set above data.index for better packing
4 bytes down

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-19 18:20:10 -05:00
Marek Olšák
b160acb9f5 glsl_to_nir: rename image_access to mem_access
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-19 18:20:09 -05:00
Marek Olšák
193e2c9625 nir/print: only print image.format for image variables
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-19 18:20:07 -05:00
Marek Olšák
ebe7579655 nir: move data.image.access to data.access
The size of the data structure doesn't change.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-19 18:20:05 -05:00
Marek Olšák
3a8d686889 st/mesa: call nir_serialize only once per shader
It was called twice.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
db0c89d4bf st/mesa: keep serialized NIR instead of nir_shader in st_program
This decreases memory usage, because serialized NIR is more compact.

If shader_has_one_variant is true and the shader is uncached, the first
variant is created from nir_shader, otherwise the first variant and
all other variants are created from serialized NIR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
610fb0e19c st/mesa: call nir_sweep in st_finalize_nir
This is invoked sooner before (pre-)compiling the first variant and is
also applied to fixed-func and ARB programs.
2019-11-19 18:02:06 -05:00
Marek Olšák
4e70cba638 st/mesa: subclass st_vertex_program for VP-specific members
Inheritance:
    gl_program -> st_program -> st_vertex_program

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
16e5f13b64 st/mesa: more cleanups after unification of st_vertex/common_program
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
6b3d72b041 st/mesa: rename occurences of stcp to stp to correspond to st_program
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
1375217116 st/mesa: cleanups after unification of st_vertex/common program
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
5fed208285 st/mesa: rename st_common_program to st_program
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
2e39e8b972 st/mesa: trivially merge st_vertex_program into st_common_program
a later commit will add back st_vertex_program as a subclass of
st_common_program

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
c97df7b4c7 st/mesa: consolidate and simplify code flagging program::affected_states
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
f71e93db0a st/mesa: initialize affected_states and uniform storage earlier in deserialize
This matches the uncached codepath.

affected_states was used before initialization, which was technically
a bug, but probably not reproducible due to _NEW_PROGRAM rebinding
everything.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
60398e2d45 st/mesa: start deduplicating some program code
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
445ec0fc63 st/mesa: decrease the size of st_fp_variant_key from 48 to 40 bytes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Marek Olšák
2c8652f98a st/mesa: rename delete_basic_variant -> delete_common_variant
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-19 18:02:06 -05:00
Eric Engestrom
51e214c1db anv: add missing "fall-through" annotation
CoverityID: 1455884
Fixes: c1c346f166 ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-19 22:03:00 +00:00
Eric Engestrom
99788de909 egl: use EGL_CAST() macro in eglmesaext.h
Allows eglmesaext.h to be used in C++ code.

This aligns this file with the rest of EGL.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
2019-11-19 22:00:24 +00:00
Eric Engestrom
344859c32d vulkan: delete typo'd header
Two files exist in that directory:
- vulkan_xlib_randr.h
- vulkan_xlib_xrandr.h

Both were imported in 205c271562 ("vulkan: Update the XML and
headers to 1.1.70") with identical contents (ie. the
VK_EXT_acquire_xlib_display extension), but the former was never
included anywhere and can't be found upstream [1], while the latter is
included in vulkan.h and found upstream.

[1] https://github.com/KhronosGroup/Vulkan-Headers/tree/master/include/vulkan

Fixes: 205c271562 ("vulkan: Update the XML and headers to 1.1.70")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-19 21:56:22 +00:00
Eric Engestrom
0d69c2e932 CL: sync C++ headers with Khronos
https://github.com/KhronosGroup/OpenCL-CLHPP at commit
cf9fc1035e8298c7ce65ee33066a660fd9892ebb

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 21:50:26 +00:00
Eric Engestrom
a15aef0d39 CL: sync C headers with Khronos
https://github.com/KhronosGroup/OpenCL-Headers at commit
0d5f18c6e7196863bc1557a693f1509adfcee056

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 21:50:25 +00:00
Rafael Antognolli
dadb6ebbd1 intel: Add workaround for stencil state.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
2019-11-19 21:43:09 +00:00
Jonathan Marek
d2cf3cad91 turnip: fix sRGB GMEM clear
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-19 21:35:37 +00:00
Jonathan Marek
d68acdb3b9 turnip: implement CmdClearColorImage/CmdClearDepthStencilImage
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-19 21:35:37 +00:00
Rhys Perry
7eb7969213 radv/aco: enable VK_KHR_shader_subgroup_extended_types
We could enable it on GFX10 if LLVM wasn't used as a fallback for
unsupported stages. Note that the CTS only tests it if
VK_KHR_shader_float16_int8 is enabled, even though it's not a
requirement.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-19 18:58:04 +00:00
Rhys Perry
56c06c79fc aco: implement 64-bit integer reductions
The multiplication reduction is larger than it could be, but it should be
easier to implement this way.

No failures with dEQP-VK.subgroups.*int64* except those caused by LLVM
being used for other stages.

v2: don't call setFixed() for v_add carry-out, since setHint sets physReg
v3: add and use emit_vadd32() helper
v4: use num_opcodes instead of last_opcode

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v3)
2019-11-19 18:58:04 +00:00
Rhys Perry
33277bd66e aco: refactor reduction lowering helpers
Should make 64-bit integer reductions easier to implement.

v4: use num_opcodes instead of last_opcode

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v3)
2019-11-19 18:56:21 +00:00
Samuel Pitoiset
c93f2cefd5 radv: advertise VK_KHR_shader_subgroup_extended_types on GFX8-GFX9
This extension allows to use subgroup operations with 8 and 16-bits

Untested on GFX6-GFX7, and most of subgroup operations are broken
on GFX10, so don't enable it for now. Not enabled on ACO because
it's still doesn't support 8-bits/16-bits.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
80c71cbbd8 ac: add 16-bit float support to ac_build_alu_op()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
670aa24c69 ac: add 8-bit and 16-bit supports to ac_build_optimization_barrier()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
21a9243f5e ac: add 8-bit and 16-bit supports to ac_build_wwm()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
ef352a2466 ac: add 8-bit and 16-bit supports to get_reduction_identity()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
c8af1d51d4 ac: add 8-bit and 16-bit supports to ac_build_swizzle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
1565118d8f ac: add 8-bit and 16-bit supports to ac_build_dpp()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
2113867f0c ac: add 8-bit and 16-bit supports to ac_build_set_inactive()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
c29514bd22 ac: add 8-bit and 16-bit supports to ac_build_readlane()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
58d5ab98a3 ac: add 8-bit and 16-bit supports to ac_build_shuffle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
204cf54b70 ac: remove useless cast in ac_build_set_inactive()
The return type is always the src type (32 or 64 bits).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Samuel Pitoiset
194bee193c spirv: fix lowering of OpGroupNonUniformAllEqual
It should rely on the source type, not on the return type which
is always a boolean anyways, so vote_feq was never selected. For
OpSubgroupAllEqualKHR it's always an integer comparison.

This fixes some VK_KHR_shader_subgroup_extended_types tests with RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-19 18:01:13 +00:00
Tomeu Vizoso
2941a734a0 gitlab-ci: Remove limit on kernel logging
We don't seem to fault any more when running dEQP GLES2, and we don't
scrape serial output any more anyway so no problems should be caused by
that.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 15:39:13 +01:00
Pierre-Eric Pelloux-Prayer
99f0feb9e2 mesa: fix warning in 32 bits build
Fixes: febedee4f6 ("mesa: add EXT_dsa glGetVertexArray* 4 functions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
3a5a55e5a5 mesa: enable EXT_direct_state_access
Always enabled; this doesn't require any driver work, it's just
core mesa bits.

quick_gl.txt is also updated because previously piglit ext_dsa
tests were skipped.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
1ef297645c mesa: add ARB_sparse_buffer NamedBufferPageCommitmentEXT function
The spec is unclear on how to handle the buffer argument so we reuse
the logic from the EXT_direct_state_access spec.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
8b6d19413f mesa: add ARB_vertex_attrib_binding glVertexArray* functions
We can't simply alias ARB_direct_state_access functions because
those fail if the vao has never been bound before.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
657396aa10 mesa: extend vertex_array_attrib_format to support EXT_dsa
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
bb2241bf06 mesa: implement ARB_texture_storage_multisample + EXT_dsa functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
a0d667036d mesa: add ARB_texture_buffer_range glTextureBufferRangeEXT function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
b78e2a197a mesa: add ARB_instanced_arrays EXT_dsa function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
a807b8c0a8 mesa: add ARB_gpu_shader_fp64 selector-less functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
e3385eb0c1 mesa: add ARB_clear_buffer_object named functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:45 +01:00
Pierre-Eric Pelloux-Prayer
442fd3d007 mesa: add ARB_vertex_attrib_64bit VertexArrayVertexAttribLOffsetEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:44 +01:00
Pierre-Eric Pelloux-Prayer
8cfb3e4ee5 mesa: add ARB_framebuffer_no_attachments named functions
The wording in ARB_framebuffer_no_attachments and EXT_direct_state_access
is different.
In the former framebuffer names must have been generated using glGenFramebuffers
before using the named functions.
In the latter framebuffer names have no such constraints, so we can't use
the _mesa_lookup_framebuffer_dsa function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:44 +01:00
Pierre-Eric Pelloux-Prayer
dc057f638c mesa: update features.txt to reflect EXT_dsa status
All features from the EXT_dsa spec are implemented.

Interactions with other specs:
- GL_AMD_gpu_shader_int64: not needed, since it's not enabled in
  compatibility profile.
- GL_ARB_bindless_texture is DONE
    "INVALID_OPERATION is generated when calling various functions
    to modify the state of a texture object from which handles have
    been extracted"
- GL_ARB_buffer_storage/GL_EXT_buffer_storage is DONE (NamedBufferStorageEXT function)
- GL_ARB_texture_storage is DONE (3 TextureStorage*DEXT functions)
- GL_ARB_vertex_attrib_binding is DONE (6 VertexArray* functions)
- GL_EXT_external_buffer is not supported by Mesa

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-19 08:49:44 +01:00
Alyssa Rosenzweig
8b1548a12f panfrost: Set PIPE_COMPUTE_CAP_ADDRESS_BITS to 64
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 06:22:31 +00:00
Alyssa Rosenzweig
9c28700aaf panfrost: Disable tiling for GLOBAL resources
It doesn't make sense to have nonlinear layouts for a buffer that can be
accessed as direct memory for a compute kernel. Turn that off so things
work as expected.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 06:22:31 +00:00
Alyssa Rosenzweig
21dd7574a8 panfrost: Pass kernel inputs as uniforms
We can take the OpenCL kernel inputs and interpret them as uniforms by
simply reusing the Gallium callback.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 06:22:31 +00:00
Alyssa Rosenzweig
a7b5dd1290 panfrost: Stub out clover callbacks
We don't implement these yet but let's not crash.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-19 06:22:31 +00:00
Miguel Casas-Sanchez
b196958574 i965: Ensure that all 2101010 image imports can pass framebuffer completeness.
Chrome OS would like to import and render to any supported format that has
a corresponding display plane format, and this prevents throwing
framebuffer incomplete for FBOs using these textures.

See: crbug.com/949260

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-19 02:21:12 +00:00
Dave Airlie
1468a4f1f3 nir/serialize: fix serializing functions with no implementations.
Store a flag stating if there was an implmentation, and use
fxn->impl as a temporary flag between deserializsation stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-19 09:30:32 +10:00
Dave Airlie
0fd6b8aa98 nir/serialize: pack function has name and entry point into flags.
Suggested by Jason.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-19 09:30:12 +10:00
Jason Ekstrand
fc72df1d93 iris: Re-enable param compaction
In d1c4e64a69, we added a parameter to tell the back-end compiler to
ignore the param array and just push however many constants you ask it
to push.  I enabled it for iris because this is really what iris wants
but it seems to have caused a number of regressions.  Revert to the old
behavior for now.

Fixes: d1c4e64a69 "intel/compiler: Add a flag to avoid compacting..."
2019-11-18 16:54:07 -06:00
Marek Olšák
189c0cc45b mesa: enable glthread for 7 Days To Die
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-18 17:25:57 -05:00
Iván Briano
ca94717035 intel/compiler: Don't change hstride if not needed
Alignment requirements may have changed the horizontal stride already,
so don't set it if not required to avoid breaking said requirements.

Fixes several tests such as
dEQP-VK.subgroups.vote.graphics.subgroupallequal_int8_t

Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-18 14:19:41 -08:00
Jonathan Marek
3cd44839fa turnip: add x11 wsi
Copied from radv

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-18 22:18:05 +00:00
Jonathan Marek
df9f2adfa3 turnip: add display wsi
Copied from radv (minus the fence change)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-18 22:18:05 +00:00
Jason Ekstrand
7260df5894 nir: Validate that variables are in the right lists
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-18 16:15:30 -06:00
Jonathan Marek
e2b9d6277e etnaviv: blt: set TS dirty after clear
RS engine does this already, it is missing for BLT engine. This fixes
cases where a clear isn't immediately at the start of the frame.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-18 20:59:02 +01:00
Jonathan Marek
d819d4b344 etnaviv: separate PE and RS formats, use only RS only for tiling
There are PE formats not supported by RS, so we can't have a single
to translate both.

Use RS only for same formats until we have a translate_rs_format and test
the possible different format blits.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-18 20:58:14 +01:00
Jonathan Marek
e1a86bd634 etnaviv: blt: use only for tiling, and add missing formats
* Removes the incorrect usage of translate_rs_format
* Disables use of BLT engine for different src/dst format

We only really need the BLT engine for tiling/detiling right now, but it
would be nice to support as many blit cases as possible to avoid using PE
for that.

To deal with different formats we need to:
 * Have a translate_blt_format which has all supported formats
 * Fix the swizzle translation from gallium (current version was wrong)
 * Set the src/dst sRGB bits as needed
 * Find which type conversions the BLT engine can actually do

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-11-18 20:57:40 +01:00
Brian Paul
02c3dad0f3 Call shmget() with permission 0600 instead of 0777
A security advisory (TALOS-2019-0857/CVE-2019-5068) found that
creating shared memory regions with permission mode 0777 could allow
any user to access that memory.  Several Mesa drivers use shared-
memory XImages to implement back buffers for improved performance.

This path changes the shmget() calls to use 0600 (user r/w).

Tested with legacy Xlib driver and llvmpipe.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-18 12:28:59 -07:00
Jason Ekstrand
fdaf8144a8 anv: Emit a NULL vertex for zero base_vertex/instance
If both are zero (the common case), we can emit a null vertex buffer
rather than emitting a vertex buffer with zeros in it.  The packing of
the VERTEX_BUFFER_STATE is faster because no relocation is emitted and
we can avoid creating the vertex buffer which means one less
anv_state_stream_alloc.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
bc9d7836bc anv: Use an anv_state for the next binding table
This is a bit more natural because we're already getting an anv_state
most places in the pipeline.  The important part here, however, is that
we're no longer calling anv_block_pool_map on every alloc_binding_table
call.  While it's probably pretty cheap, it is potentially a linear walk
over the list of BOs and it was showing up in profiles.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
98dc179c1e anv: More carefully dirty state in BindPipeline
Instead of blindly dirtying descriptors and push constants the moment we
see a pipeline change, check to see if it actually changes the bind
layout or push constant layout.  This doubles the runtime performance of
one CPU-limited example running with the Dawn WebGPU implementation when
running on my laptop.

NOTE: This effectively reverts beca63c6c0.  While it was a nice
optimization, it was based on prog_data and we can't do that anymore
once we start allowing the same binding table to be used with multiple
different pipelines.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
22f16ff54a anv: More carefully dirty state in BindDescriptorSets
Instead of dirtying all graphics or all compute based on binding point,
we're now much more careful.  We first check to see if the actual
descriptor set changed and then only dirty the stages used by that
descriptor set.  For dynamic offsets, we keep a bitfield per-stage of
which offsets are actually used in that stage and we only dirty push
constants and descriptors if that stage has dynamic offsets AND those
offsets actually change.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
ca8117b5d5 anv: Use a switch statement for binding table setup
It theoretically could be more efficient but the real point here is that
it's no longer really a matter of dealing with special cases and then
the "real" thing.  The way we're handling binding tables, it's more of a
multi-step process and a switch is more natural.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
9baa33cef0 anv: Rework push constant handling
This substantially reworks both the state setup side of push constant
handling and the pipeline compile side.  The fundamental change here is
that we're no longer respecting the prog_data::param array and instead
are just instructing the back-end compiler to leave the array alone.
This makes the state setup side substantially simpler because we can now
just memcpy the whole block of push constants and don't have to
upload one DWORD at a time.

This also means that we can compute the full push constant layout
up-front and just trust the back-end compiler to not mess with it.
Maybe one day we'll decide that the back-end compiler can do useful
things there again but for now, this is functionally no different from
what we had before this commit and makes the NIR handling cleaner.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
ca91ab8015 anv: Re-arrange push constant data a bit
This moves the compute stuff into a anv_push_constants::cs sub-struct.
It also moves dynamic offsets into the push constants.  This means we
have to duplicate the data per-stage but that doesn't seem like the end
of the world and one day we may wish to make dynamic offsets per-stage
anyway.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
d1c4e64a69 intel/compiler: Add a flag to avoid compacting push constants
In vec4, we can just not run the pass.  In fs, things are a bit more
deeply intertwined.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
aecde23519 anv: Pre-compute push ranges for graphics pipelines
It turns off that emitting push constants is one of the hottest paths in
the driver and ANY work we do there costs us.  By pre-computing things a
bit ahead of time, we shave 5% off the runtime of a CPU-limited example
running with the Dawn WebGPU implementation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
4b392ced2d anv: Stop bounds-checking pushed UBOs
The bounds checking is actually less safe than just pushing the data.
If the bounds checking actually ever kicks in and it's not on the last
UBO push range, then the shrinking will cause all subsequent ranges to
be pushed to the wrong place in the GRF.  One of the behaviors we
definitely don't want is for OOB UBO access to result in completely
unrelated UBOs returning garbage values.  It's safer to just push the
UBOs as-requested.  If we're really concerned about robustness, we can
emit shader code to do bounds checking which should be stupid cheap (a
CMP followed by SEL).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
ebad00d9e7 anv: Delete dead shader constant pushing code
As of 2d78e55a8c, nir_intrinsic_load_constant with a constant offset
is constant-folded so we should never end up with any that trigger
brw_nir_analyze_ubo_ranges.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
0709c0f6b4 anv: Flatten descriptor bindings in anv_nir_apply_pipeline_layout
This lets us stop tracking the pipeline layout.  It also means less
indirection on a very hot path.  As an extra bonus, we can make some of
our data structures smaller.  No measurable CPU overhead improvement.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
fa120cb31c anv: Input attachments are always single-plane
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
0a02f2a278 genxml: Mark everything in genX_pack.h always_inline
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Jason Ekstrand
abfd4651ed anv/pipeline: Assume layout != NULL
In the early days of the driver we allowed layout to be VK_NULL_HANDLE
and used that for some internal pipelines when we wanted to be lazy.
Vulkan doesn't actually allow NULL layouts, however, so there's no
reason to have this check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-18 18:35:14 +00:00
Italo Nicola
59623f211b intel/compiler: remove old comment
This comment was correct some time ago, but since commit
d3c10ad427, it isn't true anymore.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2019-11-18 10:20:34 -08:00
Alyssa Rosenzweig
3663340049 pan/midgard: Use shader stage in mir_op_computes_derivative
A 'normal' texture op may be emitted in a vertex shader on T720 but it
still doesn't take any derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-18 08:48:54 -05:00
Danylo Piliaiev
6f17fe0606 i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround
Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting
3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in
SuperTuxCart and Tropico 6 which was seen only on Haswell.
The reason for this is unknown and fix was found empirically.

The closest mention in PRM is that it should improve performance.
From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS):
 "When the BLEND_STATE pointer changes but not the CC_STATE pointer,
  driver needs to force a CC_STATE pointer change to improve
  blend performance in pixel backend."

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834
Fixes: eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-18 11:00:23 +02:00
Samuel Pitoiset
1ebd9459e7 radv: implement VK_AMD_device_coherent_memory
This extension adds the device coherent and device uncached memory
types. It's known to be slower than non-device coherent memory but
it might be useful for debugging.

This is only exposed for chips that support L2 uncached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-18 08:20:19 +00:00
Samuel Pitoiset
2af7511ed2 ac: add radeon_info::has_l2_uncached
For chips that have uncached device memory (ie. MTYPE_UC).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-18 08:20:19 +00:00
Pierre-Eric Pelloux-Prayer
3c9ea6bdfd radeonsi: enable mesa_glthread for GfxBench
It improves offscreen tests performance.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-18 09:16:18 +01:00
Alyssa Rosenzweig
bc9a7d0699 pan/midgard: Represent ld/st offset unpacked
This simplifies manipulation of the offsets dramatically, fixing some
UBO access related bugs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-17 22:19:31 -05:00
Alyssa Rosenzweig
1798f6bfc3 pan/midgard: Fix masks/alignment for 64-bit loads
These need to be handled with special care.

Oh, Midgard, you're *extra* special.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-17 22:19:31 -05:00
Alyssa Rosenzweig
34a860b9e3 pan/midgard: Expose more typesize helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-17 21:30:14 -05:00
Alyssa Rosenzweig
2236904f72 pan/midgard: Implement non-aligned UBOs
The field is more fine-grained than we had assumed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-17 21:18:45 -05:00
Christian Gmeiner
ee3ad0fad2 etnaviv: rs: upsampling is not supported
This change makes it possible to support different downsample cases
like 4 -> 2 or 4 -> 1.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
2019-11-17 18:42:31 +00:00
Jonathan Marek
75e58d1fae freedreno/registers: fix a6xx_2d_blit_cntl ROTATE
A change from b7093882 got overwritten by 610c8c93

Fixes: 610c8c93 ("freedreno/registers: Update with GS, HS and DS registers")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-17 17:40:53 +00:00
Jonathan Marek
0f5743429c freedreno/ir3: disable texture prefetch for 1d array textures
Prefetch only supports the basic 2D texture case, checking is_array is
needed because 1d array textures pass the coord num_components==2 test.

Fixes: 2a0d45ae ("freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetch")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-17 17:01:18 +00:00
Andreas Baierl
ef9635d0bc lima: Parse VS and PLBU command stream while making a dump
This makes the streams more readable and comparable with the blob's parser
as it parses the VS and PLBU stream and shows the currently known values.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2019-11-17 05:39:17 +00:00
Andreas Baierl
c76eb7ea84 lima: Beautify stream dumps
Change the dump, that the output looks more like the output of
mali-syscall-tracker [1].
This is a preparation for a more detailed stream analysis.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>

[1]: https://gitlab.freedesktop.org/lima/mali-syscall-tracker
2019-11-17 05:39:17 +00:00
Aaron Watry
3b3494174d clover/llvm: fix build after llvm 10 commit 1dfede3122ee
CodeGenFileType moved from ::llvm::TargetMachine in
llvm/Target/TargetMachine.h to ::llvm:: in llvm/Support/CodeGen.h

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2019-11-15 22:54:31 -06:00
Mauro Rossi
09ab297e9f android: util/format: fix include path list
To avoid following building error:

out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_util_intermediates/format/u_format_table.c:30:10:
fatal error: 'u_format.h' file not found
         ^~~~~~~~~~~~
1 error generated.

Fixes: 882ca6d ("util: Move gallium's PIPE_FORMAT utils to /util/format/")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2019-11-16 00:06:31 +01:00
Mauro Rossi
3cd522c70a android: radeonsi: fix build error due to wrong u_format.csv file path
GEN10_FORMAT_TABLE_INPUTS requires correction of u_format.csv file path
in order to avoid following build error:

ninja: error: 'external/mesa/util/format/u_format.csv',
needed by 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/gfx10_format_table.h',
missing and no known rule to make it

Fixes: 882ca6d ("util: Move gallium's PIPE_FORMAT utils to /util/format/")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2019-11-15 23:20:03 +01:00
Eric Anholt
b30589cbd3 mesa/st: Reuse st_choose_matching_format from st_choose_format().
We had this ad-hoc exact size matching for unsized internalformats,
but st_choose_matching_format() can do exactly what we want.  This
means, that, for example, we'll now prefer the matching ordering for
565/565_REV if the driver supports both orders.  We also pass
Unpack.SwapBytes through from ChooseTextureFormat so that we can hit
the memcpy path for 8888 formats when that flag is set.

Some interesting format choice changes from this (on softpipe):
intf/form/type        before            after
----------------------------------------------------
RGBA/RGBA/USHORT:     R8G8B8A8_UNORM -> RGBA_UNORM16
RGB/RGBA/8888:        X8B8G8R8_UNORM -> R8G8B8X8_UNORM
RGB/ABGR/8888_REV:    X8B8G8R8_UNORM -> R8G8B8X8_UNORM
RGBA/RGBA/5551:       B5G5R5A1_UNORM -> A1B5G5R5_UNORM
RGBA/RGBA/4444:       R8G8B8A8_UNORM -> A4B4G4R4_UNORM
RGBA/GL_RGBA/1010102: R8G8B8A8_UNORM -> A2B10G10R10_UNORM
DEPTH/DEPTH/UINT:     Z24X8          -> Z_UNORM32
DEPTH/DEPTH/USHORT:   Z24X8          -> Z_UNORM16

v2: Make sure that the baseformat still matches.  v1 would pick
    MESA_FORMAT_L16_UNORM for RED/LUMINANCE/SHORT, when we clearly
    want a red format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-15 20:32:17 +00:00
Eric Anholt
bc2b14a4a3 mesa: Don't put sRGB formats in the array format table.
sRGB vs unorm was the only conflict case being guarded against in this
function.  Before the PIPE_FORMAT conversion, we always listed the
unorm before the sRGB in the enums, but PIPE_FORMAT_A8B8G8R8_SRGB
happens to be before _UNORM.  We always want the unorm result here.

Fixes: 807a800d8c ("mesa: Redefine MESA_FORMAT_* in terms of PIPE_FORMAT_*.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-15 20:32:17 +00:00
Eric Anholt
e5b06008f1 mesa/st: Simplify st_choose_matching_format().
We now have a nice helper function for finding those memcpy formats,
without needing to go through each entry of the mesa format table to
see if it happens to match.

While looking at sysprof of a softpipe GLES2 CTS run, we were spending
~8% of the CPU on ChooseTextureFormat.  With this, roughly the same
region of the testsuite was .4%.

v2: Add Ken's fix for canonicalizing array formats.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-15 20:32:17 +00:00
Kenneth Graunke
69f109cc37 mesa: Handle GL_COLOR_INDEX in _mesa_format_from_format_and_type().
Just return MESA_FORMAT_NONE to avoid triggering unreachable; there's
really no sensible thing to return for this case anyway.

This prevents regressions in the next commit, which makes st/mesa
start using this function to find a reasonable format from GL format
and type enums.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-15 20:32:17 +00:00
Alyssa Rosenzweig
ea232c7cfd pan/midgard: Use generic constant packing for 8/64-bit
Eventually, we will want to combine constants across types, but for now
let's not break the world.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 20:08:46 +00:00
Alyssa Rosenzweig
4c182a6d11 pan/midgard: Pack 64-bit swizzles
64-bit ops have their own funky swizzles. Let's pack them, both for
native 64-bit sources as well as extended 32-bit sources.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 20:08:46 +00:00
Alyssa Rosenzweig
ba2fb98d36 pan/midgard: Fix mir_round_bytemask_down for !32b
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 20:08:46 +00:00
Alyssa Rosenzweig
2655a300a3 pan/midgard: Implement i2i64 and u2u64
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 20:08:46 +00:00
Alyssa Rosenzweig
855eec93b1 pan/midgard: Expand 64-bit writemasks
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 20:08:46 +00:00
Marek Olšák
bda3ec5d55 radeonsi/nir: don't lower fma, instead, fuse fma
We want fma. This decreases compile times by 4% for Borderlands 2.

48505 shaders in 30515 tests
Totals:
SGPRS: 2206584 -> 2204784 (-0.08 %)
VGPRS: 1647892 -> 1648964 (0.07 %)
Spilled SGPRs: 6256 -> 6078 (-2.85 %)
Spilled VGPRs: 72 -> 72 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2240 -> 2240 (0.00 %) dwords per thread
Code Size: 49680804 -> 49837988 (0.32 %) bytes
LDS: 74 -> 74 (0.00 %) blocks
Max Waves: 371387 -> 371352 (-0.01 %)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-15 14:34:49 -05:00
Marek Olšák
dec34e880d radeonsi/nir: call nir_lower_flrp only once per shader
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-15 14:34:49 -05:00
Marek Olšák
0714b3d57e radeonsi/nir: remove dead function temps
glxgears has dead temps after lowering color inputs to load intrinsics.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-15 14:34:49 -05:00
Marek Olšák
bc5097a7d9 gallium/noop: call finalize_nir
For measuring st/mesa compile time.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-15 14:34:49 -05:00
Tomeu Vizoso
27801b90fa panfrost: Make sure the shader descriptor is in sync with the GL state
State was leaking from previous frames as we weren't updating the
descriptor in all cases.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:34 +00:00
Alyssa Rosenzweig
095654e3c2 pan/midgard: Prioritize texture registers
On newer GPUs, this is a no-op. On older GPUs, this prevents needless
spilling since texture registers are shared with a subset of work
registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:34 +00:00
Alyssa Rosenzweig
339401b53c pan/midgard: Disassemble with old pipeline always on T720
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:33 +00:00
Alyssa Rosenzweig
8344d7425b pan/midgard: Use texture, not textureLod, on early Midgard
We have to disable the fixup.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:33 +00:00
Alyssa Rosenzweig
29f5b00e6e pan/midgard: Fix vertex texturing on early Midgard
We use a different set of texture registers, probably to save hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:33 +00:00
Alyssa Rosenzweig
3866d0776f pan/midgard: Generalize texture registers across GPUs
Early Midgard uses a different set of texture registers; let's not
hardcode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andre Heider <a.heider@gmail.com>
2019-11-15 18:37:33 +00:00
Rhys Perry
df645fa369 aco: implement VK_KHR_shader_float_controls
This actually supports more of the extension than the LLVM backend but we
can't enable it because ACO doesn't work with all stages yet.

With more of it enabled, some CTS tests fail because our 64-bit sqrt
is very imprecise. I can't find any precision requirements for it
anywhere, so I'm thinking it might be a CTS issue.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-15 17:36:21 +00:00
Rhys Perry
be1d11249b aco: fix 64-bit fsign with 0
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-15 17:36:21 +00:00
Rhys Perry
b062b92ab1 aco: don't combine literals into v_cndmask_b32/v_subb/v_addc
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-15 17:36:21 +00:00
Rhys Perry
d7b0d9a8d8 radv: enable FP16/FP64 denormals earlier and only for LLVM
ACO sets this itself and will have to set it differently in the future to
support shaderDenormFlushToZeroFloat64.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-15 17:36:21 +00:00
Michel Dänzer
c6c7652753 gitlab-ci: Organize images using new REPO_SUFFIX templates feature
Two benefits:

Most docker image related environment variables can now be defined in
the jobs where they're used instead of globally. The DEBIAN_TAG values
are propagated to other jobs via YAML anchors.

Images on https://gitlab.freedesktop.org/mesa/mesa/container_registry
are now organized in separate repositories with a suffix matching the
name of the job which makes sure the image is there.

Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-15 16:23:22 +01:00
Michel Dänzer
506e9d5fc7 gitlab-ci: Rename container install scripts to match job names (better)
Cleans up .gitlab-ci/ a little, and allows using a single DEBIAN_EXEC
line for all container jobs.

v2:
* Use lava_arm.sh instead of arm_lava.sh for consistency with v2 of the
  previous change

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-15 16:21:10 +01:00
Michel Dänzer
3a48f4565e gitlab-ci: Use functional container job names
This makes it easier to tell which job is which in a pipeline.

v2:
* Use lava_arm{64,hf} instead of arm{64,hf}_lava to keep these jobs
  together in pipeline overviews

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-15 16:20:16 +01:00
Michel Dänzer
670277846d gitlab-ci: Document that ci-templates refs must be in sync
Otherwise there can be weird breakage.

(Removing the include from .gitlab-ci/lava-gitlab-ci.yml doesn't seem
possible unfortunately:
https://gitlab.freedesktop.org/daenzer/mesa/pipelines/79458)

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-15 16:06:54 +01:00
Tomeu Vizoso
7d24cef200 panfrost: Multiply offset_units by 2
Per the spec, the units passed to glPolygonOffset are to be multiplied
by an implementation-defined constant.

On Midgard, this constant seems to be 2.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-15 14:45:29 +01:00
Lionel Landwerlin
c061185e17 intel/perf: add EHL performance query support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-11-15 13:14:30 +00:00
Lionel Landwerlin
39fd11a9f8 intel/dev: flag the Elkhart Lake platform
We'll use this for performance metrics which are different from ICL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-11-15 13:14:30 +00:00
Tapani Pälli
7a893a0d57 gitlab-ci: update Piglit commit, update skips
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-15 12:06:15 +02:00
Tapani Pälli
1d970f15e2 mesa: allow bit queries for EXT_disjoint_timer_query
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-15 12:05:56 +02:00
Samuel Pitoiset
41a1152cdc radv: make sure to not clear the ds attachment after resolves
To not overwrite the resolve if there is pending clear aspects,
same as color resolves.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-15 09:36:43 +01:00
Samuel Pitoiset
519d9b30de radv: remove useless RADV_DEBUG=unsafemath debug option
This option is useless and shouldn't be used at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-15 09:07:34 +01:00
Nathan Kidd
9a80b7fd8f llvmpipe: Check thread creation errors
In the case of glibc, pthread_t is internally a pointer.  If
lp_rast_destroy() passes a 0-value pthread_t to pthread_join(), the
latter will SEGV dereferencing it.

pthread_create() can fail if either the user's ulimit -u or Linux
kernel's /proc/sys/kernel/threads-max is reached.

Choosing to continue, rather than fail, on theory that it is better to
run with the one main thread, than not run at all.

Keeping as many threads as we got, since lack of threads severely
degrades llvmpipe performance.

Signed-off-by: Nathan Kidd <nkidd@opentext.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-11-15 02:43:22 +01:00
Ben Crocker
9c3be6d21f llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders
Large programs, e.g. gnome-shell and firefox, may tax the
addressability of the Medium code model once a (potentially unbounded)
number of dynamically generated JIT-compiled shader programs are
linked in and relocated.  Yet the default code model as of LLVM 8 is
Medium or even Small.

The cost of changing from Medium to Large is negligible:
- an additional 8-byte pointer stored immediately before the shader entrypoint;
- change an add-immediate (addis) instruction to a load (ld).

Testing with WebGL Conformance 
(https://www.khronos.org/registry/webgl/sdk/tests/webgl-conformance-tests.html)
yields clean runs with this change (and crashes without it).

Testing with glxgears shows no detectable performance difference.

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1753327, 1753789, 1543572, 1747110, and 1582226

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/223

Co-authored by: Nemanja Ivanovic <nemanjai@ca.ibm.com>, Tom Stellard <tstellar@redhat.com>

CC: mesa-stable@lists.freedesktop.org

Signed-off-by: Ben Crocker <bcrocker@redhat.com>
2019-11-14 23:07:26 +00:00
Kenneth Graunke
4242c57227 iris: Wrap iris_fix_edge_flags in NIR_PASS
So nir_validate happens properly.  Unfortunately this means we have
to play the metadata song and dance, so walk over all impls and say
that we didn't hurt anything.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-14 14:50:11 -08:00
Kenneth Graunke
39c23fd1bb iris: Properly move edgeflag_out from output list to global list
When demoting it from an output to a global, we need to actually move
it to the correct list.  While here, we also refactor so it's clear
we aren't mutating the list while iterating.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2106
Fixes: f9fd04aca1 ("nir: Fix non-determinism in lower_global_vars_to_local")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-14 14:50:09 -08:00
Eric Anholt
790d0ebef3 mesa: Move compile of common Mesa core files to a static lib.
We were compiling them twice, costing extra build time.  Reduces my
ccache-hot clean build time by a second (24.3s to 23.3s, 3 runs each).

The windows args are a little strange -- it's not clear to me that
they're actually used for building these files, but keep them in place
just in case, since we don't have a good windows CI story yet.  We
should want them on both gallium and classic regardless: Only osmesa
could be built for windows in classic, and classic OSMesa's scons
build defines these flags too.

Closes: #2052
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-14 21:46:10 +00:00
Prodea Alexandru-Liviu
cc758f1224 Appveyor: Quickly fix meson build.
As this required use of Python 3.8, mako module also had to be updated.

v2 - Unbind mako module version when using Meson.
Signed-off-by: Prodea Alexandru-Liviu <liviuprodea@yahoo.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-14 21:45:23 +00:00
Danylo Piliaiev
0904ee0c60 intel/fs: Do not lower large local arrays to scratch on gen7
On gen7 and earlier the scratch space size is limited to 12kB.
By enabling this optimization we may easily exceed this limit
without having any fallback.

arb_compute_shader/linker/bug-93840.shader_test crashes with
this lowering on IVB due to exceeding scratch size limit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2092
Fixes: 69244fc7
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-14 20:08:30 +00:00
Eric Anholt
882ca6dfb0 util: Move gallium's PIPE_FORMAT utils to /util/format/
To make PIPE_FORMATs usable from non-gallium parts of Mesa, I want to
move their helpers out of gallium.  Since u_format used
util_copy_rect(), I moved that in there, too.

I've put it in a separate directory in util/ because it's a big chunk
of related code, and it's not clear to me whether we might want it as
a separate library from libmesa_util at some point.

Closes: #1905
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-14 10:47:20 -08:00
Eric Engestrom
ac78ca4b39 gitlab-ci: auto-cancel CI runs when a newer commit is pushed to the same branch
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-14 17:32:31 +00:00
Timur Kristóf
9b8dc6929e aco: Optimize out trivial code from uniform bools.
This should remove most of the excess code size that was
introduced by making all booleans per-lane.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-14 17:27:11 +01:00
Timur Kristóf
8995c0b30a aco: Treat all booleans as per-lane.
Previously, instruction selection had two kinds of booleans:
1. divergent which was per-lane and stored in s2 (VCC size)
2. uniform which was stored in s1
Additionally, uniform booleans were made per-lane when they resulted
from operations which were supported only by the VALU.

To decide which type was used, we relied on the destination size,
which was not reliable due to the per-lane uniform bools, but it
mostly works on wave64.
However, in wave32 mode (where VCC is also s1) this approach
makes it impossible keep track of which boolean is uniform and
which is divergent.

This commit makes all booleans per-lane.
The resulting excess code size will be taken care of by the optimizer.

v2 (by Daniel Schürmann):
- Better names for some functions
- Use s_andn2_b64 with exec for nir_op_inot
- Simplify code due to using s_and_b64 in bool_to_scalar_condition

v3 (by Timur Kristóf):
- Fix several subgroups regressions

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-14 17:27:11 +01:00
Daniel Schürmann
a1622c1a11 aco: use s_and_b64 exec to reduce uniform booleans to one bit
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-14 17:27:10 +01:00
Timur Kristóf
94e355148f aco: Make sure not to mistakenly propagate 64-bit constants.
ACO's optimizer would try to propagate 64-bit constants, but
does so in such a way that wouldn't work due to how the 64-bit
constants are handled in the IR.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-14 17:27:10 +01:00
Daniel Schürmann
9d3e070524 aco: value number instructions using the execution mask
This patch tries to give instructions with the same execution
mask also the same pass_flags and enables VN for SALU instructions
using exec as Operand.
This patch also adds back VN for VOPC instructions and removes VN for phis.

v2 (by Timur Kristóf):
- Fix some regressions.
v3 (by Daniel Schürmann):
- Fix additional issues

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-14 17:27:10 +01:00
Daniel Schürmann
8657eede8a aco: check if SALU instructions are predeceeded by exec when calculating WQM needs
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-14 17:27:10 +01:00
Samuel Pitoiset
ee9811a0bb ac: fix build with recent LLVM
Build is broken since "Move CodeGenFileType enum to Support/CodeGen.h".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-14 14:41:55 +00:00
Tapani Pälli
94cb4916e3 Revert "mesa: allow bit queries for EXT_disjoint_timer_query"
This reverts commit 66d24a9ef7.

This commit made Mesa CI red because commit depends on a Piglit test
change.
2019-11-14 13:34:33 +00:00
Connor Abbott
f9fd04aca1 nir: Fix non-determinism in lower_global_vars_to_local
Using a hash-table walk means that variables will get inserted in
different orders on different runs. Just walk the list of globals
instead, even if some of them can't be turned into locals.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-14 13:10:58 +00:00
Iago Toral Quiroga
f512965b0b mesa/st: make sure we remove dead IO variables before handing NIR to backends
Commit "1c2bf82d24a glsl: disable lower_fragdata_array() for NIR drivers"
disabled the GLSL IR lowering that turned gl_FragData from an array into a
collection of scalar outputs under the assumption that this was already being
handled properly elsewhere, however there are some corner cases where NIR
would fail to do this, leaving gl_FragData[] as an array variable. This can
break backends that assume that all their outputs will be scalar and use the
variable definitions from the shader to do their output setup, such as the
case of V3D.

At least one corner case was found in some Portal shaders from shader-db, where
NIR would optimize out the full body of a fragment shader. In this scenario,
the empty shader would keep the original array definition of gl_FragData[],
causing the backend to assert.

We need to do this late enough for it to be effective, since doing it in
st_nir_preprocess does not fix the original problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2091
Fixes: 1c2bf82d ("glsl: disable lower_fragdata_array() for NIR drivers")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-14 10:49:00 +01:00
Tapani Pälli
66d24a9ef7 mesa: allow bit queries for EXT_disjoint_timer_query
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-14 09:27:13 +02:00
Tapani Pälli
1a093a06d6 Revert "dri_interface: add interface for EGL_EXT_image_flush_external"
This reverts commit 7520478461.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14 07:46:36 +02:00
Tapani Pälli
7951eb146c Revert "st/dri: assume external consumers of back buffers can write to the buffers"
This reverts commit 1d1b457821.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14 07:46:30 +02:00
Tapani Pälli
25f596e6ba Revert "st/dri: add support for EGL_EXT_image_flush_external"
This reverts commit 1d122c104a.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14 07:46:20 +02:00
Tapani Pälli
ff05f16c99 Revert "egl: handle EGL_IMAGE_EXTERNAL_FLUSH_EXT"
This reverts commit 34b1aa957a.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14 07:46:14 +02:00
Tapani Pälli
e64b91e34a Revert "egl: implement new functions from EGL_EXT_image_flush_external"
This reverts commit c1c574fdf1.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-14 07:46:04 +02:00
Alyssa Rosenzweig
ad6b2ac374 pan/midgard: Fix copypropagation for textures
total instructions in shared programs: 3562 -> 3457 (-2.95%)
instructions in affected programs: 575 -> 470 (-18.26%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 14 x̄: 6.56 x̃: 10
helped stats (rel) min: 5.71% max: 24.56% x̄: 16.83% x̃: 18.87%
95% mean confidence interval for instructions value: -9.07 -4.06
95% mean confidence interval for instructions %-change: -19.00% -14.66%
Instructions are helped.

total bundles in shared programs: 1846 -> 1830 (-0.87%)
bundles in affected programs: 338 -> 322 (-4.73%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.50% max: 20.00% x̄: 8.85% x̃: 3.33%
95% mean confidence interval for bundles value: -1.00 -1.00
95% mean confidence interval for bundles %-change: -13.02% -4.67%
Bundles are helped.

total quadwords in shared programs: 3191 -> 3144 (-1.47%)
quadwords in affected programs: 606 -> 559 (-7.76%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 14 x̄: 2.94 x̃: 3
helped stats (rel) min: 5.17% max: 22.22% x̄: 11.20% x̃: 5.62%
95% mean confidence interval for quadwords value: -4.58 -1.29
95% mean confidence interval for quadwords %-change: -15.16% -7.24%
Quadwords are helped.

total registers in shared programs: 312 -> 303 (-2.88%)
registers in affected programs: 27 -> 18 (-33.33%)
helped: 9
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
95% mean confidence interval for registers value: -1.00 -1.00
95% mean confidence interval for registers %-change: -33.33% -33.33%
Registers are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-14 02:36:21 +00:00
Alyssa Rosenzweig
f72873e6aa pan/midgard: Copypropagate vector creation
total instructions in shared programs: 3457 -> 3431 (-0.75%)
instructions in affected programs: 787 -> 761 (-3.30%)
helped: 14
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 1.86 x̃: 1
helped stats (rel) min: 1.01% max: 11.11% x̄: 9.22% x̃: 11.11%
95% mean confidence interval for instructions value: -3.55 -0.16
95% mean confidence interval for instructions %-change: -11.41% -7.03%
Instructions are helped.

total bundles in shared programs: 1830 -> 1826 (-0.22%)
bundles in affected programs: 279 -> 275 (-1.43%)
helped: 2
HURT: 0

total quadwords in shared programs: 3144 -> 3121 (-0.73%)
quadwords in affected programs: 645 -> 622 (-3.57%)
helped: 13
HURT: 0
helped stats (abs) min: 1 max: 11 x̄: 1.77 x̃: 1
helped stats (rel) min: 2.09% max: 16.67% x̄: 12.61% x̃: 14.29%
95% mean confidence interval for quadwords value: -3.45 -0.09
95% mean confidence interval for quadwords %-change: -15.43% -9.79%
Quadwords are helped.

total registers in shared programs: 303 -> 301 (-0.66%)
registers in affected programs: 14 -> 12 (-14.29%)
helped: 2
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-14 02:36:21 +00:00
Alyssa Rosenzweig
39b5f2fa0b pan/lcra: Use Chaitin's spilling heuristic
Not much of a difference but slightly better and slightly less
arbitrary.

total instructions in shared programs: 3560 -> 3559 (-0.03%)
instructions in affected programs: 44 -> 43 (-2.27%)
helped: 1
HURT: 0

total bundles in shared programs: 1844 -> 1843 (-0.05%)
bundles in affected programs: 23 -> 22 (-4.35%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-14 02:36:21 +00:00
Alyssa Rosenzweig
23c83f3f05 pan/midgard: Compute spill costs
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-14 02:36:21 +00:00
Paulo Zanoni
eb6352162d intel/compiler: fix nir_op_{i,u}*32 on ICL
On ICL we have the src1 restriction which is applied through
fix_byte_src() and potentially changes the type of the operands from 8
to 32 bits. When this change happens, we fall into the "else if
(bit_size < 32)" case and miscompute src_type because it takes into
consideration bit_size (8) instead of the adjusted size of temp_op
(32). This results in the shader reading unused memory, giving us
mostly failures, but occasional passes due to whatever was already in
the registers we were reading.

This commit fixes a lot of dEQP subgroup i8vec2 tests on ICL, such as:
    dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

This can also be verified by simply changing fix_byte_src() to apply
on all platforms.

Fixes: 5847de6e9a ("intel/compiler: don't use byte operands for src1 on ICL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2019-11-13 22:13:52 +00:00
Caio Marcelo de Oliveira Filho
7ae506e5b8 spirv: Consider the sampled_image case in wa_glslang_179 workaround
Fixes: 9e440b8d0b ("spirv: Sort out the mess that is sampled image")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-13 12:02:29 -08:00
Dylan Baker
943f630f8e docs: update calendar, add news item and link release notes for 19.2.4 2019-11-13 11:12:53 -08:00
Dylan Baker
ff5bcd7ce9 docs: Add SHA256 sum for for 19.2.4 2019-11-13 11:10:51 -08:00
Dylan Baker
67fd2b936d docs: Add release notes for 19.2.4 2019-11-13 11:10:47 -08:00
Eric Anholt
f0eeb98c6c ci: Expand the freedreno blit skip regex to cover more cases.
We've had flaps on at least:
- r16f_to_r16f
- r16i_to_rg16i

Reviewed-by: Daniel Stone <daniels@collabora.com>
2019-11-13 10:58:52 -08:00
Caio Marcelo de Oliveira Filho
0aaf47f7cd anv: Initialize depth_bounds_test_enable when not explicitly set
This was causing uninitialized value to end up propagated to the
3DSTATE_DEPTH_BOUNDS packet, leading to asserts on packet
building due to the value being greater than 1.

Fixes: 939ddccb7a ("anv: Add support for depth bounds testing.")
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
2019-11-13 10:13:27 -08:00
Alyssa Rosenzweig
771d23584a pan/midgard: Remove util/ra support
It's now unused, in favour of LCRA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-13 15:27:56 +00:00
Alyssa Rosenzweig
e343f2ceb9 pan/midgard: Integrate LCRA
Pretty routine, we do have a hack to force swizzle alignment for !32-bit
for until we implement !32-bit the right way.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-13 15:27:56 +00:00
Alyssa Rosenzweig
66ad64d73d pan/midgard: Implement linearly-constrained register allocation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-13 15:27:56 +00:00
Alyssa Rosenzweig
fd81916ee5 pan/midgard: Add blend shader selection bits for MRT
This is less complicated than previously thought. Note we have no way of
specifying the work register count for blend shaders; it must be
strictly less than the work register count of the corresponding fragment
shader (which is fine since we force the fragment shader to report a
count of 16 with a blend shader as a major hack until we get register
pressure down for blend shaders).

TODO: pandecode the flags.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-13 15:27:56 +00:00
Christian Gmeiner
e101af8671 drm-shim: fix EOF case
Close input end of the pipe after data was written. Without this
fix I have seen a hang in sysfs_uevent_get(.., "OF_FULLNAME")
when key was not found.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-13 12:39:14 +00:00
Tapani Pälli
b12911c88e util/android: fix android build errors
Fixes: 9020f519 ("util/u_endian: Add error checks")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2078
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-13 12:31:31 +02:00
Samuel Pitoiset
47ba227448 gitlab-ci: build RADV on ARM64
The ARMHF LLVM package is LLVM 7 but RADV requires LLVM 8.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-13 10:52:10 +01:00
Samuel Pitoiset
cb19f69ff0 gitlab-ci: build a specific libdrm version for ARM64
RADV requires libdrm-2.4.100 but the distrib package is too old.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-13 10:52:08 +01:00
Erik Faye-Lund
4c1cef68cf zink: move drawing separate source
This code is kinda stand-alone, and it makes it a bit easier to find the
right source in the source-tree.
2019-11-13 09:14:05 +01:00
Erik Faye-Lund
589e8651e6 zink: move blitting to separate source
This code is kinda stand-alone, and it makes it a bit easier to find the
right source in the source-tree
2019-11-13 09:14:05 +01:00
Erik Faye-Lund
1605a0c8f2 zink: move filter-helper to separate helper-header
This will help code-reuse a bit in the next commit.
2019-11-13 09:12:36 +01:00
Erik Faye-Lund
36f3902213 zink: move format-checking to separate source
This code is more or less stand-alone, and this keeps the formats array
a bit more encapsulated.
2019-11-13 09:12:36 +01:00
Eric Anholt
fd777d2cea ci: Disable flappy blit tests on a630.
These have shown up with the new CTS runner, which has changed test
ordering.

Reviewed-by: Daniel Stone <daniels@collabora.com>
2019-11-12 16:43:04 -08:00
Rob Clark
0f33c255d3 freedreno/ir3: remove unused parameter
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-12 13:57:52 -08:00
Rob Clark
df7a88dca3 freedreno/ir3: legalize cleanups
We can clear the "needs" flags once we emit a flag.  And also, don't
open-code the opcode name.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:57:52 -08:00
Rob Clark
b22617fb57 freedreno/ir3: fix gpu hang with pre-fs-tex-fetch
For pre-fs-dispatch texture fetch, we need to assign bary_ij to r0.x,
even if it is not used in the shader (ie. only varying use is for tex
coords).  But if, for example, gl_FragCoord is used, it could get
assigned on top of bary_ij, resulting in a GPU hang.

The solution to this is two-fold: (1) the inputs/outputs rework has the
benefit of making RA realize bary_ij is a vec2, even if there are no
split/collect instructions (due to no varying fetches in the shader
itself).  And (2) extend the live ranges of meta:input instructions to
the first non-input, to prevent RA from assigning the same register to
multiple inputs.

Backport note: because of (1) above, a better solution for 19.3 would be
to revert f30c256ec0.

Fixes: f30c256ec0 ("freedreno/ir3: enable pre-fs texture fetch for a6xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:57:52 -08:00
Rob Clark
4bb697d938 freedreno/ir3: only tex instructions have wrmask
At the ir3 level, we would assume that we could use wrmask to mask
off other components of an instruction returning a vecN when they are
not used.  Which would let RA use components not written for other live
values.  But this is only true for tex instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:57:52 -08:00
Rob Clark
bdf6b7018c freedreno/ir3: re-work shader inputs/outputs
Allow inputs/outputs to be vecN (ie. whatever their actual size is), and
use split to get scalar components of inputs, and collect to gather up
scalar components of outputs.

The main motivation is to simplify RA, by only having to consider split/
collect to figure out where values need to land in consecutive scalar
registers, rather than having to also deal with left/right neighbors.

Because of varying packing, and the resulting fractional location
(location_frac), to implement load_input/store_output, it is still
convenient to have a table of scalar inputs/outputs.  We move this to
the compile ctx (since it is only needed for nir->ir3).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:57:52 -08:00
Rob Clark
2aae13f642 freedreno/ir3: simplify creating sysval inputs
In almost all places, the add_sysval_input() is paired directly with a
create_input().  (The one exception is frag shader ij bary coord, and
this exception will go away in a later patch.)

So go ahead and clean this up before reworking input/output handling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
68d2ec5f7e freedreno/ir3: remove first-vertex sysval
This is a driver-param (loaded from uniform), not a sysval (populated by
hw into a register).  So it has no value to having a sysval slot.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
7b2166785a freedreno/ir3: helper to print ir if debug enabled
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
7a5f073da3 freedreno/ir3: show input/output wrmask's in disasm
Currently it is always 0x1 (scalar), but that will change in a later
patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
c00a67171c freedreno/ir3: add input/output iterators
We can at least get rid of the if-not-NULL check in a bunch of places.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
b2417801e5 freedreno/ir3: remove impossible condition
We keep kill's alive w/ keeps these days, rather than a fake output.
This condition was left over from prior to that change.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
611258d578 freedreno/ir3: rename fanin/fanout to collect/split
If I'm going to refactor a bit to use these meta instructions to also
handle input/output, then might as well cleanup the names first.
Nouveau also uses collect/split for names of these meta instructions,
and I like those names better.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
4af86bd0b9 freedreno/ir3: remove half-precision output
This doesn't really work, we can't necessarily just change the outputs
to half-precision like this in anything but simple cases.

Keep the shader key entry around though, eventually with proper mediump
support we could use this with a nir pass to use lower precision frag
shader outputs when the render target format has <= 16b/component.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Rob Clark
089b105396 freedreno/ir3: fix valgrind complaint with STLW
The instruction has 3 src regs, so `instr->regs[0..3]` are valid, but
`instr->regs[4]` is not.

```
Test case 'dEQP-GLES31.functional.shaders.linkage.es31.tessellation.varying.rules.output_superfluous_declaration'..
==29239== Invalid read of size 8
==29239==    at 0x5BE9CDC: emit_cat6 (ir3.c:841)
==29239==    by 0x5BEA1BF: ir3_assemble (ir3.c:921)
==29239==    by 0x5BDF0A7: ir3_shader_assemble (ir3_shader.c:133)
==29239==    by 0x5BDF193: assemble_variant (ir3_shader.c:162)
==29239==    by 0x5BDF407: create_variant (ir3_shader.c:215)
==29239==    by 0x5BDF4DB: shader_variant (ir3_shader.c:241)
==29239==    by 0x5BDF553: ir3_shader_get_variant (ir3_shader.c:257)
==29239==    by 0x5BA85F7: ir3_shader_variant (ir3_gallium.c:80)
==29239==    by 0x5BA7703: ir3_cache_lookup (ir3_cache.c:96)
==29239==    by 0x5B8B8B3: fd6_emit_get_prog (fd6_emit.h:119)
==29239==    by 0x5B8C137: fd6_draw_vbo (fd6_draw.c:186)
==29239==    by 0x5BB1FBB: fd_draw_vbo (freedreno_draw.c:290)
==29239==  Address 0xb97f2d0 is 0 bytes after a block of size 240 alloc'd
==29239==    at 0x4848D54: malloc (in /usr/lib/aarch64-linux-gnu/valgrind/vgpreload_memcheck-arm64-linux.so)
==29239==    by 0x61BD35B: ralloc_size (ralloc.c:119)
==29239==    by 0x61BD41B: rzalloc_size (ralloc.c:151)
==29239==    by 0x5BE599B: ir3_alloc (ir3.c:45)
==29239==    by 0x5BEA583: instr_create (ir3.c:984)
==29239==    by 0x5BEA5DF: ir3_instr_create2 (ir3.c:1000)
==29239==    by 0x5BEE317: ir3_STLW (ir3.h:1431)
==29239==    by 0x5BF12D3: emit_intrinsic_store_shared_ir3 (ir3_compiler_nir.c:903)
==29239==    by 0x5BF418B: emit_intrinsic (ir3_compiler_nir.c:1802)
==29239==    by 0x5BF5D07: emit_instr (ir3_compiler_nir.c:2339)
==29239==    by 0x5BF603F: emit_block (ir3_compiler_nir.c:2426)
==29239==    by 0x5BF624B: emit_cf_list (ir3_compiler_nir.c:2474)
==29239==
```

Probably this only triggers in non-optimized builds?

Fixes: 1f3b52ce50 ("freedreno/a6xx: Add register offset for STG/LDG")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 13:55:03 -08:00
Eric Anholt
f3244c6019 ci: Remove old commented copy of freedreno artifacts.
This path was from an older version of freedreno CI.
2019-11-12 12:54:04 -08:00
Eric Anholt
52843ec5d3 ci: Enable all of GLES3/3.1 testing for softpipe.
Now that we're not using so many job slots, it's easy to get these
jobs run in a reasonable amount of time (gles3 took 10 minutes for 4
cores, and gles31 was 15 minutes for 4 cores).

Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-12 12:54:04 -08:00
Eric Anholt
f08c810028 ci: Use cts_runner for our dEQP runs.
This runner is a little project by Bas, written in C++, that spawns
threads that then loop grabbing chunks of the (randomly shuffled but
consistently so) test list and hand it to a dEQP instance.  As the
remaining list gets shorter, so do the chunks, so hopefully the
threads all complete effectively at once.  It also handles restarting
after crashes automatically.  I've extended the runner a bit to do
what I was doing in the bash scripts before, like the skip list and
expected failures handling.  This project should also be a good
baseline for extending to handle retesting of intermittent failures.

By switching to it, we can have the swrast tests just take up one job
slot on the shared runners and keep their allotment of CPUs busy,
instead of taking up job slots with single-threaded dEQP jobs.  It
will also let us (eventually, once I reprovision) switch the freedreno
runners over to threading within the job instead of running concurrent
jobs, so that memory scribbles in one pipeline don't affect unrelated
pipelines, and I can experiment with their parallelism (particularly
on a306 where we are frequently backed up) without trashing other
people's jobs.

What we lose in this process is per-test output in the log (not a big
loss, I think, since we summarize fails at the end and reducing log
length keeps chrome from choking on our logs so badly).  We also drop
the renderer sanity checking, since it's not saving qpa files for us
to go poke through.  Given that all the drivers involved have fail
lists, if we got the wrong renderer somehow, we'd get a job failure
anyway.

v2: Rebase on droppong of the autoscale cluster and the arm64
    build/test split.  Use a script to deduplicate the cts-runner
    build.
v3: Rebase on the amd64 build/test container split.

Acked-by: Daniel Stone <daniels@collabora.com> (v1)
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2)
2019-11-12 12:54:04 -08:00
Eric Anholt
7f52df7fc9 ci: Make the skip list regexes match the full test name.
The bash scripts were using grep in the manner that matches any subset
of the line, but the new CTS runner matches the whole line and I think
that's a pretty good behavior.  Given that some of the skip lists
already were written to match the full test name, just make them
consistently do so.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-12 12:54:04 -08:00
Eric Anholt
66719e0242 ci: Use several debian buster packages instead of hand-building.
This helps cut down our container build time.  I've left a few that
we're likely to rev more frequently or I was less confident in
dropping.

v2: Rebase on the build/test container split, now bumps the build
    container tag in this commit.

Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Daniel Stone <daniels@collabora.com> (v1)
2019-11-12 12:54:04 -08:00
Rafael Antognolli
a4da6008b6 iris: Use mocs from isl_dev.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-12 20:41:52 +00:00
Rafael Antognolli
d4f628235e anv: Use mocs settings from isl_dev.
v2: Remove device->default_mocs and external_mocs (Jason).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-12 20:41:52 +00:00
Rafael Antognolli
2b01636ddb intel/isl: Add MOCS settings to isl_device.
Centralize mocs settings into isl.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-12 20:41:52 +00:00
Rob Clark
d509a46225 freedreno: fix eglDupNativeFenceFD error
We can end up with scenarios where last_fence is associated with a batch
that is flushed through some other path before needs_out_fence_fd gets
set.  Resulting in returning a fence that has no backing fd.

The simplest thing is to just skip the optimization to try and avoid
no-op batches when a fence-fd is requested.  This should normally be
just once a frame anyways.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-12 11:38:16 -08:00
Brian Paul
bd49dedae0 nir: fix a couple signed/unsigned comparison warnings in nir_builder.h
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-12 11:44:02 -07:00
Brian Paul
a69e105361 s/APIENTRY/GLAPIENTRY/ in teximage.c
The later is the right symbol for entrypoint functions.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-12 11:44:01 -07:00
Lepton Wu
5c2d307a10 android: mesa: Revert "android: mesa: revert "Enable asm unconditionally""
Commit 45206d7673 fixed PIC issue of x86 asm stub.
We can enable asm for Android x86 now. This should sightly improve performance.

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>
2019-11-12 18:09:43 +00:00
Rhys Perry
6914b0236f aco: combine read_invocation and shuffle implementations
They do mostly the same thing now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-12 17:21:38 +00:00
Rhys Perry
2c98d79d11 aco: don't propagate vgprs into v_readlane/v_writelane
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
2019-11-12 17:21:38 +00:00
Rhys Perry
5a1bacb6f9 aco: fix read_invocation with VGPR lane index
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
2019-11-12 17:21:38 +00:00
Rhys Perry
c877f4d320 nir/divergence: improve DA of shuffle
If the data is uniform, then it's really a uniform copy. If the index is
uniform, then it's really a read_invocation.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-12 17:21:38 +00:00
Rhys Perry
f97d933426 aco: fix shuffle with uniform operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
2019-11-12 17:21:38 +00:00
Rhys Perry
3204e83768 aco: use DPP instead of exec modification when lowering GFX10 shuffles
Seems we can use DPP's row_mask field to get an effect similar to
modifying exec.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
2019-11-12 17:21:38 +00:00
Eric Engestrom
06347989a0 gitlab-ci: build libdrm using meson instead of autotools
Autotools was deprecated for a while and has now been removed, so let's
start using meson here so that we won't have any issues next time we
update libdrm.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-11-12 17:08:02 +00:00
Daniel Schürmann
746b9380bd aco: rematerialize s_movk instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-12 15:59:48 +00:00
Daniel Schürmann
b6f5085dfe aco: preserve kill flag on moved operands during RA
Fixes: 93c8ebfa78 aco: Initial commit of independent AMD compiler

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-12 15:59:48 +00:00
Daniel Schürmann
a2a6880743 aco: fix invalid access on Pseudo_instructions
Fixes: 93c8ebfa78 aco: Initial commit of independent AMD compiler

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-12 15:59:48 +00:00
Erik Faye-Lund
5b09a7e2e4 zink: remove no-longer-needed hack
It seems whatever was causing this is no longer an issue. So let's get
rid of the hack here.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-11-12 13:30:35 +00:00
Erik Faye-Lund
e1c87bbb4b zink: implement buffer-to-buffer copies 2019-11-12 12:40:49 +00:00
Erik Faye-Lund
9352991880 zink: always allow transfer to/from buffers 2019-11-12 12:40:49 +00:00
Danylo Piliaiev
d4c8182018 intel/blorp: Fix usage of uninitialized memory in key hashing
The automatically generated padding in structs contains
undefined values, force pack the structs to eliminate the
padding. Otherwise structs with the same values may generate
different hashes.

Valgrind output:

Conditional jump or move depends on uninitialised value(s)
 util_fast_urem32 (fast_urem_by_const.h:71)
 hash_table_search (hash_table.c:262)
 _mesa_hash_table_search (hash_table.c:296)
 anv_pipeline_cache_search_locked (anv_pipeline_cache.c:318)
 anv_pipeline_cache_search (anv_pipeline_cache.c:335)
 lookup_blorp_shader (anv_blorp.c:38)
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1112)
 blorp_mcs_partial_resolve (blorp_clear.c:1205)
 anv_image_mcs_op (anv_blorp.c:1742)
 anv_cmd_predicated_mcs_resolve (genX_cmd_buffer.c:774)
 transition_color_buffer (genX_cmd_buffer.c:1159)
 cmd_buffer_end_subpass (genX_cmd_buffer.c:4840)

Uninitialised value was created by a stack allocation
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1103)

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-12 13:59:29 +02:00
Danylo Piliaiev
3349b4b056 i965/program_cache: Lift restriction on shader key size
This will allow usage of packed structs which may have size
not divisible by 4.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-12 13:59:24 +02:00
Michel Dänzer
af684753f3 gitlab-ci: Delete install/bin from artifacts as well
This cuts the x86 artifacts zip file size in less than half.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:18:31 +01:00
Michel Dänzer
aebf43dcc1 gitlab-ci: Use separate docker images for x86 build/test jobs
Same as was done for the ARM images before.

This should make it less painful to update to newer dEQP / piglit as
well as to make changes to the build/test environment.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:17:21 +01:00
Michel Dänzer
576f7b6ea5 gitlab-ci: Run piglit tests with llvmpipe
One job for the quick_gl profile, one for the glslparser & quick_shader
profiles (doing these together takes hardly any more time than
quick_shader alone).

v2:
* Don't break lava tests
v3:
* Remove piglit test artifacts paths:
* Exclude some quick_shader tests again:
  - Test whose result flips between pass/fail/skip
  - *@vs_in tests, as not the same one of these gets picked every time
v4:
* Do not list passing tests in .gitlab-ci/piglit/*.txt (Eric Anholt)
* Include the test number summary in .gitlab-ci/piglit/*.txt
* Completely disable generating any vs_in tests in the piglit build.
* Remove some more unneded files from the piglit build tree.
* Exclude quick_gl arb_gpu_shader5 tests; they were all skipped anyway,
  as llvmpipe doesn't support this extension yet, but occasionally they
  would spuriously fail instead.
v5:
* Set LD_LIBRARY_PATH, so we actually test the Mesa build from the
  pipeline...
* Verify that wflinfo reports the expected Mesa version
* Pass -noreset to Xvfb
v6:
* Don't use autoscale runners, run piglit with -j4 (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:16:23 +01:00
Michel Dänzer
4b25b5885b gitlab-ci: Sort packages in debian-install.sh
And remove duplicates.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:16:08 +01:00
Michel Dänzer
df26e18b9f gitlab-ci: Share dEQP build process between x86 & ARM test image scripts
See https://gitlab.freedesktop.org/mesa/mesa/issues/2056

v2:
* Rename .gitlab-ci/deqp-build.sh => .gitlab-ci/build-deqp.sh
  (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:14:49 +01:00
Michel Dänzer
59fcb019d0 gitlab-ci: Move artifact preparation to separate script
It's currently only needed for the meson-main and meson-arm64 jobs, not
the other meson build jobs.

Also remove MESON_SHADERDB, just run .gitlab-ci/run-shader-db.sh
directly from the meson-main job.

v2:
* Also run prepare-artifacts.sh in meson-arm64 script
v3:
* Move tarball creation into the new script as well, as it prevented
  ccache --show-stats from running in after_script

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> # v1
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:14:26 +01:00
Michel Dänzer
2921a38484 gitlab-ci: Use ninja -j4 for building dEQP
By default, ninja tries to saturate all cores of the runner host
machine, which could overload it due to other jobs running in parallel.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-12 10:14:04 +01:00
Jason Ekstrand
0c7e0c5599 spirv: Fix the MSVC build
Fixes: 9cc4c2c916 "spirv: Add a vtn_decorate_pointer helper"
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-12 08:34:55 +00:00
Erik Faye-Lund
9b8964d064 nir: patch up deref-vars when lowering clip-planes
Otherwise, we fail validation and potentially generate invalid code.
Let's fix up the mode of the accesses to the variable.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-12 09:13:22 +01:00
Samuel Pitoiset
bef7b2f805 ac: handle pointer types to LDS in ac_get_elem_bits()
This fixes crashes with some
dEQP-VK.spirv_assembly.instruction.spirv1p4.* tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-12 08:32:15 +01:00
Jonathan Marek
01cae57c80 freedreno: add Adreno 640 ID
A640 seems to work without any other changes (glmark and vkcube).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-11-11 20:46:01 -05:00
Luis Mendes
0cb5c96a83 radv: fix radv secure compile feature breaks compilation on armhf EABI and aarch64
__NR_select is not defined the same way across architectures, sometimes is
not even defined, like in armhf EABI and aarch64.

Signed-off-by: Luis Mendes <luis.p.mendes@gmail.com>

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2042
2019-11-12 11:47:20 +11:00
Marek Olšák
3a23af9f44 st/mesa: remove unused TGSI-only debug printing functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:45:12 -05:00
Marek Olšák
d29a332862 st/mesa: add ST_DEBUG=nir to print NIR shaders
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:45:10 -05:00
Marek Olšák
265abc54f8 st/mesa: print TCS/TES/GS/CS TGSI in the right place & keep disk cache enabled
The old place only printed on a disk cache miss, which is why the disk
cache was disabled.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:45:08 -05:00
Marek Olšák
98e27e5e28 st/mesa: remove \n being only printed in debug builds after printed TGSI
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:45:07 -05:00
Marek Olšák
c3351bb44b st/mesa: rename DEBUG_TGSI -> DEBUG_PRINT_IR
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:45:04 -05:00
Marek Olšák
e00791c552 st/mesa: fix Sanctuary and Tropics by disabling ARB_gpu_shader5 for them
They use the "sample" keyword as a variable name.

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 19:23:37 -05:00
Lionel Landwerlin
34f32a6d66 anv: implement VK_KHR_timeline_semaphore
v2: Fix inverted condition in vkGetPhysicalDeviceExternalSemaphoreProperties()

v3: Add anv_timeline_* helpers (Jason)

v4: Avoid variable shadowing (Jason)
    Split timeline wait/signal device operations (Jason/Lionel)

v5: s/point/signal_value/ (Jason)
    Drop piece of drm-syncobj timeline code (Jason)

v6: Add missing sync_fd semaphore signaling (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Jason Ekstrand
5a4f15ef2c anv: Plumb timeline semaphore signal/wait values through from the API
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
edc6606d4e anv/wsi: signal the semaphore in the acquireNextImage
We seem to have forgotten about the semaphore in the
acquireNextImageInfo.

v2: Signal semaphore/fence regardless of presentation status (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Jason Ekstrand
b10b455c1d anv: Lock around fetching sync file FDs from semaphores
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
246261f0ad anv: prepare the driver for delayed submissions
Timeline semaphore introduce support for wait before signal behavior,
which means that it is now allowed to call vkQueueSubmit() with wait
semaphores not yet submitted for execution. Our kernel driver requires
all of the wait primitives to be created before calling the execbuf
ioctl. As a result, we must delay submissions in the userspace driver.
This change store the necessary information to be able to delay a
VkSubmitInfo submission to the kernel driver.

v2: Fold count++ into array access (Jason)
    Move queue list to another patch (Jason)

v3: Document cleanup of temporary semaphores (Jason)

v4: Track semaphores of SYNC_FD type that needs updating after delayed
    submission

v5: Don't forget to update sync_fd in signaled semaphores after
    submission (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
3e22363537 anv: refcount semaphores
Delayed submissions required by timeline semaphores mean we need to be
able to update the sync fd backed semaphores in a delayed fashion.
This could mean a race between the application destroying the
semaphore and the submission code trying to update it with the new
sync fd.

This change prepares semaphores to be refcounted, we'll most likely
only take a reference for cases where we signal a sync fd semaphore.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
3da798c9f1 anv: prepare driver to report submission error through queues
When we will submit to i915 from a submission thread, we won't be able
to directly report the error to the user (in particular through the
debug report callbacks). So prepare 2 paths to report errors device ->
notifying the user immediately, queue -> notifying the user the next
time an entry point is called.

In this change we still report directly for both paths, this will
change in the next commit.

v2: Split NULL batch parameter handling in
    anv_queue_submit_simple_batch() in a different commit

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
89de271bc2 anv: allow NULL batch parameter to anv_queue_submit_simple_batch
We can reuse device->trivial_batch_bo

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
f606c12731 anv: move queue init/finish to anv_queue.c
Prepare the queue initialization to take on more responsabilities and
possibly fail.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
206ab49ba1 anv: expose timeout helpers outside of anv_queue.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
2f4dcc8a1c anv: detach batch emission allocation from device
In the future we'll have 2 different allocations depending on whether
we're using threaded submission or not.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
935f8f0e56 anv: remove list items on batch fini
This doesn't seem to fix anything because those destroy() calls happen
right before the command buffer object & its list of batch_bo is also
destroyed. Still looks a bit cleaner.

v2: Found a second occurence

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
Fixes: 26ba0ad54d ("vk: Re-name command buffer implementation files")
Cc: <mesa-stable@lists.freedesktop.org>
2019-11-11 21:46:51 +00:00
Lionel Landwerlin
048f0690ee anv: invalidate file descriptor of semaphore sync fd at vkQueueSubmit
We always close the in_fence at the end the anv_cmd_buffer_execbuf()
so when we take it from the semaphore, let's not forget to invalidate
it.

Note that the code leaks the fence_in if we get any error before
reaching the close(). Let's fix that in another patch or better,
rewrite the whole thing!

v2: drop redundant fd = -1 (Jason)

v3: Update commit message (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 21:46:51 +00:00
Rhys Perry
de998d3eb5 radv: fix radv_nir_get_max_workgroup_size when nir=NULL
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 84a1a2578 ('compiler: pack shader_info from 160 bytes to 96 bytes')
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-11 20:44:12 +00:00
Lionel Landwerlin
f93bb90302 mesa: check framebuffer completeness only after state update
The change made in 88d665830f ("mesa: check draw buffer completeness
on glClearBufferfi/glClearBufferiv") correctly updated the state prior
to checking the framebuffer completeness on glClearBufferiv but not in
glClearBufferfi.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Fixes: 88d665830f ("mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv")
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/issues/2072
2019-11-11 22:04:55 +02:00
Caio Marcelo de Oliveira Filho
d4a3b09c4b glsl: Check earlier for MaxTextureImageUnits and MaxImageUniforms
Currently the linker do all the work then check for the limits, which
means num_textures and num_images in shader_info may have to store more
than the limit.  This breaks down now since shader_info was packed and
doesn't expect to store larger invalid values.

To fix this, pull the check before we set the counts in shader_info.
Add necessary plumbing to make sure we bail once those errors are
found.

Fixes: 84a1a2578d ("compiler: pack shader_info from 160 bytes to 96 bytes")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 10:58:40 -08:00
Caio Marcelo de Oliveira Filho
fce76ae769 glsl: Check earlier for MaxShaderStorageBlocks and MaxUniformBlocks
Currently the linker do all the work then check for the limits, which
means num_ssbos and num_ubos in shader_info may have to store more
than the limit.  This breaks down now since shader_info was packed and
doesn't expect to store larger invalid values.

To fix this, pull the check before we set the counts in shader_info.
One drawback of this approach is that for some cases we might not see
the collected errors from various stages, but bail as soon as a stage
breaks the limits.

Fixes: 84a1a2578d ("compiler: pack shader_info from 160 bytes to 96 bytes")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-11 10:58:40 -08:00
Dylan Baker
a8d941091f util: Use ZSTD for shader cache if possible
This allows ZSTD instead of ZLIB to be used for compressing the shader
cache.

On a 72 core system emulating skl with a full shader-db (with i965):
ZSTD:
    1915.10s user 229.27s system 5150% cpu 41.632 total (cold cache)
    225.40s user 10.87s system 3810% cpu 6.201 total (warm cache)
    154M (235M on disk)
ZLIB:
    2231.33s user 194.24s system 1899% cpu 2:07.72 total (cold cache)
    229.15s user 10.63s system 3906% cpu 6.139 total (warm cache)
    163M (244M on disk)

Tim Arceri sees (8 core ryzen and a full shader-db):
ZSTD:
    2505.22 user 40.50 system 3:18.73 elapsed 1280% CPU (cold cache)
    418.71 user 14.93 system 0:46.53 elapsed 931% CPU (warm cache)
    454.3 MB (681.7 MB on disk)
ZLIB:
    3069.83 user 40.02 system 4:20.13 elapsed 1195% CPU (cold cache)
    425.50 user 15.17 system 0:46.80 elapsed 941% CPU (warm cache)
    470.3 MB (701.4 MB on disk)

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-11 18:53:45 +00:00
Laurent Carlier
57acf921e2 egl: avoid local modifications for eglext.h Khronos standard header file
Move differences in eglextchromium.h header file, then provide the same header than libglvnd-1.2
So program that omit to include eglextchromium.h will fail to build with both mesa and libglvnd headers.

Fixes: a0a8109f "include: add the definition of EGL_EXT_image_flush_external"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-11 17:20:16 +00:00
Eric Engestrom
eaf4396602 egl: move #include of local headers out of Khronos headers
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-11 17:20:16 +00:00
Jason Ekstrand
69244fc72a intel/fs: Lower large local arrays to scratch
Shader-db results on Kaby Lake:

    total instructions in shared programs: 14929212 -> 14880028 (-0.33%)
    instructions in affected programs: 72428 -> 23244 (-67.91%)
    helped: 6
    HURT: 2
    helped stats (abs) min: 2165 max: 15981 x̄: 8590.00 x̃: 7624
    helped stats (rel) min: 56.06% max: 74.52% x̄: 67.55% x̃: 72.08%
    HURT stats (abs)   min: 1178 max: 1178 x̄: 1178.00 x̃: 1178
    HURT stats (rel)   min: 350.60% max: 361.35% x̄: 355.97% x̃: 355.97%
    95% mean confidence interval for instructions value: -11947.03 -348.97
    95% mean confidence interval for instructions %-change: -125.72% 202.37%
    Inconclusive result (%-change mean confidence interval includes 0).

    total cycles in shared programs: 368585300 -> 342557344 (-7.06%)
    cycles in affected programs: 28144921 -> 2116965 (-92.48%)
    helped: 6
    HURT: 2
    helped stats (abs) min: 1404978 max: 7766106 x̄: 4353922.00 x̃: 3890682
    helped stats (rel) min: 82.01% max: 95.57% x̄: 89.95% x̃: 92.28%
    HURT stats (abs)   min: 47778 max: 47798 x̄: 47788.00 x̃: 47788
    HURT stats (rel)   min: 278.20% max: 282.98% x̄: 280.59% x̃: 280.59%
    95% mean confidence interval for cycles value: -5900438.73 -606550.27
    95% mean confidence interval for cycles %-change: -140.79% 146.16%
    Inconclusive result (%-change mean confidence interval includes 0).

    total spills in shared programs: 9243 -> 8901 (-3.70%)
    spills in affected programs: 2718 -> 2376 (-12.58%)
    helped: 4
    HURT: 4

    total fills in shared programs: 21831 -> 10141 (-53.55%)
    fills in affected programs: 11804 -> 114 (-99.03%)
    helped: 6
    HURT: 2

    total sends in shared programs: 815912 -> 815912 (0.00%)
    sends in affected programs: 0 -> 0
    helped: 0
    HURT: 0

    LOST:   1
    GAINED: 3

The helped shaders are all compute shaders in Aztec Ruins.  There is
also a compute shader in synmark2 OglCSDof that's helped but it doesn't
show up in above shader-db results because it went from SIMD8 to SIMD16.
That shader improves enough to yield an 15-20% performance boost to the
benchmark as a whole on my KBL laptop.  The hurt shaders are a couple
shaders in Kerbal Space Program and a couple in Aztec Ruins.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
53bfcdeecf intel/fs: Implement the new load/store_scratch intrinsics
This commit fills in a number of different pieces:

 1. We add support to brw_nir_lower_mem_access_bit_sizes to handle the
    new intrinsics.  This involves simple plumbing work as well as a
    tiny bit of extra logic to always scalarize scratch intrinsics

 2. Add code to brw_fs_nir.cpp to turn nir_load/store_scratch intrinsics
    into byte/dword scattered read/write messages which use the A32
    stateless model.

 3. Add code to lower_surface_logical_send to handle dword scattered
    messages and the A32 stateless model.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
e2297699de intel/nir: Plumb devinfo through lower_mem_access_bit_sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
1dff48af05 intel/fs: refactor surface header setup
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
a0999bc049 intel/fs: Add DWord scattered read/write opcodes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
83f04d80b0 intel/nir: Use nir_extract_bits in lower_mem_access_bit_sizes
The new helper solves most of the annoying problems with data wrangling
in brw_nir_lower_mem_access_bit_sizes.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Jason Ekstrand
b8d45d9307 nir: Add tests for nir_extract_bits 2019-11-11 17:17:02 +00:00
Jason Ekstrand
d0bbf98c96 nir/builder: Add a nir_extract_bits helper
This new helper is better than nir_bitcast_vector because it's able to
take a (mostly) arbitrary range from the source vector.  The only
requirement is that first_bit has to be aligned to the smaller of the
two bit sizes.  It wouldn't be hard to lift that requirement but it's
reasonable for now.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-11 17:17:02 +00:00
Eric Engestrom
86d3a346f1 egl: fix _EGL_NATIVE_PLATFORM fallback
When the X11 or Haiku platforms were compiled in, they would bypass the
`_EGL_NATIVE_PLATFORM` fallback by always returning themselves instead.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-11 17:14:07 +00:00
Ricardo Garcia
20b403aad0 anv: Unify GetDeviceQueue and GetDeviceQueue2
Avoid duplicating some checks and code by making anv_GetDeviceQueue a
subcase of anv_GetDeviceQueue2, like radv does.

Signed-off-by: Ricardo Garcia <rgarcia@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-11 16:14:56 +00:00
Alyssa Rosenzweig
5b31182665 panfrost: Select format-specific blending intrinsics
If we have an accelerated path for a particular framebuffer format,
let's use it to save a bunch of instructions in a blend shader.

[Tomeu: Only use the faster intrinsic on >T760]

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-11 15:23:44 +00:00
Alyssa Rosenzweig
3295edaadf pan/midgard: Pack load/store masks
While most load/store operations on 32-bit/vec4 intriniscally, some are
not and have special type-size-dependent semantics for the mask. We need
to convert into this native format.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-11 15:23:44 +00:00
Alyssa Rosenzweig
843874c7c3 pan/midgard: Implement nir_intrinsic_load_output_u8_as_fp16_pan
We can use the native Midgard ops for this, depending what chip we're
on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-11 15:23:44 +00:00
Alyssa Rosenzweig
5885b64e42 pan/midgard: Identify ld_color_buffer_u8_as_fp16*
There are two versions of this opcode, depending what version of the ISA
you're using. I'm not sure if there's a semantic difference; I think
there might be some slight subtleties but it's too early to know at this
stage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-11 15:23:44 +00:00
Alyssa Rosenzweig
03f73c7fc6 nir: Add load_output_u8_as_fp16_pan intrinsic
This is a single opcode, at least on newer Midgard chips. It's easier to
have this represented in NIR rather than trying to optimize out the
conversions, so let's add the intrinsic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-11 15:23:44 +00:00
Tomeu Vizoso
ee5321f239 panfrost: Set depth and stencil for SFBD based on the format
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-11 15:23:44 +00:00
Erik Faye-Lund
b4d47e21d7 zink: correct depth-stencil format
When using packed vulkan-formats on little-endian systems, we need to
swap the components for the gallium formats. And since Zink isn't
big-endian safe yet, little-endian is the only endianess we care about
right now.

This fixes a bunch of piglit tests, amongs others:
- spec@arb_depth_texture@depth-level-clamp
- spec@arb_depth_texture@depthstencil-render-miplevels * d=z24
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-blit
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-copypixels
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-drawpixels
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-readpixels

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
2019-11-11 14:35:53 +00:00
Erik Faye-Lund
d7a6cc8f4a zink/spirv: add support for nir_op_flrp
This fixes the following piglit:

spec@ati_fragment_shader@ati_fragment_shader-render-fog

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-11-11 14:25:30 +01:00
Chris Wilson
863872e141 egl: Mention if swrast is being forced
The system can be disabling HW acceleration unbeknown to the user,
leading to a long debug session trying to work out which component is
failing. A quick mention that it is the environment override would be
very useful.

v2: Use more generic "CPU renderer" and so try to avoid jargon.

Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Martin Peres <martin.peres@linux.intel.com>
2019-11-11 11:52:02 +00:00
Jason Ekstrand
9e440b8d0b spirv: Sort out the mess that is sampled image
This commit makes two major changes.  First, we add a second case to
OpLoad for sampled images which constructs a vtn_sampled_image and
stashes that rather than stashing a pointer to the combined image
sampler like we do for bare samplers and images.  This should be more in
line with how SPIR-V is intended to work and hopefully doesn't cause any
weird problems.  The second is a rework of vtn_handle_texture to assume
that everything has an image but not everything has a sampler.  We also
add a vtn_fail_if for the case where a texture instructions require a
sampler but none is provided.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-09 15:29:01 +00:00
Jason Ekstrand
9cc4c2c916 spirv: Add a vtn_decorate_pointer helper
This helper makes a duplicate copy of the pointer if any new access
flags are set at this stage.  This way we don't end up propagating
access flags further than they actual SPIR-V decorations.  In several
instances where we create new pointers, we still call the decoration
helper directly because no copy is needed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-09 15:29:01 +00:00
Jason Ekstrand
4f9688e571 spirv: Remove the type from sampled_image
We have types on all vtn_values at this point so there's no reason to
carry the redundant type information.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-09 15:29:01 +00:00
Rob Clark
a3dc975ee7 freedreno/ir3: also track # of nops for shader-db
The instruction count is (mostly) a measure of what optimization passes
can do, while # of nops is more an indication of how effectively the
scheduler is balancing register pressure vs instruction count.  So track
these independently.

(There could be opportunities to rematerialize values to reduce register
pressure, swapping some nop's with other alu instructions, so nothing is
truely independent.. but it is still useful to break these stats out.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
5f45818673 freedreno/ir3: sync disasm changes from envytools
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
f3980a8ef7 freedreno/a4xx: fix SP_FS_MRT_REG.HALF_PRECISION
Set flag based on actual output reg type.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
f0f9ec6882 freedreno/a3xx: fix SP_FS_MRT_REG.HALF_PRECISION
We should really be setting this based on the actual output register
type.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
df229977c3 freedreno/ir3: remove obsolete comment
The meta PHI instruction was removed long ago.  And fanin/fanout
themselves to not contribute actual instructions (at least not by the
time you get to sched, they may prevent copy-propagating away a mov)

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
e804b42fd7 freedreno/ir3/ra: remove ir print after livein/out
The IR hasn't changed at this point, so it isn't really adding any
value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
8b92052f10 freedreno/ir3/ra: move regs_count==0 check
Fold it in to writes_gpr() (since a register that does not reference any
registers by definition does not write a register).  This lets us avoid
having to handle this case in a few other places.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
bd21c73d3f freedreno/ir3: ir3_print tweaks
Handle HALF/HIGH flags in all cases, and colorize SSA src notation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:15 +00:00
Rob Clark
5da10704bb freedreno/ir3: use SSA flag on dest register too
We did this in some places before, but not consistantly.  But it will be
useful for two-pass RA, to identify which registers have already been
assigned.

While we are cleaning this up, use __ssa_src() and new __ssa_dst()
helper more consistently.  (If nothing else, this reduces the # of
callers of ir3_reg_create() to audit that we didn't miss something)

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:14 +00:00
Rob Clark
8449f6183f freedreno/ir3: split pre-coloring to it's own function
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-11-09 02:49:14 +00:00
Caio Marcelo de Oliveira Filho
087ecd9ca5 spirv: Don't leak GS initialization to other stages
The stage specific fields of shader_info are in an union.  We've
likely been lucky that this value was either overwritten or ignored by
other stages.  The recent change in shader_info layout in commit
84a1a2578d ("compiler: pack shader_info from 160 bytes to 96 bytes")
made this issue visible.

Fixes: cf2257069c ("nir/spirv: Set a default number of invocations for geometry shaders")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-08 16:28:21 -08:00
Marek Olšák
84a1a2578d compiler: pack shader_info from 160 bytes to 96 bytes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-08 16:54:08 -05:00
Marek Olšák
9950523368 glsl/linker: pass shader_info to analyze_clip_cull_usage directly
This will be needed by the next commit.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-11-08 16:54:06 -05:00
Marek Olšák
3ef50b023e radeonsi/nir: fix compute shader crash due to nir_binary == NULL
This partially reverts 8b30114dda.

Fixes: 8b30114dda "radeonsi/nir: call nir_serialize only once per shader"
2019-11-08 16:47:59 -05:00
Marek Olšák
8b30114dda radeonsi/nir: call nir_serialize only once per shader
We were calling it twice.

First serialize it, then use it to compute the cache key.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-08 15:30:28 -05:00
Marek Olšák
ad56022b0d util: add blob_finish_get_buffer
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-08 15:30:28 -05:00
Eric Anholt
b1f38aed84 u_format: Fix swizzle of A1R5G5B5.
Found once I started using the generated unpack code from the Mesa side.

Fixes: 4bbaac3782 ("gallium: Add some more channel orderings of packed formats.")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-11-08 11:56:02 -08:00
David Stevens
0466239aae virgl: support emulating planar image sampling
Mesa emulates planar format sampling with per-plane samplers. Virgl now
supports this by allowing the plane index to be passed when creating a
sampler view from a planar image. With this change, mesa now passes that
information to virgl.

Signed-off-by: David Stevens <stevensd@chromium.org>
Reviewed-by: Lepton Wu <lepton@chromium.org>
2019-11-08 17:06:56 +00:00
Krzysztof Raszkowski
084431ce45 gallium/swr: Enable some ARB_gpu_shader5 extensions
Enable / add to features.txt:
- Enhanced textureGather.
- Geometry shader instancing.
- Geometry shader multiple streams.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-11-08 16:04:47 +00:00
Krzysztof Raszkowski
e5ed9a1b91 gallium/swr: Fix GS invocation issues
- Fixed proper setting gl_InvocationID.
- Fixed GS vertices output memory overflow.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-11-08 14:52:16 +00:00
Timur Kristóf
911a826141 ac: Handle invalid GFX10 format correctly in ac_get_tbuffer_format.
It happens that some games try to access a vertex buffer without
a valid format. This case was incorrectly handled by
ac_get_tbuffer_format which made ACO emit an invalid instruction.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-08 13:30:30 +01:00
Boris Brezillon
ee82f9f07e panfrost: Try to evict unused BOs from the cache
The panfrost BO cache can only grow since all newly allocated BOs are
returned to the cache (unless they've been exported).

With the MADVISE ioctl that's not a big issue because the kernel can
come and reclaim this memory, but MADVISE will only be available on 5.4
kernels. This means an app can currently allocate a lot memory without
ever releasing it, leading to some situations where the OOM-killer kicks
in and kills the app (or even worse, kills another process consuming
more memory than the GL app) to get some of this memory back.

Let's try to limit the amount of BOs we keep in the cache by evicting
entries that have not been used for more than one second (if the app
stopped allocating BOs of this size, it's likely to not allocate
similar BOs in a near future).

This solution is based on the VC4/V3D implementation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 11:26:47 +01:00
Boris Brezillon
25059cc41f panfrost: Move BO cache related fields to a sub-struct
We will soon introduce an LRU list to evict BOs that have been unused
for more than 1 second. Let's first move all BO cache fields to a
sub-struct to clarify which fields are used by the BO caching logic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 11:26:47 +01:00
Alyssa Rosenzweig
5f768eda43 pan/midgard: Switch base for vertex texturing on T720
There aren't texture pipeline registers anymore; instead, space is
shared with work and ldst registers for output and input respectively.
We need to shift the base registers to represent this correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 06:45:03 +00:00
Alyssa Rosenzweig
ac14facf7a pan/midgard: Pass shader stage to disassembler
Vertex texturing behaves differently from fragment texturing on some
GPUs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 06:45:03 +00:00
Alyssa Rosenzweig
515941202d pan/midgard: Disassemble half-steps correctly
The meaning of some bits shifts; we need to account for this to print
swizzles sanely.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 06:45:03 +00:00
Alyssa Rosenzweig
ec2af6bc97 pan/midgard: Fix printing of half-registers in texture ops
We were using old style half-registers; let's update that to be
consistent, preparing us for more disassmbler changes in this area.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-08 06:45:03 +00:00
Kristian H. Kristensen
4a4fad7f40 freedreno/ir3: Use regid() helper when setting up precolor regs
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:46:21 -08:00
Kristian H. Kristensen
3699a74a43 freedreno/a6xx: Turn on tessellation shaders
Wow. Very triangle. So shader.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
53782571ae freedreno/a6xx: Only use merged regs and four quads for VS+FS
When other geometry stages are present, we chose two quads and no
merged regs.

Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
07aedc367c freedreno/blitter: Save tessellation state
We have tessellation state now.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
d2d0c8186d freedreno/a6xx: Only set emit.hs/ds when we're drawing patches
At least the gallium blitter helper will call us to draw with
tessellation shaders set but a non-patch primitive.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>

Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
e584790885 freedreno: Use bypass rendering for tessellation
It seems like tiling could work in the Adreno architecture, but we've
only ever seen bypass rendering with tessellation.  For now, let's do
that too.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
47e2c19511 freedreno/a6xx: Program state for tessellation stages
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
03a30e7c3d freedreno/a6xx: Emit constant parameters for tessellation stages
Assemble the information the stages need and emit the constants.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
5dd51d2da7 freedreno/a6xx: Allocate and program tessellation buffer
Tessellation needs a couple of buffers that should hold the entire
output from a full VS+TCS draw call.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
f0ef3e9697 freedreno/a6xx: Build the right draw command for tessellation
We need to select the right primitive type, set a bit to turn on
tessellation and or in the TES output primitive type.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
7272e8a709 freedreno/ir3: Allocate const space for tessellation parameters
The tessellation stages need size and stride or the patch layout as
well as locations of attributes in the patch.  The tesselation stages
also use two system memory BOs and need the iovas of those.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
8739ea3ab5 freedreno/ir3: Pre-color TCS header and primitive ID inputs
Similar to GS, the registers are shared and not reinitialized betewen
VS and TCS, so we need to make sure to allocate the same registers for
the system values between stages.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
b12ebe3e81 freedreno/ir3: Don't assume binning shader is always VS
In tessellation mode, the TES is (probably) the binning shader.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
3cedeba7c9 freedreno/ir3: Setup inputs and outputs for tessellation stages
Similar to GS, some inputs are reused when the chsh from VS to TCS or
TES to GS, so we need to make sure we setup the right inputs and make
the shared system values outputs so they don't get clobbered.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
e28fbbd861 freedreno/ir3: Implement TCS synchronization intrinsics
We add two new IR3 specific nir intrinsics that map to the new condend
and endpatch instructions.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:40:27 -08:00
Kristian H. Kristensen
4915231b8a freedreno/ir3: Implement tess coord intrinsic
Our lowering pass made the z component unused by replacing its uses
by 1 - x - y.  The intrinsic implementation then just need to return
the x and y components.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:37:08 -08:00
Kristian H. Kristensen
e16e48d00c freedreno/ir3: End TES with chsh when using GS
When we have both TES and GS, the TES needs to chain to the VS with
chmask and chsh GS just like the VS does to either TCS or GS.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:37:05 -08:00
Kristian H. Kristensen
581cd59692 freedreno/ir3: Add new synchronization opcodes
There are two new opcodes in use in tesselation control shaders:
category 0, opcodes 13 and 15.  unk13 is a kill type of instruction
that terminates threads where !p0.x and it used to narrow down a patch
wavefront to just thread 0.  Then, once thread 0 has written the tess
levels, it issues unk15, which might signal the TE that another patch
has been fully written.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:37:02 -08:00
Kristian H. Kristensen
56ed835bff freedreno/ir3: Extend geometry lowering pass to handle tessellation
VS and TCS pass varyings the same way as VS and GS does. TCS then
writes entire patch to a system memory BO and TES eventually reads
back from the BO once the TE starts generating vertices.  TES outputs
vertices the same way as VS and GS, except when there's a GS as well,
in which case TES passes varyings to GS same way the VS would.

In addition, the TCS needs a little bit of control flow massaging so
that it only runs for valid invocations needs a couple of unknown
instructions to synchronize with the TE.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:59 -08:00
Kristian H. Kristensen
8621fbc37b freedreno/ir3: Add tessellation field to shader key
Whether we're tessellating and which primitives the TES outputs
affects the entire pipeline so let's add a field to the key to track
that.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:56 -08:00
Kristian H. Kristensen
77b96b843e freedreno/ir3: Use imul24 in offset calculations
With the imul24 opcode in place, we can now use it for computing local
offsets (ie for ldlw/stlw).

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:53 -08:00
Kristian H. Kristensen
41984c8422 freedreno/ir3: Add ir3 intrinsics for tessellation
These provide the iovas for system memory buffers used for
tessellation as well as a new HW specific system value.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:50 -08:00
Kristian H. Kristensen
d6209a50bb freedreno: Don't count primitives for patches
The gallium helper doesn't like patches and we can't determine how
many primitives it gets tessellated into anyway.  On gens where we
have tessellation, we get the prim count from a HW counter so just
skip counting on the CPU.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:47 -08:00
Kristian H. Kristensen
fe450ef4cf freedreno/ir3: Add load and store intrinsics for global io
These intrinsics take a ivec2 for the 64 bit base address and a
integer offset.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:44 -08:00
Kristian H. Kristensen
5d67da13a3 freedreno/ir3: Emit link map as byte or dwords offsets as needed
Stages that load inputs with ldlw (TCS, GS) need byte offsets, stages
that load with ldg (TES) need dwords offsets.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:42 -08:00
Kristian H. Kristensen
1f3b52ce50 freedreno/a6xx: Add register offset for STG/LDG
These instructions take a 64 bit iova as two conescutive registers and
a immediate offset.  This patch adds support for the offset to be a
single register, which is added to the 64 bit iova.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:39 -08:00
Kristian H. Kristensen
3d16ec4a71 freedreno/a6x: Rename z/s formats
What we call eRB6_Z24_UNORM_S8_UINT now is actually
RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 and RB6_X8Z24_UNORM is actually
RB6_Z24_UNORM_S8_UINT.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:36 -08:00
Kristian H. Kristensen
50124afe34 freedreno/a6xx: Fix layered texture type enum
2D array textures and 3D textures are different enum values after all.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:33 -08:00
Kristian H. Kristensen
0276d0766d freedreno: Add nogmem debug option to force bypass rendering
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:31 -08:00
Kristian H. Kristensen
7fed7c2a7d freedreno/a6xx: Clear sysmem with CP_BLIT
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:28 -08:00
Kristian H. Kristensen
b0b443dcab freedreno/a6xx: Fix primitive counters again
We use one mechanism for (REG_A6XX_RBBM_PRIMCTR_8_LO)
PIPE_QUERY_PRIMITIVES_GENERATED, which counts all primitives that exit
the geometry pipeline, whether or not xfb is on.  Then for
PIPE_QUERY_PRIMITIVES_EMITTED, we use the CP_EVENT_WRITE subfunction
that writes out per-stream counts for generated and emitted, but only
when xfb is enabled.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:22 -08:00
Kristian H. Kristensen
835f8d1ba1 freedreno/registers: Add comments about primitive counters
Adding comments about best guess at what the counters count.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:19 -08:00
Kristian H. Kristensen
96968d0ba2 freedreno/registers: Move SP_PRIMITIVE_CNTL and SP_VS_VPC_DST
Move these two to be in order with the other VS regs.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:36:16 -08:00
Kristian H. Kristensen
ba54f7dd03 freedreno/registers: Fix typo
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-11-07 16:35:27 -08:00
Rhys Perry
78e3ea9a0f aco: add Instruction::usesModifiers() and add more checks in the optimizer
No pipeline-db changes.

v2: use early-exit for VOP3

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
2019-11-08 00:14:06 +00:00
Rhys Perry
76544f632d radv: adjust loop unrolling heuristics for int64
In particular, increase the cost of 64-bit integer division.

Fixes huge shaders with dEQP-VK.spirv_assembly.type.scalar.i64.mod_geom
, with ACO used for GS this creates shaders requiring a branch with
>32767 dword offset.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-07 23:29:12 +00:00
Erico Nunes
9817bff4da lima: fix bo submit memory leak
Fix memory leak on allocation for lima submit, reported by valgrind.

128 bytes in 1 blocks are definitely lost in loss record 38 of 84
   at 0x484A6E8: realloc (in /usr/lib/valgrind/vgpreload_memcheck-arm64-linux.so)
   by 0x58689C7: util_dynarray_ensure_cap (u_dynarray.h:91)
   by 0x5868BBB: util_dynarray_grow_bytes (u_dynarray.h:139)
   by 0x5868BBB: lima_submit_add_bo (lima_submit.c:113)
   by 0x585D7D3: lima_ctx_buff_va (lima_context.c:57)
   by 0x586378F: lima_pack_plbu_cmd (lima_draw.c:802)
   by 0x586378F: lima_draw_vbo (lima_draw.c:1351)
   by 0x5406A2F: u_vbuf_draw_vbo (u_vbuf.c:1184)
   by 0x55D0A57: st_draw_vbo (st_draw.c:268)
   by 0x55576CB: _mesa_draw_arrays (draw.c:374)
   by 0x55576CB: _mesa_draw_arrays (draw.c:351)
   by 0x43610B: Mesh::render_vbo() (mesh.cpp:583)
   by 0x415DBB: SceneBuild::draw() (scene-build.cpp:242)
   by 0x41131B: MainLoop::draw() (main-loop.cpp:133)
   by 0x411947: MainLoop::step() (main-loop.cpp:108)

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-11-07 23:03:01 +00:00
Erico Nunes
d939f5d463 lima: fix nir shader memory leak
Fix memory leak on allocation for nir shader, reported by valgrind.

3,502 (480 direct, 3,022 indirect) bytes in 1 blocks are definitely lost in loss record 77 of 84
   at 0x48483F8: malloc (in /usr/lib/valgrind/vgpreload_memcheck-arm64-linux.so)
   by 0x5750817: ralloc_size (ralloc.c:119)
   by 0x5750977: rzalloc_size (ralloc.c:151)
   by 0x575C173: nir_shader_create (nir.c:45)
   by 0x5763ACB: nir_shader_clone (nir_clone.c:728)
   by 0x55D5003: st_create_fp_variant (st_program.c:1242)
   by 0x55D789F: st_get_fp_variant (st_program.c:1522)
   by 0x55D789F: st_get_fp_variant (st_program.c:1507)
   by 0x56400C3: st_update_fp (st_atom_shader.c:163)
   by 0x563D333: st_validate_state (st_atom.c:261)
   by 0x55D07CB: prepare_draw (st_draw.c:132)
   by 0x55D08DF: st_draw_vbo (st_draw.c:184)
   by 0x55576CB: _mesa_draw_arrays (draw.c:374)
   by 0x55576CB: _mesa_draw_arrays (draw.c:351)

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-11-07 23:03:01 +00:00
Prodea Alexandru-Liviu
1a05811936 Meson: Remove lib prefix from graw and osmesa when building with Mingw.
Also remove version sufix from osmesa swrast on Windows.

v2: Make sure we don't remove lib prefix on *nix platforms.

Signed-off-by: Prodea Alexandru-Liviu <liviuprodea@yahoo.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

Cc: "19.3" <mesa-stable@lists.freedesktop.org>
2019-11-07 22:04:50 +00:00
Marek Olšák
0b3111ed84 mesa: expose SPIR-V extensions in the Compatibility profile too
We would like to have GL 4.6 Compatibility too.

The extensions don't support compatibility features, so no other changes
are needed.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-11-07 16:04:30 -05:00
Drew DeVault
299c55df88 st_get_external_sampler_key: improve error message
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 15:57:23 -05:00
Eric Anholt
9d2c8df3eb mesa/st: Make st_pipe_format_to_mesa_format an effective no-op.
All callers other than the unit test just wanted to convert back from
a known-mesa-equivalent format, which is now a no-op.

v2: Fix assertion failure in iris GL startup with BGR565 by continuing
    to return MESA_FORMAT_NONE for non-Mesa formats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2019-11-07 19:43:41 +00:00
Eric Anholt
75921a0912 mesa/st: Gut most of st_mesa_format_to_pipe_format().
Now that MESA_FORMAT_x is just a PIPE_FORMAT_x define, we can strip
this function down to just the compression fallbacks.

v2: Restore the SRGB format for ASTC SRGB fallback case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
807a800d8c mesa: Redefine MESA_FORMAT_* in terms of PIPE_FORMAT_*.
There are various places in Mesa where we would like to be able to
have a shared format enum between Mesa and gallium (NIR compiler's
image formats, for example, or mapping from gallium's formats to
mesa's and vice versa in st_format.c).  Rewriting all MESA_FORMAT to
PIPE_FORMAT would be disruptive and possibly more work than it's worth
(And I actually prefer MESA_FORMAT's name scheme), so for now just
make it so that there's one shared set of enum values.

The #defines here were generated by printing out from the
tests/st_format.c round-tripping loop, with the exception of 8888
formats where I hand-edited the #defines to point at the corresponding
gallium packed format define.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
d27dda907a mesa: Prepare for the MESA_FORMAT_* enum to be sparse.
To redefine MESA_FORMAT in terms of PIPE_FORMAT enums, we need to fix
places where we iterated up to MESA_FORMAT_COUNT.  I use
_mesa_get_format_name(f) == NULL as the signal that it's not an enum
value with a MESA_FORMAT.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
6b1c250245 mesa/st: Test round-tripping of all compressed formats.
We checked round-tripping of formats without fallbacks, but weren't
setting the compression support flags in the mock context and thus
needed to skip testing those.  Just set all the flags and assert that
no fallbacks are triggered, so we get full test coverage.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
80a8021d6c mesa: Stop defining a full separate format for RGBA_UINT8.
We have packed formats for RGBA and ABGR already, so we can just
pack/unpack code.

v2: Rebase on endianness macro rename

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2019-11-07 19:43:41 +00:00
Eric Anholt
b28eb044cd gallium: Add equivalents of packed MESA_FORMAT_*UINT formats.
These are the last formats that MESA_FORMAT had and PIPE_FORMAT
didn't.  The .csv entries channel sizes and swizzles all came from the
corresponding UNORM format.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
6fab4a7b59 gallium: Add an equivalent of MESA_FORMAT_BGR_UNORM8.
This is the last unorm format that MESA_FORMAT had and PIPE_FORMAT
didn't.  Note that it's an array format on gallium's side as well,
since it's a NPOT pixel size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
4bbaac3782 gallium: Add some more channel orderings of packed formats.
This covers everything that MESA_FORMAT had for packed unorm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
6196259d95 gallium: Add defines for FXT1 texture compression.
This texture compression is exposed by 830 and 915, and to make
MESA_FORMAT match PIPE_FORMAT defines I need a corresponding
PIPE_FORMAT.

v2: Set is_hand_written so we don't try to generate pack/unpack code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Eric Anholt
cb9fefe1db mesa/st: Add mapping of MESA_FORMAT_RGB_SNORM16 to gallium.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-07 19:43:41 +00:00
Samuel Pitoiset
deafe4cc58 radv/gfx10: fix primitive indices orientation for NGG GS
The primitive indices have to be swapped to follow the drawing
order.

This fixes corruption with Overwatch when NGG GS is force enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-07 19:21:15 +00:00
Kenneth Graunke
49ee657ef8 Revert "intel/blorp: Fix usage of uninitialized memory in key hashing"
This reverts commit 4432a2d14d.

Pretty much every SKQP test dies with this assertion:
skqp: ../src/mesa/drivers/dri/i965/brw_program_cache.c:102: hash_key: Assertion `item->key_size % 4 == 0' failed.
2019-11-07 09:27:12 -08:00
Danylo Piliaiev
4432a2d14d intel/blorp: Fix usage of uninitialized memory in key hashing
The automatically generated padding in structs contains
undefined values, force pack the structs to eliminate the
padding. Otherwise structs with the same values may generate
different hashes.

Valgrind output:

Conditional jump or move depends on uninitialised value(s)
 util_fast_urem32 (fast_urem_by_const.h:71)
 hash_table_search (hash_table.c:262)
 _mesa_hash_table_search (hash_table.c:296)
 anv_pipeline_cache_search_locked (anv_pipeline_cache.c:318)
 anv_pipeline_cache_search (anv_pipeline_cache.c:335)
 lookup_blorp_shader (anv_blorp.c:38)
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1112)
 blorp_mcs_partial_resolve (blorp_clear.c:1205)
 anv_image_mcs_op (anv_blorp.c:1742)
 anv_cmd_predicated_mcs_resolve (genX_cmd_buffer.c:774)
 transition_color_buffer (genX_cmd_buffer.c:1159)
 cmd_buffer_end_subpass (genX_cmd_buffer.c:4840)

Uninitialised value was created by a stack allocation
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1103)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-07 16:02:55 +00:00
Dylan Baker
0013af540d osmesa/tests: Extend render test to cover other working cases
Only the GL_UNSIGNED_BYTE cases actually work, the rest all fail, but we
should test the working cases to ensure that they continue to work.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-11-07 06:11:19 -08:00
Dylan Baker
7bfb56a135 gallium/osmesa: Convert osmesa test to gtest
This uses a bunch of additional C++ features for niceness and safety.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-11-07 06:11:19 -08:00
Dylan Baker
d1767362aa meson: gtest needs pthreads
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-11-07 06:11:19 -08:00
Tomeu Vizoso
072207bc18 panfrost: Pipe the GPU ID into compiler and disassembler
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-11-07 08:48:45 +00:00
Daniel Schürmann
a47e232ccd aco: workaround Tonga/Iceland hardware bug
The workaround got accidentally moved to the wrong place

Fixes: 08d510010b aco: increase accuracy of SGPR limits

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-11-07 09:19:50 +01:00
Boris Brezillon
b60ed3c7b2 panfrost: Release the ctx->pipe_framebuffer ref
ctx->pipe_framebuffer contains the last bound FB state, let's release
resources pointed by this FB state when the context is destroyed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-07 08:33:08 +01:00
Boris Brezillon
8c8e4fd5c6 panfrost: Destroy the upload manager allocated in panfrost_create_context()
pipe->stream_uploader has been allocated with u_upload_create_default()
in panfrost_create_context(), let's destroy it in the context destroy
path.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-07 08:33:08 +01:00
Kai Wasserbäch
ddc588ff71 intel/gen_decoder: Fix unused-but-set-variable warning
This commit fixes the following warning:
../src/intel/common/gen_decoder.c: In function ‘gen_spec_load_from_path’:
../src/intel/common/gen_decoder.c:741:11: warning: variable ‘len’ set but not used [-Wunused-but-set-variable]
  741 |    size_t len, filename_len = strlen(path) + 20;
      |           ^~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-11-07 11:32:55 +11:00
Kai Wasserbäch
acfea09dbd nir: fix unused function warning in src/compiler/nir/nir.c
This commit fixes the following warning:
../src/compiler/nir/nir.c:1827:1: warning: ‘dest_is_ssa’ defined but not used [-Wunused-function]
 1827 | dest_is_ssa(nir_dest *dest, void *_state)
      | ^~~~~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-07 11:32:55 +11:00
Kai Wasserbäch
4f8cc032b7 nir: fix unused variable warning in find_and_update_previous_uniform_storage
This commit fixes the following warning:
../src/compiler/glsl/gl_nir_link_uniforms.c: In function ‘find_and_update_previous_uniform_storage’:
../src/compiler/glsl/gl_nir_link_uniforms.c:166:16: warning: unused variable ‘num_blks’ [-Wunused-variable]
  166 |       unsigned num_blks = nir_variable_is_in_ubo(var) ?
      |                ^~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-07 11:32:55 +11:00
Kai Wasserbäch
8aa4d0bff6 nir: fix unused variable warning in nir_lower_vars_to_explicit_types
This commit fixes the following warning:
../src/compiler/nir/nir_lower_io.c: In function ‘nir_lower_vars_to_explicit_types’:
../src/compiler/nir/nir_lower_io.c:1435:22: warning: unused variable ‘supported’ [-Wunused-variable]
 1435 |    nir_variable_mode supported = nir_var_mem_shared | nir_var_shader_temp | nir_var_function_temp;
      |                      ^~~~~~~~~

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-07 11:32:55 +11:00
Lepton Wu
5a40e153fd gallium: dri2: Use index as plane number.
This fix wrong color when playing video under Android + virgl
configuration.

Fixes: 2decad495f ("gallium/dri2: Support images with multiple planes for modifiers")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lepton Wu <lepton@chromium.org>
2019-11-06 21:58:28 +00:00
Lionel Landwerlin
c1c346f166 anv: implement VK_KHR_separate_depth_stencil_layouts
v2: Use ternary to simplify code (Jason)

v3: Reorder switch cases to follow existing section ordering (Nanley)
    Add missing comment in cmd_buffer_end_subpass() about new layout (Nanley)

v4: Fix layout comparison for stencil case (Nanley)
    Update a few more comments (Nanley)
    Move VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR in color
    attachment case for future stencil-CCS support (Nanley)

v5: Missed comments update (Nanley)
    Updated relnotes.txt (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-11-06 20:13:30 +00:00
Eric Anholt
cb655d2554 Revert "ci: Switch over to an autoscaling GKE cluster for builds."
This reverts commit c9df92bf79.

It turns out that gitlab-runner uses kubernetes all wrong, spawning Pods
and sshing into them to run the script instead of Jobs containing the
script to run.  This means that when anything goes wrong with the pod
(autoscale, preemption, VM maintenance, cluster reconfiguration), the job
fails and only sometimes gets handled as a runner system failure.  Even
worse, due to bugs in either the runner or k8s itself, some classes of
timeout-related failure end up not being reported as failures, and the job
will incorrectly report success!

Disable using the "autoscale" cluster until we can do something else
(docker-machine instead of k8s, or the custom third-party k8s-native
runner).

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
2019-11-06 11:38:07 -08:00
Tomeu Vizoso
94e6d17043 panfrost: Print the right zero field
Copy paste error.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2019-11-06 18:13:16 +01:00
Dylan Baker
401d7221ed docs: update calendar, add news item and link release notes for 19.2.2 2019-11-06 09:07:02 -08:00
Dylan Baker
6fb82263d4 docs: add sha256 sum to 19.2.3 release notes 2019-11-06 09:05:58 -08:00
Dylan Baker
d7418d67af docs: add release notes for 19.2.3 2019-11-06 09:05:56 -08:00
Tomeu Vizoso
6469c1a445 panfrost: Generate polygon list manually for SFBD
On clears without draws, the SFBD GPUs need for userspace to generate
the trivial polygon list.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:19:31 +01:00
Tomeu Vizoso
8e1ae5fa14 panfrost: Decode blend shaders for SFBD
Also set MALI_HAS_BLEND_SHADER as needed.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:18:46 +01:00
Tomeu Vizoso
afeda06062 panfrost: Take into account texture layers in SFBD
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:18:46 +01:00
Tomeu Vizoso
9447a84f69 panfrost: Rework format encoding on SFBD
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:18:46 +01:00
Tomeu Vizoso
e40d11ccb2 panfrost: Set 0x10 bit on mali_shader_meta.unknown2_4 on T720
Testing shows that it's needed.

Also remove ctx->is_t6xx as it was the last use of it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:17:13 +01:00
Tomeu Vizoso
23fe7cd2d6 panfrost: Add checksum fields to SFBD descriptor
During tests on T720, these fields were discovered.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-06 16:17:13 +01:00
Erik Faye-Lund
bc80900b6c zink: do advertize integer support in shaders
This is supported, so let's correct this.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-11-06 13:43:14 +01:00
Erik Faye-Lund
8920689a58 zink/spirv: implement ball_fequal[2-4] 2019-11-06 13:43:14 +01:00
Erik Faye-Lund
ea2d9b3d38 zink/spirv: implement ball_iequal[2-4] 2019-11-06 13:43:14 +01:00
Erik Faye-Lund
0515ac4571 zink/spirv: implement bany_inequal[2-4] 2019-11-06 13:43:14 +01:00
Erik Faye-Lund
c18c81edc6 zink/spirv: implement bany_fnequal[2-4] 2019-11-06 13:43:14 +01:00
Erik Faye-Lund
4e0ca477d8 zink/spirv: support loading bool constants
Seems I missed this before; let's add support for this.
2019-11-06 13:43:14 +01:00
Erik Faye-Lund
6630baecf1 zink/spirv: drop temp-array for component-count 2019-11-06 13:43:14 +01:00
Michel Dänzer
e0fff37f70 gitlab-ci: Don't build libdrm for ARM
The Debian packages work fine. Saves a little bit of time and disk
space.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-11-06 13:10:07 +01:00
Michel Dänzer
b4d3ae2269 gitlab-ci: Use separate arm64 build/test docker images
The image used for test jobs is only about 1/6 as big as before, which
may help avoid some issues with some of the test boards.

Inspired by https://gitlab.freedesktop.org/mesa/mesa/issues/2046 .

v2:
* Leave LIBDRM_VERSION at 2.4.99 (Daniel Stone)
* Delete more build artifacts from dEQP tree (Daniel Stone)
v3:
* Set LD_LIBRARY_PATH for ldd

Acked-by: Daniel Stone <daniels@collabora.com> # v2
Reviewed-by: Eric Anholt <eric@anholt.net> # Except for the ldd line
2019-11-06 13:10:07 +01:00
Erik Faye-Lund
dd4587b55c zink: use u_blitter when format-reinterpreting 2019-11-06 11:37:36 +00:00
Erik Faye-Lund
7b9d17fe84 zink: always allow sampling of images
This is required if we're going to blit from/to it using u_blitter.
2019-11-06 11:37:36 +00:00
Erik Faye-Lund
1277192d55 zink: transition resources before resolving 2019-11-06 11:37:36 +00:00
Erik Faye-Lund
b385ad0c75 zink: disable fragment-shader texture-lod
We don't support nir_texop_txd, which is required by this cap. So let's
disable it for now.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
2019-11-06 11:37:36 +00:00
Duncan Hopkins
aa64b6dc7f zink: make sure src image is transfer-src-optimal
Fixes: d2bb63c8d4 ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
2019-11-06 11:37:36 +00:00
Erik Faye-Lund
a32a92f53a zink: do not advertize coherent mapping
We do not support them yet, so let's not pretend.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
2019-11-06 11:37:36 +00:00
Erik Faye-Lund
ca87a53b46 zink: always allow mutating the format
There's no good way to know if a texture-view will be created, so we
just have to accept it for all resources.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
2019-11-06 11:37:36 +00:00
Erik Faye-Lund
f3a72fd61c zink: use actual format for render-pass
We should use the format derived from the image-view here, not from the
image itselt. Otherwise, we'll end up with incompatible render-passes.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
2019-11-06 11:37:36 +00:00
Pierre-Eric Pelloux-Prayer
21be5c8edd radeonsi: fix shader disk cache key
Use unsigned values otherwise signed extension will produce a 64 bits value where
the 32 left-most bits are 1.

Fixes: 2afeed3010 ("radeonsi: tell the shader disk cache what IR is used")
2019-11-06 10:15:37 +01:00
Samuel Pitoiset
fb07fd4e6c radv: implement VK_EXT_subgroup_size_control
This extension allows to control the subgroup size by allowing a
varying subgroup size and also specifying a required subgroup size.

This implementation only allows to specify a required subgroup
size for compute shaders because there is some caveats with
other shader stages (eg. NGG with geometry shader). This
basically allows apps to use Wave32 for compute shaders.

This extension is enabled for all chips but only GFX10 supports
Wave32. ACO doesn't support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 09:20:39 +01:00
Samuel Pitoiset
da6c30f9f6 radv: rely on shader's wavesize when computing NGG info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 09:20:36 +01:00
Samuel Pitoiset
d3f9957de4 radv: determine shaders wavesize at pipeline level
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 09:20:34 +01:00
Samuel Pitoiset
d1e1f7c4d5 radv: hardcode the number of waves for the GFX6 LS-HS bug
It's always 64.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 09:20:32 +01:00
Samuel Pitoiset
f010b90ac5 radv/gfx10: enable wave32 for compute based on shader's wavesize
This will allow to change wavesize on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 09:20:30 +01:00
Samuel Pitoiset
c0f76528ae nir: fix packing of nir_variable
The maximum number of descriptor sets is indeed 32 but without
the sign bit.

The maximum number of bindings for RADV is way larger, keep it
as 32-bit.

Fixes: 96e6ef80d9 ("nir: pack the rest of nir_variable::data")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2019-11-06 08:51:53 +01:00
Samuel Pitoiset
0b3bd1a7c2 radv: fix 32-bit compiler warnings
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2031
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 08:00:33 +01:00
Samuel Pitoiset
50b3ec35d2 radv: add a note about perftest/debug options
Now that all environment variables are documented, it would be
appreciated if we can keep this up-to-date.

[skip ci]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 07:58:33 +01:00
Samuel Pitoiset
cc66976d0a docs: document all RADV environment variables
Requested by https://gitlab.freedesktop.org/mesa/mesa/issues/2022

[skip ci]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-06 07:58:22 +01:00
Marek Olšák
8145492f4a nir/serialize: pack nir_variable flags
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-05 23:35:31 -05:00
Marek Olšák
3aa72a394a nir/serialize: store 32-bit object IDs instead of 64-bit
That means we have only 30 bits for object IDs, because 2 bits are
sometimes used for something else.

This decrease the uncompressed shader size for the biggest Borderlands 2
shader from 33.6 KB to 23.2 KB. (31% decrease)

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-05 23:35:31 -05:00
Marek Olšák
d5768fcd45 nir/serialize: don't expand 16-bit variable state slots to 32 bits
the swizzle also needs only 16 bits

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-05 23:35:31 -05:00
Marek Olšák
96e6ef80d9 nir: pack the rest of nir_variable::data
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-05 23:32:34 -05:00
Marek Olšák
442ef8c3e3 radeonsi: keep serialized NIR instead of nir_shader in si_shader_selector
This decreases memory usage, because serialized NIR is more compact.

The main shader part is compiled from nir_shader.
Monolithic shader variants are compiled from nir_binary.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-05 23:28:45 -05:00
Marek Olšák
abb8011f9d radeonsi: don't keep compute shader IR after compilation
not needed. We also need to free TGSI in the destroy function for the case
when an app is terminated and si_create_compute_state_async is never
executed because of util_queue_drop_job.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-05 23:28:43 -05:00
Marek Olšák
62229e8949 radeonsi: use IR SHA1 as the cache key for the in-memory shader cache
instead of using whole IR binaries. This saves some memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-05 23:28:42 -05:00
Vasily Khoruzhick
65a5b24aee lima: add support for gl_PointSize
GP handles gl_PointSize similar to gl_Position, i.e. it needs
separate buffer and it has special type in varying descriptors, also
for indexed draw we need to emit special PLBU command to pass
address of gl_PointSize buffer.

Blob also clamps gl_PointSize to 1 .. 100 (as well as line width),
so let's do the same.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-05 17:44:56 -08:00
Eric Engestrom
73cc2fec10 mesa/imports: let the build system detect strtok_r()
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2013
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Prodea Alexandru-Liviu <liviuprodea@yahoo.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-11-05 22:38:04 +00:00
Eric Engestrom
66dd53584e meson: require nm again on Unix systems
This was made optional in ff9bf223c2 ("meson: make nm binary optional")
for Windows, but proper windows has been added and `nm` is now only used
on Unix systems.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
2019-11-05 20:56:44 +00:00
Eric Engestrom
4d5cde1fff meson: add windows support to symbols checks
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
2019-11-05 20:31:37 +00:00
Eric Engestrom
2f652e0b36 meson: move the generic symbols check arguments to a common variable
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
2019-11-05 20:30:47 +00:00
Eric Engestrom
2c4395e61c meson: add variable to control the symbols checks
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
2019-11-05 20:12:32 +00:00
Pierre-Eric Pelloux-Prayer
67718ca352 mesa: fix call to _mesa_lookup_vao_err
Fixes: 3e842a0b0e ("mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2055
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-11-05 12:05:33 -08:00
Dylan Baker
5d085ad052 meson: Add dep_glvnd to egl deps when building with glvnd
Otherwise if glvnd is not installed systemwide, but only in a prefix,
it's headers wont be found. This happens because if it's headers are in
/usr/include/ then another dependence will provide the necessary -I
arguments and compilation will work.

Fixes: 035ec7a2bb
       ("meson: Add support for EGL glvnd")
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:44:41 +00:00
Dylan Baker
9020f519d2 util/u_endian: Add error checks
As suggested by Eric Engestrom and Michel Dänzer.
2019-11-05 16:39:55 +00:00
Dylan Baker
ee4f1bc187 util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIAN
As requested by Tim.

This was generated with:
grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g

v2: - add this patch

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
6b6897a9f9 gallium/osmesa: Use PIPE_ARCH_*_ENDIAN instead of little_endian function
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
39b9fe03a9 mesa/main: delete now unused _mesa_little_endian
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
f73a9c6586 mesa/swrast: replace instances of _mesa_little_endian with preprocessor
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
453d52acd8 mesa/main: replace uses of _mesa_little_endian with preprocessor
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
f9f60da813 util/u_endian: set PIPE_ARCH_*_ENDIAN to 1
This will allow it to be used as a drop in replacement for
_mesa_little_endian in a number of cases.

v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN,
      define the one that reflects the host system to 1 and the other to 0
    - replace all uses of #ifdef, #ifndef, and #if defined() with #if
      and #if ! with PIPE_ARCH_*_ENDIAN

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
37e54736a7 util/u_endian: Use _WIN32 instead of _MSC_VER
_WIN32 is defined by basically all windows compilers (MSVC, ICL, MinGW),
wereas _MSC_VER is not defined by MinGW. Without this change MinGW falls
through and doesn't define PIPE_ARCH at all, and is caught by some extra
code in gallium.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
cb0dbdd369 dri/osmesa: use preprocessor for selecting endian code paths
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
68d8c1f971 r100: Use preprocessor to select big vs little endian paths
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
a550b6b7f8 r200: use preprocessor for big vs little endian checks
Instead of using a function at runtime we can just build the right code
for the right platform.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Philipp Sieweck
38e706656d svga: check return value of define_query_vgpu{9,10}
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-11-05 16:23:39 +00:00
Tomeu Vizoso
427d0c4b6a gitlab-ci: Run only LAVA jobs in special-named branches
Run only jobs needed for testing on LAVA devices if a branch starts with
lava-ci-.

This allows developers to have faster test cycles as these pipelines
take only a bit above 8 minutes. Also has the advantage of conserving
resources.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-05 16:09:47 +01:00
Pierre-Eric Pelloux-Prayer
febedee4f6 mesa: add EXT_dsa glGetVertexArray* 4 functions
The implementation doesn't share much with get.c because:
  * the refactoring needed for get.c to not depend on ctx->Array.VAO would
    be quite large
  * glGetVertexArray* would still need to filter pname to only accept the one
    specified by the spec
  * these functions are getter, the implementation is trivial (the complexity
    is in the correct filtering of pname input)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
2b44ca779b mesa: extract helper function from _mesa_GetPointerv
Will be used by EXT_dsa gllGetVertexArrayPointervEXT implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
5adeff8033 mesa: add EXT_dsa EnableVertexArrayAttribEXT / DisableVertexArrayAttribEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
f793a8663d mesa: add EXT_dsa glEnableVertexArrayEXT / glDisableVertexArrayEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
a053361793 mesa: add gl_vertex_array_object parameter to client state helpers
This will allow to use the same helper for the EXT_direct_state_access
implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
aef5d99671 mesa: add EXT_dsa glVertexArray* functions implementation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
a78d4e7e75 mesa: add vao/vbo lookup helper for EXT_dsa
Add a single helper dealing with the lookup of both the vao
and the vbo to avoid duplicating this code in all the
glVertexArray* functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
3e842a0b0e mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa
ARB_dsa and EXT_dsa slightly differs when an uninitialized VAO
is requested.
In this case ARB_dsa fails while EXT_dsa requires to initialize
the object.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
a26bb93943 mesa: add EXT_dsa glVertexArray* functions declarations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Pierre-Eric Pelloux-Prayer
bfc1e4c112 mesa: pass vao as a function paramter
This change will allow reusing the same function for the
EXT_direct_state_access implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-05 13:58:28 +01:00
Michel Dänzer
d80dece065 gitlab-ci: Set arm job CCACHE_DIR properly
$PWD doesn't work for variables:, it ended up as "/ccache", always
starting with an empty cache.

v2:
* Use relative path and realpath
v3:
* Use $CI_PROJECT_DIR (Eric Anholt)
* Clear ccache stats in before_script if the cache is in $CI_PROJECT_DIR

Fixes: c9df92bf79 "ci: Switch over to an autoscaling GKE cluster for
                     builds."
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-11-05 09:27:32 +01:00
Kenneth Graunke
337f58438e nir: Handle image arrays when setting variable data
Fixes a ton of regressions in image load store tests.

Fixes: 4319cc8c0f ("nir: pack nir_variable::data::xfb_*")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 18:16:06 -08:00
Paulo Zanoni
b57383a944 intel/compiler: remove the operand restriction for src1 on GLK
Commit 5847de6e9a implemented a restriction that applies to ICL, but
wrongly marked it as also applying to GLK. Reviewers or MR !1125
pointed this, and the commit history shows removal of GLK to parts of
the patch, but it turns there was still a left-over GLK check in the
code.

This code was breaking some of the i8vec2 tests on GLK, for example:
  dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

Removing the GLK check solves the issue for GLK. I don't see a reason
on why implementing this restriction would actually break GLK, so
there's still more to investigate here since this bug may be affecting
ICL+, but let's apply the real GLK fix while we analyze and discuss
the other possible issues.

Fixes: 5847de6e9a ("intel/compiler: don't use byte operands for src1
on ICL")
BSpec: 3017
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2019-11-05 00:08:34 +00:00
Marek Olšák
4319cc8c0f nir: pack nir_variable::data::xfb_*
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 18:17:34 -05:00
Marek Olšák
08dc541b66 nir: pack nir_variable::data::stream
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 18:17:34 -05:00
Ian Romanick
9be4a422a0 nir/algebraic: Mark other comparison exact when removing a == a
This prevents some additional optimizations that would change the
original result.  This includes things like (b < a && b < c) => b <
min(a, c) and !(a < b) => b >= a.  Both of these optimizations were
specifically observed in the piglit tests added in piglit!160.

This was discovered while investigating
https://gitlab.freedesktop.org/mesa/mesa/issues/1958.  However, the
problem in that issue was Chrome or Angle is replacing calls to isnan()
with some stuff that we (correctly) optimize to false.  If they had left
the calls to isnan() alone, everything would have just worked.

No shader-db changes on any Intel platform.

I also tried marking the comparison generated by the isnan() function
precise.  The precise marker "infects" every computation involved in
calculating the parameter to the isnan() function, and this severely
hurt all of the (few) shaders in shader-db that use isnan().

I also considered adding a new ir_unop_isnan opcode that would implement
the functionality.  During GLSL IR-to-NIR translation, the resulting
comparison operation would be marked exact (and the samething would need
to happen in SPIR-V translation).

This approach taken by this patch seemed easier, but we may want to do
the ir_unop_isnan thing anyway.

Fixes: d55835b8bd ("nir/algebraic: Add optimizations for "a == a && a CMP b"")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 14:05:49 -08:00
Ian Romanick
ea19f2fb68 nir/algebraic: Add the ability to mark a replacement as exact
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 14:05:49 -08:00
Marek Olšák
af94600484 compiler: make variable::data::binding unsigned
Nothing seems to set a negative value.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 16:49:46 -05:00
Marek Olšák
4b4b383f38 st/mesa: call nir_lower_flrp only once per shader
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 16:49:44 -05:00
Marek Olšák
7d00218aed st/mesa: call nir_opt_access only once
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-11-04 16:49:42 -05:00
Leo Liu
352b57d709 ac: add missing Arcturus to the info of pc lines
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
2019-11-04 16:27:35 -05:00
Alyssa Rosenzweig
4da648a170 panfrost/ci: Update T760 expectations
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
12d071024b pan/midgard: Extend default_phys_reg to !32-bit
We can pass through a size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
762623381d pan/midgard: Extend swizzle packing for vec4/16-bit
We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
bf5508f7b9 pan/midgard: Extend offset_swizzle to non-32-bit
We take a size parameter; use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
f538981384 pan/midgard: offset_swizzle doesn't need dstsize
This argument should be omitted.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
9eac9389fb pan/midgard: Add bizarre corner case
Someone really needs to look into this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
4ae4d82e21 pan/midgard: Compute bundle interference
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
45ac8ea8bd pan/midgard: Fix quadword_count handling
Spilling can mess with this considerably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Alyssa Rosenzweig
0a77dd3203 pan/midgard: Validate tags when branching
Midgard prefetches instructions based on tag (ALU, LD/ST, texture *
size). To do so, the shader descriptor specifies the tag of the first
instruction, all instructions specify the tag of the next linear
instruction is, and all branches explicitly specify the tag of the
branch target.

If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously
refers to this problem, but it's still annoying to try to work out all
the branch targets in your head to debug.

Instead, let's track the tags of various blocks over time, so we can
automatically validate tags of branch targets, to make
INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 15:36:08 -05:00
Daniel Schürmann
efe737fc4f aco: fix accidential reordering of instructions when scheduling
Fixes: 8678699918 "aco: implement VGPR spilling"

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-04 20:14:14 +01:00
Daniel Schürmann
5c7dcb15e0 aco: only use single-dword loads/stores for spilling
Fixes: 8678699918 "aco: implement VGPR spilling"

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-04 20:14:14 +01:00
Daniel Schürmann
d97c0bdd55 aco: fix immediate offset for spills if scratch is used
Fixes: 8678699918 "aco: implement VGPR spilling"

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
2019-11-04 20:14:14 +01:00
Lionel Landwerlin
ee6fbb95a7 anv: Properly handle host query reset of performance queries
The host query reset entry point didn't use the availability offset
for performance queries.

To fix this, reorder the availability of performance queries to match
other queries.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-04 19:04:38 +00:00
Paul Gofman
ecc31d032e state_tracker: Handle texture view min level in st_generate_mipmap()
Signed-off-by: Paul Gofman <gofmanp@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-11-04 13:24:31 -05:00
James Xiong
b6d45e7f74 iris: try to set the specified tiling when importing a dmabuf
When importing a dmabuf with a specified tiling, the dmabuf user
should always try to set the tiling mode because: 1) the exporter
can set tiling AFTER exporting/importing. 2) a dmabuf could be
exported from a kernel driver other than i915, in this case the
dmabuf user and exporter need to set tiling separately.

This patch fixes a problem when running vkmark under weston with
iris on ICL, it crashed to console with the following assert. i965
doesn't have this problem as it always tries to set the specified
tiling mode.

weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-11-04 17:59:52 +00:00
Kenneth Graunke
fc7b748086 iris: Fix "Force Zero RTA Index Enable" setting again
In 2ca0d913ea, we began updating cso_fb->layers to the actual layer
count, rather than 0.  This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering.  Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.

Fixes: 2ca0d913ea ("iris: Fix framebuffer layer count")
2019-11-04 08:57:37 -08:00
Dylan Baker
717606f9f3 nir: correct use of identity check in python
Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.

Fixes: 96c4b135e3
       ("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-11-04 16:06:39 +00:00
Boris Brezillon
28440820ef panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASK
MALI_DEPTH_TEST should only be set when depth->writemask is true,
not when the depth test is enabled. Let's rename the flag and patch
panfrost_bind_depth_stencil_state() to do the right thing.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-04 16:14:09 +01:00
Lionel Landwerlin
71634b1003 vulkan: bump headers/registry to 1.1.127
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-04 17:07:11 +02:00
Samuel Pitoiset
9ab27647ff radv: fix compute pipeline keys when optimizations are disabled
If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.

Fixes: ce188813bf ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-11-04 08:50:00 +01:00
Karol Herbst
538d2c33b8 nv50/ir: fix crash in isUniform for undefined values
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-11-03 01:02:52 +01:00
Lionel Landwerlin
88d665830f mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-02 09:14:26 +00:00
Vasily Khoruzhick
103378f332 lima: set dithering flag when necessary
Bit 13 in aux1 enables dithering

Reviewed-by: Qiang.Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-01 21:44:31 -07:00
Marek Olšák
c236e6c1e3 glsl: encode struct/interface types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 19:19:03 -04:00
Marek Olšák
5dde2aa8d9 glsl: encode array types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 19:19:03 -04:00
Marek Olšák
c141366560 glsl: encode explicit_stride for basic types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 19:19:03 -04:00
Marek Olšák
86adce4fef glsl: encode vector_elements and matrix_columns better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 19:19:03 -04:00
Marek Olšák
21d2fbb8c3 glsl: encode/decode types using a union with bitfields for readability
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 19:19:03 -04:00
Vasily Khoruzhick
dd52744201 lima: ignore flags while looking for BO in cache
Any BO would work, we don't have any BO types yet anyway. Moreover
lima_submit_add_bo() changes BO flags so they won't match allocation
flags.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-01 13:12:07 -07:00
Vasily Khoruzhick
ae0b05d8db lima: align size before trying to fetch BO from cache
Otherwise we may be looking in wrong bucket

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-01 13:12:03 -07:00
Vasily Khoruzhick
08d6416a1d lima: add debug prints for BO cache
LIMA_DEBUG=bocache now activates debug prints for BO allocation,
destruction and BO cache.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-11-01 13:11:47 -07:00
Alyssa Rosenzweig
b32caa6f1f pan/midgard: Use fp32 blend shaders
Clearly we do want to have fp16 at some point ... but I kind of give up
debugging and it turns out the issues with fp16 support in 'frost are so
deeply rooted that I might as well disable this non-opt and land
LCRA now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-01 13:47:52 -04:00
Bas Nieuwenhuizen
8efb8f55a6 radv: Close all unnecessary fds in secure compile.
The seccomp filter allows read/write, let us make sure nobody can
do anything with this.

Fixes: cff53da374 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-01 17:15:34 +01:00
Erik Faye-Lund
dd77bdb34b anv: remove incorrect polygonMode=point early-out
This is incorrect, because polygonMode only applies if the final
primitive type is a polygon; polygonMode doesn't apply to
line-primitives as the comment suggests.

The Vulkan 1.1 spec, section 26.11, "Polygons" defines that polygons are
separate from points and line segments:

" A polygon results from the decomposition of a triangle strip, triangle
  fan or a series of independent triangles. Like points and line segments,
  polygon rasterization is controlled by several variables in the
  VkPipelineRasterizationStateCreateInfo structure. "

Further, section 26.11.2, "Polygon Mode", only define polygonMode to
apply to polygons:

" Possible values of the VkPipelineRasterizationStateCreateInfo::polygonMode
  property of the currently active pipeline, specifying the method of
  rasterization for polygons, are: "

This seems to clearly define that polygonMode doesn't apply to points
and lines, so let's make sure that we don't early out with the wrong
value.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-11-01 07:26:03 +00:00
Alyssa Rosenzweig
c3a46e7644 pan/midgard: Eliminate blank_alu_src
We don't need it in practice, so this is some more cleanup.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-01 01:01:47 +00:00
Alyssa Rosenzweig
70072a20e0 pan/midgard: Refactor swizzles
Rather than having hw-specific swizzles encoded directly in the
instructions, have a unified swizzle arary so we can manipulate swizzles
generically.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-01 01:01:47 +00:00
Alyssa Rosenzweig
e7fd14ca8a pan/midgard: Add a dummy source for loads
We want symmetry between loads and stores, so we add a dummy source. So
we get, e.g.

   st_int4 _,    val, arg_1, arg_2
   ld_int4 dest,   _, arg_1, arg_2

Semantically, this dummy source represents the data itself, as if the
load is simply a move. That means it has a swizzle that acts as a
source.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-01 01:01:47 +00:00
Alyssa Rosenzweig
b5938be51d pan/midgard: Remove OP_IS_STORE_VARY
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-11-01 01:01:46 +00:00
Timothy Arceri
1c2bf82d24 glsl: disable lower_fragdata_array() for NIR drivers
This function was added in 7e414b5864 to work around a defect in
lower_output_reads(). As of the previous commit no NIR driver calls
lower_output_reads().

This change means we don't need the special GLSL IR style
gl_FragData handling for building the resource list in a NIR based
linker.

No shader-db change on SKL i965.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-01 11:33:54 +11:00
Timothy Arceri
0e186c18ba glsl: just use NIR to lower outputs when driver can't read outputs
This will allow us to stop lowering gl_FragData in GLSL IR for NIR
drivers which means we won't need the special GLSL IR type
handling for building the resource list in a NIR based linker.

i965 has been doing this since b828f7a27b.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-11-01 11:33:33 +11:00
Icenowy Zheng
8fa13db251 lima: support indexed draw with bias
When doing an indexed draw with index_bias set to a non-zero value (e.g.
by glDrawElementsBaseVertex), the vertex buffer should be offseted by
index_bias vertices.

Add this offset when setting the vertex buffer address.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-10-31 21:56:45 +00:00
Jason Ekstrand
f60ef0fff4 anv: Move the RT BTI flush workaround to begin_subpass
Now that we're no longer compacting binding table entries, the only time
they can possibly change is when we actually switch subpasses.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-10-31 21:07:15 +00:00
Jason Ekstrand
6a8f43030c anv: Stop compacting render targets in the binding table
Instead, always emit one entry for every color attachment in the subpass
or one NULL if there are no color attachments.  This will let us adjust
an Ice Lake workaround so we don't get a stall on every draw call.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-10-31 21:07:15 +00:00
Jason Ekstrand
c765e2156a anv: Don't claim the null RT as a valid color target
If it's NULL, we can let the compiler go ahead and delete it or flag it
as NULL.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-10-31 21:07:15 +00:00
Jason Ekstrand
df7a730b4f anv: Don't delete fragment shaders that write sample mask
Also, use color_outputs_valid rather than nr_color_outputs since it
should be a bit more accurate.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-10-31 21:07:15 +00:00
Yevhenii Kolesnikov
265e4d9432 glsl: Enable textureSize for samplerExternalOES
From OES_EGL_image_external_essl3

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-10-31 20:23:56 +00:00
Eric Anholt
c9df92bf79 ci: Switch over to an autoscaling GKE cluster for builds.
The GKE pool we're using is 1-3 32-core VMs, preemptible (to keep
costs down), with 8 jobs concurrent per system.  We have plenty of
memory (4G/core), so we run make -j8 to try to keep the cores busy even
when one job is in a single-threaded step (docker image download, git
clone, artifacts processing, etc.)  When all jobs are generating work
for all the cores, they'll be scheduled fairly.

The nodes in the pool have 300GB boot disks (over-provisioned in space
to provide enough iops and throughput) mounted to /ccache, and
CACHE_DIR set pointing to them.  This means that once a new
autoscaled-up node has run some jobs, it should have a hot ccache from
then on (instead of having to rely on the docker container cache
having our ccache laying around and not getting wiped out by some
other fd.o job).  Local SSDs would provide higher performance, but
unfortunately are not supported with the cluster autoscaler.

For now, the softpipe/llvmpipe test runs are still on the shared
runners, until I can get them ported onto Bas's runner so they can be
parallelized in a single job.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-10-31 11:19:43 -07:00
Eric Anholt
da6cc72237 ci: Make lava inherit the ccache setup of the .build script.
It was just duplicating the code.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
2019-10-31 11:19:43 -07:00
Eric Engestrom
6e21dcc5a3 meson: revert glvnd workaround
This effectively reverts MR !2112.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 17:09:59 +00:00
Eric Engestrom
0f201e9dbc meson: require glvnd 1.2.0
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 17:09:59 +00:00
Eric Engestrom
9b58ab803d gitlab-ci: build a recent enough version of GLVND (ie. 1.2.0)
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 17:09:59 +00:00
Eric Engestrom
c32236811d meson: move idep_xmlconfig_headers to xmlpool/
That's where `xmlpool_options_h` is defined, and this way we can make sure
nobody starts making use of it in the future :)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 16:03:57 +00:00
Jason Ekstrand
02d9403067 anv: Use the new BO alloc API for Android
Fixes: a44f5ee0d8 "anv: Rework the internal BO allocation API"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 15:46:39 +00:00
Erik Faye-Lund
b7674829a1 zink: emit line-width when using polygon line-mode
When switching this to dynamic state, I forgot that this also needs to
be emitted when we use a polygon-mode set to lines.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 6d30abb4f1 ("zink: use dynamic state for line-width")
2019-10-31 15:38:21 +00:00
Eric Engestrom
fbb98ae0ed radeon: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
2c9898a329 r200: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
ea36ddae1e nouveau: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
4c5c31a651 i915: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
039797bef9 dri: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
5774abe725 targets/xvmc: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
ad8cd21def targets/xa: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
ec2555a3d6 targets/vdpau: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
8be89b4319 targets/va: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
375094c70b targets/omx: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
71ca5fb68a loader: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
0bd6fc0a84 pipe-loader: drop unnecessary xmlpool_options_h
idep_xmlconfig already covers that

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
a2eba4b17d radv: drop unnecessary xmlpool_options_h
idep_xmlconfig already covers that

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
791ece114e anv: add missing xmlconfig headers dependency
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Eric Engestrom
4072b3360b meson: split out idep_xmlconfig_headers from idep_xmlconfig
A bunch of components need the former but not the latter.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2019-10-31 15:29:06 +00:00
Alyssa Rosenzweig
bf15318991 pipe-loader: Build kmsro loader for with all kmsro targets
Build failure reported by i965 CI, triggered by building dynamic
pipeloaders with kmsro drivers (besides 'frost). At this point, there's
no reason to actually do that -- mesa CI didn't mind -- but let's not
break the build.

v2: Simplify script. Add extra dependencies for v3d.

Fixes: afb0d08cb0 ("pipe-loader: Default to kmsro if probe fails")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-10-31 15:26:10 +00:00
Erik Faye-Lund
5ea787950f zink: heap-allocate samplers objects
VkSampler is 64-bit even on 32-bit systems, so casting it to a pointer
is a bad idea there. So let's heap-allocate the sampler-object instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2017
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-10-31 13:57:43 +00:00
Jason Ekstrand
0ca0ad1252 anv: Zero released anv_bo structs
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
b3c0b1b218 anv: Use a bitset for tracking residency
Now that we can conveniently map between GEM handles and struct anv_bo
pointers, we can use a simple bitset for residency tracking instead of
the complex hash set.  This shaves about 3% off of a CPU-limited example
running with the Dawn WebGPU implementation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
9ef198c59a anv: Set the batch allocator for compute pipelines
Otherwise relocations just up and crash.

Fixes: a3153162a9 "anv: Delay allocation of relocation lists"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
9f665d9c1c anv: Add a device parameter to anv_execbuf_add_bo
We're about to start needing to lookup BO pointers by GEM handle so we
need access to the device.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
63d7a38630 anv: Drop anv_bo_init and anv_bo_init_new
BOs are now only ever allocated through the BO cache so there's no need
to have these exposed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
853d3b59fd anv: Allocate misc BOs from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
d0ec55d5a3 anv: Allocate scratch BOs from the cache
While we're here, we get rid of the locking and use a lock-free
algorithm.  The chances of spilling contention are low and this is
actually a bit simpler in some ways.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
ee77938733 anv: Allocate batch and fence buffers from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
e4f01eca3b util: Add a free list structure for use with util_sparse_array
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
0a6d2593b8 anv: Allocate descriptor buffers from the BO cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
e0ee23660f anv: Set more flags on descriptor pool buffers
the ASYNC flag, in particular, has the potential to help performance
because it means less sync tracking in the kernel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
c3eb4b3ba5 anv: Allocate query pool BOs from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
0d2787f7c9 anv: Use the query_slot helper in vkResetQueryPoolEXT
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
3119b96bdf anv: Allocate block pool BOs from the cache
This commit switches block pools over to being allocated from the BO
cache rather than being allocated manually by the block pool.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
cc972d72c7 anv/tests: Initialize the BO cache and device mutex
We're about to start depending on the BO cache in the state and block
pools so we need them properly initialized for the tests to work.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
9076e9f375 anv/tests: Zero-initialize instances
Some of the tests were actually relying on some of those uninitialized
bits to be non-zero.  In particular, a couple want use_softpin = true.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
5c664dff75 anv: Choose BO flags internally in anv_block_pool
All block pools are allocated with the same flags.  There's no good
reason why it needs to be configurable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
a44f5ee0d8 anv: Rework the internal BO allocation API
This makes a number of changes to the current API:

 1. Everything is renamed to anv_device_* instead of anv_bo_cache_*
    because the BO cache is soon going to be the sole BO allocation path
    and not some special case to make import/export work.

 2. Drop the cache parameter.  It's totally redundant with the device
    and just annoying to keep typing.

 3. Rework flags so that they go the convenient direction for usage in
    ANV rather than whichever awkward way the i915 specified it to
    maintain backwards compatibility.  This also gives us the
    opportunity to set some defaults.

 4. Add flags for mapping and coherency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:09 +00:00
Jason Ekstrand
1be2e4c0ef anv: Use anv_block_pool_foreach_bo in get_bo_from_pool
While we're at it, use gen_48b_address().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
3178e583c8 anv: Rework anv_block_pool_expand_range
The growing algorithms for the softpin case and the userptr version are
almost entirely different.  Having this weird join doesn't make the code
more comprehensible.  This rework does a few things:

 1. Move the comment about 48-bit addresses to anv_device_init where we
    actually unset the EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.

 2. Separate the paths in anv_block_pool_expand_range so it's easier to
    see what happens in the two different cases.

 3. Use the anv_block_poo::bos array for storing all allocated BOs in
    both paths rather than using the cleanup list in both paths.  This
    lets us make the cleanups array only used for mmaps of the memfd for
    the userptr case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
bb257e1852 anv: Fix a potential BO handle leak
Fixes: 731c4adcf9 "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
6f4fa81769 anv: Handle state pool relocations using "wrapper" BOs
Instead of depending on a mutable BO in the state pool for handling
growing state pools, add a concept of "wrapper" BOs which just wrap an
actual BO.  This way, the wrapper can exist once for all of time and we
can put it in relocation lists even if the actual BO it references gets
swapped out.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
b781c85c79 anv: Replace ANV_BO_EXTERNAL with anv_bo::is_external
We're not THAT strapped for space that we can't burn one extra bit for
a boolean.  If we're really worried about it, we can always shrink the
flags field to 16 bits because the kernel only uses 7 currently.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
5534358ef6 anv: Inline anv_block_pool_get_bo
It has exactly one caller and we're about to change some of the dynamics
which would make this confusing as a separate function.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
c0a4722f29 anv: Declare the bo in the anv_block_pool_foreach_bo loop
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
325345b2bd anv: Stop storing the GEM handle in anv_reloc_list_add
We have to go through and rewrite them all anyway so it doesn't do us
any good to put them in the list in anv_reloc_list_add.  Also, for state
pools the handles are likely wrong by the time vkQueueSubmit is called.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
c4be72934e anv: Fix a relocation race condition
Previously, we would read the offset from the BO in anv_reloc_list_add
to generate the presumed offset and then again in the caller to compute
the 64-bit address to write into the buffer.  However, if the offset
somehow changed between these two points, the presumed offset would no
longer match the written offset.  This is unlikely to actually ever be a
problem in practice because the presumed offset gets recorded first and
so if the written address is wrong then the presumed offset is almost
certainly wrong and the relocation will trigger.  However, it's much
safer to simply have anv_reloc_list_add return the 64-bit address.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
bbf389013f anv: Use a util_sparse_array for the GEM handle -> BO map
This lets us do less allocation because the anv_bo's are now embedded in
the sparse array and it also allows lock-free translation from GEM
handle to BO which will be useful in future commits.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
821ce7be36 anv: Move refcount to anv_bo
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Jason Ekstrand
09ec6917c1 util: Add a util_sparse_array data structure
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 13:46:08 +00:00
Pierre-Eric Pelloux-Prayer
8a723282e3 mesa: enable msaa in clear_with_quad if needed
If the DrawBuffer sample count is > 1 and msaa is enabled we must also
enable msaa when clearing it.

Fixes: ea5b7de138 ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1991

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
2019-10-31 12:30:53 +01:00
Lionel Landwerlin
b087b7bd90 intel/perf: fix Android build
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15b7b56eb2 ("intel/perf: add TGL support")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
2019-10-31 11:20:30 +00:00
Tomeu Vizoso
01af59b2d9 gitlab-ci: Disable lima jobs
The runner that submits jobs there is down and will turn some time to
get fixed. Disable them for now to keep the CI green.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-10-31 11:08:11 +00:00
Bas Nieuwenhuizen
6ced684e27 radv: Fix disk_cache_get size argument.
Got some int->pointer warnings and 20 is not a valid pointer ....

Fixes: 2e3a635ee6 "radv: Add an early exit in the secure compile if we already have the cache entries."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-10-31 11:40:43 +01:00
Andrii Simiklit
e06fcbe2c8 main: fix several 'may be used uninitialized' warnings
This patch fixes approximately 39 warnings in 'texcompress_etc.c'
for the release configuration

v2: Fixed by adding the unreachable case to the etc2_rgb8_fetch_texel
       ( Eric Engestrom <eric.engestrom@intel.com> )

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
2019-10-31 10:14:09 +00:00
Bas Nieuwenhuizen
3e86d553a4 anv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.

CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-10-31 09:47:56 +00:00
Bas Nieuwenhuizen
72f858fc07 turnip: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.

CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-10-31 09:47:56 +00:00
Bas Nieuwenhuizen
344ba56b0f radv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.

CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-10-31 09:47:56 +00:00
Pierre-Eric Pelloux-Prayer
2afeed3010 radeonsi: tell the shader disk cache what IR is used
Until 8bef4df196 the IR (TGSI or NIR) was used in disk_cache driver_flags.
This commit restores this features to avoid crashing when switching from
one IR to the other.

As radeonsi's default is TGSI, I used "driver_flags & 0x8000000 = 0" for TGSI
to keep the same driver_flags.

Fixes: 8bef4df196 ("radeonsi: add si_debug_options for convenient adding/removing of options")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-10-31 10:43:40 +01:00
Lionel Landwerlin
15b7b56eb2 intel/perf: add TGL support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-31 09:13:20 +00:00
Robert Foss
f140467b5b android: Add panfrost support to build scripts
Currently the Android build system doesn't expose the panfrost
driver.

This patch enables the panfrost driver to be build on for the
Android platform.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-By: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-31 10:03:54 +01:00
Robert Foss
6f3f855320 nir: Build nir_lower_point_size.c in libmesa_nir
nir_lower_point_size.c was not build into the libmesa_nir library for non-meson
builds. However it was included in the meson build.

This patch fixes that.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-31 10:03:54 +01:00
Iago Toral Quiroga
e7e501efce v3d: rename vertex shader key (num)_fs_inputs fields
Until now this made sense because we always paired vertex shaders
with fragment shaders, but as soon as we implement geometry and
tessellation shaders that will no longer be the case, so rename
this to (num_)used_outputs.

v2: Use 'used_outputs' instead of ns_outputs, which is more explicit (Eric).

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-31 08:46:35 +00:00
Mauro Rossi
d688e4166c android: aco: fix Lower to CSSA
Fixes the following building error:

external/mesa/src/amd/compiler/aco_spill.cpp:1768:
error: undefined reference to 'aco::lower_to_cssa(aco::Program*, aco::live&, radv_nir_compiler_options const*)'

Fixes: 0b8216b ("aco: Lower to CSSA")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2019-10-31 07:38:46 +00:00
Jan Zielinski
7baedc9162 gallium/swr: Fix depth values for blit scenario
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-10-31 07:25:54 +00:00
Jordan Justen
bb0c5c487e iris/gen11+: Move flush for render target change
When starting a BLORP operation, we do the BTI-change flush.  However,
when ending it and transitioning back to regular drawing, we change the
render target again - without a set_framebuffer_state() call.  We need
to do the BTI flush there too.  BLORP flags IRIS_DIRTY_RENDER_BUFFER
now, which will cause the next draw to get the BTI flush again.

(explanation of fix by Ken)

Fixes: 2b956a093a ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-31 00:24:25 -07:00
Jordan Justen
a2c3c65a31 iris: Add IRIS_DIRTY_RENDER_BUFFER state flag
Fixes: 2b956a093a ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-31 00:24:25 -07:00
Samuel Pitoiset
1e36a8f41d radv: declare NGG scratch for VS or TES and only on GFX10
Do not need to declare it for other stages because this is for
streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-31 06:51:01 +00:00
Arno Messiaen
a9391a1a01 lima: add cubemap support
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-10-31 06:29:31 +00:00
Arno Messiaen
9890590fba lima: introduce ppir_op_load_coords_reg to differentiate between loading texture coordinates straight from a varying vs loading them from a register
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-10-31 06:29:31 +00:00
Arno Messiaen
28e1d55d6e lima: add layer_stride field to lima_resource struct
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-10-31 06:29:31 +00:00
Arno Messiaen
f3686083a4 lima: fix stride in texture descriptor
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
2019-10-31 06:29:31 +00:00
Ian Romanick
7b3f38ef69 intel/compiler: Report the number of non-spill/fill SEND messages on vec4 too
This make shader-db's report.py work on Haswell and earlier platforms.
The problem is that the script would detect the "sends" output for
scalar shaders and expect in in vec4 shaders too.  When it didn't find
it, the script would fail with:

    Traceback (most recent call last):
      File "./report.py", line 351, in <module>
        main()
      File "./report.py", line 182, in main
        before_count = before[p][m]
    KeyError: 'sends'

Fixes: f192741ddd ("intel/compiler: Report the number of non-spill/fill SEND messages")

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-30 21:27:03 -07:00
Tapani Pälli
b380d47998 nir: fix couple of compile warnings
Fixes "warning: braces around scalar initializer" warnings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-31 00:21:44 +00:00
Bas Nieuwenhuizen
ec770085c2 radv: Fix timeout handling in syncobj wait.
libdrm returns -errno instead of directly the ioctl ret of -1.

Fixes: 1c3cda7d27 "radv: Add syncobj signal/reset/wait to winsys."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-10-31 00:48:17 +01:00
Ilia Mirkin
1b9d1e13d8 nv50/ir: mark STORE destination inputs as used
Observed an issue when looking at the code generatedy by the
image-vertex-attrib-input-output piglit test. Even though the test
itself worked fine (due to TIC 0 being used for the image), this needs
to be fixed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2019-10-30 19:13:18 -04:00
Ilia Mirkin
869e32593a gm107/ir: fix loading z offset for layered 3d image bindings
Unfortuantely we don't know if a particular load is a real 2d image (as
would be a cube face or 2d array element), or a layer of a 3d image.
Since we pass in the TIC reference, the instruction's type has to match
what's in the TIC (experimentally). In order to properly support
bindless images, this also can't be done by looking at the current
bindings and generating appropriate code.

As a result all plain 2d loads are converted into a pair of 2d/3d loads,
with appropriate predicates to ensure only one of those actually
executes, and the values are all merged in.

This goes somewhat against the current flow, so for GM107 we do the OOB
handling directly in the surface processing logic. Perhaps the other
gens should do something similar, but that is left to another change.

This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS
tests like shader_image_load_store.non-layered_binding without breaking
anything else.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "20.0" <mesa-stable@lists.freedesktop.org>
2019-10-30 19:12:36 -04:00
Lionel Landwerlin
e02c181bfd intel/dev: set default num_eu_per_subslice on gen12
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 8125d7960b ("intel/dev: Add preliminary device info for Tigerlake")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-30 22:30:09 +00:00
Dylan Baker
4226952199 docs/new_features: Empty the feature list for the 20.0 cycle 2019-10-30 15:18:27 -07:00
Dylan Baker
1fdcc2494e Bump VERSION to 20.0.0-devel 2019-10-30 14:56:02 -07:00
2917 changed files with 338945 additions and 162970 deletions

View File

@@ -16,7 +16,7 @@ if "%buildsystem%" == "scons" (
call scons --version
) else (
python --version
python -m pip install Mako==1.0.7 meson
python -m pip install Mako meson
meson --version
rem Install pkg-config, which meson requires even on windows

View File

@@ -32,6 +32,10 @@ indent_size = 2
indent_style = space
indent_size = 2
[*.html]
indent_style = space
indent_size = 2
[*.patch]
trim_trailing_whitespace = false

File diff suppressed because it is too large Load Diff

View File

@@ -1,14 +1,104 @@
## Mesa testing using gitlab-runner
# Mesa testing
The goal of the "test" stage of the .gitlab-ci.yml is to do pre-merge
testing of Mesa drivers on various platforms, so that we can ensure no
regressions are merged, as long as developers are merging code using
the "Merge when pipeline completes" button.
marge-bot.
This document only covers the CI from .gitlab-ci.yml and this
directory. For other CI systems, see Intel's [Mesa
CI](https://gitlab.freedesktop.org/Mesa_CI) or panfrost's LAVA-based
CI (`src/gallium/drivers/panfrost/ci/`)
There are currently 4 automated testing systems deployed for Mesa.
LAVA and gitlab-runner on the DUTs are used in pre-merge testing and
are described in this document. Managing bare metal using
gitlab-runner is described under [bare-metal/README.md]. Intel also
has a jenkins-based CI system with restricted access that isn't
connected to gitlab.
## Mesa testing using LAVA
[LAVA](https://lavasoftware.org/) is a system for functional testing
of boards including deploying custom bootloaders and kernels. This is
particularly relevant to testing Mesa because we often need to change
kernels for UAPI changes (and this lets us do full testing of a new
kernel during development), and our workloads can easily take down
boards when mistakes are made (kernel oopses, OOMs that take out
critical system services).
### Mesa-LAVA software architecture
The gitlab-runner will run on some host that has access to the LAVA
lab, with tags like "lava-mesa-boardname" to control only taking in
jobs for the hardware that the LAVA lab contains. The gitlab-runner
spawns a docker container with lava-cli in it, and connects to the
LAVA lab using a predefined token to submit jobs under a specific
device type.
The LAVA instance manages scheduling those jobs to the boards present.
For a job, it will deploy the kernel, device tree, and the ramdisk
containing the CTS.
### Deploying a new Mesa-LAVA lab
You'll want to start with setting up your LAVA instance and getting
some boards booting using test jobs. Start with the stock QEMU
examples to make sure your instance works at all. Then, you'll need
to define your actual boards.
The device type in lava-gitlab-ci.yml is the device type you create in
your LAVA instance, which doesn't have to match the board's name in
`/etc/lava-dispatcher/device-types`. You create your boards under
that device type and the Mesa jobs will be scheduled to any of them.
Instantiate your boards by creating them in the UI or at the command
line attached to that device type, then populate their dictionary
(using an "extends" line probably referencing the board's template in
`/etc/lava-dispatcher/device-types`). Now, go find a relevant
healthcheck job for your board as a test job definition, or cobble
something together from a board that boots using the same boot_method
and some public images, and figure out how to get your boards booting.
Once you can boot your board using a custom job definition, it's time
to connect Mesa CI to it. Install gitlab-runner and register as a
shared runner (you'll need a gitlab admin for help with this). The
runner *must* have a tag (like "mesa-lava-db410c") to restrict the
jobs it takes or it will grab random jobs from tasks across fd.o, and
your runner isn't ready for that.
The runner will be running an ARM docker image (we haven't done any
x86 LAVA yet, so that isn't documented). If your host for the
gitlab-runner is x86, then you'll need to install qemu-user-static and
the binfmt support.
The docker image will need access to the lava instance. If it's on a
public network it should be fine. If you're running the LAVA instance
on localhost, you'll need to set `network_mode="host"` in
`/etc/gitlab-runner/config.toml` so it can access localhost. Create a
gitlab-runner user in your LAVA instance, log in under that user on
the web interface, and create an API token. Copy that into a
`lavacli.yaml`:
```
default:
token: <token contents>
uri: <url to the instance>
username: gitlab-runner
```
Add a volume mount of that `lavacli.yaml` to
`/etc/gitlab-runner/config.toml` so that the docker container can
access it. You probably have a `volumes = ["/cache"]` already, so now it would be
```
volumes = ["/home/anholt/lava-config/lavacli.yaml:/root/.config/lavacli.yaml", "/cache"]
```
Note that this token is visible to anybody that can submit MRs to
Mesa! It is not an actual secret. We could just bake it into the
gitlab CI yml, but this way the current method of connecting to the
LAVA instance is separated from the Mesa branches (particularly
relevant as we have many stable branches all using CI).
Now it's time to define your test runner in
`.gitlab-ci/lava-gitlab-ci.yml`.
## Mesa testing using gitlab-runner on DUTs
### Software architecture

View File

@@ -44,3 +44,4 @@ CONFIG_DEBUG_LOCKDEP=n
CONFIG_SOFTLOCKUP_DETECTOR=n
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=n
CONFIG_FW_LOADER_COMPRESS=y

View File

@@ -12,6 +12,9 @@ CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_PANFROST=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_MSM=y
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7533=y
CONFIG_PWM_CROS_EC=y
CONFIG_BACKLIGHT_PWM=y
@@ -26,7 +29,9 @@ CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_ARCH_SUNXI=n
# db410c ethernet
CONFIG_USB_RTL8152=y
CONFIG_ARCH_ALPINE=n
CONFIG_ARCH_BCM2835=n
CONFIG_ARCH_BCM_IPROC=n
@@ -39,7 +44,6 @@ CONFIG_ARCH_LG1K=n
CONFIG_ARCH_HISI=n
CONFIG_ARCH_MEDIATEK=n
CONFIG_ARCH_MVEBU=n
CONFIG_ARCH_QCOM=n
CONFIG_ARCH_SEATTLE=n
CONFIG_ARCH_SYNQUACER=n
CONFIG_ARCH_RENESAS=n
@@ -63,7 +67,13 @@ CONFIG_ARCH_XGENE=n
CONFIG_ARCH_ZX=n
CONFIG_ARCH_ZYNQMP=n
CONFIG_ACPI=n
# Strip out some stuff we don't need for graphics testing, to reduce
# the build.
CONFIG_CAN=n
CONFIG_SPI=n
CONFIG_WIRELESS=n
CONFIG_RFKILL=n
CONFIG_WLAN=n
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR=y
@@ -82,3 +92,5 @@ CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_FW_LOADER_COMPRESS=y

View File

@@ -0,0 +1,2 @@
[*.sh]
indent_size = 2

View File

@@ -0,0 +1,80 @@
# bare-metal Mesa testing
Testing Mesa with gitlab-runner running on the devices being tested
(DUTs) proved to be too unstable, so this set of scripts is for
running Mesa testing on bare-metal boards connected to a separate
system using gitlab-runner. Currently only "fastboot" devices are
supported.
In comparison with LAVA, this doesn't involve maintaining a separate
webservice with its own job scheduler and replicating jobs between the
two. It also places more of the board support in git, instead of
webservice configuration. Most importantly, it doesn't download the
rootfs as artifacts on each job, so we can avoid traffic to
freedesktop.org. On the other hand, the serial interactions and
bootloader support are more primitive.
## Requirements
This testing requires power control of the DUTs by the gitlab-runner
machine, since this is what we use to reset the system and get back to
a pristine state at the start of testing.
We require access to the console output from the gitlb-runner system,
since that is how we get the final results back from te tests. You
should probably have the console on a serial connection, so that you
can see bootloader progress.
The boards need to be able to have a kernel/initramfs supplied by the
gitlab-runner system, since the initramfs is what contains the Mesa
testing payload. Currently only "fastboot" devices are supported.
The boards should have networking, so that (in a future iteration of
this code) we can extract the dEQP .xml results to artifacts on
gitlab.
## Setup
Each board will be registered in fd.o gitlab. You'll want something
like this to register:
```
sudo gitlab-runner register \
--url https://gitlab.freedesktop.org \
--registration-token $1 \
--name MY_BOARD_NAME \
--tag-list MY_BOARD_TAG \
--executor docker \
--docker-image "alpine:latest" \
--docker-volumes "/dev:/dev" \
--docker-network-mode "host" \
--docker-privileged \
--non-interactive
```
The registration token has to come from a fd.o gitlab admin going to
https://gitlab.freedesktop.org/admin/runners
The name scheme for Google's lab is google-freedreno-boardname-nn, and
our tag is google-freedreno-db410c. The tag is what identifies a
board type so that board-specific jobs can be dispatched into that
pool.
We need privileged mode and the /dev bind mount in order to get at the
serial console and fastboot USB devices (--device arguments don't
apply to devices that show up after container start, which is the case
with fastboot). We use host network mode so that we can (in the
future) spin up a server to collect XML results.
Once you've added your boards, you're going to need to specify the
board-specific env vars, adding something like this `environment` line
to each runner in `/etc/gitlab-runner/config.toml`
```
[[runners]]
name = "google-freedreno-db410c-01"
environment = ["BM_SERIAL=/dev/ttyDB410c8", "BM_POWERUP=google-power-up.sh 8", "BM_FASTBOOT_SERIAL=15e9e390"]
```
Once you've updated your runners' configs, restart with `sudo service
gitlab-runner restart`

View File

@@ -0,0 +1,9 @@
#!/bin/bash
set -e
echo "Waiting for $1 to say '$2'"
while ! grep -q "$2" $1; do
sleep 2
done

108
.gitlab-ci/bare-metal/fastboot.sh Executable file
View File

@@ -0,0 +1,108 @@
#!/bin/bash
BM=$CI_PROJECT_DIR/.gitlab-ci/bare-metal
if [ -z "$BM_SERIAL" ]; then
echo "Must set BM_SERIAL in your gitlab-runner config.toml [[runners]] environment"
echo "This is the serial device to talk to for waiting for fastboot to be ready and logging from the kernel."
exit 1
fi
if [ -z "$BM_POWERUP" ]; then
echo "Must set BM_POWERUP in your gitlab-runner config.toml [[runners]] environment"
echo "This is a shell script that should reset the device and begin its boot sequence"
echo "such that it pauses at fastboot."
exit 1
fi
if [ -z "$BM_POWERDOWN" ]; then
echo "Must set BM_POWERDOWN in your gitlab-runner config.toml [[runners]] environment"
echo "This is a shell script that should power off the device."
exit 1
fi
if [ -z "$BM_FASTBOOT_SERIAL" ]; then
echo "Must set BM_FASTBOOT_SERIAL in your gitlab-runner config.toml [[runners]] environment"
echo "This must be the a stable-across-resets fastboot serial number."
exit 1
fi
if [ -z "$BM_KERNEL" ]; then
echo "Must set BM_KERNEL to your board's kernel vmlinuz or Image.gz in the job's variables:"
exit 1
fi
if [ -z "$BM_DTB" ]; then
echo "Must set BM_DTB to your board's DTB file in the job's variables:"
exit 1
fi
if [ -z "$BM_ROOTFS" ]; then
echo "Must set BM_ROOTFS to your board's rootfs directory in the job's variables:"
exit 1
fi
set -ex
# Copy the rootfs to a temporary for our setup, as I believe changes to the
# container can end up impacting future runs.
cp -Rp $BM_ROOTFS rootfs
# Set up the init script that brings up the system.
cp $BM/init.sh rootfs/init
sed -i "s|DEQP_VER_REPLACE|$DEQP_VER|g" rootfs/init
sed -i "s|DEQP_PARALLEL_REPLACE|$DEQP_PARALLEL|g" rootfs/init
sed -i "s|DEQP_EXPECTED_RENDERER_REPLACE|$DEQP_EXPECTED_RENDERER|g" rootfs/init
sed -i "s|CI_NODE_INDEX_REPLACE|$CI_NODE_INDEX|g" rootfs/init
sed -i "s|CI_NODE_TOTAL_REPLACE|$CI_NODE_TOTAL|g" rootfs/init
# Add the Mesa drivers we built, and make a consistent symlink to them.
mkdir -p rootfs/$CI_PROJECT_DIR
tar -C rootfs/$CI_PROJECT_DIR/ -xf $CI_PROJECT_DIR/artifacts/install.tar
ln -sf $CI_PROJECT_DIR/install rootfs/install
# Copy the deqp runner script and metadata.
cp .gitlab-ci/deqp-runner.sh rootfs/deqp/.
cp .gitlab-ci/$DEQP_SKIPS rootfs/$CI_PROJECT_DIR/install/deqp-skips.txt
if [ -n "$DEQP_EXPECTED_FAILS" ]; then
cp .gitlab-ci/$DEQP_EXPECTED_FAILS rootfs/$CI_PROJECT_DIR/install/deqp-expected-fails.txt
fi
# Finally, pack it up into a cpio rootfs.
pushd rootfs
find -H | cpio -H newc -o | xz --check=crc32 -T4 - > $CI_PROJECT_DIR/rootfs.cpio.gz
popd
cat $BM_KERNEL $BM_DTB > Image.gz-dtb
abootimg \
--create artifacts/fastboot.img \
-k Image.gz-dtb \
-r rootfs.cpio.gz \
-c cmdline="$BM_CMDLINE"
rm Image.gz-dtb
# Start watching serial, and power up the device.
$BM/serial-buffer.py $BM_SERIAL | tee artifacts/serial-output.txt &
while [ ! -e artifacts/serial-output.txt ]; do
sleep 1
done
PATH=$BM:$PATH $BM_POWERUP
# Once fastboot is ready, boot our image.
$BM/expect-output.sh artifacts/serial-output.txt "fastboot: processing commands"
fastboot boot -s $BM_FASTBOOT_SERIAL artifacts/fastboot.img
# Wait for the device to complete the deqp run
$BM/expect-output.sh artifacts/serial-output.txt "DEQP RESULT"
# power down the device
PATH=$BM:$PATH $BM_POWERDOWN
set +e
if grep -q "DEQP RESULT: pass" artifacts/serial-output.txt; then
exit 0
else
exit 1
fi

View File

@@ -0,0 +1,10 @@
#!/bin/bash
relay=$1
if [ -z "$relay" ]; then
echo "Must supply a relay arg"
exit 1
fi
$CI_PROJECT_DIR/.gitlab-ci/bare-metal/google-power-relay.py off $relay

View File

@@ -0,0 +1,19 @@
#!/usr/bin/python3
import sys
import serial
mode = sys.argv[1]
relay = sys.argv[2]
# our relays are "off" means "board is powered".
mode_swap = {
"on" : "off",
"off" : "on",
}
mode = mode_swap[mode]
ser = serial.Serial('/dev/ttyACM0', 115200, timeout=2)
command = "relay {} {}\n\r".format(mode, relay)
ser.write(command.encode())
ser.close()

View File

@@ -0,0 +1,12 @@
#!/bin/bash
relay=$1
if [ -z "$relay" ]; then
echo "Must supply a relay arg"
exit 1
fi
$CI_PROJECT_DIR/.gitlab-ci/bare-metal/google-power-relay.py off $relay
sleep 5
$CI_PROJECT_DIR/.gitlab-ci/bare-metal/google-power-relay.py on $relay

View File

@@ -0,0 +1,30 @@
#!/bin/sh
set -ex
mount -t proc none /proc
mount -t sysfs none /sys
mount -t devtmpfs none /dev || echo possibly already mounted
mkdir -p /dev/pts
mount -t devpts devpts /dev/pts
export DEQP_NO_SAVE_RESULTS=1
export DEQP_VER=DEQP_VER_REPLACE
export DEQP_PARALLEL=DEQP_PARALLEL_REPLACE
export DEQP_EXPECTED_RENDERER=DEQP_EXPECTED_RENDERER_REPLACE
export CI_NODE_INDEX=CI_NODE_INDEX_REPLACE
export CI_NODE_TOTAL=CI_NODE_TOTAL_REPLACE
export DEQP_SKIPS=deqp-skips.txt
if [ -e /install/deqp-expected-fails.txt ]; then
export DEQP_EXPECTED_FAILS=deqp-expected-fails.txt
fi
if sh /deqp/deqp-runner.sh; then
echo "DEQP RESULT: pass"
else
echo "DEQP RESULT: fail"
fi
# Wait until the job would have timed out anyway, so we don't spew a "init
# exited" panic.
sleep 6000

View File

@@ -0,0 +1,46 @@
#!/usr/bin/python3
# Copyright © 2020 Google LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
# IN THE SOFTWARE.
# Tiny script to read bytes from serial, and write the output to stdout, with a
# buffer in between so we don't lose serial output from its buffer.
#
# We don't use 'cu' because it requires stdin to be hooked up and I never
# managed to make that work without getting blocked somewhere. We don't use
# 'conserver' because it's non-free.
import sys
import serial
import select
import os
import posix
dev=sys.argv[1]
ser = serial.Serial(dev, 115200, timeout=10)
while True:
bytes = ser.read()
sys.stdout.buffer.write(bytes)
sys.stdout.flush()
ser.close()

View File

@@ -0,0 +1,30 @@
#!/bin/bash
set -ex
# Need an unreleased version of Waffle for surfaceless support in apitrace
# Replace this build with the Debian package once that's possible
WAFFLE_VERSION="e3c995d9a2693b687501715b6550619922346089"
git clone https://gitlab.freedesktop.org/mesa/waffle.git --single-branch --no-checkout /waffle
pushd /waffle
git checkout "$WAFFLE_VERSION"
cmake -B_build -DCMAKE_INSTALL_LIBDIR=lib -DCMAKE_BUILD_TYPE=Release .
make -C _build -j4 install
popd
rm -rf /waffle
APITRACE_VERSION="9.0"
git clone https://github.com/apitrace/apitrace.git --single-branch --no-checkout /apitrace
pushd /apitrace
git checkout "$APITRACE_VERSION"
cmake -G Ninja -B_build -H. -DCMAKE_BUILD_TYPE=Release -DENABLE_GUI=False -DENABLE_WAFFLE=on -DWaffle_DIR=/usr/local/lib/cmake/Waffle/
ninja -C _build
mkdir build
cp _build/apitrace build
cp _build/glretrace build
cp _build/eglretrace build
strip build/*
find . -not -path './build' -not -path './build/*' -delete
popd

View File

@@ -0,0 +1,10 @@
#!/bin/bash
set -ex
git clone https://gitlab.freedesktop.org/mesa/parallel-deqp-runner.git --depth 1 -b mesa-ci-2019-12-17 /parallel-deqp-runner
pushd /parallel-deqp-runner
meson build/ $EXTRA_MESON_ARGS
ninja -C build install
popd
rm -rf /parallel-deqp-runner

View File

@@ -0,0 +1,60 @@
#!/bin/bash
git config --global user.email "mesa@example.com"
git config --global user.name "Mesa CI"
git clone \
--depth 1 \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b opengl-es-cts-3.2.6.1 \
/VK-GL-CTS
pushd /VK-GL-CTS
# surfaceless links against libkms and such despite not using it.
sed -i '/gbm/d' targets/surfaceless/surfaceless.cmake
sed -i '/libkms/d' targets/surfaceless/surfaceless.cmake
sed -i '/libgbm/d' targets/surfaceless/surfaceless.cmake
# --insecure is due to SSL cert failures hitting sourceforge for zlib and
# libpng (sigh). The archives get their checksums checked anyway, and git
# always goes through ssh or https.
python3 external/fetch_sources.py --insecure
mkdir -p /deqp
# Save the testlog stylesheets:
cp doc/testlog-stylesheet/testlog.{css,xsl} /deqp
popd
pushd /deqp
cmake -G Ninja \
-DDEQP_TARGET=surfaceless \
-DCMAKE_BUILD_TYPE=Release \
$EXTRA_CMAKE_ARGS \
/VK-GL-CTS
ninja
# Copy out the mustpass lists we want from a bunch of other junk.
mkdir /deqp/mustpass
for gles in gles2 gles3 gles31; do
cp \
/deqp/external/openglcts/modules/gl_cts/data/mustpass/gles/aosp_mustpass/3.2.6.x/$gles-master.txt \
/deqp/mustpass/$gles-master.txt
done
# Save *some* executor utils, but otherwise strip things down
# to reduct deqp build size:
mkdir /deqp/executor.save
cp /deqp/executor/testlog-to-* /deqp/executor.save
rm -rf /deqp/executor
mv /deqp/executor.save /deqp/executor
rm -rf /deqp/external
rm -rf /deqp/modules/internal
rm -rf /deqp/execserver
rm -rf /deqp/modules/egl
rm -rf /deqp/framework
find -iname '*cmake*' -o -name '*ninja*' -o -name '*.o' -o -name '*.a' | xargs rm -rf
${STRIP_CMD:-strip} modules/*/deqp-*
du -sh *
rm -rf /VK-GL-CTS
popd

View File

@@ -0,0 +1,42 @@
#!/bin/bash
set -ex
git clone \
--depth 1 \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b vulkan-cts-1.2.1.0 \
/VK-GL-CTS
pushd /VK-GL-CTS
# --insecure is due to SSL cert failures hitting sourceforge for zlib and
# libpng (sigh). The archives get their checksums checked anyway, and git
# always goes through ssh or https.
python3 external/fetch_sources.py --insecure
mkdir -p /deqp
popd
pushd /deqp
cmake -G Ninja \
-DDEQP_TARGET=x11_glx \
-DCMAKE_BUILD_TYPE=Release \
/VK-GL-CTS
ninja
# Copy out the mustpass list we want.
mkdir /deqp/mustpass
cp /VK-GL-CTS/external/vulkancts/mustpass/master/vk-default.txt \
/deqp/mustpass/vk-master.txt
rm -rf /deqp/modules/internal
rm -rf /deqp/executor
rm -rf /deqp/execserver
rm -rf /deqp/modules/egl
rm -rf /deqp/framework
find -iname '*cmake*' -o -name '*ninja*' -o -name '*.o' -o -name '*.a' | xargs rm -rf
strip external/vulkancts/modules/vulkan/deqp-vk
du -sh *
rm -rf /VK-GL-CTS
popd

View File

@@ -0,0 +1,14 @@
#!/bin/bash
set -ex
git clone https://github.com/ValveSoftware/Fossilize.git
cd Fossilize
git checkout 6b5b570008c9ab5269e341f04c811fe49a1bb72c
git submodule update --init
mkdir build
cd build
cmake .. -DCMAKE_BUILD_TYPE=Release -G Ninja
ninja -C . install
cd ../..
rm -rf Fossilize

View File

@@ -0,0 +1,19 @@
#!/bin/bash
set -ex
# https://github.com/LunarG/gfxreconstruct/issues/328
GFXRECONSTRUCT_VERSION=b66cd392a84b226cb60ad9d4130ddeb58a1559cb
git clone https://github.com/LunarG/gfxreconstruct.git --single-branch --no-checkout /gfxreconstruct
pushd /gfxreconstruct
git checkout "$GFXRECONSTRUCT_VERSION"
git submodule update --init
git submodule update
cmake -G Ninja -B_build -H. -DCMAKE_BUILD_TYPE=Release
ninja -C _build gfxrecon-replay
mkdir -p build/bin
install _build/tools/replay/gfxrecon-replay build/bin
strip build/bin/*
find . -not -path './build' -not -path './build/*' -delete
popd

View File

@@ -0,0 +1,13 @@
#!/bin/bash
set -ex
git clone https://gitlab.freedesktop.org/mesa/piglit.git --single-branch --no-checkout /piglit
pushd /piglit
git checkout 8771c3860505db2bcf4877216221d774bf90af6b
patch -p1 <$OLDPWD/.gitlab-ci/piglit/disable-vs_in.diff
cmake -G Ninja -DCMAKE_BUILD_TYPE=Release
ninja
find -name .git -o -name '*ninja*' -o -iname '*cmake*' -o -name '*.[chao]' | xargs rm -rf
rm -rf target_api
popd

View File

@@ -0,0 +1,17 @@
#!/bin/bash
set -ex
RENDERDOC_VERSION=da02e88201dc3b64316fc33ce6ff69cc729689aa
git clone https://github.com/baldurk/renderdoc.git --single-branch --no-checkout /renderdoc
pushd /renderdoc
git checkout "$RENDERDOC_VERSION"
cmake -G Ninja -B_build -H. -DENABLE_QRENDERDOC=false -DCMAKE_BUILD_TYPE=Release
ninja -C _build
mkdir -p build/lib
cp _build/lib/renderdoc.so build/lib
cp _build/lib/librenderdoc.so build/lib
strip build/lib/*
find . -not -path './build' -not -path './build/*' -delete
popd

View File

@@ -0,0 +1,20 @@
#!/bin/bash
set -ex
mkdir -p /epoxy
pushd /epoxy
wget -qO- https://github.com/anholt/libepoxy/releases/download/1.5.4/libepoxy-1.5.4.tar.xz | tar -xJ --strip-components=1
meson build/ $EXTRA_MESON_ARGS
ninja -C build install
popd
rm -rf /epoxy
VIRGLRENDERER_VERSION=70b18e56d5c3ed69c561c36e098e8aea71ebffc2
git clone https://gitlab.freedesktop.org/virgl/virglrenderer.git --single-branch --no-checkout /virglrenderer
pushd /virglrenderer
git checkout "$VIRGLRENDERER_VERSION"
meson build/ $EXTRA_MESON_ARGS
ninja -C build install
popd
rm -rf /virglrenderer

View File

@@ -0,0 +1,29 @@
#!/bin/bash
set -ex
VULKANTOOLS_VERSION=1862c6a47b64cd09156205d7f7e6b3bfcea76390
git clone https://github.com/LunarG/VulkanTools.git --single-branch --no-checkout /VulkanTools
pushd /VulkanTools
git checkout "$VULKANTOOLS_VERSION"
./update_external_sources.sh
mkdir _build
./scripts/update_deps.py --dir=_build --config=release --generator=Ninja
cmake -G Ninja -B_build -H. \
-DCMAKE_BUILD_TYPE=Release \
-DCMAKE_INSTALL_PREFIX=/VulkanTools/build \
-DBUILD_TESTS=OFF \
-DBUILD_VLF=OFF \
-DBUILD_VKTRACE=OFF \
-DBUILD_VIA=OFF \
-DBUILD_VKTRACE_REPLAY=OFF \
-C_build/helper.cmake
ninja -C _build VkLayer_screenshot VkLayer_screenshot-staging-json
mkdir -p build/etc/vulkan/explicit_layer.d
mkdir build/lib
install _build/layersvt/staging-json/VkLayer_screenshot.json build/etc/vulkan/explicit_layer.d
install _build/layersvt/libVkLayer_screenshot.so build/lib
strip build/lib/*
find . -not -path './build' -not -path './build/*' -delete
popd

View File

@@ -0,0 +1,83 @@
#!/bin/bash
set -e
set -o xtrace
############### Install packages for building
apt-get -y install ca-certificates
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
dpkg --add-architecture armhf
apt-get update
apt-get -y install \
abootimg \
android-sdk-ext4-utils \
bc \
bison \
ccache \
cmake \
cpio \
crossbuild-essential-armhf \
debootstrap \
fastboot \
flex \
g++ \
gettext \
git \
lavacli \
libdrm-dev:armhf \
libegl1-mesa-dev \
libegl1-mesa-dev:armhf \
libelf-dev \
libelf-dev:armhf \
libexpat1-dev \
libexpat1-dev:armhf \
libgles2-mesa-dev \
libgles2-mesa-dev:armhf \
libpng-dev \
libpng-dev:armhf \
libssl-dev \
libvulkan-dev \
libvulkan-dev:armhf \
llvm-7-dev:armhf \
llvm-8-dev \
meson \
pkg-config \
python \
python3-distutils \
python3-mako \
python3-serial \
unzip \
wget \
xz-utils \
zlib1g-dev
. .gitlab-ci/container/container_pre_build.sh
# dependencies where we want a specific version
export LIBDRM_VERSION=libdrm-2.4.100
wget https://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
tar -xvf $LIBDRM_VERSION.tar.bz2 && rm $LIBDRM_VERSION.tar.bz2
cd $LIBDRM_VERSION; meson build -D vc4=true -D freedreno=true -D etnaviv=true; ninja -C build install; cd ..
rm -rf $LIBDRM_VERSION
############### Generate cross build file for Meson
cross_file="/cross_file-armhf.txt"
/usr/share/meson/debcrossgen --arch armhf -o "$cross_file"
# Explicitly set ccache path for cross compilers
sed -i "s|/usr/bin/\([^-]*\)-linux-gnu\([^-]*\)-g|/usr/lib/ccache/\\1-linux-gnu\\2-g|g" "$cross_file"
# Don't need wrapper for armhf executables
sed -i -e '/\[properties\]/a\' -e "needs_exe_wrapper = False" "$cross_file"
############### Generate kernel, ramdisk, test suites, etc for LAVA jobs
DEBIAN_ARCH=arm64 . .gitlab-ci/container/lava_arm.sh
DEBIAN_ARCH=armhf . .gitlab-ci/container/lava_arm.sh
apt-get purge -y \
python3-distutils \
wget
. .gitlab-ci/container/container_post_build.sh

View File

@@ -0,0 +1,72 @@
#!/bin/bash
set -e
set -o xtrace
############### Install packages for building
apt-get -y install ca-certificates
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
apt-get update
apt-get -y install \
bzip2 \
ccache \
cmake \
g++ \
gcc \
git \
libc6-dev \
libdrm-nouveau2 \
libexpat1 \
libgbm-dev \
libgbm-dev \
libgles2-mesa-dev \
libllvm8 \
libpng16-16 \
libpng-dev \
libvulkan-dev \
libvulkan1 \
meson \
netcat \
pkg-config \
procps \
python \
python3-distutils \
waffle-utils \
wget \
zlib1g
. .gitlab-ci/container/container_pre_build.sh
############### Build dEQP runner
. .gitlab-ci/build-cts-runner.sh
############### Build dEQP GL
. .gitlab-ci/build-deqp-gl.sh
############### Uninstall the build software
ccache --show-stats
apt-get purge -y \
bzip2 \
ccache \
cmake \
g++ \
gcc \
git \
libc6-dev \
libgbm-dev \
libgles2-mesa-dev \
libpng-dev \
libvulkan-dev \
meson \
pkg-config \
python \
python3-distutils \
wget
apt-get autoremove -y --purge

View File

@@ -0,0 +1,5 @@
#!/bin/sh
apt-get autoremove -y --purge
ccache --show-stats

View File

@@ -0,0 +1,29 @@
#!/bin/sh
# Common setup among container builds before we get to building code.
export CCACHE_COMPILERCHECK=content
export CCACHE_COMPRESS=true
export CCACHE_DIR=/cache/mesa/ccache
export PATH=/usr/lib/ccache:$PATH
# CMake ignores $PATH, so we have to force CC/GCC to the ccache versions.
# Watch out, you can't have spaces in here because the renderdoc build fails.
export CC="/usr/lib/ccache/gcc"
export CXX="/usr/lib/ccache/g++"
ccache --show-stats
if uname -m | grep -q arm || uname -m | grep -q aarch64; then
export JFLAGS=-j8
else
export JFLAGS=-j4
fi
# Make a wrapper script for ninja to always include the -j flags
echo /usr/bin/ninja $JFLAGS '"$@"' > /usr/local/bin/ninja
chmod +x /usr/local/bin/ninja
# Set MAKEFLAGS so that all make invocations in container builds include the
# flags (doesn't apply to non-container builds, but we don't run make there)
export MAKEFLAGS=$JFLAGS

View File

@@ -0,0 +1,98 @@
#!/bin/bash
set -e
set -o xtrace
if [[ "$DEBIAN_ARCH" = "arm64" ]]; then
GCC_ARCH="aarch64-linux-gnu"
KERNEL_ARCH="arm64"
DEFCONFIG="arch/arm64/configs/defconfig"
DEVICE_TREES="arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dtb arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dtb arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dtb arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dtb arch/arm64/boot/dts/qcom/apq8016-sbc.dtb"
KERNEL_IMAGE_NAME="Image"
else
GCC_ARCH="arm-linux-gnueabihf"
KERNEL_ARCH="arm"
DEFCONFIG="arch/arm/configs/multi_v7_defconfig"
DEVICE_TREES="arch/arm/boot/dts/rk3288-veyron-jaq.dtb arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dtb"
KERNEL_IMAGE_NAME="zImage"
fi
############### Build dEQP runner
if [[ "$DEBIAN_ARCH" = "armhf" ]]; then
EXTRA_MESON_ARGS="--cross-file /cross_file-armhf.txt"
fi
. .gitlab-ci/build-cts-runner.sh
mkdir -p /lava-files/rootfs-${DEBIAN_ARCH}/usr/bin
mv /usr/local/bin/deqp-runner /lava-files/rootfs-${DEBIAN_ARCH}/usr/bin/.
############### Build dEQP
EXTRA_CMAKE_ARGS="-DCMAKE_C_COMPILER=${GCC_ARCH}-gcc -DCMAKE_CXX_COMPILER=${GCC_ARCH}-g++"
STRIP_CMD="${GCC_ARCH}-strip"
. .gitlab-ci/build-deqp-gl.sh
mv /deqp /lava-files/rootfs-${DEBIAN_ARCH}/.
############### Cross-build kernel
KERNEL_URL="https://gitlab.freedesktop.org/tomeu/linux/-/archive/v5.5-panfrost-fixes/linux-v5.5-panfrost-fixes.tar.gz"
if [[ "$DEBIAN_ARCH" = "armhf" ]]; then
export ARCH=${KERNEL_ARCH}
export CROSS_COMPILE="${GCC_ARCH}-"
fi
mkdir -p kernel
wget -qO- ${KERNEL_URL} | tar -xz --strip-components=1 -C kernel
pushd kernel
./scripts/kconfig/merge_config.sh ${DEFCONFIG} ../.gitlab-ci/${KERNEL_ARCH}.config
make ${KERNEL_IMAGE_NAME} dtbs
cp arch/${KERNEL_ARCH}/boot/${KERNEL_IMAGE_NAME} /lava-files/.
cp ${DEVICE_TREES} /lava-files/.
popd
rm -rf kernel
############### Create rootfs
set +e
debootstrap \
--variant=minbase \
--arch=${DEBIAN_ARCH} \
--components main,contrib,non-free \
testing \
/lava-files/rootfs-${DEBIAN_ARCH}/ \
http://deb.debian.org/debian
cat /lava-files/rootfs-${DEBIAN_ARCH}/debootstrap/debootstrap.log
set -e
cp .gitlab-ci/create-rootfs.sh /lava-files/rootfs-${DEBIAN_ARCH}/.
chroot /lava-files/rootfs-${DEBIAN_ARCH} sh /create-rootfs.sh
rm /lava-files/rootfs-${DEBIAN_ARCH}/create-rootfs.sh
if [ ${DEBIAN_ARCH} = arm64 ]; then
# Pull down a specific build of qcomlt/release/qcomlt-5.4 8c79b3d12355
# ("Merge tag 'v5.4.23' into release/qcomlt-5.4"), where I used the
# .config from
# http://snapshots.linaro.org/96boards/dragonboard820c/linaro/debian/457/config-5.4.0-qcomlt-arm64
# with the following merged in:
#
# CONFIG_DRM=y
# CONFIG_DRM_MSM=y
# CONFIG_ATL1C=y
#
# Reason: 5.5 has a big stack of oopses and warns on db820c. 4.14-5.4
# linaro kernel binaries (see above .config link) have these as modules
# and distributed the modules only in the debian system, not the initrd,
# so they're very hard to extract (involving simg2img and loopback
# mounting). 4.11 is missing d72fea538fe6 ("drm/msm: Fix the check for
# the command size") so it can't actually run fredreno. qcomlt-4.14 is
# unstable at boot (~10% instaboot rate). The 5.4 qcomlt kernel with msm
# built in seems like the easiest way to go.
wget https://people.freedesktop.org/~anholt/qcomlt-5.4-msm-build/Image.gz -O Image.gz \
-O /lava-files/db820c-kernel
wget https://people.freedesktop.org/~anholt/qcomlt-5.4-msm-build/apq8096-db820c.dtb \
-O /lava-files/db820c.dtb
# Make a gzipped copy of the Image for db410c.
gzip -k /lava-files/Image
fi

View File

@@ -0,0 +1,52 @@
-----BEGIN PGP PUBLIC KEY BLOCK-----
Version: GnuPG v1.4.12 (GNU/Linux)
mQINBFE9lCwBEADi0WUAApM/mgHJRU8lVkkw0CHsZNpqaQDNaHefD6Rw3S4LxNmM
EZaOTkhP200XZM8lVdbfUW9xSjA3oPldc1HG26NjbqqCmWpdo2fb+r7VmU2dq3NM
R18ZlKixiLDE6OUfaXWKamZsXb6ITTYmgTO6orQWYrnW6ckYHSeaAkW0wkDAryl2
B5v8aoFnQ1rFiVEMo4NGzw4UX+MelF7rxaaregmKVTPiqCOSPJ1McC1dHFN533FY
Wh/RVLKWo6npu+owtwYFQW+zyQhKzSIMvNujFRzhIxzxR9Gn87MoLAyfgKEzrbbT
DhqqNXTxS4UMUKCQaO93TzetX/EBrRpJj+vP640yio80h4Dr5pAd7+LnKwgpTDk1
G88bBXJAcPZnTSKu9I2c6KY4iRNbvRz4i+ZdwwZtdW4nSdl2792L7Sl7Nc44uLL/
ZqkKDXEBF6lsX5XpABwyK89S/SbHOytXv9o4puv+65Ac5/UShspQTMSKGZgvDauU
cs8kE1U9dPOqVNCYq9Nfwinkf6RxV1k1+gwtclxQuY7UpKXP0hNAXjAiA5KS5Crq
7aaJg9q2F4bub0mNU6n7UI6vXguF2n4SEtzPRk6RP+4TiT3bZUsmr+1ktogyOJCc
Ha8G5VdL+NBIYQthOcieYCBnTeIH7D3Sp6FYQTYtVbKFzmMK+36ERreL/wARAQAB
tD1TeWx2ZXN0cmUgTGVkcnUgLSBEZWJpYW4gTExWTSBwYWNrYWdlcyA8c3lsdmVz
dHJlQGRlYmlhbi5vcmc+iQI4BBMBAgAiBQJRPZQsAhsDBgsJCAcDAgYVCAIJCgsE
FgIDAQIeAQIXgAAKCRAVz00Yr090Ibx+EADArS/hvkDF8juWMXxh17CgR0WZlHCC
9CTBWkg5a0bNN/3bb97cPQt/vIKWjQtkQpav6/5JTVCSx2riL4FHYhH0iuo4iAPR
udC7Cvg8g7bSPrKO6tenQZNvQm+tUmBHgFiMBJi92AjZ/Qn1Shg7p9ITivFxpLyX
wpmnF1OKyI2Kof2rm4BFwfSWuf8Fvh7kDMRLHv+MlnK/7j/BNpKdozXxLcwoFBmn
l0WjpAH3OFF7Pvm1LJdf1DjWKH0Dc3sc6zxtmBR/KHHg6kK4BGQNnFKujcP7TVdv
gMYv84kun14pnwjZcqOtN3UJtcx22880DOQzinoMs3Q4w4o05oIF+sSgHViFpc3W
R0v+RllnH05vKZo+LDzc83DQVrdwliV12eHxrMQ8UYg88zCbF/cHHnlzZWAJgftg
hB08v1BKPgYRUzwJ6VdVqXYcZWEaUJmQAPuAALyZESw94hSo28FAn0/gzEc5uOYx
K+xG/lFwgAGYNb3uGM5m0P6LVTfdg6vDwwOeTNIExVk3KVFXeSQef2ZMkhwA7wya
KJptkb62wBHFE+o9TUdtMCY6qONxMMdwioRE5BYNwAsS1PnRD2+jtlI0DzvKHt7B
MWd8hnoUKhMeZ9TNmo+8CpsAtXZcBho0zPGz/R8NlJhAWpdAZ1CmcPo83EW86Yq7
BxQUKnNHcwj2ebkCDQRRPZQsARAA4jxYmbTHwmMjqSizlMJYNuGOpIidEdx9zQ5g
zOr431/VfWq4S+VhMDhs15j9lyml0y4ok215VRFwrAREDg6UPMr7ajLmBQGau0Fc
bvZJ90l4NjXp5p0NEE/qOb9UEHT7EGkEhaZ1ekkWFTWCgsy7rRXfZLxB6sk7pzLC
DshyW3zjIakWAnpQ5j5obiDy708pReAuGB94NSyb1HoW/xGsGgvvCw4r0w3xPStw
F1PhmScE6NTBIfLliea3pl8vhKPlCh54Hk7I8QGjo1ETlRP4Qll1ZxHJ8u25f/ta
RES2Aw8Hi7j0EVcZ6MT9JWTI83yUcnUlZPZS2HyeWcUj+8nUC8W4N8An+aNps9l/
21inIl2TbGo3Yn1JQLnA1YCoGwC34g8QZTJhElEQBN0X29ayWW6OdFx8MDvllbBV
ymmKq2lK1U55mQTfDli7S3vfGz9Gp/oQwZ8bQpOeUkc5hbZszYwP4RX+68xDPfn+
M9udl+qW9wu+LyePbW6HX90LmkhNkkY2ZzUPRPDHZANU5btaPXc2H7edX4y4maQa
xenqD0lGh9LGz/mps4HEZtCI5CY8o0uCMF3lT0XfXhuLksr7Pxv57yue8LLTItOJ
d9Hmzp9G97SRYYeqU+8lyNXtU2PdrLLq7QHkzrsloG78lCpQcalHGACJzrlUWVP/
fN3Ht3kAEQEAAYkCHwQYAQIACQUCUT2ULAIbDAAKCRAVz00Yr090IbhWEADbr50X
OEXMIMGRLe+YMjeMX9NG4jxs0jZaWHc/WrGR+CCSUb9r6aPXeLo+45949uEfdSsB
pbaEdNWxF5Vr1CSjuO5siIlgDjmT655voXo67xVpEN4HhMrxugDJfCa6z97P0+ML
PdDxim57uNqkam9XIq9hKQaurxMAECDPmlEXI4QT3eu5qw5/knMzDMZj4Vi6hovL
wvvAeLHO/jsyfIdNmhBGU2RWCEZ9uo/MeerPHtRPfg74g+9PPfP6nyHD2Wes6yGd
oVQwtPNAQD6Cj7EaA2xdZYLJ7/jW6yiPu98FFWP74FN2dlyEA2uVziLsfBrgpS4l
tVOlrO2YzkkqUGrybzbLpj6eeHx+Cd7wcjI8CalsqtL6cG8cUEjtWQUHyTbQWAgG
5VPEgIAVhJ6RTZ26i/G+4J8neKyRs4vz+57UGwY6zI4AB1ZcWGEE3Bf+CDEDgmnP
LSwbnHefK9IljT9XU98PelSryUO/5UPw7leE0akXKB4DtekToO226px1VnGp3Bov
1GBGvpHvL2WizEwdk+nfk8LtrLzej+9FtIcq3uIrYnsac47Pf7p0otcFeTJTjSq3
krCaoG4Hx0zGQG2ZFpHrSrZTVy6lxvIdfi0beMgY6h78p6M9eYZHQHc02DjFkQXN
bXb5c6gCHESH5PXwPU4jQEE7Ib9J6sbk7ZT2Mw==
=j+4q
-----END PGP PUBLIC KEY BLOCK-----

View File

@@ -0,0 +1,20 @@
-----BEGIN PGP PUBLIC KEY BLOCK-----
Version: GnuPG v2.0.15 (GNU/Linux)
mQENBFu8fWQBCADM64J7qlcnI2KwxSKSdyaOi7hz44EUXDpC3+3hfFP8k28SgV3U
4a/ydOdd2cDSne5w+yjrnJWYuS0sTiE7vQPtKfmCmQZfCStvoRe5Pt+AOy1GA/iu
U5wHIZD+/A9CeQcu5L3PkVkmijz0LmSCq7HnnVB0SdFA5eFlV98H875EasvpJ3xU
ziI3yvqdZ5/0LgKzOiFjk4rMXQS01a1dNpwFO7EXiq921ZjnXatdnsDQ/NAj7z8P
3qnTAj6yvl7DtdlXXA2hiznEOZNCRLZ69vHq0hGIw+OKjpsUkCZK29AnY4wJxxzY
frjknVW7tyZ6Hxwz6R4vaVlZ6h5WR/OiAdqlABEBAAG0NEVtdWxhdG9ycyBPQlMg
UHJvamVjdCA8RW11bGF0b3JzQGJ1aWxkLm9wZW5zdXNlLm9yZz6JAT4EEwEIACgF
Alu8fWQCGwMFCQQesAAGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEN+hdadR
BJYOXVoH/Rd0dRx4SUx7KVjTrDfSuf6jXseyenkl4aQnp46n0MttatkoCdGVvyrq
VWvGfO3MI122MnFKqia7Hep1HlcYGe2a5tW/w1SGGEy+VZduxcZCMmVuSnl+3ioG
2fRGx3uoNBEGQIbZ5VVlABUJC+c/Vq1m6kT9Edz4XWRPHW1Nwjjfn79618ebGZMc
R0fUM9L3GZw9V/kAK8kXmIL7rkglfewTbs6fByqAix79MjsNURAuCeIc5OmbxL4j
LxuoNhnxxucB7YGBhCa9ZL8LYEIbdeyaJmgdHDoUQjz4peXibz5v+Er8mGOwuSLl
y1U21T3huNf9Osjw52nxVcDmugBWqQKIRgQTEQIABgUCW7x9ZAAKCRA7MBG3a51l
IwayAJ9dHmDag9nFY9GujfMr+foKquFS9wCfQlvp6Sz0N5aKdW00NGnZZ/EKHIQ=
=uZyA
-----END PGP PUBLIC KEY BLOCK-----

View File

@@ -5,90 +5,133 @@ set -o xtrace
export DEBIAN_FRONTEND=noninteractive
CROSS_ARCHITECTURES="i386"
CROSS_ARCHITECTURES="i386 ppc64el s390x"
for arch in $CROSS_ARCHITECTURES; do
dpkg --add-architecture $arch
done
apt-get install -y \
ca-certificates \
wget \
unzip
gnupg \
unzip \
wget
# Upstream LLVM package repository
apt-key add .gitlab-ci/container/llvm-snapshot.gpg.key
echo "deb https://apt.llvm.org/buster/ llvm-toolchain-buster-9 main" >/etc/apt/sources.list.d/llvm9.list
# Upstream Wine (WineHQ) package repository. We use the OBS service
# instead of the repository at the winehq.org domain because:
#
# " The WineHQ packages for Debian 10 and later require libfaudio0
# as a dependency. Since the distro does not provide it for Debian
# 10, users of that version can download libfaudio0 packages from
# the OBS. See https://forum.winehq.org/viewtopic.php?f=8&t=32192
# for details."
#
# As explained at https://wiki.winehq.org/Debian
apt-key add .gitlab-ci/container/obs-emulators-wine-debian.gpg.key
echo 'deb https://download.opensuse.org/repositories/Emulators:/Wine:/Debian/Debian_10/ ./' >/etc/apt/sources.list.d/obs-emulators-wine-debian.list
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
apt-get update
# Use newer packages from backports by default
cat >/etc/apt/preferences <<EOF
Package: *
Pin: release a=buster-backports
Pin-Priority: 500
EOF
apt-get dist-upgrade -y
apt-get install -y --no-remove \
llvm-6.0-dev \
libclang-6.0-dev \
llvm-7-dev \
libclang-7-dev \
llvm-8-dev \
libclang-8-dev \
autoconf \
automake \
autotools-dev \
bison \
ccache \
clang-9 \
cmake \
flex \
g++ \
clang-8 \
git \
bzip2 \
zlib1g-dev \
pkg-config \
libxrender-dev \
libxdamage-dev \
libxxf86vm-dev \
gcc \
gettext \
git \
libepoxy-dev \
libegl1-mesa-dev \
libgbm-dev \
libclang-6.0-dev \
libclang-7-dev \
libclang-8-dev \
libclang-9-dev \
libclc-dev \
libxvmc-dev \
libomxil-bellagio-dev \
xz-utils \
libexpat1-dev \
libx11-xcb-dev \
libelf-dev \
libunwind-dev \
libglvnd-dev \
libgtk-3-dev \
libpng-dev \
libepoxy-dev \
libexpat1-dev \
libgbm-dev \
libgles2-mesa-dev \
libgtk-3-dev \
libomxil-bellagio-dev \
libpciaccess-dev \
libtool \
libunwind-dev \
libva-dev \
libvdpau-dev \
libvulkan-dev \
libvulkan-dev:ppc64el \
libx11-dev \
libx11-xcb-dev \
libxdamage-dev \
libxext-dev \
libxml2-utils \
libxrandr-dev \
libxrender-dev \
libxshmfence-dev \
libxvmc-dev \
libxxf86vm-dev \
llvm-6.0-dev \
llvm-7-dev \
llvm-9-dev \
meson \
pkg-config \
python-mako \
python3-mako \
bison \
flex \
gettext \
cmake \
meson \
scons
python3-pil \
python3-requests \
qemu-user \
scons \
x11proto-dri2-dev \
x11proto-gl-dev \
x11proto-randr-dev \
xz-utils \
zlib1g-dev
. .gitlab-ci/container/container_pre_build.sh
# Cross-build Mesa deps
for arch in $CROSS_ARCHITECTURES; do
apt-get install -y --no-remove \
crossbuild-essential-${arch} \
libdrm-dev:${arch} \
libexpat1-dev:${arch} \
libelf-dev:${arch} \
crossbuild-essential-${arch}
libexpat1-dev:${arch} \
libffi-dev:${arch} \
libllvm8:${arch} \
libstdc++6:${arch} \
libtinfo-dev:${arch}
if [ "$arch" == "i386" ]; then
# libpciaccess-dev is only needed for Intel.
apt-get install -y --no-remove \
libpciaccess-dev:${arch}
fi
mkdir /var/cache/apt/archives/${arch}
# Download llvm-* packages, but don't install them yet, since they can
# only be installed for one architecture at a time
apt-get install -o Dir::Cache::archives=/var/cache/apt/archives/$arch --download-only -y --no-remove \
llvm-8-dev:${arch}
done
apt-get install -y --no-remove \
llvm-8-dev \
# for 64bit windows cross-builds
apt-get install -y --no-remove \
mingw-w64 \
libz-mingw-w64-dev \
wine \
wine32 \
wine64
libz-mingw-w64-dev \
mingw-w64 \
winehq-stable
# Debian's pkg-config wrapers for mingw are broken, and there's no sign that
# they're going to be fixed, so we'll just have to fix it ourselves
@@ -100,6 +143,23 @@ PKG_CONFIG_LIBDIR=/usr/x86_64-w64-mingw32/lib/pkgconfig pkg-config \$@
EOF
chmod +x /usr/local/bin/x86_64-w64-mingw32-pkg-config
# Generate cross build files for Meson
for arch in $CROSS_ARCHITECTURES; do
cross_file="/cross_file-$arch.txt"
/usr/share/meson/debcrossgen --arch "$arch" -o "$cross_file"
# Explicitly set ccache path for cross compilers
sed -i "s|/usr/bin/\([^-]*\)-linux-gnu\([^-]*\)-g|/usr/lib/ccache/\\1-linux-gnu\\2-g|g" "$cross_file"
if [ "$arch" = "i386" ]; then
# Work around a bug in debcrossgen that should be fixed in the next release
sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" "$cross_file"
fi
# Rely on qemu-user being configured in binfmt_misc on the host
sed -i -e '/\[properties\]/a\' -e "needs_exe_wrapper = False" "$cross_file"
done
# for the vulkan overlay layer
wget https://github.com/KhronosGroup/glslang/releases/download/master-tot/glslang-master-linux-Release.zip
unzip glslang-master-linux-Release.zip bin/glslangValidator
@@ -113,17 +173,9 @@ export XCB_RELEASES=https://xcb.freedesktop.org/dist
export WAYLAND_RELEASES=https://wayland.freedesktop.org/releases
export XORGMACROS_VERSION=util-macros-1.19.0
export GLPROTO_VERSION=glproto-1.4.17
export DRI2PROTO_VERSION=dri2proto-2.8
export LIBPCIACCESS_VERSION=libpciaccess-0.13.4
export LIBDRM_VERSION=libdrm-2.4.100
export XCBPROTO_VERSION=xcb-proto-1.13
export RANDRPROTO_VERSION=randrproto-1.5.0
export LIBXRANDR_VERSION=libXrandr-1.5.0
export LIBXCB_VERSION=libxcb-1.13
export LIBXSHMFENCE_VERSION=libxshmfence-1.3
export LIBVDPAU_VERSION=libvdpau-1.1
export LIBVA_VERSION=libva-1.7.0
export LIBWAYLAND_VERSION=wayland-1.15.0
export WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.12
@@ -132,16 +184,6 @@ tar -xvf $XORGMACROS_VERSION.tar.bz2 && rm $XORGMACROS_VERSION.tar.bz2
cd $XORGMACROS_VERSION; ./configure; make install; cd ..
rm -rf $XORGMACROS_VERSION
wget $XORG_RELEASES/proto/$GLPROTO_VERSION.tar.bz2
tar -xvf $GLPROTO_VERSION.tar.bz2 && rm $GLPROTO_VERSION.tar.bz2
cd $GLPROTO_VERSION; ./configure; make install; cd ..
rm -rf $GLPROTO_VERSION
wget $XORG_RELEASES/proto/$DRI2PROTO_VERSION.tar.bz2
tar -xvf $DRI2PROTO_VERSION.tar.bz2 && rm $DRI2PROTO_VERSION.tar.bz2
cd $DRI2PROTO_VERSION; ./configure; make install; cd ..
rm -rf $DRI2PROTO_VERSION
wget $XCB_RELEASES/$XCBPROTO_VERSION.tar.bz2
tar -xvf $XCBPROTO_VERSION.tar.bz2 && rm $XCBPROTO_VERSION.tar.bz2
cd $XCBPROTO_VERSION; ./configure; make install; cd ..
@@ -152,41 +194,15 @@ tar -xvf $LIBXCB_VERSION.tar.bz2 && rm $LIBXCB_VERSION.tar.bz2
cd $LIBXCB_VERSION; ./configure; make install; cd ..
rm -rf $LIBXCB_VERSION
wget $XORG_RELEASES/lib/$LIBPCIACCESS_VERSION.tar.bz2
tar -xvf $LIBPCIACCESS_VERSION.tar.bz2 && rm $LIBPCIACCESS_VERSION.tar.bz2
cd $LIBPCIACCESS_VERSION; ./configure; make install; cd ..
rm -rf $LIBPCIACCESS_VERSION
wget https://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
tar -xvf $LIBDRM_VERSION.tar.bz2 && rm $LIBDRM_VERSION.tar.bz2
cd $LIBDRM_VERSION; ./configure --enable-vc4 --enable-freedreno --enable-etnaviv-experimental-api; make install; cd ..
cd $LIBDRM_VERSION
meson build -D vc4=true -D freedreno=true -D etnaviv=true -D libdir=lib/x86_64-linux-gnu; ninja -C build install
rm -rf build; meson --cross-file=/cross_file-ppc64el.txt build -D libdir=lib/powerpc64le-linux-gnu; ninja -C build install
rm -rf build; meson --cross-file=/cross_file-i386.txt build -D libdir=lib/i386-linux-gnu; ninja -C build install
cd ..
rm -rf $LIBDRM_VERSION
wget $XORG_RELEASES/proto/$RANDRPROTO_VERSION.tar.bz2
tar -xvf $RANDRPROTO_VERSION.tar.bz2 && rm $RANDRPROTO_VERSION.tar.bz2
cd $RANDRPROTO_VERSION; ./configure; make install; cd ..
rm -rf $RANDRPROTO_VERSION
wget $XORG_RELEASES/lib/$LIBXRANDR_VERSION.tar.bz2
tar -xvf $LIBXRANDR_VERSION.tar.bz2 && rm $LIBXRANDR_VERSION.tar.bz2
cd $LIBXRANDR_VERSION; ./configure; make install; cd ..
rm -rf $LIBXRANDR_VERSION
wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2
tar -xvf $LIBXSHMFENCE_VERSION.tar.bz2 && rm $LIBXSHMFENCE_VERSION.tar.bz2
cd $LIBXSHMFENCE_VERSION; ./configure; make install; cd ..
rm -rf $LIBXSHMFENCE_VERSION
wget https://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
tar -xvf $LIBVDPAU_VERSION.tar.bz2 && rm $LIBVDPAU_VERSION.tar.bz2
cd $LIBVDPAU_VERSION; ./configure; make install; cd ..
rm -rf $LIBVDPAU_VERSION
wget https://www.freedesktop.org/software/vaapi/releases/libva/$LIBVA_VERSION.tar.bz2
tar -xvf $LIBVA_VERSION.tar.bz2 && rm $LIBVA_VERSION.tar.bz2
cd $LIBVA_VERSION; ./configure --disable-wayland --disable-dummy-driver; make install; cd ..
rm -rf $LIBVA_VERSION
wget $WAYLAND_RELEASES/$LIBWAYLAND_VERSION.tar.xz
tar -xvf $LIBWAYLAND_VERSION.tar.xz && rm $LIBWAYLAND_VERSION.tar.xz
cd $LIBWAYLAND_VERSION; ./configure --enable-libraries --without-host-scanner --disable-documentation --disable-dtd-validation; make install; cd ..
@@ -197,6 +213,17 @@ tar -xvf $WAYLAND_PROTOCOLS_VERSION.tar.xz && rm $WAYLAND_PROTOCOLS_VERSION.tar.
cd $WAYLAND_PROTOCOLS_VERSION; ./configure; make install; cd ..
rm -rf $WAYLAND_PROTOCOLS_VERSION
# The version of libglvnd-dev in debian is too old
# Check this page to see when this local compilation can be dropped in favour of the package:
# https://packages.debian.org/libglvnd-dev
GLVND_VERSION=1.2.0
wget https://gitlab.freedesktop.org/glvnd/libglvnd/-/archive/v$GLVND_VERSION/libglvnd-v$GLVND_VERSION.tar.gz
tar -xvf libglvnd-v$GLVND_VERSION.tar.gz && rm libglvnd-v$GLVND_VERSION.tar.gz
pushd libglvnd-v$GLVND_VERSION; ./autogen.sh; ./configure; make install; popd
rm -rf libglvnd-v$GLVND_VERSION
pushd /usr/local
git clone https://gitlab.freedesktop.org/mesa/shader-db.git --depth 1
rm -rf shader-db/.git
@@ -204,82 +231,19 @@ cd shader-db
make
popd
# Use ccache to speed up builds
apt-get install -y --no-remove ccache
# We need xmllint to validate the XML files in Mesa
apt-get install -y --no-remove libxml2-utils
# Generate cross build files for Meson
for arch in $CROSS_ARCHITECTURES; do
cross_file="/cross_file-$arch.txt"
/usr/share/meson/debcrossgen --arch "$arch" -o "$cross_file"
# Explicitly set ccache path for cross compilers
sed -i "s|/usr/bin/\([^-]*\)-linux-gnu\([^-]*\)-g|/usr/lib/ccache/\\1-linux-gnu\\2-g|g" "$cross_file"
if [ "$arch" = "i386" ]; then
# Work around a bug in debcrossgen that should be fixed in the next release
sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" "$cross_file"
# Don't need wrapper for i386 executables
sed -i -e '/\[properties\]/a\' -e "needs_exe_wrapper = False" "$cross_file"
fi
done
############### Build dEQP
git config --global user.email "mesa@example.com"
git config --global user.name "Mesa CI"
# XXX: Use --depth 1 once we can drop the cherry-picks.
git clone \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b opengl-es-cts-3.2.5.1 \
/VK-GL-CTS
cd /VK-GL-CTS
# Fix surfaceless build
git cherry-pick -x 22f41e5e321c6dcd8569c4dad91bce89f06b3670
git cherry-pick -x 1daa8dff73161ea60ead965bd6c9f2a0a2165648
# surfaceless links against libkms and such despite not using it.
sed -i '/gbm/d' targets/surfaceless/surfaceless.cmake
sed -i '/libkms/d' targets/surfaceless/surfaceless.cmake
sed -i '/libgbm/d' targets/surfaceless/surfaceless.cmake
python3 external/fetch_sources.py
mkdir -p /deqp
cd /deqp
cmake -G Ninja \
-DDEQP_TARGET=surfaceless \
-DCMAKE_BUILD_TYPE=Release \
/VK-GL-CTS
ninja
# Copy out the mustpass lists we want from a bunch of other junk.
mkdir /deqp/mustpass
for gles in gles2 gles3 gles31; do
cp \
/deqp/external/openglcts/modules/gl_cts/data/mustpass/gles/aosp_mustpass/3.2.5.x/$gles-master.txt \
/deqp/mustpass/$gles-master.txt
done
# Remove the rest of the build products that we don't need.
rm -rf /deqp/external
rm -rf /deqp/modules/internal
rm -rf /deqp/executor
rm -rf /deqp/execserver
rm -rf /deqp/modules/egl
rm -rf /deqp/framework
du -sh *
rm -rf /VK-GL-CTS
############### Uninstall the build software
apt-get purge -y \
wget \
unzip \
autoconf \
automake \
autotools-dev \
cmake \
git \
libgles2-mesa-dev \
libgbm-dev
gnupg \
libgbm-dev \
libtool \
unzip \
wget
apt-get autoremove -y --purge
. .gitlab-ci/container/container_post_build.sh

View File

@@ -24,36 +24,37 @@ EOF
apt-get dist-upgrade -y
apt-get install -y --no-remove \
llvm-3.9-dev \
libclang-3.9-dev \
llvm-4.0-dev \
libclang-4.0-dev \
llvm-5.0-dev \
libclang-5.0-dev \
g++ \
bison \
bzip2 \
ccache \
zlib1g-dev \
pkg-config \
flex \
g++ \
gcc \
gettext \
git \
libepoxy-dev \
libclang-3.9-dev \
libclang-4.0-dev \
libclang-5.0-dev \
libclc-dev \
xz-utils \
libdrm-dev \
libexpat1-dev \
libelf-dev \
libunwind-dev \
libepoxy-dev \
libexpat1-dev \
libpng-dev \
libunwind-dev \
llvm-3.9-dev \
llvm-4.0-dev \
llvm-5.0-dev \
meson \
pkg-config \
python-mako \
python3-mako \
bison \
flex \
gettext \
scons \
meson
xz-utils \
zlib1g-dev
. .gitlab-ci/container/container_pre_build.sh
############### Uninstall unused packages
apt-get autoremove -y --purge
. .gitlab-ci/container/container_post_build.sh

View File

@@ -0,0 +1,137 @@
#!/bin/bash
set -e
set -o xtrace
export DEBIAN_FRONTEND=noninteractive
apt-get install -y \
ca-certificates \
gnupg
# Upstream LLVM package repository
apt-key add .gitlab-ci/container/llvm-snapshot.gpg.key
echo "deb https://apt.llvm.org/buster/ llvm-toolchain-buster-9 main" >/etc/apt/sources.list.d/llvm9.list
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
apt-get update
# Use newer packages from backports by default
cat >/etc/apt/preferences <<EOF
Package: *
Pin: release a=buster-backports
Pin-Priority: 500
EOF
apt-get dist-upgrade -y
apt-get install -y --no-remove \
autoconf \
automake \
ccache \
cmake \
g++ \
gcc \
git \
libexpat1 \
libgbm-dev \
libgles2-mesa-dev \
libllvm9 \
libpcre3-dev \
libpcre32-3 \
libpng-dev \
libpng16-16 \
libpython3.7 \
libvulkan-dev \
libvulkan1 \
libwaffle-dev \
libwayland-server0 \
libxcb-keysyms1 \
libxcb-keysyms1-dev \
libxcb-xfixes0 \
libxkbcommon-dev \
libxkbcommon0 \
libxrender-dev \
libxrender1 \
make \
meson \
patch \
pkg-config \
python \
python3-distutils \
python3-mako \
python3-numpy \
python3-pil \
python3-requests \
python3-six \
python3-yaml \
python3.7 \
python3.7-dev \
qt5-default \
qt5-qmake \
waffle-utils \
wget \
xauth \
xvfb \
xz-utils \
zlib1g
. .gitlab-ci/container/container_pre_build.sh
############### Build virglrenderer
. .gitlab-ci/build-virglrenderer.sh
############### Build piglit
. .gitlab-ci/build-piglit.sh
############### Build dEQP runner
. .gitlab-ci/build-cts-runner.sh
############### Build dEQP GL
. .gitlab-ci/build-deqp-gl.sh
############### Build apitrace
. .gitlab-ci/build-apitrace.sh
############### Build renderdoc
. .gitlab-ci/build-renderdoc.sh
############### Uninstall the build software
ccache --show-stats
apt-get purge -y \
autoconf \
automake \
ccache \
cmake \
g++ \
gcc \
gnupg \
libc6-dev \
libgbm-dev \
libgles2-mesa-dev \
libpcre3-dev \
libpng-dev \
libwaffle-dev \
libxcb-keysyms1-dev \
libxkbcommon-dev \
libxrender-dev \
make \
meson \
patch \
pkg-config \
python3-distutils \
python3.7-dev \
wget \
xz-utils
apt-get autoremove -y --purge

View File

@@ -0,0 +1,182 @@
#!/bin/bash
set -e
set -o xtrace
export DEBIAN_FRONTEND=noninteractive
apt-get install -y \
ca-certificates \
gnupg
# Upstream LLVM package repository
apt-key add .gitlab-ci/container/llvm-snapshot.gpg.key
echo "deb https://apt.llvm.org/buster/ llvm-toolchain-buster-9 main" >/etc/apt/sources.list.d/llvm9.list
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
apt-get update
apt-get dist-upgrade -y
apt-get install -y --no-remove \
ccache \
cmake \
g++ \
gcc \
git \
git-lfs \
libexpat1 \
libgbm-dev \
libgles2-mesa-dev \
libllvm9 \
liblz4-1 \
liblz4-dev \
libpng-dev \
libpng16-16 \
libvulkan-dev \
libvulkan1 \
libwayland-client0 \
libwayland-server0 \
libxcb-ewmh-dev \
libxcb-ewmh2 \
libxcb-keysyms1 \
libxcb-keysyms1-dev \
libxcb-randr0 \
libxcb-xfixes0 \
libxkbcommon-dev \
libxkbcommon0 \
libxrandr-dev \
libxrandr2 \
libxrender-dev \
libxrender1 \
meson \
p7zip \
pkg-config \
python \
python3-distutils \
python3-pil \
python3-requests \
python3-yaml \
vulkan-tools \
wget \
xauth \
xvfb
# We need multiarch for Wine
dpkg --add-architecture i386
apt-get update
apt-get install -y --no-remove \
wine \
wine32 \
wine64
############### Set up Wine env variables
export WINEDEBUG="-all"
export WINEPREFIX="/dxvk-wine64"
############### Install DXVK
DXVK_VERSION="1.6"
# We don't want crash dialogs
cat >crashdialog.reg <<EOF
Windows Registry Editor Version 5.00
[HKEY_CURRENT_USER\Software\Wine\WineDbg]
"ShowCrashDialog"=dword:00000000
EOF
# Set the wine prefix and disable the crash dialog
wine regedit crashdialog.reg
rm crashdialog.reg
# DXVK's setup often fails with:
# "${WINEPREFIX}: Not a valid wine prefix."
# and that is just spit because of checking the existance of the
# system.reg file, which fails.
# Just giving it a bit more of time for it to be created solves the
# problem ...
test -f "${WINEPREFIX}/system.reg" || sleep 2
wget "https://github.com/doitsujin/dxvk/releases/download/v${DXVK_VERSION}/dxvk-${DXVK_VERSION}.tar.gz"
tar xzpf dxvk-"${DXVK_VERSION}".tar.gz
dxvk-"${DXVK_VERSION}"/setup_dxvk.sh install
rm -rf dxvk-"${DXVK_VERSION}"
rm dxvk-"${DXVK_VERSION}".tar.gz
############### Install Windows' apitrace binaries
APITRACE_VERSION="9.0"
APITRACE_VERSION_DATE="20191126"
wget "https://github.com/apitrace/apitrace/releases/download/${APITRACE_VERSION}/apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64.7z"
7zr x "apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64.7z" \
"apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64/bin/apitrace.exe" \
"apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64/bin/d3dretrace.exe"
mv "apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64" /apitrace-msvc-win64
rm "apitrace-${APITRACE_VERSION}.${APITRACE_VERSION_DATE}-win64.7z"
# Add the apitrace path to the registry
wine \
reg add "HKEY_LOCAL_MACHINE\System\CurrentControlSet\Control\Session Manager\Environment" \
/v Path \
/t REG_EXPAND_SZ \
/d "C:\windows\system32;C:\windows;C:\windows\system32\wbem;Z:\apitrace-msvc-win64\bin" \
/f
############### Building ...
. .gitlab-ci/container/container_pre_build.sh
############### Build dEQP runner
. .gitlab-ci/build-cts-runner.sh
############### Build Fossilize
. .gitlab-ci/build-fossilize.sh
############### Build dEQP VK
. .gitlab-ci/build-deqp-vk.sh
############### Build gfxreconstruct
. .gitlab-ci/build-gfxreconstruct.sh
############### Build VulkanTools
. .gitlab-ci/build-vulkantools.sh
############### Uninstall the build software
ccache --show-stats
apt-get purge -y \
ccache \
cmake \
g++ \
gcc \
gnupg \
libgbm-dev \
libgles2-mesa-dev \
liblz4-dev \
libpng-dev \
libvulkan-dev \
libxcb-ewmh-dev \
libxcb-keysyms1-dev \
libxkbcommon-dev \
libxrandr-dev \
libxrender-dev \
meson \
p7zip \
pkg-config \
wget
apt-get autoremove -y --purge

View File

@@ -1,16 +1,43 @@
#!/bin/sh
#!/bin/bash
set -ex
apt-get -y install --no-install-recommends initramfs-tools libpng16-16 strace libsensors5 libexpat1 libdrm2
apt-get -y install --no-install-recommends \
ca-certificates \
initramfs-tools \
libpng16-16 \
strace \
libsensors5 \
libexpat1 \
libdrm2 \
libdrm-nouveau2 \
firmware-qcom-media \
wget \
xz-utils
passwd root -d
chsh -s /bin/sh
ln -s /bin/sh /init
cat > /init <<EOF
#!/bin/sh
export PS1=lava-shell:
exec sh
EOF
chmod +x /init
mkdir -p /lib/firmware/rtl_nic
wget https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/rtl_nic/rtl8153a-3.fw -O /lib/firmware/rtl_nic/rtl8153a-3.fw
#######################################################################
# Strip the image to a small minimal system without removing the debian
# toolchain.
# xz compress firmware so it doesn't waste RAM at runtime. Except db820c's
# GPU firmware, due to using a precompiled kernel without compression support.
find /lib/firmware -type f -print0 | \
grep -vz a530 | \
xargs -0r -P4 -n4 xz -T1 -C crc32
ln -s /lib/firmware/qcom/a530* /lib/firmware/
# Copy timezone file and remove tzdata package
rm -rf /etc/localtime
cp /usr/share/zoneinfo/Etc/UTC /etc/localtime
@@ -78,19 +105,14 @@ UNNEEDED_PACKAGES="apt libapt-pkg5.0 "\
"init-system-helpers "\
"bash "\
"cpio "\
"xz-utils "\
"passwd "\
"libsemanage1 libsemanage-common "\
"libsepol1 "\
"gzip "\
"gnupg "\
"gpgv "\
"hostname "\
"adduser "\
"debian-archive-keyring "\
"libgl1 libgl1-mesa-dri libglapi-mesa libglvnd0 libglx-mesa0 libegl-mesa0 libgles2 "\
"libllvm7 "\
"libx11-data libthai-data "\
"systemd dbus "\
# Removing unneeded packages
for PACKAGE in ${UNNEEDED_PACKAGES}
@@ -181,5 +203,3 @@ rm usr/lib/*/libdb-5.3.so
# remove NSS support for nis, nisplus and hesiod
rm usr/lib/*/libnss_hesiod*
rm usr/lib/*/libnss_nis*
rm bin/tar

View File

@@ -0,0 +1,4 @@
lp_test_arit
roundeven
u_format_test
u_half_test

View File

@@ -0,0 +1,4 @@
lp_test_arit
lp_test_format
lp_test_printf
u_format_test

View File

@@ -1,121 +0,0 @@
#!/bin/bash
set -e
set -o xtrace
############### Install packages for building
apt-get -y install ca-certificates
sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list
echo 'deb https://deb.debian.org/debian buster-backports main' >/etc/apt/sources.list.d/backports.list
dpkg --add-architecture armhf
apt-get update
apt-get -y install \
bc \
bison \
bzip2 \
ccache \
cmake \
crossbuild-essential-armhf \
curl \
flex \
g++ \
gettext \
git \
libdrm-dev \
libdrm-dev:armhf \
libelf-dev \
libelf-dev:armhf \
libexpat1-dev \
libexpat1-dev:armhf \
libgbm-dev \
libgles2-mesa-dev \
libpng-dev \
libssl-dev \
llvm-7-dev:armhf \
llvm-8-dev \
meson \
ninja-build \
pkg-config \
procps \
python \
python3-mako \
wget \
zlib1g-dev
############### Generate cross build file for Meson
cross_file="/cross_file-armhf.txt"
/usr/share/meson/debcrossgen --arch armhf -o "$cross_file"
# Explicitly set ccache path for cross compilers
sed -i "s|/usr/bin/\([^-]*\)-linux-gnu\([^-]*\)-g|/usr/lib/ccache/\\1-linux-gnu\\2-g|g" "$cross_file"
# Don't need wrapper for armhf executables
sed -i -e '/\[properties\]/a\' -e "needs_exe_wrapper = False" "$cross_file"
export LIBDRM_VERSION=libdrm-2.4.99
############### Build libdrm
wget https://dri.freedesktop.org/libdrm/$LIBDRM_VERSION.tar.bz2
tar -xvf $LIBDRM_VERSION.tar.bz2 && rm $LIBDRM_VERSION.tar.bz2
cd $LIBDRM_VERSION; meson build/ -Detnaviv=true; ninja -C build/ install; cd ..
rm -rf $LIBDRM_VERSION
############### Build dEQP
git config --global user.email "mesa@example.com"
git config --global user.name "Mesa CI"
# XXX: Use --depth 1 once we can drop the cherry-picks.
git clone \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b opengl-es-cts-3.2.5.1 \
/VK-GL-CTS
cd /VK-GL-CTS
# Fix surfaceless build
git cherry-pick -x 22f41e5e321c6dcd8569c4dad91bce89f06b3670
git cherry-pick -x 1daa8dff73161ea60ead965bd6c9f2a0a2165648
# surfaceless links against libkms and such despite not using it.
sed -i '/gbm/d' targets/surfaceless/surfaceless.cmake
sed -i '/libkms/d' targets/surfaceless/surfaceless.cmake
sed -i '/libgbm/d' targets/surfaceless/surfaceless.cmake
# --insecure is due to SSL cert failures hitting sourceforge for zlib and
# libpng (sigh). The archives get their checksums checked anyway, and git
# always goes through ssh or https.
python3 external/fetch_sources.py --insecure
mkdir -p /deqp
cd /deqp
cmake -G Ninja \
-DDEQP_TARGET=surfaceless \
-DCMAKE_BUILD_TYPE=Release \
/VK-GL-CTS
ninja
# Copy out the mustpass lists we want from a bunch of other junk.
mkdir /deqp/mustpass
for gles in gles2 gles3 gles31; do
cp \
/deqp/external/openglcts/modules/gl_cts/data/mustpass/gles/aosp_mustpass/3.2.5.x/$gles-master.txt \
/deqp/mustpass/$gles-master.txt
done
rm -rf /deqp/external
rm -rf /deqp/modules/internal
rm -rf /deqp/executor
rm -rf /deqp/execserver
rm -rf /deqp/modules/egl
rm -rf /deqp/framework
du -sh *
rm -rf /VK-GL-CTS
############### Uninstall the build software
apt-get purge -y \
cmake \
git \
libgbm-dev \
libgles2-mesa-dev \
wget
apt-get autoremove -y --purge

View File

@@ -3,8 +3,8 @@
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance
dEQP-GLES[0-9]*.stress
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish
dEQP-GLES[0-9]*.functional.flush_finish.*

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,23 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish.*
# Flaky results
dEQP-GLES3.functional.occlusion_query.stencil_write
dEQP-GLES3.functional.rasterization.fbo.rbo_.*
dEQP-GLES3.functional.rasterization.fbo.texture_2d.interpolation.triangles
dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.points
dEQP-GLES3.functional.rasterization.flatshading.lines_wide
dEQP-GLES3.functional.rasterization.flatshading.triangles
dEQP-GLES3.functional.shaders.linkage.varying.interpolation.centroid
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.*
dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.*
dEQP-GLES3.functional.texture.units.4_units.only_3d.*
dEQP-GLES3.functional.vertex_arrays.single_attribute.*

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,17 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish.*
# unstable results (probably related to the iommu faults).
dEQP-GLES3.functional.texture.filtering.3d.*
dEQP-GLES3.functional.texture.vertex.3d.filtering.*
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_stencil
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_stencil
dEQP-GLES31.functional.ubo.2_level_struct_array.single_buffer.packed_instance_array_fragment

View File

@@ -0,0 +1,96 @@
dEQP-GLES31.functional.blend_equation_advanced.barrier.colorburn
dEQP-GLES31.functional.blend_equation_advanced.barrier.colordodge
dEQP-GLES31.functional.blend_equation_advanced.barrier.darken
dEQP-GLES31.functional.blend_equation_advanced.barrier.difference
dEQP-GLES31.functional.blend_equation_advanced.barrier.exclusion
dEQP-GLES31.functional.blend_equation_advanced.barrier.hardlight
dEQP-GLES31.functional.blend_equation_advanced.barrier.hsl_color
dEQP-GLES31.functional.blend_equation_advanced.barrier.hsl_hue
dEQP-GLES31.functional.blend_equation_advanced.barrier.hsl_luminosity
dEQP-GLES31.functional.blend_equation_advanced.barrier.hsl_saturation
dEQP-GLES31.functional.blend_equation_advanced.barrier.lighten
dEQP-GLES31.functional.blend_equation_advanced.barrier.multiply
dEQP-GLES31.functional.blend_equation_advanced.barrier.overlay
dEQP-GLES31.functional.blend_equation_advanced.barrier.screen
dEQP-GLES31.functional.blend_equation_advanced.barrier.softlight
dEQP-GLES31.functional.blend_equation_advanced.basic.colorburn
dEQP-GLES31.functional.blend_equation_advanced.basic.colordodge
dEQP-GLES31.functional.blend_equation_advanced.basic.darken
dEQP-GLES31.functional.blend_equation_advanced.basic.difference
dEQP-GLES31.functional.blend_equation_advanced.basic.exclusion
dEQP-GLES31.functional.blend_equation_advanced.basic.hardlight
dEQP-GLES31.functional.blend_equation_advanced.basic.hsl_color
dEQP-GLES31.functional.blend_equation_advanced.basic.hsl_hue
dEQP-GLES31.functional.blend_equation_advanced.basic.hsl_luminosity
dEQP-GLES31.functional.blend_equation_advanced.basic.hsl_saturation
dEQP-GLES31.functional.blend_equation_advanced.basic.lighten
dEQP-GLES31.functional.blend_equation_advanced.basic.multiply
dEQP-GLES31.functional.blend_equation_advanced.basic.overlay
dEQP-GLES31.functional.blend_equation_advanced.basic.screen
dEQP-GLES31.functional.blend_equation_advanced.basic.softlight
dEQP-GLES31.functional.blend_equation_advanced.msaa.colorburn
dEQP-GLES31.functional.blend_equation_advanced.msaa.colordodge
dEQP-GLES31.functional.blend_equation_advanced.msaa.darken
dEQP-GLES31.functional.blend_equation_advanced.msaa.difference
dEQP-GLES31.functional.blend_equation_advanced.msaa.exclusion
dEQP-GLES31.functional.blend_equation_advanced.msaa.hardlight
dEQP-GLES31.functional.blend_equation_advanced.msaa.hsl_color
dEQP-GLES31.functional.blend_equation_advanced.msaa.hsl_hue
dEQP-GLES31.functional.blend_equation_advanced.msaa.hsl_luminosity
dEQP-GLES31.functional.blend_equation_advanced.msaa.hsl_saturation
dEQP-GLES31.functional.blend_equation_advanced.msaa.lighten
dEQP-GLES31.functional.blend_equation_advanced.msaa.multiply
dEQP-GLES31.functional.blend_equation_advanced.msaa.overlay
dEQP-GLES31.functional.blend_equation_advanced.msaa.screen
dEQP-GLES31.functional.blend_equation_advanced.msaa.softlight
dEQP-GLES31.functional.blend_equation_advanced.srgb.colorburn
dEQP-GLES31.functional.blend_equation_advanced.srgb.colordodge
dEQP-GLES31.functional.blend_equation_advanced.srgb.darken
dEQP-GLES31.functional.blend_equation_advanced.srgb.difference
dEQP-GLES31.functional.blend_equation_advanced.srgb.exclusion
dEQP-GLES31.functional.blend_equation_advanced.srgb.hardlight
dEQP-GLES31.functional.blend_equation_advanced.srgb.hsl_color
dEQP-GLES31.functional.blend_equation_advanced.srgb.hsl_hue
dEQP-GLES31.functional.blend_equation_advanced.srgb.hsl_luminosity
dEQP-GLES31.functional.blend_equation_advanced.srgb.hsl_saturation
dEQP-GLES31.functional.blend_equation_advanced.srgb.lighten
dEQP-GLES31.functional.blend_equation_advanced.srgb.multiply
dEQP-GLES31.functional.blend_equation_advanced.srgb.overlay
dEQP-GLES31.functional.blend_equation_advanced.srgb.screen
dEQP-GLES31.functional.blend_equation_advanced.srgb.softlight
dEQP-GLES31.functional.compute.basic.shared_var_single_group
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_advanced_blend_eq_buffer_advanced_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_blend_eq_buffer_advanced_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_separate_blend_eq_buffer_advanced_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_advanced_blend_eq_buffer_advanced_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_advanced_blend_eq_buffer_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_advanced_blend_eq_buffer_separate_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_separate_blend_eq_buffer_blend_eq
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.11
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.15
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.17
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.18
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.2
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.3
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.6
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.7
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.19
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.3
dEQP-GLES31.functional.image_load_store.early_fragment_tests.early_fragment_tests_depth_fbo
dEQP-GLES31.functional.ssbo.layout.3_level_array.std140.column_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std430.mat3
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
dEQP-GLES31.functional.ssbo.layout.unsized_struct_array.per_block_buffer.shared_instance_array
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_draw
dEQP-GLES31.functional.stencil_texturing.render.depth32f_stencil8_clear
dEQP-GLES31.functional.stencil_texturing.render.depth32f_stencil8_draw
dEQP-GLES31.functional.tessellation.invariance.inner_triangle_set.quads_fractional_even_spacing
dEQP-GLES31.functional.tessellation.invariance.tess_coord_component_range.triangles_fractional_odd_spacing_cw
dEQP-GLES31.functional.texture.multisample.samples_1.use_texture_depth_2d
dEQP-GLES31.functional.texture.multisample.samples_1.use_texture_depth_2d_array
dEQP-GLES31.functional.texture.multisample.samples_2.use_texture_depth_2d
dEQP-GLES31.functional.texture.multisample.samples_2.use_texture_depth_2d_array
dEQP-GLES31.functional.texture.multisample.samples_3.use_texture_depth_2d
dEQP-GLES31.functional.texture.multisample.samples_3.use_texture_depth_2d_array
dEQP-GLES31.functional.texture.multisample.samples_4.use_texture_depth_2d
dEQP-GLES31.functional.texture.multisample.samples_4.use_texture_depth_2d_array

View File

@@ -1,3 +1,4 @@
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clip_control.depth_mode_zero_to_one
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_clear
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_draw

View File

@@ -0,0 +1,18 @@
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_clear
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_draw
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.11
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.16
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.21
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.31
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.6
dEQP-GLES31.functional.ubo.random.all_shared_buffer.12
dEQP-GLES31.functional.ubo.random.all_shared_buffer.17
dEQP-GLES31.functional.ubo.random.all_shared_buffer.2
dEQP-GLES31.functional.ubo.random.all_shared_buffer.27
dEQP-GLES31.functional.ubo.random.all_shared_buffer.37
dEQP-GLES31.functional.ubo.random.all_shared_buffer.47
dEQP-GLES31.functional.ubo.random.basic_type_arrays.1
dEQP-GLES31.functional.ubo.random.basic_type_arrays.11
dEQP-GLES31.functional.ubo.random.basic_type_arrays.16
dEQP-GLES31.functional.ubo.random.basic_type_arrays.21
dEQP-GLES31.functional.ubo.random.basic_type_arrays.6

View File

@@ -3,27 +3,61 @@
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance
dEQP-GLES[0-9]*.stress
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish
dEQP-GLES[0-9]*.functional.flush_finish.*
# Unstable test results
dEQP-GLES3.functional.fragment_out.random.*
dEQP-GLES3.functional.transform_feedback.*
#dEQP-GLES3.functional.fragment_out.random.*
dEQP-GLES3.functional.transform_feedback.*points.*
dEQP-GLES3.functional.transform_feedback.*lines.*
dEQP-GLES31.functional.primitive_bounding_box.*
#dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array.*
# Intermittent timeout
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.48
# Flakes reported more than once during Jan-Feb 2020
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array
# Seen a couple flakes on this one. Note that valgrind complains about
# some things in deqp reference renderer on this one. Not sure if that
# is a real problem or perhaps valgrind gets confused about unitialized
# z24 channel in z24s8?? Let's just skip this one for now:
dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
# Two reports of spurious failures on unrelated MRs (2019-09-27, 2019-10-05)
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.r16ui_2d
# Layered rendering is sysmem only and needs working clears
dEQP-GLES31.functional.geometry_shading.layered.*
dEQP-GLES31.functional.geometry_shading.instanced.*layer.*
dEQP-GLES3.functional.fragment_out.random.0
dEQP-GLES3.functional.fragment_out.random.1
dEQP-GLES3.functional.fragment_out.random.12
dEQP-GLES3.functional.fragment_out.random.13
dEQP-GLES3.functional.fragment_out.random.17
dEQP-GLES3.functional.fragment_out.random.24
dEQP-GLES3.functional.fragment_out.random.27
dEQP-GLES3.functional.fragment_out.random.28
dEQP-GLES3.functional.fragment_out.random.32
dEQP-GLES3.functional.fragment_out.random.34
dEQP-GLES3.functional.fragment_out.random.35
dEQP-GLES3.functional.fragment_out.random.36
dEQP-GLES3.functional.fragment_out.random.40
dEQP-GLES3.functional.fragment_out.random.44
dEQP-GLES3.functional.fragment_out.random.47
dEQP-GLES3.functional.fragment_out.random.5
dEQP-GLES3.functional.fragment_out.random.50
dEQP-GLES3.functional.fragment_out.random.51
dEQP-GLES3.functional.fragment_out.random.55
dEQP-GLES3.functional.fragment_out.random.58
dEQP-GLES3.functional.fragment_out.random.59
dEQP-GLES3.functional.fragment_out.random.61
dEQP-GLES3.functional.fragment_out.random.63
dEQP-GLES3.functional.fragment_out.random.66
dEQP-GLES3.functional.fragment_out.random.67
dEQP-GLES3.functional.fragment_out.random.69
dEQP-GLES3.functional.fragment_out.random.70
dEQP-GLES3.functional.fragment_out.random.71
dEQP-GLES3.functional.fragment_out.random.80
dEQP-GLES3.functional.fragment_out.random.82
dEQP-GLES3.functional.fragment_out.random.86
dEQP-GLES3.functional.fragment_out.random.88
dEQP-GLES3.functional.fragment_out.random.91
dEQP-GLES3.functional.fragment_out.random.93
dEQP-GLES3.functional.fragment_out.random.95
dEQP-GLES3.functional.fragment_out.random.96
dEQP-GLES3.functional.transform_feedback.array_element.interleaved.triangles.highp_mat2x3
dEQP-GLES3.functional.transform_feedback.array_element.interleaved.triangles.lowp_mat2x4
dEQP-GLES3.functional.transform_feedback.array_element.separate.triangles.lowp_mat2x4

File diff suppressed because it is too large Load Diff

View File

@@ -9,13 +9,30 @@ dEQP-GLES[0-9]*.stress
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish
dEQP-GLES2.accuracy.texture.*
dEQP-GLES2.functional.clipping.*
dEQP-GLES2.functional.fbo.render.depth.*
dEQP-GLES2.functional.fbo.render.*
dEQP-GLES2.functional.fbo.completeness.*
dEQP-GLES2.functional.fragment_ops.*
dEQP-GLES2.functional.light_amount.*
dEQP-GLES2.functional.polygon_offset.*
dEQP-GLES2.functional.shaders.*
dEQP-GLES2.functional.texture.*
# Flaky
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.default_vertex_attrib.*
dEQP-GLES2.functional.fbo.completeness.size.distinct
dEQP-GLES2.functional.negative_api.shader.uniform_matrixfv_invalid_transpose
dEQP-GLES2.functional.negative_api.texture.generatemipmap_zero_level_array_compressed
dEQP-GLES2.functional.shaders.builtin_variable.frontfacing
dEQP-GLES2.functional.shaders.random.exponential.fragment.94
dEQP-GLES2.functional.shaders.random.all_features.fragment.55
dEQP-GLES2.functional.shaders.random.trigonometric.fragment.1
dEQP-GLES2.functional.shaders.random.trigonometric.fragment.69
# Hangs / OOM
dEQP-GLES2.functional.shaders.indexing.varying_array.vec4_dynamic_loop_write_static_read
dEQP-GLES2.functional.shaders.indexing.varying_array.vec4_dynamic_loop_write_dynamic_read
dEQP-GLES2.functional.shaders.indexing.varying_array.vec4_dynamic_loop_write_static_loop_read
dEQP-GLES2.functional.shaders.indexing.varying_array.vec4_dynamic_loop_write_dynamic_loop_read
dEQP-GLES2.functional.shaders.indexing.tmp_array.vec4_dynamic_loop_write_static_read_vertex
dEQP-GLES2.functional.shaders.indexing.tmp_array.vec4_dynamic_loop_write_dynamic_read_vertex
dEQP-GLES2.functional.shaders.indexing.tmp_array.vec4_dynamic_loop_write_static_loop_read_vertex
dEQP-GLES2.functional.shaders.indexing.tmp_array.vec4_dynamic_loop_write_dynamic_loop_read_vertex
dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_dynamic_loop_write_static_read_vertex
dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_dynamic_loop_write_dynamic_read_vertex
dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_dynamic_loop_write_static_loop_read_vertex
dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_dynamic_loop_write_dynamic_loop_read_vertex

View File

@@ -28,7 +28,6 @@ dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide
dEQP-GLES2.functional.rasterization.limits.points
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2d_bias
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2dproj_vec3_bias
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2dproj_vec4_bias

View File

@@ -0,0 +1,31 @@
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgba_depth_component16

View File

@@ -0,0 +1,14 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish.*
# XXX: Why does this flake?
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z

View File

@@ -1,728 +1,31 @@
dEQP-GLES2.functional.depth_range.write.0_8_to_third Fail
dEQP-GLES2.functional.depth_range.write.clamp_both Fail
dEQP-GLES2.functional.depth_range.write.clamp_far Fail
dEQP-GLES2.functional.depth_range.write.clamp_near Fail
dEQP-GLES2.functional.depth_range.write.default Fail
dEQP-GLES2.functional.depth_range.write.half_to_half Fail
dEQP-GLES2.functional.depth_range.write.half_to_one Fail
dEQP-GLES2.functional.depth_range.write.half_to_zero Fail
dEQP-GLES2.functional.depth_range.write.one_to_half Fail
dEQP-GLES2.functional.depth_range.write.one_to_one Fail
dEQP-GLES2.functional.depth_range.write.reverse Fail
dEQP-GLES2.functional.depth_range.write.third_to_0_8 Fail
dEQP-GLES2.functional.depth_range.write.zero_to_half Fail
dEQP-GLES2.functional.depth_stencil_clear.depth Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_scissored Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_scissored_masked Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_scissored Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_scissored_masked Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_stencil_index8 Fail
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgba_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb565_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgba_depth_component16 Fail
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgb_depth_component16 Fail
dEQP-GLES2.functional.fragment_ops.blend.equation_src_func_dst_func.add_dst_color_one_minus_src_color Fail
dEQP-GLES2.functional.fragment_ops.blend.equation_src_func_dst_func.reverse_subtract_zero_dst_alpha Fail
dEQP-GLES2.functional.fragment_ops.blend.equation_src_func_dst_func.reverse_subtract_zero_dst_color Fail
dEQP-GLES2.functional.fragment_ops.blend.equation_src_func_dst_func.reverse_subtract_zero_one Fail
dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.dst.one_minus_src_color_one_minus_src_alpha Fail
dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.dst.one_minus_src_color_one_minus_src_color Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.0 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.10 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.11 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.12 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.13 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.14 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.15 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.16 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.17 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.18 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.19 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.1 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.20 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.21 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.22 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.23 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.24 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.2 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.3 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.4 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.5 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.6 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.7 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.8 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.random.9 Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.no_stencil_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_always_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_gequal_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_greater_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_lequal_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_less_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_never_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_always Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_equal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_gequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_greater Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_lequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_less Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_never Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_depth_notequal Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_notequal_no_depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_wrap_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_wrap_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.incr_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.invert_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.keep_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.replace_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_decr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_wrap_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_incr_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_invert_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_keep_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_replace_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_decr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_decr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_incr Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_incr_wrap Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_invert Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_keep Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_replace Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.zero_zero_zero Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.write_mask.both Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.write_mask.depth Fail
dEQP-GLES2.functional.fragment_ops.depth_stencil.write_mask.stencil Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.11 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.13 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.15 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.17 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.18 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.19 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.20 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.22 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.26 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.39 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.42 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.44 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.47 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.48 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.57 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.60 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.61 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.64 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.68 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.72 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.75 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.77 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.79 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.8 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.93 Fail
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.98 Fail
dEQP-GLES2.functional.fragment_ops.random.0 Fail
dEQP-GLES2.functional.fragment_ops.random.11 Fail
dEQP-GLES2.functional.fragment_ops.random.19 Fail
dEQP-GLES2.functional.fragment_ops.random.24 Fail
dEQP-GLES2.functional.fragment_ops.random.25 Fail
dEQP-GLES2.functional.fragment_ops.random.32 Fail
dEQP-GLES2.functional.fragment_ops.random.37 Fail
dEQP-GLES2.functional.fragment_ops.random.3 Fail
dEQP-GLES2.functional.fragment_ops.random.45 Fail
dEQP-GLES2.functional.fragment_ops.random.48 Fail
dEQP-GLES2.functional.fragment_ops.random.53 Fail
dEQP-GLES2.functional.fragment_ops.random.56 Fail
dEQP-GLES2.functional.fragment_ops.random.63 Fail
dEQP-GLES2.functional.fragment_ops.random.65 Fail
dEQP-GLES2.functional.fragment_ops.random.66 Fail
dEQP-GLES2.functional.fragment_ops.random.67 Fail
dEQP-GLES2.functional.fragment_ops.random.68 Fail
dEQP-GLES2.functional.fragment_ops.random.6 Fail
dEQP-GLES2.functional.fragment_ops.random.72 Fail
dEQP-GLES2.functional.fragment_ops.random.75 Fail
dEQP-GLES2.functional.fragment_ops.random.81 Fail
dEQP-GLES2.functional.fragment_ops.random.87 Fail
dEQP-GLES2.functional.fragment_ops.random.94 Fail
dEQP-GLES2.functional.fragment_ops.random.96 Fail
dEQP-GLES2.functional.polygon_offset.default_render_with_units Fail
dEQP-GLES2.functional.polygon_offset.fixed16_factor_1_slope Fail
dEQP-GLES2.functional.polygon_offset.fixed16_render_with_units Fail
dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_fragment Fail
dEQP-GLES2.functional.shaders.scoping.valid.local_variable_hides_function_parameter_vertex Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgba_depth_component16

View File

@@ -3,61 +3,9 @@
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance
dEQP-GLES[0-9]*.stress
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish
dEQP-GLES2.functional.fbo.render.depth.*
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_pos_y_pos_z_and_neg_x_neg_y_pos_z_and_pos_x_pos_y_neg_z
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgba4
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgba4
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.*
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.*
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgb
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgba
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.stencil_clear.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.npot_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.npot_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.lifetime.attach.deleted_input.renderbuffer_framebuffer
dEQP-GLES2.functional.lifetime.attach.deleted_output.renderbuffer_framebuffer
dEQP-GLES2.functional.polygon_offset.fixed16_factor_0_slope
dEQP-GLES2.functional.polygon_offset.fixed16_factor_1_slope
dEQP-GLES2.functional.shaders.invariance.highp.loop_4
dEQP-GLES2.functional.shaders.matrix.mul.dynamic_highp_mat4_vec4_vertex
dEQP-GLES2.functional.shaders.matrix.mul.dynamic_highp_vec4_mat4_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.smoothstep.mediump_vec3_vertex
dEQP-GLES2.functional.shaders.random.all_features.fragment.12
dEQP-GLES2.functional.shaders.random.all_features.fragment.37
dEQP-GLES2.functional.texture.units.2_units.mixed.1
dEQP-GLES2.functional.texture.units.2_units.mixed.3
dEQP-GLES2.functional.texture.units.2_units.only_2d.2
dEQP-GLES2.functional.texture.units.4_units.mixed.5
dEQP-GLES2.functional.texture.units.4_units.only_2d.0
dEQP-GLES2.functional.texture.units.8_units.only_cube.2
dEQP-GLES2.functional.texture.units.all_units.mixed.6
dEQP-GLES2.functional.texture.units.all_units.only_cube.4
dEQP-GLES2.functional.texture.units.all_units.only_cube.7
dEQP-GLES2.functional.texture.units.all_units.only_cube.8
dEQP-GLES[0-9]*.functional.flush_finish.*

View File

@@ -0,0 +1,31 @@
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb565_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgb_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_tex2d_rgba_stencil_index8
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgba_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb565_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgb_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.tex2d_rgba_depth_component16

View File

@@ -0,0 +1,13 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish.*
# XXX: Why does this flake?
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z

File diff suppressed because it is too large Load Diff

View File

@@ -3,61 +3,18 @@
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance
dEQP-GLES[0-9]*.stress
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish
dEQP-GLES[0-9]*.functional.flush_finish.*
dEQP-GLES2.functional.fbo.render.depth.*
# XXX: Why does this flake?
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_pos_y_pos_z_and_neg_x_neg_y_pos_z_and_pos_x_pos_y_neg_z
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgba4
dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgba4
dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.*
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.*
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgb
dEQP-GLES2.functional.fbo.render.shared_colorbuffer_clear.tex2d_rgba
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb5_a1
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgb5_a1_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.stencil_clear.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.npot_rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.npot_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.rbo_rgb5_a1_stencil_index8
dEQP-GLES2.functional.fbo.render.stencil.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.lifetime.attach.deleted_input.renderbuffer_framebuffer
dEQP-GLES2.functional.lifetime.attach.deleted_output.renderbuffer_framebuffer
dEQP-GLES2.functional.polygon_offset.fixed16_factor_0_slope
dEQP-GLES2.functional.polygon_offset.fixed16_factor_1_slope
dEQP-GLES2.functional.shaders.invariance.highp.loop_4
dEQP-GLES2.functional.shaders.matrix.mul.dynamic_highp_mat4_vec4_vertex
dEQP-GLES2.functional.shaders.matrix.mul.dynamic_highp_vec4_mat4_fragment
dEQP-GLES2.functional.shaders.operator.common_functions.smoothstep.mediump_vec3_vertex
dEQP-GLES2.functional.shaders.random.all_features.fragment.12
dEQP-GLES2.functional.shaders.random.all_features.fragment.37
dEQP-GLES2.functional.texture.units.2_units.mixed.1
dEQP-GLES2.functional.texture.units.2_units.mixed.3
dEQP-GLES2.functional.texture.units.2_units.only_2d.2
dEQP-GLES2.functional.texture.units.4_units.mixed.5
dEQP-GLES2.functional.texture.units.4_units.only_2d.0
dEQP-GLES2.functional.texture.units.8_units.only_cube.2
dEQP-GLES2.functional.texture.units.all_units.mixed.6
dEQP-GLES2.functional.texture.units.all_units.only_cube.4
dEQP-GLES2.functional.texture.units.all_units.only_cube.7
dEQP-GLES2.functional.texture.units.all_units.only_cube.8
# XXX: Causes irrecoverable GPU hangs when run in parallel with dEQP-GLES3.functional.transform_feedback.*
dEQP-GLES3.functional.rasterizer_discard.*
# XXX: Not completely implemented yet, behave flakily
dEQP-GLES3.functional.shaders.derivate.*

View File

@@ -0,0 +1,3 @@
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*

View File

@@ -0,0 +1,32 @@
# CTS bug (should be fixed in next version)
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.draw
dEQP-VK.api.buffer_marker.graphics.external_host_mem.bottom_of_pipe.memory_dep.draw
# SPIR-V->NIR issues.
dEQP-VK.glsl.builtin.precision.asin.highp.scalar
dEQP-VK.glsl.builtin.precision.asin.highp.vec2
dEQP-VK.glsl.builtin.precision.asin.highp.vec3
dEQP-VK.glsl.builtin.precision.asin.highp.vec4
# CTS bug (list of extensions not up-to-date).
dEQP-VK.info.device_extensions
# Interesting failures...
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_zero
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_zero
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_zero
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_zero
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_zero
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_max
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_min
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_zero

View File

@@ -0,0 +1,12 @@
# SPIR-V->NIR issues.
dEQP-VK.glsl.builtin.precision.asin.highp.scalar
dEQP-VK.glsl.builtin.precision.asin.highp.vec2
dEQP-VK.glsl.builtin.precision.asin.highp.vec3
dEQP-VK.glsl.builtin.precision.asin.highp.vec4
# CTS bug (list of extensions not up-to-date).
dEQP-VK.info.device_extensions
# ACO specific issues.
dEQP-VK.transform_feedback.simple.multistreams_1
dEQP-VK.transform_feedback.simple.multistreams_3

View File

@@ -0,0 +1,8 @@
# SPIR-V->NIR issues.
dEQP-VK.glsl.builtin.precision.asin.highp.scalar
dEQP-VK.glsl.builtin.precision.asin.highp.vec2
dEQP-VK.glsl.builtin.precision.asin.highp.vec3
dEQP-VK.glsl.builtin.precision.asin.highp.vec4
# CTS bug (list of extensions not up-to-date).
dEQP-VK.info.device_extensions

View File

@@ -0,0 +1,12 @@
# CTS bug (should be fixed in next version)
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.draw
dEQP-VK.api.buffer_marker.graphics.external_host_mem.bottom_of_pipe.memory_dep.draw
# SPIR-V->NIR issues.
dEQP-VK.glsl.builtin.precision.asin.highp.scalar
dEQP-VK.glsl.builtin.precision.asin.highp.vec2
dEQP-VK.glsl.builtin.precision.asin.highp.vec3
dEQP-VK.glsl.builtin.precision.asin.highp.vec4
# CTS bug (list of extensions not up-to-date).
dEQP-VK.info.device_extensions

View File

@@ -0,0 +1,31 @@
# Disable a TON of tests to keep the run around 5-10 minutes because my runner is
# slow.
dEQP-VK.api.*
dEQP-VK.binding_model.*
dEQP-VK.clipping.*
dEQP-VK.compute.*
dEQP-VK.conditional_rendering.*
dEQP-VK.descriptor_indexing.*
dEQP-VK.device_group.*
dEQP-VK.fragment_operations.*
dEQP-VK.fragment_shader_interlock.*
dEQP-VK.graphicsfuzz.*
dEQP-VK.image.*
dEQP-VK.imageless_framebuffer.*
dEQP-VK.info.*
dEQP-VK.memory.*
dEQP-VK.memory_model.*
dEQP-VK.multiview.*
dEQP-VK.pipeline.*
dEQP-VK.protected_memory.*
dEQP-VK.query_pool.*
dEQP-VK.robustness.*
dEQP-VK.sparse_resources.*
dEQP-VK.spirv_assembly.*
dEQP-VK.subgroups.*
dEQP-VK.synchronization.*
dEQP-VK.texture.*
dEQP-VK.transform_feedback.*
dEQP-VK.ubo.*
dEQP-VK.wsi.*
dEQP-VK.ycbcr.*

View File

@@ -0,0 +1,12 @@
# SPIR-V->NIR issues.
dEQP-VK.glsl.builtin.precision.asin.highp.scalar
dEQP-VK.glsl.builtin.precision.asin.highp.vec2
dEQP-VK.glsl.builtin.precision.asin.highp.vec3
dEQP-VK.glsl.builtin.precision.asin.highp.vec4
# CTS bug (list of extensions not up-to-date).
dEQP-VK.info.device_extensions
# ACO specific issues.
dEQP-VK.transform_feedback.simple.multistreams_1
dEQP-VK.transform_feedback.simple.multistreams_3

View File

@@ -1,49 +1,42 @@
#!/bin/bash
#!/bin/sh
set -ex
DEQP_OPTIONS=(--deqp-surface-width=256 --deqp-surface-height=256)
DEQP_OPTIONS+=(--deqp-surface-type=pbuffer)
DEQP_OPTIONS+=(--deqp-gl-config-name=rgba8888d24s8ms0)
DEQP_OPTIONS+=(--deqp-visibility=hidden)
DEQP_OPTIONS+=(--deqp-log-images=disable)
DEQP_OPTIONS+=(--deqp-crashhandler=enable)
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-surface-width=256 --deqp-surface-height=256"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-surface-type=pbuffer"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-gl-config-name=rgba8888d24s8ms0"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-visibility=hidden"
# It would be nice to be able to enable the watchdog, so that hangs in a test
# don't need to wait the full hour for the run to time out. However, some
# shaders end up taking long enough to compile
# (dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20 for example)
# that they'll sporadically trigger the watchdog.
#DEQP_OPTIONS+=(--deqp-watchdog=enable)
#DEQP_OPTIONS="$DEQP_OPTIONS --deqp-watchdog=enable"
if [ -z "$DEQP_VER" ]; then
echo 'DEQP_VER must be set to something like "gles2" or "gles31" for the test run'
echo 'DEQP_VER must be set to something like "gles2", "gles31" or "vk" for the test run'
exit 1
fi
if [ "$DEQP_VER" = "vk" ]; then
if [ -z "$VK_DRIVER" ]; then
echo 'VK_DRIVER must be to something like "radeon" or "intel" for the test run'
exit 1
fi
fi
if [ -z "$DEQP_SKIPS" ]; then
echo 'DEQP_SKIPS must be set to something like "deqp-default-skips.txt"'
exit 1
fi
# Prep the expected failure list
if [ -n "$DEQP_EXPECTED_FAILS" ]; then
export DEQP_EXPECTED_FAILS=`pwd`/artifacts/$DEQP_EXPECTED_FAILS
else
export DEQP_EXPECTED_FAILS=/tmp/expect-no-failures.txt
touch $DEQP_EXPECTED_FAILS
fi
sort < $DEQP_EXPECTED_FAILS > /tmp/expected-fails.txt
# Fix relative paths on inputs.
export DEQP_SKIPS=`pwd`/artifacts/$DEQP_SKIPS
# Be a good citizen on the shared runners.
export LP_NUM_THREADS=4
INSTALL=`pwd`/install
# Set up the driver environment.
export LD_LIBRARY_PATH=`pwd`/install/lib/
export EGL_PLATFORM=surfaceless
export VK_ICD_FILENAMES=`pwd`/install/share/vulkan/icd.d/"$VK_DRIVER"_icd.x86_64.json
# the runner was failing to look for libkms in /usr/local/lib for some reason
# I never figured out.
@@ -52,18 +45,14 @@ export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/lib
RESULTS=`pwd`/results
mkdir -p $RESULTS
cd /deqp/modules/$DEQP_VER
# Generate test case list file
cp /deqp/mustpass/$DEQP_VER-master.txt /tmp/case-list.txt
# Note: not using sorted input and comm, becuase I want to run the tests in
# the same order that dEQP would.
while read -r line; do
if echo "$line" | grep -q '^[^#]'; then
sed -i "/$line/d" /tmp/case-list.txt
fi
done < $DEQP_SKIPS
# Generate test case list file.
if [ "$DEQP_VER" = "vk" ]; then
cp /deqp/mustpass/vk-master.txt /tmp/case-list.txt
DEQP=/deqp/external/vulkancts/modules/vulkan/deqp-vk
else
cp /deqp/mustpass/$DEQP_VER-master.txt /tmp/case-list.txt
DEQP=/deqp/modules/$DEQP_VER/deqp-$DEQP_VER
fi
# If the job is parallel, take the corresponding fraction of the caselist.
# Note: N~M is a gnu sed extension to match every nth line (first line is #1).
@@ -71,66 +60,229 @@ if [ -n "$CI_NODE_INDEX" ]; then
sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" /tmp/case-list.txt
fi
if [ -n "$DEQP_CASELIST_FILTER" ]; then
sed -i "/$DEQP_CASELIST_FILTER/p" /tmp/case-list.txt
fi
if [ ! -s /tmp/case-list.txt ]; then
echo "Caselist generation failed"
exit 1
fi
# Cannot use tee because dash doesn't have pipefail
touch /tmp/result.txt
tail -f /tmp/result.txt &
if [ -n "$DEQP_EXPECTED_FAILS" ]; then
XFAIL="--xfail-list $INSTALL/$DEQP_EXPECTED_FAILS"
fi
./deqp-$DEQP_VER "${DEQP_OPTIONS[@]}" --deqp-log-filename=$RESULTS/results.qpa --deqp-caselist-file=/tmp/case-list.txt >> /tmp/result.txt
set +e
if [ -n "$DEQP_PARALLEL" ]; then
JOB="--job $DEQP_PARALLEL"
fi
run_cts() {
deqp=$1
caselist=$2
output=$3
deqp-runner \
--deqp $deqp \
--output $output \
--caselist $caselist \
--exclude-list $INSTALL/$DEQP_SKIPS \
--compact-display false \
$XFAIL \
$JOB \
--allow-flakes true \
$DEQP_RUNNER_OPTIONS \
-- \
$DEQP_OPTIONS
}
report_flakes() {
if [ -z "$FLAKES_CHANNEL" ]; then
return 0
fi
flakes=$1
bot="$CI_RUNNER_DESCRIPTION-$CI_PIPELINE_ID"
channel="$FLAKES_CHANNEL"
(
echo NICK $bot
echo USER $bot unused unused :Gitlab CI Notifier
sleep 10
echo "JOIN $channel"
sleep 1
desc="Flakes detected in job: $CI_JOB_URL on $CI_RUNNER_DESCRIPTION"
if [ -n "CI_MERGE_REQUEST_SOURCE_BRANCH_NAME" ]; then
desc="$desc on branch $CI_MERGE_REQUEST_SOURCE_BRANCH_NAME ($CI_MERGE_REQUEST_TITLE)"
fi
echo "PRIVMSG $channel :$desc"
for flake in `cat $flakes`; do
echo "PRIVMSG $channel :$flake"
done
echo "PRIVMSG $channel :See $CI_JOB_URL/artifacts/browse/results/"
echo "QUIT"
) | nc irc.freenode.net 6667 > /dev/null
}
extract_xml_result() {
testcase=$1
shift 1
qpas=$*
start="#beginTestCaseResult $testcase"
for qpa in $qpas; do
while IFS= read -r line; do
if [ "$line" = "$start" ]; then
dst="$testcase.qpa"
echo "#beginSession" > $dst
echo $line >> $dst
while IFS= read -r line; do
if [ "$line" = "#endTestCaseResult" ]; then
echo $line >> $dst
echo "#endSession" >> $dst
/deqp/executor/testlog-to-xml $dst "$RESULTS/$testcase$DEQP_RUN_SUFFIX.xml"
# copy the stylesheets here so they only end up in artifacts
# if we have one or more result xml in artifacts
cp /deqp/testlog.css "$RESULTS/"
cp /deqp/testlog.xsl "$RESULTS/"
return 0
fi
echo $line >> $dst
done
return 1
fi
done < $qpa
done
}
extract_xml_results() {
qpas=$*
while IFS= read -r testcase; do
testcase=${testcase%,*}
extract_xml_result $testcase $qpas
done
}
# Generate junit results
generate_junit() {
results=$1
echo "<?xml version=\"1.0\" encoding=\"utf-8\"?>"
echo "<testsuites>"
echo "<testsuite name=\"$DEQP_VER-$CI_NODE_INDEX\">"
while read line; do
testcase=${line%,*}
result=${line#*,}
# avoid counting Skip's in the # of tests:
if [ "$result" = "Skip" ]; then
continue;
fi
echo "<testcase name=\"$testcase\">"
if [ "$result" != "Pass" ]; then
echo "<failure type=\"$result\">"
echo "$result: See $CI_JOB_URL/artifacts/results/$testcase.xml"
echo "</failure>"
fi
echo "</testcase>"
done < $results
echo "</testsuite>"
echo "</testsuites>"
}
parse_renderer() {
RENDERER=`grep -A1 TestCaseResult.\*info.renderer $RESULTS/deqp-info.qpa | grep '<Text' | sed 's|.*<Text>||g' | sed 's|</Text>||g'`
VERSION=`grep -A1 TestCaseResult.\*info.version $RESULTS/deqp-info.qpa | grep '<Text' | sed 's|.*<Text>||g' | sed 's|</Text>||g'`
echo "Renderer: $RENDERER"
echo "Version: $VERSION "
if ! echo $RENDERER | grep -q $DEQP_EXPECTED_RENDERER; then
echo "Expected GL_RENDERER $DEQP_EXPECTED_RENDERER"
exit 1
fi
}
check_renderer() {
echo "Capturing renderer info for driver sanity checks"
# If you're having trouble loading your driver, uncommenting this may help
# debug.
# export EGL_LOG_LEVEL=debug
VERSION=`echo $DEQP_VER | tr '[a-z]' '[A-Z]'`
$DEQP $DEQP_OPTIONS --deqp-case=dEQP-$VERSION.info.\* --deqp-log-filename=$RESULTS/deqp-info.qpa
parse_renderer
}
# wrapper to supress +x to avoid spamming the log
quiet() {
set +x
"$@"
set -x
}
if [ "$GALLIUM_DRIVER" = "virpipe" ]; then
# deqp is to use virpipe, and virgl_test_server llvmpipe
export GALLIUM_DRIVER="$GALLIUM_DRIVER"
GALLIUM_DRIVER=llvmpipe \
GALLIVM_PERF="nopt,no_filter_hacks" \
VTEST_USE_EGL_SURFACELESS=1 \
VTEST_USE_GLES=1 \
virgl_test_server >$RESULTS/vtest-log.txt 2>&1 &
sleep 1
fi
if [ $DEQP_VER != vk ]; then
quiet check_renderer
fi
RESULTSFILE=$RESULTS/cts-runner-results$DEQP_RUN_SUFFIX.txt
UNEXPECTED_RESULTSFILE=$RESULTS/cts-runner-unexpected-results$DEQP_RUN_SUFFIX.txt
FLAKESFILE=$RESULTS/cts-runner-flakes$DEQP_RUN_SUFFIX.txt
run_cts $DEQP /tmp/case-list.txt $RESULTSFILE
DEQP_EXITCODE=$?
sed -ne \
'/StatusCode="Fail"/{x;p}; s/#beginTestCaseResult //; T; h' \
$RESULTS/results.qpa \
> /tmp/unsorted-fails.txt
# junit is disabled, because it overloads gitlab.freedesktop.org to parse it.
#quiet generate_junit $RESULTSFILE > $RESULTS/results.xml
# Scrape out the renderer that the test run used, so we can validate that the
# right driver was used.
if grep -q "dEQP-.*.info.renderer" /tmp/case-list.txt; then
# This is an ugly dependency on the .qpa format: Print 3 lines after the
# match, which happens to contain the result.
RENDERER=`sed -n '/#beginTestCaseResult dEQP-.*.info.renderer/{n;n;n;p}' $RESULTS/results.qpa | sed -n -E "s|<Text>(.*)</Text>|\1|p"`
if [ $DEQP_EXITCODE -ne 0 ]; then
# preserve caselist files in case of failures:
cp /tmp/deqp_runner.*.txt $RESULTS/
egrep -v ",Pass|,Skip|,ExpectedFail" $RESULTSFILE > $UNEXPECTED_RESULTSFILE.txt
echo "GL_RENDERER for this test run: $RENDERER"
if [ -z "$DEQP_NO_SAVE_RESULTS" ]; then
echo "Some unexpected results found (see cts-runner-results.txt in artifacts for full results):"
head -n 50 $UNEXPECTED_RESULTSFILE.txt
if [ -n "$DEQP_RENDERER_MATCH" ]; then
echo $RENDERER | grep -q $DEQP_RENDERER_MATCH > /dev/null
# Save the logs for up to the first 50 unexpected results:
head -n 50 $UNEXPECTED_RESULTSFILE.txt | quiet extract_xml_results /tmp/*.qpa
else
echo "Unexpected results found:"
cat $UNEXPECTED_RESULTSFILE.txt
fi
count=`cat $UNEXPECTED_RESULTSFILE.txt | wc -l`
# Re-run fails to detect flakes. But use a small threshold, if
# something was fundamentally broken, we don't want to re-run
# the entire caselist
else
grep ",Flake" $RESULTSFILE > $FLAKESFILE
count=`cat $FLAKESFILE | wc -l`
if [ $count -gt 0 ]; then
echo "Some flakes found (see cts-runner-flakes.txt in artifacts for full results):"
head -n 50 $FLAKESFILE
if [ -z "$DEQP_NO_SAVE_RESULTS" ]; then
# Save the logs for up to the first 50 flakes:
head -n 50 $FLAKESFILE | quiet extract_xml_results /tmp/*.qpa
fi
# Report the flakes to IRC channel for monitoring (if configured):
quiet report_flakes $FLAKESFILE
else
# no flakes, so clean-up:
rm $FLAKESFILE
fi
fi
if grep -q "dEQP-.*.info.version" /tmp/case-list.txt; then
# This is an ugly dependency on the .qpa format: Print 3 lines after the
# match, which happens to contain the result.
VERSION=`sed -n '/#beginTestCaseResult dEQP-.*.info.version/{n;n;n;p}' $RESULTS/results.qpa | sed -n -E "s|<Text>(.*)</Text>|\1|p"`
echo "Driver version tested: $VERSION"
fi
if [ $DEQP_EXITCODE -ne 0 ]; then
exit $DEQP_EXITCODE
fi
sort < /tmp/unsorted-fails.txt > $RESULTS/fails.txt
comm -23 $RESULTS/fails.txt /tmp/expected-fails.txt > /tmp/new-fails.txt
if [ -s /tmp/new-fails.txt ]; then
echo "Unexpected failures:"
cat /tmp/new-fails.txt
exit 1
else
echo "No new failures"
fi
sort /tmp/case-list.txt > /tmp/sorted-case-list.txt
comm -12 /tmp/sorted-case-list.txt /tmp/expected-fails.txt > /tmp/expected-fails-in-caselist.txt
comm -13 $RESULTS/fails.txt /tmp/expected-fails-in-caselist.txt > /tmp/new-passes.txt
if [ -s /tmp/new-passes.txt ]; then
echo "Unexpected passes, please update $DEQP_EXPECTED_FAILS (or add flaky tests to $DEQP_SKIPS):"
cat /tmp/new-passes.txt
exit 1
else
echo "No new passes"
fi
exit $DEQP_EXITCODE

View File

@@ -443,3 +443,401 @@ dEQP-GLES3.functional.texture.wrap.astc_8x8_srgb.repeat_repeat_linear_divisible
dEQP-GLES3.functional.texture.wrap.astc_8x8_srgb.repeat_repeat_linear_not_divisible
dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads1
dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads256
dEQP-GLES31.functional.debug.error_filters.case_29
dEQP-GLES31.functional.debug.negative_coverage.callbacks.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.blit_framebuffer_multisample
dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES31.functional.debug.negative_coverage.log.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.line_loop.instanced_attributes
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.0
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.1
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.10
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.11
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.12
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.14
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.16
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.17
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.19
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.2
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.3
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.4
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.5
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.6
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.7
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.8
dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.9
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.0
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.14
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.15
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.16
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.17
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.19
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.2
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.4
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.5
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.7
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.9
dEQP-GLES31.functional.draw_indirect.draw_arrays_indirect.line_strip.multiple_attributes
dEQP-GLES31.functional.fbo.no_attachments.interaction.17x512ms4_default_16x16ms2
dEQP-GLES31.functional.fbo.no_attachments.interaction.1x1ms0_default_2048x2048ms4
dEQP-GLES31.functional.fbo.no_attachments.interaction.2048x2048ms4_default_1x1ms0
dEQP-GLES31.functional.fbo.no_attachments.interaction.256x256ms0_default_512x512ms2
dEQP-GLES31.functional.fbo.no_attachments.interaction.256x256ms2_default_128x512ms0
dEQP-GLES31.functional.fbo.no_attachments.multisample.samples2
dEQP-GLES31.functional.fbo.no_attachments.multisample.samples3
dEQP-GLES31.functional.fbo.no_attachments.multisample.samples4
dEQP-GLES31.functional.fbo.no_attachments.random.1
dEQP-GLES31.functional.fbo.no_attachments.random.11
dEQP-GLES31.functional.fbo.no_attachments.random.14
dEQP-GLES31.functional.fbo.no_attachments.random.15
dEQP-GLES31.functional.fbo.no_attachments.random.4
dEQP-GLES31.functional.fbo.no_attachments.random.9
dEQP-GLES31.functional.geometry_shading.query.primitives_generated_amplification
dEQP-GLES31.functional.geometry_shading.query.primitives_generated_instanced
dEQP-GLES31.functional.geometry_shading.query.primitives_generated_no_amplification
dEQP-GLES31.functional.geometry_shading.query.primitives_generated_no_geometry
dEQP-GLES31.functional.geometry_shading.query.primitives_generated_partial_primitives
dEQP-GLES31.functional.image_load_store.early_fragment_tests.early_fragment_tests_stencil
dEQP-GLES31.functional.image_load_store.early_fragment_tests.early_fragment_tests_stencil_fbo
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_geometry
dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getfloat
dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getinteger
dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getinteger64
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_format_float
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_format_integer
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_format_pure_int
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_format_pure_uint
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_levels_float
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_levels_integer
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_levels_pure_int
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_levels_pure_uint
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_format_float
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_format_integer
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_format_pure_int
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_format_pure_uint
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_levels_float
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_levels_integer
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_levels_pure_int
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_levels_pure_uint
dEQP-GLES31.functional.texture.border_clamp.depth_compare_mode.depth32f_stencil8.linear_size_npot
dEQP-GLES31.functional.texture.border_clamp.depth_compare_mode.depth32f_stencil8.linear_size_pot
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_linear_clamp_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_linear_mirror_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_linear_repeat_clamp
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_linear_repeat_mirror
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_linear_repeat_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_linear_clamp_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_linear_mirror_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_linear_repeat_clamp
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_linear_repeat_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_nearest_clamp_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_nearest_mirror_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_nearest_repeat_clamp
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_linear_nearest_repeat_mirror
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_linear_clamp_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_linear_mirror_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_linear_repeat_clamp
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_linear_repeat_mirror
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_nearest_repeat_clamp
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_nearest_repeat_mirror
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_nearest_nearest_repeat_repeat
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_nearest_repeat_mirror
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb10_a2_linear_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb10_a2_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb10_a2_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb10_a2_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb565_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb565_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb5_a1_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb5_a1_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb9_e5_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgb9_e5_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba16f_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba16f_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba4_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba4_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba8_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba8_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba8_snorm_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.rgba8_snorm_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.srgb8_alpha8_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.formats.srgb8_alpha8_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.128x128x12_linear
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.128x128x12_linear_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.128x128x12_linear_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.128x128x12_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.128x128x12_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.63x63x18_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.64x64x12_nearest_mipmap_linear
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.64x64x12_nearest_mipmap_nearest
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.8x8x6_nearest
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.2d.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.2d_array.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8.no_corners.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8.no_corners.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8.no_corners.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.no_corners.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.no_corners.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.no_corners.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.no_corners.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.no_corners.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.no_corners.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.basic.cube.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.filter_mode.min_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.filter_mode.min_linear_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.filter_mode.min_linear_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.filter_mode.min_nearest_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.filter_mode.min_nearest_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.filter_mode.min_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.filter_mode.min_linear_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.filter_mode.min_linear_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.filter_mode.min_nearest_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.filter_mode.min_nearest_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.filter_mode.min_nearest_mipmap_nearest_mag_nearest
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.filter_mode.min_nearest_mipmap_nearest_mag_nearest
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.filter_mode.min_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.filter_mode.min_linear_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.filter_mode.min_linear_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.filter_mode.min_nearest_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.filter_mode.min_nearest_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.filter_mode.min_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.filter_mode.min_linear_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.filter_mode.min_linear_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.filter_mode.min_nearest_mipmap_linear_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.filter_mode.min_nearest_mipmap_nearest_mag_linear
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.filter_mode.min_nearest_mipmap_nearest_mag_nearest
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.base_level.level_1
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.base_level.level_2
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.filter_mode.min_nearest_mipmap_nearest_mag_nearest
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.red_green_blue_alpha
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8i.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d.rgba8ui.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_greater.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_less.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8i.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_npot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_npot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_npot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_pot.clamp_to_edge_repeat
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_pot.mirrored_repeat_clamp_to_edge
dEQP-GLES31.functional.texture.gather.offset_dynamic.min_required_offset.2d_array.rgba8ui.size_pot.repeat_mirrored_repeat
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue
dEQP-GLES31.functional.texture.gather.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_and_sample_coverage_and_alpha_to_coverage
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_non_effective_bits
dEQP-GLES31.functional.texture.multisample.samples_1.sample_mask_only

View File

@@ -0,0 +1,19 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance.*
dEQP-GLES[0-9]*.stress.*
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish.*
# Random failures
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_color_mask_buffer_color_mask
dEQP-GLES31.functional.fbo.no_attachments.maximums.all
dEQP-GLES31.functional.fbo.no_attachments.maximums.size
dEQP-GLES31.functional.geometry_shading.input.basic_primitive.points
dEQP-GLES31.functional.shaders.builtin_functions.*geometry
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.geometry.usampler3d
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.dynamically_uniform.geometry.sampler2darray

View File

@@ -0,0 +1,720 @@
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES2.functional.clipping.point.wide_point_clip
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_center
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_corner
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_neg_y_neg_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_pos_y_pos_z_and_neg_x_neg_y_neg_z
dEQP-GLES2.functional.draw.random.10
dEQP-GLES2.functional.draw.random.42
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.depth.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
dEQP-GLES2.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide
dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_center
dEQP-GLES3.functional.clipping.triangle_vertex.clip_two.clip_neg_y_neg_z_and_neg_x_neg_y_pos_z
dEQP-GLES3.functional.clipping.triangle_vertex.clip_two.clip_pos_y_pos_z_and_neg_x_neg_y_neg_z
dEQP-GLES3.functional.draw.random.124
dEQP-GLES3.functional.draw.random.174
dEQP-GLES3.functional.draw.random.31
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_x
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_dst_y
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_dst_x
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth_component16
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_color
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_depth_stencil
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_depth
dEQP-GLES3.functional.fbo.msaa.2_samples.depth_component16
dEQP-GLES3.functional.fbo.msaa.2_samples.r16f
dEQP-GLES3.functional.fbo.msaa.2_samples.rgb565
dEQP-GLES3.functional.fbo.msaa.2_samples.rgba4
dEQP-GLES3.functional.fbo.msaa.2_samples.rgba8
dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
dEQP-GLES3.functional.fbo.msaa.4_samples.depth24_stencil8
dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component24
dEQP-GLES3.functional.fbo.msaa.4_samples.r11f_g11f_b10f
dEQP-GLES3.functional.fbo.msaa.4_samples.r8
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb10_a2
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb8
dEQP-GLES3.functional.multisample.fbo_max_samples.proportionality_sample_coverage_inverted
dEQP-GLES3.functional.multisample.fbo_max_samples.sample_coverage_invert
dEQP-GLES3.functional.negative_api.buffer.blit_framebuffer_multisample
dEQP-GLES3.functional.negative_api.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES3.functional.polygon_offset.default_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
dEQP-GLES3.functional.polygon_offset.float32_displacement_with_units
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.fbo.texture_2d.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.interpolation.basic.line_loop_wide
dEQP-GLES3.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.fastest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.fastest.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.fastest.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa2.float_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa2.vec2_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa2.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.nicest.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.nicest.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.texture.msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.fwidth.texture.msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.fwidth.texture.msaa4.vec4_highp
dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64
dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads1
dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.unsigned_int.components2_vec2_quads256
dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.unsigned_int.components2_vec3_quads256
dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.unsigned_int.components2_vec4_quads256
dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.unsigned_int.components4_vec2_quads1
dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.unsigned_int.components4_vec4_quads1
dEQP-GLES31.functional.atomic_counter.dec.1_counter_100_calls_1_thread
dEQP-GLES31.functional.atomic_counter.dec.8_counters_5_calls_1_thread
dEQP-GLES31.functional.atomic_counter.dec_branch.4_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.get.1_counter_100_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get.8_counters_5_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get_branch.4_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.get_dec.1_counter_100_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get_dec.8_counters_5_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get_dec_branch.4_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.get_inc.1_counter_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.get_inc.4_counters_5_calls_10_threads
dEQP-GLES31.functional.atomic_counter.get_inc_branch.1_counter_1_call_5000_threads
dEQP-GLES31.functional.atomic_counter.get_inc_branch.8_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.get_inc_dec.1_counter_100_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get_inc_dec.8_counters_5_calls_1_thread
dEQP-GLES31.functional.atomic_counter.get_inc_dec_branch.4_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.inc.1_counter_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.inc.4_counters_5_calls_10_threads
dEQP-GLES31.functional.atomic_counter.inc_branch.1_counter_1_call_5000_threads
dEQP-GLES31.functional.atomic_counter.inc_branch.8_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.inc_dec.1_counter_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.inc_dec.4_counters_5_calls_10_threads
dEQP-GLES31.functional.atomic_counter.inc_dec_branch.1_counter_1_call_5000_threads
dEQP-GLES31.functional.atomic_counter.inc_dec_branch.8_counters_1_call_10_threads
dEQP-GLES31.functional.atomic_counter.layout.default_offset_set.get_dec.8_counters_5_calls_1_thread
dEQP-GLES31.functional.atomic_counter.layout.first_offset_set.inc_dec.8_counters_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.layout.reset_default_offset.get_dec.8_counters_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.layout.reverse_offset.get_inc.8_counters_1_call_1_thread
dEQP-GLES31.functional.atomic_counter.layout.reverse_offset.inc_dec.8_counters_5_calls_1_thread
dEQP-GLES31.functional.compute.basic.copy_ssbo_to_image_small
dEQP-GLES31.functional.compute.basic.shared_var_single_invocation
dEQP-GLES31.functional.compute.basic.ssbo_unsized_arr_multiple_groups
dEQP-GLES31.functional.compute.basic.ubo_to_ssbo_single_invocation
dEQP-GLES31.functional.compute.indirect_dispatch.gen_in_compute.large_offset_multiple_invocations
dEQP-GLES31.functional.compute.indirect_dispatch.upload_buffer.large_offset
dEQP-GLES31.functional.compute.shared_var.atomic.add.mediump_uint
dEQP-GLES31.functional.compute.shared_var.atomic.and.highp_uint
dEQP-GLES31.functional.compute.shared_var.atomic.compswap.lowp_uint
dEQP-GLES31.functional.compute.shared_var.atomic.max.lowp_uint
dEQP-GLES31.functional.compute.shared_var.atomic.xor.mediump_uint
dEQP-GLES31.functional.compute.shared_var.basic_type.float_lowp
dEQP-GLES31.functional.compute.shared_var.basic_type.int_mediump
dEQP-GLES31.functional.compute.shared_var.basic_type.ivec4_highp
dEQP-GLES31.functional.compute.shared_var.basic_type.mat2x4_highp
dEQP-GLES31.functional.compute.shared_var.basic_type.mat4x2_lowp
dEQP-GLES31.functional.compute.shared_var.basic_type.uvec4_lowp
dEQP-GLES31.functional.compute.shared_var.basic_type.vec4_mediump
dEQP-GLES31.functional.compute.shared_var.work_group_size.float_1_1_64
dEQP-GLES31.functional.compute.shared_var.work_group_size.vec4_13_2_4
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_10x10_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_10x5_khr.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_10x6_khr.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_12x10_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_12x12_khr.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_5x4_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_5x5_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_6x5_khr.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_6x6_khr.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_8x6_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_8x8_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_10x5_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_10x6_khr.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_10x8_khr.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_12x10_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_12x12_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_4x4_khr.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_10x10_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_10x10_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_10x6_khr_rgba32f.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_10x8_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_10x8_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_12x10_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_4x4_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_4x4_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x5_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x5_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x6_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x6_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x8_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_10x10_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_10x10_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_10x5_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_10x8_khr_rgba32f.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_12x10_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_12x10_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_12x12_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_4x4_khr_rgba32f.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.cubemap_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_array_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_array_to_texture3d
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_to_texture3d
dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_combined_grid_200x200_drawcount_8
dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawarrays_separate_grid_200x200_drawcount_800
dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_combined_grid_1000x1000_drawcount_5000
dEQP-GLES31.functional.draw_indirect.compute_interop.large.drawelements_separate_grid_200x200_drawcount_1
dEQP-GLES31.functional.draw_indirect.compute_interop.separate.drawelements_compute_data_and_indices
dEQP-GLES31.functional.fbo.no_attachments.interaction.127x127ms0_default_129x129ms0
dEQP-GLES31.functional.fbo.no_attachments.npot_size.15x511
dEQP-GLES31.functional.fbo.no_attachments.npot_size.65x65
dEQP-GLES31.functional.fbo.no_attachments.random.0
dEQP-GLES31.functional.image_load_store.2d.atomic.comp_swap_r32ui_result
dEQP-GLES31.functional.image_load_store.2d.atomic.max_r32ui_result
dEQP-GLES31.functional.image_load_store.2d.atomic.or_r32i_return_value
dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.r32f_r32i
dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.r32i_rgba8ui
dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba32i_rgba32ui
dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba8_rgba8_snorm
dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba8ui_r32i
dEQP-GLES31.functional.image_load_store.2d.image_size.readonly_7x1
dEQP-GLES31.functional.image_load_store.2d.load_store.rgba8i
dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i
dEQP-GLES31.functional.image_load_store.2d.store.r32f
dEQP-GLES31.functional.image_load_store.2d.store.rgba8_snorm
dEQP-GLES31.functional.image_load_store.2d_array.atomic.exchange_r32ui_return_value
dEQP-GLES31.functional.image_load_store.2d_array.atomic.min_r32ui_return_value
dEQP-GLES31.functional.image_load_store.2d_array.atomic.or_r32i_result
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.r32f_rgba8i
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.r32i_r32f
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.rgba32i_rgba32f
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.rgba8_r32i
dEQP-GLES31.functional.image_load_store.2d_array.format_reinterpret.rgba8ui_rgba8i
dEQP-GLES31.functional.image_load_store.2d_array.image_size.readonly_1x1x1
dEQP-GLES31.functional.image_load_store.2d_array.load_store.r32i_single_layer
dEQP-GLES31.functional.image_load_store.2d_array.load_store.rgba32f_single_layer
dEQP-GLES31.functional.image_load_store.2d_array.load_store.rgba8ui_single_layer
dEQP-GLES31.functional.image_load_store.2d_array.qualifiers.volatile_r32ui
dEQP-GLES31.functional.image_load_store.2d_array.store.rgba16i_single_layer
dEQP-GLES31.functional.image_load_store.2d_array.store.rgba32ui_single_layer
dEQP-GLES31.functional.image_load_store.3d.atomic.add_r32ui_result
dEQP-GLES31.functional.image_load_store.3d.atomic.max_r32i_return_value
dEQP-GLES31.functional.image_load_store.3d.atomic.xor_r32ui_result
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.r32ui_r32i
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.rgba16f_rgba16i
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.rgba16ui_rgba16i
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.rgba8_rgba8ui
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.rgba8_snorm_rgba8
dEQP-GLES31.functional.image_load_store.3d.format_reinterpret.rgba8i_r32i
dEQP-GLES31.functional.image_load_store.3d.image_size.readonly_writeonly_12x34x56
dEQP-GLES31.functional.image_load_store.3d.load_store.rgba16ui
dEQP-GLES31.functional.image_load_store.3d.load_store.rgba8i
dEQP-GLES31.functional.image_load_store.3d.qualifiers.coherent_r32f
dEQP-GLES31.functional.image_load_store.3d.store.r32f
dEQP-GLES31.functional.image_load_store.3d.store.rgba32i
dEQP-GLES31.functional.image_load_store.3d.store.rgba8_snorm
dEQP-GLES31.functional.image_load_store.cube.atomic.and_r32ui_return_value
dEQP-GLES31.functional.image_load_store.cube.atomic.exchange_r32i_result
dEQP-GLES31.functional.image_load_store.cube.atomic.min_r32i_result
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.r32i_rgba8
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.r32ui_r32f
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.rgba32f_rgba32ui
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.rgba32ui_rgba32f
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.rgba8_snorm_r32ui
dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.rgba8i_r32f
dEQP-GLES31.functional.image_load_store.cube.image_size.writeonly_1x1
dEQP-GLES31.functional.image_load_store.cube.load_store.r32f_single_layer
dEQP-GLES31.functional.image_load_store.cube.load_store.rgba32i_single_layer
dEQP-GLES31.functional.image_load_store.cube.load_store.rgba8_snorm_single_layer
dEQP-GLES31.functional.image_load_store.cube.store.r32i_single_layer
dEQP-GLES31.functional.image_load_store.cube.store.rgba32f_single_layer
dEQP-GLES31.functional.image_load_store.cube.store.rgba8ui_single_layer
dEQP-GLES31.functional.shaders.builtin_constants.core.max_combined_image_uniforms
dEQP-GLES31.functional.shaders.builtin_constants.core.max_draw_buffers
dEQP-GLES31.functional.shaders.builtin_constants.core.max_vertex_atomic_counter_buffers
dEQP-GLES31.functional.shaders.builtin_constants.tessellation_shader.max_tess_control_total_output_components
dEQP-GLES31.functional.shaders.builtin_constants.tessellation_shader.max_tess_evaluation_uniform_components
dEQP-GLES31.functional.shaders.builtin_functions.common.abs.int_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.abs.ivec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.abs.vec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.abs.vec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.ceil.vec2_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.ceil.vec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floatbitstoint.vec2_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floatbitstoint.vec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floatbitstouint.float_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floatbitstouint.vec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floatbitstouint.vec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floor.float_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floor.vec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.floor.vec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.fract.float_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.fract.vec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.fract.vec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.vec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.vec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.intbitstofloat.int_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.isinf.float_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.isinf.vec2_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.isinf.vec4_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.isnan.float_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.isnan.vec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.ldexp.float_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.ldexp.vec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.modf.vec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.modf.vec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.round.float_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.round.vec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.roundeven.float_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.roundeven.vec2_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.roundeven.vec4_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.sign.float_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.sign.ivec2_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.sign.ivec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.sign.vec2_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.sign.vec4_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.trunc.vec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.trunc.vec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.common.uintbitstofloat.uvec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.int_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.ivec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.uint_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.uvec2_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.uvec4_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.ivec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uint_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldextract.uvec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.int_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.ivec2_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.ivec4_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.uvec2_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.uvec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.int_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.ivec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.ivec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.uvec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.uvec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.ivec2_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.ivec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.uint_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.uvec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.uvec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.ivec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.ivec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.uint_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.uvec3_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.ivec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.uaddcarry.uint_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.uaddcarry.uvec3_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.uaddcarry.uvec4_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.uvec3_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.usubborrow.uvec2_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.integer.usubborrow.uvec4_lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.pack_unpack.packsnorm4x8_mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.pack_unpack.packunorm4x8_highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.precision.abs.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.acos.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.acosh.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.add.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.add.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.asin.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.asinh.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.atan2.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.atanh.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.ceil.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.ceil.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.clamp.mediump_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.cos.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.cosh.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.degrees.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.degrees.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.distance.lowp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.div.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.dot.highp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.dot.lowp_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.exp.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.exp2.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.exp2.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.faceforward.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.floor.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.fract.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.lowp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.mediump_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.inversesqrt.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.ldexp.highp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.length.mediump_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.log.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.log2.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.matrixcompmult.highp_compute.mat2
dEQP-GLES31.functional.shaders.builtin_functions.precision.matrixcompmult.lowp_compute.mat4
dEQP-GLES31.functional.shaders.builtin_functions.precision.max.lowp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.min.lowp_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.mix.mediump_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.mod.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.mul.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.normalize.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.outerproduct.highp_compute.mat3x2
dEQP-GLES31.functional.shaders.builtin_functions.precision.outerproduct.lowp_compute.mat2x3
dEQP-GLES31.functional.shaders.builtin_functions.precision.outerproduct.mediump_compute.mat2x4
dEQP-GLES31.functional.shaders.builtin_functions.precision.pow.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.radians.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.reflect.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.refract.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.refract.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.round.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.roundeven.lowp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.sign.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.sign.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.sin.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.sinh.highp_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.sinh.lowp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.smoothstep.lowp_compute.vec4
dEQP-GLES31.functional.shaders.builtin_functions.precision.sqrt.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.step.mediump_compute.vec2
dEQP-GLES31.functional.shaders.builtin_functions.precision.sub.highp_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.tan.mediump_compute.scalar
dEQP-GLES31.functional.shaders.builtin_functions.precision.tanh.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.precision.transpose.highp_compute.mat4x2
dEQP-GLES31.functional.shaders.builtin_functions.precision.transpose.lowp_compute.mat3
dEQP-GLES31.functional.shaders.builtin_functions.precision.transpose.mediump_compute.mat3x4
dEQP-GLES31.functional.shaders.builtin_functions.precision.trunc.mediump_compute.vec3
dEQP-GLES31.functional.shaders.builtin_functions.texture_size.samples_1_texture_2d_array
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findLSBMinusOne.mediump_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findMSBMinusOne.highp_tess_eval
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findMSBZero.lowp_tess_eval
dEQP-GLES31.functional.shaders.builtin_var.compute.global_invocation_id
dEQP-GLES31.functional.shaders.linkage.es31.tessellation.uniform.types.int
dEQP-GLES31.functional.shaders.linkage.es31.tessellation.uniform.types.vec4
dEQP-GLES31.functional.shaders.linkage.es31.tessellation.varying.rules.internal_superfluous_declaration
dEQP-GLES31.functional.shaders.linkage.es31.tessellation.varying.types.ivec2
dEQP-GLES31.functional.shaders.linkage.es31.tessellation.varying.types.mat2
dEQP-GLES31.functional.shaders.opaque_type_indexing.atomic_counter.const_literal_tessellation_evaluation
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.compute.samplercubeshadow
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.tessellation_control.isampler2d
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.tessellation_evaluation.isamplercube
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.compute.isampler2darray
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.tessellation_control.samplercube
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.tessellation_control.usampler2d
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.tessellation_evaluation.sampler2darray
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.tessellation_evaluation.usamplercube
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.const_expression_tessellation_evaluation
dEQP-GLES31.functional.ssbo.array_length.unsized_writeonly_array
dEQP-GLES31.functional.ssbo.atomic.add.mediump_uint
dEQP-GLES31.functional.ssbo.atomic.and.highp_uint
dEQP-GLES31.functional.ssbo.atomic.compswap.lowp_uint
dEQP-GLES31.functional.ssbo.atomic.max.lowp_uint
dEQP-GLES31.functional.ssbo.atomic.xor.mediump_uint
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.column_major_mat2
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.mat2x4
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.row_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.uint
dEQP-GLES31.functional.ssbo.layout.2_level_array.shared.column_major_mat3
dEQP-GLES31.functional.ssbo.layout.2_level_array.shared.mat3x2
dEQP-GLES31.functional.ssbo.layout.2_level_array.shared.row_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.2_level_array.shared.uvec4
dEQP-GLES31.functional.ssbo.layout.2_level_array.shared.vec2
dEQP-GLES31.functional.ssbo.layout.2_level_array.std140.bvec4
dEQP-GLES31.functional.ssbo.layout.2_level_array.std140.ivec2
dEQP-GLES31.functional.ssbo.layout.2_level_array.std140.mat2x3
dEQP-GLES31.functional.ssbo.layout.2_level_array.std140.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.2_level_array.std430.bool
dEQP-GLES31.functional.ssbo.layout.2_level_array.std430.column_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.2_level_array.std430.mat4
dEQP-GLES31.functional.ssbo.layout.2_level_array.std430.row_major_mat3x2
dEQP-GLES31.functional.ssbo.layout.2_level_array.std430.vec3
dEQP-GLES31.functional.ssbo.layout.2_level_unsized_struct_array.per_block_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.3_level_array.packed.column_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.3_level_array.packed.ivec3
dEQP-GLES31.functional.ssbo.layout.3_level_array.packed.mat2
dEQP-GLES31.functional.ssbo.layout.3_level_array.packed.row_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.3_level_array.shared.column_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.3_level_array.shared.mat3
dEQP-GLES31.functional.ssbo.layout.3_level_array.shared.row_major_mat2x4
dEQP-GLES31.functional.ssbo.layout.3_level_array.shared.uvec2
dEQP-GLES31.functional.ssbo.layout.3_level_array.std140.bvec2
dEQP-GLES31.functional.ssbo.layout.3_level_array.std140.column_major_mat3x2
dEQP-GLES31.functional.ssbo.layout.3_level_array.std140.row_major_mat4
dEQP-GLES31.functional.ssbo.layout.3_level_array.std140.vec4
dEQP-GLES31.functional.ssbo.layout.3_level_array.std430.column_major_mat2x4
dEQP-GLES31.functional.ssbo.layout.3_level_array.std430.float
dEQP-GLES31.functional.ssbo.layout.3_level_array.std430.mat4x3
dEQP-GLES31.functional.ssbo.layout.3_level_array.std430.row_major_mat3
dEQP-GLES31.functional.ssbo.layout.3_level_array.std430.uvec3
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.packed.bvec3
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.packed.column_major_mat4
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.packed.int
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.packed.mat3x4
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.shared.column_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.shared.ivec4
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.shared.mat4x2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.shared.row_major_mat2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std140.column_major_mat3
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std140.mat3x2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std140.row_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std140.uvec4
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std140.vec2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std430.column_major_mat2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std430.mat2x4
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std430.row_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.3_level_unsized_array.std430.uint
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.packed.column_major_mat2x4
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.packed.float
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.packed.mat4x3
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.packed.row_major_mat3
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.packed.uvec3
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.shared.bvec2
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.shared.column_major_mat3x2
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.shared.row_major_mat4
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.shared.vec4
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std140.column_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std140.ivec4
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std140.mat4x2
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std140.row_major_mat2
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std430.bvec3
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std430.column_major_mat4
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std430.int
dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std430.mat3x4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.packed.column_major_mat2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.packed.mat2x4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.packed.row_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.packed.uint
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.shared.column_major_mat3
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.shared.mat3x2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.shared.row_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.shared.uvec4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.shared.vec2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std140.bvec4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std140.ivec2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std140.mat2x3
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std140.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.bool
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.column_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.mat4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.row_major_mat3x2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.vec3
dEQP-GLES31.functional.ssbo.layout.multi_basic_types.single_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.multi_nested_struct.per_block_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.multi_nested_struct.single_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.12
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.2
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.22
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.32
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.42
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.12
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.2
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.22
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.32
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.42
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.12
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.2
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.22
dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.12
dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.2
dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.22
dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.7
dEQP-GLES31.functional.ssbo.layout.random.basic_types.17
dEQP-GLES31.functional.ssbo.layout.random.basic_types.7
dEQP-GLES31.functional.ssbo.layout.random.nested_structs.12
dEQP-GLES31.functional.ssbo.layout.random.nested_structs.2
dEQP-GLES31.functional.ssbo.layout.random.nested_structs.22
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.7
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.7
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_instance_arrays.12
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_instance_arrays.2
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_instance_arrays.22
dEQP-GLES31.functional.ssbo.layout.random.scalar_types.17
dEQP-GLES31.functional.ssbo.layout.random.scalar_types.7
dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.7
dEQP-GLES31.functional.ssbo.layout.random.vector_types.12
dEQP-GLES31.functional.ssbo.layout.random.vector_types.2
dEQP-GLES31.functional.ssbo.layout.random.vector_types.22
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.bool
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.column_major_mat4x3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.mat4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.row_major_mat3x2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.vec3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.bvec4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.ivec2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.column_major_mat4x2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.mat3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.row_major_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.uvec2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.column_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.ivec3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.row_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.bvec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.column_major_highp_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.column_major_lowp_mat4x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.highp_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.highp_vec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.lowp_ivec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.lowp_mat4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_uvec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.row_major_highp_mat4x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.row_major_lowp_mat3x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.row_major_mediump_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.bvec4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.column_major_lowp_mat4x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.column_major_mediump_mat4x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.highp_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.highp_uvec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.lowp_mat3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.lowp_vec4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.mediump_ivec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.mediump_mat4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.row_major_highp_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.row_major_lowp_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.shared.row_major_mediump_mat3x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.bvec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.column_major_highp_mat3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.column_major_mediump_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.highp_ivec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.highp_mat3x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.lowp_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.lowp_uvec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.mediump_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.mediump_vec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.row_major_highp_mat4x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.row_major_lowp_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.row_major_mediump_mat4x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.bool
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.column_major_highp_mat4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.column_major_lowp_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.column_major_mediump_mat3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.highp_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.highp_uint
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.lowp_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.lowp_vec3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.mediump_ivec2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.mediump_mat3x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_lowp_mat4x2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_mediump_mat4x3
dEQP-GLES31.functional.ssbo.layout.single_nested_struct.per_block_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct.single_buffer.std430_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct.per_block_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.unsized_nested_struct_array.per_block_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.unsized_struct_array.per_block_buffer.std430_instance_array
dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getinteger64
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.texture_immutable_format_pure_uint
dEQP-GLES31.functional.state_query.texture.texture_2d_multisample_array.texture_immutable_levels_integer
dEQP-GLES31.functional.synchronization.in_invocation.image_atomic_read_write
dEQP-GLES31.functional.synchronization.in_invocation.ssbo_atomic_read_write
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.image_multiple_unrelated_write_read_non_ordered
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_atomic_multiple_unrelated_write_read_ordered
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_overwrite
dEQP-GLES31.functional.synchronization.inter_call.without_memory_barrier.atomic_counter_dispatch_2_calls_32_invocations
dEQP-GLES31.functional.synchronization.inter_call.without_memory_barrier.ssbo_atomic_counter_mixed_dispatch_5_calls_32_invocations
dEQP-GLES31.functional.synchronization.inter_call.without_memory_barrier.ssbo_atomic_dispatch_100_calls_32k_invocations
dEQP-GLES31.functional.synchronization.inter_invocation.image_atomic_read_write
dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_read_write
dEQP-GLES31.functional.tessellation.common_edge.quads_fractional_odd_spacing
dEQP-GLES31.functional.tessellation.invariance.one_minus_tess_coord_component.isolines_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.one_minus_tess_coord_component.quads_fractional_odd_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.one_minus_tess_coord_component.triangles_fractional_even_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_index_independence.quads_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_index_independence.triangles_fractional_odd_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_fractional_even_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.quads_equal_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.quads_fractional_even_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.outer_triangle_set.triangles_equal_spacing
dEQP-GLES31.functional.tessellation.invariance.primitive_set.isolines_equal_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.primitive_set.isolines_fractional_even_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.primitive_set.quads_equal_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.primitive_set.triangles_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.tess_coord_component_range.isolines_equal_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.tess_coord_component_range.isolines_fractional_even_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.tess_coord_component_range.quads_equal_spacing_cw
dEQP-GLES31.functional.tessellation.invariance.tess_coord_component_range.triangles_fractional_odd_spacing_ccw
dEQP-GLES31.functional.tessellation.invariance.triangle_set.triangles_fractional_even_spacing
dEQP-GLES31.functional.tessellation.misc_draw.fill_overlap_quads_equal_spacing
dEQP-GLES31.functional.tessellation.primitive_discard.isolines_fractional_odd_spacing_cw
dEQP-GLES31.functional.tessellation.primitive_discard.quads_fractional_even_spacing_ccw
dEQP-GLES31.functional.tessellation.primitive_discard.triangles_equal_spacing_ccw
dEQP-GLES31.functional.tessellation.primitive_discard.triangles_fractional_even_spacing_cw
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_in_tes
dEQP-GLES31.functional.tessellation.tesscoord.isolines_fractional_even_spacing
dEQP-GLES31.functional.tessellation.user_defined_io.per_patch.vertex_io_array_size_implicit.isolines
dEQP-GLES31.functional.tessellation.user_defined_io.per_patch_array.vertex_io_array_size_shader_builtin.triangles
dEQP-GLES31.functional.tessellation.user_defined_io.per_patch_block.vertex_io_array_size_shader_builtin.quads
dEQP-GLES31.functional.tessellation.user_defined_io.per_patch_block_array.vertex_io_array_size_shader_builtin.isolines
dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex.vertex_io_array_size_query.quads_explicit_tcs_out_size
dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex.vertex_io_array_size_shader_builtin.triangles
dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.vertex_io_array_size_shader_builtin.isolines
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_float_depth

16
.gitlab-ci/fossilize-runner.sh Executable file
View File

@@ -0,0 +1,16 @@
#!/bin/sh
set -ex
if [ -z "$VK_DRIVER" ]; then
echo 'VK_DRIVER must be to something like "radeon" or "intel" for the test run'
exit 1
fi
INSTALL=`pwd`/install
# Set up the driver environment.
export LD_LIBRARY_PATH=`pwd`/install/lib/
export VK_ICD_FILENAMES=`pwd`/install/share/vulkan/icd.d/"$VK_DRIVER"_icd.x86_64.json
"$INSTALL/fossils/fossils.sh" "$INSTALL/fossils.yml"

6
.gitlab-ci/fossils.yml Normal file
View File

@@ -0,0 +1,6 @@
fossils-db:
repo: "https://gitlab.freedesktop.org/hakzsam/fossils-db"
commit: "59b11cd19e375c5871c512f73b1f8ecc33a5c417"
fossils:
- path: sascha-willems/database.foz

71
.gitlab-ci/fossils/fossils.sh Executable file
View File

@@ -0,0 +1,71 @@
#!/usr/bin/env bash
FOSSILS_SCRIPT_DIR="$(dirname "$(readlink -f "$0")")"
FOSSILS_YAML="$(readlink -f "$1")"
clone_fossils_db()
{
local repo="$1"
local commit="$2"
rm -rf fossils-db
git clone --no-checkout "$repo" fossils-db
(cd fossils-db; git reset "$commit" || git reset "origin/$commit")
}
query_fossils_yaml()
{
python3 "$FOSSILS_SCRIPT_DIR/query_fossils_yaml.py" \
--file "$FOSSILS_YAML" "$@"
}
create_clean_git()
{
rm -rf .clean_git
cp -R .git .clean_git
}
restore_clean_git()
{
rm -rf .git
cp -R .clean_git .git
}
fetch_fossil()
{
local fossil="${1//,/?}"
echo -n "[fetch_fossil] Fetching $1... "
local output=$(git lfs pull -I "$fossil" 2>&1)
local ret=0
if [[ $? -ne 0 || ! -f "$1" ]]; then
echo "ERROR"
echo "$output"
ret=1
else
echo "OK"
fi
restore_clean_git
return $ret
}
if [[ -n "$(query_fossils_yaml fossils_db_repo)" ]]; then
clone_fossils_db "$(query_fossils_yaml fossils_db_repo)" \
"$(query_fossils_yaml fossils_db_commit)"
cd fossils-db
else
echo "Warning: No fossils-db entry in $FOSSILS_YAML, assuming fossils-db is current directory"
fi
# During git operations various git objects get created which
# may take up significant space. Store a clean .git instance,
# which we restore after various git operations to keep our
# storage consumption low.
create_clean_git
for fossil in $(query_fossils_yaml fossils)
do
fetch_fossil "$fossil" || exit $?
fossilize-replay $fossil || exit $?
rm $fossil
done
exit $ret

View File

@@ -0,0 +1,69 @@
#!/usr/bin/python3
# Copyright (c) 2019 Collabora Ltd
# Copyright (c) 2020 Valve Corporation
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# SPDX-License-Identifier: MIT
import argparse
import yaml
def cmd_fossils_db_repo(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
print(y['fossils-db']['repo'])
def cmd_fossils_db_commit(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
print(y['fossils-db']['commit'])
def cmd_fossils(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
fossils = list(y['fossils'])
if len(fossils) == 0:
return
print('\n'.join((t['path'] for t in fossils)))
def main():
parser = argparse.ArgumentParser()
parser.add_argument('--file', required=True,
help='the name of the yaml file')
subparsers = parser.add_subparsers(help='sub-command help')
parser_fossils_db_repo = subparsers.add_parser('fossils_db_repo')
parser_fossils_db_repo.set_defaults(func=cmd_fossils_db_repo)
parser_fossils_db_commit = subparsers.add_parser('fossils_db_commit')
parser_fossils_db_commit.set_defaults(func=cmd_fossils_db_commit)
parser_fossils = subparsers.add_parser('fossils')
parser_fossils.set_defaults(func=cmd_fossils)
args = parser.parse_args()
args.func(args)
if __name__ == "__main__":
main()

View File

@@ -2,57 +2,44 @@
from jinja2 import Environment, FileSystemLoader
import argparse
device_types = {
"rk3288-veyron-jaq": {
"gpu_version": "panfrost-t760",
"boot_method": "depthcharge",
"lava_device_type": "rk3288-veyron-jaq",
"kernel_image_type": "",
},
"rk3399-gru-kevin": {
"gpu_version": "panfrost-t860",
"boot_method": "depthcharge",
"lava_device_type": "rk3399-gru-kevin",
"kernel_image_type": "",
},
"sun8i-h3-libretech-all-h3-cc": {
"gpu_version": "lima",
"boot_method": "u-boot",
"lava_device_type": "sun8i-h3-libretech-all-h3-cc",
"kernel_image_type": "type: zimage",
},
"meson-gxl-s905x-libretech-cc": {
"gpu_version": "lima",
"boot_method": "u-boot",
"lava_device_type": "meson-gxl-s905x-libretech-cc",
"kernel_image_type": "type: image",
},
}
import os
parser = argparse.ArgumentParser()
parser.add_argument("--template")
parser.add_argument("--pipeline-info")
parser.add_argument("--base-artifacts-url")
parser.add_argument("--arch")
parser.add_argument("--device-types", nargs="+")
parser.add_argument("--device-type")
parser.add_argument("--kernel-image-name")
parser.add_argument("--kernel-image-type", nargs='?', default="")
parser.add_argument("--gpu-version")
parser.add_argument("--boot-method")
parser.add_argument("--lava-tags", nargs='?', default="")
parser.add_argument("--env-vars", nargs='?', default="")
parser.add_argument("--deqp-version")
parser.add_argument("--arch")
parser.add_argument("--ci-node-index")
parser.add_argument("--ci-node-total")
args = parser.parse_args()
env = Environment(loader = FileSystemLoader('.'), trim_blocks=True, lstrip_blocks=True)
template = env.get_template(args.template)
env = Environment(loader = FileSystemLoader(os.path.dirname(args.template)), trim_blocks=True, lstrip_blocks=True)
template = env.get_template(os.path.basename(args.template))
for device_type in args.device_types:
values = {}
values['base_artifacts_url'] = args.base_artifacts_url
values['arch'] = args.arch
values['device_type'] = device_type
values['kernel_image_name'] = args.kernel_image_name
values['lava_device_type'] = device_types[device_type]['lava_device_type']
values['gpu_version'] = device_types[device_type]['gpu_version']
values['boot_method'] = device_types[device_type]['boot_method']
values['kernel_image_type'] = device_types[device_type]['kernel_image_type']
env_vars = "%s CI_NODE_INDEX=%s CI_NODE_TOTAL=%s" % (args.env_vars, args.ci_node_index, args.ci_node_total)
f = open('results/lava-deqp-%s.yml' % device_type, "w")
f.write(template.render(values))
f.close()
values = {}
values['pipeline_info'] = args.pipeline_info
values['base_artifacts_url'] = args.base_artifacts_url
values['device_type'] = args.device_type
values['kernel_image_name'] = args.kernel_image_name
values['kernel_image_type'] = args.kernel_image_type
values['gpu_version'] = args.gpu_version
values['boot_method'] = args.boot_method
values['tags'] = args.lava_tags
values['env_vars'] = env_vars
values['deqp_version'] = args.deqp_version
values['arch'] = args.arch
f = open('lava-deqp.yml', "w")
f.write(template.render(values))
f.close()

View File

@@ -1,187 +0,0 @@
#!/bin/bash
set -e
set -o xtrace
############### Install packages for building
dpkg --add-architecture ${DEBIAN_ARCH}
echo 'deb-src https://deb.debian.org/debian testing main' > /etc/apt/sources.list.d/deb-src.list
apt-get update
apt-get -y install ca-certificates
apt-get -y install --no-install-recommends \
crossbuild-essential-${DEBIAN_ARCH} \
meson \
g++ \
git \
ccache \
pkg-config \
python3-mako \
python-numpy \
python-six \
python-mako \
python3-pip \
python3-setuptools \
python3-six \
python3-wheel \
python3-jinja2 \
bison \
flex \
gettext \
cmake \
bc \
libssl-dev \
lqa \
csvkit \
curl \
unzip \
wget \
debootstrap \
procps \
qemu-user-static \
cpio \
clang-8 \
llvm-8 \
libclang-8-dev \
llvm-8-dev \
gdc-9 \
lld-8 \
nasm \
libegl1-mesa-dev \
\
libdrm-dev:${DEBIAN_ARCH} \
libx11-dev:${DEBIAN_ARCH} \
libxxf86vm-dev:${DEBIAN_ARCH} \
libexpat1-dev:${DEBIAN_ARCH} \
libsensors-dev:${DEBIAN_ARCH} \
libxfixes-dev:${DEBIAN_ARCH} \
libxdamage-dev:${DEBIAN_ARCH} \
libxext-dev:${DEBIAN_ARCH} \
x11proto-dev:${DEBIAN_ARCH} \
libx11-xcb-dev:${DEBIAN_ARCH} \
libxcb-dri2-0-dev:${DEBIAN_ARCH} \
libxcb-glx0-dev:${DEBIAN_ARCH} \
libxcb-xfixes0-dev:${DEBIAN_ARCH} \
libxcb-dri3-dev:${DEBIAN_ARCH} \
libxcb-present-dev:${DEBIAN_ARCH} \
libxcb-randr0-dev:${DEBIAN_ARCH} \
libxcb-sync-dev:${DEBIAN_ARCH} \
libxrandr-dev:${DEBIAN_ARCH} \
libxshmfence-dev:${DEBIAN_ARCH} \
libelf-dev:${DEBIAN_ARCH} \
zlib1g-dev:${DEBIAN_ARCH} \
libglvnd-core-dev:${DEBIAN_ARCH} \
libgles2-mesa-dev:${DEBIAN_ARCH} \
libegl1-mesa-dev:${DEBIAN_ARCH} \
libpng-dev:${DEBIAN_ARCH}
############### Install lavacli (remove after it's back into Debian testing)
mkdir -p lavacli
wget -qO- https://git.lavasoftware.org/lava/lavacli/-/archive/v0.9.8/lavacli-v0.9.8.tar.gz | tar -xz --strip-components=1 -C lavacli
pushd lavacli
python3 ./setup.py install
popd
############### Cross-build dEQP
mkdir -p /artifacts/rootfs/deqp
git config --global user.email "mesa@example.com"
git config --global user.name "Mesa CI"
# XXX: Use --depth 1 once we can drop the cherry-picks.
git clone \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b opengl-es-cts-3.2.5.1 \
/VK-GL-CTS
cd /VK-GL-CTS
# Fix surfaceless build
git cherry-pick -x 22f41e5e321c6dcd8569c4dad91bce89f06b3670
git cherry-pick -x 1daa8dff73161ea60ead965bd6c9f2a0a2165648
# surfaceless links against libkms and such despite not using it.
sed -i '/gbm/d' targets/surfaceless/surfaceless.cmake
sed -i '/libkms/d' targets/surfaceless/surfaceless.cmake
sed -i '/libgbm/d' targets/surfaceless/surfaceless.cmake
python3 external/fetch_sources.py
cd /artifacts/rootfs/deqp
cmake -G Ninja \
-DDEQP_TARGET=surfaceless \
-DCMAKE_BUILD_TYPE=Release \
-DCMAKE_C_COMPILER=${GCC_ARCH}-gcc \
-DCMAKE_CXX_COMPILER=${GCC_ARCH}-g++ \
/VK-GL-CTS
ninja
rm -rf /artifacts/rootfs/deqp/external
rm -rf /artifacts/rootfs/deqp/modules/gles31
rm -rf /artifacts/rootfs/deqp/modules/internal
rm -rf /artifacts/rootfs/deqp/executor
rm -rf /artifacts/rootfs/deqp/execserver
rm -rf /artifacts/rootfs/deqp/modules/egl
rm -rf /artifacts/rootfs/deqp/framework
find . -name CMakeFiles | xargs rm -rf
find . -name lib\*.a | xargs rm -rf
du -sh *
rm -rf /VK-GL-CTS-opengl-es-cts-3.2.5.0
############### Cross-build Volt dEQP runner
mkdir -p /battery
cd /battery
wget https://github.com/VoltLang/Battery/releases/download/v0.1.23/battery-0.1.23-x86_64-linux.tar.gz
tar xzvf battery-0.1.23-x86_64-linux.tar.gz
rm battery-0.1.23-x86_64-linux.tar.gz
mv battery /usr/local/bin
rm -rf /battery
mkdir -p /volt
cd /volt
mkdir -p Watt Volta dEQP
wget -qO- https://github.com/VoltLang/Watt/archive/v0.1.3.tar.gz | tar -xz --strip-components=1 -C ./Watt
wget -qO- https://github.com/VoltLang/Volta/archive/v0.1.3.tar.gz | tar -xz --strip-components=1 -C ./Volta
wget -qO- https://github.com/Wallbraker/dEQP/archive/v0.1.4.tar.gz | tar -xz --strip-components=1 -C ./dEQP
battery config --release --lto Volta Watt
battery build
battery config --arch ${VOLT_ARCH} --cmd-volta Volta/volta Volta/rt Watt dEQP
battery build
rm /usr/local/bin/battery
cp dEQP/deqp /artifacts/rootfs/deqp/deqp-volt
rm -rf /volt
############### Remove LLVM now, so the container image is smaller
apt-get -y remove \*llvm\*
############### Cross-build kernel
KERNEL_URL="https://gitlab.freedesktop.org/tomeu/linux/-/archive/panfrost-veyron-fix/linux-panfrost-veyron-fix.tar.gz"
export ARCH=${KERNEL_ARCH}
export CROSS_COMPILE="${GCC_ARCH}-"
mkdir -p /kernel
wget -qO- ${KERNEL_URL} | tar -xz --strip-components=1 -C /kernel
cd /kernel
./scripts/kconfig/merge_config.sh ${DEFCONFIG} /tmp/clone/.gitlab-ci/${KERNEL_ARCH}.config
make -j12 ${KERNEL_IMAGE_NAME} dtbs
cp arch/${KERNEL_ARCH}/boot/${KERNEL_IMAGE_NAME} /artifacts/.
cp ${DEVICE_TREES} /artifacts/.
rm -rf /kernel
############### Create rootfs
cp /tmp/clone/.gitlab-ci/create-rootfs.sh /artifacts/rootfs/.
mkdir -p /artifacts/rootfs/bin
cp /usr/bin/qemu-aarch64-static /artifacts/rootfs/bin
cp /usr/bin/qemu-arm-static /artifacts/rootfs/bin
set +e
debootstrap --variant=minbase --arch=${DEBIAN_ARCH} testing /artifacts/rootfs/ http://deb.debian.org/debian
cat /artifacts/rootfs/debootstrap/debootstrap.log
set -e
chroot /artifacts/rootfs sh /create-rootfs.sh
rm /artifacts/rootfs/bin/qemu-arm-static
rm /artifacts/rootfs/bin/qemu-aarch64-static
rm /artifacts/rootfs/create-rootfs.sh

View File

@@ -1,51 +0,0 @@
#!/bin/sh
GPU_VERSION="$1"
DEQP_OPTIONS="--deqp-surface-width=256 --deqp-surface-height=256"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-visibility=hidden"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-log-images=disable"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-watchdog=enable"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-crashhandler=enable"
DEQP_OPTIONS="$DEQP_OPTIONS --deqp-surface-type=pbuffer"
export LIBGL_DRIVERS_PATH=/mesa/lib/dri/
export LD_LIBRARY_PATH=/mesa/lib/
export MESA_GLES_VERSION_OVERRIDE=3.0
DEVFREQ_GOVERNOR=`echo /sys/devices/platform/*.gpu/devfreq/devfreq0/governor`
echo performance > $DEVFREQ_GOVERNOR
cd /deqp/modules/gles2
# Generate test case list file
./deqp-gles2 $DEQP_OPTIONS --deqp-runmode=stdout-caselist | grep "TEST: dEQP-GLES2" | cut -d ' ' -f 2 > /tmp/case-list.txt
# Note: not using sorted input and comm, becuase I want to run the tests in
# the same order that dEQP would.
while read -r line; do
if echo "$line" | grep -q '^[^#]'; then
sed -i "/$line/d" /tmp/case-list.txt
fi
done < /deqp/deqp-$GPU_VERSION-skips.txt
/deqp/deqp-volt --cts-build-dir=/deqp \
--threads=8 \
--test-names-file=/tmp/case-list.txt \
--results-file=/tmp/results.txt \
--no-passed-results \
--regression-file=/deqp/deqp-$GPU_VERSION-fails.txt \
--no-rerun-tests \
--print-regression \
--no-print-fail \
--no-print-quality \
--no-colour-term \
$DEQP_OPTIONS
if [ $? -ne 0 ]; then
echo "Regressions detected"
echo "deqp: fail"
else
echo "No regressions detected"
echo "deqp: pass"
fi

View File

@@ -1,5 +1,5 @@
job_name: mesa-deqp-{{ gpu_version }}
device_type: {{ lava_device_type }}
job_name: mesa-deqp-{{ deqp_version }}-{{ gpu_version }} {{ pipeline_info }}
device_type: {{ device_type }}
timeouts:
job:
minutes: 40
@@ -10,27 +10,54 @@ timeouts:
seconds: 30
priority: 75
visibility: public
{% if tags %}
{% set lavatags = tags.split(',') %}
tags:
{% for tag in lavatags %}
- {{ tag }}
{% endfor %}
{% endif %}
actions:
- deploy:
timeout:
minutes: 10
{% if boot_method == "fastboot" %}
{# fastboot has just one boot image with the dtb and rootfs packed in #}
to: fastboot
images:
boot:
url: {{ base_artifacts_url }}/{{ kernel_image_name }}
{% else %}
to: tftp
kernel:
url: {{ base_artifacts_url }}/{{ kernel_image_name }}
{% if kernel_image_type %}
{{ kernel_image_type }}
{% endif %}
ramdisk:
url: {{ base_artifacts_url }}/lava-rootfs-{{ arch }}.cpio.gz
compression: gz
dtb:
url: {{ base_artifacts_url }}/{{ device_type }}.dtb
{% endif %}
os: oe
- boot:
timeout:
minutes: 5
method: {{ boot_method }}
{% if boot_method == "fastboot" %}
{#
For fastboot, LAVA doesn't know how to unpack the rootfs/apply overlay/repack,
so we transfer the overlay over the network after boot.
#}
transfer_overlay:
download_command: wget -S --progress=dot:giga
unpack_command: tar -C / -xzf
{% else %}
commands: ramdisk
{% endif %}
prompts:
- '#'
- 'lava-shell:'
- test:
timeout:
minutes: 60
@@ -48,12 +75,29 @@ actions:
steps:
- mount -t proc none /proc
- mount -t sysfs none /sys
- mount -t devtmpfs none /dev
- mount -t devtmpfs none /dev || echo possibly already mounted
- mkdir -p /dev/pts
- mount -t devpts devpts /dev/pts
- echo 3 > /proc/sys/kernel/printk
- sh /deqp/lava-deqp-runner.sh {{ gpu_version }}
- cat /proc/loadavg
{% if env_vars %}
- export {{ env_vars }}
{% endif %}
# deqp-runner.sh assumes some stuff is in pwd
- cd /
- export DEQP_NO_SAVE_RESULTS=1
- 'export DEQP_RUNNER_OPTIONS="--shuffle false"'
- export DEQP_EXPECTED_FAILS=deqp-{{ gpu_version }}-fails.txt
- export DEQP_SKIPS=deqp-{{ gpu_version }}-skips.txt
- export DEQP_VER={{ deqp_version }}
- export LIBGL_DRIVERS_PATH=`pwd`/install/lib/dri
- "if sh /install/deqp-runner.sh; then
echo 'deqp: pass';
else
echo 'deqp: fail';
fi"
parse:
pattern: '(?P<test_case_id>\S*):\s+(?P<result>(pass|fail))'
from: inline

View File

@@ -1,209 +1,173 @@
variables:
LAVA_DEBIAN_VERSION: testing-slim
LAVA_IMAGE_TAG: "lava-2019-10-23-1"
include:
- project: 'wayland/ci-templates'
ref: 1f7f57c64ff4ebbf7292e3b7a13600518b8cb24c
file: '/templates/debian.yml'
# When to automatically run the CI
.ci-run-policy:
only:
- branches@mesa/mesa
- merge_requests
- /^ci([-/].*)?$/
retry:
max: 2
when:
- runner_system_failure
# Build Docker image with deqp, the rootfs and the build deps for Mesa
.lava-container:
extends:
- .debian@container-ifnot-exists
- .container
variables:
DEBIAN_TAG: '${DEBIAN_ARCH}-${LAVA_IMAGE_TAG}'
DEBIAN_EXEC: 'DEBIAN_ARCH=${DEBIAN_ARCH}
GCC_ARCH=${GCC_ARCH}
KERNEL_ARCH=${KERNEL_ARCH}
VOLT_ARCH=${VOLT_ARCH}
DEFCONFIG=${DEFCONFIG}
DEVICE_TREES="${DEVICE_TREES}"
KERNEL_IMAGE_NAME=${KERNEL_IMAGE_NAME}
bash .gitlab-ci/lava-debian-install.sh'
DEBIAN_VERSION: ${LAVA_DEBIAN_VERSION}
lava-container:armhf:
extends: .lava-container
variables:
DEBIAN_ARCH: "armhf"
GCC_ARCH: "arm-linux-gnueabihf"
KERNEL_ARCH: "arm"
VOLT_ARCH: "armhf"
DEFCONFIG: "arch/arm/configs/multi_v7_defconfig"
DEVICE_TREES: "arch/arm/boot/dts/rk3288-veyron-jaq.dtb arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dtb"
KERNEL_IMAGE_NAME: "zImage"
lava-container:arm64:
extends: .lava-container
variables:
DEBIAN_ARCH: "arm64"
GCC_ARCH: "aarch64-linux-gnu"
KERNEL_ARCH: "arm64"
VOLT_ARCH: "aarch64"
DEFCONFIG: "arch/arm64/configs/defconfig"
DEVICE_TREES: "arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dtb arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dtb"
KERNEL_IMAGE_NAME: "Image"
.lava-build:
image: $CI_REGISTRY_IMAGE/debian/$LAVA_DEBIAN_VERSION:$DEBIAN_ARCH-$LAVA_IMAGE_TAG
extends:
- .build-linux
# Use ccache transparently, and print stats before/after
before_script:
- mkdir -p results mesa-build
- mkdir -p ccache
- export PATH="/usr/lib/ccache:$PATH"
- export CCACHE_BASEDIR="$PWD"
- export CCACHE_DIR="$PWD/ccache"
- ccache --max-size=1500M
- ccache --zero-stats || true
- ccache --show-stats || true
script:
# Build Mesa
- /usr/share/meson/debcrossgen --arch ${DEBIAN_ARCH} -o /tmp/cross_file.txt
- meson . mesa-build
--cross-file /tmp/cross_file.txt
--libdir /artifacts/rootfs/mesa/lib/
--buildtype debugoptimized
-D gallium-drivers=kmsro,panfrost,lima
-D dri-drivers=
-D prefix=/artifacts/rootfs/mesa
-D glx=disabled
-D gbm=false
-D egl=true
-D platforms=surfaceless
-D osmesa=none
-D dri3=false
-D gallium-vdpau=false
-D gallium-xvmc=false
-D gallium-omx=disabled
-D gallium-va=false
-D gallium-xa=false
-D gallium-nine=false
-D llvm=false
- ninja -C mesa-build -j4
- ninja -C mesa-build install
- find /artifacts/rootfs/mesa/lib -name \*.so -exec ${GCC_ARCH}-strip {} \;
- du -sh /artifacts/rootfs/mesa/*
- rm -rf /artifacts/rootfs/mesa/include
# Pack rootfs
- cp .gitlab-ci/lava-deqp-runner.sh /artifacts/rootfs/deqp/.
- cp .gitlab-ci/deqp-*-fails.txt /artifacts/rootfs/deqp/.
- cp .gitlab-ci/deqp-*-skips.txt /artifacts/rootfs/deqp/.
- du -sh /artifacts/rootfs/deqp/*
- find /artifacts/rootfs/ -type f -printf "%s\t%p\n" | sort -n
- pushd /artifacts/rootfs/ ; find -H | cpio -H newc -v -o | gzip -c - > $CI_PROJECT_DIR/results/lava-rootfs-${DEBIAN_ARCH}.cpio.gz; popd
# Copy kernel and DT
- cp /artifacts/${KERNEL_IMAGE_NAME} /artifacts/*.dtb $CI_PROJECT_DIR/results/.
# Generate LAVA job
- cd $CI_PROJECT_DIR
- .gitlab-ci/generate_lava.py
--template .gitlab-ci/lava-deqp.yml.jinja2
--arch ${DEBIAN_ARCH}
--base-artifacts-url $CI_PROJECT_URL/-/jobs/$CI_JOB_ID/artifacts/raw/results
--device-types ${DEVICE_TYPES}
--kernel-image-name ${KERNEL_IMAGE_NAME}
after_script:
- export CCACHE_DIR="$PWD/ccache"
- ccache --show-stats
artifacts:
when: always
paths:
- results/
lava-build:armhf:
extends: .lava-build
needs: ["lava-container:armhf"]
variables:
DEBIAN_ARCH: "armhf"
GCC_ARCH: "arm-linux-gnueabihf"
DEVICE_TYPES: "rk3288-veyron-jaq sun8i-h3-libretech-all-h3-cc"
KERNEL_IMAGE_NAME: "zImage"
lava-build:arm64:
extends: .lava-build
needs: ["lava-container:arm64"]
variables:
DEBIAN_ARCH: "arm64"
GCC_ARCH: "aarch64-linux-gnu"
DEVICE_TYPES: "rk3399-gru-kevin meson-gxl-s905x-libretech-cc"
KERNEL_IMAGE_NAME: "Image"
.lava-test:
extends:
- .test
- .ci-run-policy
variables:
GIT_STRATEGY: none # testing doesn't build anything from source
ENV_VARS: "DEQP_PARALLEL=6"
DEQP_VERSION: gles2
script:
- lava_job_id=`lavacli jobs submit $CI_PROJECT_DIR/results/lava-deqp-$DEVICE_TYPE.yml`
- mkdir -p /srv/${FILES_HOST_NAME}/$CI_JOB_ID/
- cp /lava-files/${KERNEL_IMAGE_NAME} /srv/${FILES_HOST_NAME}/$CI_JOB_ID/.
- cp /lava-files/${DEVICE_TYPE}.dtb /srv/${FILES_HOST_NAME}/$CI_JOB_ID/.
- tar -C /lava-files/rootfs-${ARCH} -xf artifacts/install.tar
- pushd /lava-files/rootfs-${ARCH}
- find -H | cpio -H newc -o | gzip -c - > /srv/${FILES_HOST_NAME}/$CI_JOB_ID/lava-rootfs-${ARCH}.cpio.gz
- popd
- >
artifacts/generate_lava.py \
--template artifacts/lava-deqp.yml.jinja2 \
--pipeline-info "$CI_PIPELINE_URL on $CI_COMMIT_REF_NAME ${CI_NODE_INDEX}/${CI_NODE_TOTAL}" \
--base-artifacts-url ${FILES_HOST_URL}/$CI_JOB_ID \
--device-type ${DEVICE_TYPE} \
--env-vars "${ENV_VARS}" \
--arch ${ARCH} \
--deqp-version ${DEQP_VERSION} \
--kernel-image-name ${KERNEL_IMAGE_NAME} \
--kernel-image-type "${KERNEL_IMAGE_TYPE}" \
--gpu-version ${GPU_VERSION} \
--boot-method ${BOOT_METHOD} \
--lava-tags "${LAVA_TAGS}" \
--ci-node-index "${CI_NODE_INDEX}" \
--ci-node-total "${CI_NODE_TOTAL}"
- lava_job_id=`lavacli jobs submit lava-deqp.yml` || lavacli jobs submit lava-deqp.yml
- echo $lava_job_id
- lavacli jobs logs $lava_job_id | grep -a -v "{'case':" | tee results/lava-deqp-$lava_job_id.log
- rm -rf artifacts/*
- cp lava-deqp.yml artifacts/.
- lavacli jobs logs $lava_job_id | tee artifacts/lava-deqp-$lava_job_id.log
- lavacli jobs show $lava_job_id
- result=`lavacli results $lava_job_id 0_deqp deqp | head -1`
- echo $result
- '[[ "$result" == "pass" ]]'
after_script:
- rm -rf /srv/${FILES_HOST_NAME}/$CI_JOB_ID/
artifacts:
name: "mesa_${CI_JOB_NAME}"
when: always
paths:
- results/
- artifacts/
.lava-test:armhf:
image: $CI_REGISTRY_IMAGE/debian/$LAVA_DEBIAN_VERSION:armhf-$LAVA_IMAGE_TAG
extends: .lava-test
needs:
- lava-container:armhf
- lava-build:armhf
variables:
ARCH: armhf
KERNEL_IMAGE_NAME: zImage
KERNEL_IMAGE_TYPE: "type:\ zimage"
BOOT_METHOD: u-boot
extends:
- .lava-test
- .use-arm_build
dependencies:
- lava-build:armhf
- meson-armhf
needs:
- arm_build
- meson-armhf
.lava-test:arm64:
image: $CI_REGISTRY_IMAGE/debian/$LAVA_DEBIAN_VERSION:arm64-$LAVA_IMAGE_TAG
extends: .lava-test
needs:
- lava-container:arm64
- lava-build:arm64
variables:
ARCH: arm64
KERNEL_IMAGE_NAME: Image
KERNEL_IMAGE_TYPE: "type:\ image"
BOOT_METHOD: u-boot
extends:
- .lava-test
- .use-arm_build
dependencies:
- lava-build:arm64
- meson-arm64
needs:
- arm_build
- meson-arm64
panfrost-t760-test:armhf:
extends: .lava-test:armhf
panfrost-t720-gles2:arm64:
extends:
- .lava-test:arm64
- .panfrost-rules
variables:
DEVICE_TYPE: sun50i-h6-pine-h64
GPU_VERSION: panfrost-t720
ENV_VARS: "PAN_MESA_DEBUG=gles3 DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=T720"
FILES_HOST_NAME: "mesa-ci-lava-files.freedesktop.org"
FILES_HOST_URL: "https://mesa-ci-lava-files.freedesktop.org"
tags:
- mesa-ci-aarch64-lava-collabora
panfrost-t760-gles2:armhf:
extends:
- .lava-test:armhf
- .panfrost-rules
variables:
DEVICE_TYPE: rk3288-veyron-jaq
GPU_VERSION: panfrost-t760
BOOT_METHOD: depthcharge
KERNEL_IMAGE_TYPE: ""
ENV_VARS: "PAN_MESA_DEBUG=gles3 DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=T760"
FILES_HOST_NAME: "mesa-ci-lava-files.freedesktop.org"
FILES_HOST_URL: "https://mesa-ci-lava-files.freedesktop.org"
tags:
- lava-rk3288-veyron-jaq
- mesa-ci-aarch64-lava-collabora
panfrost-t860-test:arm64:
extends: .lava-test:arm64
panfrost-t860-gles2:arm64:
extends:
- .lava-test:arm64
- .panfrost-rules
variables:
DEVICE_TYPE: rk3399-gru-kevin
GPU_VERSION: panfrost-t860
BOOT_METHOD: depthcharge
KERNEL_IMAGE_TYPE: ""
ENV_VARS: "PAN_MESA_DEBUG=gles3 DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=T860"
FILES_HOST_NAME: "mesa-ci-lava-files.freedesktop.org"
FILES_HOST_URL: "https://mesa-ci-lava-files.freedesktop.org"
tags:
- lava-rk3399-gru-kevin
- mesa-ci-aarch64-lava-collabora
lima-test:armhf:
extends: .lava-test:armhf
panfrost-t860-gles3:arm64:
extends:
- .lava-test:arm64
- .panfrost-rules
variables:
DEVICE_TYPE: rk3399-gru-kevin
GPU_VERSION: panfrost-t860
BOOT_METHOD: depthcharge
KERNEL_IMAGE_TYPE: ""
DEQP_VERSION: gles3
ENV_VARS: "PAN_MESA_DEBUG=gles3 DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=T860"
CI_NODE_INDEX: 1
CI_NODE_TOTAL: 5
FILES_HOST_NAME: "mesa-ci-lava-files.freedesktop.org"
FILES_HOST_URL: "https://mesa-ci-lava-files.freedesktop.org"
tags:
- mesa-ci-aarch64-lava-collabora
.panfrost-t820-gles2:arm64:
extends:
- .lava-test:arm64
- .panfrost-rules
variables:
DEVICE_TYPE: meson-gxm-khadas-vim2
GPU_VERSION: panfrost-t820
LAVA_TAGS: panfrost
ENV_VARS: "PAN_MESA_DEBUG=gles3 DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=T820"
tags:
- mesa-ci-aarch64-lava-baylibre
.lima-mali400-test:armhf:
parallel: 2
extends:
- .lava-test:armhf
- .lima-rules
variables:
DEVICE_TYPE: sun8i-h3-libretech-all-h3-cc
GPU_VERSION: lima
ENV_VARS: "DEQP_PARALLEL=3 DEQP_EXPECTED_RENDERER=Mali400"
tags:
- lava-sun8i-h3-libretech-all-h3-cc
- mesa-ci-aarch64-lava-baylibre
lima-test:arm64:
extends: .lava-test:arm64
.lima-mali450-test:arm64:
extends:
- .lava-test:arm64
- .lima-rules
variables:
DEVICE_TYPE: meson-gxl-s905x-libretech-cc
GPU_VERSION: lima
ENV_VARS: "DEQP_PARALLEL=6 DEQP_EXPECTED_RENDERER=Mali450"
tags:
- lava-meson-gxl-s905x-libretech-cc
- mesa-ci-aarch64-lava-baylibre

View File

@@ -54,36 +54,10 @@ meson _build --native-file=native.file \
${GALLIUM_ST} \
-D gallium-drivers=${GALLIUM_DRIVERS:-[]} \
-D vulkan-drivers=${VULKAN_DRIVERS:-[]} \
-D I-love-half-baked-turnips=true \
${EXTRA_OPTION}
cd _build
meson configure
ninja -j4
ninja
LC_ALL=C.UTF-8 ninja test
ninja install
cd ..
if test -n "$MESON_SHADERDB"; then
./.gitlab-ci/run-shader-db.sh;
fi
# Delete 2MB of includes from artifacts.
rm -rf install/include
# Strip the drivers in the artifacts to cut 80% of the artifacts size.
if [ -n "$CROSS" ]; then
STRIP=`sed -n -E "s/strip\s*=\s*'(.*)'/\1/p" "$CROSS_FILE"`
if [ -z "$STRIP" ]; then
echo "Failed to find strip command in cross file"
exit 1
fi
else
STRIP="strip"
fi
find install -name \*.so -exec $STRIP {} \;
# Test runs don't pull down the git tree, so put the dEQP helper
# script and associated bits there.
mkdir -p artifacts/
cp -Rp .gitlab-ci/deqp* artifacts/
# cp -Rp src/freedreno/ci/expected* artifacts/

View File

@@ -0,0 +1,36 @@
diff --git a/generated_tests/CMakeLists.txt b/generated_tests/CMakeLists.txt
index 738526546..6f89048cd 100644
--- a/generated_tests/CMakeLists.txt
+++ b/generated_tests/CMakeLists.txt
@@ -206,11 +206,6 @@ piglit_make_generated_tests(
templates/gen_variable_index_write_tests/vs.shader_test.mako
templates/gen_variable_index_write_tests/fs.shader_test.mako
templates/gen_variable_index_write_tests/helpers.mako)
-piglit_make_generated_tests(
- vs_in_fp64.list
- gen_vs_in_fp64.py
- templates/gen_vs_in_fp64/columns.shader_test.mako
- templates/gen_vs_in_fp64/regular.shader_test.mako)
piglit_make_generated_tests(
shader_framebuffer_fetch_tests.list
gen_shader_framebuffer_fetch_tests.py)
@@ -279,7 +274,6 @@ add_custom_target(gen-gl-tests
gen_extensions_defined.list
vp-tex.list
variable_index_write_tests.list
- vs_in_fp64.list
gpu_shader4_tests.list
)
diff --git a/tests/sanity.py b/tests/sanity.py
index 12f1614c9..9019087e2 100644
--- a/tests/sanity.py
+++ b/tests/sanity.py
@@ -100,7 +100,6 @@ shader_tests = (
'spec/arb_tessellation_shader/execution/barrier-patch.shader_test',
'spec/arb_tessellation_shader/execution/built-in-functions/tcs-any-bvec4-using-if.shader_test',
'spec/arb_tessellation_shader/execution/sanity.shader_test',
- 'spec/arb_vertex_attrib_64bit/execution/vs_in/vs-input-uint_uvec4-double_dmat3x4_array2-position.shader_test',
'spec/glsl-1.50/execution/geometry-basic.shader_test',
'spec/oes_viewport_array/viewport-gs-write-simple.shader_test',
)

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

29
.gitlab-ci/piglit/run.sh Executable file
View File

@@ -0,0 +1,29 @@
#!/bin/bash
set -e
set -o xtrace
VERSION=`cat install/VERSION`
cd /piglit
PIGLIT_OPTIONS=$(echo $PIGLIT_OPTIONS | head -n 1)
xvfb-run --server-args="-noreset" sh -c \
"export LD_LIBRARY_PATH=$OLDPWD/install/lib;
wflinfo --platform glx --api gl --profile core | grep \"Mesa $VERSION\\\$\" &&
./piglit run -j4 $PIGLIT_OPTIONS $PIGLIT_PROFILES $OLDPWD/results"
PIGLIT_RESULTS=${PIGLIT_RESULTS:-$PIGLIT_PROFILES}
mkdir -p .gitlab-ci/piglit
cp $OLDPWD/install/piglit/$PIGLIT_RESULTS.txt .gitlab-ci/piglit/$PIGLIT_RESULTS.txt.baseline
./piglit summary console $OLDPWD/results | head -n -1 | grep -v ": pass" >.gitlab-ci/piglit/$PIGLIT_RESULTS.txt
if diff -q .gitlab-ci/piglit/$PIGLIT_RESULTS.txt{.baseline,}; then
exit 0
fi
./piglit summary html --exclude-details=pass $OLDPWD/summary $OLDPWD/results
echo Unexpected change in results:
diff -u .gitlab-ci/piglit/$PIGLIT_RESULTS.txt{.baseline,}
exit 1

49
.gitlab-ci/prepare-artifacts.sh Executable file
View File

@@ -0,0 +1,49 @@
#!/bin/bash
set -e
set -o xtrace
CROSS_FILE=/cross_file-"$CROSS".txt
# Delete unused bin and includes from artifacts to save space.
rm -rf install/bin install/include
# Strip the drivers in the artifacts to cut 80% of the artifacts size.
if [ -n "$CROSS" ]; then
STRIP=`sed -n -E "s/strip\s*=\s*'(.*)'/\1/p" "$CROSS_FILE"`
if [ -z "$STRIP" ]; then
echo "Failed to find strip command in cross file"
exit 1
fi
else
STRIP="strip"
fi
find install -name \*.so -exec $STRIP {} \;
# Test runs don't pull down the git tree, so put the dEQP helper
# script and associated bits there.
cp VERSION install/
cp -Rp .gitlab-ci/deqp* install/
cp -Rp .gitlab-ci/piglit install/
cp -Rp .gitlab-ci/traces.yml install/
cp -Rp .gitlab-ci/tracie install/
cp -Rp .gitlab-ci/tracie-runner-gl.sh install/
cp -Rp .gitlab-ci/tracie-runner-vk.sh install/
cp -Rp .gitlab-ci/fossils.yml install/
cp -Rp .gitlab-ci/fossils install/
cp -Rp .gitlab-ci/fossilize-runner.sh install/
cp -Rp .gitlab-ci/deqp-runner.sh install/
cp -Rp .gitlab-ci/deqp-*-fails.txt install/
cp -Rp .gitlab-ci/deqp-*-skips.txt install/
# Tar up the install dir so that symlinks and hardlinks aren't each
# packed separately in the zip file.
mkdir -p artifacts/
tar -cf artifacts/install.tar install
# If the container has LAVA stuff, prepare the artifacts for LAVA jobs
if [ -d /lava-files ]; then
# Pass needed files to the test stage
cp $CI_PROJECT_DIR/.gitlab-ci/generate_lava.py artifacts/.
cp $CI_PROJECT_DIR/.gitlab-ci/lava-deqp.yml.jinja2 artifacts/.
fi

View File

@@ -0,0 +1,146 @@
# This file list source dependencies to avoid creating/running jobs
# those outcome cannot be changed by the modifications from a branch.
# Mesa core source file dependencies
# ----------------------------------
.mesa-rules:
rules:
- changes: &mesa_core_file_list
- .gitlab-ci.yml
- .gitlab-ci/**/*
- include/**/*
- meson.build
- SConstruct
- src/*
- src/compiler/**/*
- src/drm-shim/**/*
- src/egl/**/*
- src/gbm/**/*
- src/glx/**/*
- src/gtest/**/*
- src/hgl/**/*
- src/include/**/*
- src/loader/**/*
- src/mapi/**/*
- src/mesa/**/*
- src/util/**/*
# Gallium core source file dependencies
# -------------------------------------
.gallium-rules:
rules:
- changes: &gallium_core_file_list
- src/gallium/*
- src/gallium/auxiliary/**/*
- src/gallium/drivers/*
- src/gallium/include/**/*
- src/gallium/state_trackers/**/*
- src/gallium/targets/**/*
- src/gallium/tests/**/*
- src/gallium/winsys/*
.softpipe-rules:
stage: softpipe
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/gallium/drivers/softpipe/**/*
- src/gallium/winsys/sw/**/*
when: on_success
- when: never
.llvmpipe-rules:
stage: llvmpipe
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/gallium/drivers/llvmpipe/**/*
- src/gallium/winsys/sw/**/*
when: on_success
- when: never
.freedreno-rules:
stage: freedreno
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/freedreno/**/*
- src/gallium/drivers/freedreno/**/*
- src/gallium/winsys/freedreno/**/*
when: on_success
- when: never
.panfrost-rules:
stage: panfrost
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/gallium/drivers/panfrost/**/*
- src/gallium/winsys/panfrost/**/*
- src/panfrost/**/*
when: on_success
- when: never
.lima-rules:
stage: lima
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/gallium/drivers/lima/**/*
- src/gallium/winsys/lima/**/*
- src/lima/**/*
when: on_success
- when: never
.radv-rules:
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
- src/amd/**/*
- src/vulkan/**/*
when: on_success
- when: never
.virgl-rules:
stage: virgl
rules:
- changes:
*mesa_core_file_list
when: on_success
- changes:
*gallium_core_file_list
when: on_success
- changes:
- src/gallium/drivers/llvmpipe/**/*
- src/gallium/drivers/virgl/**/*
- src/gallium/winsys/virgl/**/*
- src/gallium/winsys/sw/**/*
when: on_success
- when: never

35
.gitlab-ci/traces.yml Normal file
View File

@@ -0,0 +1,35 @@
traces-db:
gitlab-project-url: "https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db"
commit: "d3b1efe0cd69ef6ae40a29a14ed733ee0ba0cb4c"
traces:
- path: glmark2/desktop-blur-radius=5:effect=blur:passes=1:separable=true:windows=4.rdc
expectations:
- device: gl-vmware-llvmpipe
checksum: 8867f3a41f180626d0d4b7661ff5c0f4
- device: gl-virgl
checksum: 8867f3a41f180626d0d4b7661ff5c0f4
- path: glmark2/jellyfish.rdc
expectations:
- device: gl-vmware-llvmpipe
checksum: e0fe979fee129c0ed42a3059d1a4e1c9
- device: gl-virgl
checksum: e0fe979fee129c0ed42a3059d1a4e1c9
- path: glxgears/glxgears.trace
expectations:
- device: gl-vmware-llvmpipe
checksum: 02aca9b4b4ad6fd60331df6e4f87f2cd
- device: gl-virgl
checksum: 02aca9b4b4ad6fd60331df6e4f87f2cd
- path: KhronosGroup-Vulkan-Tools/vkcube.gfxr
expectations:
- device: vk-amd-polaris10
checksum: 29dc9e5e55c3de331407248737c23aa7
- path: LunarG-VulkanSamples/Hologram:-w:640:-h:480.gfxr
expectations:
- device: vk-amd-polaris10
checksum: 351710942ea93d511cef39ae2d7c68da
- path: Wicked-Engine/Tests:Cloth_Physics_Test.trace-dxgi
expectations:
- device: vk-amd-polaris10
checksum: 6b6d27df609b8d086cc3335e6d103581

49
.gitlab-ci/tracie-runner-gl.sh Executable file
View File

@@ -0,0 +1,49 @@
#!/bin/sh
set -ex
INSTALL="$(pwd)/install"
# Set up the driver environment.
export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:$(pwd)/install/lib/"
# Set environment for renderdoc libraries.
export PYTHONPATH="$PYTHONPATH:/renderdoc/build/lib"
export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/renderdoc/build/lib"
# Set environment for the waffle library.
export LD_LIBRARY_PATH="/waffle/build/lib:$LD_LIBRARY_PATH"
# Set environment for apitrace executable.
export PATH="/apitrace/build:$PATH"
# Use the surfaceless EGL platform.
export EGL_PLATFORM="surfaceless"
export DISPLAY=
export WAFFLE_PLATFORM="surfaceless_egl"
RESULTS=`pwd`/results
mkdir -p $RESULTS
# Perform a self-test to ensure tracie is working properly.
"$INSTALL/tracie/tests/test.sh"
if [ "$GALLIUM_DRIVER" = "virpipe" ]; then
# tracie is to use virpipe, and virgl_test_server llvmpipe
export GALLIUM_DRIVER="$GALLIUM_DRIVER"
GALLIUM_DRIVER=llvmpipe \
GALLIVM_PERF="nopt,no_filter_hacks" \
VTEST_USE_EGL_SURFACELESS=1 \
VTEST_USE_GLES=1 \
virgl_test_server >$RESULTS/vtest-log.txt 2>&1 &
sleep 1
fi
# Sanity check to ensure that our environment is sufficient to make our tests
# run against the Mesa built by CI, rather than any installed distro version.
MESA_VERSION=$(cat "$INSTALL/VERSION" | sed 's/\./\\./g')
wflinfo --platform surfaceless_egl --api gles2 | grep "Mesa $MESA_VERSION\(\s\|$\)"
python3 "$INSTALL/tracie/tracie.py" --file "$INSTALL/traces.yml" --device-name "$DEVICE_NAME"

37
.gitlab-ci/tracie-runner-vk.sh Executable file
View File

@@ -0,0 +1,37 @@
#!/bin/sh
set -ex
INSTALL="$(pwd)/install"
# Set the Vulkan driver to use.
export VK_ICD_FILENAMES="$(pwd)/install/share/vulkan/icd.d/${VK_DRIVER}_icd.x86_64.json"
# Set environment for VulkanTools' VK_LAYER_LUNARG_screenshot layer.
export VK_LAYER_PATH="$VK_LAYER_PATH:/VulkanTools/build/etc/vulkan/explicit_layer.d"
export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/VulkanTools/build/lib"
# Set environment for Wine
export WINEDEBUG="-all"
export WINEPREFIX="/dxvk-wine64"
export WINEESYNC=1
# Set environment for DXVK
export DXVK_LOG_LEVEL="none"
export DXVK_STATE_CACHE=0
# Perform a self-test to ensure tracie is working properly.
"$INSTALL/tracie/tests/test.sh"
# Sanity check to ensure that our environment is sufficient to make our tests
# run against the Mesa built by CI, rather than any installed distro version.
MESA_VERSION=$(cat "$INSTALL/VERSION" | sed 's/\./\\./g')
vulkaninfo | grep "Mesa $MESA_VERSION\(\s\|$\)"
# Run gfxreconstruct traces against the host's running X server (xvfb
# doesn't have DRI3 support).
# Set the DISPLAY env variable in each gitlab-runner's configuration
# file:
# https://docs.gitlab.com/runner/configuration/advanced-configuration.html#the-runners-section
PATH="/gfxreconstruct/build/bin:$PATH" \
python3 "$INSTALL/tracie/tracie.py" --file "$INSTALL/traces.yml" --device-name "$DEVICE_NAME"

156
.gitlab-ci/tracie/README.md Normal file
View File

@@ -0,0 +1,156 @@
Tracie - Mesa Traces Continuous Integration System
==================================================
Home of the Mesa trace testing effort.
### Traces definition file
The trace definition file contains information about the GitLab
project and git commit to get the traces from, and a list of the
traces to run along with their expected image checksums on each
device. An example:
```yaml
traces-db:
gitlab-project-url: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db
commit: master
traces:
- path: glmark2/jellyfish.rdc
expectations:
- device: gl-intel-0x3185
checksum: 58359ea4caf6ad44c6b65526881bbd17
- device: gl-vmware-llvmpipe
checksum: d82267c25a0decdad7b563c56bb81106
- path: supertuxkart/supertuxkart-antediluvian-abyss.rdc
expectations:
- device: gl-intel-0x3185
checksum: ff827f7eb069afd87cc305a422cba939
```
The `traces-db` entry can be absent, in which case it is assumed that
the traces can be found in the `CWD/traces-db` directory.
Traces that don't have an expectation for the current device are skipped
during trace replay.
Adding a new trace to the list involves commiting the trace to the git repo and
adding an entry to the `traces` list. The reference checksums can be calculated
with the [image_checksum.py](.gitlab-ci/tracie/image_checksum.py) script.
Alternatively, an arbitrary checksum can be used, and during replay (see below)
the scripts will report the mismatch and expected checksum.
### Trace-db GitLab projects
The trace-db GitLab projects are assumed to have git repositories
using LFS for their trace files. This is so that trace files can be
potentially checked out and replayed individually, thus reducing
storage requirements during CI runs.
### Enabling trace testing on a new device
To enable trace testing on a new device:
1. Create a new job in .gitlab-ci.yml. The job will need to be tagged
to run on runners with the appropriate hardware.
1. If you mean to test GL traces, use the `.traces-test-gl`
template jobs as a base, and make sure you set a unique value for the
`DEVICE_NAME` variable:
```yaml
my-hardware-gl-traces:
extends: .traces-test-gl
variables:
DEVICE_NAME: "gl-myhardware"
```
2. If you mean to test Vulkan traces, use the `.traces-test-vk`
template jobs as a base, set the `VK_DRIVER` variable, and make
sure you set a unique value for the `DEVICE_NAME` variable:
```yaml
my-hardware-vk-traces:
extends: .traces-test-vk
variables:
VK_DRIVER: "radeon"
DEVICE_NAME: "vk-myhardware"
```
2. Update the .gitlab-ci/traces.yml file with expectations for the new device.
Ensure that the device name used in the expectations matches the one
set in the job. For more information, and tips about how to calculate
the checksums, see the section describing the trace definition files.
### Trace files
Tracie supports renderdoc (.rdc), apitrace (.trace) and gfxreconstruct
(.gfxr) files. Trace files need to have the correct extension so that
tracie can detect them properly.
The trace files that are contained in public traces-db repositories must be
legally redistributable. This is typically true for FOSS games and
applications. Traces for proprietary games and application are typically not
redistributable, unless specific redistribution rights have been granted by the
publisher.
### Replaying traces
Mesa traces CI uses a set of scripts to replay traces and check the output
against reference checksums.
The high level script [tracie.py](.gitlab-ci/tracie/tracie.py) accepts
a traces definition file and the name of the device to be tested:
tracie.py --file .gitlab-ci/traces.yml --device-name gl-vmware-llvmpipe
tracie.py copies the produced artifacts to the `$CI_PROJECT_DIR/result`
directory. By default, created images from traces are only stored in case of a
checksum mismatch. The `TRACIE_STORE_IMAGES` CI/environment variable can be set
to `1` to force storing images, e.g., to get a complete set of reference
images.
At a lower level the
[dump_trace_images.py](.gitlab-ci/tracie/dump_trace_images.py) script is
called, which replays a trace, dumping a set of images in the process. By
default only the image corresponding to the last frame of the trace is dumped,
but this can be changed with the `--calls` parameter. The dumped images are
stored in a subdirectory `test/<device-name>` next to the trace file itself,
with names of the form `tracefilename-callnum.png`. The full log of any
commands used while dumping the images is also saved in a file in the
'test/<device-name>' subdirectory, named after the trace name with '.log'
appended.
Examples:
python3 dump_traces_images.py --device-name=gl-vmware-llvmpipe mytrace.trace
python3 dump_traces_images.py --device-name=gl-vmware-llvmpipe --calls=2075,3300 mytrace.trace
### Running the replay scripts locally
It's often useful, especially during development, to be able to run the scripts
locally.
Depending on the target 3D API, the scripts require a recent version
of apitrace being in the path, and also the renderdoc python module
being available, for GL traces.
To ensure python3 can find the renderdoc python module you need to set
`PYTHONPATH` to point to the location of `renderdoc.so` (binary python modules)
and `LD_LIBRARY_PATH` to point to the location of `librenderdoc.so`. In the
renderdoc build tree, both of these are in `renderdoc/<builddir>/lib`. Note
that renderdoc doesn't install the `renderdoc.so` python module.
In the case of Vulkan traces, the scripts need a recent version of
gfxrecon-replay being in the path, and also the
`VK_LAYER_LUNARG_screenshot` Vulkan layer from LunarG's VulkanTools.
To ensure that this layer can be found when running the trace you need
to set `VK_LAYER_PATH` to point to the location of
`VkLayer_screenshot.json` and `LD_LIBRARY_PATH` to point to the
location of `libVkLayer_screenshot.so`.
In the case of DXGI traces, the scripts require Wine, a recent version
of DXVK installed in the default `WINEPREFIX`, and a recent binary
version of apitrace for Windows which should be reachable through
Windows' `PATH` environment variable.

View File

@@ -0,0 +1,180 @@
#!/usr/bin/python3
# Copyright (c) 2019 Collabora Ltd
# Copyright © 2019-2020 Valve Corporation.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# SPDX-License-Identifier: MIT
import argparse
import os
import sys
import subprocess
from pathlib import Path
from traceutil import trace_type_from_filename, TraceType
def log(severity, msg, end='\n'):
print("[dump_trace_images] %s: %s" % (severity, msg), flush=True, end=end)
def log_result(msg):
print(msg, flush=True)
def run_logged_command(cmd, env, log_path):
ret = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, env=env)
logoutput = ("[dump_trace_images] Running: %s\n" % " ".join(cmd)).encode() + \
ret.stdout
log_path.parent.mkdir(parents=True, exist_ok=True)
with log_path.open(mode='wb') as log:
log.write(logoutput)
if ret.returncode:
raise RuntimeError(
logoutput.decode(errors='replace') +
"[dump_traces_images] Process failed with error code: %d" % ret.returncode)
def get_last_apitrace_frame_call(cmd_wrapper, trace_path):
cmd = cmd_wrapper + ["apitrace", "dump", "--calls=frame", str(trace_path)]
ret = subprocess.run(cmd, stdout=subprocess.PIPE)
for l in reversed(ret.stdout.decode(errors='replace').splitlines()):
s = l.split(None, 1)
if len(s) >= 1 and s[0].isnumeric():
return int(s[0])
return -1
def get_last_gfxreconstruct_frame_call(trace_path):
# FIXME: It would be great to have another way to get the amount of
# traces which wouldn't imply replaying the whole trace:
# https://github.com/LunarG/gfxreconstruct/issues/329
cmd = ["gfxrecon-replay", str(trace_path)]
ret = subprocess.run(cmd, stdout=subprocess.PIPE)
for l in reversed(ret.stdout.decode(errors='replace').splitlines()):
s = l.split(", ", 2)
if len(s) >= 3:
c = s[2].split(None, 1)
if len(c) >= 1 and c[0].isnumeric():
return int(c[0])
return -1
def dump_with_apitrace(retrace_cmd, trace_path, calls, device_name):
outputdir = str(trace_path.parent / "test" / device_name)
os.makedirs(outputdir, exist_ok=True)
outputprefix = str(Path(outputdir) / trace_path.name) + "-"
if len(calls) == 0:
calls = [str(get_last_apitrace_frame_call(retrace_cmd[:-1], trace_path))]
cmd = retrace_cmd + ["--headless",
"--snapshot=" + ','.join(calls),
"--snapshot-prefix=" + outputprefix, str(trace_path)]
log_path = Path(outputdir) / (trace_path.name + ".log")
run_logged_command(cmd, None, log_path)
def dump_with_renderdoc(trace_path, calls, device_name):
outputdir = str(trace_path.parent / "test" / device_name)
script_path = Path(os.path.dirname(os.path.abspath(__file__)))
cmd = [str(script_path / "renderdoc_dump_images.py"), str(trace_path), outputdir]
cmd.extend(calls)
log_path = Path(outputdir) / (trace_path.name + ".log")
run_logged_command(cmd, None, log_path)
def dump_with_gfxreconstruct(trace_path, calls, device_name):
from PIL import Image
outputdir_path = trace_path.parent / "test" / device_name
outputdir_path.mkdir(parents=True, exist_ok=True)
outputprefix = str(outputdir_path / trace_path.name) + "-"
if len(calls) == 0:
# FIXME: The VK_LAYER_LUNARG_screenshot numbers the calls from
# 0 to (total-num-calls - 1) while gfxreconstruct does it from
# 1 to total-num-calls:
# https://github.com/LunarG/gfxreconstruct/issues/284
calls = [str(get_last_gfxreconstruct_frame_call(trace_path) - 1)]
cmd = ["gfxrecon-replay", str(trace_path)]
log_path = outputdir_path / (trace_path.name + ".log")
env = os.environ.copy()
env["VK_INSTANCE_LAYERS"] = "VK_LAYER_LUNARG_screenshot"
env["VK_SCREENSHOT_FRAMES"] = ",".join(calls)
env["VK_SCREENSHOT_DIR"] = str(outputdir_path)
run_logged_command(cmd, env, log_path)
for c in calls:
ppm = str(outputdir_path / c) + ".ppm"
outputfile = outputprefix + c + ".png"
with log_path.open(mode='w') as log:
log.write("Writing: %s to %s" % (ppm, outputfile))
Image.open(ppm).save(outputfile)
os.remove(ppm)
def dump_with_testtrace(trace_path, calls, device_name):
from PIL import Image
outputdir_path = trace_path.parent / "test" / device_name
outputdir_path.mkdir(parents=True, exist_ok=True)
with trace_path.open() as f:
rgba = f.read()
color = [int(rgba[0:2], 16), int(rgba[2:4], 16),
int(rgba[4:6], 16), int(rgba[6:8], 16)]
if len(calls) == 0: calls = ["0"]
for c in calls:
outputfile = str(outputdir_path / trace_path.name) + "-" + c + ".png"
log_path = outputdir_path / (trace_path.name + ".log")
with log_path.open(mode='w') as log:
log.write("Writing RGBA: %s to %s" % (rgba, outputfile))
Image.frombytes('RGBA', (32, 32), bytes(color * 32 * 32)).save(outputfile)
def dump_from_trace(trace_path, calls, device_name):
log("Info", "Dumping trace %s" % trace_path, end='... ')
trace_type = trace_type_from_filename(trace_path.name)
try:
if trace_type == TraceType.APITRACE:
dump_with_apitrace(["eglretrace"], trace_path, calls, device_name)
elif trace_type == TraceType.APITRACE_DXGI:
dump_with_apitrace(["wine", "d3dretrace"], trace_path, calls, device_name)
elif trace_type == TraceType.RENDERDOC:
dump_with_renderdoc(trace_path, calls, device_name)
elif trace_type == TraceType.GFXRECONSTRUCT:
dump_with_gfxreconstruct(trace_path, calls, device_name)
elif trace_type == TraceType.TESTTRACE:
dump_with_testtrace(trace_path, calls, device_name)
else:
raise RuntimeError("Unknown tracefile extension")
log_result("OK")
return True
except Exception as e:
log_result("ERROR")
log("Debug", "=== Failure log start ===")
print(e)
log("Debug", "=== Failure log end ===")
return False
def main():
parser = argparse.ArgumentParser()
parser.add_argument('tracepath', help="trace to dump")
parser.add_argument('--device-name', required=True,
help="the name of the graphics device used to produce images")
parser.add_argument('--calls', required=False,
help="the call numbers from the trace to dump (default: last frame)")
args = parser.parse_args()
if args.calls is not None:
args.calls = args.calls.split(",")
else:
args.calls = []
success = dump_from_trace(Path(args.tracepath), args.calls, args.device_name)
sys.exit(0 if success else 1)
if __name__ == "__main__":
main()

View File

@@ -0,0 +1,39 @@
#!/usr/bin/env python3
# Copyright (c) 2019 Collabora Ltd
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# SPDX-License-Identifier: MIT
import argparse
import hashlib
from PIL import Image
def main():
parser = argparse.ArgumentParser()
parser.add_argument('imagefile', help='image file to calculate checksum for')
args = parser.parse_args()
md5 = hashlib.md5(Image.open(args.imagefile).tobytes())
print(md5.hexdigest())
if __name__ == "__main__":
main()

View File

@@ -0,0 +1,108 @@
#!/usr/bin/python3
# Copyright (c) 2019 Collabora Ltd
# Copyright © 2020 Valve Corporation.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# SPDX-License-Identifier: MIT
import argparse
import yaml
from traceutil import all_trace_type_names, trace_type_from_name
from traceutil import trace_type_from_filename
def trace_devices(trace):
return [e['device'] for e in trace['expectations']]
def cmd_traces_db_gitlab_project_url(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
print(y['traces-db']['gitlab-project-url'])
def cmd_traces_db_commit(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
print(y['traces-db']['commit'])
def cmd_traces(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
traces = y['traces']
traces = filter(lambda t: trace_type_from_filename(t['path']) in args.trace_types,
traces)
if args.device_name:
traces = filter(lambda t: args.device_name in trace_devices(t), traces)
traces = list(traces)
if len(traces) == 0:
return
print('\n'.join((t['path'] for t in traces)))
def cmd_checksum(args):
with open(args.file, 'r') as f:
y = yaml.safe_load(f)
traces = y['traces']
trace = next(t for t in traces if t['path'] == args.trace_path)
expectation = next(e for e in trace['expectations'] if e['device'] == args.device_name)
print(expectation['checksum'])
def main():
parser = argparse.ArgumentParser()
parser.add_argument('--file', required=True,
help='the name of the yaml file')
subparsers = parser.add_subparsers(help='sub-command help')
parser_traces_db_gitlab_project_url = subparsers.add_parser('traces_db_gitlab_project_url')
parser_traces_db_gitlab_project_url.set_defaults(func=cmd_traces_db_gitlab_project_url)
parser_traces_db_commit = subparsers.add_parser('traces_db_commit')
parser_traces_db_commit.set_defaults(func=cmd_traces_db_commit)
parser_traces = subparsers.add_parser('traces')
parser_traces.add_argument('--device-name', required=False,
help="the name of the graphics device used to "
"produce images")
parser_traces.add_argument('--trace-types', required=False,
default=",".join(all_trace_type_names()),
help="the types of traces to look for in recursive "
"dir walks " "(by default all types)")
parser_traces.set_defaults(func=cmd_traces)
parser_checksum = subparsers.add_parser('checksum')
parser_checksum.add_argument('--device-name', required=True,
help="the name of the graphics device used to "
"produce images")
parser_checksum.add_argument('trace_path')
parser_checksum.set_defaults(func=cmd_checksum)
args = parser.parse_args()
if hasattr(args, 'trace_types'):
args.trace_types = [trace_type_from_name(t) for t in args.trace_types.split(",")]
args.func(args)
if __name__ == "__main__":
main()

View File

@@ -0,0 +1,126 @@
#!/usr/bin/env python3
# Copyright (c) 2019 Collabora Ltd
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# SPDX-License-Identifier: MIT
import atexit
import os
import shutil
import sys
import tempfile
from pathlib import Path
def cleanup(dirpath):
shutil.rmtree(dirpath)
dirpath = tempfile.mkdtemp()
atexit.register(cleanup, dirpath)
RENDERDOC_DEBUG_FILE = dirpath + "/renderdoc.log"
# Needs to be in the environment before importing the module
os.environ['RENDERDOC_DEBUG_LOG_FILE'] = RENDERDOC_DEBUG_FILE
import renderdoc as rd
def findDrawWithEventId(controller, eventId):
for d in controller.GetDrawcalls():
if d.eventId == eventId:
return d
return None
def dumpImage(controller, eventId, outputDir, tracefile):
draw = findDrawWithEventId(controller, eventId)
if draw is None:
raise RuntimeError("Couldn't find draw call with eventId " + str(eventId))
controller.SetFrameEvent(draw.eventId, True)
texsave = rd.TextureSave()
# Select the first color output
texsave.resourceId = draw.outputs[0]
if texsave.resourceId == rd.ResourceId.Null():
return
filepath = Path(outputDir)
filepath.mkdir(parents = True, exist_ok = True)
filepath = filepath / (tracefile + "-" + str(int(draw.eventId)) + ".png")
print("Saving image at eventId %d: %s to %s" % (draw.eventId, draw.name, filepath))
# Most formats can only display a single image per file, so we select the
# first mip and first slice
texsave.mip = 0
texsave.slice.sliceIndex = 0
# For formats with an alpha channel, preserve it
texsave.alpha = rd.AlphaMapping.Preserve
texsave.destType = rd.FileType.PNG
controller.SaveTexture(texsave, str(filepath))
def loadCapture(filename):
cap = rd.OpenCaptureFile()
status = cap.OpenFile(filename, '', None)
if status != rd.ReplayStatus.Succeeded:
raise RuntimeError("Couldn't open file: " + str(status))
if not cap.LocalReplaySupport():
raise RuntimeError("Capture cannot be replayed")
status, controller = cap.OpenCapture(rd.ReplayOptions(), None)
if status != rd.ReplayStatus.Succeeded:
if os.path.exists(RENDERDOC_DEBUG_FILE):
print(open(RENDERDOC_DEBUG_FILE, "r").read())
raise RuntimeError("Couldn't initialise replay: " + str(status))
if os.path.exists(RENDERDOC_DEBUG_FILE):
open(RENDERDOC_DEBUG_FILE, "w").write("")
return (cap, controller)
def renderdoc_dump_images(filename, eventIds, outputDir):
rd.InitialiseReplay(rd.GlobalEnvironment(), [])
cap, controller = loadCapture(filename);
tracefile = Path(filename).name
if len(eventIds) == 0:
eventIds.append(controller.GetDrawcalls()[-1].eventId)
for eventId in eventIds:
dumpImage(controller, eventId, outputDir, tracefile)
controller.Shutdown()
cap.Shutdown()
rd.ShutdownReplay()
if __name__ == "__main__":
if len(sys.argv) < 3:
raise RuntimeError("Usage: renderdoc_dump_images.py <trace> <outputdir> [<draw-id>...]")
eventIds = [int(e) for e in sys.argv[3:]]
renderdoc_dump_images(sys.argv[1], eventIds, sys.argv[2])

View File

@@ -0,0 +1 @@
ff00ffff

View File

@@ -0,0 +1 @@
80800080

154
.gitlab-ci/tracie/tests/test.sh Executable file
View File

@@ -0,0 +1,154 @@
#!/bin/sh
TRACIE_DIR="$(dirname "$(readlink -f "$0")")/.."
TEST_DIR=""
TEST_EXIT=0
assert() {
if ! $1; then
echo "Assertion failed: \"$1\""
exit 1
fi
}
run_tracie() {
# Run tests for the .testtrace types, using the "gl-test-device" and "vk-test-device" device names.
python3 $TEST_DIR/tracie.py --file $TEST_DIR/tests/traces.yml --device-name gl-test-device && \
python3 $TEST_DIR/tracie.py --file $TEST_DIR/tests/traces.yml --device-name vk-test-device
}
cleanup() {
[ "$TEST_DIR" = "/tmp/*" ] && rm -rf "$TEST_DIR"
}
prepare_for_run() {
TEST_DIR="$(mktemp -d -t tracie.test.XXXXXXXXXX)"
# Copy all the tracie scripts to the test dir for the run-tests.sh script.
# This avoids polluting the normal working dir with test result artifacts.
cp -R "$TRACIE_DIR"/. "$TEST_DIR"
cd "$TEST_DIR"
mkdir traces-db
mv tests/test-data/* traces-db/.
trap cleanup EXIT
# Ensure we have a clean environment.
unset TRACIE_STORE_IMAGES
}
run_test() {
prepare_for_run
log=$(mktemp)
if ($1 > "$log" 2>&1 ;); then
if [ -t 1 ]; then
echo "$1: \e[0;32mSuccess\e[0m"
else
echo "$1: Success"
fi
else
if [ -t 1 ]; then
echo "$1: \e[0;31mFail\e[0m"
else
echo "$1: Fail"
fi
cat "$log"
TEST_EXIT=1
fi
rm "$log"
cleanup
}
assert_results_yaml_contains() {
grep -q "actual: $1" $4
assert "[ $? = 0 ]"
grep -q "expected: $2" $4
assert "[ $? = 0 ]"
if [ $3 != "" ]; then
grep -q $3 $4
fi
assert "[ $? = 0 ]"
}
tracie_succeeds_if_all_images_match() {
run_tracie
assert "[ $? = 0 ]"
assert_results_yaml_contains 5efda83854befe0155ff8517a58d5b51 5efda83854befe0155ff8517a58d5b51 "" "$PWD/results/results.yml"
}
tracie_fails_on_image_mismatch() {
sed -i 's/5efda83854befe0155ff8517a58d5b51/8e0a801367e1714463475a824dab363b/g' \
"$TEST_DIR/tests/traces.yml"
run_tracie
assert "[ $? != 0 ]"
assert_results_yaml_contains 5efda83854befe0155ff8517a58d5b51 8e0a801367e1714463475a824dab363b "trace2/test/vk-test-device/olive.testtrace-0.png" "$PWD/results/results.yml"
}
tracie_skips_traces_without_checksum() {
echo "traces:" > "$TEST_DIR/tests/traces.yml"
echo " - path: trace1/red.testtrace" >> "$TEST_DIR/tests/traces.yml"
echo " expectations:" >> "$TEST_DIR/tests/traces.yml"
echo " - device: bla" >> "$TEST_DIR/tests/traces.yml"
echo " checksum: 000000000000000" >> "$TEST_DIR/tests/traces.yml"
# red.testtrace should be skipped, since it doesn't
# have any checksums for our device
echo "ff0000ff" > traces-db/trace1/red.testtrace
run_tracie
assert "[ $? = 0 ]"
}
tracie_fails_on_dump_image_error() {
# "invalid" should fail to parse as rgba and
# cause an error
echo "invalid" > traces-db/trace1/magenta.testtrace
run_tracie
assert "[ $? != 0 ]"
assert_results_yaml_contains "error" "8e0a801367e1714463475a824dab363b" "trace1/magenta.testtrace" "$PWD/results/results.yml"
}
tracie_stores_only_logs_on_checksum_match() {
run_tracie
assert "[ $? = 0 ]"
assert "[ -f "$TEST_DIR/results/trace1/test/gl-test-device/magenta.testtrace.log" ]"
assert "[ -f "$TEST_DIR/results/trace2/test/vk-test-device/olive.testtrace.log" ]"
assert "[ ! -f "$TEST_DIR/results/trace1/test/gl-test-device/magenta.testtrace-0.png" ]"
assert "[ ! -f "$TEST_DIR/results/trace2/test/vk-test-device/olive.testtrace-0.png" ]"
ls -lR "$TEST_DIR"
}
tracie_stores_images_on_checksum_mismatch() {
sed -i 's/5efda83854befe0155ff8517a58d5b51/8e0a801367e1714463475a824dab363b/g' \
"$TEST_DIR/tests/traces.yml"
run_tracie
assert "[ $? != 0 ]"
assert "[ ! -f "$TEST_DIR/results/trace1/test/gl-test-device/magenta.testtrace-0.png" ]"
assert "[ -f "$TEST_DIR/results/trace2/test/vk-test-device/olive.testtrace-0.png" ]"
}
tracie_stores_images_on_request() {
(export TRACIE_STORE_IMAGES=1; run_tracie)
assert "[ $? = 0 ]"
assert "[ -f "$TEST_DIR/results/trace1/test/gl-test-device/magenta.testtrace-0.png" ]"
assert "[ -f "$TEST_DIR/results/trace2/test/vk-test-device/olive.testtrace-0.png" ]"
ls -lR "$TEST_DIR"
}
run_test tracie_succeeds_if_all_images_match
run_test tracie_fails_on_image_mismatch
run_test tracie_skips_traces_without_checksum
run_test tracie_fails_on_dump_image_error
run_test tracie_stores_only_logs_on_checksum_match
run_test tracie_stores_images_on_checksum_mismatch
run_test tracie_stores_images_on_request
exit $TEST_EXIT

View File

@@ -0,0 +1,9 @@
traces:
- path: trace1/magenta.testtrace
expectations:
- device: gl-test-device
checksum: 8e0a801367e1714463475a824dab363b
- path: trace2/olive.testtrace
expectations:
- device: vk-test-device
checksum: 5efda83854befe0155ff8517a58d5b51

Some files were not shown because too many files have changed in this diff Show More