docs: 9.1.4 release notes

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>

Makefile.am

@@ -36,7 +36,7 @@ check-local:
 
 # Rules for making release tarballs
 
-PACKAGE_VERSION=9.1-devel
+PACKAGE_VERSION=9.1.4
 PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
 PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
 

bin/.cherry-ignore

@@ -0,0 +1,32 @@
+d60da27273d2cdb68bc32cae2ca66718dab15f27 st/mesa: set ctx->Const.MaxSamples = 0, not 1
+5c86a728d4f688c0fe7fbf9f4b8f88060b65c4ee r600g: fix htile buffer leak
+496928a442cec980b534bc5da2523b3632b21b61 CopyTexImage: Don't check sRGB vs LINEAR for desktop GL
+3ee602314fc22054f69ee476f2e1037653d269bc mesa: Allow glGet* queries of MAX_VARYING_COMPONENTS in ES 3
+
+# Already cherry picked without -x
+96b3ca89b153f358de74059151d2b0e8bd884dfa scons: Allows choosing VS 10 or 11.
+
+# This patch is superceded by 7d4f1e6
+dbf94d105a48b7aafb2c8cf64d8b4392d87efea1 glsl: Replace constant-index vector array accesses with swizzles
+
+# This patch is superceded by 34a4fc5
+0967c362bf378b7415c30ca6d9523d3b2a3a7f5d i965: Fix an inconsistency inb the VUE map with gl_ClipVertex on gen4/5.
+
+# This patch was backported as c3eb301
+a8246927e35a49097f70cffb7fa8dd05ec1365e1 r600g: Fix UMAD on Cayman
+
+# These patches cannot be backported without other, too invasive changes
+eb19163a4dd3d7bfeed63229820c926f99ed00d9 radeonsi: Initial support for multiple constant buffers
+e3befbca5ed9f22effcdc91c5886c86b644bc190 radeonsi: Handle TGSI_SEMANTIC_CLIPVERTEX
+
+# These patches are performance improvements that are difficult to backport and cause regressions
+740350c982bd2735b9eb9063c2b91856b6f1ad31 i965: Make the fragment shader pull constants index by dwords, not vec4s.
+dca5fc14358a8b267b3854c39c976a822885898f i965/fs: Improve performance of varying-index uniform loads on IVB.
+70b27e0e4b5d15e575ea477d63c0f6cb19d645c2 i965/fs: Use LD messages for pre-gen7 varying-index uniform loads
+62501c3af85089b423218a41a2e2433ac849c2d3 i965/fs: Allow CSE on pre-gen7 varying-index uniform loads
+
+# Reverted in master
+98dfd59a0445666060c97b0dccaf0e9f030b547a i965: fix problem with constant out of bounds access (v2)
+
+# Already cherry-picked, but squashed with the commit that broke what this fixed
+4405ff4055685841c9d9545da52c7edc8708b14b i965: Fix haswell_upload_cut_index when there's no index buffer.

bin/bugzilla_mesa.sh

@@ -0,0 +1,52 @@
+#!/bin/bash
+
+# This script is used to generate the list of fixed bugs that
+# appears in the release notes files, with HTML formatting.
+#
+# Note: This script could take a while until all details have
+#       been fetched from bugzilla.
+#
+# Usage examples:
+#
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 > bugfixes
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee bugfixes
+# $ DRYRUN=yes bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ DRYRUN=yes bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | wc -l
+
+
+# regex pattern: trim before url
+trim_before='s/.*\(http\)/\1/'
+
+# regex pattern: trim after url
+trim_after='s/\(show_bug.cgi?id=[0-9]*\).*/\1/'
+
+# regex pattern: always use https
+use_https='s/http:/https:/'
+
+# extract fdo urls from commit log
+urls=$(git log $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before -e $trim_after -e $use_https | sort | uniq)
+
+# if DRYRUN is set to "yes", simply print the URLs and don't fetch the
+# details from fdo bugzilla.
+#DRYRUN=yes
+
+if [ "x$DRYRUN" = xyes ]; then
+	for i in $urls
+	do
+		echo $i
+	done
+else
+	echo "<ul>"
+	echo ""
+
+	for i in $urls
+	do
+		id=$(echo $i | cut -d'=' -f2)
+		summary=$(wget --quiet -O - $i | grep -e '<title>.*</title>' | sed -e 's/ *<title>Bug [0-9]\+ &ndash; \(.*\)<\/title>/\1/')
+		echo "<li><a href=\"$i\">Bug $id</a> - $summary</li>"
+		echo ""
+	done
+
+	echo "</ul>"
+fi

bin/get-pick-list.sh

@@ -1,6 +1,12 @@
 #!/bin/sh
 
 # Script for generating a list of candidates for cherry-picking to a stable branch
+#
+# Usage examples:
+#
+# $ bin/get-pick-list.sh
+# $ bin/get-pick-list.sh > picklist
+# $ bin/get-pick-list.sh | tee picklist
 
 # Grep for commits with "cherry picked from commit" in the commit message.
 git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
@@ -8,7 +14,7 @@ git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
 	sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
 
 # Grep for commits that were marked as a candidate for the stable tree.
-git log --reverse --pretty=%H -i --grep='^[[:space:]]*NOTE: This is a candidate' HEAD..origin/master |\
+git log --reverse --pretty=%H -i --grep='^[[:space:]]*NOTE: .*[Cc]andidate' HEAD..origin/master |\
 while read sha
 do
 	# Check to see whether the patch is on the ignore list.

bin/shortlog_mesa.sh

@@ -2,6 +2,12 @@
 
 # This script is used to generate the list of changes that
 # appears in the release notes files, with HTML formatting.
+#
+# Usage examples:
+#
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 > changes
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee changes
 
 
 typeset -i in_log=0

common.py

@@ -100,4 +100,4 @@ def AddOptions(opts):
 	opts.Add(BoolOption('quiet', 'DEPRECATED: profile build', 'yes'))
 	opts.Add(BoolOption('texture_float', 'enable floating-point textures and renderbuffers', 'no'))
 	if host_platform == 'windows':
-		opts.Add(EnumOption('MSVS_VERSION', 'MS Visual C++ version', None, allowed_values=('7.1', '8.0', '9.0')))
+		opts.Add(EnumOption('MSVC_VERSION', 'MS Visual C++ version', None, allowed_values=('7.1', '8.0', '9.0', '10.0', '11.0')))

configure.ac

@@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output
 m4_divert_once([HELP_END], [
 See docs/autoconf.html for more details on the options for Mesa.])
 
-AC_INIT([Mesa], [9.1.0],
+AC_INIT([Mesa], [9.1.4],
     [https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa])
 AC_CONFIG_AUX_DIR([bin])
 AC_CONFIG_MACRO_DIR([m4])
@@ -20,7 +20,8 @@ echo \#buildapi-variable-no-builddir >/dev/null
 # Support silent build rules, requires at least automake-1.11. Disable
 # by either passing --disable-silent-rules to configure or passing V=1
 # to make
-m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])],
+    [AC_SUBST([AM_DEFAULT_VERBOSITY], [1])])
 
 m4_ifdef([AM_PROG_AR], [AM_PROG_AR])
 
@@ -30,7 +31,7 @@ AC_SUBST([OSMESA_VERSION])
 
 dnl Versions for external dependencies
 LIBDRM_REQUIRED=2.4.24
-LIBDRM_RADEON_REQUIRED=2.4.40
+LIBDRM_RADEON_REQUIRED=2.4.42
 LIBDRM_INTEL_REQUIRED=2.4.38
 LIBDRM_NVVIEUX_REQUIRED=2.4.33
 LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41"
@@ -57,10 +58,10 @@ LT_PREREQ([2.2])
 LT_INIT([disable-static])
 
 AX_PROG_BISON([],
-              AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-parse.c"]
+              AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-parse.c"],
                     [AC_MSG_ERROR([bison not found - unable to compile glcpp-parse.y])]))
 AX_PROG_FLEX([],
-             AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-lex.c"]
+             AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-lex.c"],
                    [AC_MSG_ERROR([flex not found - unable to compile glcpp-lex.l])]))
 
 AC_PATH_PROG([PERL], [perl])
@@ -451,6 +452,9 @@ if test "x$enable_asm" = xyes; then
         linux* | *freebsd* | dragonfly* | *netbsd*)
             test "x$enable_64bit" = xyes && asm_arch=x86_64 || asm_arch=x86
             ;;
+        gnu*)
+            asm_arch=x86
+            ;;
         esac
         ;;
     x86_64)
@@ -611,7 +615,7 @@ AC_ARG_ENABLE([opencl],
          [enable OpenCL library NOTE: Enabling this option will also enable
           --with-llvm-shared-libs
           @<:@default=no@:>@])],
-   [enable_opencl="$enableval" with_llvm_shared_libs="$enableval"],
+   [],
    [enable_opencl=no])
 AC_ARG_ENABLE([xlib_glx],
     [AS_HELP_STRING([--enable-xlib-glx],
@@ -701,6 +705,16 @@ if test "x$enable_dri$enable_xlib_glx" = xyesyes; then
     AC_MSG_ERROR([DRI and Xlib-GLX cannot be built together])
 fi
 
+if test "x$enable_opengl$enable_xlib_glx" = xnoyes; then
+    AC_MSG_ERROR([Xlib-GLX cannot be built without OpenGL])
+fi
+
+# Disable GLX if OpenGL is not enabled
+if test "x$enable_glx$enable_opengl" = xyesno; then
+    AC_MSG_WARN([OpenGL not enabled, disabling GLX])
+    enable_glx=no
+fi
+
 # Disable GLX if DRI and Xlib-GLX are not enabled
 if test "x$enable_glx" = xyes -a \
         "x$enable_dri" = xno -a \
@@ -815,20 +829,6 @@ if test "x$enable_dri" = xyes; then
     fi
 fi
 
-dnl Find out if X is available.
-PKG_CHECK_MODULES([X11], [x11], [no_x=no], [no_x=yes])
-
-dnl Try to tell the user that the --x-* options are only used when
-dnl pkg-config is not available. This must be right after AC_PATH_XTRA.
-m4_divert_once([HELP_BEGIN],
-[These options are only used when the X libraries cannot be found by the
-pkg-config utility.])
-
-dnl We need X for xlib and dri, so bomb now if it's not found
-if test "x$enable_glx" = xyes -a "x$no_x" = xyes; then
-    AC_MSG_ERROR([X11 development libraries needed for GLX])
-fi
-
 dnl Direct rendering or just indirect rendering
 case "$host_os" in
 gnu*)
@@ -1059,26 +1059,24 @@ if test "x$enable_dri" = xyes; then
     DRI_DIRS=`echo "$DRI_DIRS" | $SED 's/  */ /g'`
 
     # Check for expat
-    if test "x$enable_dri" = xyes; then
+    EXPAT_INCLUDES=""
-        EXPAT_INCLUDES=""
+    EXPAT_LIB=-lexpat
-        EXPAT_LIB=-lexpat
+    AC_ARG_WITH([expat],
-        AC_ARG_WITH([expat],
+        [AS_HELP_STRING([--with-expat=DIR],
-            [AS_HELP_STRING([--with-expat=DIR],
+            [expat install directory])],[
-                [expat install directory])],[
+        EXPAT_INCLUDES="-I$withval/include"
-            EXPAT_INCLUDES="-I$withval/include"
+        CPPFLAGS="$CPPFLAGS $EXPAT_INCLUDES"
-            CPPFLAGS="$CPPFLAGS $EXPAT_INCLUDES"
+        LDFLAGS="$LDFLAGS -L$withval/$LIB_DIR"
-            LDFLAGS="$LDFLAGS -L$withval/$LIB_DIR"
+        EXPAT_LIB="-L$withval/$LIB_DIR -lexpat"
-            EXPAT_LIB="-L$withval/$LIB_DIR -lexpat"
+        ])
-            ])
+    AC_CHECK_HEADER([expat.h],[],[AC_MSG_ERROR([Expat required for DRI.])])
-        AC_CHECK_HEADER([expat.h],[],[AC_MSG_ERROR([Expat required for DRI.])])
+    save_LIBS="$LIBS"
-	save_LIBS="$LIBS"
+    AC_CHECK_LIB([expat],[XML_ParserCreate],[],
-        AC_CHECK_LIB([expat],[XML_ParserCreate],[],
+        [AC_MSG_ERROR([Expat required for DRI.])])
-            [AC_MSG_ERROR([Expat required for DRI.])])
+    LIBS="$save_LIBS"
-	LIBS="$save_LIBS"
-    fi
 
-    # if we are building any dri driver other than swrast or using the dri state tracker ...
+    # If we are building any DRI driver other than swrast.
-    if test -n "$DRI_DIRS" -a x"$DRI_DIRS" != xswrast || test "x$enable_dri" = xyes; then
+    if test -n "$DRI_DIRS" -a x"$DRI_DIRS" != xswrast; then
         # ... libdrm is required
         if test "x$have_libdrm" != xyes; then
             AC_MSG_ERROR([DRI drivers requires libdrm >= $LIBDRM_REQUIRED])
@@ -1146,14 +1144,6 @@ case $DRI_DIRS in
     ;;
 esac
 
-AM_CONDITIONAL(HAVE_I915_DRI, test x$HAVE_I915_DRI = xyes)
-AM_CONDITIONAL(HAVE_I965_DRI, test x$HAVE_I965_DRI = xyes)
-AM_CONDITIONAL(HAVE_NOUVEAU_DRI, test x$HAVE_NOUVEAU_DRI = xyes)
-AM_CONDITIONAL(HAVE_R200_DRI, test x$HAVE_R200_DRI = xyes)
-AM_CONDITIONAL(HAVE_RADEON_DRI, test x$HAVE_RADEON_DRI = xyes)
-AM_CONDITIONAL(HAVE_SWRAST_DRI, test x$HAVE_SWRAST_DRI = xyes)
-AM_CONDITIONAL(HAVE_COMMON_DRI, test x$HAVE_COMMON_DRI = xyes)
-
 dnl
 dnl OSMesa configuration
 dnl
@@ -1619,8 +1609,13 @@ AC_ARG_ENABLE([gallium-llvm],
 AC_ARG_WITH([llvm-shared-libs],
     [AS_HELP_STRING([--with-llvm-shared-libs],
         [link with LLVM shared libraries @<:@default=disabled@:>@])],
-    [with_llvm_shared_libs=yes],
+    [],
     [with_llvm_shared_libs=no])
+AS_IF([test x$enable_opencl = xyes],
+    [
+        AC_MSG_WARN([OpenCL required, forcing LLVM shared libraries])
+        with_llvm_shared_libs=yes
+    ])
 
 AC_ARG_WITH([llvm-prefix],
     [AS_HELP_STRING([--with-llvm-prefix],
@@ -1662,16 +1657,17 @@ if test "x$enable_gallium_llvm" = xyes; then
     if test "x$LLVM_CONFIG" != xno; then
 	LLVM_VERSION=`$LLVM_CONFIG --version | sed 's/svn.*//g'`
 	LLVM_VERSION_INT=`echo $LLVM_VERSION | sed -e 's/\([[0-9]]\)\.\([[0-9]]\)/\10\2/g'`
-        if test "x$with_llvm_shared_libs" != xyes; then
+        LLVM_COMPONENTS="engine bitwriter"
-            LLVM_COMPONENTS="engine bitwriter"
+        if $LLVM_CONFIG --components | grep -q '\<mcjit\>'; then
-            if $LLVM_CONFIG --components | grep -q '\<mcjit\>'; then
+            LLVM_COMPONENTS="${LLVM_COMPONENTS} mcjit"
-                LLVM_COMPONENTS="${LLVM_COMPONENTS} mcjit"
+        fi
-            fi
+        if $LLVM_CONFIG --components | grep -q '\<oprofilejit\>'; then
+            LLVM_COMPONENTS="${LLVM_COMPONENTS} oprofilejit"
+        fi
 
-            if test "x$enable_opencl" = xyes; then
+        if test "x$enable_opencl" = xyes; then
-                LLVM_COMPONENTS="${LLVM_COMPONENTS} ipo linker instrumentation"
+            LLVM_COMPONENTS="${LLVM_COMPONENTS} ipo linker instrumentation"
-            fi
+        fi
-	fi
 	LLVM_LDFLAGS=`$LLVM_CONFIG --ldflags`
 	LLVM_BINDIR=`$LLVM_CONFIG --bindir`
 	LLVM_CPPFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cppflags"`
@@ -1746,6 +1742,7 @@ gallium_check_st() {
     fi
     if test "x$HAVE_ST_DRI" = xyes && test "x$2" != x; then
          GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS $2"
+         HAVE_COMMON_DRI=yes
     fi
     if test "x$HAVE_ST_XORG" = xyes && test "x$3" != x; then
          GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS $3"
@@ -1840,6 +1837,9 @@ if test "x$with_gallium_drivers" != x; then
             if test "x$enable_r600_llvm" = xyes; then
                 USE_R600_LLVM_COMPILER=yes;
             fi
+            if test "x$enable_opencl" = xyes; then
+                LLVM_COMPONENTS="${LLVM_COMPONENTS} bitreader asmparser"
+            fi
             gallium_check_st "radeon/drm" "dri-r600" "xorg-r600" "" "xvmc-r600" "vdpau-r600"
             ;;
         xradeonsi)
@@ -1868,6 +1868,7 @@ if test "x$with_gallium_drivers" != x; then
 
             if test "x$HAVE_ST_DRI" = xyes; then
                 GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS dri-swrast"
+                HAVE_COMMON_DRI=yes
             fi
             if test "x$HAVE_ST_VDPAU" = xyes; then
                 GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS vdpau-softpipe"
@@ -1984,6 +1985,14 @@ for driver in $GALLIUM_DRIVERS_DIRS; do
     esac
 done
 
+AM_CONDITIONAL(HAVE_I915_DRI, test x$HAVE_I915_DRI = xyes)
+AM_CONDITIONAL(HAVE_I965_DRI, test x$HAVE_I965_DRI = xyes)
+AM_CONDITIONAL(HAVE_NOUVEAU_DRI, test x$HAVE_NOUVEAU_DRI = xyes)
+AM_CONDITIONAL(HAVE_R200_DRI, test x$HAVE_R200_DRI = xyes)
+AM_CONDITIONAL(HAVE_RADEON_DRI, test x$HAVE_RADEON_DRI = xyes)
+AM_CONDITIONAL(HAVE_SWRAST_DRI, test x$HAVE_SWRAST_DRI = xyes)
+AM_CONDITIONAL(HAVE_COMMON_DRI, test x$HAVE_COMMON_DRI = xyes)
+
 AM_CONDITIONAL(HAVE_GALAHAD_GALLIUM, test x$HAVE_GALAHAD_GALLIUM = xyes)
 AM_CONDITIONAL(HAVE_IDENTITY_GALLIUM, test x$HAVE_IDENTITY_GALLIUM = xyes)
 AM_CONDITIONAL(HAVE_NOOP_GALLIUM, test x$HAVE_NOOP_GALLIUM = xyes)

docs/index.html

@@ -16,6 +16,23 @@
 
 <h1>News</h1>
 
+<h2>February 22, 2013</h2>
+
+<p>
+<a href="relnotes-9.1.html">Mesa 9.1</a> is released.
+This is a new development release.
+See the release notes for more information about the release.
+</p>
+
+
+<h2>February 21, 2013</h2>
+
+<p>
+<a href="relnotes-9.0.3.html">Mesa 9.0.3</a> is released.
+This is a bug fix release.
+</p>
+
+
 <h2>January 22, 2013</h2>
 
 <p>

docs/relnotes-9.1.1.html

@@ -0,0 +1,235 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.1 Release Notes / March 19th, 2013</h1>
+
+<p>
+Mesa 9.1.1 is a bug fix release which fixes bugs found since the 9.1 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+6508d9882d8dce7106717f365632700c  MesaLib-9.1.1.tar.gz
+6ea2bdc3b7ecfb4257b39814b4182580  MesaLib-9.1.1.tar.bz2
+3434c0eb47849a08c53cd32833d10d13  MesaLib-9.1.1.zip
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=30232">Bug 30232</a> - [GM45] mesa demos spriteblast render incorrectly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=32429">Bug 32429</a> - [gles2] Ironlake: gl_PointCoord takes no effect for point sprites</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=38086">Bug 38086</a> - Mesa 7.11-devel implementation error: Unexpected program target in destroy_program_variants_cb()</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57121">Bug 57121</a> - [snb] corrupted GLSL built-in function results when using Uniform Buffer contents as arguments</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58042">Bug 58042</a> - [bisected] Garbled UI in Team Fortress 2 and Counter-Strike: Source</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58960">Bug 58960</a> - Texture flicker with fragment shader</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59495">Bug 59495</a> - [i965 Bisected]Oglc fbblit(advanced.blitFb-3d-cube.mirror.both) fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59783">Bug 59783</a> - [IVB bisected] 3DMMES2.0 Taiji performance reduced by ~13% with gnome-session enable compositing</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60121">Bug 60121</a> - build - libvdpau_softpipe fails at runtime.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60143">Bug 60143</a> - gbm_dri_bo_create fails to initialize bo-&gt;base.base.format</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60802">Bug 60802</a> - Corruption with DMA ring on cayman</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60848">Bug 60848</a> - [bisected] r600g: add htile support cause gpu lockup in Dishonored wine.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60938">Bug 60938</a> - [softpipe] piglit interpolation-noperspective-gl_BackColor-flat-fixed regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61012">Bug 61012</a> - alloc_layout_array tx * ty assertion failure when making pbuffer current</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61026">Bug 61026</a> - Segfault in glBitmap when called with PBO source</li>
+
+<!-- <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=">Bug </a> - </li> -->
+</ul>
+
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.1..mesa-9.1.1
+</pre>
+
+
+<p>Adam Sampson (1):</p>
+<ul>
+  <li>autotools: oprofilejit should be included in the list of LLVM components required</li>
+</ul>
+
+<p>Alex Deucher (2):</p>
+<ul>
+  <li>r600g: add Richland APU pci ids</li>
+  <li>r600g: Use blitter rather than DMA for 128bpp on cayman (v3)</li>
+</ul>
+
+<p>Andreas Boll (2):</p>
+<ul>
+  <li>docs: Add 9.1 release md5sums</li>
+  <li>docs: add news item for 9.1 release</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>meta: Allocate texture before initializing texture coordinates</li>
+</ul>
+
+<p>Brian Paul (11):</p>
+<ul>
+  <li>docs: remove stray 'date' text</li>
+  <li>docs: insert links to the 9.0.3 release</li>
+  <li>draw: fix non-perspective interpolation in interp()</li>
+  <li>st/mesa: implement glBitmap unpacking from a PBO, for the cache path</li>
+  <li>st/xlib: initialize the drawable size in create_xmesa_buffer()</li>
+  <li>st/mesa: fix trimming of GL_QUAD_STRIP</li>
+  <li>st/mesa: check for dummy programs in destroy_program_variants()</li>
+  <li>st/mesa: fix polygon offset state translation logic</li>
+  <li>draw: fix broken polygon offset stage</li>
+  <li>llvmpipe: add missing checks for polygon offset point/line modes</li>
+  <li>svga: always link with C++</li>
+</ul>
+
+<p>Daniel van Vugt (1):</p>
+<ul>
+  <li>gbm: Remember to init format on gbm_dri_bo_create.</li>
+</ul>
+
+<p>Eric Anholt (7):</p>
+<ul>
+  <li>i965/fs: Do a general SEND dependency workaround for the original 965.</li>
+  <li>i965/fs: Fix copy propagation with smearing.</li>
+  <li>i965/fs: Delay setup of uniform loads until after pre-regalloc scheduling.</li>
+  <li>i965/fs: Only do CSE when the dst types match.</li>
+  <li>i965/fs: Fix broken math on values loaded from uniform buffers on gen6.</li>
+  <li>mesa: Fix setup of ctx-&gt;Point.PointSprite for GLES2.</li>
+  <li>i965: Fix the W value of deprecated pointcoords on pre-gen6.</li>
+</ul>
+
+<p>Frank Henigman (1):</p>
+<ul>
+  <li>i965: Link i965_dri.so with C++ linker.</li>
+</ul>
+
+<p>Ian Romanick (3):</p>
+<ul>
+  <li>mesa: Add previously picked commit to .cherry-ignore</li>
+  <li>mesa: Modify candidate search string</li>
+  <li>egl: Allow 24-bit visuals for 32-bit RGBA8888 configs</li>
+</ul>
+
+<p>Jakub Bogusz (1):</p>
+<ul>
+  <li>vdpau-softpipe: Build correct source file - vl_winsys_xsp.c</li>
+</ul>
+
+<p>Jerome Glisse (1):</p>
+<ul>
+  <li>r600g: workaround hyperz lockup on evergreen</li>
+</ul>
+
+<p>John Kåre Alsaker (1):</p>
+<ul>
+  <li>llvmpipe: Fix creation of shared and scanout textures.</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+  <li>attrib: push/pop FRAGMENT_PROGRAM_ARB state</li>
+</ul>
+
+<p>José Fonseca (3):</p>
+<ul>
+  <li>scons: Allows choosing VS 10 or 11.</li>
+  <li>scons: Define _ALLOW_KEYWORD_MACROS on MSVC builds.</li>
+  <li>scons: Warn when using MSVS versions prior to 2012.</li>
+</ul>
+
+<p>Keith Kriewall (1):</p>
+<ul>
+  <li>scons: Fix Windows build with LLVM 3.2</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>i965: Fix Crystal Well PCI IDs.</li>
+</ul>
+
+<p>Marek Olšák (5):</p>
+<ul>
+  <li>r600g: use async DMA with a non-zero src offset</li>
+  <li>r600g: flush and invalidate htile cache when appropriate</li>
+  <li>gallium/util: add helper code for 1D integer range</li>
+  <li>r600g: always map uninitialized buffer range as unsynchronized</li>
+  <li>r600g: pad the DMA CS to a multiple of 8 dwords</li>
+</ul>
+
+<p>Martin Andersson (1):</p>
+<ul>
+  <li>winsys/radeon: Only add bo to hash table when creating flink</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+  <li>mesa: Allow ETC2/EAC formats with ARB_ES3_compatibility.</li>
+</ul>
+
+<p>Michel Dänzer (3):</p>
+<ul>
+  <li>radeonsi: Fix up and enable flat shading.</li>
+  <li>r600g/Cayman: Fix blending using destination alpha factor but non-alpha dest</li>
+  <li>radeonsi: Fix off-by-one for maximum vertex element index in some cases</li>
+</ul>
+
+<p>Tapani Pälli (2):</p>
+<ul>
+  <li>mesa: add missing case in _mesa_GetTexParameterfv()</li>
+  <li>mesa/es: NULL check in EGLImageTargetTexture2DOES</li>
+</ul>
+
+<p>Vadim Girlin (1):</p>
+<ul>
+  <li>r600g: fix check_and_set_bank_swizzle for cayman</li>
+</ul>
+
+<p>Vincent Lejeune (2):</p>
+<ul>
+  <li>r600g/llvm: Add support for UBO</li>
+  <li>r600g: Check comp_mask before merging export instructions</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes-9.1.2.html

@@ -0,0 +1,237 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.2 Release Notes / April 30th, 2013</h1>
+
+<p>
+Mesa 9.1.2 is a bug fix release which fixes bugs found since the 9.1.1 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+df2aab86ff4a510ce5b0d074caa0a59f  MesaLib-9.1.2.tar.bz2
+415c2bc3a9eb571aafbfa474ebf5a2e0  MesaLib-9.1.2.tar.gz
+b1ae5a4d9255953980bc9254f5323420  MesaLib-9.1.2.zip
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44567">Bug 44567</a> - [965gm] green artifacts when using GLSL in XBMC</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59238">Bug 59238</a> - many new symbols in libxatracker after recent automake work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59445">Bug 59445</a> - [SNB/IVB/HSW Bisected]Oglc draw-buffers2(advanced.blending.none) segfault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59495">Bug 59495</a> - [i965 Bisected]Oglc fbblit(advanced.blitFb-3d-cube.mirror.both) fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60503">Bug 60503</a> - [r300g] Unigine Heaven 3.0: all objects are black</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60510">Bug 60510</a> - Firefox 18.0.2 Crash On Nvidia GeForce2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61197">Bug 61197</a> - [SNB Bisected] kwin_gles screen corruption</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61317">Bug 61317</a> - [IVB] corrupt rendering with UBOs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61395">Bug 61395</a> - glEdgeFlag can't be set to false</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61947">Bug 61947</a> - nullpointer dereference causes xorg-server segfault when nouveau DRI driver is loaded</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62357">Bug 62357</a> - llvmpipe: Fragment Shader with &quot;return&quot; in main causes back output</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62434">Bug 62434</a> - [bisected] 3284.073] (EE) AIGLX error: dlopen of /usr/lib/xorg/modules/dri/r600_dri.so failed (/usr/lib/libllvmradeon9.2.0.so: undefined symbol: lp_build_tgsi_intrinsic)</li>
+
+<li><a href="http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=349437">Debian bug #349437</a> - mesa - FTBFS: error: 'IEEE_ONE' undeclared</li>
+
+<li><a href="http://bugzilla.redhat.com/show_bug.cgi?id=918661">Redhat bug #918661</a> - crash in routine Avogadro UI manipulation</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.1.1..mesa-9.1.2
+</pre>
+
+<p>Adam Jackson (2):</p>
+<ul>
+  <li>glx: Build with VISIBILITY_CFLAGS in automake</li>
+  <li>linux: Don't emit a .note.ABI-tag section anymore (#26663)</li>
+</ul>
+
+<p>Alan Hourihane (3):</p>
+<ul>
+  <li>Add missing GL_TEXTURE_CUBE_MAP entry in _mesa_legal_texture_dimensions</li>
+  <li>Unreference sampler object when it's currently bound to texture unit.</li>
+  <li>mesa: fix glGetInteger*(GL_SAMPLER_BINDING).</li>
+</ul>
+
+<p>Alex Deucher (1):</p>
+<ul>
+  <li>r600g: disable hyperz by default on 9.1</li>
+</ul>
+
+<p>Andreas Boll (5):</p>
+<ul>
+  <li>radeon/llvm: Link against libgallium.la to fix an undefined symbol</li>
+  <li>mesa: use ieee fp on s390 and m68k</li>
+  <li>build: Enable x86 assembler on Hurd.</li>
+  <li>osmesa: fix out-of-tree build</li>
+  <li>gallium/egl: fix out-of-tree build</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>mesa: Fix FB blitting in case of zero size src or dst rect</li>
+</ul>
+
+<p>Brian Paul (4):</p>
+<ul>
+  <li>mesa: flush current state when querying GL_EDGE_FLAG</li>
+  <li>vbo: fix crash found with shared display lists</li>
+  <li>llvmpipe: tweak CMD_BLOCK_MAX and LP_SCENE_MAX_SIZE</li>
+  <li>llvmpipe: add some scene limit sanity check assertions</li>
+</ul>
+
+<p>Carl Worth (1):</p>
+<ul>
+  <li>i965: Avoid segfault in gen6_upload_state</li>
+</ul>
+
+<p>Chris Forbes (1):</p>
+<ul>
+  <li>i965/vs: Fix Gen4/5 VUE map inconsistency with gl_ClipVertex</li>
+</ul>
+
+<p>Christoph Bumiller (4):</p>
+<ul>
+  <li>nv50: fix 3D render target setup</li>
+  <li>nv50,nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blit</li>
+  <li>nv50,nvc0: fix 3d blits, restore viewport after blit</li>
+  <li>nvc0: fix for 2d engine R source formats writing RRR1 and not R001</li>
+</ul>
+
+<p>Eric Anholt (5):</p>
+<ul>
+  <li>i965/fs: Fix register allocation for uniform pull constants in 16-wide.</li>
+  <li>i965/fs: Fix broken rendering in large shaders with UBO loads.</li>
+  <li>i965/fs: Also do the gen4 SEND dependency workaround against other SENDs.</li>
+  <li>i965: Add definitions for gen7+ data cache messages.</li>
+  <li>mesa: Disable validate_ir_tree() on release builds.</li>
+</ul>
+
+<p>Ian Romanick (5):</p>
+<ul>
+  <li>docs: Add 9.1.1 release md5sums</li>
+  <li>mesa: Add previously picked commit to .cherry-ignore</li>
+  <li>glsl: Add missing bool case in glsl_type::get_scalar_type</li>
+  <li>mesa: Note that patch dbf94d1 should't actually get picked to the 9.1 branch</li>
+  <li>mesa: Bump version to 9.1.2</li>
+</ul>
+
+<p>Jan de Groot (1):</p>
+<ul>
+  <li>dri/nouveau: fix crash in nouveau_flush</li>
+</ul>
+
+<p>José Fonseca (3):</p>
+<ul>
+  <li>autotools: Add missing top-level include dir.</li>
+  <li>mesa,gallium,egl,mapi: One definition of C99 inline/__func__ to rule them all.</li>
+  <li>include: Fix build with VS 11 (i.e, 2012).</li>
+</ul>
+
+<p>Kenneth Graunke (4):</p>
+<ul>
+  <li>i965: Fix INTEL_DEBUG=shader_time for Haswell.</li>
+  <li>i965: Specialize SURFACE_STATE creation for shader time.</li>
+  <li>i965: Make INTEL_DEBUG=shader_time use the RAW surface format.</li>
+  <li>i965: Don't use texture swizzling to force alpha to 1.0 if unnecessary.</li>
+</ul>
+
+<p>Maarten Lankhorst (2):</p>
+<ul>
+  <li>gallium/build: Fix visibility CFLAGS in automake</li>
+  <li>radeon/llvm: Do not link against libgallium when building statically.</li>
+</ul>
+
+<p>Marcin Slusarz (1):</p>
+<ul>
+  <li>dri/nouveau: NV17_3D class is not available for NV1a chipset</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>mesa: don't allocate a texture if width or height is 0 in CopyTexImage</li>
+  <li>gallium/tgsi: fix valgrind warning</li>
+  <li>mesa: handle HALF_FLOAT like FLOAT in get_tex_rgba</li>
+</ul>
+
+<p>Martin Andersson (1):</p>
+<ul>
+  <li>r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_end</li>
+</ul>
+
+<p>Matt Turner (3):</p>
+<ul>
+  <li>configure.ac: Don't check for X11 unconditionally.</li>
+  <li>configure.ac: Remove stale comment about --x-* arguments.</li>
+  <li>mesa: Implement TEXTURE_IMMUTABLE_LEVELS for ES 3.0.</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeonsi: Emit pixel shader state even when only the vertex shader changed</li>
+</ul>
+
+<p>Paul Berry (1):</p>
+<ul>
+  <li>i965: Apply depthstencil alignment workaround when doing fast clears.</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: fix return opcode handling in main function of a shader</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>intel: Fix regression in intel_create_image_from_name stride handling</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>r300g: Fix bug in OMOD optimization</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes-9.1.3.html

@@ -0,0 +1,230 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.3 Release Notes / May 21st, 2013</h1>
+
+<p>
+Mesa 9.1.3 is a bug fix release which fixes bugs found since the 9.1.1 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+952ccd03547ed72333b64e1746cf8ada  MesaLib-9.1.3.tar.bz2
+26d2f1aa8e9db388d51fcbd163c61fb7  MesaLib-9.1.3.tar.gz
+7017b7bdf0ebfd39a5c46cee7cf6b567  MesaLib-9.1.3.zip
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=39251">Bug 39251</a> - Second Life viewers from release 2.7.4.235167 to the last  3.4.0.264911 crash on start.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47478">Bug 47478</a> - [wine] GLX_DONT_CARE does not work for GLX_DRAWABLE_TYPE or GLX_RENDER_TYPE</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=56416">Bug 56416</a> - [SNB bisected] SNB hang with rc6 and hiz on glxgears (and other GL apps) immediately after xinit.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57436">Bug 57436</a> - [GLSL1.40 IVB/HSW]Piglit spec/glsl-1.40/compiler_built-in-functions/inverse-mat2.frag fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61554">Bug 61554</a> - [ivb] Mesa 9.1 performance regression on KWin's Lanczos shader</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61773">Bug 61773</a> - abort is an incredibly not-smart way to handle IR validation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62868">Bug 62868</a> - solaris build broken with missing ffsll</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62999">Bug 62999</a> - glXChooseFBConfig with GLX_DRAWABLE_TYPE, GLX_DONT_CARE fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63078">Bug 63078</a> - EGL X11 Regression: Maximum swap interval is 0 (worked with 9.0)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63447">Bug 63447</a> - [i965 Bisected]Ogles1conform/Ogles2conform/Ogles3conform cases segfault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64662">Bug 64662</a> - [SNB 9.1 Bisected]Ogles2conform GL2ExtensionTests/depth_texture_cube_map/depth_texture_cube_map.test fail</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.1.2..mesa-9.1.3
+</pre>
+
+<p>Alex Deucher (2):</p>
+<ul>
+  <li>r600g: add new richland pci ids</li>
+  <li>radeonsi: add new SI pci ids</li>
+</ul>
+
+<p>Alexander Monakov (1):</p>
+<ul>
+  <li>Honor GLX_DONT_CARE in MATCH_MASK</li>
+</ul>
+
+<p>Andreas Boll (2):</p>
+<ul>
+  <li>mesa: Add a script to generate the list of fixed bugs</li>
+  <li>mesa: add usage examples to get-pick-list and shortlog scripts</li>
+</ul>
+
+<p>Aras Pranckevicius (1):</p>
+<ul>
+  <li>GLSL: fix lower_jumps to report progress properly</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+  <li>mesa: remove platform checks around __builtin_ffs, __builtin_ffsll</li>
+  <li>gallium/u_blitter: fix is_blit_generic_supported() stencil checking</li>
+  <li>mesa: enable GL_ARB_texture_float if TEXTURE_FLOAT_ENABLED is defined</li>
+</ul>
+
+<p>Chad Versace (2):</p>
+<ul>
+  <li>egl/dri2: Fix min/max swap interval of configs</li>
+  <li>intel: Allocate hiz in intel_renderbuffer_move_to_temp()</li>
+</ul>
+
+<p>Chris Forbes (2):</p>
+<ul>
+  <li>i965/fs: Don't try to use bogus interpolation modes pre-Gen6.</li>
+  <li>mesa: don't memcmp() off the end of a cache key.</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+  <li>st/mesa: fix UBO offsets.</li>
+  <li>ralloc: don't write to memory in case of alloc fail.</li>
+</ul>
+
+<p>Eric Anholt (11):</p>
+<ul>
+  <li>i965/fs: Remove creation of a MOV instruction that's never used.</li>
+  <li>i965/fs: Move varying uniform offset compuation into the helper func.</li>
+  <li>i965: Make the constant surface interface take a normal byte size.</li>
+  <li>i965/fs: Avoid inappropriate optimization with regs_written &gt; 1.</li>
+  <li>i965/fs: Do CSE on gen7's varying-index pull constant loads.</li>
+  <li>i965/fs: Clean up the setup of gen4 simd16 message destinations.</li>
+  <li>i965/gen7: Skip resetting SOL offsets at batch start with HW contexts.</li>
+  <li>i965/gen6: Reduce updates of transform feedback offsets with HW contexts.</li>
+  <li>i965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.</li>
+  <li>i965: Fix hangs on HSW since the gen6 blorp fix.</li>
+  <li>i965: Disable write masking when setting up texturing m0.</li>
+</ul>
+
+<p>Haixia Shi (1):</p>
+<ul>
+  <li>ACTIVE_UNIFORM_MAX_LENGTH should include 3 extra characters for arrays.</li>
+</ul>
+
+<p>Ian Romanick (11):</p>
+<ul>
+  <li>docs: Add 9.1.2 release md5sums</li>
+  <li>mesa: Note that patch 0967c36 shouldn't actually get picked to the 9.1 branch</li>
+  <li>mesa: NULL check the pointer before trying to dereference it</li>
+  <li>egl/dri2: NULL check value returned by dri2_create_surface</li>
+  <li>mesa: Don't leak shared state when context initialization fails</li>
+  <li>mesa: Don't leak gl_context::BeginEnd at context destruction</li>
+  <li>mesa/swrast: Refactor no-memory error checking in blit_linear</li>
+  <li>mesa/swrast: Move free calls outside the attachment loop</li>
+  <li>intel: Don't dereference a NULL pointer of calloc fails</li>
+  <li>mesa: Note that a824692 is already back ported</li>
+  <li>mesa: Bump version to 9.1.3</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>winsys/sw/xlib: Prevent shared memory segment leakage.</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+  <li>mesa: Add new ctx-&gt;Stencil._WriteEnabled derived state flag.</li>
+  <li>i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.</li>
+  <li>mesa: Fix unpack function for ETC2_SRGB8_PUNCHTHROUGH_ALPHA1.</li>
+  <li>mesa: Add an unpack function for ARGB2101010_UINT.</li>
+  <li>mesa: Add unpack functions for R/RG/RGB [U]INT8/16/32 formats.</li>
+  <li>mesa: Add unpack functions for A/I/L/LA [U]INT8/16/32 formats.</li>
+  <li>glsl: Ignore redundant prototypes after a function's been defined.</li>
+  <li>i965: Lower textureGrad() for samplerCubeShadow.</li>
+  <li>i965/vs: Fix textureGrad() with shadow samplers on Haswell.</li>
+</ul>
+
+<p>Maarten Lankhorst (1):</p>
+<ul>
+  <li>nvc0: Fix fd leak in nvc0_create_decoder</li>
+</ul>
+
+<p>Marek Olšák (5):</p>
+<ul>
+  <li>radeonsi: add more cases for copying unsupported formats to resource_copy_region</li>
+  <li>mesa: fix glGet queries depending on derived framebuffer state (v2)</li>
+  <li>gallium/u_blitter: implement buffer clearing</li>
+  <li>r600g: initialize CMASK and HTILE with the GPU using streamout</li>
+  <li>st/mesa: depth-stencil-alpha state also depends on _NEW_BUFFERS</li>
+</ul>
+
+<p>Martin Andersson (1):</p>
+<ul>
+  <li>r600g: Fix UMAD on Cayman</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeonsi: Handle arbitrary 2-byte formats in resource_copy_region</li>
+</ul>
+
+<p>Paul Berry (7):</p>
+<ul>
+  <li>glsl: Fix array indexing when constant folding built-in functions.</li>
+  <li>i965: Reduce code duplication in handling of depth, stencil, and HiZ.</li>
+  <li>glsl/linker: fix varying packing for non-flat integer varyings.</li>
+  <li>glsl: Document lower_packed_varyings' "flat" requirement with an assert.</li>
+  <li>glsl/linker: Adapt flat varying handling in preparation for geometry shaders.</li>
+  <li>glsl/linker: Reduce scope of non-flat integer varying fix.</li>
+  <li>intel: Do a depth resolve before copying images between miptrees.</li>
+</ul>
+
+<p>Ralf Jung (1):</p>
+<ul>
+  <li>egl/x11: Fix initialisation of swap_interval</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: fix small but severe bug in handling multiple lod level strides</li>
+</ul>
+
+<p>Vadim Girlin (1):</p>
+<ul>
+  <li>gallium: handle drirc disable_glsl_line_continuations option</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes-9.1.4.html

@@ -0,0 +1,319 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.4 Release Notes / July 1st, 2013</h1>
+
+<p>
+Mesa 9.1.4 is a bug fix release which fixes bugs found since the 9.1.3 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1.  OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+TBD
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=37871">Bug 37871</a> - [bisected i965] Bus error (core dumped) on oglc texdecaltile</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=42182">Bug 42182</a> - egl/opengles1/tri_x11 renders wrong</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44958">Bug 44958</a> - [SNB IVB HSW] mesa demo test texleak bus error</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53494">Bug 53494</a> - [snb] crash in texsubimage to a large atlas in clutter</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60518">Bug 60518</a> - glDrawElements segfault when compiled into display list</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61821">Bug 61821</a> - src/mesa/drivers/dri/common/xmlpool.h:96:29: fatal error: xmlpool/options.h</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63520">Bug 63520</a> - r300g regression (RV380): Strange rendering of light sources in Penumbra  (bisected)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63701">Bug 63701</a> - [HSW] support new haswell graphics [8086:0a2e]</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64727">Bug 64727</a> - [gm45, bisected] some piglit glsl 1.10 built-in-functions tests crash</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64745">Bug 64745</a> - [llvmpipe] SIGSEGV src/gallium/state_trackers/glx/xlib/glx_api.c:1374</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64934">Bug 64934</a> - [llvmpipe] SIGSEGV src/gallium/state_trackers/glx/xlib/glx_api.c:1363</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=65173">Bug 65173</a> - segfault in _mesa_get_format_datatype and _mesa_get_color_read_type when state dumping with glretrace</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-9.1.3..mesa-9.1.4
+</pre>
+
+<p>Alan Coopersmith (2):</p>
+<ul>
+  <li>integer overflow in XF86DRIOpenConnection() [CVE-2013-1993 1/2]</li>
+  <li>integer overflow in XF86DRIGetClientDriverName() [CVE-2013-1993 2/2]</li>
+</ul>
+
+<p>Alex Deucher (3):</p>
+<ul>
+  <li>radeonsi: add support for hainan chips</li>
+  <li>radeonsi: add Hainan pci ids</li>
+  <li>winsys/radeon: add env var to disable VM on Cayman/Trinity</li>
+</ul>
+pp
+<p>Andreas Boll (1):</p>
+<ul>
+  <li>glapi: Add some missing static_dispatch="false" annotations to es_EXT.xml</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>intel: Add a null pointer check before dereferencing the pointer</li>
+</ul>
+
+<p>Armin K (1):</p>
+<ul>
+  <li>gallivm: Fix build with LLVM 3.3</li>
+</ul>
+
+<p>Brian Paul (9):</p>
+<ul>
+  <li>mesa: fix the compressed TexSubImage size checking code</li>
+  <li>st/mesa: generate GL_OUT_OF_MEMORY if we can't create the index buffer</li>
+  <li>mesa: fix error checking of DXT sRGB formats in _mesa_base_tex_format()</li>
+  <li>st/glx/xlib: check for null ctx pointer in glXIsDirect()</li>
+  <li>xlib: check for null ctx pointer in glXIsDirect()</li>
+  <li>st/glx: add null ctx check in glXDestroyContext()</li>
+  <li>xlib: add null ctx check in glXDestroyContext()</li>
+  <li>meta: move vertex array enables for mipmap generation</li>
+  <li>mesa: handle missing read buffer in _mesa_get_color_read_format/type()</li>
+</ul>
+
+<p>Bryan Cain (1):</p>
+<ul>
+  <li>nv50: initialize kick_notify callback in nv50_create</li>
+</ul>
+
+<p>Chad Versace (3):</p>
+<ul>
+  <li>egl/android: Fix error condition for EGL_ANDROID_image_native_buffer</li>
+  <li>i965: Fix glColorPointer(GL_FIXED)</li>
+  <li>intel: Return early if miptree allocation fails</li>
+</ul>
+
+<p>Chia-I Wu (1):</p>
+<ul>
+  <li>u_vbuf: fix index buffer leak</li>
+</ul>
+
+<p>Chris Forbes (8):</p>
+<ul>
+  <li>mesa: add accessor for effective stencil ref</li>
+  <li>intel: Use accessor for stencil reference values</li>
+  <li>nouveau: Use accessor for stencil reference values</li>
+  <li>radeon: Use accessor for stencil reference values</li>
+  <li>st: Use accessor for stencil reference values</li>
+  <li>swrast: Use accessor for stencil reference values</li>
+  <li>mesa: Stop clamping stencil reference value at specification time</li>
+  <li>mesa: Use accessor for stencil reference values in glGet</li>
+</ul>
+
+<p>Chí-Thanh Christopher Nguyễn (1):</p>
+<ul>
+  <li>targets/dri-i915: Force c++ linker in all cases</li>
+</ul>
+
+<p>Daniel Martin (1):</p>
+<ul>
+  <li>Fix build of swrast only without libdrm</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>i965: fix problem with constant out of bounds access (v3)</li>
+</ul>
+
+<p>Eric Anholt (10):</p>
+<ul>
+  <li>mesa: Make core Mesa allocate the texture renderbuffer wrapper.</li>
+  <li>mesa: Make gl_renderbuffers backed by EGL images use FinishRenderTexture.</li>
+  <li>i965/fs: Bake regs_written into the IR instead of recomputing it later.</li>
+  <li>i965/vs: Fix implied_mrf_writes() for integer division pre-gen6.</li>
+  <li>intel: Add support for writing to our linear-temporary-CPU-map case.</li>
+  <li>intel: Do temporary CPU maps of textures that are too big to GTT map.</li>
+  <li>intel: Avoid making tiled miptrees we won't be able to blit.</li>
+  <li>intel: Fix MRT handling of glBitmap().</li>
+  <li>intel: Fix format handling of blit glBitmap()</li>
+  <li>i965: Shut up the last release build warning.</li>
+</ul>
+
+<p>Fabian Bieler (2):</p>
+<ul>
+  <li>mesa/st: Don't copy propagate from swizzles.</li>
+  <li>mesa/program: Don't copy propagate from swizzles.</li>
+</ul>
+
+<p>Frank Henigman (1):</p>
+<ul>
+  <li>intel: initialize fs_visitor::params_remap in constructor</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>docs: Add 9.1.3 release md5sums</li>
+  <li>mesa: Bump version to 9.1.4</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>scons: Fix implicit python dependency discovery on Windows.</li>
+</ul>
+
+<p>Kenneth Graunke (17):</p>
+<ul>
+  <li>mesa: Add i965 varying index patches to .cherry-ignore.</li>
+  <li>i965: Turn brw-&gt;urb.vs_size and gs_size into local variables.</li>
+  <li>i965: Use a variable for the push constant size in kB.</li>
+  <li>i965: Update URB partitioning code for Haswell's GT3 variant.</li>
+  <li>i965: Add chipset limits for the Haswell GT3 variant.</li>
+  <li>i965: Enable the Bay Trail platform.</li>
+  <li>mesa: Add a reverted commit to cherry-ignore.</li>
+  <li>vbo: Ignore PRIMITIVE_RESTART_FIXED_INDEX for glDrawArrays().</li>
+  <li>mesa: Add a helper function for determining the restart index.</li>
+  <li>vbo: Use the new primitive restart index helper function.</li>
+  <li>i965: Use the correct restart index for fixed index mode on Haswell.</li>
+  <li>mesa: Cherry-ignore a patch that got picked but squashed.</li>
+  <li>i965: Fix can_cut_index_handle_restart_index() for byte/short types.</li>
+  <li>st/mesa: Go back to using ctx-&gt;Array.RestartIndex, not _RestartIndex.</li>
+  <li>mesa: Ignore fixed-index primitive restart in ArrayElement().</li>
+  <li>mesa: Delete the ctx-&gt;Array._RestartIndex derived state.</li>
+  <li>glsl: Bail on parsing if the #version directive is bogus.</li>
+</ul>
+
+<p>Lauri Kasanen (1):</p>
+<ul>
+  <li>r600g: Correctly initialize the shader key, v2</li>
+</ul>
+
+<p>Maarten Lankhorst (4):</p>
+<ul>
+  <li>nvc0: fix up video buffer alignment requirements</li>
+  <li>nvc0: kill assert in ppp code</li>
+  <li>nvc0: set rsvd_kick correctly</li>
+  <li>nvc0: allow frame dropping in h264</li>
+</ul>
+
+<p>Marek Olšák (7):</p>
+<ul>
+  <li>radeonsi: increase array size for shader inputs and outputs</li>
+  <li>vbo: fix possible use-after-free segfault after a VAO is deleted</li>
+  <li>glsl: fix the value of gl_MaxFragmentUniformVectors</li>
+  <li>st/mesa: initialize all program constants and UBO limits</li>
+  <li>st/mesa: initialize Const.MaxColorAttachments</li>
+  <li>st/mesa: fix a couple of issues in st_bind_ubos</li>
+  <li>mesa: declare UniformBufferBindings as an array with a static size</li>
+</ul>
+
+<p>Matt Turner (3):</p>
+<ul>
+  <li>configure.ac: Remove redundant checks of enable_dri.</li>
+  <li>configure.ac: Build dricommon for DRI gallium drivers</li>
+  <li>i965: NULL check depth_mt to quiet static analysis.</li>
+</ul>
+
+<p>Michel Dänzer (3):</p>
+<ul>
+  <li>radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE</li>
+  <li>radeonsi: Fix user clip planes</li>
+  <li>mesa: Note that two radeonsi fixes cannot be backported after all</li>
+</ul>
+
+<p>Mike Stroyan (1):</p>
+<ul>
+  <li>configure.ac: Build dricommon for gallium swrast</li>
+</ul>
+
+<p>Naohiro Aota (1):</p>
+<ul>
+  <li>xmlpool/build: Make sure to set mo properly</li>
+</ul>
+
+<p>Paul Berry (2):</p>
+<ul>
+  <li>glsl: Fix error checking on "flat" keyword to match GLSL ES 3.00, GLSL 1.50.</li>
+  <li>i965/gen7.5: Allow HW primitive restart for all primitive types.</li>
+</ul>
+
+<p>Paulo Zanoni (1):</p>
+<ul>
+  <li>i965: make GT3 machines work as GT3 instead of GT2</li>
+</ul>
+
+<p>Rodrigo Vivi (2):</p>
+<ul>
+  <li>i965: Add missing Haswell GT3 Desktop to IS_HSW_GT3 check.</li>
+  <li>i965: Adding more reserved PCI IDs for Haswell.</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: fix out-of-bounds access with mirror_clamp_to_edge address mode</li>
+</ul>
+
+<p>Stéphane Marchesin (2):</p>
+<ul>
+  <li>st/xlib: Fix upside down coordinates for CopySubBuffer</li>
+  <li>st/xlib: Flush the front buffer before doing CopySubBuffer</li>
+</ul>
+
+<p>Sven Joachim (1):</p>
+<ul>
+  <li>mesa: Fix ieee fp on Alpha</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>mesa: fix type comparison errors in sub-texture error checking code</li>
+</ul>
+
+<p>Tom Stellard (2):</p>
+<ul>
+  <li>gallivm: Fix build with LLVM &gt;= r180063</li>
+  <li>r300g/compiler: Prevent regalloc from swizzling texture operands v2</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+  <li>radeon: Initialize variables in radeon_llvm_context_init.</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes-9.1.html

@@ -14,7 +14,7 @@
 <iframe src="contents.html"></iframe>
 <div class="content">
 
-<h1>Mesa 9.1 Release Notes / date TBD</h1>
+<h1>Mesa 9.1 Release Notes / February 22, 2013</h1>
 
 <p>
 Mesa 9.1 is a new development release.
@@ -33,7 +33,9 @@ because GL_ARB_compatibility is not supported.
 
 <h2>MD5 checksums</h2>
 <pre>
-tbd
+86d40f3056f89949368764bf84aff55e  MesaLib-9.1.tar.gz
+d3891e02215422e120271d976ff1947e  MesaLib-9.1.tar.bz2
+01645f28f53351c23b0beb6c688911d8  MesaLib-9.1.zip
 </pre>
 
 
@@ -44,9 +46,19 @@ Note: some of the new features are only available with certain drivers.
 </p>
 
 <ul>
+<li>GL_ANGLE_texture_compression_dxt3</li>
+<li>GL_ANGLE_texture_compression_dxt5</li>
+<li>GL_ARB_ES3_compatibility</li>
+<li>GL_ARB_internalformat_query</li>
 <li>GL_ARB_map_buffer_alignment</li>
-<li>GL_ARB_texture_cube_map_array</li>
+<li>GL_ARB_shading_language_packing</li>
 <li>GL_ARB_texture_buffer_object_rgb32</li>
+<li>GL_ARB_texture_cube_map_array</li>
+<li>GL_EXT_color_buffer_float</li>
+<li>GL_OES_depth_texture_cube_map</li>
+<li>OpenGL 3.1 core profile support on Radeon HD2000 up to HD6000 series </li>
+<li>Multisample anti-aliasing support on Radeon X1000 series</li>
+<li>OpenGL ES 3.0 support on Intel HD Graphics 2000, 2500, 3000, and 4000</li>
 </ul>
 
 
@@ -63,6 +75,7 @@ Note: some of the new features are only available with certain drivers.
 <li>Removed swrast support for GL_NV_vertex_program</li>
 <li>Removed swrast support for GL_NV_fragment_program</li>
 <li>Removed OpenVMS support (unmaintained and broken)</li>
+<li>Removed makedepend build dependency</li>
 </ul>
 
 </div>

docs/relnotes.html

@@ -22,6 +22,7 @@ The release notes summarize what's new or changed in each Mesa release.
 
 <ul>
 <li><a href="relnotes-9.1.html">9.1 release notes</a>
+<li><a href="relnotes-9.0.3.html">9.0.3 release notes</a>
 <li><a href="relnotes-9.0.2.html">9.0.2 release notes</a>
 <li><a href="relnotes-9.0.1.html">9.0.1 release notes</a>
 <li><a href="relnotes-9.0.html">9.0 release notes</a>

include/c99_compat.h

@@ -0,0 +1,147 @@
+/**************************************************************************
+ *
+ * Copyright 2007-2013 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+#ifndef _C99_COMPAT_H_
+#define _C99_COMPAT_H_
+
+
+/*
+ * MSVC hacks.
+ */
+#if defined(_MSC_VER)
+   /*
+    * Visual Studio 2012 will complain if we define the `inline` keyword, but
+    * actually it only supports the keyword on C++.
+    *
+    * We could skip this check by defining _ALLOW_KEYWORD_MACROS, but there is
+    * probably value in checking this for other keywords.  So simply include
+    * the checking before we define it below.
+    */
+#  if _MSC_VER >= 1700
+#    include <xkeycheck.h>
+#  endif
+
+   /*
+    * XXX: MSVC has a `__restrict` keyword, but it also has a
+    * `__declspec(restrict)` modifier, so it is impossible to define a
+    * `restrict` macro without interfering with the latter.  Furthermore the
+    * MSVC standard library uses __declspec(restrict) under the _CRTRESTRICT
+    * macro.  For now resolve this issue by redefining _CRTRESTRICT, but going
+    * forward we should probably should stop using restrict, especially
+    * considering that our code does not obbey strict aliasing rules any way.
+    */
+#  include <crtdefs.h>
+#  undef _CRTRESTRICT
+#  define _CRTRESTRICT
+#endif
+
+
+/*
+ * C99 inline keyword
+ */
+#ifndef inline
+#  ifdef __cplusplus
+     /* C++ supports inline keyword */
+#  elif defined(__GNUC__)
+#    define inline __inline__
+#  elif defined(_MSC_VER)
+#    define inline __inline
+#  elif defined(__ICL)
+#    define inline __inline
+#  elif defined(__INTEL_COMPILER)
+     /* Intel compiler supports inline keyword */
+#  elif defined(__WATCOMC__) && (__WATCOMC__ >= 1100)
+#    define inline __inline
+#  elif defined(__SUNPRO_C) && defined(__C99FEATURES__)
+     /* C99 supports inline keyword */
+#  elif (__STDC_VERSION__ >= 199901L)
+     /* C99 supports inline keyword */
+#  else
+#    define inline
+#  endif
+#endif
+
+
+/*
+ * C99 restrict keyword
+ *
+ * See also:
+ * - http://cellperformance.beyond3d.com/articles/2006/05/demystifying-the-restrict-keyword.html
+ */
+#ifndef restrict
+#  if (__STDC_VERSION__ >= 199901L)
+     /* C99 */
+#  elif defined(__SUNPRO_C) && defined(__C99FEATURES__)
+     /* C99 */
+#  elif defined(__GNUC__)
+#    define restrict __restrict__
+#  elif defined(_MSC_VER)
+#    define restrict __restrict
+#  else
+#    define restrict /* */
+#  endif
+#endif
+
+
+/*
+ * C99 __func__ macro
+ */
+#ifndef __func__
+#  if (__STDC_VERSION__ >= 199901L)
+     /* C99 */
+#  elif defined(__SUNPRO_C) && defined(__C99FEATURES__)
+     /* C99 */
+#  elif defined(__GNUC__)
+#    if __GNUC__ >= 2
+#      define __func__ __FUNCTION__
+#    else
+#      define __func__ "<unknown>"
+#    endif
+#  elif defined(_MSC_VER)
+#    if _MSC_VER >= 1300
+#      define __func__ __FUNCTION__
+#    else
+#      define __func__ "<unknown>"
+#    endif
+#  else
+#    define __func__ "<unknown>"
+#  endif
+#endif
+
+
+/* Simple test case for debugging */
+#if 0
+static inline const char *
+test_c99_compat_h(const void * restrict a,
+                  const void * restrict b)
+{
+   return __func__;
+}
+#endif
+
+
+#endif /* _C99_COMPAT_H_ */

include/pci_ids/i965_pci_ids.h

@@ -28,37 +28,66 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
 CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
 CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
 CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
-CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0422, HASWELL_GT3, hsw_gt3)
 CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
 CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
-CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3)
 CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
 CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
-CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3)
+CHIPSET(0x040B, HASWELL_B_GT1, hsw_gt1)
+CHIPSET(0x041B, HASWELL_B_GT2, hsw_gt2)
+CHIPSET(0x042B, HASWELL_B_GT3, hsw_gt3)
+CHIPSET(0x040E, HASWELL_E_GT1, hsw_gt1)
+CHIPSET(0x041E, HASWELL_E_GT2, hsw_gt2)
+CHIPSET(0x042E, HASWELL_E_GT3, hsw_gt3)
 CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
 CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
-CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3)
 CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1)
 CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2)
-CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3)
 CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
 CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
-CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3)
+CHIPSET(0x0C0B, HASWELL_SDV_B_GT1, hsw_gt1)
+CHIPSET(0x0C1B, HASWELL_SDV_B_GT2, hsw_gt2)
+CHIPSET(0x0C2B, HASWELL_SDV_B_GT3, hsw_gt3)
+CHIPSET(0x0C0E, HASWELL_SDV_E_GT1, hsw_gt1)
+CHIPSET(0x0C1E, HASWELL_SDV_E_GT2, hsw_gt2)
+CHIPSET(0x0C2E, HASWELL_SDV_E_GT3, hsw_gt3)
 CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
 CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
-CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3)
 CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1)
 CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2)
-CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3)
 CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
 CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
-CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3)
-CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1)
+CHIPSET(0x0A0B, HASWELL_ULT_B_GT1, hsw_gt1)
-CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2)
+CHIPSET(0x0A1B, HASWELL_ULT_B_GT2, hsw_gt2)
-CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A2B, HASWELL_ULT_B_GT3, hsw_gt3)
-CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1)
+CHIPSET(0x0A0E, HASWELL_ULT_E_GT1, hsw_gt1)
-CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2)
+CHIPSET(0x0A1E, HASWELL_ULT_E_GT2, hsw_gt2)
-CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0A2E, HASWELL_ULT_E_GT3, hsw_gt3)
-CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1)
+CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
-CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2)
+CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
-CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3)
+CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1)
+CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2)
+CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3)
+CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
+CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
+CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3)
+CHIPSET(0x0D0B, HASWELL_CRW_B_GT1, hsw_gt1)
+CHIPSET(0x0D1B, HASWELL_CRW_B_GT2, hsw_gt2)
+CHIPSET(0x0D2B, HASWELL_CRW_B_GT3, hsw_gt3)
+CHIPSET(0x0D0E, HASWELL_CRW_E_GT1, hsw_gt1)
+CHIPSET(0x0D1E, HASWELL_CRW_E_GT2, hsw_gt2)
+CHIPSET(0x0D2E, HASWELL_CRW_E_GT3, hsw_gt3)
+CHIPSET(0x0F31, BAYTRAIL_M_1, byt)
+CHIPSET(0x0F32, BAYTRAIL_M_2, byt)
+CHIPSET(0x0F33, BAYTRAIL_M_3, byt)
+CHIPSET(0x0157, BAYTRAIL_M_4, byt)
+CHIPSET(0x0155, BAYTRAIL_D, byt)

include/pci_ids/r600_pci_ids.h

@@ -298,6 +298,10 @@ CHIPSET(0x9907, ARUBA_9907, ARUBA)
 CHIPSET(0x9908, ARUBA_9908, ARUBA)
 CHIPSET(0x9909, ARUBA_9909, ARUBA)
 CHIPSET(0x990A, ARUBA_990A, ARUBA)
+CHIPSET(0x990B, ARUBA_990B, ARUBA)
+CHIPSET(0x990C, ARUBA_990C, ARUBA)
+CHIPSET(0x990D, ARUBA_990D, ARUBA)
+CHIPSET(0x990E, ARUBA_990E, ARUBA)
 CHIPSET(0x990F, ARUBA_990F, ARUBA)
 CHIPSET(0x9910, ARUBA_9910, ARUBA)
 CHIPSET(0x9913, ARUBA_9913, ARUBA)
@@ -309,6 +313,15 @@ CHIPSET(0x9991, ARUBA_9991, ARUBA)
 CHIPSET(0x9992, ARUBA_9992, ARUBA)
 CHIPSET(0x9993, ARUBA_9993, ARUBA)
 CHIPSET(0x9994, ARUBA_9994, ARUBA)
+CHIPSET(0x9995, ARUBA_9995, ARUBA)
+CHIPSET(0x9996, ARUBA_9996, ARUBA)
+CHIPSET(0x9997, ARUBA_9997, ARUBA)
+CHIPSET(0x9998, ARUBA_9998, ARUBA)
+CHIPSET(0x9999, ARUBA_9999, ARUBA)
+CHIPSET(0x999A, ARUBA_999A, ARUBA)
+CHIPSET(0x999B, ARUBA_999B, ARUBA)
+CHIPSET(0x999C, ARUBA_999C, ARUBA)
+CHIPSET(0x999D, ARUBA_999D, ARUBA)
 CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
 CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
 CHIPSET(0x99A4, ARUBA_99A4, ARUBA)

include/pci_ids/radeonsi_pci_ids.h

@@ -28,6 +28,7 @@ CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN)
 
 CHIPSET(0x6820, VERDE_6820, VERDE)
 CHIPSET(0x6821, VERDE_6821, VERDE)
+CHIPSET(0x6822, VERDE_6822, VERDE)
 CHIPSET(0x6823, VERDE_6823, VERDE)
 CHIPSET(0x6824, VERDE_6824, VERDE)
 CHIPSET(0x6825, VERDE_6825, VERDE)
@@ -35,14 +36,37 @@ CHIPSET(0x6826, VERDE_6826, VERDE)
 CHIPSET(0x6827, VERDE_6827, VERDE)
 CHIPSET(0x6828, VERDE_6828, VERDE)
 CHIPSET(0x6829, VERDE_6829, VERDE)
+CHIPSET(0x682A, VERDE_682A, VERDE)
 CHIPSET(0x682B, VERDE_682B, VERDE)
 CHIPSET(0x682D, VERDE_682D, VERDE)
 CHIPSET(0x682F, VERDE_682F, VERDE)
 CHIPSET(0x6830, VERDE_6830, VERDE)
 CHIPSET(0x6831, VERDE_6831, VERDE)
+CHIPSET(0x6835, VERDE_6835, VERDE)
 CHIPSET(0x6837, VERDE_6837, VERDE)
 CHIPSET(0x6838, VERDE_6838, VERDE)
 CHIPSET(0x6839, VERDE_6839, VERDE)
 CHIPSET(0x683B, VERDE_683B, VERDE)
 CHIPSET(0x683D, VERDE_683D, VERDE)
 CHIPSET(0x683F, VERDE_683F, VERDE)
+
+CHIPSET(0x6600, OLAND_6600, OLAND)
+CHIPSET(0x6601, OLAND_6601, OLAND)
+CHIPSET(0x6602, OLAND_6602, OLAND)
+CHIPSET(0x6603, OLAND_6603, OLAND)
+CHIPSET(0x6606, OLAND_6606, OLAND)
+CHIPSET(0x6607, OLAND_6607, OLAND)
+CHIPSET(0x6610, OLAND_6610, OLAND)
+CHIPSET(0x6611, OLAND_6611, OLAND)
+CHIPSET(0x6613, OLAND_6613, OLAND)
+CHIPSET(0x6620, OLAND_6620, OLAND)
+CHIPSET(0x6621, OLAND_6621, OLAND)
+CHIPSET(0x6623, OLAND_6623, OLAND)
+CHIPSET(0x6631, OLAND_6631, OLAND)
+
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)

scons/custom.py

@@ -95,7 +95,7 @@ def createConvenienceLibBuilder(env):
 
 # TODO: handle import statements with multiple modules
 # TODO: handle from import statements
-import_re = re.compile(r'^import\s+(\S+)$', re.M)
+import_re = re.compile(r'^\s*import\s+(\S+)\s*$', re.M)
 
 def python_scan(node, env, path):
     # http://www.scons.org/doc/0.98.5/HTML/scons-user/c2781.html#AEN2789
@@ -113,6 +113,7 @@ def python_scan(node, env, path):
             if os.path.exists(file):
                 results.append(env.File(file))
                 break
+    #print node, map(str, results)
     return results
 
 python_scanner = SCons.Scanner.Scanner(function = python_scan, skeys = ['.py'])

scons/gallium.py

@@ -289,6 +289,7 @@ def generate(env):
                 '_CRT_SECURE_NO_DEPRECATE',
                 '_SCL_SECURE_NO_WARNINGS',
                 '_SCL_SECURE_NO_DEPRECATE',
+                '_ALLOW_KEYWORD_MACROS',
             ]
         if env['build'] in ('debug', 'checked'):
             cppdefines += ['_DEBUG']
@@ -401,6 +402,8 @@ def generate(env):
               '/Oi', # enable intrinsic functions
             ]
         else:
+            if distutils.version.LooseVersion(env['MSVC_VERSION']) < distutils.version.LooseVersion('11.0'):
+                print 'scons: warning: Visual Studio versions prior to 2012 are known to produce incorrect code when optimizations are enabled ( https://bugs.freedesktop.org/show_bug.cgi?id=58718 )'
             ccflags += [
                 '/O2', # optimize for speed
             ]
@@ -530,7 +533,7 @@ def generate(env):
     env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
     env.PkgCheckModules('DRM', ['libdrm >= 2.4.24'])
     env.PkgCheckModules('DRM_INTEL', ['libdrm_intel >= 2.4.30'])
-    env.PkgCheckModules('DRM_RADEON', ['libdrm_radeon >= 2.4.40'])
+    env.PkgCheckModules('DRM_RADEON', ['libdrm_radeon >= 2.4.42'])
     env.PkgCheckModules('XORG', ['xorg-server >= 1.6.0'])
     env.PkgCheckModules('KMS', ['libkms >= 2.4.24'])
     env.PkgCheckModules('UDEV', ['libudev > 150'])

scons/llvm.py

@@ -92,7 +92,19 @@ def generate(env):
             'HAVE_STDINT_H',
         ])
         env.Prepend(LIBPATH = [os.path.join(llvm_dir, 'lib')])
-        if llvm_version >= distutils.version.LooseVersion('3.0'):
+        if llvm_version >= distutils.version.LooseVersion('3.2'):
+            # 3.2
+            env.Prepend(LIBS = [
+                'LLVMBitWriter', 'LLVMX86Disassembler', 'LLVMX86AsmParser',
+                'LLVMX86CodeGen', 'LLVMX86Desc', 'LLVMSelectionDAG',
+                'LLVMAsmPrinter', 'LLVMMCParser', 'LLVMX86AsmPrinter',
+                'LLVMX86Utils', 'LLVMX86Info', 'LLVMJIT',
+                'LLVMExecutionEngine', 'LLVMCodeGen', 'LLVMScalarOpts',
+                'LLVMInstCombine', 'LLVMTransformUtils', 'LLVMipa',
+                'LLVMAnalysis', 'LLVMTarget', 'LLVMMC', 'LLVMCore',
+                'LLVMSupport', 'LLVMRuntimeDyld', 'LLVMObject'
+            ])
+        elif llvm_version >= distutils.version.LooseVersion('3.0'):
             # 3.0
             env.Prepend(LIBS = [
                 'LLVMBitWriter', 'LLVMX86Disassembler', 'LLVMX86AsmParser',

src/egl/drivers/dri2/egl_dri2.c

@@ -195,7 +195,14 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
       for (i = 0; attr_list[i] != EGL_NONE; i += 2)
          _eglSetConfigKey(&base, attr_list[i], attr_list[i+1]);
 
-   if (depth > 0 && depth != base.BufferSize)
+   /* Allow a 24-bit RGB visual to match a 32-bit RGBA EGLConfig.  Otherwise
+    * it will only match a 32-bit RGBA visual.  On a composited window manager
+    * on X11, this will make all of the EGLConfigs with destination alpha get
+    * blended by the compositor.  This is probably not what the application
+    * wants... especially on drivers that only have 32-bit RGBA EGLConfigs!
+    */
+   if (depth > 0 && depth != base.BufferSize
+       && !(depth == 24 && base.BufferSize == 32))
       return NULL;
 
    if (rgba_masks && memcmp(rgba_masks, dri_masks, sizeof(dri_masks)))
@@ -214,6 +221,9 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
    base.RenderableType = disp->ClientAPIs;
    base.Conformant = disp->ClientAPIs;
 
+   base.MinSwapInterval = dri2_dpy->min_swap_interval;
+   base.MaxSwapInterval = dri2_dpy->max_swap_interval;
+
    if (!_eglValidateConfig(&base, EGL_FALSE)) {
       _eglLog(_EGL_DEBUG, "DRI2: failed to validate config %d", id);
       return NULL;
@@ -261,9 +271,6 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
 
    if (double_buffer) {
       surface_type &= ~EGL_PIXMAP_BIT;
-
-      conf->base.MinSwapInterval = dri2_dpy->min_swap_interval;
-      conf->base.MaxSwapInterval = dri2_dpy->max_swap_interval;
    }
 
    conf->base.SurfaceType |= surface_type;

src/egl/drivers/dri2/platform_android.c

@@ -338,7 +338,7 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
 }
 
 static _EGLImage *
-dri2_create_image_android_native_buffer(_EGLDisplay *disp,
+dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
                                         struct ANativeWindowBuffer *buf)
 {
    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
@@ -346,6 +346,18 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp,
    int name;
    EGLint format;
 
+   if (ctx != NULL) {
+      /* From the EGL_ANDROID_image_native_buffer spec:
+       *
+       *     * If <target> is EGL_NATIVE_BUFFER_ANDROID and <ctx> is not
+       *       EGL_NO_CONTEXT, the error EGL_BAD_CONTEXT is generated.
+       */
+      _eglError(EGL_BAD_CONTEXT, "eglCreateEGLImageKHR: for "
+                "EGL_NATIVE_BUFFER_ANDROID, the context must be "
+                "EGL_NO_CONTEXT");
+      return NULL;
+   }
+
    if (!buf || buf->common.magic != ANDROID_NATIVE_BUFFER_MAGIC ||
        buf->common.version != sizeof(*buf)) {
       _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
@@ -417,7 +429,7 @@ droid_create_image_khr(_EGLDriver *drv, _EGLDisplay *disp,
 {
    switch (target) {
    case EGL_NATIVE_BUFFER_ANDROID:
-      return dri2_create_image_android_native_buffer(disp,
+      return dri2_create_image_android_native_buffer(disp, ctx,
             (struct ANativeWindowBuffer *) buffer);
    default:
       return dri2_create_image_khr(drv, disp, ctx, target, buffer, attr_list);

src/egl/drivers/dri2/platform_wayland.c

@@ -446,6 +446,7 @@ dri2_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
 {
    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
    struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
+   __DRIbuffer buffer;
    int i, ret = 0;
 
    while (dri2_surf->frame_callback && ret != -1)
@@ -463,6 +464,13 @@ dri2_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
       if (dri2_surf->color_buffers[i].age > 0)
          dri2_surf->color_buffers[i].age++;
 
+   /* Make sure we have a back buffer in case we're swapping without ever
+    * rendering. */
+   if (get_back_bo(dri2_surf, &buffer) < 0) {
+      _eglError(EGL_BAD_ALLOC, "dri2_swap_buffers");
+      return EGL_FALSE;
+   }
+
    dri2_surf->back->age = 1;
    dri2_surf->current = dri2_surf->back;
    dri2_surf->back = NULL;

src/egl/drivers/dri2/platform_x11.c

@@ -284,14 +284,15 @@ dri2_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
 
    surf = dri2_create_surface(drv, disp, EGL_WINDOW_BIT, conf,
                               window, attrib_list);
+   if (surf != NULL) {
+      /* When we first create the DRI2 drawable, its swap interval on the
+       * server side is 1.
+       */
+      surf->SwapInterval = 1;
 
-   /* When we first create the DRI2 drawable, its swap interval on the server
+      /* Override that with a driconf-set value. */
-    * side is 1.
+      drv->API.SwapInterval(drv, disp, surf, dri2_dpy->default_swap_interval);
-    */
+   }
-   surf->SwapInterval = 1;
-
-   /* Override that with a driconf-set value. */
-   drv->API.SwapInterval(drv, disp, surf, dri2_dpy->default_swap_interval);
 
    return surf;
 }
@@ -1162,6 +1163,8 @@ dri2_initialize_x11_dri2(_EGLDriver *drv, _EGLDisplay *disp)
    if (!dri2_create_screen(disp))
       goto cleanup_fd;
 
+   dri2_setup_swap_interval(dri2_dpy);
+
    if (dri2_dpy->conn) {
       if (!dri2_add_configs_for_visuals(dri2_dpy, disp))
 	 goto cleanup_configs;
@@ -1181,8 +1184,6 @@ dri2_initialize_x11_dri2(_EGLDriver *drv, _EGLDisplay *disp)
    disp->VersionMajor = 1;
    disp->VersionMinor = 4;
 
-   dri2_setup_swap_interval(dri2_dpy);
-
    return EGL_TRUE;
 
  cleanup_configs:

src/egl/main/eglcompiler.h

@@ -31,6 +31,9 @@
 #define EGLCOMPILER_INCLUDED
 
 
+#include "c99_compat.h" /* inline, __func__, etc. */
+
+
 /**
  * Get standard integer types
  */
@@ -62,30 +65,7 @@
 #endif
 
 
-/**
+/* XXX: Use standard `inline` keyword instead */
- * Function inlining
- */
-#ifndef inline
-#  ifdef __cplusplus
-     /* C++ supports inline keyword */
-#  elif defined(__GNUC__)
-#    define inline __inline__
-#  elif defined(_MSC_VER)
-#    define inline __inline
-#  elif defined(__ICL)
-#    define inline __inline
-#  elif defined(__INTEL_COMPILER)
-     /* Intel compiler supports inline keyword */
-#  elif defined(__WATCOMC__) && (__WATCOMC__ >= 1100)
-#    define inline __inline
-#  elif defined(__SUNPRO_C) && defined(__C99FEATURES__)
-     /* C99 supports inline keyword */
-#  elif (__STDC_VERSION__ >= 199901L)
-     /* C99 supports inline keyword */
-#  else
-#    define inline
-#  endif
-#endif
 #ifndef INLINE
 #  define INLINE inline
 #endif
@@ -104,21 +84,9 @@
 #  endif
 #endif
 
-/**
+/* XXX: Use standard `__func__` instead */
- * The __FUNCTION__ gcc variable is generally only used for debugging.
- * If we're not using gcc, define __FUNCTION__ as a cpp symbol here.
- * Don't define it if using a newer Windows compiler.
- */
 #ifndef __FUNCTION__
-# if (!defined __GNUC__) && (!defined __xlC__) && \
+#  define __FUNCTION__ __func__
-      (!defined(_MSC_VER) || _MSC_VER < 1300)
-#  if (__STDC_VERSION__ >= 199901L) /* C99 */ || \
-    (defined(__SUNPRO_C) && defined(__C99FEATURES__))
-#   define __FUNCTION__ __func__
-#  else
-#   define __FUNCTION__ "<unknown>"
-#  endif
-# endif
 #endif
 
 #endif /* EGLCOMPILER_INCLUDED */

src/gallium/auxiliary/Makefile.am

@@ -7,7 +7,10 @@ noinst_LTLIBRARIES = libgallium.la
 
 AM_CFLAGS = \
 	-I$(top_srcdir)/src/gallium/auxiliary/util \
-	$(GALLIUM_CFLAGS)
+	$(GALLIUM_CFLAGS) \
+	$(VISIBILITY_CFLAGS)
+
+AM_CXXFLAGS = $(VISIBILITY_CXXFLAGS)
 
 libgallium_la_SOURCES = \
 	$(C_SOURCES) \
@@ -18,7 +21,7 @@ if HAVE_MESA_LLVM
 AM_CFLAGS += \
 	$(LLVM_CFLAGS)
 
-AM_CXXFLAGS = \
+AM_CXXFLAGS += \
 	$(GALLIUM_CFLAGS) \
 	$(LLVM_CXXFLAGS)
 

src/gallium/auxiliary/draw/draw_pipe_clip.c

@@ -167,12 +167,17 @@ static void interp( const struct clip_stage *clip,
    {
       int k;
       t_nopersp = t;
-      for (k = 0; k < 2; k++)
+      /* find either in.x != out.x or in.y != out.y */
+      for (k = 0; k < 2; k++) {
          if (in->clip[k] != out->clip[k]) {
-            t_nopersp = (dst->clip[k] - out->clip[k]) /
+            /* do divide by W, then compute linear interpolation factor */
-               (in->clip[k] - out->clip[k]);
+            float in_coord = in->clip[k] / in->clip[3];
+            float out_coord = out->clip[k] / out->clip[3];
+            float dst_coord = dst->clip[k] / dst->clip[3];
+            t_nopersp = (dst_coord - out_coord) / (in_coord - out_coord);
             break;
          }
+      }
    }
 
    /* Other attributes

src/gallium/auxiliary/draw/draw_pipe_offset.c

@@ -127,10 +127,44 @@ static void offset_first_tri( struct draw_stage *stage,
 			      struct prim_header *header )
 {
    struct offset_stage *offset = offset_stage(stage);
+   const struct pipe_rasterizer_state *rast = stage->draw->rasterizer;
+   unsigned fill_mode = rast->fill_front;
+   boolean do_offset;
+
+   if (rast->fill_back != rast->fill_front) {
+      /* Need to check for back-facing triangle */
+      boolean ccw = header->det < 0.0f;
+      if (ccw != rast->front_ccw)
+         fill_mode = rast->fill_back;
+   }
+
+   /* Now determine if we need to do offsetting for the point/line/fill mode */
+   switch (fill_mode) {
+   case PIPE_POLYGON_MODE_FILL:
+      do_offset = rast->offset_tri;
+      break;
+   case PIPE_POLYGON_MODE_LINE:
+      do_offset = rast->offset_line;
+      break;
+   case PIPE_POLYGON_MODE_POINT:
+      do_offset = rast->offset_point;
+      break;
+   default:
+      assert(!"invalid fill_mode in offset_first_tri()");
+      do_offset = rast->offset_tri;
+   }
+
+   if (do_offset) {
+      offset->scale = rast->offset_scale;
+      offset->clamp = rast->offset_clamp;
+      offset->units = (float) (rast->offset_units * stage->draw->mrd);
+   }
+   else {
+      offset->scale = 0.0f;
+      offset->clamp = 0.0f;
+      offset->units = 0.0f;
+   }
 
-   offset->units = (float) (stage->draw->rasterizer->offset_units * stage->draw->mrd);
-   offset->scale = stage->draw->rasterizer->offset_scale;
-   offset->clamp = stage->draw->rasterizer->offset_clamp;
 
    stage->tri = offset_tri;
    stage->tri( stage, header );

src/gallium/auxiliary/gallivm/lp_bld_debug.cpp

@@ -55,6 +55,10 @@
 #include <llvm/MC/MCRegisterInfo.h>
 #endif /* HAVE_LLVM >= 0x0301 */
 
+#if HAVE_LLVM >= 0x0303
+#include <llvm/ADT/OwningPtr.h>
+#endif
+
 #include "util/u_math.h"
 #include "util/u_debug.h"
 

src/gallium/auxiliary/gallivm/lp_bld_misc.cpp

@@ -60,6 +60,12 @@
 #include <llvm/Target/TargetSelect.h>
 #endif /* HAVE_LLVM < 0x0300 */
 
+#if HAVE_LLVM >= 0x0303
+#include <llvm/IR/IRBuilder.h>
+#include <llvm/IR/Module.h>
+#include <llvm/Support/CBindingWrapping.h>
+#endif
+
 #include "pipe/p_config.h"
 #include "util/u_debug.h"
 #include "util/u_cpu_detect.h"

src/gallium/auxiliary/gallivm/lp_bld_sample.c

@@ -867,7 +867,7 @@ lp_build_get_level_stride_vec(struct lp_build_sample_context *bld,
       stride = bld->int_coord_bld.undef;
       for (i = 0; i < bld->num_lods; i++) {
          LLVMValueRef indexi = lp_build_const_int32(bld->gallivm, i);
-         LLVMValueRef indexo = lp_build_const_int32(bld->gallivm, i);
+         LLVMValueRef indexo = lp_build_const_int32(bld->gallivm, 4 * i);
          indexes[1] = LLVMBuildExtractElement(builder, level, indexi, "");
          stride1 = LLVMBuildGEP(builder, stride_array, indexes, 2, "");
          stride1 = LLVMBuildLoad(builder, stride1, "");

src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c

@@ -406,7 +406,6 @@ lp_build_sample_wrap_linear(struct lp_build_sample_context *bld,
 
    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
       {
-         LLVMValueRef min, max;
          struct lp_build_context abs_coord_bld = bld->coord_bld;
          abs_coord_bld.type.sign = FALSE;
          coord = lp_build_abs(coord_bld, coord);
@@ -416,16 +415,18 @@ lp_build_sample_wrap_linear(struct lp_build_sample_context *bld,
             coord = lp_build_mul(coord_bld, coord, length_f);
          }
 
-         /* clamp to [0.5, length - 0.5] */
+         /* clamp to length max */
-         min = half;
+         coord = lp_build_min(coord_bld, coord, length_f);
-         max = lp_build_sub(coord_bld, length_f, min);
+         /* subtract 0.5 */
-         coord = lp_build_clamp(coord_bld, coord, min, max);
-
          coord = lp_build_sub(coord_bld, coord, half);
+         /* clamp to [0, length - 0.5] */
+         coord = lp_build_max(coord_bld, coord, coord_bld->zero);
 
          /* convert to int, compute lerp weight */
          lp_build_ifloor_fract(&abs_coord_bld, coord, &coord0, &weight);
          coord1 = lp_build_add(int_coord_bld, coord0, int_coord_bld->one);
+         /* coord1 = min(coord1, length-1) */
+         coord1 = lp_build_min(int_coord_bld, coord1, length_minus_one);
       }
       break;
 

src/gallium/auxiliary/gallivm/lp_bld_tgsi.h

@@ -240,6 +240,7 @@ struct lp_exec_mask {
    struct lp_build_context *bld;
 
    boolean has_mask;
+   boolean ret_in_main;
 
    LLVMTypeRef int_vec_type;
 

src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c

@@ -73,6 +73,7 @@ static void lp_exec_mask_init(struct lp_exec_mask *mask, struct lp_build_context
 
    mask->bld = bld;
    mask->has_mask = FALSE;
+   mask->ret_in_main = FALSE;
    mask->cond_stack_size = 0;
    mask->loop_stack_size = 0;
    mask->call_stack_size = 0;
@@ -108,7 +109,7 @@ static void lp_exec_mask_update(struct lp_exec_mask *mask)
    } else
       mask->exec_mask = mask->cond_mask;
 
-   if (mask->call_stack_size) {
+   if (mask->call_stack_size || mask->ret_in_main) {
       mask->exec_mask = LLVMBuildAnd(builder,
                                      mask->exec_mask,
                                      mask->ret_mask,
@@ -117,7 +118,8 @@ static void lp_exec_mask_update(struct lp_exec_mask *mask)
 
    mask->has_mask = (mask->cond_stack_size > 0 ||
                      mask->loop_stack_size > 0 ||
-                     mask->call_stack_size > 0);
+                     mask->call_stack_size > 0 ||
+                     mask->ret_in_main);
 }
 
 static void lp_exec_mask_cond_push(struct lp_exec_mask *mask,
@@ -348,11 +350,23 @@ static void lp_exec_mask_ret(struct lp_exec_mask *mask, int *pc)
    LLVMBuilderRef builder = mask->bld->gallivm->builder;
    LLVMValueRef exec_mask;
 
-   if (mask->call_stack_size == 0) {
+   if (mask->cond_stack_size == 0 &&
+       mask->loop_stack_size == 0 &&
+       mask->call_stack_size == 0) {
       /* returning from main() */
       *pc = -1;
       return;
    }
+
+   if (mask->call_stack_size == 0) {
+      /*
+       * This requires special handling since we need to ensure
+       * we don't drop the mask even if we have no call stack
+       * (e.g. after a ret in a if clause after the endif)
+       */
+      mask->ret_in_main = TRUE;
+   }
+
    exec_mask = LLVMBuildNot(builder,
                             mask->exec_mask,
                             "ret");

src/gallium/auxiliary/tgsi/tgsi_text.c

@@ -1569,7 +1569,7 @@ tgsi_text_translate(
    struct tgsi_token *tokens,
    uint num_tokens )
 {
-   struct translate_ctx ctx;
+   struct translate_ctx ctx = {0};
 
    ctx.text = text;
    ctx.cur = text;

src/gallium/auxiliary/util/u_blitter.c

@@ -100,7 +100,7 @@ struct blitter_context_priv
    void *velem_state;
    void *velem_uint_state;
    void *velem_sint_state;
-   void *velem_state_readbuf;
+   void *velem_state_readbuf[4]; /**< X, XY, XYZ, XYZW */
 
    /* Sampler state. */
    void *sampler_state, *sampler_state_linear;
@@ -277,9 +277,19 @@ struct blitter_context *util_blitter_create(struct pipe_context *pipe)
    }
 
    if (ctx->has_stream_out) {
-      velem[0].src_format = PIPE_FORMAT_R32_UINT;
+      static enum pipe_format formats[4] = {
-      velem[0].vertex_buffer_index = ctx->base.vb_slot;
+         PIPE_FORMAT_R32_UINT,
-      ctx->velem_state_readbuf = pipe->create_vertex_elements_state(pipe, 1, &velem[0]);
+         PIPE_FORMAT_R32G32_UINT,
+         PIPE_FORMAT_R32G32B32_UINT,
+         PIPE_FORMAT_R32G32B32A32_UINT
+      };
+
+      for (i = 0; i < 4; i++) {
+         velem[0].src_format = formats[i];
+         velem[0].vertex_buffer_index = ctx->base.vb_slot;
+         ctx->velem_state_readbuf[i] =
+               pipe->create_vertex_elements_state(pipe, 1, &velem[0]);
+      }
    }
 
    /* fragment shaders are created on-demand */
@@ -344,8 +354,11 @@ void util_blitter_destroy(struct blitter_context *blitter)
       pipe->delete_vertex_elements_state(pipe, ctx->velem_sint_state);
       pipe->delete_vertex_elements_state(pipe, ctx->velem_uint_state);
    }
-   if (ctx->velem_state_readbuf)
+   for (i = 0; i < 4; i++) {
-      pipe->delete_vertex_elements_state(pipe, ctx->velem_state_readbuf);
+      if (ctx->velem_state_readbuf[i]) {
+         pipe->delete_vertex_elements_state(pipe, ctx->velem_state_readbuf[i]);
+      }
+   }
 
    for (i = 0; i < PIPE_MAX_TEXTURE_TYPES; i++) {
       if (ctx->fs_texfetch_col[i])
@@ -1120,18 +1133,17 @@ static boolean is_blit_generic_supported(struct blitter_context *blitter,
 
    if (dst) {
       unsigned bind;
-      boolean is_stencil;
       const struct util_format_description *desc =
             util_format_description(dst_format);
-
+      boolean dst_has_stencil = util_format_has_stencil(desc);
-      is_stencil = util_format_has_stencil(desc);
 
       /* Stencil export must be supported for stencil copy. */
-      if ((mask & PIPE_MASK_S) && is_stencil && !ctx->has_stencil_export) {
+      if ((mask & PIPE_MASK_S) && dst_has_stencil &&
+          !ctx->has_stencil_export) {
          return FALSE;
       }
 
-      if (is_stencil || util_format_has_depth(desc))
+      if (dst_has_stencil || util_format_has_depth(desc))
          bind = PIPE_BIND_DEPTH_STENCIL;
       else
          bind = PIPE_BIND_RENDER_TARGET;
@@ -1153,15 +1165,18 @@ static boolean is_blit_generic_supported(struct blitter_context *blitter,
       }
 
       /* Check stencil sampler support for stencil copy. */
-      if (util_format_has_stencil(util_format_description(src_format))) {
+      if (mask & PIPE_MASK_S) {
-         enum pipe_format stencil_format =
+         if (util_format_has_stencil(util_format_description(src_format))) {
+            enum pipe_format stencil_format =
                util_format_stencil_only(src_format);
-         assert(stencil_format != PIPE_FORMAT_NONE);
+            assert(stencil_format != PIPE_FORMAT_NONE);
 
-         if (stencil_format != src_format &&
+            if (stencil_format != src_format &&
-             !screen->is_format_supported(screen, stencil_format, src->target,
+                !screen->is_format_supported(screen, stencil_format,
-                                 src->nr_samples, PIPE_BIND_SAMPLER_VIEW)) {
+                                             src->target, src->nr_samples,
-            return FALSE;
+                                             PIPE_BIND_SAMPLER_VIEW)) {
+               return FALSE;
+            }
          }
       }
    }
@@ -1714,7 +1729,7 @@ void util_blitter_copy_buffer(struct blitter_context *blitter,
    vb.stride = 4;
 
    pipe->set_vertex_buffers(pipe, ctx->base.vb_slot, 1, &vb);
-   pipe->bind_vertex_elements_state(pipe, ctx->velem_state_readbuf);
+   pipe->bind_vertex_elements_state(pipe, ctx->velem_state_readbuf[0]);
    pipe->bind_vs_state(pipe, ctx->vs_pos_only);
    if (ctx->has_geometry_shader)
       pipe->bind_gs_state(pipe, NULL);
@@ -1731,6 +1746,66 @@ void util_blitter_copy_buffer(struct blitter_context *blitter,
    pipe_so_target_reference(&so_target, NULL);
 }
 
+void util_blitter_clear_buffer(struct blitter_context *blitter,
+                               struct pipe_resource *dst,
+                               unsigned offset, unsigned size,
+                               unsigned num_channels,
+                               const union pipe_color_union *clear_value)
+{
+   struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
+   struct pipe_context *pipe = ctx->base.pipe;
+   struct pipe_vertex_buffer vb = {0};
+   struct pipe_stream_output_target *so_target;
+
+   assert(num_channels >= 1);
+   assert(num_channels <= 4);
+
+   /* IMPORTANT:  DON'T DO ANY BOUNDS CHECKING HERE!
+    *
+    * R600 uses this to initialize texture resources, so width0 might not be
+    * what you think it is.
+    */
+
+   /* Streamout is required. */
+   if (!ctx->has_stream_out) {
+      assert(!"Streamout unsupported in util_blitter_clear_buffer()");
+      return;
+   }
+
+   /* Some alignment is required. */
+   if (offset % 4 != 0 || size % 4 != 0) {
+      assert(!"Bad alignment in util_blitter_clear_buffer()");
+      return;
+   }
+
+   u_upload_data(ctx->upload, 0, num_channels*4, clear_value,
+                 &vb.buffer_offset, &vb.buffer);
+   vb.stride = 0;
+
+   blitter_set_running_flag(ctx);
+   blitter_check_saved_vertex_states(ctx);
+   blitter_disable_render_cond(ctx);
+
+   pipe->set_vertex_buffers(pipe, ctx->base.vb_slot, 1, &vb);
+   pipe->bind_vertex_elements_state(pipe,
+                                    ctx->velem_state_readbuf[num_channels-1]);
+   pipe->bind_vs_state(pipe, ctx->vs_pos_only);
+   if (ctx->has_geometry_shader)
+      pipe->bind_gs_state(pipe, NULL);
+   pipe->bind_rasterizer_state(pipe, ctx->rs_discard_state);
+
+   so_target = pipe->create_stream_output_target(pipe, dst, offset, size);
+   pipe->set_stream_output_targets(pipe, 1, &so_target, 0);
+
+   util_draw_arrays(pipe, PIPE_PRIM_POINTS, 0, size / 4);
+
+   blitter_restore_vertex_states(ctx);
+   blitter_restore_render_cond(ctx);
+   blitter_unset_running_flag(ctx);
+   pipe_so_target_reference(&so_target, NULL);
+   pipe_resource_reference(&vb.buffer, NULL);
+}
+
 /* probably radeon specific */
 void util_blitter_custom_resolve_color(struct blitter_context *blitter,
 				       struct pipe_resource *dst,

src/gallium/auxiliary/util/u_blitter.h

@@ -276,7 +276,7 @@ void util_blitter_default_src_texture(struct pipe_sampler_view *src_templ,
 
 /**
  * Copy data from one buffer to another using the Stream Output functionality.
- * Some alignment is required, otherwise software fallback is used.
+ * 4-byte alignment is required, otherwise software fallback is used.
  */
 void util_blitter_copy_buffer(struct blitter_context *blitter,
                               struct pipe_resource *dst,
@@ -285,6 +285,22 @@ void util_blitter_copy_buffer(struct blitter_context *blitter,
                               unsigned srcx,
                               unsigned size);
 
+/**
+ * Clear the contents of a buffer using the Stream Output functionality.
+ * 4-byte alignment is required.
+ *
+ * "num_channels" can be 1, 2, 3, or 4, and specifies if the clear value is
+ * R, RG, RGB, or RGBA.
+ *
+ * For each element, only "num_channels" components of "clear_value" are
+ * copied to the buffer, then the offset is incremented by num_channels*4.
+ */
+void util_blitter_clear_buffer(struct blitter_context *blitter,
+                               struct pipe_resource *dst,
+                               unsigned offset, unsigned size,
+                               unsigned num_channels,
+                               const union pipe_color_union *clear_value);
+
 /**
  * Clear a region of a (color) surface to a constant value.
  *

src/gallium/auxiliary/util/u_range.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright 2013 Marek Olšák <maraeo@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/**
+ * @file
+ * 1D integer range, capable of the union and intersection operations.
+ *
+ * It only maintains a single interval which is extended when the union is
+ * done. This implementation is partially thread-safe (readers are not
+ * protected by a lock).
+ *
+ * @author Marek Olšák
+ */
+
+#ifndef U_RANGE_H
+#define U_RANGE_H
+
+#include "os/os_thread.h"
+
+struct util_range {
+   unsigned start; /* inclusive */
+   unsigned end; /* exclusive */
+
+   /* for the range to be consistent with multiple contexts: */
+   pipe_mutex write_mutex;
+};
+
+
+static INLINE void
+util_range_set_empty(struct util_range *range)
+{
+   range->start = ~0;
+   range->end = 0;
+}
+
+/* This is like a union of two sets. */
+static INLINE void
+util_range_add(struct util_range *range, unsigned start, unsigned end)
+{
+   if (start < range->start || end > range->end) {
+      pipe_mutex_lock(range->write_mutex);
+      range->start = MIN2(start, range->start);
+      range->end = MAX2(end, range->end);
+      pipe_mutex_unlock(range->write_mutex);
+   }
+}
+
+static INLINE boolean
+util_ranges_intersect(struct util_range *range, unsigned start, unsigned end)
+{
+   return MAX2(start, range->start) < MIN2(end, range->end);
+}
+
+
+/* Init/deinit */
+
+static INLINE void
+util_range_init(struct util_range *range)
+{
+   pipe_mutex_init(range->write_mutex);
+   util_range_set_empty(range);
+}
+
+static INLINE void
+util_range_destroy(struct util_range *range)
+{
+   pipe_mutex_destroy(range->write_mutex);
+}
+
+#endif

src/gallium/auxiliary/util/u_surface.c

@@ -421,10 +421,10 @@ util_clear_depth_stencil(struct pipe_context *pipe,
          else {
             uint32_t dst_mask;
             if (format == PIPE_FORMAT_Z24_UNORM_S8_UINT)
-               dst_mask = 0xffffff00;
+               dst_mask = 0x00ffffff;
             else {
                assert(format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
-               dst_mask = 0xffffff;
+               dst_mask = 0xffffff00;
             }
             if (clear_flags & PIPE_CLEAR_DEPTH)
                dst_mask = ~dst_mask;

src/gallium/auxiliary/util/u_vbuf.c

@@ -307,6 +307,9 @@ void u_vbuf_destroy(struct u_vbuf *mgr)
    unsigned num_vb = screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
                                               PIPE_SHADER_CAP_MAX_INPUTS);
 
+   mgr->pipe->set_index_buffer(mgr->pipe, NULL);
+   pipe_resource_reference(&mgr->index_buffer.buffer, NULL);
+
    mgr->pipe->set_vertex_buffers(mgr->pipe, 0, num_vb, NULL);
 
    for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {

src/gallium/drivers/Makefile.am

@@ -1,6 +1,7 @@
 AUTOMAKE_OPTIONS = subdir-objects
 
 AM_CPPFLAGS = \
+	-I$(top_srcdir)/include \
 	-I$(top_srcdir)/src/gallium/include \
 	-I$(top_srcdir)/src/gallium/auxiliary \
 	-I$(top_srcdir)/src/gallium/drivers \

src/gallium/drivers/llvmpipe/Makefile.am

@@ -85,23 +85,30 @@ check_PROGRAMS = \
 	lp_test_printf
 TESTS = $(check_PROGRAMS)
 
+TEST_LIBS = \
+	    libllvmpipe.la \
+	    $(top_builddir)/src/gallium/auxiliary/libgallium.la \
+	    $(LLVM_LIBS) \
+	    $(DLOPEN_LIBS) \
+	    $(PTHREAD_LIBS)
+
 lp_test_format_SOURCES = lp_test_format.c lp_test_main.c
-lp_test_format_LDADD = libllvmpipe.la ../../auxiliary/libgallium.la $(LLVM_LIBS)
+lp_test_format_LDADD = $(TEST_LIBS)
 nodist_EXTRA_lp_test_format_SOURCES = dummy.cpp
 
 lp_test_arit_SOURCES = lp_test_arit.c lp_test_main.c
-lp_test_arit_LDADD = libllvmpipe.la ../../auxiliary/libgallium.la $(LLVM_LIBS)
+lp_test_arit_LDADD = $(TEST_LIBS)
 nodist_EXTRA_lp_test_arit_SOURCES = dummy.cpp
 
 lp_test_blend_SOURCES = lp_test_blend.c lp_test_main.c
-lp_test_blend_LDADD = libllvmpipe.la ../../auxiliary/libgallium.la $(LLVM_LIBS)
+lp_test_blend_LDADD = $(TEST_LIBS)
 nodist_EXTRA_lp_test_blend_SOURCES = dummy.cpp
 
 lp_test_conv_SOURCES = lp_test_conv.c lp_test_main.c
-lp_test_conv_LDADD = libllvmpipe.la ../../auxiliary/libgallium.la $(LLVM_LIBS)
+lp_test_conv_LDADD = $(TEST_LIBS)
 nodist_EXTRA_lp_test_conv_SOURCES = dummy.cpp
 
 lp_test_printf_SOURCES = lp_test_printf.c lp_test_main.c
-lp_test_printf_LDADD = libllvmpipe.la ../../auxiliary/libgallium.la $(LLVM_LIBS)
+lp_test_printf_LDADD = $(TEST_LIBS)
 nodist_EXTRA_lp_test_printf_SOURCES = dummy.cpp
 

src/gallium/drivers/llvmpipe/lp_scene.c

@@ -64,6 +64,28 @@ lp_scene_create( struct pipe_context *pipe )
 
    pipe_mutex_init(scene->mutex);
 
+#ifdef DEBUG
+   /* Do some scene limit sanity checks here */
+   {
+      size_t maxBins = TILES_X * TILES_Y;
+      size_t maxCommandBytes = sizeof(struct cmd_block) * maxBins;
+      size_t maxCommandPlusData = maxCommandBytes + DATA_BLOCK_SIZE;
+      /* We'll need at least one command block per bin.  Make sure that's
+       * less than the max allowed scene size.
+       */
+      assert(maxCommandBytes < LP_SCENE_MAX_SIZE);
+      /* We'll also need space for at least one other data block */
+      assert(maxCommandPlusData <= LP_SCENE_MAX_SIZE);
+
+      /* Ideally, the size of a cmd_block object will be a power of two
+       * in order to avoid wasting space when we allocation them from
+       * data blocks (which are power of two also).
+       */
+      assert(sizeof(struct cmd_block) ==
+             util_next_power_of_two(sizeof(struct cmd_block)));
+   }
+#endif
+
    return scene;
 }
 

src/gallium/drivers/llvmpipe/lp_scene.h

@@ -49,12 +49,18 @@ struct lp_rast_state;
 #define TILES_Y (LP_MAX_HEIGHT / TILE_SIZE)
 
 
-#define CMD_BLOCK_MAX 128
+/* Commands per command block (ideally so sizeof(cmd_block) is a power of
+ * two in size.)
+ */
+#define CMD_BLOCK_MAX 29
+
+/* Bytes per data block.
+ */
 #define DATA_BLOCK_SIZE (64 * 1024)
 
 /* Scene temporary storage is clamped to this size:
  */
-#define LP_SCENE_MAX_SIZE (4*1024*1024)
+#define LP_SCENE_MAX_SIZE (9*1024*1024)
 
 /* The maximum amount of texture storage referenced by a scene is
  * clamped ot this size:

src/gallium/drivers/llvmpipe/lp_state_rasterizer.c

@@ -46,6 +46,10 @@ clear_flags(struct pipe_rasterizer_state *rast)
 {
    rast->light_twoside = 0;
    rast->offset_tri = 0;
+   rast->offset_line = 0;
+   rast->offset_point = 0;
+   rast->offset_units = 0.0f;
+   rast->offset_scale = 0.0f;
 }
 
 
@@ -74,6 +78,8 @@ llvmpipe_create_rasterizer_state(struct pipe_context *pipe,
     */
    need_pipeline = (rast->fill_front != PIPE_POLYGON_MODE_FILL ||
 		    rast->fill_back != PIPE_POLYGON_MODE_FILL ||
+                    rast->offset_point ||
+                    rast->offset_line ||
 		    rast->point_smooth ||
 		    rast->line_smooth ||
 		    rast->line_stipple_enable ||

src/gallium/drivers/llvmpipe/lp_texture.c

@@ -295,7 +295,9 @@ llvmpipe_resource_create(struct pipe_screen *_screen,
    /* assert(lpr->base.bind); */
 
    if (resource_is_texture(&lpr->base)) {
-      if (lpr->base.bind & PIPE_BIND_DISPLAY_TARGET) {
+      if (lpr->base.bind & (PIPE_BIND_DISPLAY_TARGET |
+                            PIPE_BIND_SCANOUT |
+                            PIPE_BIND_SHARED)) {
          /* displayable surface */
          if (!llvmpipe_displaytarget_layout(screen, lpr))
             goto fail;

src/gallium/drivers/nv50/nv50_blit.h

@@ -180,4 +180,44 @@ nv50_blit_eng2d_get_mask(const struct pipe_blit_info *info)
    return mask;
 }
 
+#if NOUVEAU_DRIVER == 0xc0
+# define nv50_format_table nvc0_format_table
+#endif
+
+/* return TRUE for formats that can be converted among each other by NVC0_2D */
+static INLINE boolean
+nv50_2d_dst_format_faithful(enum pipe_format format)
+{
+   const uint64_t mask =
+       NV50_ENG2D_SUPPORTED_FORMATS &
+      ~NV50_ENG2D_NOCONVERT_FORMATS;
+   uint8_t id = nv50_format_table[format].rt;
+   return (id >= 0xc0) && (mask & (1ULL << (id - 0xc0)));
+}
+static INLINE boolean
+nv50_2d_src_format_faithful(enum pipe_format format)
+{
+   const uint64_t mask =
+      NV50_ENG2D_SUPPORTED_FORMATS &
+    ~(NV50_ENG2D_LUMINANCE_FORMATS | NV50_ENG2D_INTENSITY_FORMATS);
+   uint8_t id = nv50_format_table[format].rt;
+   return (id >= 0xc0) && (mask & (1ULL << (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_format_supported(enum pipe_format format)
+{
+   uint8_t id = nv50_format_table[format].rt;
+   return (id >= 0xc0) &&
+      (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_dst_format_ops_supported(enum pipe_format format)
+{
+   uint8_t id = nv50_format_table[format].rt;
+   return (id >= 0xc0) &&
+      (NV50_ENG2D_OPERATION_FORMATS & (1ULL << (id - 0xc0)));
+}
+
 #endif /* __NV50_BLIT_H__ */

src/gallium/drivers/nv50/nv50_context.c

@@ -242,6 +242,7 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
       screen->cur_ctx = nv50;
       nouveau_pushbuf_bufctx(screen->base.pushbuf, nv50->bufctx);
    }
+   nv50->base.pushbuf->kick_notify = nv50_default_kick_notify;
 
    nv50_init_query_functions(nv50);
    nv50_init_surface_functions(nv50);

src/gallium/drivers/nv50/nv50_state_validate.c

@@ -9,6 +9,7 @@ nv50_validate_fb(struct nv50_context *nv50)
    struct pipe_framebuffer_state *fb = &nv50->framebuffer;
    unsigned i;
    unsigned ms_mode = NV50_3D_MULTISAMPLE_MODE_MS1;
+   uint32_t array_size = 0xffff, array_mode = 0;
 
    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
 
@@ -23,6 +24,13 @@ nv50_validate_fb(struct nv50_context *nv50)
       struct nv50_surface *sf = nv50_surface(fb->cbufs[i]);
       struct nouveau_bo *bo = mt->base.bo;
 
+      array_size = MIN2(array_size, sf->depth);
+      if (mt->layout_3d)
+         array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */
+
+      /* can't mix 3D with ARRAY or have RTs of different depth/array_size */
+      assert(mt->layout_3d || !array_mode || array_size == 1);
+
       BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
       PUSH_DATAh(push, bo->offset + sf->offset);
       PUSH_DATA (push, bo->offset + sf->offset);
@@ -34,7 +42,7 @@ nv50_validate_fb(struct nv50_context *nv50)
          PUSH_DATA (push, sf->width);
          PUSH_DATA (push, sf->height);
          BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
-         PUSH_DATA (push, sf->depth);
+         PUSH_DATA (push, array_mode | array_size);
       } else {
          PUSH_DATA (push, 0);
          PUSH_DATA (push, 0);
@@ -63,7 +71,7 @@ nv50_validate_fb(struct nv50_context *nv50)
       struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
       struct nv50_surface *sf = nv50_surface(fb->zsbuf);
       struct nouveau_bo *bo = mt->base.bo;
-      int unk = mt->base.base.target == PIPE_TEXTURE_2D;
+      int unk = mt->base.base.target == PIPE_TEXTURE_3D || sf->depth == 1;
 
       BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
       PUSH_DATAh(push, bo->offset + sf->offset);

src/gallium/drivers/nv50/nv50_surface.c

@@ -35,25 +35,22 @@
 
 #include "nv50_context.h"
 #include "nv50_resource.h"
-#include "nv50_blit.h"
 
 #include "nv50_defs.xml.h"
 #include "nv50_texture.xml.h"
 
+/* these are used in nv50_blit.h */
 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
+#define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
+#define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
+#define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
+#define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
 
-/* return TRUE for formats that can be converted among each other by NV50_2D */
+#define NOUVEAU_DRIVER 0x50
-static INLINE boolean
+#include "nv50_blit.h"
-nv50_2d_format_faithful(enum pipe_format format)
-{
-   uint8_t id = nv50_format_table[format].rt;
-
-   return (id >= 0xc0) &&
-      (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
-}
 
 static INLINE uint8_t
-nv50_2d_format(enum pipe_format format)
+nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
 {
    uint8_t id = nv50_format_table[format].rt;
 
@@ -62,6 +59,7 @@ nv50_2d_format(enum pipe_format format)
     */
    if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
       return id;
+   assert(dst_src_equal);
 
    switch (util_format_get_blocksize(format)) {
    case 1:
@@ -78,7 +76,7 @@ nv50_2d_format(enum pipe_format format)
 static int
 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
                     struct nv50_miptree *mt, unsigned level, unsigned layer,
-                    enum pipe_format pformat)
+                    enum pipe_format pformat, boolean dst_src_pformat_equal)
 {
    struct nouveau_bo *bo = mt->base.bo;
    uint32_t width, height, depth;
@@ -86,7 +84,7 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
    uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
    uint32_t offset = mt->level[level].offset;
 
-   format = nv50_2d_format(pformat);
+   format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
    if (!format) {
       NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
                   util_format_name(pformat));
@@ -155,15 +153,16 @@ nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
    const enum pipe_format dfmt = dst->base.base.format;
    const enum pipe_format sfmt = src->base.base.format;
    int ret;
+   boolean eqfmt = dfmt == sfmt;
 
    if (!PUSH_SPACE(push, 2 * 16 + 32))
       return PIPE_ERROR;
 
-   ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt);
+   ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
    if (ret)
       return ret;
 
-   ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt);
+   ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
    if (ret)
       return ret;
 
@@ -243,8 +242,8 @@ nv50_resource_copy_region(struct pipe_context *pipe,
    }
 
    assert((src->format == dst->format) ||
-          (nv50_2d_format_faithful(src->format) &&
+          (nv50_2d_src_format_faithful(src->format) &&
-           nv50_2d_format_faithful(dst->format)));
+           nv50_2d_dst_format_faithful(dst->format)));
 
    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
@@ -936,7 +935,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
    nv50_blit_select_fp(blit, info);
    nv50_blitctx_pre_blit(blit);
 
-   nv50_blit_set_dst(blit, dst, info->dst.level,  0, info->dst.format);
+   nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
    nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
                      blit->filter);
 
@@ -977,6 +976,8 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
 
    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
    PUSH_DATA (push, 0);
+   BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
+   PUSH_DATA (push, 0x1);
 
    /* Draw a large triangle in screen coordinates covering the whole
     * render target, with scissors defining the destination region.
@@ -1059,7 +1060,8 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
    int64_t du_dx, dv_dy;
    int i;
    uint32_t mode;
-   const uint32_t mask = nv50_blit_eng2d_get_mask(info);
+   uint32_t mask = nv50_blit_eng2d_get_mask(info);
+   boolean b;
 
    mode = nv50_blit_get_filter(info) ?
       NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
@@ -1070,8 +1072,9 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
    du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
    dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
 
-   nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format);
+   b = info->dst.format == info->src.format;
-   nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format);
+   nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
+   nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
 
    if (info->scissor_enable) {
       BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
@@ -1094,6 +1097,17 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
       PUSH_DATA (push, 0xffffffff);
       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
       PUSH_DATA (push, NV50_2D_OPERATION_ROP);
+   } else
+   if (info->src.format != info->dst.format) {
+      if (info->src.format == PIPE_FORMAT_R8_UNORM ||
+          info->src.format == PIPE_FORMAT_R16_UNORM ||
+          info->src.format == PIPE_FORMAT_R16_FLOAT ||
+          info->src.format == PIPE_FORMAT_R32_FLOAT) {
+         mask = 0xffff0000; /* also makes condition for OPERATION reset true */
+         BEGIN_NV04(push, NV50_2D(BETA4), 2);
+         PUSH_DATA (push, mask);
+         PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
+      }
    }
 
    if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
@@ -1224,10 +1238,25 @@ nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
       debug_printf("blit: cannot filter array or cube textures in z direction");
    }
 
-   if (!eng3d && info->dst.format != info->src.format)
+   if (!eng3d && info->dst.format != info->src.format) {
-      if (!nv50_2d_format_faithful(info->dst.format) ||
+      if (!nv50_2d_dst_format_faithful(info->dst.format) ||
-          !nv50_2d_format_faithful(info->src.format))
+          !nv50_2d_src_format_faithful(info->src.format)) {
          eng3d = TRUE;
+      } else
+      if (!nv50_2d_src_format_faithful(info->src.format)) {
+         if (!util_format_is_luminance(info->src.format)) {
+            if (util_format_is_intensity(info->src.format))
+               eng3d = TRUE;
+            else
+            if (!nv50_2d_dst_format_ops_supported(info->dst.format))
+               eng3d = TRUE;
+            else
+               eng3d = !nv50_2d_format_supported(info->src.format);
+         }
+      } else
+      if (util_format_is_luminance_alpha(info->src.format))
+         eng3d = TRUE;
+   }
 
    if (info->src.resource->nr_samples == 8 &&
        info->dst.resource->nr_samples <= 1)

src/gallium/drivers/nvc0/nvc0_3d.xml.h

@@ -1041,7 +1041,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_VIEWPORT_TRANSFORM_EN				0x0000192c
 
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL				0x0000193c
-#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK0			0x00000001
+#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1		0x00000001
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__MASK		0x00000006
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__SHIFT		1
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK0			0x00000000

src/gallium/drivers/nvc0/nvc0_screen.c

@@ -445,6 +445,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    chan = screen->base.channel;
    push = screen->base.pushbuf;
    push->user_priv = screen;
+   push->rsvd_kick = 5;
 
    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;

src/gallium/drivers/nvc0/nvc0_surface.c

@@ -36,29 +36,32 @@
 
 #include "nv50/nv50_defs.xml.h"
 #include "nv50/nv50_texture.xml.h"
+
+/* these are used in nv50_blit.h */
+#define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
+#define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
+#define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
+#define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
+#define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
+
+#define NOUVEAU_DRIVER 0xc0
 #include "nv50/nv50_blit.h"
 
-#define NVC0_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
-
-/* return TRUE for formats that can be converted among each other by NVC0_2D */
-static INLINE boolean
-nvc0_2d_format_faithful(enum pipe_format format)
-{
-   uint8_t id = nvc0_format_table[format].rt;
-
-   return (id >= 0xc0) && (NVC0_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
-}
-
 static INLINE uint8_t
-nvc0_2d_format(enum pipe_format format)
+nvc0_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
 {
    uint8_t id = nvc0_format_table[format].rt;
 
+   /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
+   if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
+      return NV50_SURFACE_FORMAT_A8_UNORM;
+
    /* Hardware values for color formats range from 0xc0 to 0xff,
     * but the 2D engine doesn't support all of them.
     */
-   if (nvc0_2d_format_faithful(format))
+   if (nv50_2d_format_supported(format))
       return id;
+   assert(dst_src_equal);
 
    switch (util_format_get_blocksize(format)) {
    case 1:
@@ -72,6 +75,7 @@ nvc0_2d_format(enum pipe_format format)
    case 16:
       return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
    default:
+      assert(0);
       return 0;
    }
 }
@@ -79,7 +83,7 @@ nvc0_2d_format(enum pipe_format format)
 static int
 nvc0_2d_texture_set(struct nouveau_pushbuf *push, boolean dst,
                     struct nv50_miptree *mt, unsigned level, unsigned layer,
-                    enum pipe_format pformat)
+                    enum pipe_format pformat, boolean dst_src_pformat_equal)
 {
    struct nouveau_bo *bo = mt->base.bo;
    uint32_t width, height, depth;
@@ -87,7 +91,7 @@ nvc0_2d_texture_set(struct nouveau_pushbuf *push, boolean dst,
    uint32_t mthd = dst ? NVC0_2D_DST_FORMAT : NVC0_2D_SRC_FORMAT;
    uint32_t offset = mt->level[level].offset;
 
-   format = nvc0_2d_format(pformat);
+   format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
    if (!format) {
       NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
                   util_format_name(pformat));
@@ -157,15 +161,16 @@ nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
    const enum pipe_format dfmt = dst->base.base.format;
    const enum pipe_format sfmt = src->base.base.format;
    int ret;
+   boolean eqfmt = dfmt == sfmt;
 
    if (!PUSH_SPACE(push, 2 * 16 + 32))
       return PIPE_ERROR;
 
-   ret = nvc0_2d_texture_set(push, TRUE, dst, dst_level, dz, dfmt);
+   ret = nvc0_2d_texture_set(push, TRUE, dst, dst_level, dz, dfmt, eqfmt);
    if (ret)
       return ret;
 
-   ret = nvc0_2d_texture_set(push, FALSE, src, src_level, sz, sfmt);
+   ret = nvc0_2d_texture_set(push, FALSE, src, src_level, sz, sfmt, eqfmt);
    if (ret)
       return ret;
 
@@ -243,8 +248,8 @@ nvc0_resource_copy_region(struct pipe_context *pipe,
       return;
    }
 
-   assert(nvc0_2d_format_faithful(src->format));
+   assert(nv50_2d_dst_format_faithful(dst->format));
-   assert(nvc0_2d_format_faithful(dst->format));
+   assert(nv50_2d_src_format_faithful(src->format));
 
    BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
    BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
@@ -490,19 +495,19 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
 {
    static const uint32_t code_nvc0[] =
    {
-      0xfff01c66, 0x06000080, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
+      0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
-      0xfff11c26, 0x06000090, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
+      0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
-      0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
+      0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
-      0x13f01c26, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+      0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
       0x00001de7, 0x80000000, /* exit */
    };
    static const uint32_t code_nve4[] =
    {
       0x00000007, 0x20000000, /* sched */
-      0xfff01c66, 0x06000080, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
+      0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
-      0xfff11c46, 0x06000090, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
+      0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
-      0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
+      0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
-      0x13f01c46, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+      0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
       0x00001de7, 0x80000000, /* exit */
    };
 
@@ -515,13 +520,13 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
       blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
       blit->vp.code_size = sizeof(code_nvc0);
    }
-   blit->vp.max_gpr = 7;
+   blit->vp.max_gpr = 6;
    blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
 
    blit->vp.hdr[0]  = 0x00020461; /* vertprog magic */
    blit->vp.hdr[4]  = 0x000ff000; /* no outputs read */
-   blit->vp.hdr[6]  = 0x0000003f; /* a[0x80], a[0x90] */
+   blit->vp.hdr[6]  = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
-   blit->vp.hdr[13] = 0x0003f000; /* o[0x70], o[0x80] */
+   blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
 }
 
 static void
@@ -820,7 +825,7 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    nvc0_blit_select_fp(blit, info);
    nvc0_blitctx_pre_blit(blit);
 
-   nvc0_blit_set_dst(blit, dst, info->dst.level,  0, info->dst.format);
+   nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
    nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
                      blit->filter);
 
@@ -859,6 +864,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
       z += 0.5f * dz;
 
    IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
+   IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
+              NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
    PUSH_DATA (push, nvc0->framebuffer.width << 16);
    PUSH_DATA (push, nvc0->framebuffer.height << 16);
@@ -925,11 +932,14 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    if (info->dst.box.z + info->dst.box.depth - 1)
       IMMED_NVC0(push, NVC0_3D(LAYER), 0);
 
-   /* re-enable normally constant state */
-
-   IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
-
    nvc0_blitctx_post_blit(blit);
+
+   /* restore viewport */
+
+   BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
+   PUSH_DATA (push, nvc0->framebuffer.width << 16);
+   PUSH_DATA (push, nvc0->framebuffer.height << 16);
+   IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 }
 
 static void
@@ -948,7 +958,8 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    int64_t du_dx, dv_dy;
    int i;
    uint32_t mode;
-   const uint32_t mask = nv50_blit_eng2d_get_mask(info);
+   uint32_t mask = nv50_blit_eng2d_get_mask(info);
+   boolean b;
 
    mode = nv50_blit_get_filter(info) ?
       NVC0_2D_BLIT_CONTROL_FILTER_BILINEAR :
@@ -959,8 +970,9 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
    dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
 
-   nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format);
+   b = info->dst.format == info->src.format;
-   nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format);
+   nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
+   nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
 
    if (info->scissor_enable) {
       BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
@@ -981,6 +993,25 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
       PUSH_DATA (push, 0xffffffff);
       PUSH_DATA (push, 0xffffffff);
       IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_ROP);
+   } else
+   if (info->src.format != info->dst.format) {
+      if (info->src.format == PIPE_FORMAT_R8_UNORM ||
+          info->src.format == PIPE_FORMAT_R8_SNORM ||
+          info->src.format == PIPE_FORMAT_R16_UNORM ||
+          info->src.format == PIPE_FORMAT_R16_SNORM ||
+          info->src.format == PIPE_FORMAT_R16_FLOAT ||
+          info->src.format == PIPE_FORMAT_R32_FLOAT) {
+         mask = 0xffff0000; /* also makes condition for OPERATION reset true */
+         BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
+         PUSH_DATA (push, mask);
+         PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY_PREMULT);
+      } else
+      if (info->src.format == PIPE_FORMAT_A8_UNORM) {
+         mask = 0xff000000;
+         BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
+         PUSH_DATA (push, mask);
+         PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY_PREMULT);
+      }
    }
 
    if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
@@ -1106,10 +1137,24 @@ nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
       debug_printf("blit: cannot filter array or cube textures in z direction");
    }
 
-   if (!eng3d && info->dst.format != info->src.format)
+   if (!eng3d && info->dst.format != info->src.format) {
-      if (!nvc0_2d_format_faithful(info->dst.format) ||
+      if (!nv50_2d_dst_format_faithful(info->dst.format)) {
-          !nvc0_2d_format_faithful(info->src.format))
          eng3d = TRUE;
+      } else
+      if (!nv50_2d_src_format_faithful(info->src.format)) {
+         if (!util_format_is_luminance(info->src.format)) {
+            if (util_format_is_intensity(info->src.format))
+               eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
+            else
+            if (!nv50_2d_dst_format_ops_supported(info->dst.format))
+               eng3d = TRUE;
+            else
+               eng3d = !nv50_2d_format_supported(info->src.format);
+         }
+      } else
+      if (util_format_is_luminance_alpha(info->src.format))
+         eng3d = TRUE;
+   }
 
    if (info->src.resource->nr_samples == 8 &&
        info->dst.resource->nr_samples <= 1)

src/gallium/drivers/nvc0/nvc0_video.c

@@ -356,19 +356,19 @@ nvc0_create_decoder(struct pipe_context *context,
          goto fw_fail;
       }
       r = read(fd, dec->fw_bo->map, 0x4000);
+      close(fd);
+
       if (r < 0) {
          fprintf(stderr, "reading firmware file %s failed: %m\n", path);
          goto fw_fail;
       }
 
       if (r == 0x4000) {
-         close(fd);
          fprintf(stderr, "firmware file %s too large!\n", path);
          goto fw_fail;
       }
 
       if (r & 0xff) {
-         close(fd);
          fprintf(stderr, "firmware file %s wrong size!\n", path);
          goto fw_fail;
       }
@@ -558,8 +558,6 @@ nvc0_video_buffer_create(struct pipe_context *pipe,
    buffer = CALLOC_STRUCT(nvc0_video_buffer);
    if (!buffer)
       return NULL;
-   assert(!(templat->height % 4));
-   assert(!(templat->width % 2));
 
    buffer->base.buffer_format = templat->buffer_format;
    buffer->base.context = pipe;
@@ -578,7 +576,7 @@ nvc0_video_buffer_create(struct pipe_context *pipe,
    templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
    templ.format = PIPE_FORMAT_R8_UNORM;
    templ.width0 = buffer->base.width;
-   templ.height0 = buffer->base.height/2;
+   templ.height0 = (buffer->base.height + 1)/2;
    templ.flags = NVC0_RESOURCE_FLAG_VIDEO;
    templ.last_level = 0;
    templ.array_size = 1;
@@ -589,8 +587,8 @@ nvc0_video_buffer_create(struct pipe_context *pipe,
 
    templ.format = PIPE_FORMAT_R8G8_UNORM;
    buffer->num_planes = 2;
-   templ.width0 /= 2;
+   templ.width0 = (templ.width0 + 1) / 2;
-   templ.height0 /= 2;
+   templ.height0 = (templ.height0 + 1) / 2;
    for (i = 1; i < buffer->num_planes; ++i) {
       buffer->resources[i] = pipe->screen->resource_create(pipe->screen, &templ);
       if (!buffer->resources[i])

src/gallium/drivers/nvc0/nvc0_video_ppp.c

@@ -62,8 +62,6 @@ nvc0_decoder_setup_ppp(struct nvc0_decoder *dec, struct nvc0_video_buffer *targe
    PUSH_DATA (push, in_addr + y2); // 70c
    PUSH_DATA (push, in_addr + cbcr); // 710
    PUSH_DATA (push, in_addr + cbcr2); // 714
-   assert(target->resources[0]->width0 >= 16 * dec_w);
-   assert(target->resources[0]->height0 >= dec->base.height/2);
 
    for (i = 0; i < 2; ++i) {
       struct nv50_miptree *mt = (struct nv50_miptree *)target->resources[i];

src/gallium/drivers/nvc0/nvc0_video_vp.c

@@ -185,8 +185,6 @@ nvc0_decoder_handle_references(struct nvc0_decoder *dec, struct nvc0_video_buffe
               (!dec->refs[idx].decoded_bottom || !dec->refs[idx].decoded_top)));
       if (target == refs[i])
          empty_spot = 0;
-      assert(!h264 ||
-             dec->refs[idx].last_used == seq - 1);
 
       if (dec->refs[idx].vidbuf != refs[i]) {
          debug_printf("%p is not a real ref\n", refs[i]);
@@ -338,7 +336,6 @@ nvc0_decoder_fill_picparm_h264_vp(struct nvc0_decoder *dec,
    unsigned ring, i, j = 0;
    assert(offsetof(struct h264_picparm_vp, u224) == 0x224);
    *is_ref = d->is_reference;
-   assert(!d->frame_num || dec->last_frame_num + 1 == d->frame_num || dec->last_frame_num == d->frame_num);
    dec->last_frame_num = d->frame_num;
 
    h->width = mb(dec->base.width);

src/gallium/drivers/r300/Makefile.am

@@ -22,6 +22,7 @@ r300_compiler_tests_CPPFLAGS = \
 	-I$(top_srcdir)/src/gallium/drivers/r300/compiler
 r300_compiler_tests_SOURCES = \
 	$(testdir)/r300_compiler_tests.c \
+	$(testdir)/radeon_compiler_optimize_tests.c \
 	$(testdir)/radeon_compiler_util_tests.c \
 	$(testdir)/rc_test_helpers.c \
 	$(testdir)/unit_test.c

src/gallium/drivers/r300/compiler/r3xx_vertprog.c

@@ -854,7 +854,7 @@ static void rc_emulate_negative_addressing(struct radeon_compiler *compiler, voi
 		transform_negative_addressing(c, lastARL, inst, min_offset);
 }
 
-static struct rc_swizzle_caps r300_vertprog_swizzle_caps = {
+struct rc_swizzle_caps r300_vertprog_swizzle_caps = {
 	.IsNative = &swizzle_is_native,
 	.Split = 0 /* should never be called */
 };

src/gallium/drivers/r300/compiler/radeon_compiler_util.h

@@ -1,3 +1,30 @@
+/*
+ * Copyright 2010 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #include "radeon_program_constants.h"
 
 #ifndef RADEON_PROGRAM_UTIL_H

src/gallium/drivers/r300/compiler/radeon_emulate_loops.h

@@ -1,4 +1,29 @@
-
+/*
+ * Copyright 2010 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 #ifndef RADEON_EMULATE_LOOPS_H
 #define RADEON_EMULATE_LOOPS_H

src/gallium/drivers/r300/compiler/radeon_inline_literals.c

@@ -1,3 +1,27 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Tom Stellard <thomas.stellard@amd.com>
+ */
 
 #include "radeon_compiler.h"
 #include "radeon_compiler_util.h"

src/gallium/drivers/r300/compiler/radeon_optimize.c

@@ -708,6 +708,7 @@ static int peephole_mul_omod(
 	struct rc_list * writer_list;
 	struct rc_variable * var;
 	struct peephole_mul_cb_data cb_data;
+	unsigned writemask_sum;
 
 	for (i = 0; i < 2; i++) {
 		unsigned int j;
@@ -815,10 +816,11 @@ static int peephole_mul_omod(
 	}
 
 	/* Rewrite the instructions */
+	writemask_sum = rc_variable_writemask_sum(writer_list->Item);
 	for (var = writer_list->Item; var; var = var->Friend) {
-		struct rc_variable * writer = writer_list->Item;
+		struct rc_variable * writer = var;
 		unsigned conversion_swizzle = rc_make_conversion_swizzle(
-					writer->Inst->U.I.DstReg.WriteMask,
+					writemask_sum,
 					inst_mul->U.I.DstReg.WriteMask);
 		writer->Inst->U.I.Omod = omod_op;
 		writer->Inst->U.I.DstReg.File = inst_mul->U.I.DstReg.File;

src/gallium/drivers/r300/compiler/radeon_pair_dead_sources.c

@@ -1,3 +1,29 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 #include "radeon_compiler.h"
 #include "radeon_compiler_util.h"

src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c

@@ -383,6 +383,14 @@ static enum rc_reg_class variable_get_class(
 							RC_INSTRUCTION_PAIR ) {
 						old_swizzle = r.U.P.Arg->Swizzle;
 					} else {
+						/* Source operands of TEX
+						 * instructions can't be
+						 * swizzle on r300/r400 GPUs.
+						 */
+						if (!variable->C->is_r500) {
+							can_change_writemask = 0;
+							break;
+						}
 						old_swizzle = r.U.I.Src->Swizzle;
 					}
 					new_swizzle = rc_adjust_channels(

src/gallium/drivers/r300/compiler/radeon_rename_regs.h

@@ -1,3 +1,29 @@
+/*
+ * Copyright 2010 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 #ifndef RADEON_RENAME_REGS_H
 #define RADEON_RENAME_REGS_H

src/gallium/drivers/r300/compiler/radeon_swizzle.h

@@ -54,4 +54,6 @@ struct rc_swizzle_caps {
 	void (*Split)(struct rc_src_register reg, unsigned int mask, struct rc_swizzle_split * split);
 };
 
+extern struct rc_swizzle_caps r300_vertprog_swizzle_caps;
+
 #endif /* RADEON_SWIZZLE_H */

src/gallium/drivers/r300/compiler/radeon_vert_fc.c

@@ -1,3 +1,27 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Tom Stellard <thomas.stellard@amd.com>
+ */
 
 #include "radeon_compiler.h"
 #include "radeon_compiler_util.h"

src/gallium/drivers/r300/compiler/tests/r300_compiler_tests.c

@@ -1,6 +1,43 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #include "r300_compiler_tests.h"
 
+#include <stdlib.h>
+
 int main(int argc, char ** argv)
 {
-	radeon_compiler_util_run_tests();
+	unsigned pass = 1;
+	pass &= radeon_compiler_optimize_run_tests();
+	pass &= radeon_compiler_util_run_tests();
+
+	if (pass) {
+		return EXIT_SUCCESS;
+	} else {
+		return EXIT_FAILURE;
+	}
 }

src/gallium/drivers/r300/compiler/tests/r300_compiler_tests.h

@@ -1,2 +1,29 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
-void radeon_compiler_util_run_tests(void);
+unsigned radeon_compiler_optimize_run_tests(void);
+unsigned radeon_compiler_util_run_tests(void);

src/gallium/drivers/r300/compiler/tests/radeon_compiler_optimize_tests.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Tom Stellard <thomas.stellard@amd.com>
+ */
+
+#include "radeon_compiler.h"
+#include "radeon_dataflow.h"
+
+#include "r300_compiler_tests.h"
+#include "rc_test_helpers.h"
+#include "unit_test.h"
+
+static void test_runner_rc_optimize(struct test_result * result)
+{
+	struct radeon_compiler c;
+	struct rc_instruction *inst;
+	struct rc_instruction *inst_list[3];
+	unsigned inst_count = 0;
+	float const0[4] = {2.0f, 0.0f, 0.0f, 0.0f};
+	unsigned pass = 1;
+
+	test_begin(result);
+	init_compiler(&c, RC_FRAGMENT_PROGRAM, 1, 0);
+
+	rc_constants_add_immediate_vec4(&c.Program.Constants, const0);
+
+	add_instruction(&c, "RCP temp[0].x, const[1].x___;");
+	add_instruction(&c, "RCP temp[0].y, const[1]._y__;");
+	add_instruction(&c, "MUL temp[1].xy, const[0].xx__, temp[0].xy__;");
+	add_instruction(&c, "MOV output[0].xy, temp[1].xy;" );
+
+	rc_optimize(&c, NULL);
+
+	for(inst = c.Program.Instructions.Next;
+					inst != &c.Program.Instructions;
+					inst = inst->Next, inst_count++) {
+		inst_list[inst_count] = inst;
+	}
+
+	if (inst_list[0]->U.I.Omod != RC_OMOD_MUL_2 ||
+			inst_list[1]->U.I.Omod != RC_OMOD_MUL_2 ||
+			inst_list[2]->U.I.Opcode != RC_OPCODE_MOV) {
+		pass = 0;
+	}
+	test_check(result, pass);
+}
+
+unsigned radeon_compiler_optimize_run_tests()
+{
+	struct test tests[] = {
+		{"rc_optimize() => peephole_mul_omod()", test_runner_rc_optimize},
+		{NULL, NULL}
+	};
+	return run_tests(tests);
+}

src/gallium/drivers/r300/compiler/tests/radeon_compiler_util_tests.c

@@ -1,3 +1,30 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #include <stdlib.h>
 #include <string.h>
 #include <sys/types.h>
@@ -67,11 +94,11 @@ static void test_runner_rc_inst_can_use_presub(struct test_result * result)
 		"MAD temp[0].xyz, temp[2].xyz_, -temp[3].xxx_, input[5].xyz_;");
 }
 
-void radeon_compiler_util_run_tests()
+unsigned radeon_compiler_util_run_tests()
 {
 	struct test tests[] = {
 		{"rc_inst_can_use_presub()", test_runner_rc_inst_can_use_presub},
 		{NULL, NULL}
 	};
-	run_tests(tests);
+	return run_tests(tests);
 }

src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c

@@ -1,3 +1,32 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Tom Stellard <thomas.stellard@amd.com>
+ */
+
 #include <errno.h>
 #include <regex.h>
 #include <stdlib.h>
@@ -5,9 +34,14 @@
 #include <string.h>
 #include <sys/types.h>
 
-#include "../radeon_compiler_util.h"
+#include "r500_fragprog.h"
-#include "../radeon_opcodes.h"
+#include "r300_fragprog_swizzle.h"
-#include "../radeon_program.h"
+#include "radeon_compiler.h"
+#include "radeon_compiler_util.h"
+#include "radeon_opcodes.h"
+#include "radeon_program.h"
+#include "radeon_regalloc.h"
+#include "radeon_swizzle.h"
 
 #include "rc_test_helpers.h"
 
@@ -259,6 +293,7 @@ int init_rc_normal_dst(
 	if (tokens.WriteMask.Length == 0) {
 		inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
 	} else {
+		inst->U.I.DstReg.WriteMask = 0;
 		/* The first character should be '.' */
 		if (tokens.WriteMask.String[0] != '.') {
 			fprintf(stderr, "1st char of writemask is not valid.\n");
@@ -311,7 +346,8 @@ struct inst_tokens {
  * this string is the same that is output by rc_program_print.
  * @return 1 On success, 0 on failure
  */
-int init_rc_normal_instruction(
+
+int parse_rc_normal_instruction(
 	struct rc_instruction * inst,
 	const char * inst_str)
 {
@@ -320,10 +356,6 @@ int init_rc_normal_instruction(
 	regmatch_t matches[REGEX_INST_MATCHES];
 	struct inst_tokens tokens;
 
-	/* Initialize inst */
-	memset(inst, 0, sizeof(struct rc_instruction));
-	inst->Type = RC_INSTRUCTION_NORMAL;
-
 	/* Execute the regex */
 	if (!regex_helper(regex_str, inst_str, matches, REGEX_INST_MATCHES)) {
 		return 0;
@@ -340,6 +372,8 @@ int init_rc_normal_instruction(
 
 
 	/* Fill out the rest of the instruction. */
+	inst->Type = RC_INSTRUCTION_NORMAL;
+
 	for (i = 0; i < MAX_RC_OPCODE; i++) {
 		const struct rc_opcode_info * info = rc_get_opcode_info(i);
 		unsigned int first_src = 3;
@@ -378,3 +412,47 @@ int init_rc_normal_instruction(
 	}
 	return 1;
 }
+
+int init_rc_normal_instruction(
+	struct rc_instruction * inst,
+	const char * inst_str)
+{
+	/* Initialize inst */
+	memset(inst, 0, sizeof(struct rc_instruction));
+
+	return parse_rc_normal_instruction(inst, inst_str);
+}
+
+void add_instruction(struct radeon_compiler *c, const char * inst_string)
+{
+	struct rc_instruction * new_inst =
+		rc_insert_new_instruction(c, c->Program.Instructions.Prev);
+
+	parse_rc_normal_instruction(new_inst, inst_string);
+
+}
+
+void init_compiler(
+	struct radeon_compiler *c,
+	enum rc_program_type program_type,
+	unsigned is_r500,
+	unsigned is_r400)
+{
+	struct rc_regalloc_state *rs = malloc(sizeof(struct rc_regalloc_state));
+	rc_init(c, rs);
+
+	c->is_r500 = is_r500;
+	c->max_temp_regs = is_r500 ? 128 : (is_r400 ? 64 : 32);
+	c->max_constants = is_r500 ? 256 : 32;
+	c->max_alu_insts = (is_r500 || is_r400) ? 512 : 64;
+	c->max_tex_insts = (is_r500 || is_r400) ? 512 : 32;
+	if (program_type == RC_FRAGMENT_PROGRAM) {
+		c->has_half_swizzles = 1;
+		c->has_presub = 1;
+		c->has_omod = 1;
+		c->SwizzleCaps =
+			is_r500 ? &r500_swizzle_caps : &r300_swizzle_caps;
+	} else {
+		c->SwizzleCaps = &r300_vertprog_swizzle_caps;
+	}
+}

src/gallium/drivers/r300/compiler/tests/rc_test_helpers.h

@@ -1,3 +1,33 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Tom Stellard <thomas.stellard@amd.com>
+ */
+
+#include "radeon_compiler.h"
 
 int init_rc_normal_src(
 	struct rc_instruction * inst,
@@ -8,6 +38,18 @@ int init_rc_normal_dst(
 	struct rc_instruction * inst,
 	const char * dst_str);
 
+int parse_rc_normal_instruction(
+	struct rc_instruction * inst,
+	const char * inst_str);
+
 int init_rc_normal_instruction(
 	struct rc_instruction * inst,
 	const char * inst_str);
+
+void add_instruction(struct radeon_compiler *c, const char * inst_string);
+
+void init_compiler(
+	struct radeon_compiler *c,
+	enum rc_program_type program_type,
+	unsigned is_r500,
+	unsigned is_r400);

src/gallium/drivers/r300/compiler/tests/unit_test.c

@@ -1,19 +1,51 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
 
 #include "unit_test.h"
 
-void run_tests(struct test tests[])
+unsigned run_tests(struct test tests[])
 {
 	int i;
+	unsigned pass = 1;
 	for (i = 0; tests[i].name; i++) {
 		printf("Test %s\n", tests[i].name);
 		memset(&tests[i].result, 0, sizeof(tests[i].result));
 		tests[i].test_func(&tests[i].result);
 		printf("Test %s (%d/%d) pass\n", tests[i].name,
 			tests[i].result.pass, tests[i].result.test_count);
+		if (tests[i].result.pass != tests[i].result.test_count) {
+			pass = 0;
+		}
 	}
+	return pass;
 }
 
 void test_begin(struct test_result * result)

src/gallium/drivers/r300/compiler/tests/unit_test.h

@@ -1,3 +1,29 @@
+/*
+ * Copyright 2011 Tom Stellard <tstellar@gmail.com>
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 struct test_result {
 	unsigned int test_count;
@@ -11,7 +37,7 @@ struct test {
 	struct test_result result;
 };
 
-void run_tests(struct test tests[]);
+unsigned run_tests(struct test tests[]);
 
 void test_begin(struct test_result * result);
 void test_check(struct test_result * result, int cond);

src/gallium/drivers/r300/r300_state.c

@@ -487,6 +487,7 @@ static void r300_set_blend_color(struct pipe_context* pipe,
         (struct r300_blend_color_state*)r300->blend_color_state.state;
     struct pipe_blend_color c;
     enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0;
+    float tmp;
     CB_LOCALS;
 
     state->state = *color; /* Save it, so that we can reuse it in set_fb_state */
@@ -513,6 +514,13 @@ static void r300_set_blend_color(struct pipe_context* pipe,
             c.color[2] = c.color[3];
             break;
 
+        case PIPE_FORMAT_R8G8B8A8_UNORM:
+        case PIPE_FORMAT_R8G8B8X8_UNORM:
+            tmp = c.color[0];
+            c.color[0] = c.color[2];
+            c.color[2] = tmp;
+            break;
+
         default:;
         }
     }
@@ -919,6 +927,9 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
     /* Need to reset clamping or colormask. */
     r300_mark_atom_dirty(r300, &r300->blend_state);
 
+    /* Re-swizzle the blend color. */
+    r300_set_blend_color(pipe, &((struct r300_blend_color_state*)r300->blend_color_state.state)->state);
+
     /* If zsbuf is set from NULL to non-NULL or vice versa.. */
     if (!!old_state->zsbuf != !!state->zsbuf) {
         r300_mark_atom_dirty(r300, &r300->dsa_state);

src/gallium/drivers/r300/r300_texture.c

@@ -978,9 +978,9 @@ r300_texture_create_object(struct r300_screen *rscreen,
     tex->tex.microtile = microtile;
     tex->tex.macrotile[0] = macrotile;
     tex->tex.stride_in_bytes_override = stride_in_bytes_override;
-    tex->domain = base->flags & R300_RESOURCE_FLAG_TRANSFER ?
+    tex->domain = base->flags & R300_RESOURCE_FLAG_TRANSFER ? RADEON_DOMAIN_GTT :
-                  RADEON_DOMAIN_GTT :
+                  base->nr_samples > 1 ? RADEON_DOMAIN_VRAM :
-                  RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT;
+                                         RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT;
     tex->buf = buffer;
 
     r300_texture_desc_init(rscreen, tex, base);

src/gallium/drivers/r600/evergreen_hw_context.c

@@ -243,9 +243,9 @@ void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_en
 void evergreen_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
+		uint64_t dst_offset,
-		unsigned long src_offset,
+		uint64_t src_offset,
-		unsigned long size)
+		uint64_t size)
 {
 	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 	unsigned i, ncopy, csize, sub_cmd, shift;
@@ -283,4 +283,7 @@ void evergreen_dma_copy(struct r600_context *rctx,
 		src_offset += csize << shift;
 		size -= csize;
 	}
+
+	util_range_add(&rdst->valid_buffer_range, dst_offset,
+		       dst_offset + size);
 }

src/gallium/drivers/r600/evergreen_state.c

@@ -808,6 +808,7 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
 	dsa->valuemask[1] = state->stencil[1].valuemask;
 	dsa->writemask[0] = state->stencil[0].writemask;
 	dsa->writemask[1] = state->stencil[1].writemask;
+	dsa->zwritemask = state->depth.writemask;
 
 	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
@@ -1321,6 +1322,10 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
 	 * elements. */
 	surf->cb_color_dim = pipe_buffer->width0;
 
+	/* Set the buffer range the GPU will have access to: */
+	util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
+		       0, pipe_buffer->width0);
+
 	surf->cb_color_cmask = surf->cb_color_base;
 	surf->cb_color_cmask_slice = 0;
 	surf->cb_color_fmask = surf->cb_color_base;
@@ -1405,10 +1410,15 @@ void evergreen_init_color_surface(struct r600_context *rctx,
 			S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
 		        S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
 
-	if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
+	if (rctx->chip_class == CAYMAN) {
-		unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
+		color_attrib |=	S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
-		color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
+							   UTIL_FORMAT_SWIZZLE_1);
-				S_028C74_NUM_FRAGMENTS(log_samples);
+
+		if (rtex->resource.b.b.nr_samples > 1) {
+			unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
+			color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
+					S_028C74_NUM_FRAGMENTS(log_samples);
+		}
 	}
 
 	ntype = V_028C70_NUMBER_UNORM;
@@ -1647,6 +1657,11 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	if (rctx->framebuffer.state.zsbuf) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+
+		rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
+		if (rtex->htile) {
+			rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
+		}
 	}
 
 	util_copy_framebuffer_state(&rctx->framebuffer.state, state);
@@ -1668,6 +1683,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 		surf = (struct r600_surface*)state->cbufs[i];
 		rtex = (struct r600_texture*)surf->base.texture;
 
+		r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
+
 		if (!surf->color_initialized) {
 			evergreen_init_color_surface(rctx, surf);
 		}
@@ -1699,6 +1716,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	if (state->zsbuf) {
 		surf = (struct r600_surface*)state->zsbuf;
 
+		r600_context_add_resource_size(ctx, state->zsbuf->texture);
+
 		if (!surf->depth_initialized) {
 			evergreen_init_depth_surface(rctx, surf);
 		}
@@ -2218,9 +2237,23 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_
 		}
 		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
 	}
-	if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
+	/* FIXME we should be able to use hyperz even if we are not writing to
+	 * zbuffer but somehow this trigger GPU lockup. See :
+	 *
+	 * https://bugs.freedesktop.org/show_bug.cgi?id=60848
+	 *
+	 * Disable hyperz for now if not writing to zbuffer.
+	 */
+	if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
 		/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
 		db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
+		/* This is to fix a lockup when hyperz and alpha test are enabled at
+		 * the same time somehow GPU get confuse on which order to pick for
+		 * z test
+		 */
+		if (rctx->alphatest_state.sx_alpha_test_control) {
+			db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
+		}
 	} else {
 		db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
 	}
@@ -3210,7 +3243,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_pipe_state *rstate = &shader->rstate;
 	struct r600_shader *rshader = &shader->shader;
-	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
+	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
 	int pos_index = -1, face_index = -1;
 	int ninterp = 0;
 	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
@@ -3220,7 +3253,6 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 
 	rstate->nregs = 0;
 
-	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 	for (i = 0; i < rshader->ninput; i++) {
 		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
 		   POSITION goes via GPRs from the SC so isn't counted */
@@ -3454,6 +3486,24 @@ void evergreen_update_db_shader_control(struct r600_context * rctx)
 								V_02880C_EXPORT_DB_FULL) |
 			S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
 
+	/* When alpha test is enabled we can't trust the hw to make the proper
+	 * decision on the order in which ztest should be run related to fragment
+	 * shader execution.
+	 *
+	 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
+	 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
+	 * execution and thus after alpha test so if discarded by the alpha test
+	 * the z value is not written.
+	 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
+	 * get a hang unless you flush the DB in between.  For now just use
+	 * LATE_Z.
+	 */
+	if (rctx->alphatest_state.sx_alpha_test_control) {
+		db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
+	} else {
+		db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	}
+
 	if (db_shader_control != rctx->db_misc_state.db_shader_control) {
 		rctx->db_misc_state.db_shader_control = db_shader_control;
 		rctx->db_misc_state.atom.dirty = true;
@@ -3481,7 +3531,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
 	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 	unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
 	unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
-	unsigned long base, addr;
+	uint64_t base, addr;
 
 	/* make sure that the dma ring is only one active */
 	rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3502,7 +3552,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
 	if (dst_mode == RADEON_SURF_MODE_LINEAR) {
 		/* T2L */
 		array_mode = evergreen_array_mode(src_mode);
-		slice_tile_max = (((pitch * rsrc->surface.level[src_level].npix_y) >> 6) / bpp) - 1;
+		slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
+		slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 		/* linear height must be the same as the slice tile max height, it's ok even
 		 * if the linear destination/source have smaller heigh as the size of the
 		 * dma packet will be using the copy_height which is always smaller or equal
@@ -3526,7 +3577,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
 	} else {
 		/* L2T */
 		array_mode = evergreen_array_mode(dst_mode);
-		slice_tile_max = (((pitch * rdst->surface.level[dst_level].npix_y) >> 6) / bpp) - 1;
+		slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
+		slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 		/* linear height must be the same as the slice tile max height, it's ok even
 		 * if the linear destination/source have smaller heigh as the size of the
 		 * dma packet will be using the copy_height which is always smaller or equal
@@ -3624,8 +3676,19 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
 		return FALSE;
 	}
 
+	/* 128 bpp surfaces require non_disp_tiling for both
+	 * tiled and linear buffers on cayman.  However, async
+	 * DMA only supports it on the tiled side.  As such
+	 * the tile order is backwards after a L2T/T2L packet.
+	 */
+	if ((rctx->chip_class == CAYMAN) &&
+	    (src_mode != dst_mode) &&
+	    (util_format_get_blocksize(src->format) >= 16)) {
+		return FALSE;
+	}
+
 	if (src_mode == dst_mode) {
-		unsigned long dst_offset, src_offset;
+		uint64_t dst_offset, src_offset;
 		/* simple dma blit would do NOTE code here assume :
 		 *   src_box.x/y == 0
 		 *   dst_x/y == 0

src/gallium/drivers/r600/r600.h

@@ -28,6 +28,7 @@
 
 #include "../../winsys/radeon/drm/radeon_winsys.h"
 #include "util/u_double_list.h"
+#include "util/u_range.h"
 #include "util/u_transfer.h"
 
 #define R600_ERR(fmt, args...) \
@@ -50,6 +51,16 @@ struct r600_resource {
 
 	/* Resource state. */
 	unsigned			domains;
+
+	/* The buffer range which is initialized (with a write transfer,
+	 * streamout, DMA, or as a random access target). The rest of
+	 * the buffer is considered invalid and can be mapped unsynchronized.
+	 *
+	 * This allows unsychronized mapping of a buffer range which hasn't
+	 * been used yet. It's for applications which forget to use
+	 * the unsynchronized map flag and expect the driver to figure it out.
+         */
+	struct util_range		valid_buffer_range;
 };
 
 #define R600_BLOCK_MAX_BO		32
@@ -151,6 +162,8 @@ struct r600_so_target {
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(1 << 3)
 #define R600_CONTEXT_FLUSH_AND_INV		(1 << 4)
 #define R600_CONTEXT_FLUSH_AND_INV_CB_META	(1 << 5)
+#define R600_CONTEXT_PS_PARTIAL_FLUSH		(1 << 6)
+#define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 7)
 
 struct r600_context;
 struct r600_screen;
@@ -174,9 +187,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
 void r600_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
+		uint64_t dst_offset,
-		unsigned long src_offset,
+		uint64_t src_offset,
-		unsigned long size);
+		uint64_t size);
 boolean r600_dma_blit(struct pipe_context *ctx,
 			struct pipe_resource *dst,
 			unsigned dst_level,
@@ -187,9 +200,9 @@ boolean r600_dma_blit(struct pipe_context *ctx,
 void evergreen_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
+		uint64_t dst_offset,
-		unsigned long src_offset,
+		uint64_t src_offset,
-		unsigned long size);
+		uint64_t size);
 boolean evergreen_dma_blit(struct pipe_context *ctx,
 			struct pipe_resource *dst,
 			unsigned dst_level,

src/gallium/drivers/r600/r600_asm.c

@@ -68,13 +68,17 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
@@ -150,13 +154,17 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
@@ -314,6 +322,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
 		output->swizzle_y == bc->cf_last->output.swizzle_y &&
 		output->swizzle_z == bc->cf_last->output.swizzle_z &&
 		output->swizzle_w == bc->cf_last->output.swizzle_w &&
+		output->comp_mask == bc->cf_last->output.comp_mask &&
 		(output->burst_count + bc->cf_last->output.burst_count) <= 16) {
 
 		if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
@@ -865,12 +874,6 @@ static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
 	bank_swizzle[4] = SQ_ALU_SCL_210;
 	while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
 
-		if (max_slots == 4) {
-			for (i = 0; i < max_slots; i++) {
-				if (bank_swizzle[i] == SQ_ALU_VEC_210)
-				  return -1;
-			}
-		}
 		init_bank_swizzle(&bs);
 		if (scalar_only == false) {
 			for (i = 0; i < 4; i++) {
@@ -902,8 +905,10 @@ static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
 					bank_swizzle[i]++;
 					if (bank_swizzle[i] <= SQ_ALU_VEC_210)
 						break;
-					else
+					else if (i < max_slots - 1)
 						bank_swizzle[i] = SQ_ALU_VEC_012;
+					else
+						return -1;
 				}
 			}
 		}

src/gallium/drivers/r600/r600_blit.c

@@ -523,6 +523,37 @@ void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsig
 	}
 }
 
+static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
+			      unsigned offset, unsigned size, unsigned char value)
+{
+	struct r600_context *rctx = (struct r600_context*)ctx;
+
+	if (rctx->screen->has_streamout && offset % 4 == 0 && size % 4 == 0) {
+		union pipe_color_union clear_value;
+		uint32_t v = value;
+
+		clear_value.ui[0] = v | (v << 8) | (v << 16) | (v << 24);
+
+		r600_blitter_begin(ctx, R600_DISABLE_RENDER_COND);
+		util_blitter_clear_buffer(rctx->blitter, dst, offset, size,
+					  1, &clear_value);
+		r600_blitter_end(ctx);
+	} else {
+		char *map = r600_buffer_mmap_sync_with_rings(rctx, r600_resource(dst),
+							     PIPE_TRANSFER_WRITE);
+		memset(map + offset, value, size);
+	}
+}
+
+void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
+			      unsigned offset, unsigned size, unsigned char value)
+{
+	pipe_mutex_lock(rscreen->aux_context_lock);
+	r600_clear_buffer(rscreen->aux_context, dst, offset, size, value);
+	rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
+	pipe_mutex_unlock(rscreen->aux_context_lock);
+}
+
 static bool util_format_is_subsampled_2x1_32bpp(enum pipe_format format)
 {
 	const struct util_format_description *desc = util_format_description(format);

src/gallium/drivers/r600/r600_buffer.c

@@ -34,6 +34,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 {
 	struct r600_resource *rbuffer = r600_resource(buf);
 
+	util_range_destroy(&rbuffer->valid_buffer_range);
 	pb_reference(&rbuffer->buf, NULL);
 	FREE(rbuffer);
 }
@@ -98,6 +99,14 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 
 	assert(box->x + box->width <= resource->width0);
 
+	/* See if the buffer range being mapped has never been initialized,
+	 * in which case it can be mapped unsynchronized. */
+	if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
+	    usage & PIPE_TRANSFER_WRITE &&
+	    !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
+		usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
+	}
+
 	if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 	    !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 		assert(usage & PIPE_TRANSFER_WRITE);
@@ -178,6 +187,7 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 {
 	struct r600_context *rctx = (struct r600_context*)pipe;
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+	struct r600_resource *rbuffer = r600_resource(transfer->resource);
 
 	if (rtransfer->staging) {
 		struct pipe_resource *dst, *src;
@@ -189,7 +199,7 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 		doffset = transfer->box.x;
 		soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
 		/* Copy the staging buffer into the original one. */
-		if (rctx->rings.dma.cs && !(size % 4) && !(doffset % 4) && !(soffset)) {
+		if (rctx->rings.dma.cs && !(size % 4) && !(doffset % 4) && !(soffset % 4)) {
 			if (rctx->screen->chip_class >= EVERGREEN) {
 				evergreen_dma_copy(rctx, dst, src, doffset, soffset, size);
 			} else {
@@ -203,6 +213,11 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 		}
 		pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 	}
+
+	if (transfer->usage & PIPE_TRANSFER_WRITE) {
+		util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
+			       transfer->box.x + transfer->box.width);
+	}
 	util_slab_free(&rctx->pool_transfers, transfer);
 }
 
@@ -259,6 +274,7 @@ bool r600_init_resource(struct r600_screen *rscreen,
 
 	res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
 	res->domains = domains;
+	util_range_set_empty(&res->valid_buffer_range);
 	return true;
 }
 
@@ -275,6 +291,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 	pipe_reference_init(&rbuffer->b.b.reference, 1);
 	rbuffer->b.b.screen = screen;
 	rbuffer->b.vtbl = &r600_buffer_vtbl;
+	util_range_init(&rbuffer->valid_buffer_range);
 
 	if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) {
 		FREE(rbuffer);

src/gallium/drivers/r600/r600_hw_context.c

@@ -359,6 +359,16 @@ out_err:
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 			boolean count_draw_in)
 {
+	if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
+		ctx->gtt = 0;
+		ctx->vram = 0;
+		ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+		return;
+	}
+	/* all will be accounted once relocation are emited */
+	ctx->gtt = 0;
+	ctx->vram = 0;
+
 	/* The number of dwords we already used in the CS so far. */
 	num_dw += ctx->rings.gfx.cs->cdw;
 
@@ -623,17 +633,27 @@ void r600_flush_emit(struct r600_context *rctx)
 		/* Use of WAIT_UNTIL is deprecated on Cayman+ */
 		if (rctx->family >= CHIP_CAYMAN) {
 			/* emit a PS partial flush on Cayman/TN */
-			cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+			rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
-			cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 		}
 	}
 
+	if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
+		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+	}
+
 	if (rctx->chip_class >= R700 &&
 	    (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
 		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
 	}
 
+	if (rctx->chip_class >= R700 &&
+	    (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
+		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
+	}
+
 	if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
 		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
@@ -728,6 +748,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	 */
 	ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
 		      R600_CONTEXT_FLUSH_AND_INV_CB_META |
+		      R600_CONTEXT_FLUSH_AND_INV_DB_META |
 		      R600_CONTEXT_WAIT_3D_IDLE |
 		      R600_CONTEXT_WAIT_CP_DMA_IDLE;
 
@@ -784,6 +805,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
 
 	ctx->pm4_dirty_cdwords = 0;
 	ctx->flags = 0;
+	ctx->gtt = 0;
+	ctx->vram = 0;
 
 	/* Begin a new CS. */
 	r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
@@ -1103,6 +1126,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
 		       R600_CONTEXT_FLUSH_AND_INV |
 		       R600_CONTEXT_FLUSH_AND_INV_CB_META |
+		       R600_CONTEXT_FLUSH_AND_INV_DB_META |
 		       R600_CONTEXT_STREAMOUT_FLUSH |
 		       R600_CONTEXT_WAIT_3D_IDLE;
 
@@ -1145,6 +1169,12 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 		src_offset += byte_count;
 		dst_offset += byte_count;
 	}
+
+	/* Invalidate the read caches. */
+	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
+
+	util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
+		       dst_offset + size);
 }
 
 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
@@ -1160,9 +1190,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
 void r600_dma_copy(struct r600_context *rctx,
 		struct pipe_resource *dst,
 		struct pipe_resource *src,
-		unsigned long dst_offset,
+		uint64_t dst_offset,
-		unsigned long src_offset,
+		uint64_t src_offset,
-		unsigned long size)
+		uint64_t size)
 {
 	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 	unsigned i, ncopy, csize, shift;
@@ -1191,4 +1221,7 @@ void r600_dma_copy(struct r600_context *rctx,
 		src_offset += csize << shift;
 		size -= csize;
 	}
+
+	util_range_add(&rdst->valid_buffer_range, dst_offset,
+		       dst_offset + size);
 }

src/gallium/drivers/r600/r600_hw_context_priv.h

@@ -29,7 +29,7 @@
 #include "r600_pipe.h"
 
 /* the number of CS dwords for flushing and drawing */
-#define R600_MAX_FLUSH_CS_DWORDS	12
+#define R600_MAX_FLUSH_CS_DWORDS	16
 #define R600_MAX_DRAW_CS_DWORDS		34
 #define R600_TRACE_CS_DWORDS		7
 

src/gallium/drivers/r600/r600_llvm.c

@@ -38,8 +38,12 @@ static LLVMValueRef llvm_fetch_const(
 		LLVMValueRef index = LLVMBuildLoad(bld_base->base.gallivm->builder, bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
 		offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder, offset[1], index, "");
 	}
+	unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
+	if (reg->Register.Dimension) {
+		ConstantAddressSpace += reg->Dimension.Index;
+	}
 	LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024),
-							CONSTANT_BUFFER_0_ADDR_SPACE);
+							ConstantAddressSpace);
 	LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
 	LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
 	LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
@@ -537,6 +541,7 @@ const char * r600_llvm_gpu_string(enum radeon_family family)
 	case CHIP_RV630:
 	case CHIP_RV620:
 	case CHIP_RV635:
+	case CHIP_RV670:
 	case CHIP_RS780:
 	case CHIP_RS880:
 		gpu_family = "r600";
@@ -547,7 +552,6 @@ const char * r600_llvm_gpu_string(enum radeon_family family)
 	case CHIP_RV730:
 		gpu_family = "rv730";
 		break;
-	case CHIP_RV670:
 	case CHIP_RV740:
 	case CHIP_RV770:
 		gpu_family = "rv770";

src/gallium/drivers/r600/r600_pipe.c

@@ -22,6 +22,7 @@
  */
 #include "r600_pipe.h"
 #include "r600_public.h"
+#include "r600d.h"
 
 #include <errno.h>
 #include "pipe/p_shader_tokens.h"
@@ -165,12 +166,23 @@ static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
+	struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
+	unsigned padding_dw, i;
 
-	if (!rctx->rings.dma.cs->cdw) {
+	if (!cs->cdw) {
 		return;
 	}
+
+	/* Pad the DMA CS to a multiple of 8 dwords. */
+	padding_dw = 8 - cs->cdw % 8;
+	if (padding_dw < 8) {
+		for (i = 0; i < padding_dw; i++) {
+			cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
+		}
+	}
+
 	rctx->rings.dma.flushing = true;
-	rctx->ws->cs_flush(rctx->rings.dma.cs, flags);
+	rctx->ws->cs_flush(cs, flags);
 	rctx->rings.dma.flushing = false;
 }
 
@@ -822,6 +834,9 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
 	if (rscreen == NULL)
 		return;
 
+	pipe_mutex_destroy(rscreen->aux_context_lock);
+	rscreen->aux_context->destroy(rscreen->aux_context);
+
 	if (rscreen->global_pool) {
 		compute_memory_pool_delete(rscreen->global_pool);
 	}
@@ -1145,7 +1160,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 	 * case were triggering lockup quickly such as :
 	 * piglit/bin/depthstencil-render-miplevels 1024 d=s=z24_s8
 	 */
-	rscreen->use_hyperz = debug_get_bool_option("R600_HYPERZ", TRUE);
+	rscreen->use_hyperz = debug_get_bool_option("R600_HYPERZ", FALSE);
 	rscreen->use_hyperz = rscreen->info.drm_minor >= 26 ? rscreen->use_hyperz : FALSE;
 
 	rscreen->global_pool = compute_memory_pool_new(rscreen);
@@ -1164,5 +1179,41 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 	}
 #endif
 
+	/* Create the auxiliary context. */
+	pipe_mutex_init(rscreen->aux_context_lock);
+	rscreen->aux_context = rscreen->screen.context_create(&rscreen->screen, NULL);
+
+#if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
+	struct pipe_resource templ = {};
+
+	templ.width0 = 4;
+	templ.height0 = 2048;
+	templ.depth0 = 1;
+	templ.array_size = 1;
+	templ.target = PIPE_TEXTURE_2D;
+	templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
+	templ.usage = PIPE_USAGE_STATIC;
+
+	struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
+	unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
+
+	memset(map, 0, 256);
+
+	r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
+	r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
+	r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
+	r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
+	r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
+
+	ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
+
+	int i;
+	for (i = 0; i < 256; i++) {
+		printf("%02X", map[i]);
+		if (i % 16 == 15)
+			printf("\n");
+	}
+#endif
+
 	return &rscreen->screen;
 }

src/gallium/drivers/r600/r600_pipe.h

@@ -252,6 +252,11 @@ struct r600_screen {
 	unsigned			cs_count;
 #endif
 	r600g_dma_blit_t		dma_blit;
+
+	/* Auxiliary context. Mainly used to initialize resources.
+	 * It must be locked prior to using and flushed before unlocking. */
+	struct pipe_context		*aux_context;
+	pipe_mutex			aux_context_lock;
 };
 
 struct r600_pipe_sampler_view {
@@ -298,7 +303,8 @@ struct r600_dsa_state {
 	unsigned			alpha_ref;
 	ubyte				valuemask[2];
 	ubyte				writemask[2];
-	unsigned                        sx_alpha_test_control;
+	unsigned			zwritemask;
+	unsigned			sx_alpha_test_control;
 };
 
 struct r600_pipe_shader;
@@ -447,6 +453,10 @@ struct r600_context {
 	unsigned			backend_mask;
 	unsigned			max_db; /* for OQ */
 
+	/* current unaccounted memory usage */
+	uint64_t			vram;
+	uint64_t			gtt;
+
 	/* Miscellaneous state objects. */
 	void				*custom_dsa_flush;
 	void				*custom_blend_resolve;
@@ -509,6 +519,7 @@ struct r600_context {
 	bool				alpha_to_one;
 	bool				force_blend_disable;
 	boolean				dual_src_blend;
+	unsigned			zwritemask;
 
 	/* Index buffer. */
 	struct pipe_index_buffer	index_buffer;
@@ -624,6 +635,8 @@ void evergreen_update_db_shader_control(struct r600_context * rctx);
 /* r600_blit.c */
 void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
 		      struct pipe_resource *src, const struct pipe_box *src_box);
+void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
+			      unsigned offset, unsigned size, unsigned char value);
 void r600_init_blit_functions(struct r600_context *rctx);
 void r600_blit_decompress_depth(struct pipe_context *ctx,
 		struct r600_texture *texture,
@@ -869,9 +882,11 @@ static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
 	 * look serialized from driver pov
 	 */
 	if (!ring->flushing) {
-		if (ring == &ctx->rings.gfx && ctx->rings.dma.cs) {
+		if (ring == &ctx->rings.gfx) {
-			/* flush dma ring */
+			if (ctx->rings.dma.cs) {
-			ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+				/* flush dma ring */
+				ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+			}
 		} else {
 			/* flush gfx ring */
 			ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
@@ -996,4 +1011,28 @@ static INLINE unsigned u_max_layer(struct pipe_resource *r, unsigned level)
 	}
 }
 
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+	struct r600_context *rctx = (struct r600_context *)ctx;
+	struct r600_resource *rr = (struct r600_resource *)r;
+
+	if (r == NULL) {
+		return;
+	}
+
+	/*
+	 * The idea is to compute a gross estimate of memory requirement of
+	 * each draw call. After each draw call, memory will be precisely
+	 * accounted. So the uncertainty is only on the current draw call.
+	 * In practice this gave very good estimate (+/- 10% of the target
+	 * memory limit).
+	 */
+	if (rr->domains & RADEON_DOMAIN_GTT) {
+		rctx->gtt += rr->buf->size;
+	}
+	if (rr->domains & RADEON_DOMAIN_VRAM) {
+		rctx->vram += rr->buf->size;
+	}
+}
+
 #endif

src/gallium/drivers/r600/r600_query.c

@@ -186,10 +186,11 @@ static void r600_emit_query_end(struct r600_context *ctx, struct r600_query *que
 	case PIPE_QUERY_PRIMITIVES_GENERATED:
 	case PIPE_QUERY_SO_STATISTICS:
 	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+		va += query->buffer.results_end + query->result_size/2;
 		cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
 		cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
-		cs->buf[cs->cdw++] = query->buffer.results_end + query->result_size/2;
+		cs->buf[cs->cdw++] = va;
-		cs->buf[cs->cdw++] = 0;
+		cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 		break;
 	case PIPE_QUERY_TIME_ELAPSED:
 		va += query->buffer.results_end + query->result_size/2;

src/gallium/drivers/r600/r600_shader.c

@@ -5760,7 +5760,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bytecode_alu alu;
-	int i, j, r;
+	int i, j, k, r;
 	int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
 
 	/* src0 * src1 */
@@ -5768,21 +5768,40 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
 			continue;
 
-		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+                if (ctx->bc->chip_class == CAYMAN) {
+                        for (j = 0; j < 4; j++) {
+                                memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+                                alu.dst.chan = j;
+                                alu.dst.sel = ctx->temp_reg;
+                                alu.dst.write = (j == i);
 
-		alu.dst.chan = i;
+                                if (j == 3)
-		alu.dst.sel = ctx->temp_reg;
+                                        alu.last = 1;
-		alu.dst.write = 1;
+                                alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+                                for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
+                                        r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
+                                }
+                                r = r600_bytecode_add_alu(ctx->bc, &alu);
+                                if (r)
+                                        return r;
+                        }
+                } else {
+                        memset(&alu, 0, sizeof(struct r600_bytecode_alu));
 
-		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+                        alu.dst.chan = i;
-		for (j = 0; j < 2; j++) {
+                        alu.dst.sel = ctx->temp_reg;
-		        r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
+                        alu.dst.write = 1;
-		}
 
-		alu.last = 1;
+                        alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
-		r = r600_bytecode_add_alu(ctx->bc, &alu);
+                        for (j = 0; j < 2; j++) {
-		if (r)
+                                r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
-			return r;
+                        }
+
+                        alu.last = 1;
+                        r = r600_bytecode_add_alu(ctx->bc, &alu);
+                        if (r)
+                                return r;
+                }
 	}
 
 

src/gallium/drivers/r600/r600_state.c

@@ -802,6 +802,7 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
 	dsa->valuemask[1] = state->stencil[1].valuemask;
 	dsa->writemask[0] = state->stencil[0].writemask;
 	dsa->writemask[1] = state->stencil[1].writemask;
+	dsa->zwritemask = state->depth.writemask;
 
 	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
@@ -1515,6 +1516,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	if (rctx->framebuffer.state.zsbuf) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+
+		rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
+		if (rctx->chip_class >= R700 && rtex->htile) {
+			rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
+		}
 	}
 
 	/* Set the new state. */
@@ -1544,6 +1550,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 
 		surf = (struct r600_surface*)state->cbufs[i];
 		rtex = (struct r600_texture*)surf->base.texture;
+		r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
 
 		if (!surf->color_initialized || force_cmask_fmask) {
 			r600_init_color_surface(rctx, surf, force_cmask_fmask);
@@ -1576,6 +1583,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	if (state->zsbuf) {
 		surf = (struct r600_surface*)state->zsbuf;
 
+		r600_context_add_resource_size(ctx, state->zsbuf->texture);
+
 		if (!surf->depth_initialized) {
 			r600_init_depth_surface(rctx, surf);
 		}
@@ -1937,6 +1946,13 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
 	if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
 		/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
 		db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
+		/* This is to fix a lockup when hyperz and alpha test are enabled at
+		 * the same time somehow GPU get confuse on which order to pick for
+		 * z test
+		 */
+		if (rctx->alphatest_state.sx_alpha_test_control) {
+			db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
+		}
 	} else {
 		db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
 	}
@@ -2745,7 +2761,7 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
 				tmp);
 	}
 
-	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	db_shader_control = 0;
 	for (i = 0; i < rshader->noutput; i++) {
 		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
 			z_export = 1;
@@ -2940,6 +2956,19 @@ void r600_update_db_shader_control(struct r600_context * rctx)
 	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
 				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
 
+	/* When alpha test is enabled we can't trust the hw to make the proper
+	 * decision on the order in which ztest should be run related to fragment
+	 * shader execution.
+	 *
+	 * If alpha test is enabled perform z test after fragment. RE_Z (early
+	 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
+	 */
+	if (rctx->alphatest_state.sx_alpha_test_control) {
+		db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
+	} else {
+		db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	}
+
 	if (db_shader_control != rctx->db_misc_state.db_shader_control) {
 		rctx->db_misc_state.db_shader_control = db_shader_control;
 		rctx->db_misc_state.atom.dirty = true;
@@ -2979,7 +3008,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
 	struct r600_texture *rdst = (struct r600_texture*)dst;
 	unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 	unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
-	unsigned long base, addr;
+	uint64_t base, addr;
 
 	/* make sure that the dma ring is only one active */
 	rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -2998,7 +3027,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
 	if (dst_mode == RADEON_SURF_MODE_LINEAR) {
 		/* T2L */
 		array_mode = r600_array_mode(src_mode);
-		slice_tile_max = (((pitch * rsrc->surface.level[src_level].npix_y) >> 6) / bpp) - 1;
+		slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
+		slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 		/* linear height must be the same as the slice tile max height, it's ok even
 		 * if the linear destination/source have smaller heigh as the size of the
 		 * dma packet will be using the copy_height which is always smaller or equal
@@ -3016,7 +3046,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
 	} else {
 		/* L2T */
 		array_mode = r600_array_mode(dst_mode);
-		slice_tile_max = (((pitch * rdst->surface.level[dst_level].npix_y) >> 6) / bpp) - 1;
+		slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
+		slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 		/* linear height must be the same as the slice tile max height, it's ok even
 		 * if the linear destination/source have smaller heigh as the size of the
 		 * dma packet will be using the copy_height which is always smaller or equal
@@ -3037,14 +3068,15 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
 		return FALSE;
 	}
 
-	size = (copy_height * pitch) >> 2;
+	/* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
-	ncopy = (size / 0x0000ffff) + !!(size % 0x0000ffff);
+	 * line in the blit. Compute max 8 line we can copy in the size limit
+	 */
+	cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
+	ncopy = (copy_height / cheight) + !!(copy_height % cheight);
 	r600_need_dma_space(rctx, ncopy * 7);
+
 	for (i = 0; i < ncopy; i++) {
-		cheight = copy_height;
+		cheight = cheight > copy_height ? copy_height : cheight;
-		if (((cheight * pitch) >> 2) > 0x0000ffff) {
-			cheight = (0x0000ffff << 2) / pitch;
-		}
 		size = (cheight * pitch) >> 2;
 		/* emit reloc before writting cs so that cs is always in consistent state */
 		r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
@@ -3109,7 +3141,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
 	}
 
 	if (src_mode == dst_mode) {
-		unsigned long dst_offset, src_offset, size;
+		uint64_t dst_offset, src_offset, size;
 
 		/* simple dma blit would do NOTE code here assume :
 		 *   src_box.x/y == 0

src/gallium/drivers/r600/r600_state_common.c

@@ -284,6 +284,16 @@ static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 	ref.valuemask[1] = dsa->valuemask[1];
 	ref.writemask[0] = dsa->writemask[0];
 	ref.writemask[1] = dsa->writemask[1];
+	if (rctx->zwritemask != dsa->zwritemask) {
+		rctx->zwritemask = dsa->zwritemask;
+		if (rctx->chip_class >= EVERGREEN) {
+			/* work around some issue when not writting to zbuffer
+			 * we are having lockup on evergreen so do not enable
+			 * hyperz when not writting zbuffer
+			 */
+			rctx->db_misc_state.atom.dirty = true;
+		}
+	}
 
 	r600_set_stencil_ref(ctx, &ref);
 
@@ -293,6 +303,11 @@ static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 		rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 		rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 		rctx->alphatest_state.atom.dirty = true;
+		if (rctx->chip_class >= EVERGREEN) {
+			evergreen_update_db_shader_control(rctx);
+		} else {
+			r600_update_db_shader_control(rctx);
+		}
 	}
 }
 
@@ -479,7 +494,8 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 
 	if (ib) {
 		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
-	        memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+		memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+		r600_context_add_resource_size(ctx, ib->buffer);
 	} else {
 		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 	}
@@ -516,6 +532,7 @@ static void r600_set_vertex_buffers(struct pipe_context *ctx,
 					vb[i].buffer_offset = input[i].buffer_offset;
 					pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 					new_buffer_mask |= 1 << i;
+					r600_context_add_resource_size(ctx, input[i].buffer);
 				} else {
 					pipe_resource_reference(&vb[i].buffer, NULL);
 					disable_mask |= 1 << i;
@@ -613,6 +630,7 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 
 			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 			new_mask |= 1 << i;
+			r600_context_add_resource_size(pipe, views[i]->texture);
 		} else {
 			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 			disable_mask |= 1 << i;
@@ -702,6 +720,7 @@ static int r600_shader_select(struct pipe_context *ctx,
 	struct r600_pipe_shader * shader = NULL;
 	int r;
 
+	memset(&key, 0, sizeof(key));
 	key = r600_shader_selector_key(ctx, sel);
 
 	/* Check if we don't need to change anything.
@@ -748,7 +767,7 @@ static int r600_shader_select(struct pipe_context *ctx,
 			key = r600_shader_selector_key(ctx, sel);
 		}
 
-		shader->key = key;
+		memcpy(&shader->key, &key, sizeof(key));
 		sel->num_shaders++;
 	}
 
@@ -806,6 +825,8 @@ static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 	rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 	r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 
+	r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
+
 	if (rctx->chip_class <= R700) {
 		bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 
@@ -835,6 +856,8 @@ static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 	if (state) {
 		r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
 
+		r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
+
 		/* Update clip misc state. */
 		if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
 		    rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
@@ -938,10 +961,13 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 		} else {
 			u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 		}
+		/* account it in gtt */
+		rctx->gtt += input->buffer_size;
 	} else {
 		/* Setup the hw buffer. */
 		cb->buffer_offset = input->buffer_offset;
 		pipe_resource_reference(&cb->buffer, input->buffer);
+		r600_context_add_resource_size(ctx, input->buffer);
 	}
 
 	state->enabled_mask |= 1 << index;
@@ -957,6 +983,7 @@ r600_create_so_target(struct pipe_context *ctx,
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_so_target *t;
+	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
 
 	t = CALLOC_STRUCT(r600_so_target);
 	if (!t) {
@@ -976,6 +1003,9 @@ r600_create_so_target(struct pipe_context *ctx,
 	pipe_resource_reference(&t->b.buffer, buffer);
 	t->b.buffer_offset = buffer_offset;
 	t->b.buffer_size = buffer_size;
+
+	util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
+		       buffer_offset + buffer_size);
 	return &t->b;
 }
 
@@ -1004,6 +1034,7 @@ static void r600_set_so_targets(struct pipe_context *ctx,
 	/* Set the new targets. */
 	for (i = 0; i < num_targets; i++) {
 		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
+		r600_context_add_resource_size(ctx, targets[i]->buffer);
 	}
 	for (; i < rctx->num_so_targets; i++) {
 		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
@@ -1343,6 +1374,12 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		rctx->vgt_state.atom.dirty = true;
 	}
 
+	/* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
+	if (rctx->chip_class == R600) {
+		rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+		rctx->cb_misc_state.atom.dirty = true;
+	}
+
 	/* Emit states. */
 	r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
 	r600_flush_emit(rctx);

src/gallium/drivers/r600/r600_texture.c

@@ -270,6 +270,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	if (rtex->flushed_depth_texture)
 		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 
+        pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
 	pb_reference(&resource->buf, NULL);
 	FREE(rtex);
 }
@@ -479,10 +480,7 @@ r600_texture_create_object(struct pipe_screen *screen,
 			 */
 			R600_ERR("r600: failed to create bo for htile buffers\n");
 		} else {
-			void *ptr;
+			r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
-			ptr = rscreen->ws->buffer_map(rtex->htile->cs_buf, NULL, PIPE_TRANSFER_WRITE);
-			memset(ptr, 0x0, htile_size);
-			rscreen->ws->buffer_unmap(rtex->htile->cs_buf);
 		}
 	}
 
@@ -504,9 +502,8 @@ r600_texture_create_object(struct pipe_screen *screen,
 
 	if (rtex->cmask_size) {
 		/* Initialize the cmask to 0xCC (= compressed state). */
-		char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
+		r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
-		memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
+					 rtex->cmask_offset, rtex->cmask_size, 0xCC);
-		rscreen->ws->buffer_unmap(resource->cs_buf);
 	}
 
 	if (debug_get_option_print_texdepth() && rtex->is_depth && rtex->non_disp_tiling) {

src/gallium/drivers/r600/r600d.h

@@ -119,6 +119,7 @@
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH	0x1f
 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS	0x20
+#define EVENT_TYPE_FLUSH_AND_INV_DB_META       0x2c /* supported on r700+ */
 #define EVENT_TYPE_FLUSH_AND_INV_CB_META	46 /* supported on r700+ */
 #define		EVENT_TYPE(x)                           ((x) << 0)
 #define		EVENT_INDEX(x)                          ((x) << 8)

src/gallium/drivers/radeon/Makefile.am

@@ -1,11 +1,14 @@
 include Makefile.sources
 include $(top_srcdir)/src/gallium/Automake.inc
 
+LIBGALLIUM_LIBS=
+
 if HAVE_GALLIUM_R600
 if HAVE_GALLIUM_RADEONSI
 lib_LTLIBRARIES = libllvmradeon@VERSION@.la
 libllvmradeon@VERSION@_la_LDFLAGS = -Wl, -shared -avoid-version \
 	$(LLVM_LDFLAGS)
+LIBGALLIUM_LIBS += $(top_builddir)/src/gallium/auxiliary/libgallium.la
 else
 noinst_LTLIBRARIES = libllvmradeon@VERSION@.la
 endif
@@ -26,5 +29,6 @@ libllvmradeon@VERSION@_la_SOURCES = \
 	$(C_FILES)
 
 libllvmradeon@VERSION@_la_LIBADD = \
+	$(LIBGALLIUM_LIBS) \
 	$(CLOCK_LIB) \
 	$(LLVM_LIBS)

src/gallium/drivers/radeon/radeon_llvm.h

@@ -155,7 +155,7 @@ static inline LLVMValueRef bitcast(
 
 void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
                                           struct lp_build_emit_data * emit_data,
-                                          unsigned coord_arg);
+                                          LLVMValueRef *coords_arg);
 
 void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
 

src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c

@@ -531,7 +531,7 @@ static void kil_emit(
 void radeon_llvm_emit_prepare_cube_coords(
 		struct lp_build_tgsi_context * bld_base,
 		struct lp_build_emit_data * emit_data,
-		unsigned coord_arg)
+		LLVMValueRef *coords_arg)
 {
 
 	unsigned target = emit_data->inst->Texture.Texture;
@@ -542,11 +542,13 @@ void radeon_llvm_emit_prepare_cube_coords(
 	LLVMValueRef coords[4];
 	LLVMValueRef mad_args[3];
 	LLVMValueRef idx;
+	struct LLVMOpaqueValue *cube_vec;
+	LLVMValueRef v;
 	unsigned i;
 
-	LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
+	cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4);
-			LLVMVectorType(type, 4),
+	v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4),
-			&emit_data->args[coord_arg], 1, LLVMReadNoneAttribute);
+                            &cube_vec, 1, LLVMReadNoneAttribute);
 
 	for (i = 0; i < 4; ++i) {
 		idx = lp_build_const_int32(gallivm, i);
@@ -579,18 +581,14 @@ void radeon_llvm_emit_prepare_cube_coords(
 	if (target != TGSI_TEXTURE_CUBE ||
 		opcode != TGSI_OPCODE_TEX) {
 
-		/* load source coord.w component - array_index for cube arrays or
-		 * compare value for SHADOWCUBE */
-		idx = lp_build_const_int32(gallivm, 3);
-		coords[3] = LLVMBuildExtractElement(builder,
-				emit_data->args[coord_arg], idx, "");
-
 		/* for cube arrays coord.z = coord.w(array_index) * 8 + face */
 		if (target == TGSI_TEXTURE_CUBE_ARRAY ||
 			target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 
+			/* coords_arg.w component - array_index for cube arrays or
+			 * compare value for SHADOWCUBE */
 			coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
-					coords[3], lp_build_const_float(gallivm, 8.0), coords[2]);
+					coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]);
 		}
 
 		/* for instructions that need additional src (compare/lod/bias),
@@ -598,12 +596,11 @@ void radeon_llvm_emit_prepare_cube_coords(
 		if (opcode == TGSI_OPCODE_TEX2 ||
 			opcode == TGSI_OPCODE_TXB2 ||
 			opcode == TGSI_OPCODE_TXL2) {
-			coords[3] = emit_data->args[coord_arg + 1];
+			coords[3] = coords_arg[4];
 		}
 	}
 
-	emit_data->args[coord_arg] =
+	memcpy(coords_arg, coords, sizeof(coords));
-			lp_build_gather_values(bld_base->base.gallivm, coords, 4);
 }
 
 static void txd_fetch_args(
@@ -645,9 +642,6 @@ static void txp_fetch_args(
 					TGSI_OPCODE_DIV, arg, src_w);
 	}
 	coords[3] = bld_base->base.one;
-	emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
-						coords, 4);
-	emit_data->arg_count = 1;
 
 	if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
 	     inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
@@ -655,8 +649,12 @@ static void txp_fetch_args(
 	     inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
 	    inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
 	    inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
-		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
+		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
 	}
+
+	emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
+						coords, 4);
+	emit_data->arg_count = 1;
 }
 
 static void tex_fetch_args(
@@ -673,17 +671,12 @@ static void tex_fetch_args(
 
 	const struct tgsi_full_instruction * inst = emit_data->inst;
 
-	LLVMValueRef coords[4];
+	LLVMValueRef coords[5];
 	unsigned chan;
 	for (chan = 0; chan < 4; chan++) {
 		coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
 	}
 
-	emit_data->arg_count = 1;
-	emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
-						coords, 4);
-	emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
-
 	if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
 		inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
 		inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
@@ -692,7 +685,7 @@ static void tex_fetch_args(
 		 * That operand should be passed as a float value in the args array
 		 * right after the coord vector. After packing it's not used anymore,
 		 * that's why arg_count is not increased */
-		emit_data->args[1] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+		coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0);
 	}
 
 	if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
@@ -701,8 +694,13 @@ static void tex_fetch_args(
 	     inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
 	    inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
 	    inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
-		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, 0);
+		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
 	}
+
+	emit_data->arg_count = 1;
+	emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
+						coords, 4);
+	emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 }
 
 static void txf_fetch_args(
@@ -768,6 +766,22 @@ static void emit_icmp(
 	emit_data->output[emit_data->chan] = v;
 }
 
+static void emit_ucmp(
+		const struct lp_build_tgsi_action * action,
+		struct lp_build_tgsi_context * bld_base,
+		struct lp_build_emit_data * emit_data)
+{
+	unsigned pred;
+	LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+	LLVMContextRef context = bld_base->base.gallivm->context;
+
+
+	LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
+			emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), "");
+
+	emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], "");
+}
+
 static void emit_cmp(
 		const struct lp_build_tgsi_action *action,
 		struct lp_build_tgsi_context * bld_base,
@@ -1112,7 +1126,9 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 	/* XXX: We need to revisit this.I think the correct way to do this is
 	 * to use length = 4 here and use the elem_bld for everything. */
 	type.floating = TRUE;
+	type.fixed = FALSE;
 	type.sign = TRUE;
+	type.norm = FALSE;
 	type.width = 32;
 	type.length = 1;
 
@@ -1243,6 +1259,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 	bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
 	bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
 	bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
+	bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
 
 	bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
 	bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";

src/gallium/drivers/radeonsi/r600_blit.c

@@ -98,21 +98,6 @@ static void r600_blitter_end(struct pipe_context *ctx)
 	r600_context_queries_resume(rctx);
 }
 
-static unsigned u_max_layer(struct pipe_resource *r, unsigned level)
-{
-	switch (r->target) {
-	case PIPE_TEXTURE_CUBE:
-		return 6 - 1;
-	case PIPE_TEXTURE_3D:
-		return u_minify(r->depth0, level) - 1;
-	case PIPE_TEXTURE_1D_ARRAY:
-	case PIPE_TEXTURE_2D_ARRAY:
-		return r->array_size - 1;
-	default:
-		return 0;
-	}
-}
-
 void si_blit_uncompress_depth(struct pipe_context *ctx,
 		struct r600_resource_texture *texture,
 		struct r600_resource_texture *staging,
@@ -432,12 +417,30 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 			r600_change_format(dst, dst_level, &orig_info[1],
 					   PIPE_FORMAT_R8_UNORM);
 			break;
+		case 2:
+			r600_change_format(src, src_level, &orig_info[0],
+					   PIPE_FORMAT_R8G8_UNORM);
+			r600_change_format(dst, dst_level, &orig_info[1],
+					   PIPE_FORMAT_R8G8_UNORM);
+			break;
 		case 4:
 			r600_change_format(src, src_level, &orig_info[0],
 					   PIPE_FORMAT_R8G8B8A8_UNORM);
 			r600_change_format(dst, dst_level, &orig_info[1],
 					   PIPE_FORMAT_R8G8B8A8_UNORM);
 			break;
+		case 8:
+			r600_change_format(src, src_level, &orig_info[0],
+					   PIPE_FORMAT_R16G16B16A16_UINT);
+			r600_change_format(dst, dst_level, &orig_info[1],
+					   PIPE_FORMAT_R16G16B16A16_UINT);
+			break;
+		case 16:
+			r600_change_format(src, src_level, &orig_info[0],
+					   PIPE_FORMAT_R32G32B32A32_UINT);
+			r600_change_format(dst, dst_level, &orig_info[1],
+					   PIPE_FORMAT_R32G32B32A32_UINT);
+			break;
 		default:
 			fprintf(stderr, "Unhandled format %s with blocksize %u\n",
 				util_format_short_name(src->format), blocksize);

src/gallium/drivers/radeonsi/r600_texture.c

@@ -55,11 +55,8 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
 	struct pipe_resource *texture = transfer->resource;
 	struct pipe_box sbox;
 
-	sbox.x = sbox.y = sbox.z = 0;
+	u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
-	sbox.width = transfer->box.width;
+
-	sbox.height = transfer->box.height;
-	/* XXX that might be wrong */
-	sbox.depth = 1;
 	ctx->resource_copy_region(ctx, texture, transfer->level,
 				  transfer->box.x, transfer->box.y, transfer->box.z,
 				  rtransfer->staging,
@@ -153,8 +150,7 @@ static int r600_init_surface(struct r600_screen *rscreen,
 		surface->flags |= RADEON_SURF_SCANOUT;
 	}
 
-	if ((ptex->bind & PIPE_BIND_DEPTH_STENCIL) &&
+	if (!is_flushed_depth && is_depth) {
-	    !is_flushed_depth && is_depth) {
 		surface->flags |= RADEON_SURF_ZBUFFER;
 
 		if (is_stencil) {
@@ -239,7 +235,6 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-	struct pipe_resource resource;
 	struct r600_transfer *trans;
 	boolean use_staging_texture = FALSE;
 	struct radeon_winsys_cs_handle *buf;
@@ -299,42 +294,52 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
 					 level, level,
 					 box->z, box->z + box->depth - 1);
 		trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+		trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
 		trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
 
 		trans->staging = &staging_depth->resource.b.b;
 	} else if (use_staging_texture) {
-		resource.target = PIPE_TEXTURE_2D;
+		struct pipe_resource resource;
+		struct r600_resource_texture *staging;
+
+		memset(&resource, 0, sizeof(resource));
 		resource.format = texture->format;
 		resource.width0 = box->width;
 		resource.height0 = box->height;
 		resource.depth0 = 1;
 		resource.array_size = 1;
-		resource.last_level = 0;
-		resource.nr_samples = 0;
 		resource.usage = PIPE_USAGE_STAGING;
-		resource.bind = 0;
 		resource.flags = R600_RESOURCE_FLAG_TRANSFER;
-		/* For texture reading, the temporary (detiled) texture is used as
+
-		 * a render target when blitting from a tiled texture. */
+		/* We must set the correct texture target and dimensions if needed for a 3D transfer. */
-		if (usage & PIPE_TRANSFER_READ) {
+		if (box->depth > 1 && u_max_layer(texture, level) > 0)
-			resource.bind |= PIPE_BIND_RENDER_TARGET;
+			resource.target = texture->target;
-		}
+		else
-		/* For texture writing, the temporary texture is used as a sampler
+			resource.target = PIPE_TEXTURE_2D;
-		 * when blitting into a tiled texture. */
+
-		if (usage & PIPE_TRANSFER_WRITE) {
+		switch (resource.target) {
-			resource.bind |= PIPE_BIND_SAMPLER_VIEW;
+		case PIPE_TEXTURE_1D_ARRAY:
+		case PIPE_TEXTURE_2D_ARRAY:
+		case PIPE_TEXTURE_CUBE_ARRAY:
+			resource.array_size = box->depth;
+			break;
+		case PIPE_TEXTURE_3D:
+			resource.depth0 = box->depth;
+			break;
+		default:;
 		}
 		/* Create the temporary texture. */
-		trans->staging = ctx->screen->resource_create(ctx->screen, &resource);
+		staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource);
-		if (trans->staging == NULL) {
+		if (staging == NULL) {
 			R600_ERR("failed to create temporary texture to hold untiled copy\n");
 			pipe_resource_reference(&trans->transfer.resource, NULL);
 			FREE(trans);
 			return NULL;
 		}
 
-		trans->transfer.stride = ((struct r600_resource_texture *)trans->staging)
+		trans->staging = &staging->resource.b.b;
-					->surface.level[0].pitch_bytes;
+		trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+		trans->transfer.layer_stride = staging->surface.level[0].slice_size;
 		if (usage & PIPE_TRANSFER_READ) {
 			r600_copy_to_staging_texture(ctx, trans);
 			/* Always referenced in the blit. */
@@ -349,7 +354,7 @@ static void *si_texture_transfer_map(struct pipe_context *ctx,
 	if (trans->staging) {
 		buf = si_resource(trans->staging)->cs_buf;
 	} else {
-		buf = si_resource(trans->transfer.resource)->cs_buf;
+		buf = rtex->resource.cs_buf;
 	}
 
 	if (rtex->is_depth || !trans->staging)
@@ -549,6 +554,8 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 	unsigned level = surf_tmpl->u.tex.level;
 
+	assert(surf_tmpl->u.tex.first_layer <= u_max_layer(texture, surf_tmpl->u.tex.level));
+	assert(surf_tmpl->u.tex.last_layer <= u_max_layer(texture, surf_tmpl->u.tex.level));
 	assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 	if (surface == NULL)
 		return NULL;