This arg size should be 1 instead of 3. It does not affect functionality
because we does not enable it in SPI_PS_INPUT_ADDR. But it does affect
the VGPR number that LLVM produce when LLVM still count with all PS
function arguments.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
(cherry picked from commit 6f9f350622)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13053>
With NGG culling, the shaders are split into two parts:
the top part that computes just the position output,
and the bottom part which produces the other outputs.
To reduce redundancy between the two, I added some code
to reuse uniform variables between them. However, there is
an edge case I didn't think about: because of vertex repacking,
it is possible for the bottom part to process a different vertex.
Therefore it can take a different divergent code path
(though it must still take the same uniform code path).
Due to this, when a uniform value comes from divergent control
flow, this may be undefined in the bottom part.
This commit stops reusing uniform variables from
divergent control flow, to fix issues that arise from this.
Fossil DB stats on Sienna Cichlid with NGGC on:
Totals from 1723 (1.34% of 128647) affected shaders:
VGPRs: 89312 -> 89184 (-0.14%); split: -0.15%, +0.01%
SpillSGPRs: 4575 -> 120 (-97.38%)
CodeSize: 10846424 -> 10873836 (+0.25%); split: -0.68%, +0.93%
MaxWaves: 34582 -> 34602 (+0.06%); split: +0.06%, -0.01%
Instrs: 2124471 -> 2128835 (+0.21%); split: -0.51%, +0.72%
Latency: 7274569 -> 7293899 (+0.27%); split: -0.22%, +0.48%
InvThroughput: 1637130 -> 1635490 (-0.10%); split: -0.17%, +0.07%
VClause: 25141 -> 25414 (+1.09%); split: -0.02%, +1.10%
SClause: 56367 -> 59503 (+5.56%); split: -1.36%, +6.93%
Copies: 230704 -> 219313 (-4.94%); split: -5.49%, +0.55%
Branches: 72781 -> 72681 (-0.14%); split: -0.21%, +0.07%
PreSGPRs: 118766 -> 100176 (-15.65%); split: -15.70%, +0.05%
PreVGPRs: 76876 -> 76833 (-0.06%)
Fixes: 0bb543bb60
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13001>
(cherry picked from commit 09f89d15e4)
Use create_backed_surface_view helper function to create/reuse
alternate surface view when the to-be-bound surface view was created
in a different context. This fixes render target views leak running gazebo.
Cc: mesa-stable
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12952>
(cherry picked from commit e5dc900226)
These are I/O variables which are not going to be removed anyway.
However, get_variable_io_mask handles their location incorrectly.
Found using the GCC undefined behavior sanitizer.
Fixes the following error:
runtime error:
shift exponent 4294967258 is too large
for 64-bit type 'long unsigned int'
Closes: #5319
Fixes: cf5f8f55c3
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
(cherry picked from commit 872d21820f)
match_mask checks the intrinsic type and decides whether it's
per-patch or not. VS don't have per-patch outputs,
so this causes wrong behaviour there.
Found using the GCC undefined behavior sanitizer.
Fixes the following error:
runtime error:
shift exponent 18446744073709551584 is too large
for 64-bit type 'long unsigned int'
Closes: #5319
Fixes: bf966d1c1d
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
(cherry picked from commit 13e467a147)
Commit 0245b825 switched from returning the error code VK_ERROR_OUT_OF_DATE_KHR
to returning the success code VK_SUBOPTIMAL_KHR. Prior to that commit, the error
code caused all code paths to fail immediately, but the success code does not.
Currently the success code is not recorded in some scenarios, resulting in a
result of VK_SUCCESS instead. This breaks applications that rely on the
result (per the spec) to trigger resizes.
This commit ensures that the proper VK_SUBOPTIMAL_KHR success code is set as a
sticky status (as comments indicate was intended), ensuring that it is
propagated to user code.
Fixes#5331
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12782>
(cherry picked from commit fc5ea6a054)
The fd_fence_finish() may be passed a special timeout value PIPE_TIMEOUT_INFINITE.
This gets propagated all the way to get_abs_timeout(), where it gets converted to
a huge timeout value and passed down to the kernel. At least on iMX53, the kernel
may complain about this value being too large and emit a backtrace. The relevant
piece of information there is the following:
schedule_timeout: wrong timeout value bf94984b
Per suggestion by Rob Clark, fix this in get_abs_timeout() by picking the same
rollover implementation present in etnaviv. This fixes one part of the problem
where the tv_nsec becomes larger than NSEC_PER_SEC, which is invalid.
However, the PIPE_TIMEOUT_INFINITE is sufficiently large to make tv_secs larger
than KTIME_SEC_MAX, which makes kernel-side ktime_set() return KTIME_MAX and
that in turn triggers the above "wrong timeout value N" message. Fix this by
setting the timeout to large enough value in case of PIPE_TIMEOUT_INFINITE.
While the timeout is not truly infinite, the timeout is long enough as anything
longer than a few seconds means the GPU got hung.
The "util/timespec.h" is added so we can use NSEC_PER_SEC instead of ad-hoc
constant 1000000000 . The "pipe/p_defines.h" is needed for PIPE_TIMEOUT_INFINITE.
This problem can be reliably triggered on iMX53 using Qt5 with EGLFS support,
using the qtbase examples, as follows:
/usr/share/examples/opengl/qopenglwidget/qopenglwidget -platform eglfs
Fixes: f3cc0d2747 ("freedreno: import libdrm_freedreno + redesign submit")
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12886>
(cherry picked from commit 6da2727174)
As we don't know if we are going to have spilling or not, emit always a
last thrsw at the end of the shader.
If later we don't have spillings and we don't need that last thrsw, we
remove it and switch back to the previous one.
This way we ensure all the spilling happens always before the last
thrsw.
v2 (Juan):
- Rework the code to force a last thrsw and remove later if no spilling
v3:
- Merge functionality inside vir_emit_last_thrsw (Iago)
- Add vir_restore_last_thrsw (Juan)
v4 (Iago):
- Fix/add new comments
- Rename variables/parameters
v5 (Iago):
- Fix comments
- Add assertion
Cc: mesa-stable
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4760
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12322>
(cherry picked from commit c98ddc778a)
Conflicts:
src/broadcom/compiler/nir_to_vir.c
This estimation was incorrect, the number of waves doesn't only
depend of the number of VGPRs.
Though, {SPI,COMPUTE}_TMPRING_SIZE.WAVES should limit the number of
scratch waves in flight, not sure if limiting it really works.
This fixes a GPU hang with an upcoming game, and this might also
helps resolving some spurious random GPU hangs.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12700>
(cherry picked from commit b31994cf67)
Conflicts:
src/amd/vulkan/radv_shader.c
In this case std::array doesn't behave like a regular array, therefore
it is NOT okay to index it outside the array, even though std::fill
needs us to do so.
Change the syntax to do the same thing slightly differently,
and add an assertion to make sure the registers are always within
the array's bounds.
Closes: #5289
Fixes: 0e4747d3fb
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12664>
(cherry picked from commit 9d20cf2732)
Conflicts:
src/amd/compiler/aco_optimizer_postRA.cpp
At some point I split up the flags into overall/source flags and made
copies from immed/const only set IR3_REG_IMMED/IR3_REG_CONST on the
source flags, but I forgot to update this. Noticed by inspection.
Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12747>
(cherry picked from commit e7f8d283d7)
Without this, lowered saturating ALU instructions would only clamp to
the range of the new type instead of the range of the old type.
v2: Use nir_iclamp. Suggested by Jason. Use new
u_{int,uint}N_{min,max}() helpers.
Fixes: 090e282407 ("nir: Add a saturated unsigned integer add opcode")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
(cherry picked from commit 7d8bf7c167)
Many places need to know the maximum or minimum possible value for a
given size integer... so everyone just open-codes their favorite
version. There is some potential to hit either undefined or
implementation-defined behavior, so having one version that Just Works
seems beneficial.
v2: Fix copy-and-pasted bug (INT64_MAX instead of INT64_MIN) in
u_intmin. Noticed by CI. Lol. Rename functions
`s/u_(uint|int)(min|max)/u_\1N_\2/g`. Suggested by Jason. Add some
unit tests that would have caught the copy-and-paste bug before wasting
CI time. Change the implementation of u_intN_min to use the same
pattern as stdint.h. This avoids the integer division. Noticed by
Jason.
v3: Add changes to convert_clear_color
(src/gallium/drivers/iris/iris_clear.c). Suggested by Nanley.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
(cherry picked from commit 72259a870f)
According to OES_EGL_image_external_essl3:
On p. 196 in the errors section for BindImageTexture, replace the
last error with the following:
"An INVALID_OPERATION error is generated if <texture> is neither the
name of an immutable texture object, nor the name of an external
texture object."
According to OES_EGL_image_external:
The command
void EGLImageTargetTexture2DOES(enum target, eglImageOES image);
with <target> set to TEXTURE_EXTERNAL_OES defines the currently bound
external texture object to be a target sibling of <image>.
...
If <target> is not TEXTURE_EXTERNAL_OES, the error INVALID_ENUM is
generated. (Note: if GL_OES_EGL_image is supported then <target> may
also be TEXTURE_2D).
Currently, mesa only allows GL_TEXTURE_EXTERNAL_OES textures to be bound
by glBindImageTexture. However, the language of the specification does not
appear to use "external" to refer to GL_TEXTURE_EXTERNAL_OES specifically,
since OES_EGL_image_external allows external eglImageOES to be attached
to GL_TEXTURE_2D in the presence of GL_OES_EGL_image. Thus, it should be
interpreted to refer to all types of external textures, including 2D
textures attached via glEGLImageTargetTexture2DOES.
Fixes: ed43dd62ac ("main: allow external textures for BindImageTexture")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12383>
(cherry picked from commit e52aa1edff)
The lowered LS and NGG stages use local_invocation_index and they
can benefit from the unsigned upper bound because they can emit a
less expensive integer multiplication instruction.
This was working in the past, but accidentally borked by a refactor.
Fossil DB changes on Sienna Cichlid:
Totals from 956 (0.74% of 128647) affected shaders:
CodeSize: 2354172 -> 2344712 (-0.40%)
Instrs: 434359 -> 434327 (-0.01%)
Latency: 1883949 -> 1876814 (-0.38%)
InvThroughput: 762638 -> 757405 (-0.69%)
Fossil DB changes on Sienna Cichlid (with NGGC enabled):
Totals from 57873 (44.99% of 128647) affected shaders:
CodeSize: 155844192 -> 155607064 (-0.15%)
Instrs: 29799184 -> 29799152 (-0.00%)
Latency: 130959764 -> 130814224 (-0.11%); split: -0.11%, +0.00%
InvThroughput: 21100300 -> 20928635 (-0.81%); split: -0.81%, +0.00%
Fixes: 8af6766062
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>
(cherry picked from commit 548b383310)
Consider the following sequence in a shader:
b = p_extract a
c = v_mad_u32_u16 b, X, 0
The optimizer applies extract, resulting in:
c = v_mad_u32_u16 a, X, 0 (correct)
Then it mistakenly turns that into:
c = v_mul_u32_u24 a, X, 0 (incorrect)
In this case, the p_extract is applied to v_mad_u32_u16 by
apply_extract. After this, we can no longer be sure that
the operands are still 16 or 24-bit, so we have to remove
this flag.
No Fossil DB changes.
Fixes: 54292e99c7
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>
(cherry picked from commit 76b9dd6266)
We can't append instructions following a return/halt instruction
because the control flow helpers will modify the successor of the
block containing the return/halt. And the NIR validator enforces that
the return/halt must have the end of the function as successor.
This tends to happen following lower_shader_calls lowering which
inserts halts. This probably doesn't prevent the optimization, it'll
just happen in one of the return shaders after the halt has been
removed.
v2: Move prev block ending check earlier in the function (Daniel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12506>
(cherry picked from commit a13e79843e)
The hardware can handle much larger textures than we allowed. The game
"Cathedral" requires larger textures for some bizarre reason. Raise the
limit so the game runs, syncing MAX_MIP_LEVELS, the comments, and the CAPs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #5203
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12312>
(cherry picked from commit d051b06a48)
This ensures each context can have a separate batch writing a resource
and we don't race trying to flush each other's batches. Unfortunately
the extra hash table operations regress draw-overhead numbers by about
8% but I'd rather eat the overhead and have an obviously correct
implementation than leave known buggy code in tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
(cherry picked from commit 8503cab2e0)
Conflicts:
src/gallium/drivers/panfrost/pan_job.c
This expresses the semantic of the flush only applying to batches within
the context, not globally, in line with OpenGL's multithreading rules.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
(cherry picked from commit e98aa55413)
Conflicts:
src/gallium/drivers/panfrost/pan_job.c
ralloc is not thread safe, so we cannot use a pipe_screen as a ralloc
context unless we lock the screen. The allocation patterns for resources
are trivial, so just use malloc/calloc/free directly instead of ralloc.
This fixes a segfault in:
dEQP-EGL.functional.sharing.gles2.multithread.random.images.copytexsubimage2d.1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12525>
(cherry picked from commit e6924be737)
Without a lock, two threads may bind the same shader CSO simultaneously,
allocate the same variant simultaneously, and then race each other in
the compiler. This manifests in various ways, most commonly failing the
assertion that UBO pushing has only run once. The simple_mtx_t solution
is used in Iris. Fixes the crash in:
dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.bufferdata_render
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12525>
(cherry picked from commit 40edc87956)
The current code overwrote the original view which meant if we
had to reemit a surface the second emit would be wrong.
This fixes cubemaps on gm45 and maybe some issues with 3D textures
elsewhere.
Fixes: f3630548f1 ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12514>
(cherry picked from commit 63138c42c5)
Conflicts:
src/gallium/drivers/crocus/crocus_state.c
If a user attempts to run Panfrost on an unsupported GPU (e.g. Mali
T604), Panfrost will refuse to load and will destroy the screen
immediately, allowing for a graceful fallback to a software rasterizer.
However, the screen destroy code calls a screen_destroy function in the
GenXML vtbl -- and this function is still NULL when the allowlist is
checked. This manifests as crashes on unsuported GPUs.
Issue tracked down with Icecream95's mad Ghidra skills.
Closes: #5269
Fixes: 88dc4db6be ("panfrost: Init/destroy blitter from per-gen file")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12512>
(cherry picked from commit 2d31d469f7)
Fixes an invalid read caught by valgrind when there is a hole in the
valid render target mask:
==6749== Conditional jump or move depends on uninitialised value(s)
==6749== at 0x5E88EC0: panfrost_prepare_fs_state (pan_cmdstream.c:417)
==6749== by 0x5E88EC0: panfrost_emit_frag_shader (pan_cmdstream.c:501)
==6749== by 0x5E88EC0: panfrost_emit_frag_shader_meta (pan_cmdstream.c:573)
==6749== by 0x5E88EC0: panfrost_update_state_fs (pan_cmdstream.c:2593)
==6749== by 0x5E8B0BF: panfrost_direct_draw (pan_cmdstream.c:2839)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes: a124c47b9f ("panfrost: Fix NULL derefs in pan_cmdstream.c")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11383>
(cherry picked from commit 3113dbd837)
Otherwise we end up accessing overwritten registers. Fixes
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_enable_buffer_enable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11383>
(cherry picked from commit f45ceb8182)
This seems to have fixed a few additional tests on 21.2:
- dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.const_expression_fragment
- dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_separate_blend_func_buffer_separate_blend_func
- dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_blend_func_buffer_separate_blend_func
Fixes framebuffer_fetch and blend_equation_advanced dEQP tests on v6.
v2: Use clause dependencies rather than comparing the message type
v3: Shift the BIFROST_SLOT_* constants before using them as a mask
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12375>
(cherry picked from commit 295807e666)
Apparently, CLPER_V7 is missing from Mali G31, but CLPER_V6 works. Fixes
INSTR_INVALID_ENC faults and failures in
dEQP-GLES3.functional.shaders.derivate.* on Dvalin.
Technically not an errata but an implementation difference. I suspect
Mali G51 will need this as well, should we ever allowlist it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
(cherry picked from commit 61c8e39649)
Conflicts:
src/panfrost/bifrost/bi_quirks.h
Use the explicit sample mode and set the sample ID in the pixel indices
structure to the current sample ID. This fixes tilebuffer loads in blend
shaders on multisampled framebuffers.
Make sure the new routine is broken out to a helper for use with ST_TILE
in the next commit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
(cherry picked from commit 16394dc71a)
Although it is passing all of dEQP-GLES31, it is failing a few
KHR-GLES31.* tests. It also has performance issues at the moment. Invert
the existing noindirect debug flag to become a indirect debug flag. Set
this flag for dEQP-GLES31 CI on G52, to make sure the code doesn't bit
rot on the hope someone will pick this up later on.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
(cherry picked from commit a7f7d74137)
Conflicts:
src/gallium/drivers/panfrost/pan_screen.c
src/panfrost/lib/pan_util.h
In b9c095cc2c ("panfrost: Rewrite the clear colour packing code"),
packing of clear colours was corrected to use the tilebuffer's
fractional bits, fixing dithering of the clear colour with formats like
RGB565. Unfortunately, that commit did so unconditionally. If the
framebuffer is dithered, but dithering is disabled at the time of
the clear, we would incorrectly dither the clear.
This is a regression, as the old (broken) code passed the relevant CTS
test. What's the catch? Depending on dither state, there are two
formulas to pack tilebuffer colours. We need to handle both. Fixes
KHR-GLES31.core.draw_buffers_indexed.color_masks.
Fixes: b9c095cc2c ("panfrost: Rewrite the clear colour packing code")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12460>
(cherry picked from commit 22538b89b3)
Conflicts:
src/panfrost/lib/tests/test-clear.c
src/panfrost/vulkan/panvk_cmd_buffer.c
We have no reason to report a subpixel precision of 4 for lines; in fact
LLVMpipe uses 8 subpixel bits for lines, similar to other primitives.
But let's use the pipe-cap for this instead of hard-coding it.
Fixes: 9fbf6b2abf ("lavapipe: implement VK_EXT_line_rasterization")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12277>
(cherry picked from commit a16f3963d3)
Commit 3a772be026 ("freedreno: Add perfetto renderpass support")
uses C++17 init-statement feature.
GCC
../src/gallium/drivers/freedreno/freedreno_perfetto.cc: In lambda function:
../src/gallium/drivers/freedreno/freedreno_perfetto.cc:148:11: warning: init-statement in selection statements only available with ‘-std=c++17’ or ‘-std=gnu++17’
148 | if (auto state = tctx.GetIncrementalState(); state->was_cleared) {
| ^~~~
Clang
../src/gallium/drivers/freedreno/freedreno_perfetto.cc:148:11: warning: 'if' initialization statements are a C++17 extension [-Wc++17-extensions]
if (auto state = tctx.GetIncrementalState(); state->was_cleared) {
^
Intel C++ Compiler
../src/gallium/drivers/freedreno/freedreno_perfetto.cc(148): error: expected a ")"
if (auto state = tctx.GetIncrementalState(); state->was_cleared) {
^
Fixes: 3a772be026 ("freedreno: Add perfetto renderpass support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5193
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12293>
(cherry picked from commit 4fc2a6cbdb)
With hw devices, when you submit a present, implicit sync will
make sure the work submitted to the gpu on the client will end
up happening before the present work submitted on the server.
However with sw paths there is no real GPU, the lavapipe fake
GPU thread is client side only and presenting is done directly
from the pixmap (or later shared pixmap). In order for this to
make sense the wsi common code should wait for the fence on the
image before queueing the submit to the server so that all
client works has been flushed to the pixmap before the copy or
present operation is submitted.
Fixes: 8004fa9c95 ("vulkan/wsi: add sw support. (v2)")
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12502>
(cherry picked from commit 0cddfba328)
It can happen that we create an enormous merge set, even larger than the
entire register file, in which case find_best_gap() would loop
infinitely. This seems to be triggered more often with
IR3_SHADER_DEBUG=spillall, since it actually happened with a CTS test.
Just bail out in that case.
Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
(cherry picked from commit efb34d6ee6)
When we mark live-through sources that are merged with the destination
as killed, we kept the bitsets in sync, but we forgot to keep them in
sync when unmarking them after allocating the destination. The result
was that "available" wasn't correct for any instruction afterwards. This
resulted in a bad register allocation with IR3_SHADER_DEBUG=spillall for
a dEQP-VK test.
While we're changing this, use ra_foreach_src().
Fixes: 0ffcb19b9d ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>
(cherry picked from commit 70c22d3894)
Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.
Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.
A tiny helper function is introduced to compute the modifier of a
resource.
Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 7bcb223639 ("v3d, vc4: Fix dmabuf import for non-scanout buffers")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>
(cherry picked from commit 8de086e12f)
Conflicts:
src/broadcom/ci/piglit-v3d-rpi4-fails.txt
Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.
Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.
A tiny helper function is introduced to compute the modifier of a
resource.
Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 7bcb223639 ("v3d, vc4: Fix dmabuf import for non-scanout buffers")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>
(cherry picked from commit b1fbceac6f)
Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.
Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.
Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 4c092947df ("panfrost: fail in get_handle(TYPE_KMS) without a scanout resource")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>
(cherry picked from commit 99fc6f7271)
When this was rewritten to support Vulkan, we stopped initializing
file_max to -1 in the case of no inputs. This causes the draw module
to go down a needlessly pessimistic case, printing an error while we're
at it.
Fixes: 42b5cfdbd2 ("gallivm/nir: fix vulkan vertex inputs")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12440>
(cherry picked from commit 63529782d3)
16bit integer support also implies using 16-bit results when sampling
textures.
Because we're returning the results in float SSA values instead of int,
we need to bitcast back to integers before truncating the values.
Fixes: 00ff60f799 ("gallivm: add 16-bit integer support")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12413>
(cherry picked from commit 45a61f1782)
Currently stride, offset, modifier is obtained by invoking
lima_resource_get_handle() with WINSYS_HANDLE_TYPE_KMS.
Before commit 47f000c170 this path was working. Obtained handle
was simply ignored by DRI frontend and only requested data used.
After commit 47f000c170 such requests started to fail when
DRI is initialized using KMSRO and resource has no scanout data.
When lima_resource_get_param() is implemented, it will be used in
a first place to obtain resource data.
Fixes: 47f000c170 ("lima: fail in get_handle(TYPE_KMS) without a scanout resource")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12362>
(cherry picked from commit 5ec6b6e9bb)
When operators other than eq and ne are involved we can't really
move operands around and negate them because such transformation
may change the value of the whole expression.
Some examples:
For unsigned var:
0 >= 1u + var would eventually become 0xffffffff >= var,
which would always evaluate to true, when original expression
was true only for var == 0xffffffff.
For signed var:
0 >= 1 + var would become -1 >= var, which would evaluate to
false for var == 2147483647, when original expression evaluated
to true (because signed overflow is defined to wrap around in
glsl, 1 + 2147483647 == -2147483648, so 0 >= -2147483648).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5226
Fixes: 34ec1a24d6 ("glsl: Optimize (x + y cmp 0) into (x cmp -y).")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12359>
(cherry picked from commit 89bc8ff408)
At the beginning of a render pass, the hardware will fill the tilebuffer
with an arbitrary 128-bit word. To implement colour clears, the driver
must pack the API-specific clear colour according to the 128-bit layout
of the tilebuffer. This layout depends only on the render target format.
The existing code to handle this was based on loose guesswork. It works
for the format / clear colour combinations tested in dEQP-GLES3, but it
is severely deficient in the general case. It works by matching on the
PIPE format of the render target (not the layout of the tilebuffer). For
special cased PIPE formats, it open codes a buggy pack routine.
Otherwise, it defaults to util_pack_color in the hope that will work.
Since util_pack_color doesn't know anything about Mali tilebuffer
layouts, that means it's defaulting to wrong behaviour.
Now that we understand internal tilebuffer layouts, let's rewrite the
packing code. Instead of matching PIPE formats, map the PIPE format to
the internal tilebuffer layout using the common table, ensuring the
mapping remains in sync with the render target descriptor. Then for
blendable tilebuffer formats, pack using a common float -> fixed point
path supporting optional sRGB translation. Raw formats use
util_pack_color as before.
For formats with less than 8 bits per channel, the new code uses the
fractional bits of the fixed-point representation. This is required for
correct dithering if the clear colour is not exactly representable in
the final low precision format.
In summary, at least the following bugs in the old code are fixed:
* Swapped R/B channels with sRGB
* Swapped R/B channels with some missing formats
* Incorrect dithering with RGB565, RGB5_A1
Fixes the following test cases:
dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb
dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb
dEQP-EGL.functional.wide_color.window_888_colorspace_srgb
dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb
Later in the series, unit tests are added for the new implementation.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12365>
(cherry picked from commit b9c095cc2c)
Conflicts:
src/panfrost/lib/pan_util.h
Transfer ownership of the render node fd to the panfrost_device (minor
change to panvk), and then close the file descriptor for the render node
bound to the panfrost_device when destroying the panfrost_device. Of all
the users of panfrost_open_device, panvk is the only one that correctly
closed the fd before. Accordingly, this fixes an fd leak in the Gallium
driver (and performance counter utilities).
This fix still applies to the Gallium driver when renderonly is in use--
although renderonly closes its own fd, the fd is _duplicated_ in
panfrost_drm_winsys.c, so renderonly and panfrost must _both_ close
their respective fd to fix the leak.
This fixes a crash when running dEQP-EGL for more than two hours.
dEQP-EGL creates a new screen for every test case and then immediately
destroys it. If destroying a screen leaks the fd, this causes the number
of open file descriptors to increase monotonically until the process
ends. This will eventually hit the system limit for number of open files
and abort the process.
This bug was identified while attempting to run the OpenGL ES
conformance tests via cts-runner, and then confirmed with `lsof`. With
the fix, the number of file descriptors reported by `lsof | wc -l` is
now constant while running dEQP-EGL as expected.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12346>
(cherry picked from commit 76377de99b)
mmap requires its offset is page aligned, but the current code only
guarantees 4k alignment, causing drm-shim to break badly on kernels with
>4k page sizes. This fixes drm-shim on my Apple M1, running bare metal
Linux with 16k pages. It probably also fixes exotic PowerPC systems with
64k pages.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Zoltan Boszormenyi <zboszor@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12347>
(cherry picked from commit 38f39cc1e2)
When creating an image out of a swapchain on Android, the android
layer call will detect a VkBindImageMemorySwapchainInfoKHR in the
pNext chain of the vkBindImageMemory2() call and add a
VkNativeBufferANDROID in the chain. This is what we should use as
backing memory for that image.
v2: Fix a couple of obvious mistakes (Tapani)
v3: Silence build warning (Lionel)
Fix invalid object argument to vk_error() (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: bc3c71b87a ("anv: don't try to access Android swapchains")
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5180
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12244>
(cherry picked from commit 19b7bbba73)
Before a73cb106a6, cso contexts were never reused, but now that they
are we need to be extra careful that the state in the cso context and
in the pipe context matches even after an unbind, since when the cso
context is reused the state might otherwise get out of sync (as there is
no concept of "initial state", basically cso always relied on the default
values being the same both in cso and the drivers).
This fixes some errors we've seen internally with lavapipe.
Fixes: a73cb106a6 ("aux/cso: split cso_destroy_context into unbind and a destroy functions")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12261>
(cherry picked from commit 513fb5438b)
On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
using a separte cmpn and sel instruction. This lowering occurs in
fs_vistor::lower_minmax which is called very, very late... a long, long
time after the first calls to opt_cmod_propagation. As a result,
conditional modifiers can be incorrectly propagated across sel.cond on
those platforms.
No tests were affected by this change, and I find that quite shocking.
After just changing flags_written(), all of the atan tests started
failing on ILK. That required the change in cmod_propagatin (and the
addition of the prop_across_into_sel_gfx5 unit test).
Shader-db results for ILK and GM45 are below. I looked at a couple
before and after shaders... and every case that I looked at had
experienced incorrect cmod propagation. This affected a LOT of apps!
Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2,
Gang Beasts, and on and on... :(
I discovered this bug while working on a couple new optimization
passes. One of the passes attempts to remove condition modifiers that
are never used. The pass made no progress except on ILK and GM45.
After investigating a couple of the affected shaders, I noticed that
the code in those shaders looked wrong... investigation led to this
cause.
v2: Trivial changes in the unit tests.
v3: Fix type in comment in unit tests. Noticed by Jason and Priit.
v4: Tweak handling of BRW_OPCODE_SEL special case. Suggested by Jason.
Fixes: df1aec763e ("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Dave Airlie <airlied@redhat.com>
Iron Lake
total instructions in shared programs: 8180493 -> 8181781 (0.02%)
instructions in affected programs: 541796 -> 543084 (0.24%)
helped: 28
HURT: 1158
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50%
HURT stats (abs) min: 1 max: 3 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23%
95% mean confidence interval for instructions value: 1.06 1.11
95% mean confidence interval for instructions %-change: 0.31% 0.38%
Instructions are HURT.
total cycles in shared programs: 239420470 -> 239421690 (<.01%)
cycles in affected programs: 2925992 -> 2927212 (0.04%)
helped: 49
HURT: 157
helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70
helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96%
HURT stats (abs) min: 2 max: 48 x̄: 27.34 x̃: 24
HURT stats (rel) min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20%
95% mean confidence interval for cycles value: -0.80 12.64
95% mean confidence interval for cycles %-change: -0.31% <.01%
Inconclusive result (value mean confidence interval includes 0).
GM45
total instructions in shared programs: 4985517 -> 4986207 (0.01%)
instructions in affected programs: 306935 -> 307625 (0.22%)
helped: 14
HURT: 625
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49%
HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1
HURT stats (rel) min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.29% 0.36%
Instructions are HURT.
total cycles in shared programs: 153827268 -> 153828052 (<.01%)
cycles in affected programs: 1669290 -> 1670074 (0.05%)
helped: 24
HURT: 84
helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67
helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94%
HURT stats (abs) min: 2 max: 48 x̄: 27.71 x̃: 24
HURT stats (rel) min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14%
95% mean confidence interval for cycles value: -1.94 16.46
95% mean confidence interval for cycles %-change: -0.29% 0.11%
Inconclusive result (value mean confidence interval includes 0).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12191>
(cherry picked from commit 38807ceeae)
Per https://gitlab.freedesktop.org/mesa/mesa/-/issues/5178#note_1019666,
the assumption fundamental to this optimization is false. Section
2.4.1 (Float to Integer) of Ivy Bridge PRMs describes the situation.
The wording of the section is somewhat confusing (because it doesn't
clearly delineate between signed and unsigned integers), but the last
two rows of the table make it clear that F->UD conversion clamps
negative float values to 0.
All other hardware mentioned in that thread seems to behave the same
way.
The real problem is that, with hardware that behaves in this ways,
converting f2u(2147483648.0) to f2i(2147483648.0) changes the bit pattern
that would be produced from 0x80000000 to 0x7fffffff.
This reverts commit ad05920258.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12297>
(cherry picked from commit 84d2e53789)
Otherwise drivers that don't use 16-bit slots for varyings will get
confused and have their driver_locations scribbled over. This has caused
multiple problems for both Panfrost and Asahi this week. Given the only
other user of the pass for varyings is radeonsi, which needs both
together, I think this is the least controversial fix.
Fixes: fb29cef8dd ("nir: add many passes that lower and optimize 16-bit input/outputs and samplers")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11732>
(cherry picked from commit 03c18f7efc)
On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
using a separte cmpn and sel instruction. This lowering occurs in
fs_vistor::lower_minmax which is called very, very late... a long, long
time after the first calls to opt_cmod_propagation. As a result,
conditional modifiers can be incorrectly propagated across sel.cond on
those platforms.
No tests were affected by this change, and I find that quite shocking.
After just changing flags_written(), all of the atan tests started
failing on ILK. That required the change in cmod_propagatin (and the
addition of the prop_across_into_sel_gfx5 unit test).
Shader-db results for ILK and GM45 are below. I looked at a couple
before and after shaders... and every case that I looked at had
experienced incorrect cmod propagation. This affected a LOT of apps!
Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2,
Gang Beasts, and on and on... :(
I discovered this bug while working on a couple new optimization
passes. One of the passes attempts to remove condition modifiers that
are never used. The pass made no progress except on ILK and GM45.
After investigating a couple of the affected shaders, I noticed that
the code in those shaders looked wrong... investigation led to this
cause.
v2: Trivial changes in the unit tests.
v3: Fix type in comment in unit tests. Noticed by Jason and Priit.
v4: Tweak handling of BRW_OPCODE_SEL special case. Suggested by Jason.
Fixes: df1aec763e ("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Dave Airlie <airlied@redhat.com>
Iron Lake
total instructions in shared programs: 8180493 -> 8181781 (0.02%)
instructions in affected programs: 541796 -> 543084 (0.24%)
helped: 28
HURT: 1158
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50%
HURT stats (abs) min: 1 max: 3 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23%
95% mean confidence interval for instructions value: 1.06 1.11
95% mean confidence interval for instructions %-change: 0.31% 0.38%
Instructions are HURT.
total cycles in shared programs: 239420470 -> 239421690 (<.01%)
cycles in affected programs: 2925992 -> 2927212 (0.04%)
helped: 49
HURT: 157
helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70
helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96%
HURT stats (abs) min: 2 max: 48 x̄: 27.34 x̃: 24
HURT stats (rel) min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20%
95% mean confidence interval for cycles value: -0.80 12.64
95% mean confidence interval for cycles %-change: -0.31% <.01%
Inconclusive result (value mean confidence interval includes 0).
GM45
total instructions in shared programs: 4985517 -> 4986207 (0.01%)
instructions in affected programs: 306935 -> 307625 (0.22%)
helped: 14
HURT: 625
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49%
HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1
HURT stats (rel) min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.29% 0.36%
Instructions are HURT.
total cycles in shared programs: 153827268 -> 153828052 (<.01%)
cycles in affected programs: 1669290 -> 1670074 (0.05%)
helped: 24
HURT: 84
helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67
helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94%
HURT stats (abs) min: 2 max: 48 x̄: 27.71 x̃: 24
HURT stats (rel) min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14%
95% mean confidence interval for cycles value: -1.94 16.46
95% mean confidence interval for cycles %-change: -0.29% 0.11%
Inconclusive result (value mean confidence interval includes 0).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12330>
In the compute dispatch path we do not allocate a huge amount
of space to cover everything so the individual functions have to
allocate. This was missing here, causing a hang in Cyberpunk when
accessing the system menu at some locations with thread tracing
enabled.
Fixes: bd1186572f ("radv: add support for push constants inlining when possible")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12271>
(cherry picked from commit 02b6015945)
The flock is per-fd, not per thread, and we do it outside of the main mutex. This was
done to avoid having to wait in the mutex, but we can get a case where one ends up running
the body with the flock unlocked.
Fix this by adding a mutex that doesn't need to be locked for reads.
Fixes: 4f0f8133a3 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12266>
(cherry picked from commit 30a359d633)
Don't anticipate seeing any partial written headers but just in case we
should probably wait on the lock to make sure whatever header was being
written is finished being written.
Fixes: 4f0f8133a3 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>
(cherry picked from commit 96bfefe8d1)
Otherwise, another thread might reuse their object ids for other
objects. For example,
T1: free queue with object id X
T2: reuse id X
T2: emit vkCreateFoo with id X
T1: emit vkDestroyDevice
virglrenderer happily accepts that which leads to double frees of the
queue: once when X is updated to point to another object and once when
vkDestroyDevice is executed. virglrenderer should be fixed to catch
such invalid object id reuse as well.
Fixes
dEQP-VK.api.object_management.multithreaded_shared_resources.device_group.
Fixes: ddd7533055 ("venus: initial support for queue/fence/semaphore")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12252>
(cherry picked from commit da000ea2ef)
When a vertex program is translated to nir, it uses
nir_to_tgsi_compile_options for drivers with only nir-to-tgsi based
NIR support. But this compile option might not be the same as the NIR
compile option from llvmpipe, hence when the nir shader is bound
to the draw module, it hits an assertion in do_alu_action() when
encounters nir_op_fdot3.
With this patch, draw will take the nir-to-tgsi path if preferred IR
from the driver is TGSI.
Fixes assert running Maya on SVGA device.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: 21.2 mesa-stable
(cherry picked from commit 6751d832c5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12200>
Some drivers doesn't support PIPE_SHADER_CAP_INTEGERS.
This leads to using load_ubo_vec4 which throws llvmpipe off the guard since
it doesn't expect load_ubo_vec4 in shader. Use nir_to_tgsi utility in
such a case.
This fixes crash seen with conform's mustpass.c, select.c and feedback.c.
Also, few gl-select related piglit tests exhibit same crash. Found in vmware's
internal testing
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
v2: incorporated Emma's comments. Added check for PIPE_SHADER_CAP_INTEGERS and
remove PIPE_SHADER_IR_TGSI check
v3: As per Emma's comment, removed expected crashes for i915 piglit
v4: update expetcted passes
(cherry picked from commit b5e782f5f4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12200>
The radv_emit_ngg_culling_state function won't write the
SPI_SHADER_PGM_RSRC2_GS register when it knows in advance that
radv_emit_graphics_pipeline will overwrite it anyway.
However, there is an unhandled case:
radv_emit_graphics_pipeline will not emit anything (including this
register) when the pipeline is already emitted. Hence, improve
the check in radv_emit_ngg_culling_state to consider this.
Fixes: 9a95f5487f
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12237>
(cherry picked from commit 74181ffcc5)
Fixes
In file included from ../src/gallium/drivers/iris/iris_query.c:49:
../src/gallium/drivers/iris/iris_genx_macros.h:81:10: fatal error: genxml/genX_bits.h: No such file or directory
and
In file included from ../src/gallium/drivers/crocus/crocus_query.c:50:
../src/gallium/drivers/crocus/crocus_genx_macros.h:86:10: fatal error: genxml/genX_bits.h: No such file or directory
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12149>
(cherry picked from commit b4214adefc)
It was added to make sure every pipeline for a merge request has at
least one job which passes (otherwise it's not possible to merge the
MR). Now the "sanity" job always exists in such pipelines, so this
isn't needed anymore.
Fixes: 4c41d1900e "ci: Add jobs running ci-fairy checks"
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12198>
(cherry picked from commit 6ccf11ac2b)
Navi 10 can hang when an NGG workgroup has no output,
so we work around that by always exporting a single zero-area
triangle with a single vertex that has all-NaN coordinates.
Thus far, we only employed this for NGG GS, because on all
other stages, the output can't be empty.
However, with NGG culling, the output can be empty, so let's
apply the same workaround there too.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12169>
(cherry picked from commit 448592b9ae)
The `argument::size` is supposed to represent the size of a pointer on
the host and not on the device (for which argument::target_size`
exists).
v3: Use `sizeof(buf)` instead of `marg.size`. (Francisco Jerez)
Fixes: 7c6f1d3bf9 ("clover/nir: extract constant buffer into its own section")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
(cherry picked from commit b4e5bf0637)
This resolves clover returning `CL_INVALID_ARG_SIZE` whenever the OpenCL
CTS called `clSetKernelArg()` for 3-component vectors.
Fixes: 2147386505 ("clover/spirv: Add functions for parsing arguments, linking programs, etc.")
v2: Remove “api/clsetkernelarg/set kernel argument for cl_int3” from the
expected fails for llvmpipe
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
(cherry picked from commit a6c26a6ad9)
SRV descriptors can require state-transitions before it's legal to set
them on the command-list. We used to just set them right away, and get
away with is, because the validator didn't verify this because we used
to flag the parameters as volatile.
Now that we don't, we trigger validation errors when setting a root
parameter that needs a transition first.
So let's split up the logic a bit, so we can prepare the tables, then do
the transision, and finally set the tables. We do this for all tables
instead of just the SRVs, just because it makes the logic a bit easier to
follow. We leave root constants alone, because they will never require
this, and doing them late would just compilcate things.
Fixes: 1208290558 ("d3d12: Sets all SRV descriptors as data-static")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12187>
(cherry picked from commit cd79351f02)
Most of the drivers don't set up the maximum value in the query info. So
when later hud_pane_set_max_value() is invoked, we are using a rather
"random" number.
Turns out that in some 32bit cases, this random number is big enough
that `leftmost_digit` is 0 because DIV_ROUND_UP() overflows, aborting
with an assertion.
Fixes: c91cf7d7d2 ("gallium: implement a heads-up display module")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12181>
(cherry picked from commit 10541d1fad)
This fixes a hang in the following piglit test when GCM moves a
UBO load outside of the loop.
tests/shaders/ssa/fs-if-def-else-break.shader_test
The end NIR ends up looking like this:
vec2 32 ssa_3 = intrinsic load_ubo (ssa_2, ssa_0) (0, 1073741824, 0, 0, 8)
vec1 32 ssa_4 = mov ssa_3.x
vec1 32 ssa_5 = inot ssa_3.y
/* succs: block_1 */
loop {
...
if ssa_5 { }
}
Fixes: 1edf67fc3f ("intel/fs: Generate if instructions with inverted conditions")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
(cherry picked from commit a654e39f15)
To properly init buffer memory requirement for AHB, memory type bits
from dma_buf fd properties need to be masked. However, creating a test
AHB at buffer creation is too costy. This patch caches the ahb backed
buffer memory type bits at device creation time if the app is requesting
AHB extension.
Cc: 21.2 mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12171>
(cherry picked from commit e08960482a)
Similar to the fix in 6bf8e960fa ("pan/bi: Do helper termination
analysis on clauses")
Though apparently a "theoretical issue only", fixes artefacts in
DarkPlaces with both D3D9 and GL renderers.
Fixes: 9a7f0e268b ("pan/mdg: Use the helper invo analyze passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12156>
(cherry picked from commit a2b37e9592)
Hand typed. We could generate this from the XML to avoid the repititon
but I think the cure is worse than the disease.
This fixes instruction encoding faults seen in conformance tests.
Only a single shader-db affected, and it was likely already broken...
quadwords HURT: shaders/glmark/22-1.shader_test MESA_SHADER_FRAGMENT: 133 -> 135 (1.50%)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12114>
(cherry picked from commit 2cdf95703a)
Conflicts:
src/panfrost/bifrost/bi_schedule.c
The existing code handled the case where the new definition of the
same field was larger than the old one.
This commit adds a check to handle the reverse case: the new def
is smaller than the old one (= so writing using the merged macro
would affect the next fields).
The affected fields are:
* LGKM_CNT (in SQ_WAVE_IB_STS)
* DONUT_SPLIT (in VGT_TESS_DISTRIBUTION)
* HEAD_QUEUE (in GDS_GWS_RESOURCE)
DONUT_SPLIT is the only one used by radeonsi/radv.
Fixes: e6184b0892 ("amd/registers: scripts for processing register descriptions in JSON")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12063>
(cherry picked from commit 3914bd457b)
Failure to create a buffer for scanout should not be fatal when
importing a buffer. Buffers allocated from a render-only device may not
be able to scanned out directly but can still be used for other
rendering purposes (e.g. as a texture).
Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12081>
(cherry picked from commit 7bcb223639)
The previous logic was returning a handle valid for the render-only
device if rsc->scanout was NULL. However the caller doesn't expect
this: the caller will use the handle with the KMS device.
Instead of returning a handle for the wrong device, fail if we don't
have one.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074>
(cherry picked from commit 47f000c170)
The previous logic was returning a handle valid for the render-only
device if rsc->scanout was NULL. However the caller doesn't expect
this: the caller will use the handle with the KMS device.
Instead of returning a handle for the wrong device, fail if we don't
have one.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074>
(cherry picked from commit 4c092947df)
The previous logic was returning a handle valid for the render-only
device if rsc->scanout was NULL. However the caller doesn't expect
this: the caller will use the handle with the KMS device.
Instead of returning a handle for the wrong device, fail if we don't
have one.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074>
(cherry picked from commit 465eb7864b)
The previous logic was returning a handle valid for the render-only
device if rsc->scanout was NULL. However the caller doesn't expect
this: the caller will use the handle with the KMS device.
Instead of returning a handle for the wrong device, fail if we don't
have one.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074>
(cherry picked from commit 9da901d2b2)
A previous commit cleaned up the asserts but the last part of
this assert looks like it got mixed up. It should have allowed
param->rel for D3DSPR_INPUT if version is 3.0. Instead it does
&& on the enum value D3DSPR_ADDR which is of course always true,
with the version check. The result is that we miss input
validation with version 3.0.
Spotted by a compile warning
Fixes: 5974401a4a ("st/nine: Regroup param->rel tests")
Reviewed-by: Axel Davy davyaxel0@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11880>
(cherry picked from commit 71a5bcb865)
We can have more than 32 samplers, but the code below will assert in that
case. The return value is not used for samplers, so let's just return
zero early and be done with it.
Fixes: c18ff60087 ("lavapipe: emit correct textures_used for texture-arrays")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11845>
(cherry picked from commit bff8a948f7)
Under XWayland, the first present after a window resize is sometimes
completed with COPY (seems to happen when the previous present with the
old size is pending; not really sure). The following presents are
completed with FLIP.
When a swapchain is created with an old swapchain, and
old_chain->last_present_mode is FLIP, chain->last_present_mode is set to
FLIP as well. This causes the new swapchain to be marked
VK_SUBOPTIMAL_KHR, which is sticky, if the first present is completed
with COPY.
Instead of inheriting, treat each swapchain as independent. We will
miss the case where an old swapchain is flipping but a new swapchain is
copying. But swapchain reallocation normally happens in response to
present engine state change. If the newly allocated swapchain is
copying, another reallocation is unlikely to fix that.
Fixes: 61309c2a72 ("vulkan/wsi/x11: Return VK_SUBOPTIMAL_KHR for X11")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12030>
(cherry picked from commit 206fe780d5)
Implement resource_get_param for PIPE_RESOURCE_PARAM_NPLANES and fix
resource_get_handle to walk to the correct linked resource for
multiplanar images, allowing gbm_bo_get_handle_for_plane to be called
with plane > 0.
This fixes an assert that is triggered when a wayland client tries
to send weston an NV12 dmabuf, for example:
weston: .../mesa/src/gbm/backends/dri/gbm_dri.c:752: gbm_dri_bo_get_handle_for_plane: Assertion `plane == 0' failed.
Fixes: 788f6dc857 ('Revert "gallium/dri: fix dri2_from_planar for multiplanar images"')
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12037>
(cherry picked from commit 8ba44103b3)
The code in dri_make_current just checks the value of the pointers
to decide to update texture_stamp or not. This is buggy since a new
allocated drawable could share the same address with the previous
released drawable. Fix the stale pointer issue by always resetting
these pointers to NULL in dri_unbind_context.
v2:
Move the reset codes to the end of the function.
Signed-off-by: Lepton Wu <lepton@chromium.org>
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12050>
(cherry picked from commit 7ff30a0499)
The comment was incorrect: we can have N draws using the
same mode with N > 1 (eg: GL_QUAD_STRIP draws
cannot be merged).
This commit fixes the drawing code to use the correct draw
function.
This fixes a hang in Starsector (see issue #5086).
Fixes: b328d8e9bc ("dlist: use an union instead of allocating a 1-sized array")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11978>
(cherry picked from commit 11d6441b94)
When the dot product uses a source which can be optimized to a scalar,
after a bunch of nir optimization steps the source to fsum will be a scalar
with a x replicate swizzle. Hence nir_src_num_components is just 1 and the
fsum was just a no-op which is not correct. Arguably this could be optimized
a bit better, but just determine the number of addends by using nir_op_infos
instead (the operand fetch was fixed already by 39a938ecf4 doing the same).
Fixes: 4eb0475b5a ("gallivm/nir: add fsum support")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12066>
(cherry picked from commit cac5711d43)
In v3dv_write_uniforms_wg_offsets() function, the job's cmd_buffer is a
valid command buffer, so there is no reason to check if its NULL or not.
This fixes CID#1487441 ("Dereference after null check") error.
v1:
- `job->cmd_buffer` is the same as `cmd_buffer` (Alejandro)
v2:
- Use `cmd_buffer` instead of `job->cmd_buffer` (Iago)
Fixes: 31a786c80a ("v3dv: handle QUNIFORM_FB_LAYERS")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11999>
(cherry picked from commit 4eb0475b5a)
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern. We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:
1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.
2. It didn't take min_lod into account
3. It was conflated with adding a missing LOD parameter to opcodes
which expect one such as nir_texop_txf. While not really a bug,
this does make it way harder to reason about the code.
4. Unless you set a flag (which most drivers don't), it left the
opcode nir_texop_tex instead of nir_texop_txl which it should have
been.
This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod. We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken. If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.
Fixes: e382890e25 "nir: set default lod to texture opcodes that..."
Fixes: d5ac5d6e83 "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
(cherry picked from commit 74ec2b12be)
Required to build Mesa on macOS with
-Dbuild-tests=true -Dglx=gallium-xlib
Without this change, the build fails with
In file included from ../src/gallium/targets/graw-xlib/graw_xlib.c:8:
../src/gallium/include/frontend/xlibsw_api.h:5:10: fatal error: 'X11/Xlib.h' file not found
#include <X11/Xlib.h>
With `brew sh` X11 is found but linking fails due to `llvm-ar` missing
in the path. That issue appears to be unrelated to this missing
dependency. X11 is installed via XQuartz, so Homebrew should not be
required.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12022>
(cherry picked from commit 061508d310)
This expands on commit c54c42321e. See the code comment for full
justifications. At the time of the previous commit Ian wanted to
limit the relaxing of the rule to GLSL 3.30 as that was the highest
version of shaders seen in the wild that were having trouble with
the stricter rules.
However since then I've found that the long standing issue with tess
shaders failing to compile in the game 'Layers Of Fear' is due to
this same issue. The game uses 4.10 shaders and also makes use of
explicit varying locations, so here we relax the rule to 4.20 and
make sure to apply the restriction to shaders using varyings with
explicit locations also.
Fixes: c54c42321e ("glsl: relax rule on varying matching for shaders older than 4.00")
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11873>
(cherry picked from commit 0e0633ca49)
I was trying to fix this test, but noticed brw_clip.c in i965
does a * 2 here, and it seems to fix this test as well.
Fixes:
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
Fixes: f9e2c24326 ("draw,llvmpipe,util: add depth bias calculation for arb_depth_buffer_float")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12029>
(cherry picked from commit 1e5a470b43)
Unfortunately I contacted the dev about this issue years ago and he
made a fix, but it has never been released after all these years.
This stops the screen from being completely black in game.
CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11941>
(cherry picked from commit f3ec4a934d)
Before commit f7e0cdcf1a, we tried these in order
- if (!ForceSoftware) surfaceless_probe_device(disp, false);
- surfaceless_probe_device(disp, true);
- surfaceless_probe_device_sw(disp);
The commit changed it to
- surfaceless_probe_device(disp, ForceSoftware);
- surfaceless_probe_device_sw(disp);
and broke 2D virtio-gpu and vgem when ForceSoftware is false. This
commit restores the old behavior.
Fixes: f7e0cdcf1a ("egl/surfaceless: simplify dri2_initialize_surfaceless()")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11992>
(cherry picked from commit 384181921c)
With this pass enabled in Intel drivers, running shader-db on
shaders/unity/38.shader_test resulted in
Program received signal SIGSEGV, Segmentation fault.
gcm_schedule_early_src (src=0x555555d45348, void_state=0x7fffffffba40) at ../../SOURCE/master/src/compiler/nir/nir_opt_gcm.c:297
297 if (info->early_block->index < src_info->early_block->index)
(gdb) print src_info->early_block
$1 = (nir_block *) 0x0
I tracked this down to an early exit from gcm_schedule_early_instr on
the parent instruction because instr->pass_flags was 0x1c. That
should be an impossible value for this pass, so I inferred that
pass_flags must have dirt left from some previous pass.
Fixes: 8dfe6f672f ("nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinned")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
(cherry picked from commit 436668874a)
Like in the case of emitting a block, process pending TMU operations
before a jump is executed.
Fixes dEQP-VK.graphicsfuzz.stable-binarysearch-tree-nested-if-and-conditional.
Fixes: 197090a3fc ("broadcom/compiler: implement pipelining for general
TMU operations")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11971>
(cherry picked from commit dc40157888)
The function radeonsi_screen_create_impl() tries to create the
aux_context but doesn't actually check for the returned value from
si_create_context().
Then, on si_destroy_screen() the aux_context is used without actually
checking whether it's a thing or not.
As a result, if for any reason si_create_context() failed, we shall
crash in si_destroy_screen() with a NULL pointer dereference trying to
access ((struct si_context *)sscreen->aux_context)->log.
Simply check for aux_context not being NULL to avoid that crash.
Cc: mesa-stable
Signed-off-by: Olivier Fourdan <ofourdan@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11948>
(cherry picked from commit 5bfd1a7e19)
Originally I fixed the case where the nir itself has a shared mem size of
0, but the frontend (e.g. clover) set it to some other value.
But st/mesa sets the shared mem size on the state object as well and we
end up actually doubling the value in the driver as we set smemSize to the
value from the state object before calling into the compiler.
So just max the value instead.
Fixes the compute_shader.shared-max CTS test.
Fixes: dc667b1f19 ("nv50/ir/nir: fix smem size")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11047>
(cherry picked from commit ff55412f40)
This replaces some new/delete uses with malloc/free.
This is more consistent with most of the other glsl IR code but
more importantly it allows the game "Battle Block Theater" to
start working on some mesa drivers. The game overrides new and
ends up throwing an assert and crashing when it sees this
function calling new [0].
Note: The game still crashes with radeonsi due to similar conflicts
with LLVM.
CC: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11907>
(cherry picked from commit 749251391d)
Error handling with DRM_IOCTL_I915_QUERY is tricky and we got it wrong
in one of the two calls here. Use the common helper instead. This also
fixes a theoretical bug where calloc() fails. While we're here, inline
iris_bufmgr_update_meminfo because we're not really benefiting from
having it separate anymore.
Fixes: e60114b2ae "iris/bufmgr: Query memory region info."
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
(cherry picked from commit 3fa6b8d041)
Error handling with DRM_IOCTL_I915_QUERY is tricky and we got it wrong
in one of the two calls here. Use the common helper instead. This also
fixes a theoretical bug where calloc() fails. While we're here, inline
anv_track_meminfo because we're not really benefiting from having it
separate anymore.
Fixes: 65e8d72bc1 "anv: Query memory region info"
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
(cherry picked from commit 35ec1d9730)
We also add a helper which contains the standard query+alloc+query
pattern used by anv_gem_get_engine_info(). The caller is required to
free the pointer.
These are declared static inline not because we care about the
performance of these helpers but because we're going to use them in the
intel_device_info code and we don't want a link dependency.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
(cherry picked from commit ffdf4d7683)
DRM_IOCTL_I915_QUERY is a multi-query. The most egregious errors are
returned via the usual ioctl error mechanism but there are also
per-query errors that are indicated by item.length < 0. We need to
handle those as well. While we're at it, scrape errno so we can return
a proper integer error.
Fixes: c0d07c838a "anv: Support i915 query (DRM_IOCTL_I915_QUERY)..."
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770>
(cherry picked from commit b664481ba9)
On APUs, we fake heaps to simulate a dGPU setup because it seems to
have the maximum compatibility. Though, some applications like RDR2
still only looks at GTT if the driver reports an iGPU which means it
will only use 1/3rd of total memory available.
This is currently behind a drirc option because it might have
implications for other apps but we might want to extend this later
if everything is fine.
Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11891>
(cherry picked from commit cadf2d63b7)
Fix defect reported by Coverity Scan.
Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking so suggests that it may be null,
but it has already been dereferenced on all paths leading to the
check.
Fixes: dcd2d8ca50 ("asahi: Track more Gallium state")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11898>
(cherry picked from commit f5c8761eda)
Drops the vk_format_to_pipe (and it's outdated table) for vk_format_to_pipe_format, aswell as the duplicated vk_format_aspects function.
The old format table was missing USCALED and other values, causing incorrect rendering in many games.
Fixes rendering in Portal 1, Hat in Time, Half-Life 2 and pretty much every other D3D9 title with DXVK.
Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11863>
(cherry picked from commit 1744372714)
Performance improvement in
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 for n=30:
release build (w/Fedora build flags): -0.82% ± 0.23%
Meson -Dbuildtype=debugoptimized: -0.74% ± 0.27%
The difference in the debugoptimized build is the calls to
inst_is_in_block(block, this) still exist on each call to remove().
v2: Only update each block's IP data once instead of once per block.
Suggested by Emma.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
Performance improvement in
dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13 for n=30:
release build (w/Fedora build flags): -7.79% ± 0.25%
Meson -Dbuildtype=debugoptimized: -5.10% ± 0.40%
The difference in the debugoptimized build is the calls to
inst_is_in_block(block, this) still exist on each call to remove().
v2: Only update each block's IP data once instead of once per block.
Suggested by Emma.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11632>
OpenGL ES 3.1 specifies that a geometry shader can write to gl_PrimitiveID,
which can then be read by a fragment shader.
OpenGL ES 3.2 additionally adds the capacity for the fragment shader
to read gl_PrimitiveID even if there is no geometry shader. This
commit adds support for this feature, which is also implicitly
expected by the geometry shader feature in Vulkan 1.0.
Fixes:
dEQP-VK.pipeline.framebuffer_attachment.no_attachments
dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11874>
If all drawing is scissored but we have multiple discontinuous
scissor rects, we end up flushing all the tiles in the rect that
covers all scissor rects, which can be a waste, particularly for
large render targets. The obvious case for this are updates to a
mega texture or atlas for example.
This change checks if all rendering happenings against scissor
rects, in which case it keeps track of the rects and uses this to
discard tiles that are not included in any of them.
This optimization needs to be disabled if we have any
non-scissored rendering, including non-scissored clears.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11875>
The Vulkan 1.2 specification, section 11.2.12 ("Host Access to Device
Memory Objects") say the following:
> memory must have been created with a memory type that reports
> VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
Since there's no guarantee that there's any memory that is *both*
device-local *and* host-visible, let's just use the latter requirement.
Fixes: 8af568e4ae ("vulkan: implement wsi_win32 backend")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11848>
The Vulkan 1.2 specification, section 11.2.12 ("Host Access to Device
Memory Objects") say the following:
> If size is not equal to VK_WHOLE_SIZE, size must be greater than 0
So, mapping a zero-sized range is illegal. Let's instead map the
reported size of the image, which we already know.
Fixes: 8af568e4ae ("vulkan: implement wsi_win32 backend")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11848>
This way we can make the tables const. At the same time, for a6xx, this
introduces a "sub-generation template" to reduce the copy/paste for
parameters which are keyed to the sub-generation. It also explicitly
lists every supported GPU, to get rid of duplicate lists of supported
gpus between the device-info and drivers.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>
- It hurts users with newer firmware who don't need the workaround
- Kernel now rejects older firmware due to security issues, so this will
prevent users from using older firmware anyway.
- Only whitelisting 650 enables the workaround by default for any new GPUs
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>
Culling is traditionally done by the rasterizer, but that
can be a bottleneck when an app creates a large number
of primitives. Eg. a lot of tiny triangles reduce the
rasterziation efficiency.
NGG makes it possible for the shader to check primitives
and delete those that it can prove are not needed.
After this is done, we have to repack the surviving invocations
so they remain compact. This also saves bandwidth, because
some memory loads are only executed by those vertices that
survived the culling.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
The new intrinsics fall into the following categories:
1. New viewport intrinsics:
For missing components that we need.
RADV will emit new SGPR arguments which will contain the
viewport information for culling shaders. These are used to
compute the screen space coordinates for small primitive culling.
2. load_cull_xxx:
Load the culling settings in runtime.
These will be a new SGPR argument in RADV.
3. overwrite_xxx:
These are needed because system values such as vertex and
instance ID are not writeable, but we need to change them
after repacking shader invocations of VS and TES.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
No need to include the same BO multiple times in the long-lived ringbuffer
object's list of relocs to be added to the submit.
Improves non-TC drawoverhead -test 9 (8 tex updates) throughput by 1.4901%
+/- 0.8705% (n=20)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11697>
On drawoverhead -test 9 (8 texture changes), this saves us 172kb of
memory. That's only ~1% of the GEM memory while the test is running, but
more importantly it saves us 29% of the gem BO allocations.
non-TC drawoverhead -test 9 (8 texture change) throughput 0.449019% +/-
0.336296% (n=100), but this gets better as we get better suballocation
density.
Note that this means that all fd_ringbuffer_new_object calls can now
return data aligned to 64 bytes, instead of 4k. We may find that we need
to increase it if some of our objects (tex consts, sampler consts, etc.)
require more alignment than that. But, this may help non-drawoverhead
perf if any of our RB objects have a cache in front of them (indirect
consts?) and we don't have most of our data in the same cache set any
more.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11697>
This migration was done with libclang-based automatic tooling, which
performed these replacements:
* Operand(uint8_t) -> Operand::c8
* Operand(uint16_t) -> Operand::c16
* Operand(uint32_t, false) -> Operand::c32
* Operand(uint32_t, bool) -> Operand::c32_or_c64
* Operand(uint64_t) -> Operand::c64
* Operand(0) -> Operand::zero(num_bytes)
Casts that were previously used for constructor selection have automatically
been removed (e.g. Operand((uint16_t)1) -> Operand::c16(1)).
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11653>
Emit all the state layout config (such as push-const CONSTLEN) first,
before emitting anything that depends on that state. This fixes an
issue that was showing up when FLUT is enabled in ir3 (which results
in higher probability of not having any immediats lowered to push-
consts).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8705>
these are the only frontends which may be used by gallium drivers in ci,
so stop triggering all driver jobs when other frontends are changed since
those changes can never affect ci
<MrCooper> Not that simple unfortunately. E.g. the llvmpipe-piglit-cl job hits
src/gallium/frontends/clover & possibly src/gallium/targets/opencl,
many jobs hit src/gallium/{frontends,targets}/dri and probably
src/gallium/targets/pipe-loader, lavapipe jobs hit src/gallium/{frontends,targets}/lavapipe.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11832>
Otherwise there would be no clause with the dependencies needed for
ATEST set, so the GPU would get stuck.
Not needed on v7, as there shader_wait_dependency in the RSD will wait
for the dependencies before the shader starts.
Explicitly create a NOP instruction, as it is assumed that clauses
have a non-zero count of instructions in various places.
Fixes GPU timeouts in many applications, such as SuperTuxKart and
GZDoom.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11842>
Doing *both* of thse ends up rewriting the previous mapping. Since this
doesn't seem to have lead to issues, it seems like the new mapping works
just as well.
Fixes: a22a1c0324 ("zink: Fix VK_FORMAT_A8B8G8R8_SRGB_PACK32 mapping on big-endian")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11417>
I factored out the chunk of loader code that dlopen()s
libraries from the rest of the DRI driver loader function
in this commit:
commit bc343154f8
Author: James Jones <jajones@nvidia.com>
Date: Thu Apr 22 23:17:08 2021 -0700
loader: Factor out driver library loading code
However, I failed to adjust the DRI loader function that
now uses the new helper function to handle the case where
the requested DRI library is not found.
This change restores the prior behavior, and also ensures
loader_open_driver() consistently returns NULL in the
out_driver_handle parameter on failure.
Fixes: bc343154f8 ("loader: Factor out driver library loading code")
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11807>
If the allocated_vec map contains a different RegType
for the elements, ensure that the size matches exactly.
Otherwise, it could happen that extracting a dword
element matched with a subdword element.
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11823>
Unlike the dependency analysis for the skip bits which is a function of
the data flow graph, the thread termination analysis is dependent on the
actual sequence of instructions. As such, it must be done after
scheduling to be correct in the presence of out-of-order scheduling.
Furthermore it's specified in terms of clauses, not instructions.
Reflecting this in our code gets a nice simplification. As a side effect
this puts extra td flags on subsequent clauses, which matches the DDK's
behaviour. (Maybe td is just a hint?)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10961>
This was useful when panvk was being bootstrapped, allowing the blitter
to be tested against a known-working driver. With panvk in-tree, I don't
see a compelling reason to keep pan_blitter support wired in but
off-by-default. Keeping it will complicate the GenXML change we're about
to make.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11785>
The strictLines-feature requires lines to be rasterized as rectangles
by default instead of using the parallelograms you get from extending
bresenham lines along their minor axis.
Now that we can specify the line mode fully we can actually express
this, so let's do so.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11782>
With the new rectangular_lines state, we can now support rasterizing
wide lines correctly according to the vulkan spec, where this can be
specified independently of the rest of the state.
Because rectangular lines are orthogonal to multi-sampling, we now need
to also adjust with the pixel-offset in the rectangle code-path as well.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11782>
Now that we have a separate flag to signal rectangular lines, let's use
that instead of the smooth-flag.
This should have the benefit of also drawing rectangular lines when
multisampling stippled, non-smooth lines. But it seems there were no
test for that, so no results to update.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11782>
Currently, drivers infer the line rasterization mode from the
multisampling and line_smooth rasterization state. This is always
correct for OpenGL, but is subtly incorrect for DirectX 9, 10 and
Vulkan (when VK_EXT_line_rasterization is supported).
So let's allow front-ends to choose freely between rectangle and
paralellogram rendering.
The reason why there's no added cap for this, is that the implicit
selection that drivers currently do will work just as well (or more
correclty, just as subtly wrong) as before. And there's nothing
reasonable the front-ends can do to get the correct behavior, so
there's really no fall-back code to write either.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11782>
There's two of the line-modes that warrants disabling multisampling,
and that's bresenham and smooth lines.
The reason we need this for the smooth lines case, is that multisampling
overrides the smooth-flag.
Fixes: 9fbf6b2abf ("lavapipe: implement VK_EXT_line_rasterization")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11782>
this is the surface struct used by the caching manager to generate a ref update template,
which means it must be kept in sync with the current state of descriptors
when the struct is zeroed, it implies that no refs need to be taken for the cached set
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11829>
clang-format does a bad job with a few tables and macros, and there were
some places it was doing wonky things because comments were longer than
80 characters and it tries to fix that without reformatting the comment
itself. Add magic comments to tell it to turn itself off and retab those
places manually (well, with a regex!).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801>
If we're doing separate front/back stencil ops, then in the absence of a
hardware bit for setting front_ccw (which you can already see from how we
manage cull face) we need to flip front/back stencil register settings.
Closes: #4974, #4975
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11706>
I believe these Gallium caps imply these Vulkan features. If they don't,
then we got things wrong on the Zink side as well ;)
While we're at it, query shaderStorageImageWriteWithoutFormat based on
the PIPE_SHADER_CAP_MAX_SHADER_IMAGES cap. This matches what the gallium
OpenGL frontend does.
This brings Zink on Lavapipe up to OpenGL 4.5.
For some reason, a bunch of PBO tests starts failing on CI for Zink, but
that doesn't seem like a Lavapipe problem...
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10467>
A run of dEQP-VK.*geom* has 6328 test passes and 16 failures. 14 of
these failures are related to a CTS bug affecting atomic operations
for which I submitted a CL to Khronos. Another fail looks like it might
be a case of the error threshold in CTS being slightly low. There is
only one test fail in that list that looks like it might be an actual
driver bug, but it is a variable pointers test, so it might be unrelated
to geometry shaders in the end.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11783>
This was required to handle the case of secondary command buffers that
did not have framebuffer information available from the primary, since
we used to have an implementation that required this information to
be available for the fallback path of vkCmdClearAttachments. Now that
we can handle our our attachment clears in the current subpass by
emitting draw calls, we no longer need the framebuffer information to
be available and we can remove this.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11783>
Now that we have geometry shaders, we can leverage this to implement
clears of layered framebuffers by adding a geometry shader in our
clear pipelines that redirects the clear rect to the appropriate
layer in the framebuffer, instead of falling back to emitting separate
clear jobs for each layer, which is a lot slower.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11783>
There is a bit of a corner case here for secondary buffers that
don't inherit framebuffer information, since those won't have
access to the number of layers in the framebuffer by the time
we get here. Since we only emit this to sanitize the value of
gl_Layer produced from geometry shaders, I think it is probably
fine to lie about it and just use the maximum number of layers
we support. The only issue with that is that broken shaders that
emit out of bounds layer indices (which the spect states may lead
to unfined shading results) may cause undefined results.
In the future we could do better and patch the uniform streams
later when the secondary is executed inside a primary, since we
will have the required framebuffer information at that point,
but for now this seems like a reasonable compromise.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11783>
I removed this because I thought the state tracker could handle it,
and it really should handle it, but it has some minecraft side effects
I'm unsure about. This fixes the problem for now, we can revisit it later.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11822>
This uses Antonio's src/panfrost/perf for all the heavylifting, just
like the Perfetto producer. Unlike the Perfetto producer, it has no
dependencies and is a lot less useful. But it's a good smoke test.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11733>
Set the .skip bit on texture instructions and the terminate discarded
threads bit on the clause header based on data flow analysis of helper
invocations. This code is adapted from Midgard, which requires the same
analysis with a few details changed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11733>
Bifrost v7 trades off register pressure and occupancy. If we restrict to
[R0, R15] U [R48, R63], we get full occupancy, but if we use the full
register file, we only get half occupancy. Try to allocate just 32
registers, and only use the full 64 registers if that would spill.
Clever heuristics could make this both more effective (live range
splitting, shuffling, spilling if deemed acceptable) and cheaper at
compile-time (tracking maximum liveness to determine if it's possible to
hit at all). For now, this should suffice.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11733>
For virgl backend used in ARCVM, cros buffer info query brings back
real modifier info for the host image, which cannot be resolved by the
gallium virgl backend. Thus the fallback path is used here.
This patch fixes a behavior change introduced by a prior commit.
Fixes: 5d3e64f1 ("egl: android: prepare code for adding more buffer_info getters")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11771>
For compute shader textures that are backed by a display target, do not
leak the mapped pointer and unmap when access to the mapped resource is
not needed anymore.
Also use llvmpipe_resource_[un]map instead of calling winsys map
functions directly.
v2:
- use llvmpipe_resource_[un]map directly instead of winsys DT map
func and unneeded helper function for unmapping.
v3 (Emil Velikov):
- add comment in lp_csctx_set_sampler_views to explain
unmapping current texture early in the loop.
Signed-off-by: Heinrich Fink <hfink@snap.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11741>
For fragment shader textures that are backed by a display target, do not
leak the mapped pointer, but unmap before unref'ing its associated
pipe_resource instances.
Also, make sure that the pointer that's mapped into a jit texture stays
valid while rasterization works on a jit context copy by mapping the
display target again during scene setup, and unmapping when finalizing
rasterization.
v2 (Daniel Stone):
- remove redundant helper function for [un]mapping DT, use
llvmpipe_resource_[un]map right away
v3 (Emil Velikov):
- add comment in lp_setup_set_fragment_sampler_views to explain
unmapping current texture early in the loop
Signed-off-by: Heinrich Fink <hfink@snap.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11741>
Revive hooks for cleaning up shader sampler and image data and when
finalizing llvmpipe_draw_vbo. In cleanup routines, for any sampler or
image that was set up with displaytarget_map, call displaytarget_unmap.
This fixes leaks of mmap calls of the underlying displaytarget
resources.
v2 (Daniel Stone):
- Use a single cleanup function for sampler/image to simplify patchset
v3 (Emil Velikov):
- use llvmpipe_resource_[un]map instead of open-coding through
winsys
v4:
- check tex/image for NULL before calling into
llvmpipe_resource_unmap (fixes dEQP crash of llvmpipe runner)
Signed-off-by: Heinrich Fink <hfink@snap.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11741>
We currently require VK_EXT_line_rasterization with *all* optional
features to render all kinds of lines required. Because some (if not
all) of these can be emulated, let's make the list explicit, so it's
easy to remove items as we implement emulation.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>
The VK_EXT_line_rasterization extension allows to specify the
correct line-rasterization rules, which is needed for correct OpenGL
rendering.
So, let's prepare for filling this one out. Right now, it does a whole
lot of nothing, but that's about to change.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>
Example of blob's output:
(nop3) shlg.b16 hr8.x, (r)8, (r)hr8.x, 12
It does: (src2 << src1) | src2
src1 and src2 could be GPRs, relative GPRs, relative consts,
or immidiates. However, they could not be plain const registers.
Blob does use it in conjuncture with "samgq" instruction.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11760>
This is required by the Vulkan specification:
If pSurfaceFormats includes an entry whose value for colorSpace is
VK_COLOR_SPACE_SRGB_NONLINEAR_KHR and whose value for format is a UNORM
(or SRGB) format and the corresponding SRGB (or UNORM) format is a color
renderable format for VK_IMAGE_TILING_OPTIMAL, then pSurfaceFormats must also
contain an entry with the same value for colorSpace and format equal to the
corresponding SRGB (or UNORM) format.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11778>
Specifically A8B8G8R8_UINT_PACK32, A8B8G8R8_SINT_PACK32, and
A2B10G10R10_UINT_PACK32. They are based on the internal types RGBA8UI,
RGBA8I, and RGB10_A2UI, that are not filterable.
That gets several failing CTS like this:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.3d.a8b8g8r8_uint_pack32.a8b8g8r8_uint_pack32.optimal_optimal_linear_stripes_x
To properly skip instead of fail. So we also update the ci
expectation.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11794>
It's only used in assert. Avoids compiler warning/error with assertions disabled:
../src/freedreno/vulkan/tu_cs.h: In function 'tu_cs_reserve':
../src/freedreno/vulkan/tu_cs.h:208:13: error: unused variable 'result' [-Werror=unused-variable]
208 | VkResult result = tu_cs_reserve_space(cs, reserved_size);
| ^~~~~~
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>
This reduces cache-misses in execute_list for apps using lots of small
dlist, like viewperf.
This is only done for small dlist (fitting in one block) because doing
this for larger ones wouldn't bring any benefit.
For instance, in vp13/snx test 10: the % of cache-misses events in
_mesa_glthread_execute_list/execute_list goes down from 17%/10% to 4%/3%.
If "struct gl_display_list" were stored in an array this would also
remove source of cache-misses since currently they're malloc-ed
individually.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>
OpenGL 4.6 compatibility profile spec, Appendix B:
21. For any GL and framebuffer state, and for any group of GL commands and
arguments, the resulting GL and framebuffer state is identical whether the
GL commands and arguments are executed normally or from a display list.
The only exception to this corollary is for built-in shader variables
gl_VertexID and gl_PrimitiveID, which are not defined when drawing
geometry within a display list.
(thanks Ian Romanick for pointing this out in piglit !419 MR)
Remove the code introduced in ebb228bec5 to determine if merged draws can be used.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>
When EGL_KHR_mutable_render_buffer extension is enabled, advertised
configs unconditionally include EGL_MUTABLE_RENDER_BUFFER_BIT_KHR bit.
However, f61337b5 starts requesting front rendering usage bit when
EGL_MUTABLE_RENDER_BUFFER_BIT_KHR is seen on the SurfaceType, which
essentially forces linear usage on all winsys BOs for gallium dri and
i965 drivers on Android when cros gralloc is in use.
This patch dynamically appends or strips the front rendering usage bit
depends on whether EGL_RENDER_BUFFER is EGL_SINGLE_BUFFER or
EGL_BACK_BUFFER. The next dequeuBuffer call will switch the buffer
sharing mode while re-allocating winsys BOs given the updated gralloc
usage bits if necessary.
v2: handle ANativeWindow_setUsage on error
Fixes: f61337b5 ("egl/android: check front rendering support for cros gralloc")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11787>
Android.mk files haven't really been supported by Mesa devs for a long
time. Most of us have been willing to update Makefile.sources if we
remember and sometimes we try to blind code some Android.mk for a new
generator. However, the reality is that it breaks regularly and ends up
being maintained by the Android community. To address this problem
another approach was implemented in !10183 utilizing the maintained
meson build system. The old Android.mk files are no longer required.
This commit was created with the following commands:
git rm **/Android.mk
git rm **/Android.*.mk
git rm **/Makefile.sources
git rm CleanSpec.mk
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4487
Acked-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9728>
Always execute the bbox code regardless of negative W, and then simply
use || to discard the result if any W is negative. This is expected to be
rare. (it only happens when a primitive intersects the near plane)
This allows us to eliminate the else statement, which is no longer
executed for accepted primitives with negative W, which are the only
primitives that needed the else branch.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
We say that they're for debug only but we don't really have a good
policy around when to set them and when not to. In particular,
nir_lower_system_values and nir_lower_vars_to_ssa which are the chief
producers of SSA values which might reasonably have a name do not bother
to set one. We have some names set from things like BLORP and RADV's
meta shaders but AFAICT, they're setting a name more because it's there
than because they actually care.
Also, most things other than nir_clone and nir_serialize don't bother to
try and preserve them. You can see in the diffstat of this commit
exactly what passes attempt to preserve names. Notably missing from the
list is opt_algebraic which is the single largest source of SSA def
churn and it happily throws names away.
These observations lead me to question whether or not names are actually
useful at all or if they're just taking up space (8B per instruction)
and wasting CPU cycles (to ralloc_strdup on the off chance we do have
one). I don't think I can think of a single time in recent history
where I've been debugging a shader issue and a SSA value name has been
there and been useful. If anything, the few times they are there, they
just throw me off because they mess up the indentation in nir_print.
iris shader-db on my system gets runtime -2.07734% +/- 1.26933% (n=5)
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5439>
The intention is to pick the system memory for the prime blit dst, but
that is not possible when all memory types are advertised to be local.
This fixes venus over vtest (i.e., unix socket) because the driver
provides no PCI bus info and wsi_device_matches_drm_fd returns false. A
driver might also use can_present_on_device to force prime blit.
Fixes: 469875596a ("vulkan/wsi: Fix prime blits to use system memory for the destination")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11774>
This prevents the previous commit from being undone by the jump
optimizations in legalize, and fixes another potential case where
instead of a continue we have an if/else at the end of a loop.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
When loops have continue statements, it's expected that when we execute
a divergent continue (i.e. a continue where not all of the threads
active at the start take it) we keep going with the rest of the loop
body and then reconverge at the start of the next iteration. However the
Adreno ISA seems to always take a branch that jumps backwards, assuming
it's the bottom of a loop, so we get a different, undesired convergence
behavior. There's no way I know of to control this behavior in the
instruction set, so we have to instead insert a "continue block" at the
end of the loop where continue statements reconverge which then jumps
back to the top of the loop. Since this doesn't correspond 1:1 with any
NIR block we have to make control flow handling in NIR->ir3 a bit more
complicated, unfortunately.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
When we go to split e.g. a p0.x producer, the only other instructions
ready to schedule are often only p0.x producers. It could happen that
they all have a lower priority than the split instruction. Then we would
immediately schedule the split instruction again, then again try to
schedule one of the other producers, be blocked, and split it, around
and around again, leading to an infinite loop. The following commit
triggered this with
dEQP-GLES3.functional.shaders.discard.dynamic_loop_always on a3xx.
Fixes: d2f4d33 ("freedreno/ir3: new pre-RA scheduler")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
MOVMSK is a bit of a special case, because it takes multiple cycles (and
therefore reduces the nops needed if it's between some other assigner
and consumer) however weird things happen if you try to start reading
the first component while it isn't finished yet. On balance making it
use repeat seems to result in a fewer special cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
I realized that shared registers were never actually getting folded,
even after adding them to valid_flags, because the move wasn't even
being considered.
I looked at the other uses of is_same_type_mov(), and they should be ok
with this.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
This fixes a pre-existing bug in ir3, but it showed up even more due to
other changes in this series and it interacts with the logical/physical
CFG split. When both sides of an if end with a jump, a block may become
unreachable via the logical CFG, which can cause problems because it has
no predecessors to figure out the location of live-in non-shared
values. In this case we assume that nir_opt_if has removed any code in
these blocks and just skip processing live-ins for these blocks,
pretending that they aren't live.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
The way that the blob obtains the subgroup id on compute shaders is by
just and'ing gl_LocalInvocationIndex with 63, since it advertizes a
subgroupSize of 64. In order to support VK_EXT_subgroup_size_control and
expose a subgroupSize of 128, we'll have to do something a little more
flexible. Sometimes we have to fall back to a subgroup size of 64 due to
various constraints, and in that case we have to fake a subgroup size of
128 while actually using 64 under the hood, by just pretending that the
upper 64 invocations are all disabled. However when computing the
subgroup id we need to use the "real" subgroup size. For this purpose we
plumb through a driver param which exposes the real subgroup size. If
the user forces a particular subgroup size then we lower
load_subgroup_size in nir_lower_subgroups, otherwise we let it through,
and we assume when translating to ir3 that load_subgroup_size means
"give me the *actual* subgroup size that you decided in RA" and give you
the driver param.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
On qualcomm, we have shared registers similar to SGPR's on AMD. However,
there is no readlane or readfirstlane primitive. shared registers can
only be written to when just one lane is active. This means that we have
to lower readInvocation(val, id) to something like:
if (gl_SubgroupInvocation == id) {
scalar_reg = val;
}
return scalar_reg;
However it's a bit difficult to actually get the value of
gl_SubgroupInvocation in the backend, because for compute it requires
some calculations and we don't have any CSE support in the backend. This
intrinsic lets us turn it into
"readInvocationCond(val, id == gl_SubgroupInvocation)" in NIR at which
point the backend code generation is a lot easier.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
Qualcomm has a mode with a subgroup size of 128, so just emitting larger
integer operations and then lowering them later isn't an option. This
makes the pass able to handle the lowering itself, so that we don't have
to go down to 64-thread wavefronts when ballots are used.
(The GLSL and legacy SPIR-V extensions only support a maximum of 64
threads, but I guess we'll cross that bridge when we come to it...)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
We try to place persistent/coherent buffers from the application in
system memory, because they want the CPU-GPU coherency.
However, our internal u_upload_mgr buffers are also flagged persistent +
coherent, but we absolutely want most of them in device local memory.
Mark had done this correctly in an earlier patch series, but I made a
mistake when refactoring things during upstreaming, and accidentally
put these in SMEM again. This fixes that mistake.
Tested-by: Luis Felipe Strano Moraes <luis.strano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11681>
Bifrost has a new type of job called 'index-driven vertex', which takes
in two shaders. The primary shader, called for all values, performs
position shading to a cacheline-aligned attribute buffer. The secondary
shader, called for values still live after culling, performs varying
shading.
It is the responsiblilty of the implementation to ensure that vertices
from different instances do not share a cacheline.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11413>
This adds a helper isl_surf_get_uncompressed_surf for creating a surface
which provides an uncompressed view into a compressed surface. The code
is basically a direct port of the uncompressed surface code from the
Vulkan driver which, in turn, was a port from BLORP.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11647>
Back when SSBOs were first enabled in i965, we tried to work around
issues where the CPU and GPU were incoherently writing to the same
cacheline by forcing an alignment such that different sections of
data would fall in different cachelines. This seems wrong.
On integrated GPUs with LLC, CPU and GPU writes should be coherent.
On integrated GPUs without LLC, we either enable snooping (so they
are again coherent), or we use WC maps (so the CPU cache isn't used).
Discrete GPUs always use WC maps (so the CPU cache isn't used).
This should work. In other words, I think the increased alignment
was just working around coherency problems on atoms that have been
fixed in the intervening 6 year time period.
Untyped surface messages require 4B alignment.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5016
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11727>
Since writers are counted in the accessor set, the old implementation
had a redundant flush in the "flush accessing" case. To fix, split the
two modes into separate functions, removing the redundancy and offering
a much more ergonomic API.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11077>
Reduces the work that other shader passes have to do to look at dead code,
and possibly extra rounds around the optimization loop if dce wasn't the
last pass in it.
shader-db runtime -1.12919% +/- 0.264337% (n=49) on SKL.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11628>
if shaders aren't being shared between programs, they can instead directly
assign io between the shader stages such that only the producer and consumer
pair need to have their slots match up
this requires that each gfx program struct stores base nir for a given shader
in order to avoid breaking io for other programs which reuse shader states
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11691>
After attempting to use the GBM backend specified by the user
via an environment variable, if any, but before falling back
to the built-in GBM backends, attempt to dlopen
libg<DRM driver name>_gbm.so in the GBM backend library search
path (Defaults to "$libdir/gbm") and initialize a device using
it. This enables automatic backend discovery for devices that
do not provide a DRI driver.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9902>
If the user specifies a backend name explicitly
via an environment variable and it is not in the
list of built-in backends, attempt to load it at
runtime.
runtime-loaded backends get a new gbm_backend_desc
struct instance for each device using them (A
small increase in memory usage to eliminate the
need for the locking and bookkeeping sharing them
would require), so these structures need to be
freed when destroying devices using runtime-loaded
backends.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9902>
A subsequent change will allow loading backends
from DSOs specified by the GBM_BACKEND environment
variable. The exact DSO name and path are derived
by the common loader code and will be of the form:
<gbm_backend_path>/<GBM_BACKEND>_gbm.so
E.g., a user would set the environment variable to
"external" to load "external_gbm.so". Users will
also still be able to explicitly request any
builtin backends by name as well, so this change
helps keep the environment variable syntax
consistent between internal and external backends.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9902>
Define a version number for the interface GBM uses
to offload work to its backends/drivers. Store the
version in the backend interface structs provided
to the loader by backends, as well as in the core
interface struct provided to backends by the GBM
loader code to backends.
The backend can create structures of any version
it supports, which can be greater or less than the
interface version specified by GBM in the core
interface structure. Hence, GBM will need to take
care to check the backend version before accessing
any members added to structs defined in
gbm_backend_abi.h after this change.
Similarly, the backend may need to check the
interface version supported by the GBM library
before passing back data in any structure members
that require the GBM library to interact with
them for correct operation. For example, if for
some reason a structure defined in
gbm_backend_abi.h gained a field which was a
pointer to memory allocated by the backend and
freed by GBM, the backend should avoid allocating
this memory if the GBM library did not specify an
interface version new enough to indicate that it
was aware of the new structure member.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9902>
The GBM core/loader code defines one helper
function used by both itself and the built-in DRI
backend. Presumably, external backend authors
would want to use such functions as well, so
package them into a single struct that will be
passed explicitly to externally loaded backends in
subsequent changes.
Another option considered was to simply export
the gbm_format_canonicalize() function directly,
optionally renaming it to better indicate it is
intended only for "internal" use first. However,
even with a rename, this would expose it to
potential use by applications as well, which is
not ideal, as it is not intended to be part of
the application-facing GBM ABI.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9902>
There is some hardware with num_render_backends == 1, but the number
of render backends in GB_ADDR_CFG > 1. Turns out this can be turned
off by making them rb unaligned which is valid with only 1 render
backend.
Fixes: 0833dd7d12 ("amd/common: Add support for modifiers.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10575>
Per OpenGL Shading Language, section 8.11. "Atomic Memory Functions"
first argument "mem" of all atomicOP functions is inout.
The same is true for ARB_shader_storage_buffer_object and
GL_INTEL_shader_atomic_float_minmax
For implicit conversion of inout parameters it is required for type
to support bi-directional conversion, since there is no such types
in glsl - implicit conversion is effectively prohibited.
Alternatively we could have marked atomic_var parameter of built-in
atomicOP functions as inout, however it opens another can of worms
during NIR lowerings.
Fixes: ea0a1f5beb
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2837
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4887>
The Gallium and Vulkan drivers will soon use different memory pool
implementation, but some pieces in libpanfrost depend on pan_pool. Let's
split the implementation so we have common bits still available while
letting the drivers implement what really matters: the allocation logic.
All the generic pieces are prefixed pan_pool, and what will become the
gallium implementation is prefixed panfrost_pool. We'll then duplicate
the panfrost_pool bits in panvk and prefix it with panvk_pool, and
implementations will start diverging from there.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
The code was using a prim assembler after the tess stage, however
tess prims aren't necessarily the output prim types, so just put
the prim ids into the vertices at tess stage, and skip prim assembly.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11000>
This fixes a possible problem if a non-indexed draw comes in first
in a new batch, then the batch might not emit the index buffer.
I'm unsure if we see this, I just spotted it trying to fix alacritty
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11705>
ifind_msb_rev was introduced in a5747f8ab3.
ifind_msb_rev guards against src0 being both 0 or -1 at the same time.
That is always true. This patch changes it to check for those values
individually.
Spotted from a compile warning.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: a5747f8ab3 (\"nir: add opcodes for *find_msb_rev and lowering\")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11630>
+ 9.31% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d
+ 2.36% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d
If the app never uses compute, then the compute bindings bit will always
be dirty causing these two paths never get shortcuts.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11699>
Add PCI IDs based in pci_ids/i965_pci_ids.h and move crocus before
iris in driver_map[].
This allows Xorg to load the crocus driver since iris would claim
the devices handled by crocus (because the i915 kernel driver is
used for all Intel devices) then fail during initialization.
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11694>
The intention here was to pass VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT to
select_memory_types() when requesting device local memory, or simply
pass 0 for the prime blit destination which should be in system memory.
Unfortunately, that meant we did (type.propertyFlags & 0) == 0 which
was vacuously true, causing us to not filter out device local types.
Fixes hybrid display of Vulkan apps on Intel TGL+DG1 systems.
Tested-by: Luis Felipe Strano Moraes <luis.strano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11680>
Even with the wrap mode forced to REPEAT, we get undefined results in
CelShading when the Y channel is unwritten since the beginning of the
program.
I dropped the coords==0 case in the process, since that's not possible and
made the 1D case confusing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11457>
As written this would require that the driver be built before we looked
at the option. This is wrong because it affects code outside of the
driver, it's in libGL's PCI ID table. This is sort of harmless for
crocus at the moment, but for iris you would need to build it in order
to remove it from the table; if you built just i965 and tried to run it
against gen9, the libGL you just built would direct the loader to the
iris driver you just didn't, and setup would fail, which is: goofy.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11655>
If the caller has asked for a coherent BO with snooping, and the kernel
fails to set it for whatever reason, we were happily returning them a
non-coherent buffer. This isn't what they wanted and could lead to
surprising results.
Better to simply fail the allocation. Probably.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
On integrated GPUs without LLC, we enable snooping when someone requests
coherency for a buffer. (With LLC, it's already coherent.)
For discrete GPUs...if someone requests coherency, we allocate the
buffer in SMEM and resort to WC maps rather than WB maps with CPU
caches enabled. There's no snooping to enable, and calling this ioctl
is nonsensical, and may fail.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
For images, variable data includes the format. For samplers, variable
data is used for OpenCL inline samplers. When converting a variable
from one to the other, zero out the data so we don't accidentally
interpret a converted image as an inline sampler.
Fixes: fa677c86 ("nir_lower_readonly_images_to_tex: Support non-CL semantics")
Acked-by: Enrico Galli <enrico.galli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11674>
This should be a subtract, not an add. The comment's proof is correct,
but the (wrong) expression we actually use isn't what it's in the
comment! Correct the discrepancy.
The lowering in nir_opt_algebraic was correctly typed.
Fixes: 272e927d0e ("nir/spirv: initial handling of OpenCL.std extension opcodes")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11671>
this is now a screen-based queue which can be triggered to serialize
cache updates, ensuring synchronization
the cache is on the program object, enabling incremental updates as well as
variant loading for an entire pipeline collection at once
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11595>
with tc enabled, we get genuine multidraws with valid drawids, so we can
update this to reflect the new capabilities...which are the same as the old
ones except that potentially some drivers can now do direct multidraws
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11662>
If the barrier tries to apply to memory that we can't express, just
don't apply the memory portion of the barrier. Similarly, if it tries
to apply a global memory barrier at invocation level, upgrade it to
thread-group.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11670>
We already apply start when setting the bits in writable_buffer, so
shifting the bits up by start just makes us apply the offset twice.
Caught by Coverity.
Fixes: 988d091720 ("gallium/u_threaded: clear valid buffer range only if it's not bound for write")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11635>
There are some cases using kgsl backend on linux that is still not usual
setup though, we need to consider too.
Regarding the timeline semaphore feature, we could implement it for
the kgsl backend in the future, and probalby it should be using the
existing code in tu_drm.
See #4738, #4907
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11488>
The destination of the upcoming blit (the old rsc struct that houses the
fresh BO) wouldn't have its ubwc cleared first, which if it got
unfortunate data in a recycled BO could lead to blit failures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11544>
The valid flag indicates whether the bo has had any data written to it.
Failure to swap it meant that if for some reason we fell back to SW
mappings during the blit from shadow, the PIPE_MAP_READ staging blit would
get dropped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11544>
The i915_hw_samplers atom already updated both samplers and maps, since
both samplers and maps depend on parts of both the gallium sampler state
and the sampler view. Just move the samplers+views atom down to the
bottom of the file for legibility, and delete the views-only one.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>
Instead of calling droid_create_image_ for every gralloc implementation,
create struct buffer_info which contains all required field for invoking
createImageFromDmaBufs2() and let the getters to fill this structure.
Since createImageFromDmaBufs2() is called now only once, the code looks
cleaner and more robust.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6045>
Bspec programming note metions that "Atomic messages are always forced
to "un-cacheable" in the L1 cache". We can make the L1 cache
un-cacheable and L3 with write-back policy.
v2: (Sagar Ghuge):
- Fix caching policy for atomic messages
- Fix simd exec size
v3: (Sagar Ghuge):
- Add atomic messages to brw_schedule_instructions
v4: (Jason Ekstrand):
- Rebase on lsc_msg_desc reworks
Co-authored-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
This puts the basic infrastructure in place for lowering logical
dataport messages to LSC messages. We start with the two most obvious
opcodes and add more in later patches.
v2 (Sagar Ghuge):
- Pass required params to message desc
- Remove duplicate mlen calculation
- Change commit message.
v3 (Jason Ekstrand):
- Drop TGM support
Co-authored-by: Jason Ekstrand <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
Xe-HPG comes with a massively reworked dataport. The new thing, called
Load/Store Cache or LSC, has a significantly improved interface.
Instead of bespoke messages for every case, there's basically one or two
messages with different bits to control things like address size, how
much data is read/written, etc. It's way nicer but also means we get to
rewrite all our dataport encoding/decoding code. This patch kicks off
the party with all of the new enums.
v2 (Jason Ekstrand, Mark Janes):
- Rename to LSC
v3 (Jason Ekstrand):
- Add numbers to all enums
Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
When vkCmdPushDescriptorSetKHR is used, the descriptor set is allocated
internally without belonging to any pool. Such descriptor set will be
visible on the GPU side because it's a part of the dynamic state stream,
but we still have to store its address in the array of descriptor sets.
Complements: 379b9bb7b0 ("anv: Support fetching descriptor addresses from push constants")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>
Currently the cache just deletes enough items when the cache is
full to make room for the new item being stored. This hasn't
been too much of a problem in practice but for things like running
piglit where we have thousands of unique shaders and all threads
being utilised we end up with a pretty big bottle neck.
With this change rather than just brute forcing our way to having
enough room for the new item, we instead grab 10% of the least
recently used items in the random directory we chose and delete
them all. This should only be around 0.04% of total cache items
but should hopefully releave some of the pressure on system calls
like fstatat().
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11523>
When the linux-dmabuf protocol is available, prefer it over the old
wl_drm protocol. Previously wl_drm was used when modifiers aren't
supported, however linux-dmabuf supports formats without modifiers too.
In this case, linux-dmabuf will send a DRM_FORMAT_MOD_INVALID modifier
for each supported format [1].
All of this allows compositors to better handle these buffers, getting a
DMA-BUF and implementing features like direct scan-out.
A similar logic has been implemented for EGL [2].
In this patch, we bind to linux-dmabuf even if the driver doesn't support
modifiers. In this case the formats advertised by the compositor will
still be added to the display->dmabuf.formats list.
In wsi_wl_image_init, drop the assertions that display->drm_wrapper and
display->dmabuf.wl_dmabuf can't be both present. If the driver doesn't
support modifiers, the modifier is already set to DRM_FORMAT_MOD_INVALID.
If the parent compositor doesn't support modifiers, the modifiers list
passed to wsi_create_native_image will be empty, and the common code
will ensure that the image's modifier is set to DRM_FORMAT_MOD_INVALID.
In wsi_wl_surface_create_swapchain, create the wl_proxy proxy if we've
bound to it earlier. Don't decide to create the proxy depending on the
number of supported modifiers.
[1]: fb9b2a8731
[2]: c376865f5e
Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4942>
This function has a switch which currently duplicates the format
handling logic.
Move this logic out of the switch.
This avoids repeating the same code for each supported format and
prepares the work for proper DRM_FORMAT_MOD_INVALID handling.
Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4942>
This fixes:
dEQP-GLES3.functional.fbo.completeness.renderable.texture.depth.depth_component_unsigned_short
as gallium will try an allocate a DS usage, but fallback to just
a sampling usage if that fails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11646>
Compiling with clang warns about an unused variable in
nir_lower_packing.
Tracking progress was added to nir_lower_packing in
adb157ddfd but the function
will ignore the progress from impl calls and always return
false.
This patch changes it to return the progress. It fixes the
warning and should enable validation calls in NIR_PASS when
progress is made.
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: adb157ddfd "nir: Return progress from nir_lower_64bit_pack()"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11615>
With discrete GPUs, we aren't able to change mapping modes after we've
created a buffer. This is a limitation of TTM. However, we already
have a buffer cache and it's pretty likely that stuff in any given
memzone will end up with just the one mapping type anyway so this
shouldn't have much of a cost.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11583>
Surely the compiler would sort that out, you would think. But no, my
debugoptimized build improves
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 runtime by 25%
on my SKL from this change.
This was the slowest test in the GLES31 tests on APL in CI, at 22s. And
yes, we were spending around half of our runtime in this function.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11631>
The Vulkan specification says: "If VkDescriptorSetAllocateInfo::pSetLayouts[i]
does not include a variable count descriptor binding, then
pDescriptorCounts[i] is ignored". The previous code triggered an assertion
in such cases, and this patch fixes it.
v2: removed the offending assertion that is now always satisfied and
reworded the commit message with a reference to Vulkan spec.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4992
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11576>
Assert in dest_regs() that dst_count == 1, since most users of it will
blow up if they encounter multiple destinations, and split out the core
of writes_gpr() so that we can easily make code using it multi-dst
aware.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>
These were a holdover from before the src/dst split and are no longer
necessary. Just don't create any dest registers for instructions that
never have a destination.
This has the side-effect that it becomes easier to replace uses of
dest_regs() with a per-register thing, once we start adding support for
multiple destinations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>
For some reason, this was implemented with the bulk of the compute
shader enablement, but this intrinsic is specific to subgroups and
thus was not really used. Also, its implementation was not correct,
since it was returning the element index within the subgroup, not
the subgroup index itself, which is the index of the batch in the
dispatch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>
If a shader has no defined version force_glsl_version was
previous ignored and the shader would default to 110. This updates
the code so that those shaders are forced to a new level also.
We reused the existing code to make sure a sensible value is set
for the version.
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11602>
AHardwareBuffer_Format is lossier than DRM_FORMAT_*, which ends up with
unable to resolve implementation defined format upon creating sampler
ycbcr conversion. So we now use DRM format as AHB external format.
An external format error return in vkCreateSamplerYcbcrConversion is
also removed here since that is already an invalid usage per spec
(partly because there is no proper error code to return here).
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11480>
Now these major driver failures are no longer hidden under -DDEBUG, and
would also work on android (you know, if you cared). We do want to
suppress logging for u_blitter shaders that fail to compile during
util_blitter_cache_all_shaders().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11617>
CrOS gralloc was missing support for GPU_DATA_BUFFER, which was only
fixed until recently. Now we can allcate properly.
This patch also removes a redundant TODO regarding image format list
support for AHB. vkGetPhysicalDeviceImageFormatProperties2 has already
checked the support for such though it only checks whether the optimal
tiling and the associated drm format modifier for the AHB image format
itself applies to the entire format list or not. Given the use case for
such combination is quite limited, we choose not to add new gralloc
support to force linear modifier as a fallback for wider coverage.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11501>
iris, i965, and anv define the PAGE_SIZE in anv_allocator and bufmgr
files. As on FreeBSD the page size is defined in machine/param.h that is
indirectly included by those files, we'd rather define it only when the
system is not FreeBSD to avoid compile errors.
v2: Changed the path in the comment to make clear that machine/params.h
is a FreeBSD system file.
Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11203>
On Linux ENODATA is defined but on BSD, and MacOSX ENOATTR is used
instead. Defined ENODATA to be ENOATTR when the system is not Linux.
v2: Replaced ENODATA and ENOATTR with -EFAULT that is exists everywhere
and added a comment (Ian Romanick)
Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11203>
The compiler *can* eventually chew through all the copy prop, constant
folding, and dead_cf necessary to use just our constant index, but we can
save a whole lot of hassle by chasing the MOVs up front and finding the
constant.
dEQP-VK.ubo.3_level_array.scalar.row_major_mat4.both goes from 2.0s to
1.6s on a release build (3.1s to 2.1s for a debug build like we use in CI).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11613>
If we've identified another use that isn't scheduled yet, we can break
right away rather than iterating through all the other uses. While this
could be optimized further, this simple change makes
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_ivec4 go
from 40 seconds to 1.9 seconds on a release build according to my
unscientific testing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11613>
Coverity complains that memset has no effect, because of size 0.
Size of BLEND_STATE struct is 0 on gfx [6, 7.5], so memset has
nothing to do there. This is of course harmless, but we can make
code simpler by replacing memset with an empty initializer list
and at the same time avoid a warning from Coverity.
CID: 1486015
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
gcc complains:
../src/intel/tools/aub_write.c: In function ‘populate_ppgtt_table’:
../src/intel/tools/aub_write.c:254:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
254 | (void *)(aub->phys_addrs_allocator++ << 12);
| ^
../src/intel/tools/aub_write.c:258:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
258 | i, (uint64_t)table->subtables[i]);
| ^
../src/intel/tools/aub_write.c:273:24: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
273 | (level == 1 ? (uint64_t)table->subtables[i] :
| ^
../src/intel/tools/aub_write.c: In function ‘ppgtt_lookup’:
../src/intel/tools/aub_write.c:346:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
346 | return (uint64_t)L1_table(ppgtt_addr)->subtables[L1_index(ppgtt_addr)];
| ^
../src/intel/tools/intel_sanitize_gpu.c: In function ‘bo_size’:
../src/intel/tools/intel_sanitize_gpu.c:99:15: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
99 | return e ? (uint64_t)e->data : UINT64_MAX;
| ^
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
In all cases both variables has a type of uint32_t, so multiplying
them will also generate uint32_t. The results of those multiplications
are used as uint64_t's, so Coverity thinks there might be integer
overflows here.
I don't think it's possible to hit them (query BOs should be relatively
small), but let's avoid those overflows.
CID: 1472820
CID: 1472821
CID: 1472822
CID: 1472824
CID: 1475934
CID: 1475927
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574>
MESA_SHADER_READ_PATH is handy but it's not usable in
all cases.
This commit allows to implement an alternative mechanism
without assuming too much about how it's done, nor where/how
the shaders are stored.
When this is enabled MESA_SHADER_DUMP_PATH,
MESA_SHADER_CAPTURE_PATH and MESA_GLSL env var handling is
disabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11621>
Apparently the quantization math isn't cheap.
This further reduces overhead by 2% for drawoverhead/8 textures.
The improvement is measured by looking at the sysprof percentage delta and
multiplying by 2 (because we have the frontend and gallium threads with
equal overhead, so the benefit is doubled compared to 1 thread).
Both per-sampler and per-unit lod bias values are quantized.
The difference in behavior is that both values are quantized separately
and then added up, instead of first added up and then quantized.
The worst case error is +- 1/256 in the reduced precision, i.e. off by one
in a fixed-point representation, which should be fine.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11339>
- pipe_sampler_state is added into gl_sampler_attrib.
- The border color field is redundant, so the non-gallium field is removed.
- Other GL fields are still tracked because of glGet.
- Some fields are not set by GL functions because they are always derived
from multiple states.
- The behavior in GL functions is the same as st_convert_sampler.
This reduces overhead by 2% for drawoverhead/8 textures, and more is going
to be done.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11339>
This is the same mechanism we already use for buffers. The code is mostly
copied from there. See the big comment for explanation.
This will be very effective when take_ownership is added into pipe_context
::set_sampler_views because that and this commit together will eliminate
atomics for sample views almost entirely.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11428>
This is the first time we see an application running out of mmap().
We essentially allocate too many batches (+65k) and end up not being
able to mmap them, at which point we can't mmap anything anymore and
things go sideways.
This change allocates bigger batch BOs as we grow an existing command
buffer. This drastically reduces the number of BOs we need to allocate
(the benchmark that reported the issue now reaches a max of ~630 BOs,
instead of reaching 65k and failing previously).
v2: Track the total batch size of command buffers (Jason)
Just give 0 for batch_len to i915 (Jason)
v3: Fix indentation (Jason)
v4: Drop uncessary reshuffling of error labels (Jason)
v5: Remove empty lines (Marcin)
v6: Limit BO growing to chunks of 16Mb (Jason)
v7: Add assert on initial size (Jason)
v8: Add define for max size (Jason)
v9: Fixup v7 assert for non softpin platforms (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4956
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11482>
There's no SPIR-V Capability associated, so check in the Execution
Mode. For now, don't keep track of whether a shader uses uniform
control flow in the shader_info, we can add that when/if a driver
actually need that information.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11476>
Some infinite loop cases were already covered by other
restrictions (e.g. if the loop had a body), but the case with a single
block in the loop body wasn't yet.
This prevents an infinite loop when optimizing the shader in
dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting2.3.2
and various others reconvergence tests.
Fixes: 0881e90c09 ("nir: Split ALU instructions in loops that read phis")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11476>
Move and rename warn_non_conformant_implementation() to common location
of src/vulkan/util/vk_util.c as vk_warn_non_conformant_implementation().
In freedreno/ci, move MESA_VK_IGNORE_CONFORMANCE_WARNING to common
location of .baremetal-deqp-test-freedreno-vk.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11563>
The full form for ldg.a/stg.a offset is:
g[reg_address + reg_offset << (imm_shift + 2) + imm_offset << 2]
where imm_shift is in [0, 3] and imm_offset is in [0, 3]
a6xx blob was found to produce a bit simplier offset calculations
for TES/TCS shaders in GTA V:
[c002000a_03c14215] ldg.a.f32 r2.z, g[r1.y+((r2.z+1)<<2)], 3;
[c0020004_01c14609] ldg.a.f32 r1.x, g[r1.y+((r1.x+3)<<2)], 1;
Our new syntax:
stg.a.u32 g[r2.x+(r1.x+1)<<2], r5.x, 1
stg.a.u32 g[r2.x+r1.x<<4+3<<2], r5.x, 1
ldg.a.f32 r1.w, g[r1.y+(r1.w+1)<<2], 3
ldg.a.f32 r1.w, g[r1.y+r1.w<<5+2<<2], 3
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11431>
Improves drawoverhead perf through Zink up to 260%
Before:
1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 1518
After:
1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change, 3981
This brings it close to Freedreno, which has around 4300.
In vkQuake vs params re-emission now occurs in 0.23% of draw calls.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11556>
Rework:
* Jordan: Handle prog_data->total_scratch==0 in iris_upload_compute_walker
* Jordan: Resolve iris_get_scratch_space conflict with e2c5ef6cd6
* Jordan: Rebase on 4256f7ed58. broken
* Ken: Mostly fixed the rebase
* Jordan: Fix two small compilation issues
* Jordan: Rebase on Ken's ("iris: Make a pin_scratch_space() helper")
* Lionel: Fix a few bugs with scratch handles
* Jason: Tidy the patch up a bit
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
XeHP adds support for a new surface type for scratch. It's similar to
SURFTYPE_STRBUF in that it's a 2D array-of-struct format but the one
key difference is that the U coordinate is computed automatically based
on the thread ID and only the V coordinate is provided in the dataport
message.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
This reverts commit 5cb043cf82.
While the numbers were impressive for drawoverhead, it comes at the cost
of additional flushes, which for gmem access (what we actually care about
most!) would greatly increase the actual cost to render. Also, gl_driver2
overhead is increased, probably due to spending time in the kernel for the
flushes.
drawoverhead's win came from the increased flushing causing the GPU to
start processing the buffers sooner on everything but test 1, which
already had some incremental flushing happening. That was certainly not
intended by the change.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11599>
When I added the build-rules for zink to the windows build, I
accidentally added it to .windows-test-rules instead of
.windows-build-rules. This seems to trigger a build-error if we trigger
*just* a test due to a zink-change, but not a build.
Hopefully this fixes the problems Mike has had with Zink CI recently.
Fixes: a426d7c264 ("ci/windows: enable msvc builds of zink")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11597>
MSVC's qsort_s behaves similarly to sort_r. Unfortunately, qsort_s's
compare function has the "context"/"args" as its first argument. BSD's
qsort_r has a different order than GNU's qsort_r. Finally, C11 added
qsort_s's which look like GNU's gsort_r.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10989>
This code was written but (rightfully) commented out, because it
referenced non-existing vulkan formats.
The correct vulkan analogs come in the form _PACK16 and _PACK32,
respectively, which have their component ordering in high->low bit
order. This is compatible with the DRM format ordering on little endian
systems, so we can just implement them all in the obvious way. On big
endian systems, the _PACKN formats have no analogs, because the
corresponding DRM formats are specified as always being little endian.
I implemented all of the formats I could, while excluding those that
don't map to vulkan at all (e.g. BGRA1010102), and commenting out the
ones that require an extra extension (e.g. ARGB4444) because they
probably need to be checked for extension presence first.
List slightly re-ordered to make it more neatly organized. Tested
working with the 2101010 and 565 variants. Was not able to test the 4444
or 1555 formats, but I verified the channel order was correct so they
should be working in theory.
Signed-off-by: Niklas Haas <git@haasn.xyz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9737>
tu_kgsl.c: tu_enumerate_devices closed fd previously closed by
tu_physical_device_init function.
Move out the fd closing from tu_physical_device_init function because
they do not belong to it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11561>
The way p_atomic_cmpxchg is implemented on Windows really wants us to
use integers instead of things like pointers. So let's use uintptr_t
here. It seems cleaner to use that than the value zero for the last
argument, because it shows the intent of the code more clearly.
Fixes: d80d9e1c93 ("zink: queue v3.0")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11424>
The second argument to debug_get_bool_option is a boolean, not a
pointer. Passing a NULL-pointer there triggers a warning, which we treat
as an error on MSVC:
---8<---
../src/gallium/auxiliary/driver_trace/tr_screen.c(1071): error C2220:
the following warning is treated as an error
../src/gallium/auxiliary/driver_trace/tr_screen.c(1071): warning C4047:
'function': 'bool' differs in levels of indirection from 'void *'
../src/gallium/auxiliary/driver_trace/tr_screen.c(1071): error C4024:
'debug_get_bool_option': different types for formal and actual parameter 2
---8<---
Fixes: c1270d4845 ("aux/trace: add screen deduplication for zink+lavapipe tracing")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11424>
Fixes:
dEQP-VK.api.info.format_properties.g8b8g8r8_422_unorm
dEQP-VK.api.info.format_properties.b8g8r8g8_422_unorm
and part of:
dEQP-VK.api.info.format_properties.g8_b8_r8_3plane_420_unorm
dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11562>
This gets rid of the awkward interface for isl_surf_get_ccs_surf where
we passed it two aux surfaces and it was supposed to fill out the second
one based on whether or not the first one already had stuff in it.
Instead, we now pass it three well-labled surfaces: surf,
hiz_or_mcs_surf, and ccs_surf which have obvious meanings. This does
mean that iris has to carry a bit of logic and we have to flip
parameters around in all the callers. But the resulting interface is
much cleaner.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
Whether or not a surface supports CCS on Tigerlake and later is
dependent not only on the main surface but also on the MCS or HiZ
surface, if any. We were doing some of these checks in
isl_get_ccs_surf based on the extra_aux parameter but not as many as we
probably should. In particular, we were really only checking HiZ
conditions and nothing for MCS. It also meant that, in spite of the
symmetry in names, the checks in isl_surf_get_ccs_surf were more
complete than in isl_surf_supports_ccs.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>
The blend state depends on wm_prog_data dual_src and it also
depends on the cbuf formats in can_emit_logic_op.
Dirty it in the correct places.
Fixes:
dEQP-GLES3.functional.fbo.invalidate*
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
I can't tell from a quick read whether this clip region is actually just
the bounding box so could be skipped entirely. But the old code never
destroyed it, which means we'd leak a couple hundred bytes on the X
server side for every SwapBuffers until the client dies of XID
exhaustion, which is somewhere north of 2GB for typical systems so you
may or may not just run out of memory first.
Create the region at swap time and stash it in the drawable state.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
Regions are not expensive objects on the server side, it's very slightly
cheaper to update an existing one than to create a new one, and we can
garbage collect them when the drawable is destroyed. Worse, XID reuse
bugs exist, so the more we can do to not churn through XIDs the better.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
The server starts off assuming the only XFIXES request the client might
known is FixesQueryVersion, and based on the version number the client
supplies it unlocks additional requests. If you forget to do this then
xcb_xfixes_create_region will throw BadRequest and you will be very
confused. libXfixes would hide this for you in extension setup but xcb
is not so forgiving.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
RA was manually fiddling with regs to copy over the parallel copy code,
which has to be done in a different way, but if we switch this all over
at once it shouldn't be a problem.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
Also change the indexing in ir3_delayslots, so it's finally sane! To do
this we also have to change foreach_ssa_src_n to index srcs instead of
regs, so that the indexing stays in sync.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
Instructions that operate on an array read the previous state of the
array, modify it, and write a new array, at least conceptually before
RA. Previously the same register specified the previous state and acted
as the new state, but this meant that it was both a source and
destination which meant that it was getting in the way of splitting up
sources and destinations. Break out the source into a separate register,
and use the new tied-src infrastructure to share code with a6xx atomics.
With this, there are basically no more special cases for arrays in RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
Previously this was hard-coded for a6xx atomic instructions. However
we'll need a way for array destinations to point to the source with the
previous value of the array when we split them up. This is conceptually
the same as tied source/destinations for a6xx atomics, except that array
writes sometimes won't have a previous value to point to. So move this
into the IR so that it can be more dynamic. As a bonus we can move the
knowledge of a6xx atomics out of RA, where it's out-of-place, and into
the a6xx-specific code that creates them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
Right now the accumulator-clearing move emitted by the generator for
Wa_14010017096 inherits the SWSB field from the previous instruction.
This can lead to redundant synchronization, or possibly more serious
issues if the previous instruction had a TGL_SBID_SET SWSB
synchronization mode. Take the SWSB synchronization information from
the IR.
Fixes: a27542c5dd ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
This is unlikely to have had any negative side effect on the original
TGL, but will lead to issues on XeHP+ if the software scoreboard pass
isn't able to synchronize the accumulator writes.
Fixes: a27542c5dd ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
In cases where an in-order instruction is overwriting a register
previously read by another in-order instruction, drop the dependency
iff the previous read is guaranteed to have occurred from the same
in-order pipeline. This should only have an effect on XeHP+ since
previous Xe platforms only had one in-order FPU pipeline.
The previous workaround we were using for this treated all ordered
read dependencies as write dependencies to avoid noise from our
simulation environment. Relative to our previous workaround this
improves performance of GFXBench5 gl_tess by ~7% on a DG2 system
among other single-digit percentual FPS improvements.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
The hardware fails to provide the expected data coherency guarantees
for accumulator registers when accessed from multiple FPU pipelines.
Fix this by tracking implicit accumulator accesses just like we do for
regular GRF registers, but instead of adding synchronization
annotations for any dependency we only do it for dependencies with a
pipeline mismatch, since the hardware should be able to guarantee
proper synchronization for matching pipelines.
Note that this workaround handles RaW and WaW dependencies in addition
to the WaR dependencies described in the hardware bug report even
though cross-pipeline RaW accumulator dependencies should be extremely
rare, since chances are the hardware will also hang if we ever hit
such a condition. This only affects XeHP+, since all FPU instructions
are executed as a single in-order pipeline on earlier Xe platforms.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
This change reduces the precision of the scoreboard data structure for
accumulator registers, because the rules determining the aliasing of
accumulator registers are non-trivial and poorly documented (e.g. acc0
overlaps the storage of acc1 when the former is accessed with an
integer type). We could implement those rules but it wouldn't have
any practical benefit since we currently only use acc0-1, and for the
most part we can rely on the hardware's accumulator dependency
tracking. Instead make our lives easier by representing it as a
single register.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
this is another prim type bitmask which will trigger automatic draw rewriting
to a direct draw any time a prim-restart draw occurs with a prim type that is
not supported by the driver for prim restart, even if that prim type is supported
for normal drawing
the default is set to all prim types to preserve existing functionality, and PrimitiveRestartForPatches
is now explicitly set to false because no driver supports it
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10973>
this is a bit more work, as the primitive restart needs to be rewritten into a multidraw,
then the multidraw converted to the new primitive type and serialized back into a
single draw
detection is handled using a new primconvert config member, which is set to the full
primtype mask by default for compatibility with existing drivers
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10973>
Upon looking at caching the raytracing shader (in particular the
trampoline one) I kind of got afraid that some of the keys used for
blorp would end up matching other keys. This is because blorp keys are
fairly simple. There is no SPIRV module hash included.
This change includes a "blorp" string at the beginning of the queue to
ensure we don't collide with other keys.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
This allows us to convert a 64-bit address to an anv_address which is
useful for working with device addresses.
v2: switch to int64_t to keep state pool relative relocation working
on non-softpin platforms
v3: Update assert to reflect relative offsets (Jason)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
These don't necessarily go in any group but are required for dispatch to
work properly. The trampoline is a compute shader that is the initial
start point for the trace. It's in charge of invoking the actual
ray-gen shader. The trivial return shader is used whenever another
shader is missing and it does no work except the minimum required to do
a stack return.
v2: Rebase on upstream changes (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
This doesn't look too different from other compile functions we have in
anv_pipeline.c. The primary difference is that ray-tracing pipelines
have this weird two-stage thing where you have "stages" which are
individual shaders and "groups" which are sort of mini pipelines that
are used to handle hits. For any given ray intersection, only the hit
and intersection shaders from the same group get used together. You
can't have an intersection shader from group A used with an any-hit from
group B. This results in a weird two-step compile.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
Instead of depending on the driver to compile each resume shader
separately, we compile them all in one go in the back-end and build an
SBT as part of the shader program. Shader relocs are used to make the
entries in the SBT point point to the correct resume shader.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
now that submission is serialized better, it's not actually the resource that should be
tagged for scanout sync, it's the batch state, as multiple contexts might reuse the same
resource, thus requiring synchronization on every submit
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11437>
this uses a pointer to a batch state substruct for timeline tracking,
which provides a few nice benefits:
* explicit ability to detect unflushed batches (even on other contexts)
* the context doesn't need to have a "current" timeline id
* timeline (batch) ids can be distributed during submit, not when recording begins
* an abstracted api which can be more easily changed under the hood
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11437>
instead of storing separate batch_id values onto the tc fence for matching:
* use a fence pointer on the main context to indicate the current deferred fence
* add a monotonic counter to each batch state which double-increments on each use,
thereby enabling direct determination by the tc fence as to whether this is the same
batch state it was created with
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11437>
If we're remapping RGBA from the shader into dst channels, we also need to
remap the blend constant color. The previous static mapping only worked
for ARGB cbufs, but we get ABGR in surfaceless deqp.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11512>
Fixes: c9baccb5
For certain player which doesn't implement st_rps_bits, or when st_rps_bits
is set to 0 (e.g. it doesn't have rps explicitly defined in slice header),
we don't set st_rps_bits and the related flag, since we don't skip parsing
the rps structure in these cases.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11432>
The resource_busy() hook was having to check the batch cache for usage of
the resource, since TC didn't know how long our driver would. By
committing to calling the tc_driver_internal_flush_notify() hook on
non-deferred flushes, TC keeps track of which buffers have been used but
not flushed and considers them busy, saving us needing to look in the BC
(which we won't be able to do once we move it to being per-context).
drawoverhead test results (all numbers are throughput, n=5):
1, DrawElements ( 1 VBO| 0 UBO| 0 ) w/ no state change: -4.94214% +/- 2.45047%
7, DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ vertex attrib change: 48.3992% +/- 5.02827%
8, DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ 1 texture change: 26.0974% +/- 1.14932%
9, DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ 8 textures change: 12.6963% +/- 3.01077%
17, DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ 8 UBOs change: 54.3846% +/- 35.0049%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11513>
The Navi 1x NGG hardware can hang in certain conditions when
not every wave launched before s_sendmsg(GS_ALLOC_REQ).
As a workaround, to ensure this never happens, let's emit a
workgroup barrier at the beginning of NGG VS and TES.
Note that NGG GS already has a workgroup barrier so it doesn't
need this.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10837>
Navi 1x GPUs have an issue: they can hang when the output vertex
and primitive counts are zero. The workaround is exporting a dummy
triangle.
This commit changes the dummy triangle's vertex so its positions
are all NaN. This should make sure the triangle is never rendered.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10837>
During dEQP runs for radv, I see a lot of warnings like,
ERROR - dEQP error: SPIR-V WARNING:
ERROR - dEQP error: In file ../src/compiler/spirv/spirv_to_nir.c:1073
ERROR - dEQP error: Decoration not allowed on struct members: SpvDecorationRestrict
ERROR - dEQP error: 408 bytes into the SPIR-V binary
This fails jobs on Gitlab, due to,
Job's log exceeded limit of 4194304 bytes.
Job execution will continue but no more output will be collected.
Since it doesn't seem feasible right now to fix the many shaders in
the VK-CTS triggering this warning, add an environment toggle that
allows test runners to only see the level of commentary they want.
v2 from Martin:
- Add my SoB
v3 from Martin:
- fix the indentation (suggested by Eric)
- put the declarations at the top of the function
v4 from Martin:
- make vtn_default_log_level() static (Marcin)
- cache the default level in vtn_log (Marcin)
- move vtn_log_level_strings inside vtn_default_log_level()
- Fix the build issue on MSC
Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Andres Gomez <agomez@igalia.com>
Acked-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11491>
We follow the same approach that v3d. We compile the files that
depends on the version several times, passing a different version each
time. We link all those per-version libs on the main library.
Note that right now we only support version == 42, so the array of
supported versions is one-sized.
Also note that although we were doing a previous work to split
hw-version dependant code from general code, this is the first commit
that only inject the current V3D_VERSION on the former.
We have two cases where we hardcode the V3D_VERSION (as a full
wrapping would be an overkill) that we need to include here to avoid
warnings/errors if we do that before or after.
Having some exceptions also happens on v3d. As we are here we add some
comment on v3d clarifying that.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11310>
cl_packet_length depends on the specific hw generation packets, so it
is can't be included directly by main header.
The straight forward solution would be to allocate them dynamically,
based on the current generation. That ended to be complex and
messy. Also, even if that change between hw versions, it will not
change significantly.
So we just add some definition with the size of the packets we
prepack. We just need to be careful that this needs to be the maximum
value considering all the versions supported.
Note that on Opengl v3d does something similar, using hardcoded
values, but without a define, neither a runtime check.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11310>
As part of this, we get rid of the v3dv_xxx_descriptor structs to
v3dv_descriptor. The main reason is that in order to support several
versions, we would need to define them several times. Also, they were
somewhat an overkill even before, as their main advantage was getting
the offset for each data on the combined case. That functionality is
replaced with some new helpers.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11310>
The idea would be to move all the code that uses cl_emit,
cl_emit_with_prepack, v3dx_pack, and any enum/structure definition
defined on the v3d pack headers.
All those methods would be defined on v3dvx_private (that would be the
equivalent to v3dx_context.h on v3d).
This commit includes the definition of v3dX for the current version
supported (42), a function calling wrapper, and the move for v3dv_queue
methods as a reference.
About the function calling wrapper, I took the idea from anv. We don't
have on v3d, but we added it because we foresee that we will need that
functionality more often. So without that macro, in order to call the
correct version of the method from the general code we would need to
do like we do on v3d, and doing something like this:
if (devinfo->ver >= 42)
return v3d42_pack_sampler_state(sampler, pCreateInfo);
else
return v3d33_pack_sampler_state(sampler, pCreateInfo);
So with the macro we can just do this:
v3dv_X(device, pack_sampler_state)(sampler, pCreateInfo).
Note that as mentioned, that is to be used on the general code, so a
runtime decision. If we are already on version-dependant code (so at
v3dx_queue for example) we just use v3dX, as at that point is a build
time decision.
Also, fwiw, I don't like too much the name of that macro, but I was
not able to think on a better one.
v2: merge job_emit_noop_bin and job_emit_noop_render (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11310>
Instead of having different layouts which might complicate things when
some registers are missing, hardcode the SELECT and SELECT1 registers
into separate arrays.
The SELECT registers are "legacy" counters, while the SELECT1 registers
are SPM counters.
This is more verbose and emit more UCONFIG registers, but emitting the
SELECT registers is now much simpler and it seems less error prone.
This will also help emitting the SPM configuration.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11186>
This makes dEQP-VK.api.version_check.entry_points pass and matches how
other drivers are handling this case. We do not support the feature but
still need to provide a dummy entrypoint.
v2: throw error if/when called (Jason)
Fixes: 0d031d1da3 ("anv: toggle on VK_EXT_extended_dynamic_state2")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11503>
mesa/mesa@2dcc9c7f54 from mesa/mesa!6639 added a resource_get_param
hook for llvmpipe, which was nice since it gave lavapipe more features.
One of those features was not exporting llvmpipe textures, so those
parts were stubbed out and landed in an assert(0).
This completely broke kms_swrast (llvmpipe+GBM) on non-release builds,
since that definitely does need to export llvmpipe textures.
The query codepath which caused this explosion does fall back to
resource_get_handle() - which is how it worked previously - but not all
callers do this, so just do what all other drivers implementing
resource_get_param() do and open-code the translation.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reported-by: Jonas Ådahl <jadahl@gmail.com>
Tested-by: Jonas Ådahl <jadahl@gmail.com>
Fixes: 2dcc9c7f54 ("llvmpipe: add resource get param support.")
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6639
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11504>
The previous implementation had several issues:
- It wasn't checking all the conditions necessary for "this blit updates
the whole surface", like PIPE_MASK_Z but not S on a depth/stencil
buffer.
- It would reset the previous batchbuffer, even if that batch had side
effects on other buffers.
- The layering was painful to follow and made any recursion extra
dangerous.
Now, we use a more conservative test (enough for the resource shadowing
case) and just invalidate the buffer up front, which should have the right
logic for discarding drawing to that resource.
I found I had to add fd_bc_flush_writer() to the end of fd_blitter_blit()
-- a flush was happening at fb state restore time when the discard flag
was set, and losing that flush breaks
dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11455>
The block only loads input VGPRs from LDS, and the next block uses them.
The entering condition is the same, even though the second block is
the next shader part beginning with the prolog.
Simply move the VGPR loads into the prolog.
This decreases the shader code size by 12 bytes.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11102>
Extend the special handling of return types to also include pointer
type array list elements, so we ignore the initial "name" of the
element until we know a better type for them. This improves the type
"detection" of such pointer array elements when parsing the logs
with dump.py / tracediff.sh
Related to Mesa issue #4609
Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11492>
Long ago, the semantics of bcsel were such that it took a single boolean
value and selected between whole vectors. These days, it takes a vector
boolean with the assumption that if you want the old behavior you can
just use a .xxxx swizzle. There currently are no opcodes which use a
output_size of 0 but have a scalar or fixed-vector input. Let's
disallow it for now to force us to think through the semantics again if
this ever comes up as something someone actually wants.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
This thing is entirely opt-in wrt caring about it when writing to
a file anyway. Since we also lock the two at the same time and they
have an 1-1 relation we can just lock one of the two files. Saves
some syscalls.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
This avoids all locks for reads and using lock only while actually
writing.
This is enabled by doing two things:
1) Reading the index incrementally. This way we get new entries
written by other processes and do not write duplicate entries.
2) Taking the lock only during writes, and applying the incremental
read while holding the lock so we always append to the actual end of the file.
Fixes: eca6bb9540 ("util/fossilize_db: add basic fossilize db util to read/write shader caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
Function mincore expects a pointer of type char* but we use an unsigned
char* instead generating signedness related warnings.
v2: Made the fix FreeBSD specific because the type is unsigned char* for
Linux and char* for FreeBSD. (Adam Jackson)
v3: We'd rather cast the param to (void*) to avoid warnings in all
systems (Adam Jackson)
Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11298>
The algorithm used for the BVH:
1) first create 1 leaf per primitive (triangle/aabb/instance)
2) Then create internal layers from the bottom up until we are left with
1 node in the top layer. Node i in the layer will have children
(i*4+0) ... (i*4+3) in the previous layer.
This results in a very naive algorithm but it is also very simple to implement.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
The idea is that the tests will spend *some* time stalling waiting to
read back results from the GPU. So use a # of jobs that is slightly
more than the # of CPUs to keep the CPUs more busy.
Locally this is dropping a bit more than a minute off a parallel
deqp-gles31 run, so turn it on across the board for a6xx.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
I didn't feel like rewriting ir3_shader_disasm() off of FILE *s, so use
the same trick as the disasm_info path above to write to memory and then
hand the multi-line blob off to mesa_log.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
This means you can get dumps on android, and output on Linux goes to
stderr. However, this does mean that on Linux the output goes from
looking like:
AFTER: ir3_legalize:
block3276208368 {
0000:0001:002: cov.u32s16 hr2.x, c2.x
0000:0002:002: mov.u32u32 r0.x, c0.x
[...]
to:
MESA: info: AFTER: ir3_legalize:
MESA: info: block3405271904 {
MESA: info: 0000:0001:002: cov.u32s16 hr2.x, c2.x
MESA: info: 0000:0002:002: mov.u32u32 r0.x, c0.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Often disassemblers and things in our drivers want to be able to
incrementally printf together a line, but that gets in the way of
Android's logging that wants to see a whole line all at once. Make a
little wrapper to do the ralloc_asprintf_rewrite_tail() and flushing lines
as they appear.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
This commit mostly just adds the framework required to scrape
documentation out of the ISL sources and headers. The method chosen
here is a combination of doxygen and breathe (a sphinx extension for
doxygen integration). I'll freely admit that doxygen is pretty terrible
but it seems like the best option we have available to us today.
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
If compressed rendering is only used for the depth aspect of a
depth/stencil image, stencil might also be compressed and it needs
to be decompressed. This only happens for non-TC compatible images.
As long as the driver needs to decompress the depth aspect, I don't
think that decompressing the stencil aspect introduces extra cost.
Fixes dEQP-VK.renderpass*late_fragment_tests*.d32_sfloat_s8_uint for
chips that don't support TC-compat HTILE.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
From the Vulkan spec 1.2.181:
"The difference of the size of memory and memoryOffset must be
greater than or equal to the size member of the
VkMemoryRequirements structure returned from a call to
vkGetImageMemoryRequirements with the same image"
This is invalid usage but adding a check in the driver is safe and
might avoid spurious failures.
This is a workaround for the inventory GPU hang with Cyberpunk 2077
which is actually a game bug. Luckily the game handles this error
gracefully.
Since the addrlib change from March, addrlib now selects a better
swizzle mode (4KB instead of 64KB) which reduces image size. Though,
the game assumes that an image with 2 mips is always smaller than the
same image but with 6 mips. This is not always true if the swizzle mode
is different. Then, it creates a D312 heap that is too small for the 2
mips image and the GPU hang with a memory violation, ugh...
Note that next vkd3d-proton release should also reject this but
fixing both sides is fine.
Cc: 21.1 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4823
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4593
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11448>
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member min is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member max is not initialized in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11351>
This fixes ~10% of the GLES2 failures thanks to having a better compiler,
though in some cases we get some new compile fails due to instr count or
uniform count. We still have to do NIR-to-TGSI because the NIR gallivm
draw path isn't ready for non-native-integer NIR code, and st/mesa treats
native-integer as a screen property instead of a stage property.
Other than the noted regressions in the xfails, for
dEQP-GLES2.functional.uniform_api.random.74: compile fail changes reasons
triggering an aassertion instead of drawing magenta.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
limit==0 is the signal for "don't peephole anything but a move that will
be optimized aways." limit > 0 is "up to N alu instructions may be moved
out." nir-to-tgsi uses ~0 as the indicator of "No, we really need to
eliminate all if instructions" on hardware like i915 that doesn't have
control flow.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
We need to make get it updated after we may have nir_instr_remove()d an
instruction, and when we cross blocks. This didn't really matter before
because the only builder usage was idiv, which other users of
lower_int_to_float were probably never hitting.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
It's not a required feature of the GL2.1 or GLES2, and you really don't
want to be doing SW VS access of the write-combined texture data. Also,
avoids memory corruption in deqp:
Test case 'dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_nearest_linear_repeat'..
Mesa: User error: GL_INVALID_ENUM in glGetIntegerv(pname=GL_MAJOR_VERSION)
Fail (Image comparison failed)
Test case 'dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_always'..
==559181== Invalid read of size 4
==559181== at 0x641E8D0: i915_drm_buffer_unmap (i915_drm_buffer.c:204)
==559181== by 0x64151EB: i915_cleanup_vertex_sampling (i915_state.c:449)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:134)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:55)
==559181== by 0x61367B1: cso_draw_vbo (cso_context.c:1524)
[...]
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
This patch only enables the below VkFormat:
- VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
This patch ensures the proper behavior of the below APIs:
- vkGetPhysicalDeviceFormatProperties2
- vkGetPhysicalDeviceImageFormatProperties2
- vkCreateImage
- vkGetImageSubresourceLayout
- vkGetImageDrmFormatModifierPropertiesEXT
- vkGetImageMemoryRequirements
- vkGetImageMemoryRequirements2
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Add initial multi-planar format support on the images with modifiers:
- With aux usage,
- Format plane count must be 1.
- Memory plane count must be 2.
- Without aux usage,
- Each format plane must map to a distinct memory plane.
For the other cases, currently there is no way to properly map memory
planes to format planes and aux planes due to the lack of defined ABI
for external multi-planar images.
This patch doesn't include some potentially supported cases like all
format planes mapping to a single memory plane, additional refactoring
is needed to workaround explicit base offset + ANV_OFFSET_IMPLICIT.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
When storing depth- or stencil-only texture data that has been packed into
a depth/stencil texture, the tex store gets PIPE_MAP_READ added onto it
since the other channel will get ORed into the incoming data, but
sometimes we know that the other component is undefined because the whole
texture is either fresh or just invalidated.
Cleans up a confusing extra blit in a dEQP case I've been debugging, and
should be less work for dEQP CI.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
We use the same key in autotune to track historical data about a given
framebuffer state, to inform the decision about using gmem vs sysmem
rendering. Which means we need the key to stick around during the
flush, even if the batch is removed from the batch-cache before the
flush.
Fixes: 507f701d9e ("freedreno: Fix batch flush race condition")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11450>
When an OpBranchConditional that had two equal branches was parsed, we
were treating it as a regular OpBranch. However this doesn't work
well when there's an associated OpSelectionMerge. We ended up
skipping marking the merge block as such, and depending on what was
inside the construct we would end up trying to process the block
twice.
Fix this by keeping the vtn_if around, but when emitting NIR identify
the two equal branch case.
Fixes: 9c2a11430e ("spirv: Rewrite CFG construction")
Closes: #3786, #4580
Reviewed-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9297>
Read directly from the instruction getting spilt. Otherwise a fill
will be inserted before the spill writing the value, so the
instruction reading the spilt value gets garbage data.
Use the bundle_id to check if the instructions are in the same bundle.
Insert a move instruction, as the spill needs the value in a LD/ST
register such as AL0, while the ALU instruction reading the value
needs it in a work register such as R0.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4857
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
Now that we have the rest of format "casting" sharp edges sorted, flip
on copy_image and gles32.
Unfortunately it adds back to piglit xfails (but at least that is more
than offset by my previous round of piglit fixes, and these are pretty
much all things we know had issues based on corresponding nv_copy_image
tests).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
We have some logic to detect when u_blitter generated draws overwrite
the entire render-target, so we know we can discard anything previous.
But some blits (like multi-sample) do multiple draws. We don't want to
discard the earlier draws from the same blit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
The invalidate would take it out of the bc tracking, so you could go
allocate a new batch->idx matching this one, while this one is still in
the bc using that idx.
You can't generate any new rendering with the ctx's old batches at this
point, anyway, so just flush for simplicity.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
It wasn't checking that the transfer map would definitely overwrite all of
the data being initialized by the back blit, and if we knew that it
would then the caller would have provided PIPE_MAP_DISCARD_WHOLE_RESOURCE.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
We take references under the lock, but then accessed the lock-requiring
batch_cache structure without holding the lock. The batches wouldn't get
freed and removed from their slots until the last ref goes away so it was
safe (other than the assert at the end), but writing the simple code is
shorter and requires fewer assumptions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
When the system doesn't have enough memory, GNOME Shell may be crashed
by iris:
gnome-shell[1161]: iris: Failed to submit batchbuffer: Cannot allocate memory
gnome-shell[1161]: GNOME Shell crashed with signal 6
So don't abort() when kernel can't allocate memory to avoid crashing the
entire desktop.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11178>
Instead of spawning 4 threads when the cache is created,
spawn 1 and let u_queue grow the number of threads if
needed.
I wrote this patch because when running piglit's quick_shader
profile I had lots of samples in disk cache threads - mostly
in native_queued_spin_lock_slowpath kernel function.
Since these tests shouldn't really stress the cache, I assumed
it was caused only by thread creations.
After writing the patch and redoing the measurement, I got an
improvement but I still more hits in the same function for
shader_runner:$disk0 thread so something was wrong.
After digging more, I found out that my shader cache index was
corrupted: the on-disk size was 29MB but the index reported it
was way more than 1GB. So each disk cache thread was spending
a lot of time trying to evict files. Given that my cache had
a really low count of files, the LRU method based on randomly
generating subfolder names failed, so evicting was very slow.
Now that my cache index is fixed, the disk cache threads are
mostly idle but I still think it makes sense to grow the
number of threads instead of spawning 4 at the program start.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
This flag allow to create a single thread initially, but set
max_thread to the request thread count.
If the queue is full and num_threads is lower than max_threads,
we spawn a new thread to help process the queue faster.
This avoid creating N threads at queue creation time.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Commit 24342e499b changed how primitive
topology is handled on Gfx8+ but missed updating the Gfx7.x code.
As a result, tests which previously used topologies like PATCHLIST_3
instead started using bogus ones like LINESTRIP_ADJ. This caused a
GPU hangs in a bunch of Vulkan conformance tests involving tessellation.
This fixes those hangs.
Fixes: 24342e499b ("anv: fix dynamic primitive topology for tess")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11434>
GL requires explicit glMemoryBarrier calls for shader synchronization
and only calls that map/copy buffers get implicit sync, so we don't actually
need barriers for any of these cases, only the state needs to be updated
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11393>
With array registers, there are two num's we care about:
1. The base num that the whole array starts at (->array.base)
2. The num that the instruction uses, plus possibly an indirect offset
(->num or ->array.offset)
For parallel copies we always copy the whole array, so (2) is irrelevant
here. For phis and parallel copies inserted for phis, we used
assign_reg() which assigned ->array.base, but we forgot about this when
constructing our own parallel copies for live range splitting, just
setting ->num instead. The parallel copy lowering was also inconsistent
here, using ra_reg_get_num() (which looks at ->array.base for arrays)
for sources but looking at ->num directly for destinations. This makes
everything use ->array.base consistently.
While we're here, make sure to remove IR3_REG_SSA from liveout copies to
make sure printing works correctly.
Fixes: 0ffcb19 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
Normally something with IR3_REG_ARRAY doesn't have a register assigned,
but we keep IR3_REG_ARRAY for parallel copies after RA because we need
to know the appropriate size. We want to see the register assigned for
these when printing the RA result before parallel copies are lowered.
The register is in ->array.base in this case, so initialize it to
INVALID_REG and print ->array.base if it's been assigned to something,
similar to ->num in the normal case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
Buffers are created without a format in Vulkan, and we always pass in
R8_UNORM for them in Gallium. It's the view-formats we should have
checked, if anything.
But that's orthogonal to this. We shoudn't keep checking R8_UNORM
capabilities for buffers, all it's going to do is trigger asserts.
Fixes: 00dc0036b ("zink: flatten out buffer creation usage flags codepath")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11416>
I'm not even going to pretend that I grok this code, but since we take
the abs value, it's pretty obvious that we meant to use a signed value
here. So let's cast the two operands to int before we subtract.
This was noticed by the following clang warning:
---8<---
../src/gallium/drivers/zink/zink_context.c:3284:14: warning: taking the
absolute value of unsigned type 'unsigned int' has no effect
[-Wabsolute-value]
last = abs(reads - writes) > UINT32_MAX / 2 ? MIN2(reads, writes) : MAX2(reads, writes);
^
---8<---
Fixes: 0c1fe392e8 ("zink: implement a tc is_resource_busy hook")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11421>
With nir I encountered the case where the same value can be written to from
multiple surface operations. This caused some weird messups with the unions
as the def.rewrite operations caused unrelated instructions to get new their
value replaced as well.
In order to replace def.rewrite, we have to create a new temp value, write
to that one instead and move to the original value.
Fixes: 869e32593a ("gm107/ir: fix loading z offset for layered 3d image bindings")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11053>
This is required by GL. Doing this even when the backend driver does not
support it leads to creating attachments which are not renderable. This
is not ideal, but does pass tests. This covers scenarios such as missing
MSAA for 128-bit formats on Sandybridge, and missing 8x MSAA on 128-bit
formats on NVIDIA Tesla generation boards.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11372>
This has two steps. First, for each range we look at the memory object
and see if it actually needs flushing before we start throwing CLFLUSH
instructions. Second, we look at the whole list of types on device
initialization and decide whether or not we need CLFLUSH at all. The
first part should speed up atom chips a bit since we're currently
CLFLUSHing everything even when we don't need to. The second isn't
needed on most of today's parts because we base it on !has_llc but it is
needed for discrete parts. It's also over-all cleaner.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11364>
As we move the batch cache from screen to context, it cleans up the diff a
ton to separate this mechanical change out, and makes the API generally
more consistent (since you usually have to pass the ctx anyway).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11368>
This prevents problems when some CPUs are offline. In a four CPU
system, if CPUs 1 and 2 are offline, the cache topology code would
only examine CPUs 0 and 1... giving incorrect information.
The types are changed to int16_t so that the offset of num_L3_caches
does not change. This triggered a STATIC_ASSERT failure:
STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 5 * sizeof(uint32_t));
I'm assuming there's some assembly code or something that depends on
this offset, and I don't feel like messing with it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11228>
In the current code, this prevents a very unlikely corner case. More
importantly, it should prevent the next commit from breaking the
universe.
Imagine a system with 64 CPUs configured, but first 32 CPUs are offline.
_SC_NPROCESSORS_CONF will return 32. All of the surrounding code will
interpret this as meaning CPUs 0 through 31, but all of those CPUs are
offline. Nothing good can happen then.
The problem cases require systems with more than 32 CPUs because
util_cpu_caps.num_cpu_mask_bits is always rounded up to a multiple of
32.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11228>
This patch refactors to use vn_Import*FdKHR for Android WSI native sync
fence import when globalFencing is supported. Currently there's no perf
win from this, but will move the composer release fence waiting to the
GPU device side automatically when the entire Venus fencing support is
improved.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11342>
Normally when we shadow a resource (whether it is changing the modifier
or not) we do not need to flush existing batches, since they reference
the original version of the resource. There is a special case for
resources that are referenced by a batches framebuffer state, because
this state is emitted when the batch is flushed. Because of this, we
need those batches to be flushed before we shadow the resource.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11371>
Normally when demotion to uncompressed is required, it is handled when
various state is attached (sampler-view, framebuffer, etc). But in this
one path into u_blitter we need to handle it up front, to avoid
recursing back into u_blitter for a decompress blit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11371>
Use a single set and ensure dominance by checking after a equivalent
instruction is found.
Besides removing the need to copy a set, this also lets us resize the set
at the start of the pass in the next commit.
ministat (CSE only):
Difference at 95.0% confidence
-984.956 +/- 28.8559
-6.90075% +/- 0.190231%
(Student's t, pooled s = 26.9052)
ministat (entire run):
Difference at 95.0% confidence
-1246.1 +/- 257.253
-0.998972% +/- 0.205094%
(Student's t, pooled s = 239.863)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6390>
On Gfx12+, flushing tile cache ensures color/depth values are
globally visible, but that's expensive. Most operations only
need values to be GT-visible which can be achieved with depth
or rt flush. Remove a bunch of unnecessary Tile Cache flushes.
Fast clears and slow depth clears still require Tile Cache flush.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
Whilst we want to reuse the same init and job environment for LAVA and
bare-metal, LAVA needs to additionally inject wget and tar jobs, so we
can actually get our per-job environment, as the rootfs we run in is
just the container-generated base rootfs.
Split the init script into two stages, with the first stage doing very
base bringup of devices and networking, and the second stage setting the
job environment and running the jobs.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Martin Peres <martin.peres@mupuf.org>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
Determine if a given shader write the same constant value to its output
if a specific input texture is replaced by constant load.
It's done by checking if the store_output intrinsics only depends on
constant and a texture. If it's true, the given texture is replaced by
a constant load in cloned shader and this clone is optimized.
Then the output is checked (= is it constant or not).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
This allows to implement custom draw_vbo code-path without
touching si_draw_vbo.
As an example, skipped all draw calls with an odd new_draws
could be done like this:
void mywrapper(...) {
if (new_draws % 2)
return;
return sctx->real_draw_vbo(...);
}
if (some_condition_is_met)
si_install_draw_wrapper(sctx, mywrapper);
Instead of having to add the "if ()" condition inside si_draw_vbo.
Note that a single wrapper may be installed so care must be taken
to not override an existing wrapper.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
To make sure the index of global bo table in drm_msm_gem_submit_cmd is
valid at actual submit time.
v1. Move the entry_count calculation into the submit request creation
function.
Fixes: #4877
Fixes: 3f229e34 ("turnip: Implement VK_KHR_timeline_semaphore.")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11260>
This is a port of c111e9099c from iris to
crocus.
Calling SET_TILING on a DMA buffer with the gen12 CCS modifier can fail
unnecessarily. The main surface in the BO is Y-tiled, but the CCS portion is
linear and can have a stride that's not a multiple of 128B. Because SET_TILING
is called on the CCS plane with I915_TILING_Y, the ioctl will sometimes reject
the stride.
SET_TILING was originally used in b6d45e7f74 to
fix an assertion failure in iris_resource_from_handle. Assigning the BO's
tiling_mode field is sufficient to avoid the failure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
We can't invalidate the range if a buffer is bound for write because we
would need to add the range that is bound, which we don't track.
This fixes buffer mappings incorrectly promoted to unsynchronized because
the valid range was cleared while the buffers were bound for write.
It also clears the valid range if the invalidation is allowed but skipped.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11335>
The test involves timestamping to figure out how long a swap actually
takes, but if anything ends up rescheduling the process you can end up
spuriously failing. I could easily reproduce flakiness by just running a
loop accessing the filesystem in parallel with a loop running the test.
So, it's certainly not usable on a CI system with other piglit tests
running in parallel, and we don't want to run it if it's going to just
produce flake noise.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
They're too slow to run in CI even on non-tiled renderers, they don't
block conformance (unless you crash), and provide unreliable warning
results unless you isolate them from other activity on the system.
This means that the following jobs now skip these tests:
- deqp-iris-*
- deqp-llvmpipe (you know, the one mentioned in the comment!)
- deqp-virgl-gl
- deqp-zink-lvp
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
When adding crosvm to the x86_test-gl building deqp-runner was also
mistakenly introduced. deqp-runner is already included in the
x86_test-base image.
Additionally, when bumping the deqp-runner version, only the
x86_test-gl tag was updated.
Now, we remove the unnecessary build from x86_test-gl and bump the tag
for the x86_test-base image.
v2:
- Bump x86_test-gl, not x86_test-vk (Tomeu).
v3: add in fixes for duplicated lines in lvp xfails (Anholt)
Fixes: dc9cd18f52 ("ci: Build Crosvm in our container")
Fixes: 53826932db ("ci: Update piglit and deqp/piglit-runner.")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11359>
The screensaver kicks in at 10 minutes and obscures the screen,
independent of dpms. This causes piglit tests to get flaky (swaps start
taking a whole second, and swapbuffersmsc-divisor-zero times out at
exactly the wrong time) and slow if the run takes longer than 10 minutes.
Hopefully with this we'll see some piglit glx flakes go away forever, it
did seem to for this test locally.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11334>
Trying to run turnip under drm-shim reveals that pretended device
offsets are not sufficiently aligned, failing this assert in tu_pipeline.c:
/* emit program binary & private memory layout
* binary_iova should be aligned to 1 instrlen unit (128 bytes)
*/
assert((binary_iova & 0x7f) == 0);
Round up BO size to 4096 in msm_ioctl_gem_new to avoid this (the kernel
aligns to page size).
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
turnip's DRM device interface requires version 1.6 (for SYNCOBJ).
To unblock use of turnip over drm-shim, raise shim's version to 1.6.
This allows to see shader disassembly, while submission fails with
DRM_SHIM: unhandled core DRM ioctl 0xC4 (0xc01064c4)
TU: error: DRM_IOCTL_SYNCOBJ_RESET failure: Invalid argument
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
If a pipeline enables rasterizerDiscardEnable statically we have to
properly initialize the value, otherwise it won't be updated when a
new pipeline is bound.
Fixes few dEQP-VK.pipeline.extended_dynamic_state.*disable_raster.
Fixes: dd19bf9d7d ("radv: implement dynamic rasterizer discard enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11242>
That way we can actually import surfaces with modifiers & metadata
planes.
Tested with patches for ffmpeg to use this with kmsgrab & modifiers.
For AMD & multiplanar formats we always have 1 format plane = 1
memory plane, even with modifiers.
Intel (non Gallium) does have 1 format plane is 2 memory planes
for some modifiers with NV12. Currently with Gallium we don't really
have info about layer/plane ordering so this manually orders things
so that they align with Intel.
This shouldn't impact other drivers as without modifiers with metadata
planes this should give equivalent behavior to the old import path.
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10815>
Instead of avoiding out-of-bounds access, avoid creating a load larger
than the original attribute. This should work just as well, since the only
situations expending a load helped was because we shrunk it first.
Also fixes a bug where a 3 component load (4 components with the first
component skipped) would be incorrectly expanded to 4 components because
the stride check would never be performed. Maybe we should avoid skipping
the first component in some situations, but I'm not sure if it's worth
the VGPR cost.
fossil-db (vega10):
Totals from 583 (0.39% of 149974) affected shaders:
CodeSize: 1496848 -> 1500868 (+0.27%); split: -0.03%, +0.30%
Instrs: 286155 -> 286575 (+0.15%); split: -0.07%, +0.22%
Latency: 2947101 -> 2946865 (-0.01%); split: -0.23%, +0.22%
InvThroughput: 797396 -> 797127 (-0.03%); split: -0.08%, +0.04%
fossil-db (polaris10):
Totals from 583 (0.39% of 151365) affected shaders:
SGPRs: 38880 -> 39216 (+0.86%)
VGPRs: 24440 -> 24356 (-0.34%)
CodeSize: 1506808 -> 1510876 (+0.27%); split: -0.01%, +0.28%
Instrs: 288735 -> 289167 (+0.15%); split: -0.06%, +0.21%
Latency: 2963263 -> 2961884 (-0.05%); split: -0.24%, +0.19%
InvThroughput: 802351 -> 801665 (-0.09%); split: -0.12%, +0.04%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9007>
Instead of assuming scalar alignment for an attribute, we can use the
required alignment of other attributes in a binding to expect a higher
one.
This uses the alignment of all attributes in the pipeline, not just the
ones loaded. This can create slightly better code, but could break
pipelines which relied on unused (and unaligned) attributes no being
loaded. I don't think such pipelines are allowed by the spec.
fossil-db (Sienna Cichlid):
Totals from 44350 (30.32% of 146267) affected shaders:
VGPRs: 1694464 -> 1700616 (+0.36%); split: -0.08%, +0.44%
CodeSize: 60207184 -> 58093836 (-3.51%); split: -3.51%, +0.00%
MaxWaves: 1175998 -> 1174948 (-0.09%); split: +0.02%, -0.11%
Instrs: 11763444 -> 11458952 (-2.59%); split: -2.60%, +0.01%
Latency: 70679612 -> 67062215 (-5.12%); split: -5.27%, +0.15%
InvThroughput: 11482495 -> 11362911 (-1.04%); split: -1.20%, +0.16%
VClause: 359459 -> 343248 (-4.51%); split: -6.36%, +1.85%
SClause: 422404 -> 419229 (-0.75%); split: -1.17%, +0.42%
Copies: 754384 -> 764368 (+1.32%); split: -1.74%, +3.06%
Branches: 197472 -> 197474 (+0.00%); split: -0.03%, +0.03%
PreVGPRs: 1215348 -> 1215503 (+0.01%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9007>
965 and the mesa st disagree on how vertex elements are ordered when
edgeflags are involved. 965 wants them in gl_vert_attrib order,
but gallium supplies the edgeflag as the last vertex element regardless.
This adds a flag which is enabled for gen4/5 to denote that the
edgeflag is at the end. When we reap 965 later we can resolve this
better.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11146>
Some vulkan functions are not loaded when the corresponding features are
not enabled, but the verifier checks for *all* functions, so make the
verifier more forgiving and use a stub to catch when we actually use a
function that is not loaded.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11328>
There are size restrictions on 2D images which can't accommodate the
*full* 2D MSAA image. There's no way to make it work for 2D MSAA Array
images, but at least for the non-array variants, we can use the
no-mipmap variant which has a larger maximum size.
Fixes dEQP-GLES31.functional.shaders.builtin_functions.texture_size.*2d
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11285>
Now that there's a common NIR pass, there's no point in us doing this in
the back-end anymore. In order to use this pass in i965, we do have to
make one tiny change. Gallium runs the pass after assigning input and
output locations and so needs the pass to respect those locations and
num_inputs. i965, however, runs it before any location assignment or
I/O lowering so we don't care. We do, however, need the pass to succeed
with num_inputs == 0 because we set that later.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11313>
We need to do this in order to handle Yf and Ys tiling because they use
a four-dimensional tile instead of laying everything out in two
dimensions.
v2 (Jason Ekstrand):
- Update functions added since v1:
- isl_surf_get_image_range_B_tile
- blorp_can_hiz_clear_depth
- get_image_offset_el
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v1)
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11330>
The a530s will occasionally fail to make it to the fastboot prompt,
with no other deltas between a working log and a log stalled waiting
for that line to show up.
So, add a serial timeout (like the rpi boards do for similar reasons),
and on timeout restart the run. We actually restart the whole serial
watching process, because the SerialBuffer finishes itself on timeout.
This should also help with the intermittent issue we've had where a
power cycle causes the python serial module to throw an exception.
Tested with the gitlab-disabled db820c that never makes it to the
fastboot prompt (I think it's one where we need a longer micro cable
to connect it!) and saw successful boot looping to retry.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11308>
I was today years old when I learned this about classic composable UNIX
tools:
~/mesa/mesa lava-submitter-overlay * % bash
[daniels@strictly mesa]$ set -e
[daniels@strictly mesa]$ false | tee
[daniels@strictly mesa]$ echo $?
0
Use tail rather than tee, so it doesn't hide our exit status.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11309>
Truth is relative in 2021, and Python's duck-typing means truthiness
isn't what you think it is. Use an explicit fatal-error handler to make
sure we crash out hard on failure, rather than hoping sys.exit() behaves
like you think it does, because it doesn't.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11309>
Trying to get arbitrary strings suitably quoted for shell, embedded in a
YAML file, processed by Python templating, is like seven bad ideas all
embedded into one big can of bees.
Reuse the same script we use for bare-metal to generate the environment,
tar that up into a per-job overlay which is added to the
inter-pipeline-reusable rootfs built by the container jobs and the
intra-pipeline-reusable overlay built by the build jobs.
@anholt wrote a chunk of this - replacing the $ENV_VARS GitLab CI
variable with a Python loop across the POSIX job environment - in
!11192, but this still had YAML quoting nightmares, and was more
needless duplication between LAVA and bare-metal.
The diff is large and annoying, but is mostly a sed job to get
ENV_VARS="FOO=bar BAZ=quux" into FOO: bar\nBAZ: quux.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Co-authored-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11309>
The current implementation in kmsro relies on buffer sharing using
WINSYS_HANDLE_TYPE_FD, which in x11 is only used by default when dri3
is enabled.
Since the current implementation will not work without it, we can
prevent user error by checking that it is not disabled at configuration
time.
Closes#4861
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11305>
In order to use the Vulkan 1.2 core viewport and layer shader outputs,
we need to use SPIR-V 1.5. But we've recently added some preliminary
support to compute the SPIR-V version we're using, with the intention of
adding a SPIR-V version override to work around bugs in tools like
RenderDoc. We haven't implemented the latter yet.
But just to be safe, let's limit this to SPIR-V 1.5. This isn't going to
matter right now, but it might avoid a problem if we decide to finish up
the SPIR-V version overriding.
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11259>
Vulkan has some additional restrictions for vkCmdBlitImage that we
weren't testing for. Quting the Vulkan 1.2 spec, section 20.5 "Image
Copies with Scaling", "Valid Usage" subsection:
- If either of srcImage or dstImage was created with a signed integer
VkFormat, the other must also have been created with a signed integer
VkFormat
- If either of srcImage or dstImage was created with an unsigned integer
VkFormat, the other must also have been created with an unsigned
integer VkFormat.
So let's make sure we reject these illegal blits.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11217>
LLVMpipe always used the bounding-box to rasterize-points, rather than
the actual rasterization-planes. This happened because the primitive was
expanded by one unit outside the bounding box. While this kinda work for
non-multisampled cases, it's not really quite *correct*.
Rasterization of non-legacy points in OpenGL is defined as the
intersection of a the pixel centers with a rectangle of size width and
height, centered around the point in viewport coordinates. This applies
both to multi-sampled and non-multisampled cases.
So let's fix the rasterizer to use the correct definition in both cases.
We leave the legacy case as-is, and just do the inverse adjustment
there so the end result should be the same.
This fixes the following dEQP test-cases:
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.primitives.points
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.points
...as well as this one for Lavapipe:
- dEQP-VK.rasterization.primitives_multisample_4_bit.no_stipple.points
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
This does a little bit better than what we did in 2c0a078fdb
("llvmpipe: fix multisample lines."), where parts of the diamond-exit
rule stuff was bypassed. But we should actually bypass *all* of the
diamond-exit rule stuff here instead.
The reason is that multisampled lines have a completely differently
specified set of rasterization rules, as per the OpenGL 4.6 core spec,
section 14.5.4 ("Line Multisample Rasterization").
So let's give multisampled lines their own geometry-generation codepath
instead.
This fixes the following dEQP tests:
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.primitives.lines
- dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
There's no good reason why we peek into the rasterization state when
dealing with the point_quad_rasterization state, rather than set it
through lp_setup_set_point_state like other point-state.
Let's fix this up, and get rid of a needless NULL-check per primitive.
This makes the code a bit easier to read as well, and will help once
these conditions gets more complicated later on.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
In 2737abb44e, the handling of pixel-offsets and edge rules were
untangled, but one case was missed.
This fixes the following dEQP test-cases on VirGL + LLVMpipe
- dEQP-GLES2.functional.draw.random.10
- dEQP-GLES2.functional.draw.random.42
- dEQP-GLES3.functional.draw.random.105
- dEQP-GLES3.functional.draw.random.114
- dEQP-GLES3.functional.draw.random.135
- dEQP-GLES3.functional.draw.random.144
- dEQP-GLES3.functional.draw.random.155
- dEQP-GLES3.functional.draw.random.174
- dEQP-GLES3.functional.draw.random.206
- dEQP-GLES3.functional.draw.random.31
- dEQP-GLES3.functional.draw.random.43
- dEQP-GLES3.functional.draw.random.84
- dEQP-GLES31.functional.draw_indirect.random.20
...as well as these on Zink + Lavapipe:
- spec@nv_primitive_restart@primitive-restart-disable_vbo
- spec@nv_primitive_restart@primitive-restart-vbo_combined_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_index_only
- spec@nv_primitive_restart@primitive-restart-vbo_separate_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_vertex_only
Fixes: 2737abb44e ("gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
This brings in some major new features in the runner:
- piglit tests now include subtest reporting
- "-t" support for quick include-filtering of tests.
- piglit tests that crash after their result report are considered crashes.
- throws a nice error if you try to annotate the same failure twice
(e.g. lvp's dEQP-VK.glsl.builtin.precision.pow.highp.vec2,Fail)
Since the runner catches piglit test bugs where the same subtest is run
twice, we also uprev piglit to pull in the fixes for those.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
We were inserting them in what was NIR's end block with the "end"
instruction, which meant that the moves they generated couldn't be
scheduled with the rest of the last block as part of post-RA scheduling.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
RA currently can't handle a live value that's part of a vector and
introduces extra copies. This was espeically a problem for bary.f, where
the bary coords were being split and repeatedly re-collected. But this
could be a problem in other situations as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
If an instruction's destination is unused, then we shouldn't penalize
it. For example, this helps us schedule atomic operations whose results
aren't read. This works around RA failures when CSE is enabled in some
robustness2 tests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
In a scenario where there are a lot of texture fetches with constant
coordinates, this prevents the scheduler from scheduling all the setup
instructions after the first group of textures has been scheduled
because they are the only non-syncing thing and scheduling them didn't
decrease tex_delay. Collects with immed/const sources will turn into
moves of those sources, so we should treat them the same.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
This will be run right after nir->ir3. Even though we have SSA coming
out of NIR, we still need it for NIR registers, even though we keep the
original array around to insert false dependencies.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
The old delay calculation relied on the SSA information staying around,
and wouldn't work once we start introducing phi nodes and making
"normal" values defined in multiple blocks not array regs anymore.
What's worse is that properly inserting phi nodes when splitting live
ranges would make that code even more complicated, and this was the last
place post-RA that actually needed that information.
The new version only compares the physical registers of sources and
destinations. It works by going backwards up to a maximum number of
cycles, so it might be slightly slower when the definition is closer but
should be faster when it is farther away.
To avoid complicating the new method, the old method is kept around, but
only for pre-RA scheduling and it can therefore be drastically
simplified as the array case can be dropped.
ir3_delay_calc() is split into a few variants to avoid an explosion of
boolean arguments in users, especially now that merged_regs now has to
be passed to it.
The new method is a little more complicated when it comes to handling
(rptN), because both the assigner and consumer may be (rptN). This adds
some unit tests for those cases, in addition to dropping the to-SSA code
in the test harness since it's no longer needed.
Finally, ir3_legalize has to be switched to using physical registers for
the branch condition. This was the one place where IR3_REG_SSA remained
after RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
In particular, make sure they have a physreg assigned. This was the last
place after RA where SSA registers were created, which won't work with
the new post-RA delay calculation that relies on the physreg.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
There were two different approaches I saw in the post-RA code for
figuring out what regiser range a relative access touched:
1. Use reg->array.offset and reg->array.size. This is wrong in case
reg->array.offset was non-zero before RA, because array.size is
the size of the whole array and array.offset has the const offset
within the array baked in.
2. Lookup the array from the array ID and use the base + range there.
This is correct, but won't work with the new RA, where an array might
not always be assigned to the same register.
This replaces both methods with a new ir3_register::array.base field,
and switches all the users I could find to it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
To simplify the pre-RA merge set code and express the result live-range
splitting in RA, we need to add support for parallel copy instructions,
and for the merge set code these parallel copies need to be in SSA form.
Parallel copies have multiple destinations by necessity, but there was
no way to express this in the existing IR. In particular there was no
support for marking a register as being a destination, and no support
for indicating which destination register out of several an SSA source
refers to. This replaces ir3_register::instr with ir3_register::def and
re-purposes ir3_register::instr. I haven't propagated this into common
helpers, like ssa(), because that would vastly increase the amount of
churn and the number of places that produce such instructions should be
limited -- only RA will create parallel copies and they will be
destroyed right after RA. In the future swz will have multiple
destinations too, but it will only be created after RA via parallel copy
lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
We have CI, we're just a few tests away from conformance on v7, and
Midgard is just a few hundred tests behind. Given the branch point isn't
for another month, I think this is a good time to flip the switch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Suboptimal but fixes KHR-GLES31.core.compute_shader.pipeline-post-xfb,
which is stubbornly still broken with memory barriers implemented and
cache flush jobs inserted. More investigation needed but probably not
right now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
CRC is intended for final render targets and especially for UI, not the
kind of things you'd mipmap. Meanwhile CRC only works for a single
level, meaning at any given point, half the CRC buffer would be wasted
for a full miptree.
"Arm Mali Best Practices Guide" tells developers that the DDK only
enables CRC for non-mipmapped resources (at least the Vulkan DDK), so
let's do the same, save some memory, and simplify our code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Somehow XFB gets so little use we never noticed. Fixes:
KHR-GLES31.core.vertex_attrib_binding.basic-input-case9
KHR-GLES31.core.vertex_attrib_binding.basic-input-case11
KHR-GLES31.core.vertex_attrib_binding.basic-inputI-case2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Based on a misunderstanding of how the scissor test works, and in
particular breaks transform feedback and SSBO writes from vertex
shaders.
Replace it with a moral equivalent to rasterizer_discard so vertex
shaders still run.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
If we have per-draw state (vertex ID stuff), there's an ordering
mismatch. Fixes
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.builtin_variable.vertex_id
on Midgard, and I'm not sure why it was passing on Bifrost before. Also
should fix (on both architectures) DRAWID issues.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
You'd just get a blend shader anyway, and since they're not spec
requirements, let's not worry about backporting the Midgard lowerings.
Takes dEQP-GLES31.functional.fbo.color.tex2d.* on Midgard from crashing
to not supported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Since the GLSL compilers will pack together flat varyings with no regard
to type, under the assumption the backend can deal with it. I guess we
can deal with it then... Fixes fails in
dEQP-GLES31.functional.separate_shader.random.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
It's too complicated and probably for no actual benefit. The main reason
we have BGR formats is for display, but that's export and doesn't get
hit by this path. Internal BGRA textures are possible with a Mesa
extension but sufficiently rare that I regret suggesting this as a
possible optimization. My apologies, and thanks for the fish.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
If the shader packs multiple varyings into the same location with
different location_frac, we'll need to lower to a single varying store
that collects all of the channels together. This is not trivial during
code gen, but it is trivial to do in NIR right before codegen by relying
on nir_lower_io_to_temporaries. Since we're guaranteed all varyings will
be written exactly once, in the exit block, we can scan the shader
linearly and collect stores together in a single pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
We have no native way to swizzle out a nonzero component in a load, but
we can simply load extra components and do the swizzle in shader
instructions. This is inefficient, since it loads data to discard
immediately, but it's required for conformance in some edge cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
If we know that a value is killed in the next tuple, there is no need to
write it out to the register file. We already handled this as a packing
fixup. However, avoiding this write also frees up an extra slot in the
register block, which offers additional scheduling freedom. To take
advantage of this, we extend liveness analysis to work while scheduling,
and modify the schedulable predicate accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Flag day change to swap the order of the "scheduler" with the register
allocator. This gives RA much more freedom without significantly
hndering bundling.
It also opens up the door to Adult-level Scheduling which would occur
prior to bundling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
gcc 11 dixit:
In function ‘sample_2d_ewa’,
inlined from ‘sample_lambda_2d_aniso’ at ../src/mesa/swrast/s_texfilter.c:1995:10:
../src/mesa/swrast/s_texfilter.c:1729:13: warning: ‘sample_2d_nearest’ reading 16 bytes from a region of size 8 [-Wstringop-overread]
1729 | sample_2d_nearest(ctx, samp, img, newCoord, rgba);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/mesa/swrast/s_texfilter.c: In function ‘sample_lambda_2d_aniso’:
../src/mesa/swrast/s_texfilter.c:1729:13: note: referencing argument 4 of type ‘const GLfloat *’ {aka ‘const float *’}
Indeed, newCoord is GLfloat[2] but the argument is typed GLfloat[4],
even though only the first two (s and t) are ever read. Fix the array
size in the function signature to reflect the maximum element actually
addressed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11273>
The only case RTTI is used in nouveau is type assertion at:
File src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:
assert(typeid(*i) == typeid(*this));
This assertion is used 'to be on the safe side' only and not mandatory.
In Android we do not have rtti for libLLVM therefore this assertion
has to be skipped.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11069>
Fixes these new gcc11 warnings:
In file included from ../src/mapi/glapi/glapi_dispatch.c:174:
src/mapi/glapi/gen/glapitemp.h:3191:68: warning: argument 1 of type 'const GLdouble *' {aka 'const double *'} declared as a pointer [-Warray-parameter=]
3191 | KEYWORD1 void KEYWORD2 NAME(LoadTransposeMatrixd)(const GLdouble * m)
| ~~~~~~~~~~~~~~~~~^
In file included from ../src/mapi/glapi/glapi_priv.h:31,
from ../src/mapi/glapi/glapi_dispatch.c:40:
../include/GL/gl.h:1901:62: note: previously declared as an array 'const GLdouble[16]' {aka 'const double[16]'}
1901 | GLAPI void GLAPIENTRY glLoadTransposeMatrixd( const GLdouble m[16] );
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11198>
attempting to read the inlined uniforms directly after the variant key
using the size of the variant is not going to work since the variant union
is (sometimes) much larger than the size of the actual struct being used,
meaning that this would just copy a bunch of zeroes instead of the actual
inlined uniforms
Fixes: 7f28775edc ("zink: implement uniform inlining")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11003>
LAVA doesn't consider failure to download a kernel/initramfs as an
infrastructure error, rather just a user error for supplying a broken
URL. We know our URLs aren't broken (because we're perfect), so assume
that failures in download validation are network issues and retry when
we hit them.
LAVA itself has been fixed to retry internally, so we'll get that when
upgrade in a couple of weeks, but gloss over it for now.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
The intrinsic produces a vec2, so let's honor that and avoid the weird
lowering to scalar and later reconstruction to vec2 when we find
load vulkan descriptor intrinsics.
It fixes tests like this (which require that we expose KHR_spirv_1_4):
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrequal.null_comparisons_ssbo_equal
that otherwise produce bad code that tries to access a vec2 from the result of
that intrinsic, leading to NIR validation errors.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11257>
We only support the VariablePointersStorageBuffer feature for now,
which is the only one that is mandatory, and for which we seem to
be passing all the relevant tests already.
Exposing the optional VariablePointers feature would require that
we support non-constant indexing on UBO/SSBO first.
Relevant CTS tests:
dEQP-VK.*pointer*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11257>
We need to remove the batch cache entry before marking as flushed.
Note that we are already holding the batch lock, to prevent flushing
something that another context is emitting cmdstream to, but there is
a window between batch cache lookup (under screen lock) and acquiring
the batch lock that could previously result in batch cache lookup
returning a flushed batch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11200>
A number of the piglit glx tests use multiple contexts on a single
thread, and previously the flush in MakeCurrent() was enforcing the
ordering between draws on those different contexts. When that flush
made ASYNC, now there is nothing ordering the draws because we have
two (or more) driver threads for a single frontend thread which is
using nothing more than glxMakeCurrent() to enforce the ordering.
This reverts commit 057a702a3f.
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4903
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11278>
using the stride to calculate the buffer map size here is not correct, as
the stride is not necessarily equal to the attribute size, it's only the distance
between elements. for the case of overlapping elements (cts does this), the result
is that the attribute conversion will read past the end of the mapped src region
this is usually fine for drivers when they directly map the vertex buffer, as the memory
past the requested region is usually made available, but in the case where the readback
occurs using a staging resource sized exactly to the map region, this overflows and fails
silently, not even triggering a valgrind error because gpu memory lol
instead, add the size of the largest possible element, which will automatically be clamped
and ensure any staging buffers are correctly sized
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10963>
Android WSI api contract requires to allocate min_undequeued_buffers + 2
to achieve "triple buffering" effect, which is when the composer backend
acquired the allowed max numbder of buffers, the producer still has 2
buffers to rotate.
ANativeWindow either belongs to SurfaceView which presents directly to
SurfaceFlinger or belongs to other surfaces from the UI framework. For
the former, SurfaceFlinger hardcodes triple buffering for EGL. For the
latter, the surface caps decide the buffer limits or HWUI intercepts and
adjusts the min_undequeued_buffers to hint the EGL implementation to
prepare enough buffer cache slots while HWUI sets the max dequeued
buffer count accordingly.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11206>
A bunch of tests are currently taking ~60 seconds, dangerously close to
the current 60 seconds timeout. Add some congesion or just bad luck to
a runner, or some other background-task, and we can very easily be
pushed above that.
Since we're rendering on LLVMpipe rather than HW, this isn't as
unreasonable as it might sound at first. So let's copy a trick from
VirGL's CI playbook, and bump the timeout to 180 seconds, three times
of what we currently use.
That might seem a bit excessive, but it's better to make it *very*
unlikely to cause trouble than a little bit unlikely.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11272>
According to feedback, the terminology with "exclusive scan"
and "reduction" is difficult. Change it to use "repack" instead,
which better fits what this sequence is actually used for.
The new sequence stores only 1 byte / wave to LDS, and uses packed
instructions to produce the results. This has lower latency and
fewer instructions than what we previously had.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>
As a result of some previous changes, it is now possible to expose ES
3.1 without having the ARB_shader_image_load_store enable set. However
we still want those other extensions. When there's a driver that's
capable of exposing ES 3.1 but not these extensions, more caps can be
added.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11204>
When the offset is negative, reg() isn't 255. Fix this by splitting
SGPR and literal emission. While we are at it, adjust a comment
saying that literals are also accepted on GFX6 which is wrong.
Fixes another batch of robustness tests.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11247>
If the tex/sfu ssa src is from a different block than the one currently
being scheduled, we do not have a valid sched-node. So fallback to
previous behavior rather than dereference an invalid ptr.
Fixes: 7821e5a3f8 ("ir3/sched: Don't penalize uses of already-waited tex/SFU")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10306>
The relocation list currently serves two purposes. One is for
relocations on older non-softpin platforms. The second is to keep track
of driver-managed BOs which are used by the given command buffer. We
going to need a mechanism to add BOs to the command buffer without doing
a relocation into the batch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11236>
if we have
if ... {
return;
} else {
// block X
}
// block Y
phi(X: ...)
then nir_lower_returns tries to move block Y into the else body,
except nir_cf_extract doesn't move the phi. As the return is removed
in the then-body the phi suddenly has the wrong number of arguments
(and the phi doesn't dominate its uses anymore).
In this case we know that the phi has to be single arg, so we can just
rewrite the users of the phis and drop them.
Hit this in my RT adventures, not sure if this is actually reachable
right now, as single arg phis tend to be kind of exceptional outside
of CSSA and we typically call nir_lower_returns pretty early.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11207>
Debugging fd mix-ups (ie. where, possibly via close()ing the original
fd, etc, you end up with something that is a valid fd but not a valid
*fence* fd) can be difficult. Fortunately we can use the FILE_INFO
ioctl, which will return an error if the fd is not a fence fd.
For android, we instead use the libsync API, which does a similar thing
on modern kernels, but has a fallback path for older android kernels.
Note that the FILE_INFO ioctl has existed upstream since at least prior
to destaging of sync_file.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11202>
We shouldn't be using RETURN_EGL_EVAL() for eglDupNativeFenceFDANDROID()
return, as (while perhaps unlikely) zero is a valid fd. The error case
for EGL_NO_NATIVE_FENCE_FD_ANDROID is already handled in egl_dri2.c
(dri2_dup_native_fence_fd()) so just use RETURN_EGL_SUCCESS() instead.
Also fix ret type.
Fixes: 0201f01dc4 ("egl: add EGL_ANDROID_native_fence_sync")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11202>
Most allocations will want to be in device local memory (if it exists),
so we default to LMEM in the absence of a flag. However, some buffers
are expected to be read/written from the CPU multiple times, and we may
want to explicitly place those buffers in system memory.
This patch adds the infrastructure for deciding on the allocation,
and sets the flags, but does not actually hook up the flag to do
anything, as the kernel infrastructure for LMEM support hasn't landed.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
In the past, we tracked bo->tiling_mode and bo->stride, and used
GEM_{GET,SET}_TILING on all buffers we allocated. This made more sense
in the old days (long before iris even existed) when we used GTT maps to
detile resources. However, that support is now gone, and we never used
it in iris anyway. We don't need to do this in most cases anymore.
We are trying to deprecate these kernel APIs. They have many issues.
One is having a global tiling mode for a buffer when userspace may
want to suballocate multiple resources with different tiling modes
from the same object. Another is...what if processes want to interpret
the data differently, and hot-swap the tiling mode out from under
another process? Another is the fundamental race conditions. There
are many reasons not to use these APIs.
Unfortunately, there is still one case where it's used: when importing
and exporting DMABUFs, we have to communicate the tiling somehow. The
right way to do that is using modifiers, but those didn't always exist,
and aren't always enabled (maybe aren't even commonly enabled). So we
use GET/SET_TILING as a poor-man's IPC mechanism of sorts.
This patch stops calling those APIs in general but continues doing so
for imported/exported objects when we don't have modifiers.
We eliminate iris_bo_alloc_tiled entirely. There is now only one!
One small behavioral change snuck in: iris_memobj_create_from_handle
now aligns the virtual address to 64K rather than 1B when modifiers
aren't present. This should be harmless, and lets us delete a whole
bunch of code.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Based on a patch by Rafael Antognolli.
We already had a flags parameter, but omitted it from the simple alloc
interface because most callers were passing 0. However, we'll want to
use it for selecting between device local memory and system memory, and
possibly mmap cacheability modes, in the future. At that point, many
more callers will want to specify, so I think we should include flags
in iris_bo_alloc() as well.
A few places used the iris_bo_alloc_tiled() function simply to pass
flags, so this patch converts them to use iris_bo_alloc() instead now
it does everything they want.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11169>
Since 40e1d798c6, we are now using physical register numbers for
everything which makes it all simpler. In particular, we no longer need
the special case for setting up the payload for SIMD16 on Gen4-5. This
fixes a pile of piglit tests on ILK and similar.
Fixes: 40e1d798c6 "intel/fs: Use ra_alloc_contig_reg_class()..."
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11221>
How to use:
- For GALLIUM drivers:
1. Add gallium drivers into your board.mk file:
board.mk:
BOARD_MESA3D_USES_MESON_BUILD := true
BOARD_MESA3D_GALLIUM_DRIVERS := lima panfrost v3d
2. Add the following packages into your device.mk file:
device.mk:
PRODUCT_PACKAGES += \
libEGL_mesa \
libGLESv1_CM_mesa \
libGLESv2_mesa \
libgallium_dri \
libglapi
- For VULKAN drivers:
1. Add single vulkan driver into your board.mk file:
board.mk:
BOARD_MESA3D_USES_MESON_BUILD := true
BOARD_MESA3D_VULKAN_DRIVERS := freedreno broadcom
2. Add the following package configuration into your device.mk file:
device.mk:
PRODUCT_PACKAGES += \
vulkan.freedreno
PRODUCT_PROPERTY_OVERRIDES += \
ro.hardware.vulkan=freedreno
- To build 'libgbm' set definition in the board.mk:
BOARD_MESA3D_BUILD_LIBGBM := true
And add a package to the device.mk:
PRODUCT_PACKAGES += libgbm
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10183>
Not all hardware can treat float, uint and sint samplers and images the
same way, so we need to respect the format-types here.
This has the added benefit of making sure sint and uint data doesn't
get copied through a float, which might mess with signaling nan
encodings.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11164>
The Vulkan spec says the following:
> If imageType is VK_IMAGE_TYPE_2D and flags contains
> VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT, extent.width and extent.height
> must be equal and arrayLayers must be greater than or equal to 6
This makes a lot of sense, as these are also requirements for being able
to create cubemaps from them in the first place.
Let's thread a bit more careful, and only set this bit in these cases.
This matters in the new case of setting this flag on 2D array textures.
In the other cases, this should already be the case.
I haven't seen this trigger any issues, I just realized this while
reading the Vulkan-spec.
Fixes: 1887ff2ebb ("zink: mark 2d-arrays as cube-compatible")
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11081>
This clarifies the semantics of the index variables compared to the previous
version, which used the same variables in a slightly different way depending
on whether they were used for downwards moves or upwards ones.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10885>
Otherwise the pb_slabs might be freed by another thread in between.
Valgrind example:
==676841== Invalid read of size 1
==676841== at 0x6B0A8B3: get_slab_wasted_size (amdgpu_bo.c:659)
==676841== by 0x6B0AD7D: amdgpu_bo_slab_destroy (amdgpu_bo.c:684)
==676841== by 0x6ACF94F: pb_destroy (pb_buffer.h:259)
==676841== by 0x6ACF94F: pb_reference_with_winsys (pb_buffer.h:282)
==676841== by 0x6ACF94F: radeon_bo_reference (radeon_winsys.h:754)
==676841== by 0x6ACF94F: si_replace_buffer_storage (si_buffer.c:274)
==676841== by 0x6957036: tc_call_replace_buffer_storage (u_threaded_context.c:1554)
[...]
==676841== by 0x4ECCDEE: clone (clone.S:95)
==676841== Address 0x27879945 is 5 bytes inside a block of size 208 free'd
==676841== at 0x48399AB: free (vg_replace_malloc.c:538)
==676841== by 0x6B0E8BD: amdgpu_bo_slab_free (amdgpu_bo.c:863)
==676841== by 0x6B89D4A: pb_slabs_reclaim_locked (pb_slab.c:84)
==676841== by 0x6B89D4A: pb_slab_alloc (pb_slab.c:130)
==676841== by 0x6B0EE7F: amdgpu_bo_create (amdgpu_bo.c:1429)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4736
Fixes: 965c6445ad ("winsys/amdgpu,radeonsi: add HUD counters for how much memory is wasted by slabs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
This extension is basically only wrapping SPV_KHR_storage_buffer_storage_class
which is entirely implemented in the SPIR-V frontend.
Relevant CTS tests:
dEQP-VK.glsl.opaque_type_indexing.ssbo_storage_buffer_decoration.*
dEQP-VK.spirv_assembly.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11184>
This add a simple mechanism to select which GPU adapter the d3d12
driver should be using. A new environment variable is introduced.
MESA_D3D12_DEFAULT_ADAPTER_NAME
This represent a substring to search for in the GPU descrition,
for example "NVIDIA" or "INTEL", or "NVIDIA GeForce RTX 3090",
etc...
GPU are searched in order and the first one to include the substring
becomes a match. If no match is found, we default to the first
enumerated GPU.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10710>
The requirements for ES 3.1 are lower than the requirements for desktop
GL. The thread block size can be smaller, and images/buffers/atomics
need not be supported in the fragment stage. Allow a driver to expose
ES 3.1 without flipping on the desktop GL extensions.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10569>
The hardware has no support for 3d image loads/stores. So present the
image as a larger 2d image and fudge the coordinates. Note that a 2d
image (in the shader) may be backed by a slice of a 3d image, so we
always have to do the coordinate adjustments for 2d as well.
This is largely copied from the nv50 support, which has the same
restriction, with extra care taken to differentiate loads (which
specifies the X coordinate in bytes) and stores, which specifies it in
(formatted) pixels.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10820>
Prior to an earlier commit, xfb queries were not being marked as 64-bit.
The end result of this is that they would never appear to be "ready",
which in turn led to there always being a wait happening.
Once these got marked as 64-bit, we started checking the attached fence
for being signalled. However the screen fence does not seem to be enough
to wait for the streamout query data to actually be written out. So
instead we add a bit of extra "data" which emulates the 32-bit query way
of doing things (with the payload in front) which is emitted from the
same "unit" as the other streamout data. This seems to be sufficient.
Note that it does not seem to be required to actually emit the final
32-bit query from the streamout unit, but that seems logical and perhaps
there are edge cases where it is required.
While at it, also make the sequence management/initialization more
similar to the nvc0 driver.
Fixes dEQP-GLES3.functional.transform_feedback.*
Fixes: 58d47ca324 ("nv50: add compute invocations counter")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10867>
Fix defect reported by Coverity Scan.
Side effect in assertion (ASSERT_SIDE_EFFECT)
assignment_where_comparison_intended: Assignment deviceMask = 1U
has a side effect. This code will work differently in a non-debug
build.
Fixes: 234e1b7356 ("v3dv: implement VK_KHR_device_group")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11197>
On AGX, the special register for front facing is inverted from its meaning in
APIs. We need to lower load_front_face to inot(load_back_face). Doing this in
the backend is trivial, but then we would miss out on algebraic optimizations
for the inot.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
Somehow fairly recently the traces CI job started hitting timeouts, not
all the time but enough to be inconvenient for CI. I tracked it down to
getting into a situation where `ctx->batch->flush == true`, which causes
an infinite loop in the draw_vbo and clear paths (because
fd_batch_lock_submit() checks for flushed batch but fd_context_batch()
does not). I'm not entirely sure how we get into that state, or what
triggered this (seems possibly triggered by !10937). But it is easy
enough to recover.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11196>
Now that we have an idea of how many regs the conflicting allocation uses,
we can just skip to the next one and save repeated tests to find the same
conflicting neighbor again.
shadowrun-returns shader-db time on skl -1.62821% +/- 1.58079% (n=679),
now there's no statistically significant change from the start of the series
(n=420)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
By using the new class type, we don't need to make 1928 different
registers to represent each contigous reg size starting from the actual
128 HW register, or have a mapping between RA regs and HW base regs. With
the number of regs reduced, and the fast q computation when using the new
classes, we no longer need to compute our own q.
This drops the FS RA initialization time on my CFL system from about 1ms to
50us.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
In the fully general case of register classes, to expose an allocation
class of unaligned 2-contiguous-regs allocations, for example, you'd have
your base individual regs (128 on intel), and another set of 127 regs that
each conflicted with the corresponding pair of the base regs. Single-reg
nodes would allocate in the 128, and double-reg nodes would allocate in
the 127 and the user would remap from the 127 down to the base regs with
some irritating table.
If you need many different contiguous allocation sizes (16 is a pretty
common number across drivers), your number of regs explodes, wasting
memory and making the q computation expensive at startup.
If all the user has is contiguous-reg classes, we can easily compute the q
value up front (as found in the intel driver and nouveau, for example),
and we only have to change a couple of places in the conflict-checking
logic so the contiguous-reg classes can use the base registers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
Putting a const char * in the struct means it's a pointer that has to be
resolved at rtld time, which means it can be in .data.rel.ro but not
.rodata like you'd hope. Fix this with the usual string table trick.
Cuts about 20k (-80k read-write +60k read-only) and ~280 relocations
from the gallium driver.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11168>
We initially just copied on v3dv, just in case we needed to modify
it. One year later the code is exactly the same, so let's move it to
common.
This fix an additional issue, as we were not using NEON when building
v3d_tiling.c for v3dv.
v2:
* Add "#include util/u_box.h" at v3d_tiling.h, so we can't avoid
the need to include it on other places. (Juan and Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11121>
Add a moltenvk-dir build option to supply the MacOS Vulkan SDK MoltenVK location.
Force compiler, for zink only, into object-c mode when MoltenVK is used to allow for the MacOS ioSurface and CAMetalLayer types that the headers expose.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11129>
Some CTS tests use more than what we expose and other drivers
also seem to be exposing many more than us (in the order of thousands).
I don't think we want to expose a very large number since we use this
limit to size some arrays in the driver, but bumping it a bit over the
minimum of 4 required by the spec might be reasonable.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11159>
Fixes the following building errors:
external/mesa/src/amd/vulkan/radv_shader.c:868: error: undefined reference to 'ac_nir_lower_ngg_gs'
external/mesa/src/amd/vulkan/radv_shader.c:851: error: undefined reference to 'ac_nir_lower_ngg_nogs'
external/mesa/src/amd/compiler/aco_interface.cpp:155: error: undefined reference to 'aco::optimize_postRA(aco::Program*)'
Fixes: 3d589b8b46 ("ac: Add new NIR pass to lower NGG VS/TES.")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11177>
It is simpler. But I mainly want to work around
../src/virtio/vulkan/vn_cs.h:173:4: error: argument 1 null where non-null expected [-Werror=nonnull]
173 | memcpy(val, dec->cur, val_size);
We trust virglrenderer and it never instructs the decoder to memcpy to
pData when it is NULL. The compiler does not know however. A proper
fix will be to generate
if (!pData)
unreachable();
to help the compiler.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11174>
Upon instance creation, venus experimental features are cached in the
vn_instance. If memoryResourceAllocationSize feature is supported, chain
VkMemoryResourceAllocationSizeProperties100000MESA to the pNext of
VkMemoryResourcePropertiesMESA to get the host allocation size of the
dma_buf fd.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11048>
We introduce vkGetVenusExperimentalFeatureData100000MESA to negotiate
experimental venus features under development between the guest and the
host, which can help avoid breaking existing clients of venus. All the
experimental features will be cleaned up and merged into core upon
finalizing venus protocol.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11048>
No other drivers use the vendor in the title or path, so it seems better
to not do this for the vmware-guest driver as well. So let's rename it
to SVGA instead. The actual text itself makes it clear enough what it is
about.
This makes it stand out less in the toctree.
I chose the name "WMware SVGA3D", because that's less ambigious than the
"SVGA"-alternative, and was requested by VMware people.t
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11109>
Allocates VRAM in display GPU in case of prime. Then the dma_buf is imported
into prime GPU.
v2: add comments to make code more readable (Pierre-Eric)
removed if check limiting p2p only for matching driver name
v3: keep old path for non mesa driver (Michel Dänzer)
v4: destroy linear_buffer_display_gpu after import (Michel Dänzer)
fall back if linear_buffer_display_gpu alloc fail (Michel Dänzer)
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10595>
The created DRI screen can be used to allocate VRAM memory from
display GPU in case of prime.
v2: add comments to make code readable (Pierre-Eric)
remove driver name match check
v3: keep old path for non-mesa driver (Michel Dänzer)
v4: fallback if driver not found for display GPU (Michel Dänzer)
fallback if create screen fail for display gpu (Michel Dänzer)
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10595>
In 2db8867943, we introduced a new meta-op MOV_FOR_SCRATCH which is
identical to MOV except it lets us identify MOVs emitted during spilling
so we know not to re-spill those instructions. We emit them from
shuffle_for_64bit_data whenever the new for_scratch parameter is true.
Unfortunately, we missed the one used for resolving swizzles.
Fixes: 2db8867943 "intel/vec4: Don't spill fp64 registers more..."
Tested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11155>
This takes a different approach. It turns out we can patch
vkCmd{Begin,End}RenderPass, vkCmdWaitEvents, and vkCmdPipelineBarrier to
do queue family ownership transfers without tracking image ownerships.
v2: check the value of VN_PRESENT_SRC_INTERNAL_LAYOUT and keep this
Android-only
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10709>
dEQP-VK.api.external.memory.opaque_fd.* re-imports and fails because
external_handles was VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT on
allocation and is VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT on
re-import.
Fixes: ccefcb0baf ("venus: fix misaligned bo_flags between import and query")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11154>
Iris only runs on BDW+ and ANV already handles this by not even trying
on anything older than HSW. The only driver benefiting from this common
check is i965. Moving it out makes the pass more generic and if some
driver comes along which can push UBOs on IVB, it should work for that.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11145>
Always chain wsi_image_create_info to VkImageCreateInfo, which indicates
that the image is a wsi image and can be transitioned to/from
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR.
Add prime_blit_buffer to the struct as well. When set, it indicates the
prime blit destination and implies that the image is a prime blit
source.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10789>
It appears that CP can over-fetch push constants slightly. While it
otherwise has no problem fetching from an alignment of 32 bytes, if that
32 bytes is at the end of a mapped bo, this can trigger fetching up to
32 bytes beyond the patch, triggering an iova fault. While otherwise
"harmless", it is probably better to not have random intermittent
faults.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11142>
It notably didn't fit the pattern of RGB5_A1_UNORM, and violated the
general pattern for bitmask format BE channels (channels are ordered
right-to-left in the BE columns in the CSV due to the parser walking them
in that order for historical reasons).
Acked-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10505>
These tests passed for LE, and the BE channel ordering specified obviously
didn't fit the pattern of the other BE formats (channels are listed
right-to-left in the BE columns for historical reasons).
Note that we can't write pure-integer format tests in u_format_tests.c
currently.
Acked-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10505>
nir_assign_io_var_locations() does not use outputs_written when
assigning driver locations. Use driver_location to avoid incorrectly
guessing what locations it assigned.
Copied from lavapipe 8731a1beb7
Will fix provoking vertex tf tests when VK_EXT_provoking_vertex
would be enabled:
dEQP-VK.rasterization.provoking_vertex.transform_feedback.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11111>
Previously, iris_bufmgr had the ability to maintain multiple
simultaneous memory mappings for a BO, one in WB mode (with CPU caches),
and another in WC (streaming) mode. Depending on the flags passed to
iris_bo_map(), we would select one mode or the other.
The rules for deciding which to use were:
- Systems with LLC always use WB mode because it's basically free
- Non-LLC systems used...
- WB maps for all BOs where snooping is enabled (which translates to
when BO_ALLOC_COHERENT is set at allocation time)
- WB maps for reads unless persistent, coherent, async, or raw.
- WC maps for everything else.
This patch simplifies the system by selecting a single mmap mode at
BO allocation time, and always using that. Each BO now has at most one
map at a time, rather than up to two (or three before we deleted GTT
map support in recent patches).
In practical terms, this eliminates the capability to use WB maps for
reads of non-snooped BOs on non-LLC systems. Such reads would now be
slow, uncached reads. However, iris_transfer_map recently began using
staging blits for such reads - so the GPU copies the data to a snooped
buffer which will be mapped WB. So, rather than incurring slow UC
reads, we really just take the hit of a blit, and retain fast reads.
The rest of the rules remain the same.
There are a few reasons for this:
1. TTM doesn't support mapping an object as both WB and WC. The
cacheability is treated as a property of the object, not the map.
The kernel is moving to use TTM as part of adding discrete local
memory support. So it makes sense to centralize on that model.
2. Mapping the same BO as both WB and WC is impossible to support on
some CPUs. It works on x86/x86_64, which was fine for integrated
GPUs, but it may become an issue for discrete graphics paired with
other CPUs (should that ever be a thing we need to support).
3. It's overall much simpler. We only have one bo->map field, and
manage to drop a significant amount of boilerplate.
One issue that arises is the interaction with the BO cache: BOs with
WB maps and WC maps will be lumped together into the same cache. This
means that a cached BO may have the wrong mmap mode. We check that,
and if it doesn't match, we unmap it, waiting until iris_bo_map is
called to restore one with the desired mode. This may underutilize
cache mappings slightly on non-LLC systems, but I don't expect it to
have a large impact.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4747
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
In the bad old days, i965 used GTT mapping for detiling maps. iris
never has, however. The only reason it used GTT maps was in weird
fallback cases for dealing with BO imports from foreign memory. We
now do staging blits for those, and never mmap them.
There are no more users of GTT mapping, so we can delete it.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
XXX: This is actually wrong. The dmabuf imported case can be mapped via
GEM_MMAP_GTT if the iommu is working, according to Joonas, but GEM_MMAP
would fall over and fail. So we would need this fallback.
ALTERNATIVELY...we would need to flag such imported dmabufs as
unmappable, and then make iris_transfer_map/unmap always do blits
instead of direct mappings. That seems like the saner approach
We never want to use GEM_MMAP_GTT, as it does detiling maps, and iris
always wants direct maps. There were originally two cases that this
fallback path was attempting to handle:
1. The BO was allocated from stolen memory that we can't GEM_MMAP.
At one point, kernel patches were being proposed to use stolen
memory for userspace buffers, but these never landed. The kernel
has never given us stolen memory, so we cannot hit this case.
2. Imported objects may be from memory we can't GEM_MMAP.
For example, a DMABUF from a discrete AMD/NVIDIA GPU in a PRIME
setup would be backed by memory that we can't GEM_MMAP. We could
try and mmap these directly with GEM_MMAP_GTT, but that relies on
the IOMMU working. We could mmap the DMABUF fd directly (but have
never tried to do so), but there are complex rules there. Instead,
we now flag those imports, however, and rely on the iris_transfer_map
code to perform staging blits on the GPU, so we never even try to
map them directly. So this case won't reach us here any longer.
With both of those out of the way, there is no need for a fallback.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
Direct mappings of imported DMABUFs can be tricky. If they're allocated
from our own device, then we can probably mmap them and it'd be fine.
But they may come from a different device (such as a discrete GPU), in
which case I915_GEM_MMAP wouldn't work, I915_GEM_MMAP_GTT would require
a working IOMMU, and directly mmap'ing the DMABUF fd would come with a
bunch of rules and restrictions which are hard to get right.
CPU mapping an imported DMABUF image for writes seems very uncommon,
solidly in the "what are you even doing?" realm. Mapping an imported
DMABUF for reading might be a thing, in case someone wanted to do
glReadPixels on it. But in that case, the cost of doing a staging
blit is probably acceptable.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
Not all external objects are the same. Imported buffers may be from
other devices (say a dmabuf from an AMD or NVIDIA discrete card) which
are backed by memory that we can't use with I915_GEM_MMAP. However,
exported buffers are ones that we know we allocated ourselves from our
own device. We may not know what other clients are doing with them,
but we can assume a bit more about where they came from.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
In some cases, we have to map directly (e.g. coherent/persistent maps).
In other cases (e.g. tiled), we /cannot/ map directly. We should put
the code which adds the PIPE_MAP_DIRECTLY flag in mandatory cases before
the "bail and return NULL" check for cases where we can't do that.
We leave the "we would prefer to direct map this" cases after the error
check, since we -can- use blits for those, we'd just rather not. ASTC
also stays because even though it's tiled, our tiled memcpy paths work.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
Here, we're deciding when to map the buffer directly, rather than using
the GPU to blit to/from a temporary. There is already a flag for that,
PIPE_MAP_DIRECTLY, which has the added benefit of not being a negative
(such as "no_gpu").
Currently, we intend to map directly if:
1. Direct mappings were requested explicitly
2. Persistent or coherent mappings were requested (and so we must)
3. ASTC textures (we currently can't blit those correctly)
4. There is no need for a temporary (there's no image compression that
the CPU wouldn't understand, and we don't need to avoid stalls due
to the buffer being busy on the GPU)
Expressing "please memory map this directly" is easier to follow than
"please don't use the GPU as part of mapping this".
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
hang-detection is a vulkan-based lightweight wrapper from
parallel-deqp-runner that periodically submits empty command buffers
and waits for their completions. If the completion never happens, the
GPU is considered hung, the wrapped script is killed, and the job
should get aborted.
This should have no negative impact on the runtime of dEQP/traces/...,
but will allow saving time when the GPU gets hung as we can abort the
job immediately rather than waiting for the timeout.
In the case of B2C, we are using this tool's error message as a way to
trigger the reboot of the test machine and start again.
v2:
- Use hang-detection already with some jobs (Martin).
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11087>
Otherwise it will store a pointer to already unmapped memory which
could lead to a crash in tu_CmdPushDescriptorSetWithTemplateKHR since
it tries to copy data from the old memory.
Fixes a crash with Zink's new lazy descriptor manager instroduced
in bfdd1d8d
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11137>
It seems something went wrong during conversion of this article (or
maybe even before in the HTML version), where every header after the
"Gallium environment variables" header was nested below it.
That's clearly not what's meant here, so let's fix that.
This makes the toctree make a bit more sense for this article.
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11106>
This provides most of the implementation, but there are some
things we cannot enable until we improve of kernel submit
interface, namely:
We don't expose capacity to export SYNC_FD, although we do
have the implementation in place. This requires that we
improve our kernel interface and event wait implementation
first so we can cover the corner case where the application
submits a command buffer that includes a VkCmdWaitForEvents
and tries to export a SYNC_FD from its signal semaphores or
fence before it the event is signaled and the command buffer
is sent to the kernel for execution in full.
Likewise, we can't currently import semaphores. This is because
our current kernel submit interface can only take one syncobj.
We have been working around this so far by waiting on the last
syncobj produced from the device whenever we had to wait on any
semaphores (which is obviously suboptimal already), but this
won't work as soon as we allow importing external semaphores,
as those could (and would typically) be produced from a
different device.
Once we address the kernel bits, we should come back and enable
SYNC_FD exports as well as semaphore imports.
Relevant CTS tests:
dEQP-VK.api.external.fence.*
dEQP-VK.api.external.semaphore.*
dEQP-VK.synchronization.cross_instance.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11105>
We can (and should) close the descriptor immediately after the import.
Gets the following CTS test to pass without requiring to increase limits
for open file descriptors:
dEQP-VK.synchronization.basic.binary_semaphore.chain
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11105>
Fixes the following building error:
FAILED: out/target/product/x86_64/obj_x86/SHARED_LIBRARIES/i965_dri_intermediates/LINKED/i965_dri.so
...
ld.lld: error: undefined symbol: brw_compile_ff_gs_prog
>>> referenced by brw_ff_gs.c:56 (external/mesa/src/mesa/drivers/dri/i965/brw_ff_gs.c:56)
Fixes: 52e426fd8b ("intel/compiler: add support for compiling fixed function gs")
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10718>
When we remove the contents of the results directory, we `cd` into it.
The script expects that $PWD is /piglit, and $OLDPWD is the Mesa build
directory, however the cd into the results directory will make $OLDPWD
be $BUILDDIR/results.
This means that Piglit emits into results/results/ which looks weird,
but more importantly also fails OpenCL Piglit execution, because we
can't find our baseline result expectations.
Fix it by using an explicit variable rather than relying on history.
Fixes: 683ddf19dc ("ci: remove results directory content only with piglit runners")
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11126>
Android 29 introduced general-dynamic TLS variable support ("quick
function call to look up the location of the dynamically allocated
storage"), while Mesa on normal Linux has used initial-exec ("use some of
the startup-time fixed slots, hope for the best!"). Both would be better
options than falling all the way back to pthread_getspecific(), which is
the alternative we have pre-29.
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10389>
by using the bind counts, the common cases of rebinds can be immediately
handled without unnecessary iteration, and following this each rebind can
be evaluated to ensure that every necessary descriptor was rebound in order
to catch any remaining corner cases that may not be handled in the optimized
rebind path
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11093>
we want to avoid updating these values when possible in order to reduce
overhead, which means that if a descriptor is being replaced, it should
be updated only if the replacement is not the same resource
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11093>
this is the "lazy" descriptor manager, which aims to perform the least
amount of work calculating updates while ignoring the overhead that an
update may incur: effectively the inverse of the caching manager
in this initial implementation, divergence exists between the descriptor
layouts of the cached manager and the lazy manager in order to avoid
incurring regressions in the existing descriptor architecture; this will
be reconciled in a followup MR that refactors and unifies descriptor layouts
during this interim period and until such reconciliation occurs,
the default descriptor manager is now the lazy manager for testing purposes as
there are no changes here which can affect the existing infrastructure
the caching descriptor manager can be selected with the ZINK_CACHE_DESCRIPTORS
env var and will be automatically used for vulkan drivers which don't support
the features required for lazy mode (templates)
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11093>
We always want to reserve _something_, so reserve what we need at batch
creation time and stop trying to re-reserve in a zillion places after.
This has a neglible (<128 bytes per batch) increase in memory usage for
compute-only workloads, but given the amount of simplication, that's a
fair tradeoff.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11074>
We want dirty tracking for constant buffer uploads, but which dirty
flags are needed depend on what the sysvals are. So for each sysval,
record a corresponding dirty flag at compile time, so at draw-time the
check is easy.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11074>
If there is a preload job needing tiling, but no other jobs, then
first_tiler will be set but not tiler_dep.
Fixes faults when two depth-only (stencil is reloaded) clears are done
in a row.
panfrost ffa30000.gpu: Unhandled Page fault in AS1 at VA 0x0000000044870000
Reason: TODO
raw fault status: 0x49002C1
decoded fault status: SLAVE FAULT
exception type 0xC1: TRANSLATION_FAULT_LEVEL1
access type 0x2: READ
source id 0x490
panfrost ffa30000.gpu: gpu sched timeout, js=0, config=0x3301, status=0x8, head=0x608a300, tail=0x608a300, sched_job=f5b0862d
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11104>
Covert the job submission process to a python script for more
robustness and control. allowing easier manipulation of job data.
As a result, it adds retry logic to deal with Infrastructure Errors in LAVA.
_call_proxy() is equipped with a robust retry logic, which I have been
using already in the past few weeks in stress testing to run hundreds
of jobs.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11079>
We were using the CT0CA (Control List Executor Current Address) and
CT0EA (Control List Executor End Address) registers, but that would
only wait for the CLE to reach the end of the list, but there could
still be things in the rest of the pipeline.
Even if that seems to work with the current simulator, the correct way
to do that is using the BFC (Binning Mode Flush Count) and RFC
(Rendering Mode Frame Count) registers instead.
In fact, this would be needed with a newer simulator snapshot, in
order to get the followint CTS tests working:
dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.4_bit
dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit
dEQP-VK.api.copy_and_blit.core.resolve_image.whole_copy_before_resolving.4_bit
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail
dEQP-VK.api.image_clearing.core.clear_color_image.1d.optimal.multiple_layers.r32g32_uint
dEQP-VK.api.image_clearing.core.clear_color_image.1d.optimal.remaining_array_layers_twostep.r16_sint
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>
Until now we were waiting until having a dispatch current and/or
queued. But that would only wait for all shaders to have started, it
won't wait for them to have finished.
With this commit we wait until the NUM_COMPLETED_JOBS (that in spite
of that name, it is about dispatches) field got increased.
This is in general safest, and it is needed after the latest simulator
update to get CTS tests like the following ones working:
dEQP-VK.compute.basic.copy_ssbo_multiple_invocations
dEQP-VK.compute.basic.copy_ssbo_single_invocation
dEQP-VK.compute.basic.ssbo_rw_single_invocation
dEQP-VK.compute.basic.ssbo_unsized_arr_single_invocation
dEQP-VK.compute.basic.ubo_to_ssbo_multiple_invocations
dEQP-VK.compute.basic.ubo_to_ssbo_single_invocation
v2 (from Juan feedback):
* Clarify JOBS vs DISPATCHES
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>
Current code just assumes that flushes are instant, as simulator
doesn't really model the caches. So right now we have just an assert
that the flush has been done.
But that can change on the future, so let's change the assert for a
wait.
Note that for the l1t case we are writing on the field TMUWCF. So I
understand that then we need to wait for TMUWCF_SET, even if the
previous code was using L2TFLS_SET.
This also happpens on the kernel side. We need to check if this was a
typo on the kernel side.
v2 (from Juan feedback)
* Add comment about the TMUWCF vs L2TFLS difference between this
commit and the kernel.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>
So far we were not capturing any HUB interrupt, just core. This could
be a problem if any is fired, as we could enter on an infinite
loop. With this commit we start to capture them. So we split v3d_isr
into core and hub interrupt handling.
As reference we capture the same HUB interrupts that we capture on the
v3d kernel support.
It is worth to note that all those are mostly untested. Now with both
opengl/vulkan driver being stable we were not able to raise those
interrupts.
v2 (Juan feedback):
* Just one V3D_VERSION >= 41 block, more readable
* Assert that the core is 0 at v3d_isr_core (we don't handle
multi-core right now).
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>
We were using the num_components to infer it, but in the end it is
VEC2 for CMPXCHG and 32BIT for anything else.
This doesn't affect any test with the real hw, but fixes an assert
with the last version of the simulator.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>
Using stripes to deal with the different packet layout variants resulted
in redefining "register" offsets with different values, so use "prefix"
to add a suffix to disambiguate.
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1066: warning: "REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT" redefined
1066 | #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
|
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h:1057: note: this is the location of the previous definition
1057 | #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
|
(Admittedly it isn't really a "prefix" but that was the field in the
schema available to use, and REG_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE
sounds somewhat more funny.)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10944>
This runs through the SQE bootstrap code to extract the packet-table,
rather than relying on heuristics. As a bonus, it can detect the start
of the LPAC fw in a660+ fw so that we can properly decode the LPAC fw
and packet-table.
Note that this decodes the jmptable as normal instructions, which is a
change in behavior from the previous heuristic based jmptbl extraction.
Not sure if that is a good or bad thing.
For a5xx, for now the legacy heuristic based jmptable decoding is
preserved, at least until enough control regs are figured out.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10944>
This is an (at least somewhat complete) logical emulator of the a6xx SQE
that lets us step through firmware execution (bootstrap, cmdstream pkt
handling, etc). It lets us poke at various fw visible state and run
through pm4 packet(s) to better understand what the fw is doing when it
handles various packets.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10944>
Going beyond 0x100000 results in hangs, however I found that the
last 0x100000 packet just doesn't get executed. Thus the real limit is
0x0FFFFF. At least this is true for a6xx.
This could be tested by appending nops to the cmdstream and placing
e.g. CP_INTERRUPT at the end, at any position other than being
0x100000 packet it results in a hang.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10786>
There is a limit on IB size, which on freedreno is set to 0x100000.
Going beyond it results in hangs, however I found that the last
0x100000 packet just doesn't get executed. Thus the real limit is
0x0FFFFF.
This could be tested by appending nops to the cmdstream and placing
e.g. CP_INTERRUPT at the end, at any position other than being
0x100000 packet it results in a hang.
Fixes:
dEQP-VK.api.command_buffers.record_many_draws_secondary_2
dEQP-VK.api.command_buffers.record_many_draws_primary_2
However these tests could trigger hangcheck timeouts.
Also this fixes hangs when opening captures of games in RenderDoc.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10786>
There are some interactions between these two extensions that need to be
implemented when both are supported. Particularly:
1. Applications can create images that will be bound to swapchain memory
by passing a VkImageSwapchainCreateInfoKHR in the pNext chain
of VkImageCreateInfo. In this case we need to make sure that the
created image takes some of its parameters from the underlying
swapchain.
2. Applications can bind memory from a swapchain image to a VkImage
by passing a VkBindImageMemorySwapchainInfoKHR in the pNext chain
of VkBindImageMemoryInfo.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11037>
This was added with VK_KHR_device_group and allows users to specify
a base offset that will be automatically added to gl_WorkGroupID.
Unfortunately, V3D doesn't support this natively, so we need to add
the base to the workgroup id generated by hardware manually. For this,
we inject add instructions that source from a QUNIFORM that will
retrieve the actual dispatch base from the compute job when it is
dispatched.
Since a compute shader can be dispatched with CmdDispatch and/or
CmdDispatchBase, we always need to add these additional add
instructions and use a base of (0,0,0) for regular dispatches.
Since we don't support any version of OpenGL with this dispatch
base functionality we can avoid the extra instructions there.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11037>
Construct a scissor descriptor correpsonding to the intersection of the
framebuffer, the viewport, and the region selected for scissoring by the app.
Use the intersected scissor in the "clip tile" fields in the viewport. Select
this scissor descriptor from the command stream.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11084>
When drawing using util_translate_prim_restart_ib, zink explicitly
ignores pipe_draw_start_count_bias::start, because
util_translate_prim_restart_ib used to create a new index-buffer without
padding at the start.
This makes a lot of sense, because creating a padded index buffer is
just wasteful.
So let's walk back on the choice of starting to pad the output buffer.
Fixes: 1272c2e052 ("util/prim_restart: fix util_translate_prim_restart_ib")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4851
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11059>
Spec requires apps to use the size returned from
vkGetAndroidHardwareBufferPropertiesANDROID for AHB import, which
includes dedicated image/buffer import and non-dedicated buffer import.
Spec requires venus to use the size from image and buffer memory
requirement for dma_buf fd import if it's dedicated. If not dedicated,
the actual payload size should be used.
For AHB export allocation of VkImage, the app provided size will be 0,
and internally we must use the size from image memory requirement.
For AHB export allocation of VkBuffer, the app provided size comes from
buffer memory requirements and it can be smaller than the actual AHB
size due to page alignment. Internally that's the size we must use.
For AHB import, app must use the size from AHB prop query. Internally,
we have to override that with the size from memory requirement if the
import operation is dedicated to a VkImage or a VkBuffer. If not
dedicated, the actual payload size should be used.
The not working scenario is:
1. App creates an AHB backed VkBuffer, and the exported AHB size is
larger than the buffer memory requirement (very common).
2. App imports the AHB without a dedicated VkBuffer. Then the entire
AHB payload will be imported and the mmap_size might increase.
Test: dEQP-VK.api.external.memory.android_hardware_buffer.*
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11055>
For importing an dma_buf fd, export info is not required. Leaving the
bo_flags missing VIRTGPU_BLOB_FLAG_USE_SHAREABLE bit as well as the
VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE bit. Upon querying fd properties,
DMA_BUF handle type will be specified which generates a new bo_flags
not matching the prior one.
This patch aligns the above 2 bits for the dma_buf import path.
Test: vkGetAndroidHardwareBufferPropertiesANDROID should succeed with
a valid AHB with AHARDWAREBUFFER_FORMAT_BLOB format.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11055>
It is valid to not have a sampler view declaration for the corresponding
sampler in a TGSI shader, and hence we should not rely on the sampler view
declaration to determine if we need to adjust the unnormalized coordinates
for texture rectangle sampling.
This patch is to prep for tgsi shaders that are translated from nir which
in many cases do not issue sampler view declarations.
Fixes: 584b107037 ("st/mesa: Drop the TGSI paths for drawpixels and use nir-to-tgsi")
Reviewed-by: Neha Bhende <bhenden@vmware.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11011>
Sometimes, TGSI shader doesn't have SVIEW declaration if it is not
utilize in shader. In such cases, declare those resources with the
help of information stored in shader key.
Fixes: 584b107037 ("st/mesa: Drop the TGSI paths for drawpixels and use nir-to-tgsi")
Tested with piglit, gleretrace
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11011>
A simple post-RA optimization which takes advantage of the
s_cbranch_vccz and s_cbranch_vccnz instructions.
It works on the following pattern:
vcc = v_cmp ...
scc = s_and vcc, exec
p_cbranch scc
The result looks like this:
vcc = v_cmp ...
p_cbranch vcc
Fossil DB results on Sienna Cichlid:
Totals from 4814 (3.21% of 149839) affected shaders:
CodeSize: 15371176 -> 15345964 (-0.16%)
Instrs: 3028557 -> 3022254 (-0.21%)
Latency: 21872753 -> 21823476 (-0.23%); split: -0.23%, +0.00%
InvThroughput: 4470282 -> 4468691 (-0.04%); split: -0.04%, +0.00%
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7779>
This commit adds the skeleton of a new ACO post-RA optimizer,
which is intended to be a simple pass called after RA, and
is meant to do code changes which can only be done
after RA.
It is currently empty, the actual optimizations will be added
in their own commits. It only has a DCE pass, which deletes
some dead code generated by the spiller.
Fossil DB results on Sienna Cichlid:
Totals from 375 (0.25% of 149839) affected shaders:
CodeSize: 2933056 -> 2907192 (-0.88%)
Instrs: 534154 -> 530706 (-0.65%)
Latency: 12088064 -> 12084907 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 4433454 -> 4432421 (-0.02%); split: -0.02%, +0.00%
Copies: 81649 -> 78203 (-4.22%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7779>
Technically, this is correct, and I think it's the right long-term
solution. However, Iris has code that undoes the damage caused by
nir_lower_passthrough_edgeflags (see iris_fix_edge_flags in
iris_program.c), so it should be safe to do the lowering here.
I'm not marking this as closing mesa#4838 because I think we should move
the Iris code up to here, make a different version of the NIR pass, or
something different... to properly fix this problem. In the mean time,
this gets a bunch of tests to stop crashing. :)
Fixes: a76ec17f12 ("mesa/st: Fix iris regression with clip distances.")
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11013>
The CTS expects that some paths transfer SNORM data exactly, but the HW
will clamp 0x80 values to 0x81 in the process. We can treat snorm as
unorm, though, and get working compression without the clamping happening.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10735>
Now that we need FALLTHROUGH macros we weren't saving much by falling
through, and things were weirdly ordered anyway with depth intermixed with
color formats and the default case tucked in the middle of the switch
statement. Replace with pretty obvious ordering of normal color, planar
color, depth, then default.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10735>
Configure a panfrost performance structure with tables of categories and
counters for the current product id. An array for storing counter values
read from the GPU is also managed by this structure. A generic read
function can be used to retrieve the value of a counter from the conter
values array.
v2: Generate tables instead of calling register functions.
v3: Simplify counter read function and `pan_gen_perf.py` write method.
v4: Accumulate counter values from all cores.
v5: Wrap `STATIC_ASSERT`s within unused functions.
Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10844>
This reverts commit 8e470457de.
Drop that jobs, as it's sometimes causing a gitlab-ci.yml parse error
that isn't readily reproducible:
Found errors in your .gitlab-ci.yml:
'a630-profile-traces' job needs 'arm_test' job but it was not added to the pipeline
'a630-profile-traces' job needs 'meson-arm64' job but it was not added to the pipeline
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11030>
barriers just trigger a full flush, which is unnecessary if it's:
* the first cmd in a cmdbuf, as the previous cmdbuf will have already
flushed and so this is flushing nothing
* the last cmd in a cmdbuf, as there will be a flush immediately after
returning from this function
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10762>
this was added in 315f8daab1 without much detail, then refactored
a bunch of times, and there's even now been a comment added questioning
whether it's correct: it does not appear to be.
fixes lavapipe cts cases:
dEQP-VK.draw.inverted_depth_ranges.depthclamp_deltaone_bias_clamp_neg
dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_deltaone_bias_clamp_neg
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11012>
The quick_gl set is too unstable -- even when I switched to a consistent
set of tests, and added lots of flakes, I keep getting new ones as some
test (unclear which, but it's like 7-8 minutes into the run) kills other
innocent ones. Until we get per process pagetables, disable this testing
by default.
However, now that we've freed up a board that was doing quick_gl, we have
time to do all of quick_shader so that piglit uprevs don't reshuffle the
test list and expose new failures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11018>
Use Piglit's replay profile to measure and store the time that frames
take to render in the GPU.
This job won't run automatically in regular pipelines, but will be
triggered automatically by a script for every successful pre-merge
pipeline.
This is because we want to generate performance data for every relevant
commit merged in main, but we don't want to keep a device busy during
the pre-merge run.
Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-By: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7987>
Now that the compile entrypoints don't touch the context, it's clear
that we can support this. Note, even though the pools for shaders and
descriptors are referenced from particular contexts, they are unowned
pools -- once uploaded, any thread can use the results.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10976>
For fragment shaders that only contain a discard, the exec mask has
to be zero'd and everything discarded.
It seems unnecessary to emit an export here because if the FS has no
exports, the compiler already emits a null export at the end.
Fixes incorrect hair rendering in Detroit: Become Human.
fossil-db (Sienna Cichlid):
Totals from 3 (0.00% of 149839) affected shaders:
CodeSize: 2896 -> 2872 (-0.83%)
Instrs: 556 -> 553 (-0.54%)
Latency: 29266 -> 29214 (-0.18%)
InvThroughput: 3374 -> 3372 (-0.06%)
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10955>
We don't have any special restrictions associated with the number
of descriptors in a set other than maybe not exceeding what we can
put in a single memory allocation, so in practice, applications will
be limited by the per-stage contraints defined by other Vulkan limits.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10970>
In order to reduce the amount of building work and network traffic, we
use docker caching. For that, we use the MESA_IMAGE_TAG and
MESA_BASE_TAG env variables which build the MESA_IMAGE variable to
identify different containers.
We are also using these tags to identify the cached artifacts produced
by other containers when those are part of the underlying OS to run
directly in DUTs through the DISTRIBUTION_TAG env variable.
The undesirable collateral effect is that we cannot combine a test job
using a container which would like to make use of some of the cached
artifacts created by another container. In other words, we cannot have
a job using a DISTRIBUTION_TAG and a MESA_IMAGE using a different
MESA_[IMAGE|BASE]_TAG variables.
Now, we split the usage in the DISTRIBUTION_TAG through the definition
of MESA_ARTIFACTS_TAG AND MESA_ARTIFACTS_BASE_TAG.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10977>
there's not actually any reason to do these during draw other than wasting
cpu cycles, and it has the side benefit of providing a bunch more info for rebinds
image resources for gfx shaders need to have their barriers deferred until draw time,
however, as it's unknown what layout they'll require until that point due to potentially
being bound to multiple descriptor types
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
the descriptor layouts are the last component needed to create the pipeline
layout, so it makes sense to streamline setup by having the pipeline layout
created from a single place for both types of pipelines
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10849>
Enable EGL_KHR_mutable_render_buffer when below conditions are met:
1. Driver part implementation of this extension is available
2. Loader part implementation of this extension is available
3. ClientAPIs must be OpenGL ES bits (ES, ES2 or ES3)
4. Gralloc is cros gralloc and it supports front render usage query
(4) is optional as long as another gralloc supports similar query.
Upon window surface creation, if the surface type has mutable render
buffer, then append the cached front rendering usage to the existing
usage and properly set to the ANativeWindow.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10685>
Unlike front buffer used by big GL API for front rendering,
EGL_KHR_mutable_render_buffer together with ES redirects GL_BACK to the
front buffer.
This patch adds a fallback to use back buffer and ensures no behavior
change for unrelated frontends.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10685>
Instead of storing the vertex mask per wave into LDS and then computing
the prefix sum, store 8-bit bitcounts (vertex counts) of the vertex masks
into LDS. This allows us to compute the sum using v_sad_u8, which computes
a sum of 4 i8vec4 components in one instruction.
Each i8vec4 of vertex counts is loaded in parallel threads (one dword
per thread) instead of all being loaded in thread 0, and readlane copies
them to SGPRs instead of readfirstlane.
LDS is no longer initialized before culling. Instead, the counts for
inactive waves are masked with AND later.
Incorrect old comments are also fixed.
This change removes 80 bytes from the code size, and it allows increasing
the workgroup size from 128 to 256. (which is the main motivation for this)
Now changing the workgroup size with wave64 has no effect on the code size.
Switching to wave32 with 8 waves even generates slightly smaller code than
wave64 with 4 waves.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
If a shader has no param exports (no varyings), the pixel shader can start
after the VS position is written before the vertex shader finishes.
The fix is to wait for the memory stores before the position export.
The code needs to be restructured. First prepare param exports to get
nr_param_exports, then emit position exports with the wait, and then
emit param exports.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
This way if there's a fault, the pipeline won't accidentally pass
and let bugs slip into main. This seems to have occurred on both T720
and G72, leading to flakes on both. I want flakeless CI, so this is a
step in eliminating flakes before they hit the tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
It's reliably faulting in CI but not locally, and I can't figure out
what the difference could possibly be. Regardless I can't fix the fault
otherwise, and faultless CI matters more than losing a single trace
(from an app I manually test anyway).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
We previously allocated only 16MB, but this isn't always enough. Now
that we have growable (heap) on recent kernels, there's not much reason
to try to shrink this allocation.
Fixes OUT_OF_MEMORY fault on furmark trace.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
This allows failing fast (optionally still tracing, if set with
PAN_MESA_DEBUG=trace) when a GPU fault is introduced. This is better
behaviour for both use cases:
1. When debugging a known fault, setting this mode together with trace
will stop the driver as soon as a buggy command stream is submitted,
and the offending stream will be the last trace file.
2. When running test suites (particularly in CI), setting this mode
will detect faults and crash, causing the pipeline to fail fast as
opposed to incorrectly marking the run green if the test happens to
pass despite the faults and slow downs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
Some resources like backbuffers are explicitly flushed by the frontend
at the appropriate time, others however won't get flushed explicitly.
Remember those resources when they get emitted as a render buffer and
flush them on a context flush to make their content visible to other
entities sharing the buffer.
We still keep the optimized path for most resources where the frontend
promises to do the flushing for us and only enable implicit flushing
when a buffer handle is exported/imported without the
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH flag set.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
dri2_resource_get_param() is called from two different places right now.
Only one of them adds the EXPLICIT_FLUSH hint to the handle usage, which
may disable the optimizations provided by this hint without a reason.
Make sure to always add this hint when appropriate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7603>
We don't do anything for input attachment aspects read by a subpass
since it doesn't have performance implications for us.
We also ignore the the new depth stencil layouts because they don't
have practical implications for our implementation.
We also ignore the new usage info for views since we are not currently
making decisions about views based on their usage.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10951>
This is the combination of two simplifications I spotted while
researching some other issue:
1. We can use nir_const_value_as_uint to save some conditionals
2. We can unify the vector and scalar code-paths to reduce some
duplicated logic.
While we're at it, switch to using NIR_MAX_VEC_COMPONENTS rather than a
dynamic array size on the stack, because that tends to generate better
code.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10956>
ci-fairy minio ls will try to list files in the path given, which for
trace buckets is generally forbidden. We don't really need to do any
listing in this case, so use wget instead to check that the reference
image doesn't exist yet.
Previous to this patch, trace jobs would re-upload all reference images
to minio every time because they wouldn't be able to verify that the
reference image was already there. Jobs would often take up to 4 minutes
needlessly re-uploading these files.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10953>
A successful AHardwareBuffer_allocate itself will increase a refcount on
the newly allocated AHB. For the import case, the implementation must
acquire a reference on the AHB. So if we layer the exportable allocation
on top of AHB allocation and AHB import, we must release an AHB
reference to avoid leak.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10940>
A successful AHardwareBuffer_allocate itself will increase a refcount on
the newly allocated AHB. For the import case, the implementation must
acquire a reference on the AHB. So if we layer the exportable allocation
on top of AHB allocation and AHB import, we must release an AHB
reference to avoid leak.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10940>
If the varying descriptors will always be the same for a given shader
variant (certainly true if none of separable shaders, transform
feedback, or point sprites are used), we only need to link once. Now
that pan_pool supports both owned and unowned modes, we have the
flexibility to reuse the code path for both allocation strategies.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10954>
In general gallium shaders are all SSO and it's up to the driver to handle
lining up varying storage between stages at draw time. However, there's a
NIR option "unify_interfaces" that iris uses which applies to non-SSO (as
indicated by nir->info.separate_shader) shaders and makes the inputs_read
and outputs_written match up at GLSL-to-NIR link time, and then iris then
avoids any lowering passes that would add new varyings.
By introducing info gathering after variant creation (because all I knew
was "gallium is always SSO"), I broke the unify_interfaces link-time setup
on iris. Just skip that when the unify_interfaces flag is set, and add
some asserts to catch anyone trying to mix unify_interfaces with known
varying-adjusting lowering passes.
Closes: #4450
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10876>
Panfrost has two compilers, one for Midgard GPUs and one for Bifrost
GPUs. The respective compilers are src/panfrost/midgard and
src/panfrost/bifrost. Changes internal to just one compiler (or
disassembler) cannot affect the other hardware, so there's no need to
run extra jobs in these cases.
Also split out common vs Gallium panfrost so we can do the right thing
for panvk builds in the imminent future.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10924>
To avoid having to download the same traces again and again in each job,
use the caching proxy configured in the Collabora lab.
We can currently hardcode it like this because we don't test the same
driver in more than one lab, but when that changes we will need a more
flexible approach.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10949>
With display on iGPU and render on dGPU, VRR is not working. To fix
this set RADEON_FLAG_GTT_WC flag when allocating memory for prime. This
allows kernel function amdgpu_display_user_framebuffer_create() to
allocate GTT memory with USWC flag making the buffer scanout for iGPU.
This helps the ddx amdgpu_present_check_flip() function to return
true. Now, xserver will flip the framebuffer instead of blit. Due
to this VRR feature will work where iGPU supports USWC flag.
v2: modify commit message with use case (Michel Dänzer)
v3: allow GTT_WC flag only if VRAM_DOMAIN and NO_CPU_ACCESS (Bas Nieuwenhuizen)
v4: add check for wsi_info is NULL
v5: use wsi_info pointer to check for prime alloc (Bas Nieuwenhuizen)
v6: set _GTT_WC flag when wsi_info pointer is not NULL (Bas Nieuwenhuizen)
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10657>
On XeHP there are restrictions on types of source and destinations
with float types. As shuffle is implemented using MOV we need to make
sure we lower it to supported types.
This fixes tests like :
dEQP-VK.subgroups.arithmetic.framebuffer.subgroupexclusivemax_vec4_vertex
dEQP-VK.subgroups.arithmetic.framebuffer.subgroupexclusivemul_f16vec3_vertex
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10902>
Removing the directory itself can be problematic with certain runner
strategies (B2C).
v2:
- Better deleting pattern matching since the previously used one was
problematic and not pointed out by /bin/sh, as noticed by Emma.
v3:
- Check that the results directory exists before attempting to
delete its content.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
Only the AMD video drivers for xorg are added since there are no other
expected users by now.
v2:
- Remove the start/stop logic from the x.sh script. We don't care
about stopping since that's already managed by gitlab-ci (Emma).
v3:
- Remove mistakenly added ".gitlab-ci/common/start-x.sh"
script (Martin).
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10856>
Fixes perf regression introduced from tileY LID order for CS
shaders that access both textures and buffers. Walks LIDs in
X-major fashion, but with blocks of height 4. This maps LIDs per
HW thread for SIMD8/16/32 as (2x4/4x4/8x4), which is always good
for tileY resources and usually good for linear resources.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10733>
Computer shaders that access tileY resources (textures) benefit
from Y-locality accesses. Easiest way to implement this is walk
local ids in Y-major fashion, instead of X-major fashion. Y-major
local ids will reduce partial writes and increase cache locality
for tileY accesses since tileY resources cachelines progress in
Y direction.
Improves performance on TGL:
Borderlands3.dxvk-g2 +1.5%
Y-major can introduce a performance drop on CS that use mixture
of buffers and images. This should be fixed in next commit.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10733>
I forgot that after rebasing on large_consts support that this is now
called after the first time nir_lower_wrmask is called and can generate
partial writemasks that need to be lowered. While we're here, also call
the main optimization loop if things are lowered to scratch because it
generates address arithmetic that may need to be cleaned up.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10922>
There's a bug in ATEST (and LD_TILE?) handling affecting v6, manifesting
as gpu sched timeouts in dmesg and ultimately as random dEQP flakes.
Until this can be sorted out and the G72 jobs are proven to be stable,
we can't have them in the critical merge path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10923>
I've been meaning to make this change for a while, but I've been holding
out in case dEQP-GLES2 on T860/Bifrost catches a driver issue missed by
dEQP-GLES3 and also missed by T720's dEQP-GLES2 job. Given that hasn't
happened (indeed, dEQP-GLES3 is an effective super set of dEQP-GLES2),
let's save the cycles and skip the redundant jobs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10923>
this was broken for the indirect case if the indirect draw count or
firstIndex was nonzero and also would rewrite the index buffer onto the
wrong offset of the dst buffer
Fixes: 0c85d6c523 ("gallium/util: factor out primitive-restart rewriting logic")
Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10909>
The wayland EGL platform sets the modifier count to 0 in some cases
to signal that modifiers should not be used, even if a list of modifiers
is present. The loader_dri_create_image helper didn't handle this case
properly and called the modifierful driver interface with a 0 modifier
count, leading to the obvious outcome of the driver being unable to
allocate an image.
Fixes: cb9ae4273d ("dri: add loader_dri_create_image helper")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10903>
SCS_ONE and ISL_CHANNEL_SELECT_ONE (and SCS_ZERO and
ISL_CHANNEL_SELECT_ZERO) have the same values, so this doesn't matter in
practice. However, some compiler warning options will cause warnings to
be generated.
src/gallium/drivers/iris/iris_state.c: In function ‘fmt_swizzle’:
src/gallium/drivers/iris/iris_state.c:2177:32: warning: implicit conversion from ‘enum GFX125_ShaderChannelSelect’ to ‘enum isl_channel_select’ [-Wenum-conversion]
2177 | case PIPE_SWIZZLE_1: return SCS_ONE;
| ^~~~~~~
src/gallium/drivers/iris/iris_state.c:2178:32: warning: implicit conversion from ‘enum GFX125_ShaderChannelSelect’ to ‘enum isl_channel_select’ [-Wenum-conversion]
2178 | case PIPE_SWIZZLE_0: return SCS_ZERO;
| ^~~~~~~~
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
These aren't real formats. They cannot be used with
RenderbufferObjects, Textures, or anything else visible through the GL
API. The only purpose is to support YUYV textures imported through
EGL_image_external. There is hardware that can sample from this
subsampled format, but the hardware does not do the colorspace
conversion automatically.
v2: Treat these formats as compressed. This is a lie, but it seems to
be a less egregious lie than what I was doing before. It also passes
'ninja test'.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
v2: Add all the Y21x tests to the A530 expected fail list. All of the
YUV image import tests fail on this platform, and nobody has been able
to investigate why.
v3: Update the comment describing the zeroed bits in Y212. Suggested by
Emma.
v4: Add all Y21x test to the rpi3 expected fail list.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
v2: Don't leak __DRI_IMAGE_FOURCC_RGBA16161616 to applications.
v3: Fix typo in __DRI_IMAGE_FOURCC_RGBA16161616 table entry.
v4: Add the Y412 and Y416 tests to the A530 expected fail list. Many
YUV image import tests fail on this platform, and nobody has been able
to investigate why.
v5: Update the comment describing the zeroed bits in Y412. Suggested by
Emma.
v6: Add all Y41x test to the rpi3 expected fail list.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
These are similar to AYUV, but the channel ordering is different... in
such a way that there's no RGBA format that will make the channels line
up right.
v2: Rebase on bc438c91d9 ("nir/lower_tex: ignore texture_index if
tex_instr has deref src")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with PIPE_BIND_SCANOUT set,
which we can't support. That led to crashes later when we tried to
create such an image, and isl rightly denied it.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with __DRI_IMAGE_USE_SCANOUT
set, which we can't support. That led to crashes later when we tried
to create such an image, and isl rightly denied it.
This duplicates a bit of code from ISL, but the isl_gfx6_filter_tiling
function that we ought to use to filter things relies on surf_info,
which we don't have at this stage. This is probably good enough.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
The DIFFUSE thing would write an undefined result if the shader that
failed to compile didn't read VARYING_SLOT_COL0, causing flakes in CI.
This does make 2 piglit tests that were expecting red spuriously pass.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
The 3D-pipeline fast clears try to emit FS constants before an FS is
necessarily bound, causing segfaults in dEQP. Plus it flushes the whole
batchbuffer so it'll probably be slower anyway.
Fixes: 6358e6371b ("i915g: implement hw clear")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
We're supposed to map a floating-point value too large to be represented
as fp16 to infinity, however round-to-zero naturally rounds it down to
the largest representable fp16 number instead. The blob emits a bunch of
fixup code to work around this, but instead we can just do what all the
other drivers seem to do and use round-to-nearest-even instead.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10897>
Refactor all the linking code with the following objectives:
* Remove linking magic (especially around XFB)
* Cleaner code (obviously)
* Less stage coupling (in case someone ever implements geom/tess)
* Decouple ATTRIBUTE from ATTRIBUTE_BUFFER to enable optimizations
The main hack remaining is doing precision linking here to workaround
linking previously used.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
The CAP for packed transform feedback concerns packing of unrelated
variables into the same varying slot. (On Mali, transform feedback is
implemented on a per-slot basis, so different variables need different
slots to be written to different buffers.) However, this requirement is
tangential to the packing of arrays, matrices, and structures inherent
to GLSL. These array-like values need to be packed /within/ their slot,
even though drivers using the CAP (just Panfrost) cannot pack
independent values in the slot. Transform feedback of individual
elements is not independent, after all.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
We need to duplicate the subscripted members even if they happen to be
aligned, since the other elements may be passed into the consumer
shader. Fixes on Panfrost:
dEQP-GLES3.functional.transform_feedback.array_element.interleaved.lines.highp_float
Note: the test did pass on main previously due to an elaborate set of
driver hacks. I don't believe the old behaviour was correct regardless.
Only Panfrost is affected by this change and the next, as every other
driver sets PIPE_CAP_PACKED_STREAM_OUTPUT.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
Typically, we program the framebuffer dimensions using the destination
surface, however, if we blit a rect from a surface that is smaller than
the destination, the simulator will complain that the TLB load stride
is not large enough to match the destination framebuffer. We can work
around this by programming the smallest size of both surfaces, which
should be okay because the tlb blit path requires that the blit
coordinates are the same for both src and dst.
Fixes assert crashes with the simulator for MSAA tests in:
./bin/gl-1.0-logicop
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10863>
The flt version could have been added in 56e21647e2, but our
collective understanding of NaN and comparisons was poor in 2015. The
new "is_a_number" predicate makes the others possible.
All of the helped shaders in shader-db are either from Mad Max or Skia.
Some of the Skia shaders just get decimated by this change:
instructions helped: shaders/skia/580-4.shader_test FS SIMD8: 81 -> 29 (-64.20%) (scheduled: top-down)
I looked at a couple of those shaders, and they had sequences like:
vec1 32 ssa_44 = flt32 ssa_32, ssa_32
vec1 32 ssa_45 = b32csel ssa_44, ssa_43, ssa_0
vec1 32 ssa_46 = fge32 ssa_32, ssa_32
vec1 32 ssa_47 = b32csel ssa_46, ssa_0, ssa_45
vec1 32 ssa_48 = iand ssa_46, ssa_44
vec1 32 ssa_49 = b32csel ssa_48, ssa_43, ssa_0
ssa_44 is replaced with False. Then ssa_47 selects between ssa_0 and
ssa_0, so ssa_47 and ssa_46 are eliminated. ssa_48 is (False && don't
care), so ssa_48 and ssa_49 are eliminated. After that, many
calculations now involve constants of zero, so they are optimized down
too. So it continues until there's not much left!
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 21072238 -> 21071386 (<.01%)
instructions in affected programs: 33722 -> 32870 (-2.53%)
helped: 146
HURT: 1
helped stats (abs) min: 1 max: 62 x̄: 5.84 x̃: 2
helped stats (rel) min: 0.19% max: 62.35% x̄: 4.09% x̃: 1.07%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.20% max: 0.20% x̄: 0.20% x̃: 0.20%
95% mean confidence interval for instructions value: -7.94 -3.65
95% mean confidence interval for instructions %-change: -5.87% -2.25%
Instructions are helped.
total cycles in shared programs: 856203326 -> 856192238 (<.01%)
cycles in affected programs: 749966 -> 738878 (-1.48%)
helped: 148
HURT: 0
helped stats (abs) min: 1 max: 1226 x̄: 74.92 x̃: 18
helped stats (rel) min: 0.07% max: 49.70% x̄: 2.69% x̃: 0.46%
95% mean confidence interval for cycles value: -104.82 -45.02
95% mean confidence interval for cycles %-change: -4.01% -1.37%
Cycles are helped.
LOST: 4
GAINED: 0
Fossil-db results:
Tiger Lake
Instructions in all programs: 160915223 -> 160898354 (-0.0%)
SENDs in all programs: 6812780 -> 6812780 (+0.0%)
Loops in all programs: 38340 -> 38340 (+0.0%)
Cycles in all programs: 7434144207 -> 7433978462 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304537 -> 304537 (+0.0%)
Ice Lake
Instructions in all programs: 145296298 -> 145279531 (-0.0%)
SENDs in all programs: 6863692 -> 6863692 (+0.0%)
Loops in all programs: 38334 -> 38334 (+0.0%)
Cycles in all programs: 8800257014 -> 8800088384 (-0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334248 -> 334248 (+0.0%)
Skylake
Instructions in all programs: 135891664 -> 135874910 (-0.0%)
SENDs in all programs: 6802946 -> 6802946 (+0.0%)
Loops in all programs: 38331 -> 38331 (+0.0%)
Cycles in all programs: 8444273433 -> 8444130932 (-0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301114 -> 301114 (+0.0%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
If the values are known to be numbers, the the replacements are exact.
This is only applied to the patterns with constants. Constants should
always be numbers, and shaders with NaN constants should be handled in a
different way.
No shader-db or fossil-db changes on any Intel platform. The intention
is to make these patterns more future proof.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Haswell and later Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 21049056 -> 21048939 (<.01%)
instructions in affected programs: 4716 -> 4599 (-2.48%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.99% max: 5.43% x̄: 2.80% x̃: 2.51%
95% mean confidence interval for instructions value: -3.46 -2.54
95% mean confidence interval for instructions %-change: -3.22% -2.38%
Instructions are helped.
total cycles in shared programs: 855141411 -> 855141159 (<.01%)
cycles in affected programs: 54491 -> 54239 (-0.46%)
helped: 28
HURT: 5
helped stats (abs) min: 2 max: 34 x̄: 12.82 x̃: 12
helped stats (rel) min: 0.06% max: 2.73% x̄: 0.94% x̃: 0.75%
HURT stats (abs) min: 2 max: 52 x̄: 21.40 x̃: 6
HURT stats (rel) min: 0.11% max: 2.46% x̄: 0.90% x̃: 0.56%
95% mean confidence interval for cycles value: -13.72 -1.55
95% mean confidence interval for cycles %-change: -1.01% -0.31%
Cycles are helped.
Tiger Lake
Instructions in all programs: 160902191 -> 160899554 (-0.0%)
SENDs in all programs: 6812435 -> 6812435 (+0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs: 7428581420 -> 7428555881 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304539 (+0.0%)
A lot of fragment shaders in Shadow of the Tomb Raider were helped, and
a bunch of vertex shaders in Octopath Traveler were hurt.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
It seems worth the small amount of damage to give an extra cushion of
not having to debug problems later.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs: 21043197 -> 21043359 (<.01%)
instructions in affected programs: 4409 -> 4571 (3.67%)
helped: 0
HURT: 25
HURT stats (abs) min: 1 max: 16 x̄: 6.48 x̃: 5
HURT stats (rel) min: 0.39% max: 15.38% x̄: 4.59% x̃: 4.40%
95% mean confidence interval for instructions value: 4.37 8.59
95% mean confidence interval for instructions %-change: 2.93% 6.26%
Instructions are HURT.
total cycles in shared programs: 856175986 -> 856176921 (<.01%)
cycles in affected programs: 58908 -> 59843 (1.59%)
helped: 0
HURT: 25
HURT stats (abs) min: 7 max: 70 x̄: 37.40 x̃: 38
HURT stats (rel) min: 0.27% max: 5.63% x̄: 1.87% x̃: 1.39%
95% mean confidence interval for cycles value: 31.11 43.69
95% mean confidence interval for cycles %-change: 1.35% 2.39%
Cycles are HURT.
No fossil-db changes on any Intel platform.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
When most of these patterns were created, we believed, incorrectly, that
fsat(NaN) was NaN. We have since realized that fsat(NaN) is zero.
Originally, this changed the patterns to use is_a_number. This didn't
help any shaders, so it's easier to just drop the optimizations.
This commit crossed paths with 4c3ad4d065 ("nir/algebraic: mark more
optimization with fsat(NaN) as inexact") and bc123c396a
("nir/algebraic: mark some optimizations with fsat(NaN) as inexact").
Given that these don't impact very many shaders, it seems safer to just
remove them.
As discussed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8716, I tried
modifying these patterns to use !(b cmp a). Unfortunately, on Intel
GPUs, the results were much worse than just removing the patterns
altogether.
Some other related patterns will be addressed in later commits.
There are still a number of patterns that use the identity fsat(1-X) ==
1 - fsat(X). If X is NaN, the former is zero while the latter is 1.0.
I haven't evaluted these patterns yet. If changes are needed in these
patterns, it should be a separate commit anyway.
v2: Replace arrow `=>` with `->` in comments because the `=>` looks a
lot like `<=` comparison. Suggested by Rhys.
Fixes: 92b75c126b ("nir/algebraic: Replace checks that a value is between (or not) [0, 1]")
Fixes: a7f0c57673 ("nir/algebraic: Eliminate useless fsat() on operand of comparison w/value in (0, 1)")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel hardware had similar results. (Ice Lake shown)
total instructions in shared programs: 20029060 -> 20029670 (<.01%)
instructions in affected programs: 69236 -> 69846 (0.88%)
helped: 0
HURT: 263
HURT stats (abs) min: 1 max: 20 x̄: 2.32 x̃: 1
HURT stats (rel) min: 0.30% max: 11.11% x̄: 1.35% x̃: 0.98%
95% mean confidence interval for instructions value: 1.86 2.78
95% mean confidence interval for instructions %-change: 1.18% 1.52%
Instructions are HURT.
total cycles in shared programs: 979821278 -> 979834425 (<.01%)
cycles in affected programs: 1476848 -> 1489995 (0.89%)
helped: 49
HURT: 204
helped stats (abs) min: 1 max: 812 x̄: 102.31 x̃: 20
helped stats (rel) min: 0.01% max: 21.43% x̄: 2.23% x̃: 0.52%
HURT stats (abs) min: 2 max: 2600 x̄: 89.02 x̃: 16
HURT stats (rel) min: 0.04% max: 27.27% x̄: 1.49% x̃: 0.72%
95% mean confidence interval for cycles value: 13.18 90.75
95% mean confidence interval for cycles %-change: 0.29% 1.25%
Cycles are HURT.
No fossil-db changes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
As Mesa d3d12 is currently implemented, all resource data is static
at the time a SRV or CBV is created. Therefore, it makes sense for all
descriptors to use the DESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKS
flag. Use of this flag broadens debug validation and allows some
optimizations in the underlying driver.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10871>
Some GL applications, including Blender, are producing rendering
artifacts due to missing resource state barriers.
The d3d12_context keeps track of all resources bound as shader resource
or constant buffers. If any of these resources are used for Copy,
Resolve, or Clear source/target, the context tracking must be updated
so the correct state can be restored before the next draw call.
This change is something of a big hammer. Essentially, if a resource
currently bound as an SRV or CBV gets used for a non-shader access, a
flag is set in the context that invalidates all bindings of the same
type on the same shader stage. Thus the next Draw execution refreshes
the shader views and state transitions state before invoking Draw on the
command list.
A more elegant (and complex) fix would limit the invalidation to
resource state only, rather than also forcing a recreation of resource
views. It is unclear right now whether it is worth the time to
implement a more elegant fix.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10871>
The old pass had a few bugs:
- It tried to avoid folding f2f32 into f2f16, but didn't consider
conversions that were already folded in.
- It didn't prevent folding an f2f16 or f2f32 into a non-floating-point
op.
In addition it wasn't written in a manner which made handling integer
conversions practical. This rewrites the pass to instead calculate the
"type" of the conversion source and then check whether folding the
conversion is allowed. This allows us to cleanly separate the
declarative part where we describe how the HW works from the policy part
where we decide whether the transform is allowed, and makes it simple to
add support for folding integer conversions.
Closes: #3208
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10859>
Many fragment shaders do a discard using relatively little information
but still put the discard fairly far down in the shader for no good
reason. If the discard is moved higher up, we can possibly avoid doing
some or almost all of the work in the shader. When this lets us skip
texturing operations, it's an especially high win.
One of the biggest offenders here is DXVK. The D3D APIs have different
rules for discards than OpenGL and Vulkan. One effective way (which is
what DXVK uses) to implement DX behavior on top of GL or Vulkan is to
wait until the very end of the shader to discard. This ends up in the
pessimal case where we always do all of the work before discarding.
This pass helps some DXVK shaders significantly.
v2 (Jason Ekstrand):
- Fix a couple of typos (Grazvydas, Ian)
- Use the new nir_instr_move helper
- Find all movable discards before moving anything so we don't
accidentally re-order anything and break dependencies
v3 (Pierre-Eric): remove the call to nir_opt_conditional_discard based
on Daniel Schürmann comment.
v4 (Pierre-Eric):
- handle demote intrinsics and drop derivatives_safe_after_discard
- add early return if discards/demotes aren't used
v5 (Pierre-Eric):
- use pass_flags instead of instr set (Daniel Schürmann)
v6 (Daniel Schürmann):
- cleanup and fix pass_flags handling
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
With the addition of createImageWithModifiers usage flags were
dropped, as it was believed at the time that modifers will be a
full replacement for the usage flags. This has turned out to be
untrue, as modifiers are not able to describe buffer placement.
Add a new version of the interface, that allows to specifiy
use flags in addition to the modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
The DRI image extension already has two different ways to allocate an
image (with and without a modifier) and will soon grow a third one.
Add a helper, which handles calling the appropriate implementation to
get rid of code duplication in the winsys.
This convert the two obvious call sites (GBM dri and EGL wayland)
that profit from the code dedup.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
This is the vec4 equivalent of d0d039a4d3, required for proper UBO
pushing in vertex stages for Vulkan on HSW. Sadly, the implementation
requires us to do everything in ALIGN1 mode and the vec4 instruction
scheduler doesn't understand HW_GRF <-> UNIFORM interference so it's
easier to do the whole thing in the generator. We add an instruction
to the top of the program which just means "emit the blob" and all the
magic happens in codegen.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
In order to avoid switching pull constants to push constants and then
having to back to pull, compute the push ranges up-front. This way we
know by the time we emit code exactly what ranges are pushable. This is
a bit inefficient in the case where the "normal" push constants get
compacted. However, most apps don't use giant piles of dead uniforms
combined with substantial UBO use so this should be ok.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
The way we handle spilling for fp64 in vec4 is to emit a series of MOVs
which swizzles the data around and then a pair of 32-bit spills. This
works great except that the next time we go to pick a spill reg, the
compiler isn't smart enough to figure out that the register has already
been spilled. Normally we do this by looking at the sources of spill
instructions (or destinations of fills) but, because it's separated from
the actual value by a MOV, we can't see it. This commit adds a new
opcode VEC4_OPCODE_MOV_FOR_SCRATCH which is identical to MOV in
semantics except that it lets RA know not to spill again.
Fixes: 82c69426a5 "i965/vec4: support basic spilling of 64-bit registers"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
The vec4 back-end can't push UBOs just yet but it soon will be able.
When it starts pushing UBOs, it will have a lower limit than scalar due
to a crummy register allocator. Mirror that limit in ANV so we don't
run into asserts due to ANV and the back-end making different choices.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
This change adds a gallium D3D10 state tracker that works as a WDDM UMD
software driver, similar to Microsoft WARP, but using llvmpipe/softpipe.
The final deliverable is a d3d10sw.dll, which is similar to WARP's
d3d10warp.dll.
This has been used to run Microsoft Windows HCK wgf11* tests with
llvmpipe, and they were at one point passing 100%.
Known limitations:
- TGSI (no NIR)
- D3D10 only (no D3D11 support yet)
- no WINE integration (WINE doesn't implement WDDM DDI.)
For further details see:
- src/gallium/frontends/d3d10umd/README.md
- src/gallium/targets/d3d10sw/README.md
v2: Drop the DXBC-based disassembly. Add missing break statements.
v3: Incorporate Jesse's feedback.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10687>
Another lavapipe leak found with LeakSanitizer.
This happens when using tessellation without geometry shader but with a
fragment shader that consumes primitive ID, therefore requiring
primitive assembler stage.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10835>
These were already grouped nicely, just never got used. I also added
coverage writes to the list of reasons not to use early-z for
completeness. At the moment this doesn't do anything since this is a
Midgard flag and we haven't hooked up coverage writes on Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
Make sure only existing images are accessed and that the accessed
coordinates are within the image.
The generated code is quite exponsive, because it encapsulates each
access to an image with two if statements, one to check whether the
image index actually exists (this will get optimized away if the
image selection is direct), and one if statement to check whether
the coordinates are in range. For that reason it will only be enabled
for Cayman were invalid access seems to raise more issues.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10608>
I would like to reuse pan_pool for persistent uploads (shaders and CSOs)
in Gallium. In theory u_upload_mgr is more appropriate, but pan_pool is
already a knockoff u_upload_mgr, so might as well finish the job.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10866>
LOCAL_STORAGE.zw is workgroup local memory, whereas LOCAL_STORAGE.xy is
thread local memory. Likewise PC_SP.zw is the stack pointer, which is
initialized to (LOCAL_STORAGE.zw + offset) but is modifiable by the
shader. Panfrost doesn't modify the s tack pointer, and the register
allocation logic assumes a zero offset, so let's always spill to thread
local memory = LOCAL_STORAGE.xy, as was intended by Italo's cleanup.
This is visible on any shader that spills. Compute shaders aren't
advertised yet, so WLS will be null, causing a fault like the following
(reproduced on Mali T860 with the glyphy trace):
[15634.148873] panfrost ff9a0000.gpu: Unhandled Page fault in AS0 at VA 0x0000000000000000
Reason: TODO
raw fault status: 0x70003C2
decoded fault status: SLAVE FAULT
exception type 0xC2: TRANSLATION_FAULT_LEVEL2
access type 0x3: WRITE
source id 0x700
[15634.658170] panfrost ff9a0000.gpu: gpu sched timeout, js=0, config=0x3300, status=0x8, head=0x31d4540,
tail=0x31d4540, sched_job=00000000e8101b2e
Fixes: 6a12ea02fe ("pan/mdg: properly encode/decode ldst instructions")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10866>
A bunch of performance counters rely on register snapshots on top of
the OA reports. Those are already conditional to the query mode in the
equations :
availability="true $QueryMode &&"
This change allows to disable counters that are only available with
additional register snapshots. This will be useful if you only want to
OA reports to extract performance counter values.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10216>
By skipping slower tests such as `.*3_level_array.*`, we can add more
tests to CI without dramatically increase job duration.
Besides that, this patch also increases coverage by adding different
kinds of tests that were previously untested, failing or slowed CI too
much.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10855>
When exec is constant, we can remember the constant as the old exec,
and just copy the condition and use it as the new exec. There is no
need to save the constant.
Due to using p_parallelcopy which is lowered to s_mov_b64 (or 32),
many exec restores now become copies, hence the increase in the copy
stats.
Fossil DB changes on Sienna Cichlid:
Totals from 73969 (49.37% of 149839) affected shaders:
SpillSGPRs: 1768 -> 1610 (-8.94%)
CodeSize: 99053892 -> 99047884 (-0.01%); split: -0.02%, +0.01%
Instrs: 19372852 -> 19370398 (-0.01%); split: -0.02%, +0.01%
VClause: 515154 -> 515142 (-0.00%); split: -0.00%, +0.00%
SClause: 719236 -> 718395 (-0.12%); split: -0.14%, +0.02%
Copies: 1109770 -> 1254634 (+13.05%); split: -0.07%, +13.12%
Branches: 374338 -> 374348 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1776481 -> 1653761 (-6.91%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
Previously, we would store even the constant -1 exec mask from the
beginning of every merged shader. With this change it is no longer
necessary because we can restore to constant exec mask directly.
Hence, this frees up a register pair (single register for Wave32)
in every merged shader.
No Fossil DB changes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10691>
In Vulkan we configure our integer RTs to clamp automatically, so with logic
operations we need to be careful and avoid overflows by discarding any bits
that won't fit in the RT component size.
Fixes remaining CTS test failures in:
dEQP-VK.pipeline.logic_op.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10801>
This avoids debug builds to assert crash. Components that don't exist
won't be used and will be eventually DCEd, so simply lower them to 0.
Fixes CTS tests like these in debug builds:
dEQP-VK.pipeline.logic_op.r8_uint.clear
dEQP-VK.pipeline.logic_op.r8_uint.and
dEQP-VK.pipeline.logic_op.r8_uint.and_reverse
dEQP-VK.pipeline.logic_op.r8_uint.copy
dEQP-VK.pipeline.logic_op.r8_uint.and_inverted
dEQP-VK.pipeline.logic_op.r8_uint.no_op
dEQP-VK.pipeline.logic_op.r8_uint.xor
dEQP-VK.pipeline.logic_op.r8_uint.or
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10801>
There is a regression that made it impossible to export gem
handles with write access.
That is, a client may export gem handles of each buffer plane, then
export dmabuf fds using these handles, and mmap these dmabuf in
a different process (this is what Chromium does).
After https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4861,
it became impossible as mmap resulted in EACCESS error as slightly
different approach was taken for exporting these gem handles.
This CL fixes exporting gem handles (which are exported from dmabuf
fds) by adding the DRM_RDWR flag.
Cc: mesa-stable
Fixes#3119
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10850>
There is a regression that made it impossible to export gem
handles with write access.
That is, a client may export gem handles of each buffer plane, then
export dmabuf fds using these handles, and mmap these dmabuf in
a different process (this is what Chromium does).
After https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4861,
it became impossible as mmap resulted in EACCESS error as slightly
different approach was taken for exporting these gem handles.
This CL fixes exporting gem handles (which are exported from dmabuf
fds) by adding the DRM_RDWR flag.
Cc: mesa-stable
Fixes#3119
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10851>
It's perfectly legal to declare multiple SSBOs that point to the same
binding/descriptor_set with different access mask. Currently, it will
always get the first one in the list that matches binding/desc_set
regardless of the access mask, but other variables might have different
access mask.
Fix this by being conservative if another variable uses the same
binding/desc_set because we can't get it reliably without adding
a new field to vulkan_resource_index.
This fixes rendering issues in Resident Evil Village with vkd3d-proton.
This bug has been uncovered by ("spirv: Don't remove variables used by
resource indexing intrinsics") because variables are no longer removed
No fossils-db changes.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10692>
Would allow earlier faults instead of having corrupted cmdstream.
This was already done to Freedreno long ago in:
04aff7e4 "freedreno: make cmdstream bo's read-only to GPU"
Since private memory should be GPU writable it is now allocated
separately, instead of suballocation from now read-only cmdstream.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10807>
Flush batches when a new batch accessing the same set of BOs comes in
instead of delaying that operation. This greatly simplifies the
dependency tracking logic and shouldn't hurt the perfs (it might even
improve the latency since jobs are now flushed earlier).
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10842>
The PAN_BATCH_DEBUG section was too wide, potentially leading to
double insertion of the same batch in the readers array. Let's get rid
of this already_accessed parameter and make sure
panfrost_batch_update_bo_access() is only called if the RW flags have
changed.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10842>
We don't want blit batches to interfere with subsequent draw calls, but
we want to keep them in the list of pending batches (so they gets flushed
when glFlush() is called), so calling panfrost_freeze_batch() is not an
option. Reset the ctx->batch pointer manually.
Note that there's no risk to have those batches re-used to queue
unrelated draws because we created a unique pipe_surface object per
blit call, and the batch logic use the surface pointers to calculate
the batch key hash.
Fixes: e1649e916d ("panfrost: Use pan_blit() when PAN_MESA_DEBUG=panblit")
Reported-by: Icecream95 <ixn@disroot.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10842>
BOs in the cache are chronological, so we try oldest BOs first. That
means if we find the oldest BO is busy, likely every BO is busy, and we
should bail early. This dramatically reduces the useless cycles spent in
bo_wait.
I studied the BO cache of the following drivers, all of which handle
this correctly: iris, lima, etnaviv, freedreno, vc4, v3d, v3dv.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10794>
The atomic can be costly, so skip it. This should be safe because
we never have pipe_transfer as the only live reference of a buffer.
Drivers can't do this yet because something needs to hold the resource
reference while a transfer object is being passed via u_threaded_context.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10662>
We don't want to have to deal with vector phis in freedreno, because
vectors are always split/unsplit around vectorized instructions anyways,
and the stated reason for not scalarising them (it hurting coalescing)
won't apply to us because we won't be using nir_from_ssa. Add this
option so that we don't have to do the equivalent thing while
translating from NIR.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10809>
The load-store vectorizer can create a large amount
of unnecessary nir_op_vec and nir_op_mov instructions.
This prevents nir_opt_move from stalling to much and
potentially also helps other passes.
Closes: #4778
Fixes: 1958381c9a ('radv: Reorder some NIR optimizations in preparation for the I/O changes.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10804>
Not every MR, but several per day since I landed the apitrace switch which
increased trace replay resolution to 1080p. Hopefully some day we can
tune the hangcheck to be less aggressive.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10793>
when emitting barriers, we don't need to end the renderpass in some cases
this handles the case of emitting barriers for new resources which have
never before been accessed and thus do not require synchronization at a
specific point in the batch
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10700>
this is a small optimization for the no-wait case when unflushed usage
exists since it's impossible for a qbo update to happen instantly
no functionality will be fixed by this, it's just a very minor optimization
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10796>
a fence applies to all the submitted cmdbufs, so it's necessary to do
the flush which creates the user fence after all the cmdbufs have been
processed in order to avoid creating a fence that only applies to the
first cmdbuf
Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10795>
The initial value needs to be taken from the instruction that is being
moved over, not the one to be moved.
Additionally the parameter of this function was removed because it was
misleading. Setting it to any value other than source_idx would cause
register_demand to be initialized incorrectly. (Instead, the maximum
demand among the covered instructions would need to be determined.)
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
MinGW DEF parsing is even more broken than before, and 32-bits import
libs are broken regardless one uses opengl32.mingw.def or opengl32.def.
This change removes opengl32.mingw.def and addresses the issue differently:
- link opengl32.dll with --enable-stdcall-fixup
- use the systems opengl32 import lib (libopengl32.a/opengl32.lib)
instead of our own
This change also gets test_wgl built with MinGW (even if it's never tested),
which I used to verify this; and to not link against internal libraries.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
v2: Revert back to shared_library.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10767>
From the ARB_enhanced_layouts spec:
"As with input layout qualifiers, all shaders except compute shaders
allow *location* layout qualifiers on output variable declarations,
output block declarations, and output block member declarations. Of
these, variables and block members (but not blocks) additionally
allow the *component* layout qualifier."
We previously had compile tests in piglit to make sure this was not a
compile error but no execution tests.
Fixes: d99a040bbf ("i965: enable ARB_enhanced_layouts for gen8+")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10763>
With the idea of branching classic device support in to its own tree now would be a good time to also raise the minimum
requirements to something that is more "modern" on x86.
SSE2 was introduced in 2000(!) by default let's make it the minimum spec now
All the old hardware that is moving to the maintenance branch will finally be out of the way.
For the 64-bit side of the discussion there isn't much changed.
* GCC already enables -msse and -msse2 by default
* Same with clang
* fpmath=sse might remove some extraneous x87 usage
** Clang implies fpmath=sse ALWAYS
For the 32-bit side of things is where the exciting details change
* GCC by default doesn't enable sse1 or sse2
** Does all `float`, `double`, and `long double` math with x87
** -msse2 enables sse2 and sse1, gcc still uses x87 even with those enabled
** -mfpmath=sse moves away from using x87 and instead uses sse1 and sse2
* Clang already default enables sse1/sse2 which then turns on their implied fpmath=sse
What does this mean for users?
On Linux raises the default minimum processor spec to SSE2 supporting CPUs
* Intel requirements raise from P5 (1993) to Netburst (2000)
* AMD requirements raise from Athlon(1999/2000) to Athlon 64 (2003)
* Via requirements raise from C3(2001) to C7 (2005)
What does it mean for package maintainers?
For x86-64 distributions that have i386/i686 multilib, then nothing changes. You're already on a platform guaranteed to support SSE2.
For i386/i686 distributions they will need to weigh their min spec against this. Not sure how many still support classic processors.
Who is left out in the cold?
* Intel Quark (2013)
** Embedded board, doesn't have a GPU, Technically has 1x PCIe 2.0 lane that someone could plug a GPU in to
* Some older transmeta CPUs, but they had a followup that also had SSE2.
** Anyone hacking on these with a modern GPU? I'm guessing they know how to turn this option off
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9868>
Rockchip SoCs RK3566 and RK3568 have a Gondul with
one shader core and two execution engines, with product ID 0x7402.
Quoting the datasheet:
Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency
To distinguish it from other variants of G52, we agreed
to call this "G52L", L is for Little.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10771>
If we only read 8 bytes from a UBO, we need to use LD_UNIFORM.64 as
opposed to LD_UNIFORM.128. In addition to probably being faster, this
fixes a buffer overrun manifesting as MMU faults with source ID
0x500/0x600/0x700, visible in WebGL Aquarium.
This is essentially the same patch as 616394cf31 ("pan/mdg: Use
appropriate sizes for global loads/stores"), only this is for UBOs where
that was for SSBOs.
Before enabling PACKED_UNIFORMS, this bug was not visible since we could
guarantee the UBO size was a multiple of 16. We no longer have that
invariant, and in rare cases the last 8 bytes of the last 16-byte slot
of a mapped uniform buffer would overrun the BO and trigger a fault,
even if the result is unused.
Fixes: 24d7c413fe ("panfrost: Enable packed uniforms.")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10772>
The GLSL precision lowering is still buggy (see !10729), no other driver
enables all the CAPs yet. I don't know enough GLSL IR to be the one to
fix this. In the mean time, this is a hotfix to expose the same set of
CAPs that radeonsi does.
By keeping it with is_deqp, we still get CI coverage of int16.
Closes: #4759
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10777>
These intrinsics represent what the hardware can actually do.
Lowering our shaders to use these intrinsics will allow us to
deal with mapping the classic VS, TES, GS (and the future MS)
stages to the hardware capabilities using NIR, which makes our
backend compilers simpler.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
The strategy is lifted from Freedreno. The trick is to remove buffers
from the resolve set, rather than add buffers to a discard set (as you
would naively try). The latter is wrong -- draws after the
glInvalidateFramebuffer() still need to be respected.
glmark2 -btexture on-screen with sway on Mali T860 from 1393fps to
1998fps
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #2407
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6295>
It's not just position that's special here, we also need space for
other special vertex-shader outputs.
This fixes a crash with Zink on Lavapipe, because Zink always emits
psize to avoid some shader-keys. While this might not be ideal, it's not
illegal. So we need to handle it.
But it seems we're missing more, and this list is taken from
compute_vertex_info() in lp_state_derived.c.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10730>
Fix defects reported by Coverity Scan.
uninit_member: Non-static class member degree is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member degreeLimit is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member maxReg is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member f is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member reg is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member weight is not initialized in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10714>
* for samplers this is a per-stage slot mask that will be used for fast layout updates
* images get a count for gfx and compute usage
* any writable descriptor bind gets its own gfx/compute counter
* all descriptor binds are now counted
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
winsys_stride is the stride of the host storage of the classic resource,
and using that breaks the readback on the guest storage.
v2: move the scrubbing to virgl_resource_from_handle
The returned modifier also points directly to the host driver's real
modifier but not a virtualized one. Leave plane_offset as zero here
matches the prior behavior before introducing winsys info.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> (v1)
Reviewed-by: Chia-I Wu <olvaffe@gmail.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10757>
Caught this with an LTO build:
[1465/1465] Linking target src/gallium/targets/dri/libgallium_dri.so
In function ‘spirv_shader_delete’,
inlined from ‘nir_to_spirv’ at ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3907:7:
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3916:4: warning: ‘free’ called on pointer ‘block_1394’ with nonzero offset 48 [-Wfree-nonheap-object]
3916 | FREE(s);
| ^
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c: In function ‘nir_to_spirv’:
../src/util/ralloc.c:133:18: note: returned from ‘malloc’
133 | void *block = malloc(align64(size + sizeof(ralloc_header),
| ^
Since s->words is allocated on the same ralloc context we can simplify
further by freeing the context all at once.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10754>
this screen object can never, ever be accessed like this in a resource,
as it may have previously been replaced by a wrapper (e.g., driver trace)
which will then explode when it is accessed directly
instead, keep a separate screen ref on the resource which is known to be
the actual driver object and not a wrapper
Fixes: 0a497eb130 ("iris: make resources take a ref on the screen object")
Reviewed-by: Lionel Landwerlin lionel.g.landwerlin@intel.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10632>
We had re-enabled this because of some test regressions:
KHR-GLES31.core.geometry_shader.limits.max_input_components and
ext_transform_feedback-max-varyings failed to register allocate,
but now that we support indirect indexing on vertex shader outputs natively
this is no longer an issue.
Piglit's max-samplers tests failed. These tests use indirect indexing
on samplers which is not supported and fail to link with this error message:
"Failed to link: error: sampler arrays indexed with non-constant expressions
is forbidden in GLSL 110". This is expected. The reason these were passing
before is that loop unrolling was able to turn indirect indexing into
direct indexing. We add them to the expected fail list.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10723>
We have been able to to handle indirect offsets on GS outputs for
a while and we have just implemented this for VS, so we can enable
this capability and avoid the horrible if-ladder code to convert
indirect output indices to constant indices.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10723>
When spilling a register, the number of temps can be increased when
introducing a temporal variable.
Those nodes are not elegible to be spilled, but we need to take care of
no accessing out-of-bounds of the arrays defined with a size equal to
the original number of temps.
Fixes address sanitizer error on
KHR-GLES3.shaders.uniform_block.random.all_shared_buffer.14 (and many
others).
v2 (Iago):
- Add clarification in assertion.
- Use `vir_get_temp` to increase num_temps.
v3 (Iago):
- Update clarification
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10643>
these tests take over 5 minutes just locally, and the codepaths are mostly
shared with llvmpipe in the draw module, so there's not much point in running
them given that other drivers are more likely to catch any issues here over
softpipe, which is only more likely to catch timeouts
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10708>
The spec requires at least 2, but says "No specific guarantees are made
about higher priority queues receiving more processing time or better
quality of service than lower priority queues." So, we can just leave the
priorities as a stub.
Fixes dEQP-VK.info.device_properties
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10470>
This fixes the following UBSAN warning:
../mesa/src/gallium/drivers/panfrost/pan_resource.c:889:16: runtime error: member access within null pointer of type 'struct panfrost_resource'
#0 0xffff79787a1c in panfrost_resource_get_stencil ../mesa/src/gallium/drivers/panfrost/pan_resource.c:889
#1 0xffff7997af44 in u_transfer_helper_resource_destroy ../mesa/src/gallium/auxiliary/util/u_transfer_helper.c:141
#2 0xffff77187f14 in pipe_resource_reference ../mesa/src/gallium/auxiliary/util/u_inlines.h:150
#3 0xffff77187f14 in st_bufferobj_free ../mesa/src/mesa/state_tracker/st_cb_bufferobjects.c:87
#4 0xffff774be848 in _mesa_reference_buffer_object_ ../mesa/src/mesa/main/bufferobj.c:504
#5 0xffff77c2cb3c in _vbo_DestroyContext ../mesa/src/mesa/vbo/vbo_context.c:208
#6 0xffff771bd854 in st_destroy_context ../mesa/src/mesa/state_tracker/st_context.c:1082
#7 0xffff76f4b3cc in dri_destroy_context ../mesa/src/gallium/state_trackers/dri/dri_context.c:245
#8 0xffff76f298a0 in driDestroyContext ../mesa/src/mesa/drivers/dri/common/dri_util.c:528
#9 0xffff863ac118 in dri2_destroy_context ../mesa/src/egl/drivers/dri2/egl_dri2.c:1463
#10 0xffff86372484 in eglDestroyContext ../mesa/src/egl/main/eglapi.c:826
#11 0xaaaabf5ebe24 in tcu::surfaceless::EglRenderContext::~EglRenderContext() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x63e24)
#12 0xaaaabf5ebeb8 in tcu::surfaceless::EglRenderContext::~EglRenderContext() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x63eb8)
#13 0xaaaabf5ece30 in deqp::gles2::TestPackage::deinit() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x64e30)
#14 0xaaaabfaabad0 in tcu::TestHierarchyIterator::next() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x523ad0)
#15 0xaaaabfa7b65c in tcu::TestSessionExecutor::iterate() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x4f365c)
#16 0xaaaabfa5a564 in tcu::App::iterate() (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x4d2564)
#17 0xaaaabf5ea20c in main (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x6220c)
#18 0xffff85d322a8 in __libc_start_main ../csu/libc-start.c:308
#19 0xaaaabf5ea8dc (/home/tomeu/deqp-build/modules/gles2/deqp-gles2+0x628dc)
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10695>
This isn't the perfect error-code, but we don't really have anything
better, it seems.
The ideal fix here would be to fix LLVMpipe to support larger textures,
but this is probably as far as I'm interested in chasing down this path
for now.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10689>
It's possible to get all width, height and depth as negative here, and
if we take the util_logbase2 of that, we get a nonsense value that might
be outside of the range the driver supports. So let's clamp to zero here
to avoid having to make the drivers overly pessimistic about what the
state-tracker demands.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10689>
In radv_get_modifier_flags, we had a special case for multi-planar
formats. However ac_is_modifier_supported should already take care of
rejecting unsupported modifiers for multi-planar buffers.
Some time ago, ac_is_modifier_supported rejected any non-linear modifier
for multi-planar formats. 35e25ea1d0 ("ac/surface: allow non-DCC modifiers
for YUV on GFX9+") changed that to allow non-DCC modifiers with
multi-planar formats on GFX9+. Since then, the radv check has been out
of sync.
A similar patch was applied to radeonsi in 979e138695 ("radeonsi: stop
special-casing YUV formats in si_query_dmabuf_modifiers").
This fixes tiling artifacts with NV12 buffers.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10623>
this is much easier to read and is going to greatly simplify the eventual
multidraw implementation which will be dropped in
also it allows moving conditionals outside of loops to very slightly improve
drawoverhead performance (with multidraw)
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10701>
The current policy is to always favor accumulators if possible, however,
this is not always optimal.
Particularly, accumulators play a crucial role in enabling QPU instruction
merges, since these are limited to both the ADD and the ALU instructions
addressing at most 2 physical registers. For 2-src instructions, this means
that to be able to merge we need them to address at least 2 accumulators.
While favoring accumulators does help the case for instruction merges in
general, it is risky to assign accumulators to variables that have
long life spans. Doing so will make the accumulator unavailable for
any other instructions during that life span, and since we only have a few
accumulators, we can quickly run out and losing our capacity to merge
instructions for large parts of the qpu program.
On the other hand, we also want to avoid the extreme case were we keep
allocating physical registers to the point we run out, even if we have
accumulators available, since accumulators have additional restrictions
and may not be suitable for everything.
This change continues the policy of favoring accumulators, but it only
does so if the life span of the temps is short, to ensure that we can
recycle accumulators often across instructions and avoid running out
for sections of the QPU code, unless we are already running out of
physical registers.
total instructions in shared programs: 13654647 -> 13336921 (-2.33%)
instructions in affected programs: 11015919 -> 10698193 (-2.88%)
helped: 39758
HURT: 17325
Instructions are helped.
total threads in shared programs: 412046 -> 412038 (<.01%)
threads in affected programs: 16 -> 8 (-50.00%)
helped: 0
HURT: 4
Threads are HURT.
total uniforms in shared programs: 3745726 -> 3746003 (<.01%)
uniforms in affected programs: 17296 -> 17573 (1.60%)
helped: 76
HURT: 99
Uniforms are HURT.
total max-temps in shared programs: 2364430 -> 2359942 (-0.19%)
max-temps in affected programs: 109117 -> 104629 (-4.11%)
helped: 2893
HURT: 772
Max-temps are helped.
total spills in shared programs: 5727 -> 5746 (0.33%)
spills in affected programs: 221 -> 240 (8.60%)
helped: 1
HURT: 2
total fills in shared programs: 13121 -> 13139 (0.14%)
fills in affected programs: 466 -> 484 (3.86%)
helped: 1
HURT: 2
total sfu-stalls in shared programs: 33432 -> 34491 (3.17%)
sfu-stalls in affected programs: 18219 -> 19278 (5.81%)
helped: 4459
HURT: 5087
Inconclusive result
total inst-and-stalls in shared programs: 13688079 -> 13371412 (-2.31%)
inst-and-stalls in affected programs: 11030017 -> 10713350 (-2.87%)
helped: 39630
HURT: 17429
Inst-and-stalls are helped.
total nops in shared programs: 335753 -> 333708 (-0.61%)
nops in affected programs: 112659 -> 110614 (-1.82%)
helped: 8726
HURT: 7383
Inconclusive result
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10686>
Fixes the following error on Ubuntu 18.04 with GCC 7.
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:1448:72:
sorry, unimplemented: non-trivial designated initializers not supported
info_out->prop.cp.gmem[gmemSlot++] = {.valid = 1, .slot = i};
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Fixes: f451854f3 ("nv50: add remapping of buffers/images into unified space")
Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10668>
Blending in SP_BLEND_CNTL is not a binary flag but the same
mask as in RB_BLEND_CNTL. It is a per-mrt enable bit for blending.
Example SP_BLEND_CNTL produced by blob on a630 and different MRT
blendings:
SP_BLEND_CNTL: { UNK8 | 0x6 }
SP_BLEND_CNTL: { ENABLED | UNK8 | 0xe }
(Decoded before this commit)
Fixes mis-rendering with D3D11 game "Spelunky 2".
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10682>
We can do stuff like this:
vec1 32 ssa_207 = fsum3 ssa_209.xxx
In this case, we'd end up not swizzling in get_alu_src, and reading
components out-of-bounds, which LLVM isn't very happy about, and thus
takes punitive actions, in the form of a segfault.
We don't want that, and we already know from the opcode what the
component counts should be here.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10690>
This pass was originally developed for Panfrost, where it passes the
relevant dEQP tests. Upstreaming so it can be extended and then shared
with:
* Asahi, for blending
* Zink, for logic ops
* Lavapipe, for advanced blending
Note that using this with MRT in a fragment shader (as non-panfrost
drivers will) has not yet been tested. Logic ops with integer
framebuffers are probably todo. It's been enough for Panfrost, will
suffice for ES2 on Asahi, and provides an upstream base for kusma's work
on advanced blending, so overall the merge is a net benefit.
v2: Remove bogus assert that the format layout is PLAIN. We need to
render R11G11B10, which Mesa reports as layout OTHER. The code is still
correct.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10601>
This GLES extension allows to combine the formats BGR and BGRA
as host-side formatsto be combined with the internal formats
RGB8/SRGB8 and RGBA8/SRGB8_ALPHA8 respectively.
This extension is of interest to support a subset of OpenGL in
virtualized environments where the host only supports GLES.
Initial mesa/glformat.c patch: rohan.garg@collabora.com
v2: - Correct names for ClearTexture calls
- Add BGR(A)_EXT tokens
- Add format check for BGR_EXT
(All Adam Jackson)
v3: Fix ordering in extension table (Marge)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10613>
In our simplistic model of assigning types to pointer, we treat
return values specially because their "type" can't be known
easily before their first use. Improve the "ret" handling by
removing one from their count when we reassign the type to
something else.
Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10648>
Previously we inherited some options from parse.py, but
that made no sense for some of the options that are not
needed for dump_state.py (such as --plain, as we output
only JSON format text.)
So, remove the inherit and implement filename argument
here independantly.
Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10648>
Clean up tracediff.sh shellscript slightly, partially in preparation
for upcoming changes. Also add a signal handler for removing the
created temporary directory and files if we are interrupted.
Also, use the new --plain option of dump.py to suppress output
of ANSI color/formatting codes, so we do not have to post-filter
them later.
Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10648>
Remove the PAN_MESA_DEBUG=fp16 flag that was hiding it.
Skip two buggy dEQP tests. See linked discussion. We'll need to make
sure this gets sorted out before submitting conformance, but I don't see
a test with a fix in the pipeline as valid reason to hold back valid
code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9239>
gcc 11 warns:
[846/1506] Compiling C object src/mesa/libmesa_common.a.p/main_shaderapi.c.o
In function ‘shader_source’,
inlined from ‘_mesa_ShaderSource_no_error’ at ../src/mesa/main/shaderapi.c:2137:4:
../src/mesa/main/shaderapi.c:2095:25: warning: ‘*offsets_10 + _130’ may be used uninitialized [-Wmaybe-uninitialized]
2095 | totalLength = offsets[count - 1] + 2;
I can't really see how it's getting to that conclusion, but allocating
`offsets` with calloc is both natural to do here and guarantees
initialization.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10671>
gcc 11 warns:
../src/util/format/u_format_fxt1.c:940:22: warning: ‘fxt1_variance.constprop’ accessing 128 bytes in a region of size 64 [-Wstringop-overflow=]
940 | int32_t maxVarR = fxt1_variance(NULL, &input[N_TEXELS / 2], n_comp);
But, suspiciously, if you inline fxt1_variance the warning goes away.
What's happening is that the 2nd arg is uint8_t[N_TEXELS][MAX_COMP], so
it looks like we're passing too small of an array in since gcc knows
that `input` is also [N_TEXELS][MAX_COMP]. Fair enough. Fix the
signature to reflect what's actually going on, and remove some unused
arguments while we're at it.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10671>
If CRC data is currently invalid and the current batch will make it
valid, write even clean tiles to make sure CRC data is updated.
Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10566>
when an object is initialized with this, it should not be visible to any
other threads or contexts, so there should be no need to use an atomic set here
at the time of this commit, there are only two callers in the tree which pass
values != 1:
* zink uses a calculated number for framebuffer refcount on init (this is fine)
* aux/pb passes 0 on init (this is fine)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10650>
We don't really need loops unrolled, so let's just disable this. This is
generally recommended for NIR drivers, but we can do even better; not
even unroll in NIR. And since we don't set
nir_shader_compiler_options::max_unroll_iterations, we're already there.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10487>
The GL driver was getting loop unrolling from the GLSL compiler frontend,
but NIR unrolling is more sophisticated, so prefer that.
The only caveat is that loop unrolling is implemented in the Mesa state
tracker, so our backend won't have a chance to undo the optimization if
it causes us to lower thread count or spill, so we choose to be a bit more
conservative with the configuration than what we were doing with GLSL.
Shader-db results follow. Increase in instruction counts is expected due
to additional unrolling. We lose threads in very few shaders, but we
make up for this with the additional unrolling and reduced spilling. We
also managed to get 3 more shaders to compile successfully.
total instructions in shared programs: 13416427 -> 13461431 (0.34%)
instructions in affected programs: 96936 -> 141940 (46.43%)
helped: 58
HURT: 216
Instructions are HURT.
total threads in shared programs: 410626 -> 410598 (<.01%)
threads in affected programs: 56 -> 28 (-50.00%)
helped: 0
HURT: 14
Threads are HURT.
total loops in shared programs: 2121 -> 1708 (-19.47%)
loops in affected programs: 468 -> 55 (-88.25%)
helped: 446
HURT: 47
Loops are helped.
total uniforms in shared programs: 3676567 -> 3691185 (0.40%)
uniforms in affected programs: 25304 -> 39922 (57.77%)
helped: 23
HURT: 199
Uniforms are HURT.
total spills in shared programs: 5902 -> 5727 (-2.97%)
spills in affected programs: 285 -> 110 (-61.40%)
helped: 19
HURT: 0
total fills in shared programs: 13308 -> 13121 (-1.41%)
fills in affected programs: 301 -> 114 (-62.13%)
helped: 19
HURT: 0
total sfu-stalls in shared programs: 31860 -> 32856 (3.13%)
sfu-stalls in affected programs: 1692 -> 2688 (58.87%)
helped: 25
HURT: 196
Sfu-stalls are HURT.
total inst-and-stalls in shared programs: 13448287 -> 13494287 (0.34%)
inst-and-stalls in affected programs: 98404 -> 144404 (46.75%)
helped: 57
HURT: 217
Inst-and-stalls are HURT.
total nops in shared programs: 329276 -> 329551 (0.08%)
nops in affected programs: 2189 -> 2464 (12.56%)
helped: 58
HURT: 181
Nops are HURT.
LOST: 0
GAINED: 3
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10647>
Once we have exhausted compile strategies at 4 threads and we start
enabling lower thread counts, there is no point in starting compiles
with 4 threads for them, we know these will fail, so let's start at
2 in these cases.
This also has another nice implication: if the driver compiles at 4
threads and fails to register allocate, we were allowing it to try
with 2 threads, but this would only retry the register allocation
process and would not really recompile the shader with 2 threads. This
is not optimal, because at 2 threads we have more TMU fifo space for
each thread and we can do more TMU pipelining, so we were missing that
opportunity.
This improves performance in Sponza by ~1.5% and also seems to help
UE4 slightly.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10647>
Until now, if we can't compile at 4 threads we would lower thread count
with optimizations disabled, however, lowering thread count doubles the
amount of registers available per thread, so that alone is already a big
relief for register pressure so it makes sense to enable optimizations
when we do that, and progressively disable them until we enable spilling
as a last resort.
This can slightly improve performance for some applications. Sponza,
for example, gets a ~1.5% boost. I see several UE4 shaders that also get
compiled to better code at 2 threads with this, but it is more difficult
to assess how much this improves performance in practice due to the large
variance in frame times that we observe with UE4 demos.
Also, if a compiler strategy disables an optimization that did not make
any progress in the previous compile attempt, we would end up re-compiling
the exact same shader code and failing again. This, patch keeps track of
which strategies won't make progress and skips them in that case to save
some CPU time during shader compiles.
Care should be taken to ensure that we try to compile with the default
NIR scheduler at minimum thread count at least once though, so a specific
strategy for this is added, to prevent the scenario where no optimizations
are used and we skip directly to the fallback scheduler if the default
strategy fails at 4 threads.
Similarly, we now also explicitly specify which strategies are allowed to do
TMU spills and make sure we take this into account when deciding to skip
strategies. This prevents the case where no optimizations are used in a
shader and we skip directly to the fallback scheduler after failing
compilation at 2 threads with the default NIR scheduler but without trying
to spill first.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10647>
We set the maximum at 16 iterations (the GL compiler chooses 32
iterations for the GLSL front-end loop unrolling pass) because we
have observed a bunch of shaders from Sascha Willems that spill
significantly with 32, leading to massive performance degradation,
while 16 avoids spilling and doesn't seem to cause visible
performance degradation compared to cases that unroll 32 without
spilling.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10647>
It isn't reached, and shouldn't be, and it's not like returning NULL
(instead of the &null case for TGSI_FILE_NULL) will do anything good.
Shaves another tiny bit of dead code off of release builds.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10605>
It was just for the disabled check_inf_or_nan debugging, and if you want
to do that then you should do it with an assert at the end of
exec_instruction using tgsi_opcode_infer_type().
Despite the fact that this operand was dead, it actually reduces generated
code in release builds.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10605>
We were forgetting to increment in the loop, but also it looks from blob
dumps on Pixel 2 like all the pointers it emitted were shifted up by 3
compared to our xml, and that's the same shift that a6xx uses for its
pointers. None of the tests seem to use more than one
border-color-requiring texture, so it's hard to tell.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9904>
To update your local repository to use the new default branch, these
commands may help:
$ git fetch origin
$ git checkout master
$ git branch -m main
$ git branch --set-upstream-to=origin/main
$ git remote set-head origin --auto
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reworks:
* Fix mesa/mesamaster typo to mesa/mesa main (anholt)
* Use $CI_DEFAULT_BRANCH (eric_engestrom)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
It seems building the doxygen docs has bit-rotted over time, and now
generates a set of empty modules, apart from some basic descriptions.
Since Mesa is mostly implementing externally documented APIs, I don't
think it makes a whole lot of sense trying to fix this, and I think the
presence of these files might confuse users who try them out.
So let's just get rid of this.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10611>
We don't support major 1.2 required extensions like timeline semaphores.
Fixes many complaints in the dEQP-VK.info.vulkan1p2.* group.
We were originally bumped to 1.2 in 75755e0eba ("turnip: Pretend to
support Vulkan 1.2") but hopefully that build issue has been fixed in the
entrypoint reworks since then.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10471>
Gallium wants the depth or stencil component replicated on all .XYZW.
That's easily done on pre-v7 since we can forge all the swizzles we
want, but Bifrost v7 only supports a few combinations, so we have to
combine the user swizzle with our own 'replicate' swizzle to make it
work. Note that v7 has a trick to make border color work when the GRBA
order is chosen: they apply the red border color to the green component.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10612>
In particular, this gives us B8G8R8A8_UNORM storage support which is
useful for writing WSI images from compute shaders. These formats can
only be accessed in a spec-compliant way by decorating the variable
NonReadable in the SPIR-V (writeonly in GLSL). If the client doesn't so
decorate the variable, it'll get the null surface state where reads
return 0 and writes are ignored.
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
When I last time fixed this, I missed that continuing here would make us
leak pointers in the translate state, which is what made this avoid a
crash in the first place.
That's not great, we need to set *some* pointer in this case. The
obvious option would be NULL, but that means that the translate-code
also needs to support NULL-pointers here.
Instead, let's point to a small, static buffer that contains enough
zero-data for the largest possible vertex attribute. This avoids having
to add more NULL-checks.
Fixes: a8e8204b18 ("gallium/u_vbuf: support NULL-resources")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7773>
No handling of Acquire/Release because at the moment scheduler
works as if any barrier is Acq+Rel.
Instead of removing scoped_barrier with scope/mode that for TCS
corresponds to a control_barrier or a memory_barrier_tcs_patch in
ir3_nir_lower_tess_ctrl - remove them in emit_intrinsic_barrier.
And do the same for memory_barrier_tcs_patch and control_barrier.
While in any case hw fence/barrier shouldn't be emitted for them,
they still affect ordering of stores, and in feature ir3 backend
may want to have that information.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
nir_intrinsic_memory_barrier has the same semantic as memoryBarrier()
in GLSL, which is:
GLSL 4.60, 4.10. "Memory Qualifiers":
"The built-in function memoryBarrier() can be used if needed to
guarantee the completion and relative ordering of memory accesses
performed by a single shader invocation."
GLSL 4.60, 8.17. "Shader Memory Control Functions":
"The built-in functions memoryBarrier() and groupMemoryBarrier() wait
for the completion of accesses to all of the above variable types."
Fixes tests:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp
Fixes: 819a613a ("freedreno/ir3: moar better scheduler")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
The build-finished event is also triggered when there's an error. I
somehow got the second argument wrong, and ended up ignoring the case.
This can lead to new exceptions being thrown due to missing files, that
ends up hiding the real problem.
Fixes: 64a4ba9e1c ("docs: add an extension to generate redirects")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10407>
A lot of space was wasted due to 16-byte alignment for slots. This new
layout tries to match glthread. Highlights:
- the slot size changed to 8 bytes (was 16), so less padding
- the header size changed to 4 bytes (was 8), so some calls can use
the remaining 4 bytes in the slot for parameters
- draw merging merges up to 307 draws (was 256) due to space savings
- parameters in structures are sorted based on implicit type alignment
(uint8_t first, pointers last) to make it easier to utilize the 4 bytes
after the header and to remove holes
- some structures use smaller types for parameters than pipe_context where
it's safe (e.g. clear uses float instead of double for depth)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
sparse buffers are not cpu-readable, so any mapping requires that they
use a staging buffer, either the stream uploader for writes or a manual
copy for readback
future work here should attempt to resolve two perf issues:
* sparse allocations should be allocated dynamically using a suballocator
or some other, more useful strategy
* readback shouldn't allocate a huge staging buffer
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>
On Wayland, if the wl_drm interface is not available, for example if the
compositor is using the proprietary NVIDIA driver along with their egl-wayland
library, the device_select layer will fail to initialize. However, the failure
path will unconditionally call wl_drm_destroy even though info.wl_drm would be
NULL in that case. This can cause a segfault in libwayland-client.so.
To fix this, check if info.wl_drm is NULL before calling wl_drm_destroy. This
way, initialization will fail gracefully even if that interface is not present.
Signed-off-by: Erik Kurzinger <ekurzinger@nvidia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10598>
Move it out of the "cs" sub-struct, since the bit can be used for
other shader stages in the future.
This also removes a subtle issue in spirv_to_nir:
info.cs.shared_memory_explicit_layout was used without checking for
the CS shader stage. It ended up being "harmless" since the effects
also depended on presence of shared variables.
Fixes: 5de6c5973a ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10529>
We were implictly including it in exposing VK 1.2, but we weren't making
use of the supplied struct. Actually enabling it gives us a chance to do
slightly better at Z/S UBWC, and means we won't lose the separate usage
test coverage when switching back to exposing VK 1.1.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10594>
On Bifrost, fragment shaders might output either FP16 or FP32. The blend
shader will access the output as-is within the register, so depending on
the precision of the blend shader's logic, it may need to insert a
f2f16 or f2f32 conversion. This requires expanding the blend shader key.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
We only want it to trigger if MRT is actually in use. This is a cheap
key (only require multiple variants for an obscure edge case) and avoids
the perf regression of using this pass which is needed for conformance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>
Creating Android swapchain image from gralloc buffer requires to use
VkImageDrmFormatModifierExplicitCreateInfoEXT. To fill the struct info,
we need to query extended resource info from gralloc.
With the queried modifier from gralloc, we can ask the driver for the
plane count of the given format and modifier pair.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10553>
When a TSY barrier is hit, the entire supergroup will be synchronized.
If the supergoup is large and uses all available QPU threads it would
mean that we would sychronize and stall all running threads until all
of them reach the barrier, which may be inefficient.
This patch makes it so that if the compute shader has any such barriers
we limit the supergroup size so each supergroup only takes half of the
QPU threads available at most, so that if one supergroup hits a
barrier we have at least one other supergroup we can run, reducing
idle QPU time.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
Each supergroup executes a number batches. Each batch has 16 elements
(one per QPU lane), except possibly the last batch which might be
incomplete. Until now, we packed a single workgroup in each supergroup,
which can lead to more incomplete batches and less efficient use
of the QPUs depending on the configuration of workgroups being dispatched.
This patch computes a number of workgroups per supergroup so that
we reduce or completely eliminate incomplete batches if possible.
It should be noted however, that TSY barriers act on supergroups,
so larger supergroups lead to larger syncpoints on barriers too.
A follow-up patch will try to find a good balance for compute shaders
that use such barriers.
This improves performance of the Sascha Willem's computecloth demo
by ~13%.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
The V3D hardware allows us to pack multiple workgroups together to avoid
wasting execution lanes in shader cores.
For example, if we dispatch 16 workgroups with a local size of 1 element, we
can pack all 16 workgroups in a single 16-wide dispatch where each lane
executes a different workgroup, instead of 16 1-wide dispatches.
When we do this, we don't have a uniform workgroup id any more.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>
NIR provides two helper macros to run transformation passes correctly,
NIR_PASS() and NIR_PASS_V(). So far we've seemingly been a bit haphazard
about when to use them.
Let's correct that, and consistently use the NIR helpers here. This
helps us in two ways:
1. We now run nir_validate_shader after each pass, ensuring we didn't
break the shader
2. We now respect the NIR_PRINT environment variable for all NIR passes,
making debugging much less surprising.
In addition, we had an OPT()-macro that doesn't seem to provide much
help other than to hiding some trivial details. But they make our code
different to other users of NIR, which doesn't seem ideal. So let's drop
that macro while we're at it.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10585>
We've had about 1/day of the texelfetch group in the IRC flake reports
since apr 23, and tex-miplevel-selection that I marked before is actually
all the subtests it looks like. Also, you can't include the ",Fail" if
you want to actually match a test name.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10597>
Since the second source is always a constant that is known to be a
number, this should have the same performance as
GALLIVM_NAN_BEHAVIOR_UNDEFINED.
A lofty goal is to eventually remove GALLIVM_NAN_BEHAVIOR_UNDEFINED.
There's still a lot of (mostly implicit) users, and I don't feel like
tackling that right now. :)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
Like softpipe in mesa!10419, llvmpipe suffers from improper handling
of NaN in nir_op_fmax and nir_op_fmin. nir_op_fsat is already handled
correctly. OpenCL strictly requires the "NaN cleansing" behavior, so
all of the functionality is in place. Just make the graphics APIs use
the OpenCL path.
The majority of the possible performance penalty incurred here should
be resolved in the next commit.
v2: Add updated checksum for bgfx/39-assao.rdc trace. Rendering goes
from mostly garbage to looking correct to me.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10532>
There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes. The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds. Fortunately, not many shaders
actually use textureSize() with LOD.
Shader-db results on Ice Lake:
total instructions in shared programs: 19948537 -> 19948564 (<.01%)
instructions in affected programs: 3859 -> 3886 (0.70%)
helped: 0
HURT: 7
One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>
The source_depth_to_render_target flag can get set on old gen4-5 HW in a
few cases which are independent of the app writing gl_FragDepth. It
should be safe to just use fetch_payload_reg in that case instead of
depending in interpolation setup. This fixes a bug with certain very
simple shaders where we might end up not including the depth when we
should have.
While we're here, rework the logic around setting src_depth and add a
comment so it's more clear what's going on.
Fixes: 6d4070f3dd "intel/compiler: add support for fragment coordinate..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10596>
Somehow this was missed, but when we emit a query start/stop we need
have something that will need to be flushed in the batch.
Detected due to TC assert, but this had the potential to cause problems
in the non-TC case as well.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10599>
Do not set mmap_size to info.size. We do not track the size of the BO
anymore.
This fixes
dEQP-VK.api.external.memory.dma_buf.suballocated.device_only.fd_properties
where the test allocates a 1KB VkDeviceMemory, export and call
vkGetMemoryFdPropertiesKHR. It can happen that bo->mmap_size is less
than the aligned info.size.
FWIW, the test fails because it violates a VU:
VUID-vkGetMemoryFdPropertiesKHR-fd-00673
fd must be an external memory handle created outside of the Vulkan API
Fixes: 88f481dd74 ("venus: make sure gem_handle and vn_renderer_bo are 1:1")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10592>
Instead of using a separate outputs array, make the "end" instruction
(or chmask) take the outputs as sources. This works better for the new
RA, because it better models the fact that outputs are consumed all at
the same time. With the old model, each output collect would be assumed
dead after it was processed and subsequent collects could use it when
inserting shuffle code, which wouldn't work, and the new RA also deletes
collect instructions after lowering them to moves so the information
would be gone after RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
We need a stable order in order to create phi instructions. In the
future we can make this more sophisticated in order to make manipulating
the CFG easier, but for now that only happens after RA, so we won't have
to worry about it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
Originally I wrote this to support multiple ir3 blocks per NIR block,
but this turned out to be more useful for creating a stable ordering to
the predecessors. We compute the predecessors ourselves, rather than
relying on NIR, so that the array of predecessors we create in the next
commit has a stable order we can rely on when creating phi nodes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
There's an optimization here to sink direct (i.e. not relative) reads of
an array past unrelated direct writes. However, since each write
actually reads, modifies, and then writes again to the array, this means
that we need to read the latest updated array. The old RA used the array
id instead of the SSA information, so it didn't care, but the new RA
uses ->instr instead and ignores the array id because arrays are now SSA
so it needs to be correct.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
This wasn't using the same calculation that add_reg_dep() was using to
get the index into state->regs, so it was using the wrong register. Fix
this by folding it into add_reg_dep().
This shouldn't fix anything, because it's just used for scheduler
priorities, but it should reduce nop's and syncs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
a0.x is written as a half-reg, but just interpreting it as "hr61.x" will
result in it overlapping with r30.z in merged mode, which is not what
the hardware does at all. This introduced a spurious dependency on
a write to r30.z which resulted in an assert tripping. Just pretend it's
a full reg instead.
This fixes
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
with the new RA.
Fixes: 0f78c32 ("freedreno/ir3: post-RA sched pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
gcc warning:
../src/gallium/drivers/nouveau/nvc0/nvc0_screen.c: In function ‘nvc0_screen_get_compute_param’:
../src/gallium/drivers/nouveau/nvc0/nvc0_screen.c:623:7: warning: this statement may fall through [-Wimplicit-fallthrough=]
623 | switch (obj_class) {
| ^~~~~~
../src/gallium/drivers/nouveau/nvc0/nvc0_screen.c:634:4: note: here
634 | case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
| ^~~~
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10544>
gcc warning:
../src/gallium/drivers/nouveau/nv50/nv50_query_hw_metric.c: In function ‘nv50_hw_metric_get_query_result’:
../src/gallium/drivers/nouveau/nv50/nv50_query_hw_metric.c:140:26: warning: ‘sm11_hw_metric_calc_result’ accessing 64 bytes in a region of size 32 [-Wstringop-overflow=]
140 | *(uint64_t *)result = sm11_hw_metric_calc_result(hq, res64);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/gallium/drivers/nouveau/nv50/nv50_query_hw_metric.c:140:26: note: referencing argument 2 of type ‘uint64_t *’ {aka ‘long unsigned int *’}
../src/gallium/drivers/nouveau/nv50/nv50_query_hw_metric.c:105:1: note: in a call to function ‘sm11_hw_metric_calc_result’
105 | sm11_hw_metric_calc_result(struct nv50_hw_query *hq, uint64_t res64[8])
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10544>
panfrost_batch_submit can recurse to hundreds of levels to submit
dependencies, so split the actual submit code from the dependency
recursion, saving over a kilobyte of stack space per recursion
level. Enforce this with ATTRIBUTE_NOINLINE.
Use ATTRIBUTE_NOINLINE on panfrost_batch_submit itself as well to
prevent GCC from inlining the function into itself, which would use a
few hundred bytes of stack.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10574>
These turned out to be software defined structures consumed by the macOS
kernel (specifically, by IOGPUCommandQueue). I'm a bit bothered by the
sheer amount of random hex flying about, though Hector made some
progress on deciphering the structure. Nevertheless there's some comfort
knowing it's not actual hardware magic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Available on Gen11+.
v2: Order shading rate in correct order (Samuel)
v3: Move CPS_STATE emission to genX_state.c
v4: Don't override various output structures (Jason)
v5: Rebase on top master (Lionel)
v6: Fix invalid VkPhysicalDeviceFragmentShadingRatePropertiesKHR
(min|max)FragmentShadingRateAttachmentTexelSize values (Ken)
Drop #endif comment
v7: Limit extension to Gfx11+ (Lionel)
Support conservative raster (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Those helpers exist primarily to sort out some of the weirdness around
Gen4-6 dataport access. On Gen5 and earlier, everything was called
"dataport" and, instead of the SFID we have today there was a "target
cache" parameter in the descriptor. There are also some bits that moved
around on various gens depending on read vs. write. Starting with Gen6,
most things which target one of the data cache SFIDs should use
brw_dp_desc() instead.
v2: Drop backward comment (Ken)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
This is a purely software counter alongside the other hardware counters
for ease of use and consistency. However we have to make room for it in
the allocated query space. Use this opportunity to make the nv50 queries
work like the nvc0 ones in terms of space allocation.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
This handles BUFQ, SUQ, as well as all the various texture types and
formats, driven by data supplied by the driver (and shader itself).
TODO:
- 2d linear surfaces
- format via key for writeonly
These will be included in a later change. ES3.1 doesn't require
writeonly, and it's very hard to generate a 2d linear surface.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Add spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo to a530
fails for the same reason as spec@arb_texture_cube_map_array@texsubimage cube_map_array
(it is sometimes triggering gpu hangs that cause other flakes).
And remove two a630 xfails that started showing up as UnexpectedPass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
pctx->flush_resource() has the same expectations that the resource can
be shared with an external client as pctx->flush(), but without the
convenience of a fence to know *when* the resource must be visible to
that external client. So we need to ensure the batch is flushed all the
way to the kernel so that implicit-sync can do it's job.
Fixes: e9a9ac6f77 ("freedreno/drm: Async submit support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
The max values are inclusive, so add 1 before aligning. This means
that a max of 32 will be aligned up to 64 then be decremented to 63.
Add a comment to the pan_fb_info struct to document maxx and maxy as
inclusive.
Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
We want to give developers the option to run their jobs on devices
that are still being stabilized in the CI infrastructure.
These jobs should be optional and not prevent merging from happening.
The is-forked-branch-or-pre-merge anchor was not being used anywhere,
so it was changed to is-forked-branch-or-pre-merge-not-for-marge to
create this new rule.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
The prototype uses a pointer and the actual function definition had an
array. For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.
Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
Not all varying fetches could be pulled into the start block.
If there are fetches we couldn't pull, like load_interpolated_input
with offset which depends on a non-reorderable ssbo load or on a
phi node, this pass is skipped since it would be hard to find a place
to set (ei) flag (beside at the very end).
We also don't have to manually set (ei) in such cases since a5xx and
a6xx do automatically release varying storage at the end.
Earlier gens need further testing, however they do not support
interpolateAt* functions at moment, so unless we would like to support
sample shading on them - they are fine.
Fixes crash in GTA V.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10483>
This patch should not be backported directly to 21.1, as master already
fixed one failure. I'll post a backport of this series with the
additional failure documented when this one gets merged.
v2:
- remove dEQP-VK.synchronization.* from the skip list (Hakzsam)
- drop dEQP-VK.memory.pipeline_barrier.* from the skip list (Hakzsam, me)
v3:
- re-introduce dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576
Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10539>
The mysterious support_16bit_int_alu-option doesn't really mean what it
says. Instead it means "we support 16 bit compares, if 16 bit ALU
operations occur". And since 16 bit operations only appear if we're
lowering mediump/lowp, we can always set this option.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
We're about to need this in order to support 16-bit floats, because the
lowering code for that emits function-temp derefs, and we don't handle
it.
A better long-term solution would be to just support function-temp
variables and indirect derefs. But that's more work, and kinda
orthogonal to what this patchset tries to accomplish, so let's save that
for another day.
Fixes the following piglit:
- spec@arb_gl_spirv@execution@ubo@array-inside-ubo-copy
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
the only case in which this is nonzero is if a multidraw gets split by the frontend,
i.e., mesa core, and in all other cases it can be ignored. the value can also be ignored
for all indirect draws, though it seems many (most?) gallium drivers are not aware of this
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
this moves index_bias into the multidraw struct, enabling draws where the value
changes to be merged; the draw_info struct member is renamed and moved to the end
of the struct for tc use
u_vbuf still has some checks to split draws if index_bias changes, maybe
this can be removed at some point?
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
This change moves the SRVs associated with read-only SSBOs to be emitted
before any other UAV. We do this because the validator expects resources
to be emitted in a specific order, as noted by `emit_module`.
Previously, we emitted SSBOs as SRVs (read-only) or UAVs (read-write)
after other UAVs.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10514>
We'd like to avoid __glXInitialize as much as possible since it involves
taking a global lock. This means converting internal APIs to operate as
much as possible in terms of something other than a Display *, since if
that's all you have then you're forced to call __glXInitialize to get to
the glx_display.
The contortions in DRI2 displease me, but DRI2 displeases me, so.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10418>
1. pre-allocate command pools at device creation if anb enabled
2. force VK_SHARING_MODE_CONCURRENT for wsi image if necessary
3. pre-allocate and record command buffers at android wsi image creation
4. transfer in the ownership at vkAcquireImageANDROID
5. transfer out the ownership at vkQueueSignalReleaseImageANDROID
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10335>
Whenver VK_IMAGE_LAYOUT_PRESENT_SRC_KHR is used, replace it with
VK_IMAGE_LAYOUT_GENERAL as required for proper layout and ownership
transfer for external memory backed swapchain images.
This will be Android only until common WSI is fixed.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10335>
For non 64bit devices the key stored in hash_table_u64 is wrapped in
hash_key_u64 structure, which is never free.
This commit fixes this issue by just removing the user-defined
`delete_function` parameter in hash_table_u64_{destroy,clear} (which
nobody is using) and using instead a delete function to free this
structure.
Fixes: 608257cf82 ("i965: Fix INTEL_DEBUG=bat")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10480>
Otherwise, if src_bit_size > 0 and dst_bit_size == 0, we end up doing a
bad shift in `1 << (dst_bit_size - 1)`, as `dst_bit_size - 1` is a
negative value (in this case would be MAX_UINT32).
Fixes CID#1468134 "Bad bit shift operation (BAD_SHIFT)":
"large_shift: In expression 1 << dst_bit_size - 1U, left shifting by
more than 31 bits has undefined behavior. The shift amount,
dst_bit_size - 1U, is 4294967295."
v2:
- Use an assertion instead (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10251>
When we originally added patch variable handling to spirv_to_nir, we
were splitting I/O block variables in spirv_to_nir, so we weren't
guaranteed to have a nir_variable early enough in processing.
Since b0c643d8f5 ("spirv: Use NIR per-member splitting"), we've been
using NIR per-member splitting where we have a nir_variable which has
a separate nir_variable_data per member. With this, we can drop
vtn_variable::patch and use the patch boolean on the nir_variable
instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10469>
Fix defects reported by Coverity Scan.
member_not_init_in_gen_ctor: The compiler-generated constructor for this class does not initialize buf.
member_not_init_in_gen_ctor: The compiler-generated constructor for this class does not initialize st.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10399>
The combination of removing bottlenecks in userspace (userspace fences,
etc) and slow GPU results in hitting full ringbuffer on a306. Haven't
figured out a reasonable way to work around that in userspace until a
kernel fix is in place, so disable this one for now.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Move the submit ioctl to it's own thread to unblock the driver thread
and let it move on to the next frame.
Note that I did experiment with doing the append_bo() parts
synchronously on the theory that we should be more likely to hit the
fast path if we did that part of submit merging before the bo was
potentially re-used in the next batch/submit. It helped some things
by a couple percent, but hurt more things.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
This is a bit ugly, but with userspace fences and deferred submits it is
better to poll until the timestamp buffer is ready. Otherwise we could
be triggering deferred submits to flush sooner than they normally would,
changing the behavior of what we are trying to measure.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
For submits flushed with (a) no required fence, and (b) no externally
visible effects (ie. imported/exported bo), we can defer flushing the
submit and merge it into a later submit.
This is a bit more work in userspace, but it cuts down the number of
submit ioctls. And a common case is that later submits overlap in the
bo's used (for example, blit upload to a buffer, which is then used in
the following draw pass), so it reduces the net amount of work needed
to be done in the kernel to handle the submit ioctl.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/19
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Move everything into a struct assocated with the pipe_fence_handle, so
that the drm layer can fill in the seqn/fd fences directly.
This will give us a comvenient place to insert a util_queue_fence in the
next commit.
While we're at it, extract the uint32_t fence (previously called
'timestamp' in place, a kgsl legacy) into a struct that encapsulates
both the kernel fence and the userspace fence.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Without deferred flushes, we would track the last_fence any time when
there had be no rendering/etc since the last flush, to avoid creating
empty batches simply for the purpose of getting a fence. We can do the
same thing with deferred flushes, where the fence is created from the
frontend thread before we know what will be flushed, by repopulating
the pre-created fence.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
We only need fences for batches flushed via pctx->flush(). This will
serve as a useful signal about submits that can be merged.
v2. disable this optimization pre-a6xx until I can debug issues that
submit merging exposes
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Add a per-fd_pipe fence "timeline" so we can detect cases where we don't
need to call into the kernel to determine if a fd_bo is still busy.
This reuses table_lock, rather than introducing a per-bo lock to protect
fence state updates because (a) the common / hotpath pattern is to
update fences on a lot of objects, but checking the fence state of a
single object is less common, and (b) because we already hold the table
lock in common spots where we need to check the bo's fence state (ie.
allocations from the bo-cache).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
There are a couple cases where we want to use _NOSYNC, but at the same
time we want to ensure that rendering related to a bo is actually
flushed.
This doesn't do anything yet, but when we start deferring/merging
submits we'll need a way to trigger anything deferred to flush.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Most of them were actually unused. The memory type (KMEM vs SMI) only
applied to very old a2xx era devices that had a small/fast stacked
memory (SMI) vs normal memory (KMEM). And the cache flags are ignored
(ie. everything is writecombine), but we can add new cache flags later
when they actually do something.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
Before we can fix big endian, we kind of have to agree on how pixel data
should be laid out in memory.
For this we have to use packed data for !is_array declared formats and per
element values for is_array ones.
Also we need proper PACKED_1xn definitions for BE.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7776>
There is no point in having a write to an attachment enabled when there
is no corresponding output in the shader. Per VK spec it is an UB,
however a few apps depend on attachment not being changed if FS doesn't
have corresponding output.
Fixes water in Genshin Impact.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10489>
The idea behind this assert is that if a buffer is in
bufmgr->handle_table it's because it has been shared from i965 to the
outside. This is when we add the drm FD associated to this BO to
bo->exports.
But we also import buffer from the outside into i965 and those buffers
don't have an associated drm FD added to bo->exports.
If you import the same buffer more than once, you'll run into this
assert.
v2: Also drop assert from brw_bo_gem_create_from_name() (Ian)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 57e4d0aa1c ("i965: fix export of GEM handles")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10386>
For GL, we've previously mostly ignored the binding property for sampler variables
during the shader compilation step. For CL, our image bindings were always 0-based as well.
Now, for Vulkan, we are going to be getting explicit bindings and need to emit DXIL that
respects those bindings. Since Vulkan can also have both split and combined images and samplers,
we now need to be smarter about recognizing when NIR is trying to use a "sampler" as *both* an
image and sampler (in deref mode, the same variable will be deref'd as both image and sampler).
That "being smarter" bit comes next, but first, let's prep GL for building correct root
signatures and binding the resources correctly.
Reviewed-By: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10298>
Currently, a resized window results in an VK_ERROR_OUT_OF_DATE_KHR. But,
this seems to go against the spec, which suggests returning
VK_SUBOPTIMAL_KHR if the surface extent no longer matches the window
extent. (It does not *require* the WSI actually scale the contents, only
encourages doing so "if possible")
More to the point, VK_SUBOPTIMAL_KHR is the correct status to return if
the client *can* continue presenting to this swapchain, even if the
result will look wrong / "suboptimal". It's the client's decision on
when exactly to recreate the swapchain in this case, and the client may
very well end up wanting to continue presenting for a frame or two, to
prevent flooding the driver with swapchain recreations (which can result
in the window appearing visually "frozen" while resizing).
This change makes live resizing *significantly* smoother in e.g. mpv.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3196>
If the swapchain already does not match the current geometry at the time
of creation, set the initial status to VK_SUBOPTIMAL_KHR as a way to
inform clients to please resize the swapchain.
This solves a race condition where users have no way of knowing if the
surface extent changed in between the user querying the current extent
and creating the swapchain, and might end up missing a resize event
because of it, since XCB_PRESENT_CONFIGURE_NOTIFY is not yet being
handled.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3196>
This is similar to the transcode_etc flag in that it changes the ASTC
fallback (when present) to use DXT5 instead of RGBA8888. This reduces
the memory footprint of the app at the expense of a bit of correctness.
Because it's not quite correct, it's hidden behind a driconf option.
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10476>
Fixes a double-free in dEQP-VK.wsi.display_control.register_device_event
where the fence that we destroyed got destroyed again. Leaving it unset
in the error path leaves the test's NULL in place.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10473>
I mixed up the EXT and ARB version of the extensions; we actually do
require shaderStorageImageWriteWithoutFormat as well here.
Thanks to Ilia Mirkin for pointing this out.
It also seems I got really confused about what was required when writing
the docs, so let's fix that as well.
Fixes: 341332b23a ("zink: correct image cap checks")
Fixes: ecac7f3da1 ("docs: add missing zink-requirement")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10463>
Sometimes, there's a surplus of semicolons, and there's enough to go
around for everyone. So maybe you'll save a few away for later. But in
the big pictures, it seems better to get rid of these so we don't
overrun the semicolon quota.
Or whatever, I'm just cleaning up here.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10466>
Until now, the WSI code would rely on VK_EXT_pci_bus_info to check if the
WSI device matched the DRM device used for display. If they matched, then
it would allow direct presentation of the swapchain images, otherwise
it would fallback to a blit path through a linear buffer.
Unfortunately, this only works for PCI devices, so embedded GPUs would
always fail the test and fallback to the prime blit path, incurring in a
performance penalty due to the extra blit.
With this change driver backends have the possibility to attach a
callback to the WSI device to take control over that decision and have
freedom to make that choice according to their own platform particularities.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5917>
Since generated nir headers are included, it makes sense to include nir path
Fixes the following building error:
FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/si_shader_nir.o
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader_nir.c:26:
external/mesa/src/amd/common/ac_nir.h:29:10: fatal error: 'nir.h' file not found
^~~~~~~
1 error generated.
Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org>
Fixes: 1c702a8239 ("ac: move ac_lower_indirect_derefs() outside of the LLVM dir")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10443>
ideally we would want to require transformFeedbackPreservesTriangleFanProvokingVertex,
but as there is no fallback path, any amount of provoking vertex support
is still better than none, so tests related to this will continue to fail
for that hardware (intel)
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10458>
Present operations do not necessarily complete after the requested
time; if the CRTC has been blanked, they will complete
immediately. This means we cannot use the MSC value to tell when a
present has finished.
Instead of using MSC, track whether each present is complete by serial
number, which is the low 32-bits of the SBC value. This value is
provided in the present_pixmap request and returned in the present
complete notify event.
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
This avoids the use of uninitialized memory:
Conditional jump or move depends on uninitialised value(s)
at 0x5EDBF87: r600_draw_vbo (r600_state_common.c:2232)
by 0x5DEFA00: u_vbuf_draw_vbo (u_vbuf.c:1329)
by 0x5D990EF: cso_multi_draw (cso_context.c:1445)
by 0x59B7EF4: _mesa_draw_arrays (draw.c:1346)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10442>
Do all the necessary lowering in one place, during finalization, and
stop uselessly calling nir_lower_indirect_derefs in turnip. Splitting
i/o to elements should no longer be necessary since we use the i/o
semantics instead of variables now.
This has the side effect that we no longer generate enormous if-ladders
for tess/GS shaders with turnip.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7274>
Don't setup inputs and outputs if we aren't using
load_input/store_output intrinsics. While it's mostly harmless, there
may be more outputs than expected which would lead to an oob write of
the outputs array when setting the register id to INVALID_REG.
Also be more paranoid with asserts to catch this.
Fixes: a6291b1 ("freedreno/ir3: rework setup_{input,output} to make struct varyings work")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7274>
This makes the vertex order of TRISTRIP and TRISTRIP_ADJ primitves
consistent between XFB output and GS input. Technically, the Vulkan
spec allows us to XFB out in whatever order we want but being consistent
with GS inputs is probably nicer to apps.
Fixes: 36ee2fd61c "anv: Implement the basic form of VK_EXT_transform_feedback"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10460>
PIPE_CAP_IMAGE_LOAD_FORMATTED doesn't depend on
shaderStorageImageExtendedFormats or
shaderStorageImageWriteWithoutFormat.
PIPE_SHADER_CAP_MAX_SHADER_IMAGES enables
GL_EXT_shader_image_load_store, which *does* require
shaderStorageImageExtendedFormats. Having
shaderStorageImageWriteWithoutFormat and
shaderStorageImageReadWithoutFormat isn't enough to support this.
It *might* be possible to lower extended formats to format-less
reads or writes, but we don't currently do that, so we should
just correct the test for now.
Fixes: 3f9a6d333b ("zink: export shader image caps using features")
Fixes: 5282210c0b ("zink: check correct caps for PIPE_CAP_IMAGE_LOAD_FORMATTED")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10456>
We do not require the extended formats feature to enable shader-images,
so we can end up accidentally enabling the cap even when we don't need
to, which can lead to validation issues.
This also prepares us for the SPV_EXT_shader_image_int64 extension, if
we ever want to support that.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10370>
This is used in the Mesa GLUT implementation, which has been separated
out into its own repo, and is largely abandoned in favour of FreeGLUT.
So let's not try to document MESA_PRIVATE_CMAP, as it's just going to
confuse users.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10281>
The support for color-indexed rendering was removed from mesa all the
way back in 2010, in commit 81fe9949ef ("mesa/xlib: Remove support for
color-index rendering").
So let's drop it from our documentation as well. This environment
variable does nothing.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10281>
For non-CL, intrinsic access isn't set, because the image type doesn't
have access qualifier. Instead, the access qualifier is set on the variable.
So, add a mode to this pass which can chase back to the variable in addition
to the intrinsic access. Also, update the variable type and the deref chain
types so everything is consistent, that the tex is accessing a sampler. Note
we can't do this for CL, because void-typed samplers don't exist.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10356>
Modern shader APIs, like DX10 and GLSL 1.30, want min() and max() to
"cleanse" NaN. If one source is NaN, the other value should be chosen.
If both sources are NaN, the result may be either.
There are many cases where TGSI is generate from NIR, and many
optimizations in NIR expect this behavior. Not meeting these
expectations can lead to unexpected results.
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes: ffe58739da ("Softpipe: import TGSI tree. Not hooked-up yet.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10419>
Modern shader APIs, like DX10 and GLSL 1.30, want saturate or
clamp(..., 0.0, 1.0) to "cleanse" NaN. If the source is NaN, the
result should be zero.
There are many cases where TGSI is generate from NIR, and many
optimizations in NIR expect this behavior. Not meeting these
expectations can lead to unexpected results.
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes: 56c30bf17b ("tgsi: Saturate modifier obeys ExecMask. Implement NVIDIA [-1;+1] saturate mode.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10419>
I've seen this one happen at least twice today. Log shows something like:
Wallclock time between MSCs 16982.888889us does not match
glXGetMscRateOML 16668.071966us
or
Wallclock time between MSCs 16500.333333us does not match
glXGetMscRateOML 16668.071966us
Incidentally, both runs I've looked into had one run too fast and one run
too slow.
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10414>
Instead of using num_textures, determine the texture count from the
last bit set in textures_used.
Fixes ADDR_RANGE_FAULTs when draw_textured_quad writes only stencil.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10422>
If no slices were valid (the resource is uninitialized), we were reading
a bogus PIPE_FORMAT_NONE format from the blit.dst.format. Fix this --
and guard against scope similar issues -- by hoisting the blit
assignments out of the loop so they're valid.
Fixes: 9d0ad7fd2e ("panfrost: Patch the gallium driver to use pan_image_layout_init()")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10415>
Add AMDGPU to LLVM_TARGETS_TO_BUILD.
Remove explicit CMAKE_CXX_COMPILER from libclc to dodge regression from
newer CMake. The potential range seems like (3.19.7, 3.20.1].
Add -Dc_std=c17 to support static_assert.
Add -Dcpp_std=vc++latest to support designated initializers.
Add -Dvulkan-drivers=amd for RADV.
Add -Dlibelf:warning_level=1 because of warnings as error.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6162>
resetting a query pool+qbo dumpsters the existing qbo results,
so these need to be copied to the new qbo if they exist, and then the query
id needs to be updated to match the expected result offset so everything
keeps working as expected
Fixes: 00fc85a011 ("zink: reset queries when suspending if >50% of total pool is used")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10268>
Otherwise the dual-source input load is moved further down in the
shader, so the registers can get clobbered before then.
Fixes text not being visible in Alacritty.
Fixes: 52863f2e60 ("pan/bi: Enable all nir_opt_move/sink optimizations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10089>
Chrome browser has been calling this attribute to give driver the surface
usage hint. The hints include:
VA_SURFACE_ATTRIB_USAGE_HINT_GENERIC
VA_SURFACE_ATTRIB_USAGE_HINT_DECODER
VA_SURFACE_ATTRIB_USAGE_HINT_ENCODER
VA_SURFACE_ATTRIB_USAGE_HINT_VPP_READ
VA_SURFACE_ATTRIB_USAGE_HINT_VPP_WRITE
VA_SURFACE_ATTRIB_USAGE_HINT_DISPLAY
VA_SURFACE_ATTRIB_USAGE_HINT_EXPORT
The surface allocation are generic for us, and we don't need to specify
it. To add the attribute here is because we don't want application which
is calling this attribute to end up returning error and getting no surface
allocated.
Fixes: ebab310987 ("frontends/va: improve surface attribs processing")
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10353>
The bug #4657 mixed up which commit was actually responsible for
the regression, so re-apply this patch.
The indirect draw call already encodes the index bias so that no
additional encoding in the hardware is needed in this case.
This fixes a regression with a number of tests from
dEQP-GLES31.functional.draw_indirect.random.*
Fixes: c6c532faa8
"gallium/u_vbuf: use updated pipe_draw_start_count while using draw_vbo"
Closes#4671
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10388>
This code would work for GLXWindows but not for bare Windows, which I
guess you could argue is a server bug but which we can fix on the client
side with a little effort. We change __glXGetDrawableAttribute to
additionally return false if we failed to find the requested attribute
(which is safe, all the other callers discard the return value). Then
when inferring the fbconfig, if the attribute wasn't found, we ask for
the window attributes to find the visual ID and use that to find the
fbconfig.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10381>
Normally, we never see NULL in a source. However, starting with
eab1c55590, we can with a SHADER_OPCODE_SEND if it only has the first
payload. We were inserting barriers which adds unnecessary scheduling
dependencies and takes a lot of compile time because inserting a single
barrier is an O(n) operation.
All the extra O(n) can have a surprisingly large effect. This cuts the
runtime of dEQP-VK.binding_model.buffer_device_address.set3.depth3.
basessbo.convertcheckuv2.store.single.std140.frag by a factor of 20x for
a debug build.
Shader-db results on ICL:
total instructions in shared programs: 19918983 -> 19921610 (0.01%)
instructions in affected programs: 884074 -> 886701 (0.30%)
helped: 1688
HURT: 817
helped stats (abs) min: 1 max: 163 x̄: 4.23 x̃: 1
helped stats (rel) min: 0.02% max: 12.50% x̄: 1.08% x̃: 0.61%
HURT stats (abs) min: 1 max: 2674 x̄: 11.95 x̃: 2
HURT stats (rel) min: 0.11% max: 70.22% x̄: 1.71% x̃: 1.03%
95% mean confidence interval for instructions value: -1.97 4.06
95% mean confidence interval for instructions %-change: -0.28% -0.06%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 976503324 -> 975884809 (-0.06%)
cycles in affected programs: 82581703 -> 81963188 (-0.75%)
helped: 4144
HURT: 5010
helped stats (abs) min: 1 max: 79294 x̄: 311.31 x̃: 8
helped stats (rel) min: <.01% max: 53.69% x̄: 2.00% x̃: 0.51%
HURT stats (abs) min: 1 max: 92266 x̄: 134.04 x̃: 8
HURT stats (rel) min: <.01% max: 218.09% x̄: 3.25% x̃: 0.53%
95% mean confidence interval for cycles value: -119.85 -15.29
95% mean confidence interval for cycles %-change: 0.68% 1.07%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total spills in shared programs: 10659 -> 12014 (12.71%)
spills in affected programs: 441 -> 1796 (307.26%)
helped: 7
HURT: 12
total fills in shared programs: 11551 -> 14429 (24.92%)
fills in affected programs: 993 -> 3871 (289.83%)
helped: 8
HURT: 11
total sends in shared programs: 1025832 -> 1025353 (-0.05%)
sends in affected programs: 2241 -> 1762 (-21.37%)
helped: 105
HURT: 1
helped stats (abs) min: 1 max: 87 x̄: 4.57 x̃: 2
helped stats (rel) min: 5.56% max: 54.72% x̄: 11.37% x̃: 10.00%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for sends value: -7.39 -1.65
95% mean confidence interval for sends %-change: -12.95% -7.70%
Sends are helped.
LOST: 93
GAINED: 109
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4648
Fixes: eab1c55590 "intel/fs: Support SENDS in SHADER_OPCODE_SEND"
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10412>
This new surface attribute can be supplied by the client to indicate
a list of modifiers that the driver can choose from for buffer
allocation. This is useful to make sure the buffers allocated via libva
are compatible with the intended usage (e.g. can be scanned out via KMS
or can be imported to EGL).
Introduce a new Gallium pipe_context.create_video_buffer_with_modifiers
hook that drivers can implement if they are modifiers-aware. Add a
modifiers argument to vlVaHandleSurfaceAllocate so that the
user-supplied list of modifiers can be passed down from vaCreateSurfaces
to the Gallium driver.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10237>
Currently, in GetPipelineCacheData() function, in several cases if
there is an error the blob is finished and cache unlocked, but code
continues executing, which can lead to multiple
`pthread_mutex_unlock()` calls.
Instead, if there's an error just bail out to finish the blob and unlock
the cache directly.
Fixes CID#1468147 "Double unlock (LOCK)".
v2:
- Rename "bail_out" by "done" (apinheiro)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10404>
Most of the regressions we found are with the piglit testsuite. The
difference between executing all tests versus quick_gl + quick_shader
are minimal, in the sense that we would need the same number of jobs to
execute and be in the 10 minutes budget.
Hence replace "quick_gl" + "quick_shader" by "all".
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10378>
Check if v3dv_ioctl() or v3dv_bo_map() fail, and print a proper error
message.
This check happens in the rest of the code, so it makes sense to apply
here too.
Fixes CID#1468162 "Unchecked return value (CHECKED_RETURN)".
v2:
- Fix message error (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10380>
Creating resource handles upfront works well while we have fixed-size resource
counts, but once we start talking about bindless, having arrays or even sets
of handles becomes prohibitive. It also precludes dynamic indexing for textures.
Instead, rely on the load_vulkan_descriptor instruction for UBO/SSBO, and undo
nir_lower_samplers so we continue to have deref chains for image/sampler accesses.
Then, emit handles at the end of a deref chain - the chain should only have
array offsets, so once we get to a type that's not an array anymore, we can
emit the handle.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10288>
VkImportMemoryFdInfoKHR takes fd ownership on a successful import.
Internally, vn_renderer_bo_create_dmabuf doesn't rely on the fd to
extend the life cycle of the bo or the host resource, and it won't
close the fd. Thus, we shall close the fd when the import succeeds.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10390>
This commits fixes a regression caused by commit
616394cf31.
Fixes dEQP-GLES31.functional.compute.shared_var.atomic.min.*,
dEQP-GLES31.functional.ssbo.atomic.min.*,
dEQP-GLES31.functional.compute.shared_var.atomic.max.* and
dEQP-GLES31.functional.ssbo.atomic.max.*.
Midgard's non-image and non-varying store operations have a unique
behavior for the load/store writemask, with each bit being responsible
for 1/4th of the size of the total write operation. This means that we
have to pack the writemask differently since we stopped using st_u128
for everything.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10067>
To vectorize to vec8/16 or vec4 (without vec3), we can't incrementally add
components to a load/store. This patch loops vectorization so that two new
vec2/4/8 operations can be combined into a larger operation.
fossil-db (GFX10.3):
Totals from 22 (0.02% of 139391) affected shaders:
SpillVGPRs: 1749 -> 1771 (+1.26%)
CodeSize: 901212 -> 892532 (-0.96%); split: -1.19%, +0.22%
Scratch: 178176 -> 184320 (+3.45%)
Instrs: 159358 -> 158027 (-0.84%); split: -0.99%, +0.16%
Cycles: 37046772 -> 36738544 (-0.83%); split: -1.00%, +0.17%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10384>
The major thing that the codegen had was support for expanding integers
from byte-per-channel to the target format's channel size. However, the
format_utils.c caller never did that for integers, and swrast doesn't have
support for integers, so that appears to be dead code. With this done,
format_pack.py goes away entirely.
I slightly changed the prototype of _mesa_pack_ubyte_rgba_row() to match
up with the new function, which involved (mostly) dropping some manual
casts from the callers to make their data match the old prototype.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10336>
channel datatypes in Mesa are the host's endianness. For example,
PIPE_FORMAT_R32_UINT doesn't do a bswap in and out in u_format_table.c's
pack/unpack functions. So, z32_unorm shouldn't be byte swapping either,
and neither should z24s8 which is also a packed format, and once you've
got those it becomes clear that all of the swaps in this file were
mistaken.
Things would mostly work out because it's unusual to read/write Z/S data
through the GL API, and even for drivers like softpipe as long as the pack
and unpack both swap it could work anyway. However, the bug would be
visible in glReadPixels() with the matching datatype which would hit the
memcpy fastpath without doing another swap.
Caught by a mesa/main unit test on transitioning to using these
pack/unpack functions.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10336>
generally speaking, if I'm tracing an app, I want to see what's happening to
my driver, not what's happening to tc, as tc does rewriting of command streams
which can affect the operation of the driver
use GALLIUM_TRACE_TC for previous behavior
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10362>
we should probably trigger this any time a flush occurs just to avoid
doing too much (unexpected) cmdstream rewriting
both calls must be kept, however, as the one in the base flush hook will change
the behavior of flushing if no other work is queued
Fixes: 104603fa76 ("zink: create separate linear tiling image for scanout")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10358>
this is called from the non-deferred flush path, which means it should always
be triggering work, which means it will always result in a queue submission
instead of relying on the pipe_context::flush hook to be triggered, which is
not a guarantee, do scanout sync during queue submission to ensure that scanout
objects are always in sync
Fixes: 104603fa76 ("zink: create separate linear tiling image for scanout")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10358>
On a6xx/a5xx there is such dependency between branchstack bitfield
and the amount of nested ifs, which could be seen with blob:
IFs BRANCHSTACK
0 0
1 1
2 2
3 2
4 3
5 3
6 4
...
59 30
60 31
61 31
62 32
63 32
64 32
Remove open-coded branchstack for a5xx compute along the way.
Fixes tests:
dEQP-VK.spirv_assembly.instruction.compute.float16.opvectorshuffle.344
dEQP-VK.spirv_assembly.instruction.graphics.float16.opvectorshuffle.344_vert
dEQP-VK.spirv_assembly.instruction.graphics.float16.opvectorshuffle.444_geom
dEQP-VK.spirv_assembly.instruction.graphics.float16.opvectorshuffle.244_tessc
dEQP-VK.spirv_assembly.instruction.graphics.float16.opvectorshuffle.344_frag
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9859>
We can't support more than compiler->branchstack_size diverging threads
in a wave. Thus, doubling the threadsize is only possible if we don't
exceed the branchstack size limit.
As of blob version 512.490.0 - it doesn't have this heuristics.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9859>
DCC decompress/FMASK expand are supported on compute queues. Since
the driver doesn't perform fast clears with concurrent images, we
don't need to perform a FCE on compute (we can't anyways).
This fixes a performance regression with Control and
VKD3D_CONFIG=multi_queue.
One more optimization (as discussed with Bas) is to implement FCE
on compute to allow fast clears.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10323>
This fixes the
dEQP-GLES3.functional.shaders.invariance.{low,medium,high}p.loop_4 tests when
run in a VM with virgl on a host with iris. virgl mangles the GLSL shaders and
emits shader code for the host driver that contains vec4 arrays. As such, the
test did not fail when running directly on the host.
The test also did not fail if the host was using i965. Disabling
PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY in iris was sufficient to work around it,
so I believe that i965 didn't show the problem because after arrays were split
by optimize_split_arrays(), even though the invariant/precise qualifiers were
lost, do_common_optimization() would be called again and thus
propagate_invariance() would propagate the qualifiers to the new variables
produced by optimize_split_arrays().
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10292>
The claim that we require vulkan memory model's MakeAvailable and
MakeVisible semantics for image writes isn't accurate. This would be
required *if* we were already using the Vulkan memory model.
But we're using the GLSL450 memory model in those cases, which has no
such requirements.
This means that any problems on RADV due to the lack of these semantics
are RADV bugs, and should be fixed in RADV instead.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10345>
v2:
* Fixed indentation in iris_resource_from_memobj
v3:
* Removed the call to iris_resource_configure_aux, as we don't
have any auxiliary buffer support.
v4:
* Added a comment about the assertion that there's no aux buffer
in case we add them later.
v5:
* Changed the logic of iris_resource_from_memobj. When the user doesn't
explicitly set the tiling to linear, we use a similar logic with the
anv driver's logic to calculate it instead of querying the kernel.
This is because the Vulkan driver doesn't perform ioctls to update the
kernel when it suballocates buffers.
v6:
* Removed the line that sets the modifier info in the resource. We
shouldn't need it.
v7, v8:
* Removed left over code related to modifiers.
v9:
* Replaced FORCE_LINEAR_TILING flag with PIPE_BIND_LINEAR where
necessary.
v10: rebase, use iris_resource_configure_main (Tapani)
v11:
* isl surfaces should be created only for textures and not for
buffers (fixes: pixel buffer tests assertion failure on BDW).
v12:
* fix in return type is required after rebasing to master.
Signed-off--by: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Eleni Maria Stea <estea@igalia.com>
Co-authored-by: Eleni Maria Stea <estea@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com> (v9)
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v12)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4337>
v2: use iris_bo_import_dmabuf (Tapani)
v3: included "util/u_memory.h" to fixed compilation errors caused by
using the CALLOC_STRUCT macro
v4: implemented iris_memobj_destroy (pscreen->memobj_destroy) callback
v5: removed iris_bo_from_handle and changed the approach for setting the
tiling: Instead of querying the kernel and call
iris_bo_import_dmabuf to create the bo, we call
iris_bo_import_dmabuf_no_mods that imports the bo but without
setting the tiling mode. We are going to update it when we create
the resource. Also: implemented the iris_bo_import_dmabuf_no_mods.
v6: rebase to iris_bo_import_dmabuf changes and take a reference
to memobj->bo (Tapani Pälli)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Eleni Maria Stea <estea@igalia.com>
Co-authored-by: Eleni Maria Stea <estea@igalia.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4337>
Turns out both kernel v5.10 and v5.11 have the same amdgpu driver
version and only one has modifiers ... In addition the version check
is kinda annoying for backports.
So lets use the cap. Since the cap is technically about ADDFB2 I
tested that this works on rendernodes (and reading the code there
is no distinction from what kind of node this is called).
Fixes: 9a937330ef ("radeonsi: Only set modifier creation function for GFX9+ & with kernel support.")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10337>
If depth bias is enabled but zero values used, they were never
emitted to the command buffer because they are equal to the default
values.
Previously, they were always emitted when the bound DS attachment
changed.
This should fix some sort of Z fighting with Dota2 on all GPUs.
This also fixes a different issue (ie. some occlusion queries failures)
on GFX6 because CLEAR_STATE is not used on that chip.
Fixes: 8a47422d97 ("radv: do not scale the depth bias for D16_UNORM depth surfaces")
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10310>
Without this, we're left with a bunch of medium-precision residue, like
i2imp. And to avoid that the lowering intrudces left-over instructions,
also run other lowering passes, similar to what other drivers do.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10185>
If the calling process happens to use an invalid bo (e.g. fd has been
closed), this led to lseek() returning -1 and this mmap trying to mmap
a buffer of size -1 (0xffffffffffffffff ...) which led to mmap
failing, which led to munmap failing which then led to the process
aborting.
This fixes that to gracefully handle the mmap failures and percolate
the failures back up through the API so eglCreateImage will not return
a valid image anymore, thus the error is detectable in the caller
process too.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10313>
gallium hud checks for the PIPE_FORMAT_B8G8R8A8_SRGB format to set
has_srgb, but can then receive a different format such as
PIPE_FORMAT_B8G8R8X8 in hud_run.
If the driver supports PIPE_FORMAT_B8G8R8A8_SRGB but does not support
the other formats such as PIPE_FORMAT_B8G8R8X8_SRGB, that will break
rendering as gallium hud assumes srgb is also supported for that format.
Extend the check to set has_srgb to prevent that from happening.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10222>
gallium hud uses different tgsi fragment shaders for text and background
quads, which have different varying layouts. Since these are compiled
directly from tgsi they bypass some optimizations and may not work
properly on all backends.
A simple fix for the varying layout problem is to define a vs_text
shader to match the varyings in fs_text so the problem is avoided.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10222>
As requested by Ken since we're now (after 20e2c7308f)
re-emitting constants at the beginning of every batch which may lead
to some redundant constant restore overhead. No statistically
significant performance changes observed with either change.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9903>
One of the conclusions of our recent clean up on the limits was that
the pipeline limits needed to be the per-stage limits multiplied by
the number of stages.
But until now we only have a set of descriptor maps for the full
pipeline. That would work if we could set the same limit per pipeline
that per stage, but that is not the case. So if, for example, we have
the fragment shader using V3D_MAX_TEXTURE_SAMPLERS textures, and then
the vertex shader, with a different descriptor set, using one texture,
we would get an index greater that V3D_MAX_TEXTURE_SAMPLERS. We assert
that index as an error on the vulkan backend, but fwiw, it would be
also asserted on the compiler.
With this commit we track and allocate a descriptor map per stage,
although we reuse the vertex shader descriptor map for the vertex bin.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10272>
Fixes piglit crashes doing glCopyTexSubImage from (for example)
PIPE_FORMAT_Z24_UNORM_S8_UINT to PIPE_FORMAT_Z32_FLOAT_S8X24_UINT where,
in addition to reading the source Z values incorrectly, we would try to
dereference the missing separate stencil of the Z24S8 buffer.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10328>
I have a note in -flakes.txt about how it can flake to being a Crash
instead of a Fail, but I haven't been able to reproduce that flake today.
It does always fail in the GS subtest, though, so quiet the flake spam in
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10330>
We set this in deqp-runner runs to disable Mesa debug/debugoptimized
builds printing to stderr for expected GL test behavior, and with the
addition of dEQP-EGL mapi got very verbose. Move it to a call_once() too
to avoid data races.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10240>
This will be used to test llvmpipe against Xvfb and freedreno against
Xorg. We keep the core deqp testing on surfaceless because
--deqp-surface-type=pbuffer fails on x11_egl_glx, =fbo has never worked in
VK-GL-CTS, and =window would increase test runtime for all the
swapbuffers.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10240>
Since we can handle arbitrary offsets in the load_ubo paths, we can let
the GLSL compiler pack UBO 0 tighter, saving uniform uploads. This may
cause some straddling loads that could reduce performance for vec3s, but
those are rare in shader-db and we expect this to be outweighed by the
wins for normal float/vec2 packing.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10151>
In looking at the profile of dEQP, GLES3 was spending 5-10% of its time in
ReadPixels, and almost all of that is b8g8r8a8_unorm8. It's really slow
because we're getting about 47MB/s by doing uncached reads 32 bits at a
time in the code-generated unpack. If we use NEON to generate larger bus
transactions, we can speed things up to 136MB/s. In comparison, raw
ldr/str read/writes with no byte swapping can hit a max of 216MB/sec.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10014>
We have only a few callers of unpack that do rects, so add a helper that
iterates over y adding the strides. This saves us 36kb of generated code
and means that adding cpu-specific variants for RGBA format unpack will be
much simpler.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10014>
The "demote" intrinsic has the semantics of D3D discard, which means
it doesn't change the control flow, allowing derivatives to work.
On A6xx there is no known way to check whether invocation was demoted,
thus we use nir_lower_is_helper_invocation.
Add "logical" OPC_DEMOTE which is later translated to "kill".
Such separation is necessary to run "kill" specific optimizations
which are invalid for "demote".
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9460>
Some hardware doesn't have a way to check if invocation was demoted,
in such case we have to track it ourselves.
OpIsHelperInvocationEXT is specified as:
"An invocation is currently a helper invocation if it was originally
invoked as a helper invocation or if it has been demoted to a helper
invocation by OpDemoteToHelperInvocationEXT."
Therefore we:
- Set gl_IsHelperInvocationEXT = gl_HelperInvocation
- Add "gl_IsHelperInvocationEXT = true" right before each demote
- Add "gl_IsHelperInvocationEXT = gl_IsHelperInvocationEXT || condition"
right before each demote_if
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9460>
immediates_count and immediates_size are supposed to have the same
units, but it was only incrementing immediates_count by 1. While we're
here, also fix the case where constants are specified out-of-order.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
Otherwise we can end up in situations like having divide-by-zero. If the optimization is smart enough
that we end up with a *constant* divide-by-zero, then the DXIL validator will fail to sign, which
can trigger fatal errors with CLOn12.
We want to run an initial translation of all kernels during program build, but at that point we don't
know the local size to be able to specify it through kernel specialization data.
v2: Metadata output of 0 is used to indicate that the size wasn't explicitly specific. Copy the
size to the metadata before overriding it to (1,1,1). If conf was explicitly specified,
update the metadata again (though nobody should be paying attention to it).
Closes: https://github.com/microsoft/OpenCLOn12/issues/20
Closes: https://github.com/darktable-org/darktable/issues/8700
Reviewed-By: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10303>
Certain games create and destroy lots of resources without binding them.
This can take quite a bit of time and even create unneeded
synchronization. However, we know that if a resource was never bound to
anything, it can be cached. This change does that.
Counting the number of uncached allocation with a tabletop simulator trace:
Before: 2967 uncached allocations over the replay
After: 24 uncached allocations over the replay
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10225>
This is going to make it easier to implement the custom border-color
extension.
While we're moving the code, tweak the memset code a bit, so we don't do
any float-ism in the int-case. It doesn't change anything functionally,
just makes it slightly clearer what's going on here.
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10320>
tcs user vars are var_size[32], which isn't actually how many slots they need,
just how big the variable is (oops), so this needs to be divided
by MAX_PATCH_VERTICES to get the real slot count
slot mapping has always been broken for all tcs inputs, but this probably fixes
all of the related issues there, including unlimited crashes when playing Tomb Raider
Fixes: 2d98efd323 ("zink: pre-populate locations in variables")
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10269>
nir_convert_from_ssa and assign_io_locations both modify this unconditionally,
the latter of which possibly re-modifies variables in ways that can break the
slot map and cause stack overflows during vk driver pipeline compilation
Fixes: 2b4609b66c ("zink: run nir_convert_from_ssa last during compile")
Fixes: 2d98efd323 ("zink: pre-populate locations in variables")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10269>
This cap should only ever be emitted for fragment-shaders, but we
accidentally emit it for all shaders. Let's tighten the check to avoid a
validator warning when emitting non-fragment shaders without support for
VK_EXT_shader_stencil_export.
Fixes: 8724d4fb36 ("zink: check shader stencil output")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10249>
With the new Vulkan Video extensions a bunch of enum values have been
added. The problem is that those are behind #ifdef so our generated
code complains that we using enum values not defined.
Since we're not using enum names but integer values, we can silence
all those by casting the enum type to int64_t.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10304>
The prog_to_nir->NIR-to-TGSI change ended up causing regressions on r300,
and svga against r300-class hardware, because nir_lower_uniforms_to_ubo()
introduced shifts that nir_lower_ubo_vec4() tried to reverse, but that NIR
couldn't prove are no-ops (since shifting up and back down may drop bits),
and the hardware can't do the integer ops.
Instead, make it so that nir_lower_uniforms_to_ubo can generate
nir_intrinsic_load_ubo_vec4 directly for !INTEGER hardware.
Fixes: cf3fc79cd0 ("st/mesa: Replace mesa_to_tgsi() with prog_to_nir() and nir_to_tgsi().")
Closes: #4602
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10194>
This has been confirmed to fix sporadic graphics corruption on Gen12
platforms for a number of workloads (including Heaven, Valley and
CS:GO among others). Corruption seems to occur during context switch
fairly consistently, but unfortunately this problem doesn't seem to be
documented. Until the hardware team comes up with a better
workaround, fix the problem by reemitting constants at the beginning
of each batch.
No corruption has been observed so far in GL due to preemption,
however this is a possibility to keep in mind, it may be necessary to
disable preemption in addition to this patch in order to fully address
this problem (see also 81201e4617).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4412
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4454
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Previously UBOs only supported static indices, and SSBOs only
supported dynamic indices. UBO support for descriptors was added
as an alternative to static indices, but the logic for detecting
descriptors to SSBOs couldn't just differentiate on constants vs not.
Add a helper which can differentiate cleanly across the board and
handle pre-created handles from descriptors, or static/dynamic raw
indices.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Instead of doing all of the handle logic in the descriptor load, split
it so that the resource index is actually computed during resource_index
processing, and it's converted to a handle during the load_descriptor.
At the same time, add SSBO handling and dynamic indexing handling.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Fixes the following building error:
external/mesa/src/egl/drivers/dri2/platform_android.c:1263:10: error: use of undeclared identifier 'FALLTHROUGH'
FALLTHROUGH; /* for pbuffers */
^
1 error generated.
Fixes: 2928c21eb7 ("Convert most remaining free-form fall-through comments to FALLTHROUGH")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10264>
We were using the pipeline layout to discard uniform updates for
stages that don't use descriptors, but we can do better by keeping
track of the stages used by the specific dirty descriptor sets and
only update uniforms for stages that are included in those.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
In 27ee40f4c9 ("anv: Add support for sample locations") we
introduced the ability to emit sample locations baked in as part of
the pipeline or dynamically.
This is different from the previous dynamic states that were always
removed from the pipeline batch and instead emitted dynamically all
the time.
The mistake in 27ee40f4c9 is that sample locations are now emitted
all the time, leading to bigger command buffers for unnecessary
reasons.
This change introduces a bit fields of what is baked in the pipeline
and doesn't need to be dynamically emitted.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4ad4cd8906 ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
When pipeline->dynamic_state.sample_locations.samples is not set
because the state is dynamic, we're currently calling
genX(emit_multisample) with a 0 samples value which is incorrect.
Found when using renderdoc with the drawing overlay.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4ad4cd8906 ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
These are rare enough to not be worth tracking separately. Especially
since after this change all the known_gl_extensions have N for both
direct_support and direct_only (unsurprising, since that's only used to
compute usable indirect extensions).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
... at least as far as libGL is concerned, because they'd work just fine
if you tried. The only thing the ATI extension seems to add (I can't
find an official spec, this is inferred from the registry XML) is
selecting the GLX_RENDER_TYPE, which we don't validate before putting on
the wire. The only thing the NV extension adds is an additional fbconfig
attribute, and that only known by glXGetFBConfigAttrib; our
implementation of that just reads the value the server sends, if any,
and doesn't try to filter out unknown attributes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
The "left here but disabled" comment dates to 2004! The idea here is to
add extensions implied by a particular GL version to the GL extension
string, but nothing useful is accomplished by doing so, and this is all
only used in the case of indirect rendering anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
The PIXEL_X/Y opcodes used by the current implementation are broken on
XeHP due to the new regioning restrictions of the floating-point pipe.
We could have the regioning lowering pass fix it in theory by lowering
the conversions into separate MOV instructions, but that would be more
costly than this implementation that only needs a pair of pipelined
ADDs and a pair of pipelined MOVs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Unfortunately the funky Align1 regions used by the code generator in
order to implement derivatives efficiently aren't available to the
floating-point pipeline on XeHP. We need to lower them into a number
of pipelined integer shuffle instructions followed by the
floating-point difference computation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
It has been removed from the hardware.
[jordan.l.justen@intel.com: Move to brw_postprocess_nir]
v2: Switch to nir_lower_idiv_precise (Rhys).
v3: Fix for interface changes of nir_lower_idiv.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
The floating-point and double-precision FPU pipelines of XeHP
platforms don't support arbitrary regioning modes, corresponding
channels of sources and destination are required to be aligned to the
same sub-register offset, similar to the restriction FP64 instructions
had on CHV/BXT platforms.
Most violations of this restriction can be fixed easily by teaching
has_dst_aligned_region_restriction() about the change so the regioning
lowering pass gets rid of any unsupported regioning. For cases where
this is not sufficient (e.g. because a virtual instruction internally
uses some regioning mode not supported by the floating-point pipeline)
the regioning lowering pass is extended with an additional
lower_exec_type() codepath that bit-casts sources and destination to
an integer type whenever the execution type is not supported by the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
The regioning mode used here is no longer supported by the
floating-point pipeline. We could run the regioning lowering pass in
order to fix it with some extra copies, but it's more efficient to
change the instruction to use integer types.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
In combination with the previous changes we can just check whether an
instruction has any potentially unsatisfied dependencies on more than
one pipeline, and if so use TGL_PIPE_ALL synchronization with an
appropriate RegDist counter, otherwise synchronize with the single
pipeline it has a dependency on, if any.
Only minor difficulty is caused by the fact that the hardware doesn't
have any way to encode pipeline information when a RegDist and an SBID
dependency need to be provided simultaneously, in which case the
synchronization pipeline is inferred by the hardware. We need to
verify that the hardware's inference will give the correct result
(which may not be the case if e.g. some data was bit-cast from a
different type), and if not emit separate SYNC instructions instead of
baking the RegDist dependency into the instruction (Note that SET SBID
dependencies must always be baked into the corresponding out-of-order
instruction).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
This extends the current ordered_address instruction counter to a
vector with one component per asynchronous ALU pipeline, allowing us
to track the last instruction that accessed a register separately for
each ALU pipeline of the XeHP EU, making it straightforward to
infer the right cross-pipeline synchronization annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: Make unit tests happy (with ubsan as run by GitLab automation).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Define two helper functions local to the software scoreboard lowering
pass describing the behavior of the hardware and code generator:
inferred_sync_pipe() calculates the ALU pipeline the hardware will
implicitly synchronize with when a RegDist SWSB annotation is used
without providing explicit pipeline synchronization information,
inferred_exec_pipe() infers the ALU pipeline that will execute the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
The execution units of XeHP platforms have multiple asynchronous ALU
pipelines instead of (as far as software is concerned) the single
in-order pipeline that handled most ALU instructions except for
extended math in the original Xe. It's now the compiler's
responsibility to identify cross-pipeline dependencies and insert
synchronization annotations whenever necessary, which are encoded as
some additional bits of the SWSB instruction field.
This commit represents the cross-pipeline synchronization annotations
as part of the existing tgl_swsb structure used for codegen. The
existing tgl_swsb_*() helpers used by hand-crafted assembly are
extended to default to TGL_PIPE_ALL big-hammer synchronization in
order to ensure backwards compatibility with the existing assembly.
The following commits will extend the software scoreboard lowering
pass in order to keep track of cross-pipeline dependencies across IR
instructions, and insert more specific pipeline annotations in the
SWSB field.
The disassembler is also extended here to print out any existing
pipeline sync annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
For baremetal CI we are using a 'dummy' rootfs as it is required by
abootimg. This causes NFS boot problems when using u-boot as bootloader.
[ 13.230968] RAMDISK: gzip image found at block 0
[ 13.235645] using deprecated initrd support, will be removed in 2021.
[ 13.243106] List of all partitions:
If we disable CONFIG_BLK_DEV_INITRD nfsroot works.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10024>
These have flaked as Timeouts in CI in the last month. .precision.* is
generally very slow (some in the 15s-30s range), but it's unclear to me
why they sometimes spike up to 60 seconds (thermal throttling?).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10274>
The parameters GL_TEXTURE_MIN_LOD, GL_TEXTURE_MAX_LOD,
GL_TEXTURE_MAX_ANISOTROPY_EXT, GL_TEXTURE_LOD_BIAS are stored as floats but
returned as integers. Setting their values outside of the integer range results
has undefined behaviour when the c-runtime method lroundf converts the value
back to an integer.
Fixes: 53c36dfc('replace IROUND with util functions')
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10244>
We have to keep sampler uniforms around for later YUV lowering, and we
only need to remove uniforms that take up storage space. Code comes from
radeonsi.
Closes: #4644.
Fixes: de17b4aab5 ("freedreno: Remove uniform variables after finalizing NIR.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10246>
Avoids warning about the annotation with GCC 10:
../src/gallium/frontends/osmesa/osmesa.c: In function ‘osmesa_choose_format’:
../src/util/compiler.h:84:21: warning: attribute ‘fallthrough’ not preceding a case label or default label
84 | #define FALLTHROUGH __attribute__((fallthrough))
| ^~~~~~~~~~~~~
../src/gallium/frontends/osmesa/osmesa.c:316:7: note: in expansion of macro ‘FALLTHROUGH’
316 | FALLTHROUGH;
| ^~~~~~~~~~~
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
They're not warning-clean yet, but we can enable -Werror in general and
just allow the existing types of warnings as exceptions with
-Wno-error=[...]. This way, new warnings of all other types will be
prevented from entering the code base.
Once all warnings of a certain type have been eliminated in a job, the
exception for that type can be dropped from that job. This provides a
realistic path to a fully warning-clean CI build in the future.
v2:
* Use echo -n (Juan A. Suarez)
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Avoids warnings on armhf:
./src/gallium/drivers/lima/ir/pp/nir.c: In function 'ppir_get_block':
../src/gallium/drivers/lima/ir/pp/nir.c:554:66: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
ppir_block *block = _mesa_hash_table_u64_search(comp->blocks, (uint64_t)nblock);
^
../src/gallium/drivers/lima/ir/pp/nir.c: In function 'ppir_compile_nir':
../src/gallium/drivers/lima/ir/pp/nir.c:899:52: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
_mesa_hash_table_u64_insert(comp->blocks, (uint64_t)nblock, block);
^
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
If we push a UBO range but then find out at draw-time that part of the
pushed range is out of range of the UBO descriptor, then we have to fill
in the rest of the range with 0's to mimic the bounds-checking that ldc
would've done.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
We were never setting set->size, so we were always copying 0 bytes. But
as we only copy the contents when the layout and therefore the size is
the same, we don't have to take the old size into account anyway.
This fixes some VK_EXT_robustness2 tests that use push descriptors.
Fixes: 6d4f33e ("turnip: initial implementation of VK_KHR_push_descriptor")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
This needs to be part of the compiler because it's the only piece that
we always have access to in all the places ir3_optimize_loop() is
called, and it's only enabled for the whole Vulkan device. Right now
it's just used for constraining vectorization, but the next commit adds
another use.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
This fixes
dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.len_260.samples_1.1d.frag,
which accesses the shader UBO with c<a0.x + 512> due to the constant
data UBO coming before it in the const file. The len_256 variant has a
smaller constant data UBO, so it uses c<a0.x + 256> instead, and that
works, so 512 seems to be the real limit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
We forgot to remove the instruction under consideration from instr_list
before inserting it into the block's list, which caused instr_list to
become corrupted. This happened to work but caused further corruption in
some rare scenarios.
Fixes: adf1659 ("freedreno/ir3: use standard list implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Dedicated BOs waste memory and are also a significant cause of CPU
overhead when applications use hundreds of them per frame due to
all the work the kernel has to do to page in all these BOs for a job.
The UE4 Vehicle demo was hitting this causing it to freeze and stutter
under 1fps.
The hardware allows us to setup groups of 16 queries in consecutive
4-byte addresses, requiring only that each group of 16 queries is
aligned to a 1024 byte boundary. With this change, we allocate all
the queries in a pool in a single BO and we assign them different
offsets based on the above restriction. This eliminates the freezes
and stutters in the Vehicle sample.
One caveat of this solution is that we can only wait or test for
completion of a query by testing if the GPU is still using its BO,
which basically means that we can only wait for all active queries
in a pool to complete and not just the ones being requested by the
API. Since the Vulkan recommendation is to use a different query
pool per frame this should not be a big issue though.
If this ever becomes a problem (for example if an application does't
follow the recommendation and instead allocates a single pool and
splits its queries between frames), we could try to group queries
in a pool into a number of BOs to try and find a balance, but for
now this should work fine in most cases.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10253>
ACO doesn't create a waitcnt for barriers between texture samples and
image stores because texture samples are supposed to use read-only
memory. It could also schedule the barrier to above the texture sample.
We also have use a larger memory scope to avoid an ACO optimization.
Tested on GFX8 with Sachsa Willems deferred sample. With some DCC
decompressions and the compute path forced.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9496>
The resource indices we get point to descriptor map entries that include
all shader stages, so we need to size the arrays to account for more than
just one stage.
For now we only support up to 2 stages in a pipeline, so we use that.
Fixes: 002304482c ('v3dv: avoid redundant BO job additions for UBO/SSBO')
Fixes: fa170dab4c ('v3dv: avoid redundant BO job additions for textures and samplers')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
There were various issues here:
- MAX_DYNAMIC_UNIFORM_BUFFERS was larger than MAX_UNIFORM_BUFFERS.
- In some cases we were exposing more than the minimums required.
While that is not incorrect, it is not following what we have
been doing in general.
- The Vulkan spec states that some of the MaxDescriptorSet limits
need to be multipled by 6 to include all shader stages, even
if the implementation doesn't support all shader stages.
Fixes: cbd299b051 ('v3dv/device: do not compute per-pipeline limits multiplying per-stage')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
piglit_gl clocked in at 6:12 end-to-end runtime, and piglit_shader spent
2:53 in deqp-runner, so merging them together should be about 9 minutes.
Removing a boot should save us a minute or two of runner time per
pipeline.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10243>
Accept non-linear tiling for multi-planar formats on GFX9+, as long
as DCC is disabled. DCC support is possible in theory, but untested
for now.
GFX8 is still restricted to linear tiling because it's not yet clear
how modifiers should be handled on these chips for multi-planar
formats. Each plane may need a different modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Instead of having a special case for YUV formats in
si_query_dmabuf_modifiers, let ac_get_supported_modifiers handle
them. Keep setting external_only = 1 for YUV formats, since we
can only sample from such formats (we can't use them as render
targets).
This shouldn't change si_query_dmabuf_modifiers's behavior, because
for YUV formats ac_get_supported_modifiers will return a single
LINEAR modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
util_format_get_blocksize asserts that the blocksize isn't zero.
However the blocksize will be zero if the format's channel encoding
is unspecified. The channel encoding is only meaningful for the
plain u_format layout, so util_format_get_blocksize can't be used
for formats with another layout. For example, YUV formats don't have
the channel encoding specified.
Use util_format_get_blocksizebits, which just returns zero without
an assertion for formats which don't have a channel encoding.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
We are flushing tile cache more often than is necessary. In
unified cache mode, tile cache flushing is expensive, evicting all
depth/pixel data from the L3$. This is only need for a handful of
cases, such as: making cpu or gpu changes globally visible
(e.g. map), fast color clears, or slow depth clears. Tile cache
flushing is a gen12+ feature.
Remove blanket flushing of tile cache on all depth/RT flushes.
Replace with selective tile cache flushing.
Improves performance in several workloads:
AztecRuins.ogl-high-offscreen-1440p 1%
UnigineValley.ogl-g2 1%
Dota 2 (replay Jul 2020).ogl-g2 1%
Counter-Strike GO.ogl-g2 1%
Manhattan.ogl-Off-19x10 2%
CarChase.ogl-Off-19x10 1%
Bioshock Infinite.ogl-g2 1%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
We don't need to initialize the BO since blorp updates the clear color
BO content with fast clear value i.e ANV_HZ_FC_VAL for depth surface.
With this approach, we can get rid of possibility of corruption since we
are no longer sharing the same clear BO for depth formats.
Closes: #3614
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9941>
Previously, on the platforms which support the indirect clear color
values, we were just setting the clear color address and not enforcing
any clear color values but some of the blorp operations were using the
wrong fast clear value.
With this patch, we make sure to set the correct fast clear color value
during blorp operations.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9941>
Groups registers which need to be assigned to consecutive scalar
registers, for example `sam` (texture fetch) src instructions (see
`register groups`_) or array element dereference
(see `relative addressing`_).
**fanout**
The counterpart to **fanin**, when an instruction such as `sam`
**split**
The counterpart to **collect**, when an instruction such as `sam`
writes multiple components, splits the result into individual
scalar components to be consumed by other instructions.
@@ -202,22 +202,22 @@ Before register assignment, to group the two components of the texture src toget
digraph G {
{ rank=same;
fanin;
collect;
};
{ rank=same;
coord_x;
coord_y;
};
sam -> fanin [label="regs[1]"];
fanin -> coord_x [label="regs[1]"];
fanin -> coord_y [label="regs[2]"];
sam -> collect [label="regs[1]"];
collect -> coord_x [label="regs[1]"];
collect -> coord_y [label="regs[2]"];
coord_x -> coord_y [label="right",style=dotted];
coord_y -> coord_x [label="left",style=dotted];
coord_x [label="coord.x"];
coord_y [label="coord.y"];
}
The frontend sets up the SSA ptrs from ``sam`` source register to the ``fanin`` meta instruction, which in turn points to the instructions producing the ``coord.x`` and ``coord.y`` values. And the grouping_ pass sets up the ``left`` and ``right`` neighbor pointers to the ``fanin``\'s sources, used later by the `register assignment`_ pass to assign blocks of scalar registers.
The frontend sets up the SSA ptrs from ``sam`` source register to the ``collect`` meta instruction, which in turn points to the instructions producing the ``coord.x`` and ``coord.y`` values. And the grouping_ pass sets up the ``left`` and ``right`` neighbor pointers to the ``collect``\'s sources, used later by the `register assignment`_ pass to assign blocks of scalar registers.
And likewise, for the consecutive scalar registers for the destination:
@@ -230,23 +230,23 @@ And likewise, for the consecutive scalar registers for the destination:
The scheduling pass has some smarts to schedule things such that only a single ``a0.x`` value is used at any one time.
To implement variable arrays, values are stored in consecutive scalar registers. This has some overlap with `register groups`_, in that ``fanin`` and ``fanout`` are used to help group things for the `register assignment`_ pass.
To use a variable array as a src register, a slight variation of what is done for const array src. The instruction src is a `fanin` instruction that groups all the array members:
To implement variable arrays, the NIR registers are stored as an ``ir3_array``,
which will be register allocated to consecutive hardware registers. The array
access uses the id field in the ``ir3_register`` to map to the array being
accessed, and the offset field for the fixed offset within the array. A NIR
TODO better describe how actual deref offset is derived, i.e. based on array base register.
To do an indirect write to a variable array, a``fanout`` is used. Say the array was assigned to registers ``r0.z`` through ``r1.y`` (hence the constant offset of 2):
Note that only cat1 (mov) can do indirect write.
Array writes write to the array in``instr->regs[0]->array.id``. A NIR indirect
register write such as:
::
mova a0.x, hr1.y
min r2.x, r2.x, c0.x
mov r<a0.x + 2>, r2.x
mul r0.x, r0.z, c0.z
decl_reg vec2 32 r0[2]
...
r0[0 + ssa_12] = mov ssa_13
results in:
In this case, the ``mov`` instruction does not write all elements of the array (compared to usage of ``fanout`` for ``sam`` instructions in grouping_). But the ``mov`` instruction does need an additional dependency (via ``fanin``) on instructions that last wrote the array element members, to ensure that they get scheduled before the ``mov`` in scheduling_ stage (which also serves to group the array elements for the `register assignment`_ stage).
::
..graphviz::
digraph {
a0 [label="r0.z"];
a1 [label="r0.w"];
a2 [label="r1.x"];
a3 [label="r1.y"];
min;
mova;
mov;
mul;
fanout [label="fanout\noff=0"];
mul -> fanout;
fanout -> mov;
fanin;
fanin -> a0;
fanin -> a1;
fanin -> a2;
fanin -> a3;
mov -> min;
mov -> mova;
mov -> fanin;
}
Note that there would in fact be ``fanout`` nodes generated for each array element (although only the reachable ones will be scheduled, etc).
Note that only cat1 (mov) can do indirect write, and thus NIR register stores
may need to introduce an extra mov.
ir3 array accesses in the DAG get serialized by the ``instr->barrier_class`` and
containing ``IR3_BARRIER_ARRAY_W`` or ``IR3_BARRIER_ARRAY_R``.
Shader Passes
-------------
@@ -401,7 +372,7 @@ The eventual plan is to invert that, with the front-end inserting no ``mov``\s a
Grouping
~~~~~~~~
In the grouping pass, instructions which need to be grouped (for ``fanin``\s, etc) have their ``left`` / ``right`` neighbor pointers setup. In cases where there is a conflict (i.e. one instruction cannot have two unique left or right neighbors), an additional ``mov`` instruction is inserted. This ensures that there is some possible valid `register assignment`_ at the later stages.
In the grouping pass, instructions which need to be grouped (for ``collect``\s, etc) have their ``left`` / ``right`` neighbor pointers setup. In cases where there is a conflict (i.e. one instruction cannot have two unique left or right neighbors), an additional ``mov`` instruction is inserted. This ensures that there is some possible valid `register assignment`_ at the later stages.
.._depth:
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