VERSION: bump for 21.2-rc2

With this pass enabled in Intel drivers, running shader-db on
shaders/unity/38.shader_test resulted in

Program received signal SIGSEGV, Segmentation fault.
gcm_schedule_early_src (src=0x555555d45348, void_state=0x7fffffffba40) at ../../SOURCE/master/src/compiler/nir/nir_opt_gcm.c:297
297	   if (info->early_block->index < src_info->early_block->index)
(gdb) print src_info->early_block
$1 = (nir_block *) 0x0

I tracked this down to an early exit from gcm_schedule_early_instr on
the parent instruction because instr->pass_flags was 0x1c.  That
should be an impossible value for this pass, so I inferred that
pass_flags must have dirt left from some previous pass.

Fixes: 8dfe6f672f ("nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinned")

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
(cherry picked from commit 436668874a)

.gitlab-ci/crosvm-runner.sh

@@ -8,6 +8,8 @@ export LD_LIBRARY_PATH=$CI_PROJECT_DIR/install/lib/
 export EGL_PLATFORM=surfaceless
 
 export -p > /crosvm-env.sh
+export GALLIUM_DRIVER="$CROSVM_GALLIUM_DRIVER"
+export LIBGL_ALWAYS_SOFTWARE="true"
 
 CROSVM_KERNEL_ARGS="root=my_root rw rootfstype=virtiofs loglevel=3 init=$CI_PROJECT_DIR/install/crosvm-init.sh ip=192.168.30.2::192.168.30.1:255.255.255.0:crosvm:eth0"
 

VERSION

@@ -1 +1 @@
-21.2.0-devel
+21.2.0-rc2

src/amd/compiler/aco_optimizer.cpp

@@ -194,7 +194,8 @@ struct ssa_info {
       add_label(label_literal);
       val = constant;
 
-      if (chip >= GFX8 && !op16.isLiteral())
+      /* check that no upper bits are lost in case of packed 16bit constants */
+      if (chip >= GFX8 && !op16.isLiteral() && op16.constantValue64() == constant)
          add_label(label_constant_16bit);
 
       if (!op32.isLiteral())

src/amd/compiler/aco_util.h

@@ -29,6 +29,7 @@
 #include "util/bitscan.h"
 
 #include <cassert>
+#include <cstddef>
 #include <iterator>
 #include <vector>
 
@@ -51,7 +52,7 @@ public:
    using reverse_iterator = std::reverse_iterator<iterator>;
    using const_reverse_iterator = std::reverse_iterator<const_iterator>;
    using size_type = uint16_t;
-   using difference_type = ptrdiff_t;
+   using difference_type = std::ptrdiff_t;
 
    /*! \brief                  Compiler generated default constructor
     */

src/amd/vulkan/radv_cmd_buffer.c

@@ -2933,10 +2933,10 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_
             /* GFX10 uses OOB_SELECT_RAW if stride==0, so convert num_records from elements into
              * into bytes in that case. GFX8 always uses bytes.
              */
-            if (num_records && (chip == GFX8 || (chip >= GFX10 && !stride))) {
+            if (num_records && (chip == GFX8 || (chip != GFX9 && !stride))) {
                num_records = (num_records - 1) * stride + attrib_end;
             } else if (!num_records) {
-               /* On GFX9 (GFX6/7 untested), it seems bounds checking is disabled if both
+               /* On GFX9, it seems bounds checking is disabled if both
                 * num_records and stride are zero. This doesn't seem necessary on GFX8, GFX10 and
                 * GFX10.3 but it doesn't hurt.
                 */
@@ -5664,17 +5664,15 @@ enum {
 
 ALWAYS_INLINE static bool
 radv_skip_ngg_culling(bool has_tess, const unsigned vtx_cnt,
-                      bool indirect, unsigned num_viewports)
+                      bool indirect)
 {
    /* If we have to draw only a few vertices, we get better latency if
     * we disable NGG culling.
     *
     * When tessellation is used, what matters is the number of tessellated
     * vertices, so let's always assume it's not a small draw.
-    *
-    * TODO: Figure out how to do culling with multiple viewports efficiently.
     */
-   return !has_tess && !indirect && vtx_cnt < 512 && num_viewports == 1;
+   return !has_tess && !indirect && vtx_cnt < 512;
 }
 
 ALWAYS_INLINE static uint32_t
@@ -5757,9 +5755,7 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad
     * For small draw calls, we disable culling by setting the SGPR to 0.
     */
    const bool skip =
-      radv_skip_ngg_culling(
-         stage == MESA_SHADER_TESS_EVAL, draw_info->count, draw_info->indirect,
-         cmd_buffer->state.dynamic.viewport.count);
+      radv_skip_ngg_culling(stage == MESA_SHADER_TESS_EVAL, draw_info->count, draw_info->indirect);
 
    /* See if anything changed. */
    if (!dirty && skip == cmd_buffer->state.last_nggc_skip)
@@ -6621,7 +6617,7 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
 
    radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
 
-   if (radv_image_is_tc_compat_htile(image)) {
+   if (radv_image_is_tc_compat_htile(image) && (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)) {
       /* Initialize the TC-compat metada value to 0 because by
        * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
        * need have to conditionally update its value when performing

src/amd/vulkan/radv_device.c

@@ -863,6 +863,7 @@ static const driOptionDescription radv_dri_options[] = {
       DRI_CONF_RADV_INVARIANT_GEOM(false)
       DRI_CONF_RADV_DISABLE_TC_COMPAT_HTILE_GENERAL(false)
       DRI_CONF_RADV_DISABLE_DCC(false)
+      DRI_CONF_RADV_REPORT_APU_AS_DGPU(false)
    DRI_CONF_SECTION_END
 };
 // clang-format on
@@ -902,6 +903,9 @@ radv_init_dri_options(struct radv_instance *instance)
 
    if (driQueryOptionb(&instance->dri_options, "radv_disable_dcc"))
       instance->debug_flags |= RADV_DEBUG_NO_DCC;
+
+   instance->report_apu_as_dgpu =
+      driQueryOptionb(&instance->dri_options, "radv_report_apu_as_dgpu");
 }
 
 VkResult
@@ -1826,13 +1830,20 @@ radv_GetPhysicalDeviceProperties(VkPhysicalDevice physicalDevice,
       .nonCoherentAtomSize = 64,
    };
 
+   VkPhysicalDeviceType device_type;
+
+   if (pdevice->rad_info.has_dedicated_vram || pdevice->instance->report_apu_as_dgpu) {
+      device_type = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU;
+   } else {
+      device_type = VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU;
+   }
+
    *pProperties = (VkPhysicalDeviceProperties){
       .apiVersion = RADV_API_VERSION,
       .driverVersion = vk_get_driver_version(),
       .vendorID = ATI_VENDOR_ID,
       .deviceID = pdevice->rad_info.pci_id,
-      .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
-                                                         : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
+      .deviceType = device_type,
       .limits = limits,
       .sparseProperties =
          {

src/amd/vulkan/radv_meta_decompress.c

@@ -42,6 +42,7 @@ create_pass(struct radv_device *device, uint32_t samples, VkRenderPass *pass)
    VkAttachmentDescription2 attachment;
 
    attachment.sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
+   attachment.pNext = NULL;
    attachment.flags = 0;
    attachment.format = VK_FORMAT_D32_SFLOAT_S8_UINT;
    attachment.samples = samples;

src/amd/vulkan/radv_meta_fast_clear.c

@@ -153,6 +153,7 @@ create_pass(struct radv_device *device)
    VkAttachmentDescription2 attachment;
 
    attachment.sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
+   attachment.pNext = NULL;
    attachment.format = VK_FORMAT_UNDEFINED;
    attachment.samples = 1;
    attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;

src/amd/vulkan/radv_meta_resolve.c

@@ -57,6 +57,7 @@ create_pass(struct radv_device *device, VkFormat vk_format, VkRenderPass *pass)
 
    for (i = 0; i < 2; i++) {
       attachments[i].sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
+      attachments[i].pNext = NULL;
       attachments[i].format = vk_format;
       attachments[i].samples = 1;
       attachments[i].loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;

src/amd/vulkan/radv_pass.c

@@ -344,14 +344,20 @@ stencil_ref_layout(const VkAttachmentReference2 *att_ref)
    return stencil_ref->stencilLayout;
 }
 
-/* From the Vulkan Specification 1.2.166 - VkAttachmentDescription2:
+/* From the Vulkan Specification 1.2.184:
  *
- * "If format is a depth/stencil format, and initialLayout only specifies the
- *  initial layout of the depth aspect of the attachment, the initial layout of
- *  the stencil aspect is specified by the stencilInitialLayout member of a
- *  VkAttachmentDescriptionStencilLayout structure included in the pNext chain.
- *  Otherwise, initialLayout describes the initial layout for all relevant
- *  image aspects."
+ * "If the pNext chain includes a VkAttachmentDescriptionStencilLayout structure, then the
+ *  stencilInitialLayout and stencilFinalLayout members specify the initial and final layouts of the
+ *  stencil aspect of a depth/stencil format, and initialLayout and finalLayout only apply to the
+ *  depth aspect. For depth-only formats, the VkAttachmentDescriptionStencilLayout structure is
+ *  ignored. For stencil-only formats, the initial and final layouts of the stencil aspect are taken
+ *  from the VkAttachmentDescriptionStencilLayout structure if present, or initialLayout and
+ *  finalLayout if not present."
+ *
+ * "If format is a depth/stencil format, and either initialLayout or finalLayout does not specify a
+ *  layout for the stencil aspect, then the application must specify the initial and final layouts
+ *  of the stencil aspect by including a VkAttachmentDescriptionStencilLayout structure in the pNext
+ *  chain."
  */
 static VkImageLayout
 stencil_desc_layout(const VkAttachmentDescription2KHR *att_desc, bool final)
@@ -360,14 +366,12 @@ stencil_desc_layout(const VkAttachmentDescription2KHR *att_desc, bool final)
    if (!util_format_has_stencil(desc))
       return VK_IMAGE_LAYOUT_UNDEFINED;
 
-   const VkImageLayout main_layout = final ? att_desc->finalLayout : att_desc->initialLayout;
-   if (!vk_image_layout_depth_only(main_layout))
-      return main_layout;
-
    const VkAttachmentDescriptionStencilLayoutKHR *stencil_desc =
       vk_find_struct_const(att_desc->pNext, ATTACHMENT_DESCRIPTION_STENCIL_LAYOUT_KHR);
-   assert(stencil_desc);
-   return final ? stencil_desc->stencilFinalLayout : stencil_desc->stencilInitialLayout;
+
+   if (stencil_desc)
+      return final ? stencil_desc->stencilFinalLayout : stencil_desc->stencilInitialLayout;
+   return final ? att_desc->finalLayout : att_desc->initialLayout;
 }
 
 VkResult

src/amd/vulkan/radv_private.h

@@ -333,6 +333,7 @@ struct radv_instance {
    bool disable_tc_compat_htile_in_general;
    bool disable_shrink_image_store;
    bool absolute_depth_bias;
+   bool report_apu_as_dgpu;
 };
 
 VkResult radv_init_wsi(struct radv_physical_device *physical_device);

src/amd/vulkan/radv_shader.c

@@ -915,6 +915,10 @@ radv_consider_culling(struct radv_device *device, struct nir_shader *nir,
    if (!!nir->info.name)
       return false;
 
+   /* We don't support culling with multiple viewports yet. */
+   if (nir->info.outputs_written & (VARYING_BIT_VIEWPORT | VARYING_BIT_VIEWPORT_MASK))
+      return false;
+
    /* TODO: enable by default on GFX10.3 when we're confident about performance. */
    bool culling_enabled = device->instance->perftest_flags & RADV_PERFTEST_NGGC;
 

src/broadcom/ci/deqp-v3dv-rpi4-skips.txt

@@ -2,9 +2,6 @@
 dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_deltazero
 dEQP-VK.rasterization.depth_bias.d32_sfloat
 
-# This test causes GPU hangs (vk-gl-cts 1.2.6.2)
-dEQP-VK.graphicsfuzz.stable-binarysearch-tree-nested-if-and-conditional
-
 # Timeout tests (> 1 minute to run)
 dEQP-VK.api.object_management.max_concurrent.query_pool
 dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite

src/broadcom/compiler/nir_to_vir.c

@@ -3601,6 +3601,10 @@ ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
                 break;
 
         case nir_instr_type_jump:
+                /* Always flush TMU before jumping to another block, for the
+                 * same reasons as in ntq_emit_block.
+                 */
+                ntq_flush_tmu(c);
                 if (vir_in_nonuniform_control_flow(c))
                         ntq_emit_jump(c, nir_instr_as_jump(instr));
                 else

src/broadcom/vulkan/v3dvx_meta_clear.c

@@ -26,378 +26,3 @@
 #include "broadcom/cle/v3dx_pack.h"
 #include "broadcom/compiler/v3d_compiler.h"
 
-static void
-emit_tlb_clear_store(struct v3dv_cmd_buffer *cmd_buffer,
-                     struct v3dv_cl *cl,
-                     uint32_t attachment_idx,
-                     uint32_t layer,
-                     uint32_t buffer)
-{
-   const struct v3dv_image_view *iview =
-      cmd_buffer->state.framebuffer->attachments[attachment_idx];
-   const struct v3dv_image *image = iview->image;
-   const struct v3d_resource_slice *slice = &image->slices[iview->base_level];
-   uint32_t layer_offset = v3dv_layer_offset(image,
-                                             iview->base_level,
-                                             iview->first_layer + layer);
-
-   cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
-      store.buffer_to_store = buffer;
-      store.address = v3dv_cl_address(image->mem->bo, layer_offset);
-      store.clear_buffer_being_stored = false;
-
-      store.output_image_format = iview->format->rt_type;
-      store.r_b_swap = iview->swap_rb;
-      store.memory_format = slice->tiling;
-
-      if (slice->tiling == V3D_TILING_UIF_NO_XOR ||
-          slice->tiling == V3D_TILING_UIF_XOR) {
-         store.height_in_ub_or_stride =
-            slice->padded_height_of_output_image_in_uif_blocks;
-      } else if (slice->tiling == V3D_TILING_RASTER) {
-         store.height_in_ub_or_stride = slice->stride;
-      }
-
-      if (image->samples > VK_SAMPLE_COUNT_1_BIT)
-         store.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
-      else
-         store.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
-   }
-}
-
-static void
-emit_tlb_clear_stores(struct v3dv_cmd_buffer *cmd_buffer,
-                      struct v3dv_cl *cl,
-                      uint32_t attachment_count,
-                      const VkClearAttachment *attachments,
-                      uint32_t layer)
-{
-   struct v3dv_cmd_buffer_state *state = &cmd_buffer->state;
-   const struct v3dv_subpass *subpass =
-      &state->pass->subpasses[state->subpass_idx];
-
-   bool has_stores = false;
-   for (uint32_t i = 0; i < attachment_count; i++) {
-      uint32_t attachment_idx;
-      uint32_t buffer;
-      if (attachments[i].aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
-                                       VK_IMAGE_ASPECT_STENCIL_BIT)) {
-         attachment_idx = subpass->ds_attachment.attachment;
-         buffer = v3dX(zs_buffer_from_aspect_bits)(attachments[i].aspectMask);
-      } else {
-         uint32_t rt_idx = attachments[i].colorAttachment;
-         attachment_idx = subpass->color_attachments[rt_idx].attachment;
-         buffer = RENDER_TARGET_0 + rt_idx;
-      }
-
-      if (attachment_idx == VK_ATTACHMENT_UNUSED)
-         continue;
-
-      has_stores = true;
-      emit_tlb_clear_store(cmd_buffer, cl, attachment_idx, layer, buffer);
-   }
-
-   if (!has_stores) {
-      cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
-         store.buffer_to_store = NONE;
-      }
-   }
-}
-
-static void
-emit_tlb_clear_per_tile_rcl(struct v3dv_cmd_buffer *cmd_buffer,
-                            uint32_t attachment_count,
-                            const VkClearAttachment *attachments,
-                            uint32_t layer)
-{
-   struct v3dv_job *job = cmd_buffer->state.job;
-   assert(job);
-
-   struct v3dv_cl *cl = &job->indirect;
-   v3dv_cl_ensure_space(cl, 200, 1);
-   v3dv_return_if_oom(cmd_buffer, NULL);
-
-   struct v3dv_cl_reloc tile_list_start = v3dv_cl_get_address(cl);
-
-   cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
-
-   cl_emit(cl, END_OF_LOADS, end); /* Nothing to load */
-
-   cl_emit(cl, PRIM_LIST_FORMAT, fmt) {
-      fmt.primitive_type = LIST_TRIANGLES;
-   }
-
-   cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
-
-   emit_tlb_clear_stores(cmd_buffer, cl, attachment_count, attachments, layer);
-
-   cl_emit(cl, END_OF_TILE_MARKER, end);
-
-   cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
-
-   cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
-      branch.start = tile_list_start;
-      branch.end = v3dv_cl_get_address(cl);
-   }
-}
-
-static void
-emit_tlb_clear_layer_rcl(struct v3dv_cmd_buffer *cmd_buffer,
-                         uint32_t attachment_count,
-                         const VkClearAttachment *attachments,
-                         uint32_t layer)
-{
-   const struct v3dv_cmd_buffer_state *state = &cmd_buffer->state;
-   const struct v3dv_framebuffer *framebuffer = state->framebuffer;
-
-   struct v3dv_job *job = cmd_buffer->state.job;
-   struct v3dv_cl *rcl = &job->rcl;
-
-   const struct v3dv_frame_tiling *tiling = &job->frame_tiling;
-
-   const uint32_t tile_alloc_offset =
-      64 * layer * tiling->draw_tiles_x * tiling->draw_tiles_y;
-   cl_emit(rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
-      list.address = v3dv_cl_address(job->tile_alloc, tile_alloc_offset);
-   }
-
-   cl_emit(rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
-      config.number_of_bin_tile_lists = 1;
-      config.total_frame_width_in_tiles = tiling->draw_tiles_x;
-      config.total_frame_height_in_tiles = tiling->draw_tiles_y;
-
-      config.supertile_width_in_tiles = tiling->supertile_width;
-      config.supertile_height_in_tiles = tiling->supertile_height;
-
-      config.total_frame_width_in_supertiles =
-         tiling->frame_width_in_supertiles;
-      config.total_frame_height_in_supertiles =
-         tiling->frame_height_in_supertiles;
-   }
-
-   /* Emit the clear and also the workaround for GFXH-1742 */
-   for (int i = 0; i < 2; i++) {
-      cl_emit(rcl, TILE_COORDINATES, coords);
-      cl_emit(rcl, END_OF_LOADS, end);
-      cl_emit(rcl, STORE_TILE_BUFFER_GENERAL, store) {
-         store.buffer_to_store = NONE;
-      }
-      if (i == 0) {
-         cl_emit(rcl, CLEAR_TILE_BUFFERS, clear) {
-            clear.clear_z_stencil_buffer = true;
-            clear.clear_all_render_targets = true;
-         }
-      }
-      cl_emit(rcl, END_OF_TILE_MARKER, end);
-   }
-
-   cl_emit(rcl, FLUSH_VCD_CACHE, flush);
-
-   emit_tlb_clear_per_tile_rcl(cmd_buffer, attachment_count, attachments, layer);
-
-   uint32_t supertile_w_in_pixels =
-      tiling->tile_width * tiling->supertile_width;
-   uint32_t supertile_h_in_pixels =
-      tiling->tile_height * tiling->supertile_height;
-
-   const uint32_t max_render_x = framebuffer->width - 1;
-   const uint32_t max_render_y = framebuffer->height - 1;
-   const uint32_t max_x_supertile = max_render_x / supertile_w_in_pixels;
-   const uint32_t max_y_supertile = max_render_y / supertile_h_in_pixels;
-
-   for (int y = 0; y <= max_y_supertile; y++) {
-      for (int x = 0; x <= max_x_supertile; x++) {
-         cl_emit(rcl, SUPERTILE_COORDINATES, coords) {
-            coords.column_number_in_supertiles = x;
-            coords.row_number_in_supertiles = y;
-         }
-      }
-   }
-}
-
-static void
-emit_tlb_clear_job(struct v3dv_cmd_buffer *cmd_buffer,
-                   uint32_t attachment_count,
-                   const VkClearAttachment *attachments,
-                   uint32_t base_layer,
-                   uint32_t layer_count)
-{
-   const struct v3dv_cmd_buffer_state *state = &cmd_buffer->state;
-   const struct v3dv_framebuffer *framebuffer = state->framebuffer;
-   const struct v3dv_subpass *subpass =
-      &state->pass->subpasses[state->subpass_idx];
-   struct v3dv_job *job = cmd_buffer->state.job;
-   assert(job);
-
-   /* Check how many color attachments we have and also if we have a
-    * depth/stencil attachment.
-    */
-   uint32_t color_attachment_count = 0;
-   VkClearAttachment color_attachments[4];
-   const VkClearDepthStencilValue *ds_clear_value = NULL;
-   uint8_t internal_depth_type = V3D_INTERNAL_TYPE_DEPTH_32F;
-   for (uint32_t i = 0; i < attachment_count; i++) {
-      if (attachments[i].aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
-                                       VK_IMAGE_ASPECT_STENCIL_BIT)) {
-         assert(subpass->ds_attachment.attachment != VK_ATTACHMENT_UNUSED);
-         ds_clear_value = &attachments[i].clearValue.depthStencil;
-         struct v3dv_render_pass_attachment *att =
-            &state->pass->attachments[subpass->ds_attachment.attachment];
-         internal_depth_type = v3dX(get_internal_depth_type)(att->desc.format);
-      } else if (attachments[i].aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
-         color_attachments[color_attachment_count++] = attachments[i];
-      }
-   }
-
-   uint8_t internal_bpp;
-   bool msaa;
-   v3dX(framebuffer_compute_internal_bpp_msaa)(framebuffer, subpass,
-                                               &internal_bpp, &msaa);
-
-   v3dv_job_start_frame(job,
-                        framebuffer->width,
-                        framebuffer->height,
-                        framebuffer->layers,
-                        color_attachment_count,
-                        internal_bpp, msaa);
-
-   struct v3dv_cl *rcl = &job->rcl;
-   v3dv_cl_ensure_space_with_branch(rcl, 200 +
-                                    layer_count * 256 *
-                                    cl_packet_length(SUPERTILE_COORDINATES));
-   v3dv_return_if_oom(cmd_buffer, NULL);
-
-   const struct v3dv_frame_tiling *tiling = &job->frame_tiling;
-   cl_emit(rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
-      config.early_z_disable = true;
-      config.image_width_pixels = framebuffer->width;
-      config.image_height_pixels = framebuffer->height;
-      config.number_of_render_targets = MAX2(color_attachment_count, 1);
-      config.multisample_mode_4x = false; /* FIXME */
-      config.maximum_bpp_of_all_render_targets = tiling->internal_bpp;
-      config.internal_depth_type = internal_depth_type;
-   }
-
-   for (uint32_t i = 0; i < color_attachment_count; i++) {
-      uint32_t rt_idx = color_attachments[i].colorAttachment;
-      uint32_t attachment_idx = subpass->color_attachments[rt_idx].attachment;
-      if (attachment_idx == VK_ATTACHMENT_UNUSED)
-         continue;
-
-      const struct v3dv_render_pass_attachment *attachment =
-         &state->pass->attachments[attachment_idx];
-
-      uint32_t internal_type, internal_bpp, internal_size;
-      const struct v3dv_format *format =
-         v3dX(get_format)(attachment->desc.format);
-      v3dX(get_internal_type_bpp_for_output_format)(format->rt_type, &internal_type,
-                                                    &internal_bpp);
-      internal_size = 4 << internal_bpp;
-
-      uint32_t clear_color[4] = { 0 };
-      v3dX(get_hw_clear_color)(&color_attachments[i].clearValue.color,
-                               internal_type, internal_size, clear_color);
-
-      struct v3dv_image_view *iview = framebuffer->attachments[attachment_idx];
-      const struct v3dv_image *image = iview->image;
-      const struct v3d_resource_slice *slice = &image->slices[iview->base_level];
-
-      uint32_t clear_pad = 0;
-      if (slice->tiling == V3D_TILING_UIF_NO_XOR ||
-          slice->tiling == V3D_TILING_UIF_XOR) {
-         int uif_block_height = v3d_utile_height(image->cpp) * 2;
-
-         uint32_t implicit_padded_height =
-            align(framebuffer->height, uif_block_height) / uif_block_height;
-
-         if (slice->padded_height_of_output_image_in_uif_blocks -
-             implicit_padded_height >= 15) {
-            clear_pad = slice->padded_height_of_output_image_in_uif_blocks;
-         }
-      }
-
-      cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1, clear) {
-         clear.clear_color_low_32_bits = clear_color[0];
-         clear.clear_color_next_24_bits = clear_color[1] & 0xffffff;
-         clear.render_target_number = i;
-      };
-
-      if (iview->internal_bpp >= V3D_INTERNAL_BPP_64) {
-         cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2, clear) {
-            clear.clear_color_mid_low_32_bits =
-              ((clear_color[1] >> 24) | (clear_color[2] << 8));
-            clear.clear_color_mid_high_24_bits =
-              ((clear_color[2] >> 24) | ((clear_color[3] & 0xffff) << 8));
-            clear.render_target_number = i;
-         };
-      }
-
-      if (iview->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
-         cl_emit(rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3, clear) {
-            clear.uif_padded_height_in_uif_blocks = clear_pad;
-            clear.clear_color_high_16_bits = clear_color[3] >> 16;
-            clear.render_target_number = i;
-         };
-      }
-   }
-
-   cl_emit(rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
-      v3dX(cmd_buffer_render_pass_setup_render_target)
-         (cmd_buffer, 0, &rt.render_target_0_internal_bpp,
-          &rt.render_target_0_internal_type, &rt.render_target_0_clamp);
-      v3dX(cmd_buffer_render_pass_setup_render_target)
-         (cmd_buffer, 1, &rt.render_target_1_internal_bpp,
-          &rt.render_target_1_internal_type, &rt.render_target_1_clamp);
-      v3dX(cmd_buffer_render_pass_setup_render_target)
-         (cmd_buffer, 2, &rt.render_target_2_internal_bpp,
-          &rt.render_target_2_internal_type, &rt.render_target_2_clamp);
-      v3dX(cmd_buffer_render_pass_setup_render_target)
-         (cmd_buffer, 3, &rt.render_target_3_internal_bpp,
-          &rt.render_target_3_internal_type, &rt.render_target_3_clamp);
-   }
-
-   cl_emit(rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES, clear) {
-      clear.z_clear_value = ds_clear_value ? ds_clear_value->depth : 1.0f;
-      clear.stencil_clear_value = ds_clear_value ? ds_clear_value->stencil : 0;
-   };
-
-   cl_emit(rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
-      init.use_auto_chained_tile_lists = true;
-      init.size_of_first_block_in_chained_tile_lists =
-         TILE_ALLOCATION_BLOCK_SIZE_64B;
-   }
-
-   for (int layer = base_layer; layer < base_layer + layer_count; layer++) {
-      emit_tlb_clear_layer_rcl(cmd_buffer,
-                               attachment_count,
-                               attachments,
-                               layer);
-   }
-
-   cl_emit(rcl, END_OF_RENDERING, end);
-}
-
-void
-v3dX(cmd_buffer_emit_tlb_clear)(struct v3dv_cmd_buffer *cmd_buffer,
-                                uint32_t attachment_count,
-                                const VkClearAttachment *attachments,
-                                uint32_t base_layer,
-                                uint32_t layer_count)
-{
-   struct v3dv_job *job =
-      v3dv_cmd_buffer_start_job(cmd_buffer, cmd_buffer->state.subpass_idx,
-                                V3DV_JOB_TYPE_GPU_CL);
-
-   if (!job)
-      return;
-
-   /* vkCmdClearAttachments runs inside a render pass */
-   job->is_subpass_continue = true;
-
-   emit_tlb_clear_job(cmd_buffer,
-                      attachment_count,
-                      attachments,
-                      base_layer, layer_count);
-
-   v3dv_cmd_buffer_subpass_resume(cmd_buffer, cmd_buffer->state.subpass_idx);
-}

src/broadcom/vulkan/v3dvx_private.h

@@ -170,13 +170,7 @@ void
 v3dX(pack_texture_shader_state_from_buffer_view)(struct v3dv_device *device,
                                                  struct v3dv_buffer_view *buffer_view);
 
-/* Used at v3dv_meta_clear */
-void
-v3dX(cmd_buffer_emit_tlb_clear)(struct v3dv_cmd_buffer *cmd_buffer,
-                                uint32_t attachment_count,
-                                const VkClearAttachment *attachments,
-                                uint32_t base_layer,
-                                uint32_t layer_count);
+/* Used at v3dv_meta_copy */
 
 uint32_t
 v3dX(zs_buffer_from_aspect_bits)(VkImageAspectFlags aspects);
@@ -184,8 +178,6 @@ v3dX(zs_buffer_from_aspect_bits)(VkImageAspectFlags aspects);
 uint8_t
 v3dX(get_internal_depth_type)(VkFormat format);
 
-
-/* Used at v3dv_meta_copy */
 struct framebuffer_data;
 
 void

src/compiler/glsl/linker.cpp

@@ -1200,7 +1200,7 @@ static bool
 interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
                                          bool validate_ssbo)
 {
-   int *InterfaceBlockStageIndex[MESA_SHADER_STAGES];
+   int *ifc_blk_stage_idx[MESA_SHADER_STAGES];
    struct gl_uniform_block *blks = NULL;
    unsigned *num_blks = validate_ssbo ? &prog->data->NumShaderStorageBlocks :
       &prog->data->NumUniformBlocks;
@@ -1221,9 +1221,10 @@ interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
       struct gl_linked_shader *sh = prog->_LinkedShaders[i];
 
-      InterfaceBlockStageIndex[i] = new int[max_num_buffer_blocks];
+      ifc_blk_stage_idx[i] =
+         (int *) malloc(sizeof(int) * max_num_buffer_blocks);
       for (unsigned int j = 0; j < max_num_buffer_blocks; j++)
-         InterfaceBlockStageIndex[i][j] = -1;
+         ifc_blk_stage_idx[i][j] = -1;
 
       if (sh == NULL)
          continue;
@@ -1247,7 +1248,7 @@ interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
                          "definitions\n", sh_blks[j]->Name);
 
             for (unsigned k = 0; k <= i; k++) {
-               delete[] InterfaceBlockStageIndex[k];
+               free(ifc_blk_stage_idx[k]);
             }
 
             /* Reset the block count. This will help avoid various segfaults
@@ -1258,7 +1259,7 @@ interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
             return false;
          }
 
-         InterfaceBlockStageIndex[i][index] = j;
+         ifc_blk_stage_idx[i][index] = j;
       }
    }
 
@@ -1267,7 +1268,7 @@ interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
     */
    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
       for (unsigned j = 0; j < *num_blks; j++) {
-         int stage_index = InterfaceBlockStageIndex[i][j];
+         int stage_index = ifc_blk_stage_idx[i][j];
 
          if (stage_index != -1) {
             struct gl_linked_shader *sh = prog->_LinkedShaders[i];
@@ -1283,7 +1284,7 @@ interstage_cross_validate_uniform_blocks(struct gl_shader_program *prog,
    }
 
    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-      delete[] InterfaceBlockStageIndex[i];
+      free(ifc_blk_stage_idx[i]);
    }
 
    if (validate_ssbo)

src/compiler/nir/nir_opt_gcm.c

@@ -604,6 +604,11 @@ opt_gcm_impl(nir_function_impl *impl, bool value_number)
    nir_metadata_require(impl, nir_metadata_block_index |
                               nir_metadata_dominance);
 
+   /* A previous pass may have left pass_flags dirty, so clear it all out. */
+   nir_foreach_block(block, impl)
+      nir_foreach_instr(instr, block)
+         instr->pass_flags = 0;
+
    struct gcm_state state;
 
    state.impl = impl;

src/egl/drivers/dri2/platform_wayland.c

@@ -311,6 +311,16 @@ dri2_wl_create_window_surface(_EGLDisplay *disp, _EGLConfig *conf,
    int visual_idx;
    const __DRIconfig *config;
 
+   if (!window) {
+      _eglError(EGL_BAD_NATIVE_WINDOW, "dri2_create_surface");
+      return NULL;
+   }
+
+   if (window->driver_private) {
+      _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
+      return NULL;
+   }
+
    dri2_surf = calloc(1, sizeof *dri2_surf);
    if (!dri2_surf) {
       _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
@@ -643,8 +653,9 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
    struct dri2_egl_display *dri2_dpy =
       dri2_egl_display(dri2_surf->base.Resource.Display);
 
-   if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
-       dri2_surf->base.Height != dri2_surf->wl_win->height) {
+   if (dri2_surf->wl_win &&
+       (dri2_surf->base.Width != dri2_surf->wl_win->width ||
+        dri2_surf->base.Height != dri2_surf->wl_win->height)) {
 
       dri2_surf->base.Width  = dri2_surf->wl_win->width;
       dri2_surf->base.Height = dri2_surf->wl_win->height;
@@ -652,8 +663,9 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
       dri2_surf->dy = dri2_surf->wl_win->dy;
    }
 
-   if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
-       dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
+   if (dri2_surf->wl_win &&
+       (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
+        dri2_surf->base.Height != dri2_surf->wl_win->attached_height)) {
       dri2_wl_release_buffers(dri2_surf);
    }
 
@@ -1033,6 +1045,9 @@ dri2_wl_swap_buffers_with_damage(_EGLDisplay *disp,
    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
    struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
 
+   if (!dri2_surf->wl_win)
+      return _eglError(EGL_BAD_NATIVE_WINDOW, "dri2_swap_buffers");
+
    while (dri2_surf->throttle_callback != NULL)
       if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
                                     dri2_surf->wl_queue) == -1)
@@ -1676,8 +1691,9 @@ swrast_update_buffers(struct dri2_egl_surface *dri2_surf)
    if (dri2_surf->back)
       return 0;
 
-   if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
-       dri2_surf->base.Height != dri2_surf->wl_win->height) {
+   if (dri2_surf->wl_win &&
+       (dri2_surf->base.Width != dri2_surf->wl_win->width ||
+        dri2_surf->base.Height != dri2_surf->wl_win->height)) {
 
       dri2_wl_release_buffers(dri2_surf);
 
@@ -1923,6 +1939,9 @@ dri2_wl_swrast_swap_buffers(_EGLDisplay *disp, _EGLSurface *draw)
    struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
    struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
 
+   if (!dri2_surf->wl_win)
+      return _eglError(EGL_BAD_NATIVE_WINDOW, "dri2_swap_buffers");
+
    dri2_dpy->core->swapBuffers(dri2_surf->dri_drawable);
    return EGL_TRUE;
 }

src/freedreno/common/freedreno_devices.py

@@ -109,7 +109,7 @@ class A6xxGPUInfo(GPUInfo):
 
         # 96 tile alignment seems correlated to 3 CCU
         if num_ccu == 3:
-            self.tile_align_h = 96
+            self.tile_align_w = 96
 
         self.a6xx = Struct()
         self.a6xx.magic = Struct()

src/gallium/auxiliary/draw/draw_pt.c

@@ -455,6 +455,7 @@ resolve_draw_info(const struct pipe_draw_info *raw_info,
  */
 static void
 draw_instances(struct draw_context *draw,
+               unsigned drawid_offset,
                const struct pipe_draw_info *info,
                const struct pipe_draw_start_count_bias *draws,
                unsigned num_draws)
@@ -473,6 +474,7 @@ draw_instances(struct draw_context *draw,
          draw->instance_id = 0xffffffff;
       }
 
+      draw->pt.user.drawid = drawid_offset;
       draw_new_instance(draw);
 
       if (info->primitive_restart) {
@@ -601,10 +603,10 @@ draw_vbo(struct draw_context *draw,
    if (use_info->view_mask) {
       u_foreach_bit(i, use_info->view_mask) {
          draw->pt.user.viewid = i;
-         draw_instances(draw, use_info, use_draws, num_draws);
+         draw_instances(draw, drawid_offset, use_info, use_draws, num_draws);
       }
    } else
-      draw_instances(draw, use_info, use_draws, num_draws);
+      draw_instances(draw, drawid_offset, use_info, use_draws, num_draws);
 
    /* If requested emit the pipeline statistics for this run */
    if (draw->collect_statistics) {

src/gallium/drivers/asahi/agx_state.c

@@ -828,11 +828,12 @@ agx_create_shader_state(struct pipe_context *pctx,
                         const struct pipe_shader_state *cso)
 {
    struct agx_uncompiled_shader *so = CALLOC_STRUCT(agx_uncompiled_shader);
-   so->base = *cso;
 
    if (!so)
       return NULL;
 
+   so->base = *cso;
+
    if (cso->type == PIPE_SHADER_IR_NIR) {
       so->nir = cso->ir.nir;
    } else {

src/gallium/drivers/crocus/crocus_program.c

@@ -1988,6 +1988,8 @@ update_last_vue_map(struct crocus_context *ice,
 
    if (changed_slots || (old_map && old_map->separate != vue_map->separate)) {
       ice->state.dirty |= CROCUS_DIRTY_GEN7_SBE;
+      if (devinfo->ver < 6)
+         ice->state.dirty |= CROCUS_DIRTY_GEN4_FF_GS_PROG;
       ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_UNCOMPILED_FS;
    }
 

src/gallium/drivers/iris/iris_bufmgr.c

@@ -1674,10 +1674,14 @@ gem_param(int fd, int name)
    return v;
 }
 
-static void
-iris_bufmgr_update_meminfo(struct iris_bufmgr *bufmgr,
-                           const struct drm_i915_query_memory_regions *meminfo)
+static bool
+iris_bufmgr_query_meminfo(struct iris_bufmgr *bufmgr)
 {
+   struct drm_i915_query_memory_regions *meminfo =
+      intel_i915_query_alloc(bufmgr->fd, DRM_I915_QUERY_MEMORY_REGIONS);
+   if (meminfo == NULL)
+      return false;
+
    for (int i = 0; i < meminfo->num_regions; i++) {
       const struct drm_i915_memory_region_info *mem = &meminfo->regions[i];
       switch (mem->region.memory_class) {
@@ -1692,35 +1696,8 @@ iris_bufmgr_update_meminfo(struct iris_bufmgr *bufmgr,
       default:
          break;
       }
-   };
-}
-
-static bool
-iris_bufmgr_query_meminfo(struct iris_bufmgr *bufmgr)
-{
-   struct drm_i915_query_item item = {
-      .query_id = DRM_I915_QUERY_MEMORY_REGIONS,
-   };
-
-   struct drm_i915_query query = {
-      .num_items = 1,
-      .items_ptr = (uintptr_t) &item,
-   };
-
-   if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_QUERY, &query))
-      return false;
-
-   struct drm_i915_query_memory_regions *meminfo = calloc(1, item.length);
-   item.data_ptr = (uintptr_t)meminfo;
-
-   if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_QUERY, &query) ||
-       item.length <= 0) {
-      free(meminfo);
-      return false;
    }
 
-   iris_bufmgr_update_meminfo(bufmgr, meminfo);
-
    free(meminfo);
 
    return true;

src/gallium/drivers/iris/iris_state.c

@@ -6878,7 +6878,8 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
    const struct brw_cs_dispatch_info dispatch =
       brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
 
-   if (stage_dirty & IRIS_STAGE_DIRTY_CS) {
+   if ((stage_dirty & IRIS_STAGE_DIRTY_CS) ||
+       cs_prog_data->local_size[0] == 0 /* Variable local group size */) {
       /* The MEDIA_VFE_STATE documentation for Gfx8+ says:
        *
        *   "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless

src/gallium/drivers/lima/lima_draw.c

@@ -195,6 +195,7 @@ enum lima_attrib_type {
    LIMA_ATTRIB_FLOAT = 0x000,
    LIMA_ATTRIB_I32   = 0x001,
    LIMA_ATTRIB_U32   = 0x002,
+   LIMA_ATTRIB_FP16  = 0x003,
    LIMA_ATTRIB_I16   = 0x004,
    LIMA_ATTRIB_U16   = 0x005,
    LIMA_ATTRIB_I8    = 0x006,
@@ -217,7 +218,10 @@ lima_pipe_format_to_attrib_type(enum pipe_format format)
 
    switch (c->type) {
    case UTIL_FORMAT_TYPE_FLOAT:
-      return LIMA_ATTRIB_FLOAT;
+      if (c->size == 16)
+         return LIMA_ATTRIB_FP16;
+      else
+         return LIMA_ATTRIB_FLOAT;
    case UTIL_FORMAT_TYPE_FIXED:
       return LIMA_ATTRIB_FIXED;
    case UTIL_FORMAT_TYPE_SIGNED:

src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

@@ -1292,7 +1292,7 @@ Converter::parseNIR()
       info->prop.cp.numThreads[0] = nir->info.workgroup_size[0];
       info->prop.cp.numThreads[1] = nir->info.workgroup_size[1];
       info->prop.cp.numThreads[2] = nir->info.workgroup_size[2];
-      info_out->bin.smemSize += nir->info.shared_size;
+      info_out->bin.smemSize = std::max(info_out->bin.smemSize, nir->info.shared_size);
       break;
    case Program::TYPE_FRAGMENT:
       info_out->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;

src/gallium/drivers/radeonsi/si_pipe.c

@@ -862,14 +862,16 @@ static void si_destroy_screen(struct pipe_screen *pscreen)
 
    simple_mtx_destroy(&sscreen->aux_context_lock);
 
-   struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
-   if (aux_log) {
-      sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
-      u_log_context_destroy(aux_log);
-      FREE(aux_log);
-   }
+   if (sscreen->aux_context) {
+       struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
+       if (aux_log) {
+          sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
+          u_log_context_destroy(aux_log);
+          FREE(aux_log);
+       }
 
-   sscreen->aux_context->destroy(sscreen->aux_context);
+       sscreen->aux_context->destroy(sscreen->aux_context);
+   }
 
    util_queue_destroy(&sscreen->shader_compiler_queue);
    util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);

src/gallium/drivers/radeonsi/si_state.c

@@ -2257,7 +2257,7 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format
       /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
        * so don't expose 16 samples there.
        */
-      const unsigned max_eqaa_samples = sscreen->info.max_render_backends == 1 ? 8 : 16;
+      const unsigned max_eqaa_samples = util_bitcount(sscreen->info.enabled_rb_mask) <= 1 ? 8 : 16;
       const unsigned max_samples = 8;
 
       /* MSAA support without framebuffer attachments. */

src/gallium/drivers/softpipe/sp_tex_sample.c

@@ -2385,15 +2385,6 @@ img_filter_2d_ewa(const struct sp_sampler_view *sp_sview,
    float weight_buffer[TGSI_QUAD_SIZE];
    int j;
 
-   /* For each quad, the du and dx values are the same and so the ellipse is
-    * also the same. Note that texel/image access can only be performed using
-    * a quad, i.e. it is not possible to get the pixel value for a single
-    * tex coord. In order to have a better performance, the access is buffered
-    * using the s_buffer/t_buffer and weight_buffer. Only when the buffer is
-    * full, then the pixel values are read from the image.
-    */
-   const float ddq = 2 * A;
-
    /* Scale ellipse formula to directly index the Filter Lookup Table.
     * i.e. scale so that F = WEIGHT_LUT_SIZE-1
     */
@@ -2403,6 +2394,15 @@ img_filter_2d_ewa(const struct sp_sampler_view *sp_sview,
    C *= formScale;
    /* F *= formScale; */ /* no need to scale F as we don't use it below here */
 
+   /* For each quad, the du and dx values are the same and so the ellipse is
+    * also the same. Note that texel/image access can only be performed using
+    * a quad, i.e. it is not possible to get the pixel value for a single
+    * tex coord. In order to have a better performance, the access is buffered
+    * using the s_buffer/t_buffer and weight_buffer. Only when the buffer is
+    * full, then the pixel values are read from the image.
+    */
+   const float ddq = 2 * A;
+
    args.level = level;
    args.offset = offset;
 

src/gallium/drivers/virgl/ci/gitlab-ci.yml

@@ -3,7 +3,6 @@
     - .test-gl
     - .virgl-rules
   variables:
-    LIBGL_ALWAYS_SOFTWARE: "true"
     GALLIUM_DRIVER: "virpipe"
 
 virgl-gles2-on-gl:
@@ -16,6 +15,7 @@ virgl-gles2-on-gl:
     LP_NUM_THREADS: 0
     DEQP_OPTIONS: "--deqp-log-images=disable"
     DEQP_EXPECTED_RENDERER: virgl
+    LIBGL_ALWAYS_SOFTWARE: "true"
   extends:
     - .deqp-test
     - .virgl-test
@@ -82,8 +82,9 @@ virgl-traces:
     PIGLIT_RESULTS: "virgl-replay"
     MESA_GLES_VERSION_OVERRIDE: "3.1"
     MESA_GLSL_VERSION_OVERRIDE: "310"
-    GALLIUM_DRIVER: "llvmpipe"
+    GALLIUM_DRIVER: "virgl"
     CROSVM_TEST_SCRIPT: "/install/piglit/run.sh"
+    CROSVM_GALLIUM_DRIVER: "llvmpipe"
   tags:
     - kvm
   script:

src/gallium/drivers/virgl/ci/traces-virgl.yml

@@ -17,11 +17,11 @@ traces:
   - path: gputest/furmark.trace
     expectations:
       - device: gl-virgl
-        checksum: 248ee9534a1f333b479e599646f56f63
+        checksum: 1d3233c101df0aa984b22ee2037f52b0
   - path: gputest/pixmark-piano.trace
     expectations:
       - device: gl-virgl
-        checksum: 3bb42312c7d7d694f7e186b480e16314
+        checksum: fcbef51c12090119897449c75be6aef7
   - path: gputest/triangle.trace
     expectations:
       - device: gl-virgl
@@ -33,7 +33,7 @@ traces:
   - path: 0ad/0ad.trace
     expectations:
       - device: gl-virgl
-        checksum: b244fb65c77f5cca2c49bb256874e132
+        checksum: 9a430898b88ae9d2faff8f1d1027bf36
   - path: glmark2/buffer-columns=200:interleave=false:update-dispersion=0.9:update-fraction=0.5:update-method=map.rdc
     expectations:
       - device: gl-virgl
@@ -180,7 +180,7 @@ traces:
   - path: gputest/plot3d.trace
     expectations:
       - device: gl-virgl
-        checksum: 09e49ca9a988fe86c8b26f2a73d5bc08
+        checksum: 6ff8d55ffa270a9682ddd7c934b93ec8
 # Crash
 #  - path: gputest/tessmark.trace
 #    expectations:
@@ -189,7 +189,7 @@ traces:
   - path: humus/AmbientAperture.trace
     expectations:
       - device: gl-virgl
-        checksum: ff490e36a763608e1ed3fa041216a378
+        checksum: 8097a71098d20aa029ca99868a8f5303
   - path: humus/CelShading.trace
     expectations:
       - device: gl-virgl
@@ -209,16 +209,17 @@ traces:
   - path: humus/VolumetricFogging2.trace
     expectations:
       - device: gl-virgl
-        checksum: a596785521a96162204ac266d5496c23
+        checksum: 02027b453508e7ba02c289c14167469a
 # Crash
 #  - path: itoral-gl-terrain-demo/demo.trace
 #    expectations:
 #      - device: gl-virgl
 #        checksum: 9571117bf4eab6fe29b12f6c3d42d865
+# The neverball foreground is actually missing
   - path: neverball/neverball.trace
     expectations:
       - device: gl-virgl
-        checksum: 6936cde5edab2b3fd02115ef36015cde
+        checksum: aa91b3f52d233ecded7d5979351b6859
 # Crash
 #  - path: pathfinder/canvas_moire.trace
 #    expectations:
@@ -237,7 +238,7 @@ traces:
   - path: supertuxkart/supertuxkart-mansion-egl-gles.trace
     expectations:
       - device: gl-virgl
-        checksum: 7e478a9cca2686531370e91ece6b3afc
+        checksum: 9ec60b51cf869b383fd5602e02f9b1ee
 # Sometimes crashes
 #  - path: xonotic/xonotic-keybench-high.trace
 #    expectations:
@@ -246,12 +247,12 @@ traces:
   - path: valve/counterstrike.trace
     expectations:
       - device: gl-virgl
-        checksum: c63da1fbaec101dba5224ca1f52ec429
-  - path: valve/counterstrike-source.trace
-    expectations:
-      - device: gl-virgl
-        checksum: 4c19f6060ff0fe0055678c48e1e77282
-# Piglit times-out when trying to run this one
+        checksum: e27507899c353b2ff0b8a033070ac2a5
+# Piglit times-out when trying to run these two
+#  - path: valve/counterstrike-source.trace
+#    expectations:
+#      - device: gl-virgl
+#        checksum: 4c19f6060ff0fe0055678c48e1e77282
 #  - path: valve/half-life-2.trace
 #    expectations:
 #      - device: gl-virgl

src/gallium/drivers/zink/zink_draw.c

@@ -422,7 +422,8 @@ zink_draw_vbo(struct pipe_context *pctx,
    if (!dindirect || !dindirect->buffer)
       ctx->drawid_broken = BITSET_TEST(ctx->gfx_stages[PIPE_SHADER_VERTEX]->nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID) &&
                            (drawid_offset != 0 ||
-                           ((!ctx->tc || !screen->info.have_EXT_multi_draw) && num_draws > 1));
+                           (!screen->info.have_EXT_multi_draw && num_draws > 1) ||
+                           (screen->info.have_EXT_multi_draw && num_draws > 1 && !dinfo->increment_draw_id));
    if (drawid_broken != ctx->drawid_broken)
       ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_VERTEX);
    ctx->gfx_pipeline_state.vertices_per_patch = dinfo->vertices_per_patch;

src/gallium/drivers/zink/zink_resource.c

@@ -921,13 +921,13 @@ zink_resource_get_handle(struct pipe_screen *pscreen,
                          struct winsys_handle *whandle,
                          unsigned usage)
 {
-   struct zink_resource *res = zink_resource(tex);
-   struct zink_screen *screen = zink_screen(pscreen);
-   //TODO: remove for wsi
-   struct zink_resource_object *obj = res->scanout_obj ? res->scanout_obj : res->obj;
-
    if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 #ifdef ZINK_USE_DMABUF
+      struct zink_resource *res = zink_resource(tex);
+      struct zink_screen *screen = zink_screen(pscreen);
+      //TODO: remove for wsi
+      struct zink_resource_object *obj = res->scanout_obj ? res->scanout_obj : res->obj;
+
       VkMemoryGetFdInfoKHR fd_info = {0};
       int fd;
       fd_info.sType = VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR;

src/gallium/frontends/lavapipe/lvp_cmd_buffer.c

@@ -522,7 +522,7 @@ VKAPI_ATTR void VKAPI_CALL lvp_CmdDrawMultiEXT(
    else {
       unsigned i = 0;
       vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride)
-         memcpy(cmd->u.draw.draws, draw, sizeof(struct pipe_draw_start_count_bias));
+         memcpy(&cmd->u.draw.draws[i], draw, sizeof(struct VkMultiDrawInfoEXT));
    }
 
    cmd_buf_queue(cmd_buffer, cmd);
@@ -808,7 +808,7 @@ VKAPI_ATTR void VKAPI_CALL lvp_CmdDrawMultiIndexedEXT(
    else {
       unsigned i = 0;
       vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride)
-         memcpy(cmd->u.draw_indexed.draws, draw, sizeof(struct pipe_draw_start_count_bias));
+         memcpy(&cmd->u.draw_indexed.draws[i], draw, sizeof(struct pipe_draw_start_count_bias));
    }
    /* only the first member is read if vertex_offset_changes is true */
    if (pVertexOffset)

src/gallium/frontends/lavapipe/lvp_execute.c

@@ -690,7 +690,7 @@ static void handle_graphics_pipeline(struct lvp_cmd_buffer_entry *cmd,
          unsigned location = vi->pVertexAttributeDescriptions[i].location;
          state->velem.velems[location].src_offset = vi->pVertexAttributeDescriptions[i].offset;
          state->velem.velems[location].vertex_buffer_index = vi->pVertexAttributeDescriptions[i].binding;
-         state->velem.velems[location].src_format = vk_format_to_pipe(vi->pVertexAttributeDescriptions[i].format);
+         state->velem.velems[location].src_format = lvp_vk_format_to_pipe_format(vi->pVertexAttributeDescriptions[i].format);
 
          switch (vi->pVertexBindingDescriptions[vi->pVertexAttributeDescriptions[i].binding].inputRate) {
          case VK_VERTEX_INPUT_RATE_VERTEX:
@@ -894,11 +894,11 @@ static void fill_sampler_view_stage(struct rendering_state *state,
 
    enum pipe_format pformat;
    if (iv->subresourceRange.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT)
-      pformat = vk_format_to_pipe(iv->format);
+      pformat = lvp_vk_format_to_pipe_format(iv->format);
    else if (iv->subresourceRange.aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT)
-      pformat = util_format_stencil_only(vk_format_to_pipe(iv->format));
+      pformat = util_format_stencil_only(lvp_vk_format_to_pipe_format(iv->format));
    else
-      pformat = vk_format_to_pipe(iv->format);
+      pformat = lvp_vk_format_to_pipe_format(iv->format);
    u_sampler_view_default_template(&templ,
                                    iv->image->bo,
                                    pformat);
@@ -998,11 +998,11 @@ static void fill_image_view_stage(struct rendering_state *state,
    idx += dyn_info->stage[stage].image_count;
    state->iv[p_stage][idx].resource = iv->image->bo;
    if (iv->subresourceRange.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT)
-      state->iv[p_stage][idx].format = vk_format_to_pipe(iv->format);
+      state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->format);
    else if (iv->subresourceRange.aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT)
-      state->iv[p_stage][idx].format = util_format_stencil_only(vk_format_to_pipe(iv->format));
+      state->iv[p_stage][idx].format = util_format_stencil_only(lvp_vk_format_to_pipe_format(iv->format));
    else
-      state->iv[p_stage][idx].format = vk_format_to_pipe(iv->format);
+      state->iv[p_stage][idx].format = lvp_vk_format_to_pipe_format(iv->format);
 
    if (iv->view_type == VK_IMAGE_VIEW_TYPE_3D) {
       state->iv[p_stage][idx].u.tex.first_layer = 0;
@@ -1255,7 +1255,7 @@ static struct pipe_surface *create_img_surface(struct rendering_state *state,
                                                int base_layer, int layer_count)
 {
    return create_img_surface_bo(state, &imgv->subresourceRange, imgv->image->bo,
-                                vk_format_to_pipe(format), width, height, base_layer, layer_count, 0);
+                                lvp_vk_format_to_pipe_format(format), width, height, base_layer, layer_count, 0);
 }
 
 static void add_img_view_surface(struct rendering_state *state,
@@ -1642,6 +1642,7 @@ static void handle_draw(struct lvp_cmd_buffer_entry *cmd,
    state->info.start_instance = cmd->u.draw.first_instance;
    state->info.instance_count = cmd->u.draw.instance_count;
    state->info.view_mask = subpass->view_mask;
+   state->info.increment_draw_id = true;
 
    state->pctx->draw_vbo(state->pctx, &state->info, 0, NULL, cmd->u.draw.draws, cmd->u.draw.draw_count);
 }
@@ -2207,6 +2208,7 @@ static void handle_draw_indexed(struct lvp_cmd_buffer_entry *cmd,
    state->info.start_instance = cmd->u.draw_indexed.first_instance;
    state->info.instance_count = cmd->u.draw_indexed.instance_count;
    state->info.view_mask = subpass->view_mask;
+   state->info.increment_draw_id = true;
 
    if (state->info.primitive_restart)
       state->info.restart_index = util_prim_restart_index_from_size(state->info.index_size);
@@ -2917,7 +2919,7 @@ static void handle_set_vertex_input(struct lvp_cmd_buffer_entry *cmd,
       unsigned location = attrs[i].location;
       state->velem.velems[location].src_offset = attrs[i].offset;
       state->velem.velems[location].vertex_buffer_index = attrs[i].binding;
-      state->velem.velems[location].src_format = vk_format_to_pipe(attrs[i].format);
+      state->velem.velems[location].src_format = lvp_vk_format_to_pipe_format(attrs[i].format);
       state->vb[attrs[i].binding].stride = binding->stride;
 
       switch (binding->inputRate) {

src/gallium/frontends/lavapipe/lvp_formats.c

@@ -26,150 +26,6 @@
 #include "util/u_math.h"
 #include "vk_util.h"
 
-#define COMMON_NAME(x) [VK_FORMAT_##x] = PIPE_FORMAT_##x
-
-#define FLOAT_NAME(x) [VK_FORMAT_##x##_SFLOAT] = PIPE_FORMAT_##x##_FLOAT
-
-static enum pipe_format format_to_vk_table[VK_FORMAT_ASTC_12x12_SRGB_BLOCK + 1] = {
-
-   COMMON_NAME(R8_UNORM),
-   COMMON_NAME(R8G8_UNORM),
-   COMMON_NAME(R8G8B8_UNORM),
-   COMMON_NAME(R8G8B8A8_UNORM),
-
-   COMMON_NAME(R8_SNORM),
-   COMMON_NAME(R8G8_SNORM),
-   COMMON_NAME(R8G8B8_SNORM),
-   COMMON_NAME(R8G8B8A8_SNORM),
-
-   //   COMMON_NAME(R8_SRGB),
-   COMMON_NAME(R8G8B8_SRGB),
-   COMMON_NAME(R8G8B8A8_SRGB),
-
-   COMMON_NAME(B8G8R8A8_UNORM),
-   COMMON_NAME(B8G8R8A8_SRGB),
-
-   COMMON_NAME(R8_UINT),
-   COMMON_NAME(R8G8_UINT),
-   COMMON_NAME(R8G8B8_UINT),
-   COMMON_NAME(R8G8B8A8_UINT),
-
-   COMMON_NAME(R16_UINT),
-   COMMON_NAME(R16G16_UINT),
-   COMMON_NAME(R16G16B16_UINT),
-   COMMON_NAME(R16G16B16A16_UINT),
-
-   COMMON_NAME(R32_UINT),
-   COMMON_NAME(R32G32_UINT),
-   COMMON_NAME(R32G32B32_UINT),
-   COMMON_NAME(R32G32B32A32_UINT),
-
-   COMMON_NAME(R8_SINT),
-   COMMON_NAME(R8G8_SINT),
-   COMMON_NAME(R8G8B8_SINT),
-   COMMON_NAME(R8G8B8A8_SINT),
-
-   COMMON_NAME(R16_SINT),
-   COMMON_NAME(R16G16_SINT),
-   COMMON_NAME(R16G16B16_SINT),
-   COMMON_NAME(R16G16B16A16_SINT),
-
-   COMMON_NAME(R32_SINT),
-   COMMON_NAME(R32G32_SINT),
-   COMMON_NAME(R32G32B32_SINT),
-   COMMON_NAME(R32G32B32A32_SINT),
-
-   COMMON_NAME(R16_UNORM),
-   COMMON_NAME(R16G16_UNORM),
-   COMMON_NAME(R16G16B16_UNORM),
-   COMMON_NAME(R16G16B16A16_UNORM),
-
-   COMMON_NAME(R16_USCALED),
-   COMMON_NAME(R16G16_USCALED),
-   COMMON_NAME(R16G16B16_USCALED),
-   COMMON_NAME(R16G16B16A16_USCALED),
-
-   COMMON_NAME(R16_SNORM),
-   COMMON_NAME(R16G16_SNORM),
-   COMMON_NAME(R16G16B16_SNORM),
-   COMMON_NAME(R16G16B16A16_SNORM),
-
-   COMMON_NAME(R16_SSCALED),
-   COMMON_NAME(R16G16_SSCALED),
-   COMMON_NAME(R16G16B16_SSCALED),
-   COMMON_NAME(R16G16B16A16_SSCALED),
-
-   FLOAT_NAME(R16),
-   FLOAT_NAME(R16G16),
-   FLOAT_NAME(R16G16B16),
-   FLOAT_NAME(R16G16B16A16),
-
-   FLOAT_NAME(R32),
-   FLOAT_NAME(R32G32),
-   FLOAT_NAME(R32G32B32),
-   FLOAT_NAME(R32G32B32A32),
-
-   COMMON_NAME(S8_UINT),
-   [VK_FORMAT_UNDEFINED] = PIPE_FORMAT_NONE,
-   [VK_FORMAT_R5G6B5_UNORM_PACK16] = PIPE_FORMAT_B5G6R5_UNORM,
-   [VK_FORMAT_A1R5G5B5_UNORM_PACK16] = PIPE_FORMAT_B5G5R5A1_UNORM,
-   [VK_FORMAT_B4G4R4A4_UNORM_PACK16] = PIPE_FORMAT_A4R4G4B4_UNORM,
-   [VK_FORMAT_D16_UNORM] = PIPE_FORMAT_Z16_UNORM,
-
-   [VK_FORMAT_A8B8G8R8_UNORM_PACK32] = PIPE_FORMAT_R8G8B8A8_UNORM,
-   [VK_FORMAT_A8B8G8R8_SNORM_PACK32] = PIPE_FORMAT_R8G8B8A8_SNORM,
-   [VK_FORMAT_A8B8G8R8_UINT_PACK32] = PIPE_FORMAT_R8G8B8A8_UINT,
-   [VK_FORMAT_A8B8G8R8_SINT_PACK32] = PIPE_FORMAT_R8G8B8A8_SINT,
-   [VK_FORMAT_A8B8G8R8_SRGB_PACK32] = PIPE_FORMAT_R8G8B8A8_SRGB,
-
-   [VK_FORMAT_A2B10G10R10_UNORM_PACK32] = PIPE_FORMAT_R10G10B10A2_UNORM,
-   [VK_FORMAT_A2B10G10R10_SNORM_PACK32] = PIPE_FORMAT_R10G10B10A2_SNORM,
-   [VK_FORMAT_A2R10G10B10_UNORM_PACK32] = PIPE_FORMAT_B10G10R10A2_UNORM,
-   [VK_FORMAT_A2R10G10B10_SNORM_PACK32] = PIPE_FORMAT_B10G10R10A2_SNORM,
-
-   [VK_FORMAT_A2B10G10R10_UINT_PACK32] = PIPE_FORMAT_R10G10B10A2_UINT,
-   [VK_FORMAT_A2R10G10B10_UINT_PACK32] = PIPE_FORMAT_B10G10R10A2_UINT,
-   [VK_FORMAT_A2B10G10R10_USCALED_PACK32] = PIPE_FORMAT_R10G10B10A2_USCALED,
-   [VK_FORMAT_A2B10G10R10_SSCALED_PACK32] = PIPE_FORMAT_R10G10B10A2_SSCALED,
-   [VK_FORMAT_A2R10G10B10_USCALED_PACK32] = PIPE_FORMAT_B10G10R10A2_USCALED,
-   [VK_FORMAT_A2R10G10B10_SSCALED_PACK32] = PIPE_FORMAT_B10G10R10A2_SSCALED,
-
-   [VK_FORMAT_B10G11R11_UFLOAT_PACK32] = PIPE_FORMAT_R11G11B10_FLOAT,
-   [VK_FORMAT_E5B9G9R9_UFLOAT_PACK32] = PIPE_FORMAT_R9G9B9E5_FLOAT,
-
-   [VK_FORMAT_X8_D24_UNORM_PACK32] = PIPE_FORMAT_Z24X8_UNORM,
-   [VK_FORMAT_D32_SFLOAT] = PIPE_FORMAT_Z32_FLOAT,
-   [VK_FORMAT_D24_UNORM_S8_UINT] = PIPE_FORMAT_Z24_UNORM_S8_UINT,
-   [VK_FORMAT_D32_SFLOAT_S8_UINT] = PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
-
-   [VK_FORMAT_BC1_RGB_UNORM_BLOCK] = PIPE_FORMAT_DXT1_RGB,
-   [VK_FORMAT_BC1_RGBA_UNORM_BLOCK] = PIPE_FORMAT_DXT1_RGBA,
-   [VK_FORMAT_BC2_UNORM_BLOCK] = PIPE_FORMAT_DXT3_RGBA,
-   [VK_FORMAT_BC3_UNORM_BLOCK] = PIPE_FORMAT_DXT5_RGBA,
-   [VK_FORMAT_BC4_UNORM_BLOCK] = PIPE_FORMAT_RGTC1_UNORM,
-   [VK_FORMAT_BC5_UNORM_BLOCK] = PIPE_FORMAT_RGTC2_UNORM,
-
-   [VK_FORMAT_BC1_RGB_SRGB_BLOCK] = PIPE_FORMAT_DXT1_SRGB,
-   [VK_FORMAT_BC1_RGBA_SRGB_BLOCK] = PIPE_FORMAT_DXT1_SRGBA,
-   [VK_FORMAT_BC2_SRGB_BLOCK] = PIPE_FORMAT_DXT3_SRGBA,
-   [VK_FORMAT_BC3_SRGB_BLOCK] = PIPE_FORMAT_DXT5_SRGBA,
-
-   [VK_FORMAT_BC4_SNORM_BLOCK] = PIPE_FORMAT_RGTC1_SNORM,
-   [VK_FORMAT_BC5_SNORM_BLOCK] = PIPE_FORMAT_RGTC2_SNORM,
-
-   [VK_FORMAT_BC6H_UFLOAT_BLOCK] = PIPE_FORMAT_BPTC_RGB_UFLOAT,
-   [VK_FORMAT_BC6H_SFLOAT_BLOCK] = PIPE_FORMAT_BPTC_RGB_FLOAT,
-   [VK_FORMAT_BC7_UNORM_BLOCK] = PIPE_FORMAT_BPTC_RGBA_UNORM,
-   [VK_FORMAT_BC7_SRGB_BLOCK] = PIPE_FORMAT_BPTC_SRGBA,
-};
-
-enum pipe_format vk_format_to_pipe(VkFormat format)
-{
-   if (format > VK_FORMAT_ASTC_12x12_SRGB_BLOCK)
-      return PIPE_FORMAT_NONE;
-   return format_to_vk_table[format];
-}
-
 static bool lvp_is_filter_minmax_format_supported(VkFormat format)
 {
    /* From the Vulkan spec 1.1.71:
@@ -204,7 +60,7 @@ lvp_physical_device_get_format_properties(struct lvp_physical_device *physical_d
                                           VkFormat format,
                                           VkFormatProperties *out_properties)
 {
-   enum pipe_format pformat = vk_format_to_pipe(format);
+   enum pipe_format pformat = lvp_vk_format_to_pipe_format(format);
    unsigned features = 0, buffer_features = 0;
    if (pformat == PIPE_FORMAT_NONE) {
      out_properties->linearTilingFeatures = 0;
@@ -322,7 +178,7 @@ static VkResult lvp_get_image_format_properties(struct lvp_physical_device *phys
    uint32_t maxMipLevels;
    uint32_t maxArraySize;
    VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT;
-   enum pipe_format pformat = vk_format_to_pipe(info->format);
+   enum pipe_format pformat = lvp_vk_format_to_pipe_format(info->format);
    lvp_physical_device_get_format_properties(physical_device, info->format,
                                              &format_props);
    if (info->tiling == VK_IMAGE_TILING_LINEAR) {

src/gallium/frontends/lavapipe/lvp_image.c

@@ -77,7 +77,7 @@ lvp_image_create(VkDevice _device,
       if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
          template.bind |= PIPE_BIND_SHADER_IMAGE;
 
-      template.format = vk_format_to_pipe(pCreateInfo->format);
+      template.format = lvp_vk_format_to_pipe_format(pCreateInfo->format);
       template.width0 = pCreateInfo->extent.width;
       template.height0 = pCreateInfo->extent.height;
       template.depth0 = pCreateInfo->extent.depth;
@@ -199,7 +199,7 @@ lvp_CreateImageView(VkDevice _device,
                        VK_OBJECT_TYPE_IMAGE_VIEW);
    view->view_type = pCreateInfo->viewType;
    view->format = pCreateInfo->format;
-   view->pformat = vk_format_to_pipe(pCreateInfo->format);
+   view->pformat = lvp_vk_format_to_pipe_format(pCreateInfo->format);
    view->components = pCreateInfo->components;
    view->subresourceRange = pCreateInfo->subresourceRange;
    view->image = image;
@@ -402,7 +402,7 @@ lvp_CreateBufferView(VkDevice _device,
                        VK_OBJECT_TYPE_BUFFER_VIEW);
    view->buffer = buffer;
    view->format = pCreateInfo->format;
-   view->pformat = vk_format_to_pipe(pCreateInfo->format);
+   view->pformat = lvp_vk_format_to_pipe_format(pCreateInfo->format);
    view->offset = pCreateInfo->offset;
    view->range = pCreateInfo->range;
    *pView = lvp_buffer_view_to_handle(view);

src/gallium/frontends/lavapipe/lvp_pass.c

@@ -186,7 +186,7 @@ VKAPI_ATTR VkResult VKAPI_CALL lvp_CreateRenderPass2(
       att->final_layout = pCreateInfo->pAttachments[i].finalLayout;
       att->first_subpass_idx = UINT32_MAX;
 
-      bool is_zs = util_format_is_depth_or_stencil(vk_format_to_pipe(att->format));
+      bool is_zs = util_format_is_depth_or_stencil(lvp_vk_format_to_pipe_format(att->format));
       pass->has_zs_attachment |= is_zs;
       pass->has_color_attachment |= !is_zs;
    }

src/gallium/frontends/lavapipe/lvp_private.h

@@ -55,6 +55,7 @@ typedef uint32_t xcb_window_t;
 #include "vk_physical_device.h"
 #include "vk_shader_module.h"
 #include "vk_util.h"
+#include "vk_format.h"
 
 #include "wsi_common.h"
 
@@ -1167,31 +1168,39 @@ VkResult lvp_execute_cmds(struct lvp_device *device,
 
 struct lvp_image *lvp_swapchain_get_image(VkSwapchainKHR swapchain,
 					  uint32_t index);
-enum pipe_format vk_format_to_pipe(VkFormat format);
 
-static inline VkImageAspectFlags
-vk_format_aspects(VkFormat format)
+static inline enum pipe_format
+lvp_vk_format_to_pipe_format(VkFormat format)
 {
-   switch (format) {
-   case VK_FORMAT_UNDEFINED:
-      return 0;
+   /* Some formats cause problems with CTS right now.*/
+   if (format == VK_FORMAT_R4G4B4A4_UNORM_PACK16 ||
+       format == VK_FORMAT_A4R4G4B4_UNORM_PACK16_EXT || /* VK_EXT_4444_formats */
+       format == VK_FORMAT_A4B4G4R4_UNORM_PACK16_EXT || /* VK_EXT_4444_formats */
+       format == VK_FORMAT_R5G5B5A1_UNORM_PACK16 ||
+       format == VK_FORMAT_R8_SRGB ||
+       format == VK_FORMAT_R8G8_SRGB ||
+       format == VK_FORMAT_R64G64B64A64_SFLOAT ||
+       format == VK_FORMAT_R64_SFLOAT ||
+       format == VK_FORMAT_R64G64_SFLOAT ||
+       format == VK_FORMAT_R64G64B64_SFLOAT ||
+       format == VK_FORMAT_A2R10G10B10_SINT_PACK32 ||
+       format == VK_FORMAT_A2B10G10R10_SINT_PACK32 ||
+       format == VK_FORMAT_G8B8G8R8_422_UNORM ||
+       format == VK_FORMAT_B8G8R8G8_422_UNORM ||
+       format == VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM ||
+       format == VK_FORMAT_G8_B8R8_2PLANE_420_UNORM ||
+       format == VK_FORMAT_G8_B8_R8_3PLANE_422_UNORM ||
+       format == VK_FORMAT_G8_B8R8_2PLANE_422_UNORM ||
+       format == VK_FORMAT_G8_B8_R8_3PLANE_444_UNORM ||
+       format == VK_FORMAT_G16_B16_R16_3PLANE_420_UNORM ||
+       format == VK_FORMAT_G16_B16R16_2PLANE_420_UNORM ||
+       format == VK_FORMAT_G16_B16_R16_3PLANE_422_UNORM ||
+       format == VK_FORMAT_G16_B16R16_2PLANE_422_UNORM ||
+       format == VK_FORMAT_G16_B16_R16_3PLANE_444_UNORM ||
+       format == VK_FORMAT_D16_UNORM_S8_UINT)
+      return PIPE_FORMAT_NONE;
 
-   case VK_FORMAT_S8_UINT:
-      return VK_IMAGE_ASPECT_STENCIL_BIT;
-
-   case VK_FORMAT_D16_UNORM_S8_UINT:
-   case VK_FORMAT_D24_UNORM_S8_UINT:
-   case VK_FORMAT_D32_SFLOAT_S8_UINT:
-      return VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
-
-   case VK_FORMAT_D16_UNORM:
-   case VK_FORMAT_X8_D24_UNORM_PACK32:
-   case VK_FORMAT_D32_SFLOAT:
-      return VK_IMAGE_ASPECT_DEPTH_BIT;
-
-   default:
-      return VK_IMAGE_ASPECT_COLOR_BIT;
-   }
+   return vk_format_to_pipe_format(format);
 }
 
 #ifdef __cplusplus

src/intel/common/intel_gem.h

@@ -24,9 +24,13 @@
 #ifndef INTEL_GEM_H
 #define INTEL_GEM_H
 
+#include "drm-uapi/i915_drm.h"
+
+#include <assert.h>
 #include <errno.h>
 #include <stdbool.h>
 #include <stdint.h>
+#include <stdlib.h>
 #include <unistd.h>
 #include <sys/ioctl.h>
 
@@ -72,6 +76,66 @@ intel_ioctl(int fd, unsigned long request, void *arg)
     return ret;
 }
 
+/**
+ * A wrapper around DRM_IOCTL_I915_QUERY
+ *
+ * Unfortunately, the error semantics of this ioctl are rather annoying so
+ * it's better to have a common helper.
+ */
+static inline int
+intel_i915_query(int fd, uint64_t query_id, void *buffer,
+                 int32_t *buffer_len)
+{
+   struct drm_i915_query_item item = {
+      .query_id = query_id,
+      .length = *buffer_len,
+      .data_ptr = (uintptr_t)buffer,
+   };
+
+   struct drm_i915_query args = {
+      .num_items = 1,
+      .flags = 0,
+      .items_ptr = (uintptr_t)&item,
+   };
+
+   int ret = intel_ioctl(fd, DRM_IOCTL_I915_QUERY, &args);
+   if (ret != 0)
+      return -errno;
+   else if (item.length < 0)
+      return item.length;
+
+   *buffer_len = item.length;
+   return 0;
+}
+
+/**
+ * Query for the given data, allocating as needed
+ *
+ * The caller is responsible for freeing the returned pointer.
+ */
+static inline void *
+intel_i915_query_alloc(int fd, uint64_t query_id)
+{
+   int32_t length = 0;
+   int ret = intel_i915_query(fd, query_id, NULL, &length);
+   if (ret < 0)
+      return NULL;
+
+   void *data = calloc(1, length);
+   assert(data != NULL); /* This shouldn't happen in practice */
+   if (data == NULL)
+      return NULL;
+
+   ret = intel_i915_query(fd, query_id, data, &length);
+   assert(ret == 0); /* We should have caught the error above */
+   if (ret < 0) {
+      free(data);
+      return NULL;
+   }
+
+   return data;
+}
+
 bool intel_gem_supports_syncobj_wait(int fd);
 
 #endif /* INTEL_GEM_H */

src/intel/vulkan/anv_device.c

@@ -328,13 +328,17 @@ get_device_extensions(const struct anv_physical_device *device,
    };
 }
 
-static void
-anv_track_meminfo(struct anv_physical_device *device,
-                  const struct drm_i915_query_memory_regions *mem_regions)
+static bool
+anv_get_query_meminfo(struct anv_physical_device *device, int fd)
 {
+   struct drm_i915_query_memory_regions *mem_regions =
+      intel_i915_query_alloc(fd, DRM_I915_QUERY_MEMORY_REGIONS);
+   if (mem_regions == NULL)
+      return false;
+
    for(int i = 0; i < mem_regions->num_regions; i++) {
       switch(mem_regions->regions[i].region.memory_class) {
-         case I915_MEMORY_CLASS_SYSTEM:
+      case I915_MEMORY_CLASS_SYSTEM:
          device->sys.region = mem_regions->regions[i].region;
          device->sys.size = mem_regions->regions[i].probed_size;
          break;
@@ -346,32 +350,6 @@ anv_track_meminfo(struct anv_physical_device *device,
          break;
       }
    }
-}
-
-static bool
-anv_get_query_meminfo(struct anv_physical_device *device, int fd)
-{
-   struct drm_i915_query_item item = {
-      .query_id = DRM_I915_QUERY_MEMORY_REGIONS
-   };
-
-   struct drm_i915_query query = {
-      .num_items = 1,
-      .items_ptr = (uintptr_t) &item,
-   };
-
-   if (drmIoctl(fd, DRM_IOCTL_I915_QUERY, &query))
-      return false;
-
-   struct drm_i915_query_memory_regions *mem_regions = calloc(1, item.length);
-   item.data_ptr = (uintptr_t) mem_regions;
-
-   if (drmIoctl(fd, DRM_IOCTL_I915_QUERY, &query) || item.length <= 0) {
-      free(mem_regions);
-      return false;
-   }
-
-   anv_track_meminfo(device, mem_regions);
 
    free(mem_regions);
    return true;
@@ -1550,7 +1528,9 @@ void anv_GetPhysicalDeviceFeatures2(
       case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FRAGMENT_SHADING_RATE_FEATURES_KHR: {
          VkPhysicalDeviceFragmentShadingRateFeaturesKHR *features =
             (VkPhysicalDeviceFragmentShadingRateFeaturesKHR *)ext;
+         features->attachmentFragmentShadingRate = false;
          features->pipelineFragmentShadingRate = true;
+         features->primitiveFragmentShadingRate = false;
          break;
       }
 
@@ -2344,12 +2324,12 @@ void anv_GetPhysicalDeviceProperties2(
          props->maxFragmentShadingRateAttachmentTexelSize = (VkExtent2D) { 0, 0 };
          props->maxFragmentShadingRateAttachmentTexelSizeAspectRatio = 0;
 
-         props->primitiveFragmentShadingRateWithMultipleViewports = pdevice->info.ver >= 12;
+         props->primitiveFragmentShadingRateWithMultipleViewports = false;
          props->layeredShadingRateAttachments = false;
-         props->fragmentShadingRateNonTrivialCombinerOps = true;
+         props->fragmentShadingRateNonTrivialCombinerOps = false;
          props->maxFragmentSize = (VkExtent2D) { 4, 4 };
          props->maxFragmentSizeAspectRatio = 4;
-         props->maxFragmentShadingRateCoverageSamples = 4 * 4;
+         props->maxFragmentShadingRateCoverageSamples = 4 * 4 * 16;
          props->maxFragmentShadingRateRasterizationSamples = VK_SAMPLE_COUNT_16_BIT;
          props->fragmentShadingRateWithShaderDepthStencilWrites = false;
          props->fragmentShadingRateWithSampleMask = true;
@@ -4954,7 +4934,11 @@ VkResult anv_GetPhysicalDeviceFragmentShadingRatesKHR(
 
    for (uint32_t x = 4; x >= 1; x /= 2) {
        for (uint32_t y = 4; y >= 1; y /= 2) {
-         append_rate(sample_counts, x, y);
+          /* For size {1, 1}, the sample count must be ~0 */
+          if (x == 1 && y == 1)
+             append_rate(~0, x, y);
+          else
+             append_rate(sample_counts, x, y);
       }
    }
 

src/intel/vulkan/anv_gem.c

@@ -770,45 +770,10 @@ anv_gem_syncobj_timeline_query(struct anv_device *device,
    return intel_ioctl(device->fd, DRM_IOCTL_SYNCOBJ_QUERY, &args);
 }
 
-int
-anv_i915_query(int fd, uint64_t query_id, void *buffer,
-               int32_t *buffer_len)
-{
-   struct drm_i915_query_item item = {
-      .query_id = query_id,
-      .length = *buffer_len,
-      .data_ptr = (uintptr_t)buffer,
-   };
-
-   struct drm_i915_query args = {
-      .num_items = 1,
-      .flags = 0,
-      .items_ptr = (uintptr_t)&item,
-   };
-
-   int ret = intel_ioctl(fd, DRM_IOCTL_I915_QUERY, &args);
-   *buffer_len = item.length;
-   return ret;
-}
-
 struct drm_i915_query_engine_info *
 anv_gem_get_engine_info(int fd)
 {
-   int32_t length = 0;
-   int ret = anv_i915_query(fd, DRM_I915_QUERY_ENGINE_INFO, NULL, &length);
-   if (ret == -1)
-      return NULL;
-
-   struct drm_i915_query_engine_info *info = calloc(1, length);
-   ret = anv_i915_query(fd, DRM_I915_QUERY_ENGINE_INFO, info, &length);
-   assert(ret == 0);
-
-   if (ret != 0) {
-      free(info);
-      return NULL;
-   }
-
-   return info;
+   return intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO);
 }
 
 int

src/mesa/main/draw.c

@@ -1074,7 +1074,7 @@ _mesa_draw_gallium_multimode_fallback(struct gl_context *ctx,
 {
    unsigned i, first;
  
-   /* Find consecutive draws where mode and base_vertex don't vary. */
+   /* Find consecutive draws where mode doesn't vary. */
    for (i = 0, first = 0; i <= num_draws; i++) {
       if (i == num_draws || mode[i] != mode[first]) {
          info->mode = mode[first];

src/mesa/main/uniform_query.cpp

@@ -1340,7 +1340,10 @@ _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
          ctx_flushed = true;
       }
    }
-   if (!ctx_flushed)
+   /* Return early if possible. Bindless samplers need to be processed
+    * because of the !sampler->bound codepath below.
+    */
+   if (!ctx_flushed && !(uni->type->is_sampler() && uni->is_bindless))
       return; /* no change in uniform values */
 
    /* If the uniform is a sampler, do the extra magic necessary to propagate

src/mesa/state_tracker/st_cb_bufferobjects.c

@@ -250,16 +250,20 @@ static enum pipe_resource_usage
 buffer_usage(GLenum target, GLboolean immutable,
              GLbitfield storageFlags, GLenum usage)
 {
+   /* "immutable" means that "storageFlags" was set by the user and "usage"
+    * was guessed by Mesa. Otherwise, "usage" was set by the user and
+    * storageFlags was guessed by Mesa.
+    *
+    * Therefore, use storageFlags with immutable, else use "usage".
+    */
    if (immutable) {
       /* BufferStorage */
-      if (storageFlags & GL_CLIENT_STORAGE_BIT) {
-         if (storageFlags & GL_MAP_READ_BIT)
-            return PIPE_USAGE_STAGING;
-         else
-            return PIPE_USAGE_STREAM;
-      } else {
+      if (storageFlags & GL_MAP_READ_BIT)
+         return PIPE_USAGE_STAGING;
+      else if (storageFlags & GL_CLIENT_STORAGE_BIT)
+         return PIPE_USAGE_STREAM;
+      else
          return PIPE_USAGE_DEFAULT;
-      }
    }
    else {
       /* These are often read by the CPU, so enable CPU caches. */

src/mesa/state_tracker/st_draw.c

@@ -205,7 +205,7 @@ st_draw_gallium_multimode(struct gl_context *ctx,
    unsigned i, first;
    struct cso_context *cso = st->cso_context;
 
-   /* Find consecutive draws where mode and base_vertex don't vary. */
+   /* Find consecutive draws where mode doesn't vary. */
    for (i = 0, first = 0; i <= num_draws; i++) {
       if (i == num_draws || mode[i] != mode[first]) {
          info->mode = mode[first];

src/util/00-mesa-defaults.conf

@@ -516,6 +516,7 @@ TODO: document the other workarounds.
         <!-- Adaptive sync denylist follows below: -->
         <application name="gnome-shell" executable="gnome-shell">
             <option name="adaptive_sync" value="false" />
+            <option name="v3d_nonmsaa_texture_size_limit" value="true" />
         </application>
         <application name="Desktop — Plasma" executable="plasmashell">
             <option name="adaptive_sync" value="false" />
@@ -564,6 +565,7 @@ TODO: document the other workarounds.
         </application>
         <application name="mutter" executable="mutter">
             <option name="adaptive_sync" value="false" />
+            <option name="v3d_nonmsaa_texture_size_limit" value="true" />
         </application>
         <application name="muffin" executable="muffin">
             <option name="adaptive_sync" value="false" />
@@ -842,5 +844,9 @@ TODO: document the other workarounds.
         <application name="Wolfenstein II" application_name_match="Wolfenstein II The New Colossus">
             <option name="radv_disable_dcc" value="true" />
         </application>
+
+        <application name="RDR2" application_name_match="Red Dead Redemption 2">
+            <option name="radv_report_apu_as_dgpu" value="true" />
+        </application>
     </device>
 </driconf>

src/util/driconf.h

@@ -513,4 +513,8 @@
    DRI_CONF_OPT_B(radv_disable_dcc, def, \
                   "Disable DCC for color images")
 
+#define DRI_CONF_RADV_REPORT_APU_AS_DGPU(def) \
+   DRI_CONF_OPT_B(radv_report_apu_as_dgpu, def, \
+                  "Report APUs as discrete GPUs instead of integrated GPUs")
+
 #endif

src/util/fossilize_db.c

@@ -334,7 +334,8 @@ foz_prepare(struct foz_db *foz_db, char *cache_path)
 void
 foz_destroy(struct foz_db *foz_db)
 {
-   fclose(foz_db->db_idx);
+   if (foz_db->db_idx)
+      fclose(foz_db->db_idx);
    for (unsigned i = 0; i < FOZ_MAX_DBS; i++) {
       if (foz_db->file[i])
          fclose(foz_db->file[i]);

src/vulkan/wsi/wsi_common_wayland.c

@@ -1218,8 +1218,10 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase *icd_surface,
    /* Mark a bunch of stuff as NULL.  This way we can just call
     * destroy_swapchain for cleanup.
     */
-   for (uint32_t i = 0; i < num_images; i++)
+   for (uint32_t i = 0; i < num_images; i++) {
       chain->images[i].buffer = NULL;
+      chain->images[i].data_ptr = NULL;
+   }
    chain->surface = NULL;
    chain->frame = NULL;