Add release notes for the 10.2.9 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

Android.mk

@@ -24,7 +24,7 @@
 # BOARD_GPU_DRIVERS should be defined.  The valid values are
 #
 #   classic drivers: i915 i965
-#   gallium drivers: swrast i915g ilo nouveau r300g r600g radeonsi vmwgfx
+#   gallium drivers: swrast freedreno i915g ilo nouveau r300g r600g radeonsi vmwgfx
 #
 # The main target is libGLES_mesa.  For each classic driver enabled, a DRI
 # module will also be built.  DRI modules will be loaded by libGLES_mesa.
@@ -42,7 +42,7 @@ DRM_TOP := external/drm
 DRM_GRALLOC_TOP := hardware/drm_gralloc
 
 classic_drivers := i915 i965
-gallium_drivers := swrast i915g ilo nouveau r300g r600g radeonsi vmwgfx
+gallium_drivers := swrast freedreno i915g ilo nouveau r300g r600g radeonsi vmwgfx
 
 MESA_GPU_DRIVERS := $(strip $(BOARD_GPU_DRIVERS))
 

Makefile.am

@@ -64,14 +64,13 @@ IGNORE_FILES = \
 
 parsers: configure
 	$(MAKE) -C src/glsl glsl_parser.cpp glsl_parser.h glsl_lexer.cpp glcpp/glcpp-lex.c glcpp/glcpp-parse.c glcpp/glcpp-parse.h
-	$(MAKE) -C src/mesa program/lex.yy.c program/program_parse.tab.c program/program_parse.tab.h
 
 # Everything for new a Mesa release:
 ARCHIVES = $(PACKAGE_NAME).tar.gz \
 	$(PACKAGE_NAME).tar.bz2 \
 	$(PACKAGE_NAME).zip
 
-tarballs: md5
+tarballs: checksums
 	rm -f ../$(PACKAGE_DIR) $(PACKAGE_NAME).tar
 
 manifest.txt: .git
@@ -98,9 +97,9 @@ $(PACKAGE_NAME).zip: parsers ../$(PACKAGE_DIR) manifest.txt
 	zip -q -@ $(PACKAGE_NAME).zip < $(PACKAGE_DIR)/manifest.txt ; \
 	mv $(PACKAGE_NAME).zip $(PACKAGE_DIR)
 
-md5: $(ARCHIVES)
-	@-md5sum $(PACKAGE_NAME).tar.gz
-	@-md5sum $(PACKAGE_NAME).tar.bz2
-	@-md5sum $(PACKAGE_NAME).zip
+checksums: $(ARCHIVES)
+	@-sha256sum $(PACKAGE_NAME).tar.gz
+	@-sha256sum $(PACKAGE_NAME).tar.bz2
+	@-sha256sum $(PACKAGE_NAME).zip
 
 .PHONY: tarballs md5

VERSION

@@ -1 +1 @@
-10.2.5
+10.2.9

bin/.cherry-ignore

@@ -16,3 +16,15 @@ e6967270c75a5b669152127bb7a746d55f4407a6 i965: Fix depth (array slices) computat
 e5adc560cc8544200faa3e04504202839626ab37
 cf1b5eee7f36af29d1d5caba3538ad4985e51f81
 
+# The patch depends on earlier ones that are not part of 10.2.
+b3121bfd413973f460e2cc9a9f852bdfa1265fcf mesa: guard better when building with sse4.1 optimisations
+
+# The PIPE_CAP is not in mesa 10.2 - breaks the build.
+72969e0efb7a5a011629c1001e81aa2329ede6b1 radeon/compute: Report a value for PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
+
+# No whitespace fixes for the stable branches.
+38fccc37c1fa57c1fd373e8d71621bb4aed31083 radeonsi/compute: Whitespace fixes
+
+# The commit relies of patches restructuring r600_resource, which never made
+# it in the 10.2 branch.
+a15088338ebe544efd90bfa7934cb99521488141 radeonsi/compute: Stop leaking the input buffer

bin/get-pick-list.sh

@@ -14,7 +14,7 @@ git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
 	sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
 
 # Grep for commits that were marked as a candidate for the stable tree.
-git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*mesa-stable\)' HEAD..origin/master |\
+git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*10\.2.*mesa-stable\)' HEAD..origin/master |\
 while read sha
 do
 	# Check to see whether the patch is on the ignore list.

configure.ac

@@ -494,10 +494,10 @@ AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
 AC_SUBST([DLOPEN_LIBS])
 
 dnl Check if that library also has dladdr
-save_LDFLAGS="$LDFLAGS"
-LDFLAGS="$LDFLAGS $DLOPEN_LIBS"
+save_LIBS="$LIBS"
+LIBS="$LIBS $DLOPEN_LIBS"
 AC_CHECK_FUNCS([dladdr])
-LDFLAGS="$save_LDFLAGS"
+LIBS="$save_LIBS"
 
 case "$host_os" in
 darwin*|mingw*)
@@ -1273,6 +1273,10 @@ if test "x$enable_gallium_gbm" = xyes; then
         AC_MSG_ERROR([gbm_gallium requires --enable-dri to build])
     fi
 
+    if test "x$enable_gallium_egl" != xyes; then
+        AC_MSG_ERROR([gbm_gallium is only used by egl_gallium])
+    fi
+
     GALLIUM_STATE_TRACKERS_DIRS="gbm $GALLIUM_STATE_TRACKERS_DIRS"
     GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS gbm"
     enable_gallium_loader=yes
@@ -1579,6 +1583,7 @@ strip_unwanted_llvm_flags() {
     # Use \> (marks the end of the word)
     echo `$1` | sed \
 	-e 's/-DNDEBUG\>//g' \
+	-e 's/-D_GNU_SOURCE\>//g' \
 	-e 's/-pedantic\>//g' \
 	-e 's/-Wcovered-switch-default\>//g' \
 	-e 's/-O.\>//g' \
@@ -1626,11 +1631,10 @@ if test "x$enable_gallium_llvm" = xyes; then
         AC_COMPUTE_INT([LLVM_VERSION_MINOR], [LLVM_VERSION_MINOR],
             [#include "${LLVM_INCLUDEDIR}/llvm/Config/llvm-config.h"])
 
-        dnl In LLVM 3.4.1 patch level was defined in config.h and not
-        dnl llvm-config.h
-        AC_COMPUTE_INT([LLVM_VERSION_PATCH], [LLVM_VERSION_PATCH],
-            [#include "${LLVM_INCLUDEDIR}/llvm/Config/config.h"],
-            LLVM_VERSION_PATCH=0) dnl Default if LLVM_VERSION_PATCH not found
+        LLVM_VERSION_PATCH=`echo $LLVM_VERSION | cut -d. -f3 | egrep -o '^[[0-9]]+'`
+        if test -z "$LLVM_VERSION_PATCH"; then
+            LLVM_VERSION_PATCH=0
+        fi
 
         if test -n "${LLVM_VERSION_MAJOR}"; then
             LLVM_VERSION_INT="${LLVM_VERSION_MAJOR}0${LLVM_VERSION_MINOR}"
@@ -1757,6 +1761,7 @@ gallium_check_st() {
 
 gallium_require_llvm() {
     if test "x$MESA_LLVM" = x0; then
+        case "$host" in *gnux32) return;; esac
         case "$host_cpu" in
         i*86|x86_64|amd64) AC_MSG_ERROR([LLVM is required to build $1 on x86 and x86_64]);;
         esac
@@ -1809,6 +1814,9 @@ if test -n "$with_gallium_drivers"; then
         case "x$driver" in
         xsvga)
             HAVE_GALLIUM_SVGA=yes
+            if test "x$have_libdrm" != xyes; then
+                AC_MSG_ERROR([Building svga requires libdrm >= $LIBDRM_REQUIRED])
+            fi
             GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS svga softpipe"
             gallium_require_drm_loader
             gallium_check_st "svga/drm" "dri-vmwgfx" ""

docs/relnotes/10.2.5.html

@@ -30,6 +30,9 @@ because compatibility contexts are not supported.
 
 <h2>SHA256 checksums</h2>
 <pre>
+b4459f0bf7f4a3c8fb78ece3c9d2eac3d0e5bf38cb470f2a72705e744bd0310d  MesaLib-10.2.5.tar.bz2
+7b4dd0cb683f8c7dc48a3e7a315742bed58ddcd7b756c462aca4177bd1acdc79  MesaLib-10.2.5.tar.gz
+6180565914fb238dd77ccdaff96b6155d9a6e1b3e981ebbf6a6851301b384fed  MesaLib-10.2.5.zip
 </pre>
 
 <h2>New features</h2>

docs/relnotes/10.2.6.html

@@ -0,0 +1,118 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.6 Release Notes / August 19, 2014</h1>
+
+<p>
+Mesa 10.2.6 is a bug fix release which fixes bugs found since the 10.2.5 release.
+</p>
+<p>
+Mesa 10.2.6 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+193314d2adba98e43697d726739ac46b4299aae324fa1821aa226890c28ac806  MesaLib-10.2.6.tar.bz2
+f7a45a5977b485eb95ac024205c584a0c112fe3951c2313c797579bb16a7a448  MesaLib-10.2.6.tar.gz
+6d086d6fcda8f317adfaaae40011decf2f2e2dc80819c4a7a77c76f73512e8d8  MesaLib-10.2.6.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=81450">Bug 81450</a> - [BDW]Piglit spec_glsl-1.30_execution_tex-miplevel-selection_textureGrad_1DArray cases intel_do_flush_locked failed</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Anuj Phogat (15):</p>
+<ul>
+  <li>mesa: Fix error condition for valid texture targets in glTexStorage* functions</li>
+  <li>mesa: Turn target_can_be_compressed() in to a utility function</li>
+  <li>mesa: Add error condition for using compressed internalformat in glTexStorage3D()</li>
+  <li>mesa: Fix condition for using compressed internalformat in glCompressedTexImage3D()</li>
+  <li>mesa: Add utility function _mesa_is_enum_format_snorm()</li>
+  <li>mesa: Don't allow snorm internal formats in glCopyTexImage*() in GLES3</li>
+  <li>mesa: Add a helper function _mesa_is_enum_format_unsized()</li>
+  <li>mesa: Add a gles3 error condition for sized internalformat in glCopyTexImage*()</li>
+  <li>mesa: Add gles3 error condition for GL_RGBA10_A2 buffer format in glCopyTexImage*()</li>
+  <li>mesa: Add utility function _mesa_is_enum_format_unorm()</li>
+  <li>mesa: Add gles3 condition for normalized internal formats in glCopyTexImage*()</li>
+  <li>mesa: Allow GL_TEXTURE_CUBE_MAP target with compressed internal formats</li>
+  <li>meta: Use _mesa_get_format_bits() to get the GL_RED_BITS</li>
+  <li>egl: Fix OpenGL ES version checks in _eglParseContextAttribList()</li>
+  <li>meta: Fix datatype computation in get_temp_image_type()</li>
+</ul>
+
+<p>Brian Paul (1):</p>
+<ul>
+  <li>mesa: fix assertion in _mesa_drawbuffers()</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+  <li>docs: Add sha256 sums to the 10.2.5 release notes</li>
+  <li>Update VERSION to 10.2.6</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+  <li>mesa/st: only convert AND(a, NOT(b)) into MAD when not using native integers</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+  <li>i965/miptree: Layout 1D Array as 2D Array with height of 1</li>
+</ul>
+
+<p>Maarten Lankhorst (1):</p>
+<ul>
+  <li>configure.ac: Do not require llvm on x32</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>st/mesa: fix blit-based partial TexSubImage for 1D arrays</li>
+  <li>radeon,r200: fix buffer validation after CS flush</li>
+  <li>radeonsi: fix a hang with instancing in Unigine Heaven/Valley on Hawaii</li>
+  <li>radeonsi: fix CMASK and HTILE allocation on Tahiti</li>
+</ul>
+
+<p>Pali Rohár (1):</p>
+<ul>
+  <li>configure: check for dladdr via AC_CHECK_FUNC/AC_CHECK_LIB</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: fix up out-of-bounds level when using conformant out-of-bound behavior</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.7.html

@@ -0,0 +1,211 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.7 Release Notes / September 06, 2014</h1>
+
+<p>
+Mesa 10.2.7 is a bug fix release which fixes bugs found since the 10.2.6 release.
+</p>
+<p>
+Mesa 10.2.7 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+cb67dfaabf88acba29aa2cf0dd58ee17b21ebf9594f8d1226c41794da8de3e9d  MesaLib-10.2.7.tar.gz
+27b958063a4c002071f14ed45c7d2a1ee52cd85e4ac8876e8a1c273495a7d43f  MesaLib-10.2.7.tar.bz2
+a2796a2d5bbbc2edd22857ecc267cba68dfe5d0296f5d84ba7510877b216cc40  MesaLib-10.2.7.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=36193">Bug 36193</a> - [i965] brw_eu_emit.c:182: validate_reg: Assertion `execsize &gt;= width' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66184">Bug 66184</a> - src/mesa/state_tracker/st_glsl_to_tgsi.cpp:3216:simplify_cmp: Assertion `inst-&gt;dst.index &lt; 4096' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=70441">Bug 70441</a> - [Gen4-5 clip] Piglit spec_OpenGL_1.1_polygon-offset hits (execsize &gt;= width) assertion</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=76188">Bug 76188</a> - EGL_EXT_image_dma_buf_import fd ownership is incorrect</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=76789">Bug 76789</a> - [radeonsi] si_descriptors.c requires -std=gnu99 or -fms-extensions</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82139">Bug 82139</a> - [r600g, bisected] multiple ubo piglit regressions</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82255">Bug 82255</a> - [VP2] Chroma planes are vertically stretched during VDPAU playback</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82671">Bug 82671</a> - [r600g-evergreen][compute]Empty kernel execution causes crash</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82709">Bug 82709</a> - OpenCL not working on radeon hainan</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82814">Bug 82814</a> - glDrawBuffers(0, NULL) segfaults in _mesa_drawbuffers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83079">Bug 83079</a> - [NVC0] Dota 2 (Linux native and Wine) crash with Nouveau Drivers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83355">Bug 83355</a> - FTBFS: src/mesa/program/program_lexer.l:122:64: error: unknown type name 'YYSTYPE'</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Adam Jackson (1):</p>
+<ul>
+  <li>radeonsi: Don't use anonymous struct trick in atom tracking</li>
+</ul>
+
+<p>Alex Deucher (2):</p>
+<ul>
+  <li>radeonsi: add new CIK pci ids</li>
+  <li>radeonsi: add new SI pci ids</li>
+</ul>
+
+<p>Andreas Boll (1):</p>
+<ul>
+  <li>winsys/radeon: fix nop packet padding for hawaii</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>i965: Bail on vec4 copy propagation for scratch writes with source modifiers</li>
+</ul>
+
+<p>Brian Paul (1):</p>
+<ul>
+  <li>mesa: fix NULL pointer deref bug in _mesa_drawbuffers()</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.2.6 release</li>
+  <li>Makefile: Switch from md5sums to sha256sums</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>i965: add missing parens in vec4 visitor</li>
+</ul>
+
+<p>Emil Velikov (17):</p>
+<ul>
+  <li>configure.ac: bail out if building gallium_gbm without gallium_egl</li>
+  <li>android: gallium/nouveau: fix include folders, link against libstlport</li>
+  <li>android: egl/main: fixup the nouveau build</li>
+  <li>automake: gallium/freedreno: drop spurious include dirs</li>
+  <li>android: gallium/freedreno: add preliminary build</li>
+  <li>android: egl/main: add/enable freedreno</li>
+  <li>android: gallium/auxiliary: drop log2/log2f redefitions</li>
+  <li>android: drop HAL_PIXEL_FORMAT_RGBA_{5551,4444}</li>
+  <li>android: glsl: the stlport over the limited Android STL</li>
+  <li>android: dri/i915: do not build an 'empty' driver</li>
+  <li>cherry-ignore: remove patch that lacking previous dependencies</li>
+  <li>cherry-ignore: PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE is not it 10.2</li>
+  <li>cherry-ignore: drop whitespace fix</li>
+  <li>cherry-ignore: reject a15088338eb</li>
+  <li>get-pick-list.sh: Require explicit "10.2" for nominating stable patches</li>
+  <li>mesa: fix make tarballs</li>
+  <li>Update VERSION to 10.2.7</li>
+</ul>
+
+<p>Ian Romanick (1):</p>
+<ul>
+  <li>mesa: Handle uninitialized textures like other textures in get_tex_level_parameter_image</li>
+</ul>
+
+<p>Ilia Mirkin (9):</p>
+<ul>
+  <li>nouveau: make sure to invalidate any vbo state as well</li>
+  <li>nouveau: don't keep stale pointer to free'd data</li>
+  <li>nvc0/ir: avoid infinite recursion when finding first uses of tex</li>
+  <li>nv50: zero out unbound samplers</li>
+  <li>nvc0: don't make 1d staging textures linear</li>
+  <li>nv50/ir: avoid creating instructions that can't be emitted</li>
+  <li>nv50: set the miptree address when clearing bo's in vp2 init</li>
+  <li>nv50: mt address may not be the underlying bo's start address</li>
+  <li>nv50: attach the buffer bo to the miptree structures</li>
+</ul>
+
+<p>Jan Vesely (1):</p>
+<ul>
+  <li>gallivm: Fix build with latest LLVM</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>mesa: Move declaration to top of block.</li>
+</ul>
+
+<p>Kenneth Graunke (3):</p>
+<ul>
+  <li>i965/vec4: Set NoMask for GS_OPCODE_SET_VERTEX_COUNT on Gen8+.</li>
+  <li>i965/vec4: Respect ir-&gt;force_writemask_all in Gen8 code generation.</li>
+  <li>i965/clip: Fix brw_clip_unfilled.c/compute_offset's assembly.</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>r600g: fix constant buffer fetches</li>
+  <li>radeonsi: save scissor state and sample mask for u_blitter</li>
+  <li>glsl_to_tgsi: allocate and enlarge arrays for temporaries on demand</li>
+</ul>
+
+<p>Paulo Sergio Travaglia (2):</p>
+<ul>
+  <li>android: gallium/radeon: attempt to fix the android build</li>
+  <li>android: egl/main: resolve radeon linking issues</li>
+</ul>
+
+<p>Pekka Paalanen (1):</p>
+<ul>
+  <li>egl_dri2: fix EXT_image_dma_buf_import fds</li>
+</ul>
+
+<p>Robert Bragg (1):</p>
+<ul>
+  <li>meta: save and restore swizzle for _GenerateMipmap</li>
+</ul>
+
+<p>Tom Stellard (7):</p>
+<ul>
+  <li>radeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE</li>
+  <li>radeonsi/compute: Update reference counts for buffers in si_set_global_binding()</li>
+  <li>radeonsi/compute: Call si_pm4_free_state() after emitting compute state</li>
+  <li>clover: Flush the command queue in clReleaseCommandQueue()</li>
+  <li>radeon: Add work-around for missing Hainan support in clang &lt; 3.6 v2</li>
+  <li>pipe-loader: Fix memory leak v2</li>
+  <li>r600g/compute: Don't initialize vertex_buffer_state masks to 0x2</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+  <li>gallivm: Fix build with LLVM &gt;= 3.6 r215967.</li>
+</ul>
+
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.8.html

@@ -0,0 +1,130 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.8 Release Notes / September 19, 2014</h1>
+
+<p>
+Mesa 10.2.8 is a bug fix release which fixes bugs found since the 10.2.7 release.
+</p>
+<p>
+Mesa 10.2.8 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+4c5a25ccaf1a9734bbd10d62a1420cc8fd35a1060ce679f2fc846769a25fbeec  MesaLib-10.2.8.tar.gz
+1ef9ad3f241788d454f2ff8c9d65b6849dfc31c8fe91f70fd2930b81c8af1398  MesaLib-10.2.8.tar.bz2
+d26218da3b44734b1d555267b4c63c48803c4c8b14d2bc53071be57014da37fa  MesaLib-10.2.8.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=77493">Bug 77493</a> - lp_test_arit fails with llvm &gt;= llvm-3.5svn r206094</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82539">Bug 82539</a> - vmw_screen_dri.lo In file included from vmw_screen_dri.c:41: vmwgfx_drm.h:32:17: error: drm.h: No such file or directory</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82882">Bug 82882</a> - [swrast] piglit glsl-fs-uniform-bool-1 regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83432">Bug 83432</a> - r600_query.c:269:r600_emit_query_end: Assertion `ctx-&gt;num_pipelinestat_queries &gt; 0' failed [Gallium HUD]</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83567">Bug 83567</a> - Mesa 10.2.6 does not compile with llvm 3.5</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83735">Bug 83735</a> - [mesa-10.2.x] broken with llvm-3.5 and old CPUs</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Aaron Watry (1):</p>
+<ul>
+  <li>gallivm: Fix build after LLVM commit 211259</li>
+</ul>
+
+<p>Christoph Bumiller (2):</p>
+<ul>
+  <li>nv50/ir/util: fix BitSet issues</li>
+  <li>nvc0/ir: clarify recursion fix to finding first tex uses</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.2.7 release</li>
+  <li>configure: bail out if building svga without libdrm</li>
+  <li>Update VERSION to 10.2.8</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+  <li>nv50/ir: avoid array overrun when checking for supported mods</li>
+  <li>nouveau: only enable the depth test if there actually is a depth buffer</li>
+  <li>nouveau: only enable stencil func if the visual has stencil bits</li>
+  <li>nouveau: change internal variables to avoid conflicts with macro args</li>
+</ul>
+
+<p>Jonathan Gray (1):</p>
+<ul>
+  <li>configure.ac: strip _GNU_SOURCE from llvm-config output</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>gallivm: Disable workaround for PR12833 on LLVM 3.2+.</li>
+</ul>
+
+<p>Maarten Lankhorst (4):</p>
+<ul>
+  <li>nouveau: re-allocate bo's on overflow</li>
+  <li>nouveau: fix MPEG4 hw decoding</li>
+  <li>nouveau: rework reference frame handling</li>
+  <li>nouveau: remove unneeded assert</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>r600g,radeonsi: make sure there's enough CS space before resuming queries</li>
+  <li>mesa: set UniformBooleanTrue = 1.0f by default</li>
+  <li>st/mesa: use 1.0f as boolean true on drivers without integer support</li>
+</ul>
+
+<p>Richard Sandiford (1):</p>
+<ul>
+  <li>gallivm: Fix uses of 2^24</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: set mcpu when initializing llvm execution engine</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+  <li>winsys/svga: Fix incorrect type usage in IOCTL v2</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.9.html

@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.9 Release Notes / October 12, 2014</h1>
+
+<p>
+Mesa 10.2.9 is a bug fix release which fixes bugs found since the 10.2.8 release.
+This is the final planned release for the 10.2 branch.
+</p>
+<p>
+Mesa 10.2.9 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79462">Bug 79462</a> - [NVC0/Codegen] Shader compilation falis in spill logic</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83570">Bug 83570</a> - Glyphy demo throws unhandled Integer division by zero exception</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Andreas Pokorny (2):</p>
+<ul>
+  <li>egl/drm: expose KHR_image_pixmap extension</li>
+  <li>i915: Fix black buffers when importing prime fds</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.2.8 release</li>
+  <li>Update VERSION to 10.2.9</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+  <li>nv50/ir: avoid deleting pseudo instructions too early</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>radeonsi: release GS rings at context destruction</li>
+  <li>radeonsi: properly destroy the GS copy shader and scratch_bo for compute</li>
+  <li>st/dri: remove GALLIUM_MSAA and __GL_FSAA_MODE environment variables</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>gallivm: fix idiv</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+  <li>st/xa: Fix regression in xa_yuv_planar_blit()</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>configure.ac: Compute LLVM_VERSION_PATCH using llvm-config</li>
+</ul>
+
+<p>rconde (1):</p>
+<ul>
+  <li>gallivm,tgsi: fix idiv by zero crash</li>
+</ul>
+
+</div>
+</body>
+</html>

include/pci_ids/radeonsi_pci_ids.h

@@ -38,6 +38,7 @@ CHIPSET(0x6828, VERDE_6828, VERDE)
 CHIPSET(0x6829, VERDE_6829, VERDE)
 CHIPSET(0x682A, VERDE_682A, VERDE)
 CHIPSET(0x682B, VERDE_682B, VERDE)
+CHIPSET(0x682C, VERDE_682C, VERDE)
 CHIPSET(0x682D, VERDE_682D, VERDE)
 CHIPSET(0x682F, VERDE_682F, VERDE)
 CHIPSET(0x6830, VERDE_6830, VERDE)
@@ -54,8 +55,11 @@ CHIPSET(0x6600, OLAND_6600, OLAND)
 CHIPSET(0x6601, OLAND_6601, OLAND)
 CHIPSET(0x6602, OLAND_6602, OLAND)
 CHIPSET(0x6603, OLAND_6603, OLAND)
+CHIPSET(0x6604, OLAND_6604, OLAND)
+CHIPSET(0x6605, OLAND_6605, OLAND)
 CHIPSET(0x6606, OLAND_6606, OLAND)
 CHIPSET(0x6607, OLAND_6607, OLAND)
+CHIPSET(0x6608, OLAND_6608, OLAND)
 CHIPSET(0x6610, OLAND_6610, OLAND)
 CHIPSET(0x6611, OLAND_6611, OLAND)
 CHIPSET(0x6613, OLAND_6613, OLAND)
@@ -73,6 +77,8 @@ CHIPSET(0x666F, HAINAN_666F, HAINAN)
 
 CHIPSET(0x6640, BONAIRE_6640, BONAIRE)
 CHIPSET(0x6641, BONAIRE_6641, BONAIRE)
+CHIPSET(0x6646, BONAIRE_6646, BONAIRE)
+CHIPSET(0x6647, BONAIRE_6647, BONAIRE)
 CHIPSET(0x6649, BONAIRE_6649, BONAIRE)
 CHIPSET(0x6650, BONAIRE_6650, BONAIRE)
 CHIPSET(0x6651, BONAIRE_6651, BONAIRE)
@@ -132,6 +138,7 @@ CHIPSET(0x1313, KAVERI_1313, KAVERI)
 CHIPSET(0x1315, KAVERI_1315, KAVERI)
 CHIPSET(0x1316, KAVERI_1316, KAVERI)
 CHIPSET(0x1317, KAVERI_1317, KAVERI)
+CHIPSET(0x1318, KAVERI_1318, KAVERI)
 CHIPSET(0x131B, KAVERI_131B, KAVERI)
 CHIPSET(0x131C, KAVERI_131C, KAVERI)
 CHIPSET(0x131D, KAVERI_131D, KAVERI)

src/egl/drivers/dri2/egl_dri2.c

@@ -1663,36 +1663,13 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
 /**
  * The spec says:
  *
- * "If eglCreateImageKHR is successful for a EGL_LINUX_DMA_BUF_EXT target,
- *  the EGL takes ownership of the file descriptor and is responsible for
- *  closing it, which it may do at any time while the EGLDisplay is
- *  initialized."
+ * "If eglCreateImageKHR is successful for a EGL_LINUX_DMA_BUF_EXT target, the
+ *  EGL will take a reference to the dma_buf(s) which it will release at any
+ *  time while the EGLDisplay is initialized. It is the responsibility of the
+ *  application to close the dma_buf file descriptors."
+ *
+ * Therefore we must never close or otherwise modify the file descriptors.
  */
-static void
-dri2_take_dma_buf_ownership(const int *fds, unsigned num_fds)
-{
-   int already_closed[num_fds];
-   unsigned num_closed = 0;
-   unsigned i, j;
-
-   for (i = 0; i < num_fds; ++i) {
-      /**
-       * The same file descriptor can be referenced multiple times in case more
-       * than one plane is found in the same buffer, just with a different
-       * offset.
-       */
-      for (j = 0; j < num_closed; ++j) {
-         if (already_closed[j] == fds[i])
-            break;
-      }
-
-      if (j == num_closed) {
-         close(fds[i]);
-         already_closed[num_closed++] = fds[i];
-      }
-   }
-}
-
 static _EGLImage *
 dri2_create_image_dma_buf(_EGLDisplay *disp, _EGLContext *ctx,
 			  EGLClientBuffer buffer, const EGLint *attr_list)
@@ -1755,8 +1732,6 @@ dri2_create_image_dma_buf(_EGLDisplay *disp, _EGLContext *ctx,
       return EGL_NO_IMAGE_KHR;
 
    res = dri2_create_image_from_dri(disp, dri_image);
-   if (res)
-      dri2_take_dma_buf_ownership(fds, num_fds);
 
    return res;
 }

src/egl/drivers/dri2/platform_android.c

@@ -54,8 +54,6 @@ get_format_bpp(int native)
       bpp = 3;
       break;
    case HAL_PIXEL_FORMAT_RGB_565:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       bpp = 2;
       break;
    default:
@@ -371,8 +369,6 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp, _EGLContext *ctx,
       format = __DRI_IMAGE_FORMAT_XBGR8888;
       break;
    case HAL_PIXEL_FORMAT_RGB_888:
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-   case HAL_PIXEL_FORMAT_RGBA_4444:
       /* unsupported */
    default:
       _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", buf->format);

src/egl/drivers/dri2/platform_drm.c

@@ -572,6 +572,7 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
    }
 
    disp->Extensions.EXT_buffer_age = EGL_TRUE;
+   disp->Extensions.KHR_image_pixmap = EGL_TRUE;
 
 #ifdef HAVE_WAYLAND_PLATFORM
    disp->Extensions.WL_bind_wayland_display = EGL_TRUE;

src/egl/main/Android.mk

@@ -95,6 +95,12 @@ gallium_DRIVERS :=
 # swrast
 gallium_DRIVERS += libmesa_pipe_softpipe libmesa_winsys_sw_android
 
+# freedreno
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+gallium_DRIVERS += libmesa_winsys_freedreno libmesa_pipe_freedreno
+LOCAL_SHARED_LIBRARIES += libdrm_freedreno
+endif
+
 # i915g
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_winsys_i915 libmesa_pipe_i915
@@ -109,28 +115,29 @@ endif
 
 # nouveau
 ifneq ($(filter nouveau, $(MESA_GPU_DRIVERS)),)
-gallium_DRIVERS += \
-	libmesa_winsys_nouveau \
-	libmesa_pipe_nvfx \
-	libmesa_pipe_nv50 \
-	libmesa_pipe_nvc0 \
-	libmesa_pipe_nouveau
+gallium_DRIVERS +=  libmesa_winsys_nouveau libmesa_pipe_nouveau
 LOCAL_SHARED_LIBRARIES += libdrm_nouveau
+LOCAL_SHARED_LIBRARIES += libstlport
 endif
 
 # r300g/r600g/radeonsi
 ifneq ($(filter r300g r600g radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_winsys_radeon
+LOCAL_SHARED_LIBRARIES += libdrm_radeon
 ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r300
-endif
+endif # r300g
+ifneq ($(filter r600g radeonsi, $(MESA_GPU_DRIVERS)),)
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_r600
-endif
+LOCAL_SHARED_LIBRARIES += libstlport
+endif # r600g
 ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 gallium_DRIVERS += libmesa_pipe_radeonsi
-endif
-endif
+endif # radeonsi
+gallium_DRIVERS += libmesa_pipe_radeon
+endif # r600g || radeonsi
+endif # r300g || r600g || radeonsi
 
 # vmwgfx
 ifneq ($(filter vmwgfx, $(MESA_GPU_DRIVERS)),)

src/egl/main/eglcontext.c

@@ -322,11 +322,14 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy,
          break;
 
       case 3:
-      default:
          /* Don't put additional version checks here.  We don't know that
           * there won't be versions > 3.0.
           */
          break;
+
+      default:
+         err = EGL_BAD_MATCH;
+         break;
       }
    }
 

src/gallium/Android.mk

@@ -34,6 +34,11 @@ SUBDIRS := \
 # swrast
 SUBDIRS += winsys/sw/android drivers/softpipe
 
+# freedreno
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+SUBDIRS += winsys/freedreno/drm drivers/freedreno
+endif
+
 # i915g
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += winsys/i915/drm drivers/i915
@@ -57,6 +62,8 @@ SUBDIRS += winsys/radeon/drm
 ifneq ($(filter r300g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/r300
 endif
+ifneq ($(filter r600g radeonsi, $(MESA_GPU_DRIVERS)),)
+SUBDIRS += drivers/radeon
 ifneq ($(filter r600g, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/r600
 endif
@@ -64,6 +71,7 @@ ifneq ($(filter radeonsi, $(MESA_GPU_DRIVERS)),)
 SUBDIRS += drivers/radeonsi
 endif
 endif
+endif
 
 # vmwgfx
 ifneq ($(filter vmwgfx, $(MESA_GPU_DRIVERS)),)

src/gallium/auxiliary/gallivm/lp_bld_arit.c

@@ -1852,7 +1852,7 @@ lp_build_trunc(struct lp_build_context *bld,
       const struct lp_type type = bld->type;
       struct lp_type inttype;
       struct lp_build_context intbld;
-      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 2^24);
+      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 1<<24);
       LLVMValueRef trunc, res, anosign, mask;
       LLVMTypeRef int_vec_type = bld->int_vec_type;
       LLVMTypeRef vec_type = bld->vec_type;
@@ -1907,7 +1907,7 @@ lp_build_round(struct lp_build_context *bld,
       const struct lp_type type = bld->type;
       struct lp_type inttype;
       struct lp_build_context intbld;
-      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 2^24);
+      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 1<<24);
       LLVMValueRef res, anosign, mask;
       LLVMTypeRef int_vec_type = bld->int_vec_type;
       LLVMTypeRef vec_type = bld->vec_type;
@@ -1960,7 +1960,7 @@ lp_build_floor(struct lp_build_context *bld,
       const struct lp_type type = bld->type;
       struct lp_type inttype;
       struct lp_build_context intbld;
-      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 2^24);
+      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 1<<24);
       LLVMValueRef trunc, res, anosign, mask;
       LLVMTypeRef int_vec_type = bld->int_vec_type;
       LLVMTypeRef vec_type = bld->vec_type;
@@ -2029,7 +2029,7 @@ lp_build_ceil(struct lp_build_context *bld,
       const struct lp_type type = bld->type;
       struct lp_type inttype;
       struct lp_build_context intbld;
-      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 2^24);
+      LLVMValueRef cmpval = lp_build_const_vec(bld->gallivm, type, 1<<24);
       LLVMValueRef trunc, res, anosign, mask, tmp;
       LLVMTypeRef int_vec_type = bld->int_vec_type;
       LLVMTypeRef vec_type = bld->vec_type;

src/gallium/auxiliary/gallivm/lp_bld_debug.cpp

@@ -34,6 +34,10 @@
 #include <llvm/Support/Format.h>
 #include <llvm/Support/MemoryObject.h>
 
+#if HAVE_LLVM >= 0x0306
+#include <llvm/Target/TargetSubtargetInfo.h>
+#endif
+
 #if HAVE_LLVM >= 0x0300
 #include <llvm/Support/TargetRegistry.h>
 #include <llvm/MC/MCSubtargetInfo.h>
@@ -57,7 +61,9 @@
 #include <llvm/MC/MCRegisterInfo.h>
 #endif /* HAVE_LLVM >= 0x0301 */
 
-#if HAVE_LLVM >= 0x0303
+#if HAVE_LLVM >= 0x0305
+#define OwningPtr std::unique_ptr
+#elif HAVE_LLVM >= 0x0303
 #include <llvm/ADT/OwningPtr.h>
 #endif
 
@@ -302,7 +308,11 @@ disassemble(const void* func, llvm::raw_ostream & Out)
    OwningPtr<TargetMachine> TM(T->createTargetMachine(Triple, ""));
 #endif
 
+#if HAVE_LLVM >= 0x0306
+   const TargetInstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
+#else
    const TargetInstrInfo *TII = TM->getInstrInfo();
+#endif
 
    /*
     * Wrap the data in a MemoryObject

src/gallium/auxiliary/gallivm/lp_bld_misc.cpp

@@ -73,6 +73,10 @@
 #include <llvm/Support/CBindingWrapping.h>
 #endif
 
+#if HAVE_LLVM >= 0x0305
+#include <llvm/Support/Host.h>
+#endif
+
 #include "pipe/p_config.h"
 #include "util/u_debug.h"
 #include "util/u_cpu_detect.h"
@@ -266,7 +270,11 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
    using namespace llvm;
 
    std::string Error;
+#if HAVE_LLVM >= 0x0306
+   EngineBuilder builder(std::unique_ptr<Module>(unwrap(M)));
+#else
    EngineBuilder builder(unwrap(M));
+#endif
 
    /**
     * LLVM 3.1+ haven't more "extern unsigned llvm::StackAlignmentOverride" and
@@ -305,8 +313,8 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
       /*
        * AVX feature is not automatically detected from CPUID by the X86 target
        * yet, because the old (yet default) JIT engine is not capable of
-       * emitting the opcodes.  But as we're using MCJIT here, it is safe to
-       * add set this attribute.
+       * emitting the opcodes. On newer llvm versions it is and at least some
+       * versions (tested with 3.3) will emit avx opcodes without this anyway.
        */
       MAttrs.push_back("+avx");
       if (util_cpu_caps.has_f16c) {
@@ -316,12 +324,30 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
    }
    builder.setJITMemoryManager(JITMemoryManager::CreateDefaultMemManager());
 
+#if HAVE_LLVM >= 0x0305
+   StringRef MCPU = llvm::sys::getHostCPUName();
+   /*
+    * The cpu bits are no longer set automatically, so need to set mcpu manually.
+    * Note that the MAttrs set above will be sort of ignored (since we should
+    * not set any which would not be set by specifying the cpu anyway).
+    * It ought to be safe though since getHostCPUName() should include bits
+    * not only from the cpu but environment as well (for instance if it's safe
+    * to use avx instructions which need OS support). According to
+    * http://llvm.org/bugs/show_bug.cgi?id=19429 however if I understand this
+    * right it may be necessary to specify older cpu (or disable mattrs) though
+    * when not using MCJIT so no instructions are generated which the old JIT
+    * can't handle. Not entirely sure if we really need to do anything yet.
+    */
+   builder.setMCPU(MCPU);
+#endif
+
    ExecutionEngine *JIT;
-#if 0
+
+#if HAVE_LLVM >= 0x0302
    JIT = builder.create();
 #else
    /*
-    * Workaround http://llvm.org/bugs/show_bug.cgi?id=12833
+    * Workaround http://llvm.org/PR12833
     */
    StringRef MArch = "";
    StringRef MCPU = "";

src/gallium/auxiliary/gallivm/lp_bld_sample.c

@@ -927,6 +927,7 @@ lp_build_nearest_mip_level(struct lp_build_sample_context *bld,
                                                                 bld->int_coord_bld.type,
                                                                 out);
       }
+      level = lp_build_andnot(&bld->int_coord_bld, level, *out_of_bounds);
       *level_out = level;
    }
    else {

src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c

@@ -1248,8 +1248,24 @@ idiv_emit_cpu(
    struct lp_build_tgsi_context * bld_base,
    struct lp_build_emit_data * emit_data)
 {
-   emit_data->output[emit_data->chan] = lp_build_div(&bld_base->int_bld,
-                                   emit_data->args[0], emit_data->args[1]);
+   LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+   LLVMValueRef div_mask = lp_build_cmp(&bld_base->uint_bld,
+                                        PIPE_FUNC_EQUAL, emit_data->args[1],
+                                        bld_base->uint_bld.zero);
+   /* We want to make sure that we never divide/mod by zero to not
+    * generate sigfpe. We don't want to crash just because the
+    * shader is doing something weird. */
+   LLVMValueRef divisor = LLVMBuildOr(builder,
+                                      div_mask,
+                                      emit_data->args[1], "");
+   LLVMValueRef result = lp_build_div(&bld_base->int_bld,
+                                      emit_data->args[0], divisor);
+   LLVMValueRef not_div_mask = LLVMBuildNot(builder,
+                                            div_mask,"");
+   /* idiv by zero doesn't have a guaranteed return value chose 0 for now. */
+   emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
+                                                     not_div_mask,
+                                                     result, "");
 }
 
 /* TGSI_OPCODE_INEG (CPU Only) */
@@ -1675,15 +1691,15 @@ udiv_emit_cpu(
    LLVMValueRef div_mask = lp_build_cmp(&bld_base->uint_bld,
                                         PIPE_FUNC_EQUAL, emit_data->args[1],
                                         bld_base->uint_bld.zero);
-   /* We want to make sure that we never divide/mod by zero to not 
-    * generate sigfpe. We don't want to crash just because the 
+   /* We want to make sure that we never divide/mod by zero to not
+    * generate sigfpe. We don't want to crash just because the
     * shader is doing something weird. */
    LLVMValueRef divisor = LLVMBuildOr(builder,
                                       div_mask,
                                       emit_data->args[1], "");
    LLVMValueRef result = lp_build_div(&bld_base->uint_bld,
                                       emit_data->args[0], divisor);
-   /* udiv by zero is guaranteed to return 0xffffffff */
+   /* udiv by zero is guaranteed to return 0xffffffff at least with d3d10 */
    emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
                                                     div_mask,
                                                     result, "");

src/gallium/auxiliary/pipe-loader/pipe_loader.h

@@ -66,7 +66,7 @@ struct pipe_loader_device {
       } pci;
    } u; /**< Discriminated by \a type */
 
-   const char *driver_name;
+   char *driver_name;
    const struct pipe_loader_ops *ops;
 };
 

src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c

@@ -256,6 +256,7 @@ pipe_loader_drm_release(struct pipe_loader_device **dev)
       util_dl_close(ddev->lib);
 
    close(ddev->fd);
+   FREE(ddev->base.driver_name);
    FREE(ddev);
    *dev = NULL;
 }

src/gallium/auxiliary/tgsi/tgsi_exec.c

@@ -3332,10 +3332,10 @@ micro_idiv(union tgsi_exec_channel *dst,
            const union tgsi_exec_channel *src0,
            const union tgsi_exec_channel *src1)
 {
-   dst->i[0] = src0->i[0] / src1->i[0];
-   dst->i[1] = src0->i[1] / src1->i[1];
-   dst->i[2] = src0->i[2] / src1->i[2];
-   dst->i[3] = src0->i[3] / src1->i[3];
+   dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
+   dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
+   dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
+   dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
 }
 
 static void

src/gallium/auxiliary/util/u_math.h

@@ -149,28 +149,6 @@ roundf(float x)
 #endif /* _MSC_VER */
 
 
-#ifdef PIPE_OS_ANDROID
-
-static INLINE
-double log2(double d)
-{
-   return log(d) * (1.0 / M_LN2);
-}
-
-/* workaround a conflict with main/imports.h */
-#ifdef log2f
-#undef log2f
-#endif
-
-static INLINE
-float log2f(float f)
-{
-   return logf(f) * (float) (1.0 / M_LN2);
-}
-
-#endif
-
-
 #if __STDC_VERSION__ < 199901L && (!defined(__cplusplus) || defined(_MSC_VER))
 static INLINE long int
 lrint(double d)

src/gallium/drivers/freedreno/Android.mk

@@ -0,0 +1,44 @@
+# Copyright (C) 2014 Emil Velikov <emil.l.velikov@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := \
+	$(C_SOURCES) \
+	$(a2xx_SOURCES) \
+	$(a3xx_SOURCES)
+
+LOCAL_CFLAGS := \
+	-Wno-packed-bitfield-compat
+
+LOCAL_C_INCLUDES := \
+	$(LOCAL_PATH)/ir3 \
+	$(TARGET_OUT_HEADERS)/libdrm \
+	$(TARGET_OUT_HEADERS)/freedreno
+
+LOCAL_MODULE := libmesa_pipe_freedreno
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

src/gallium/drivers/freedreno/Makefile.am

@@ -5,8 +5,6 @@ include $(top_srcdir)/src/gallium/Automake.inc
 
 AM_CFLAGS = \
 	-Wno-packed-bitfield-compat \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a3xx \
-	-I$(top_srcdir)/src/gallium/drivers/freedreno/a2xx \
 	$(GALLIUM_DRIVER_CFLAGS) \
 	$(FREEDRENO_CFLAGS)
 

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -50,8 +50,8 @@
 #include "freedreno_query.h"
 #include "freedreno_util.h"
 
-#include "fd2_screen.h"
-#include "fd3_screen.h"
+#include "a2xx/fd2_screen.h"
+#include "a3xx/fd3_screen.h"
 
 /* XXX this should go away */
 #include "state_tracker/drm_driver.h"

src/gallium/drivers/nouveau/Android.mk

@@ -28,18 +28,19 @@ include $(LOCAL_PATH)/Makefile.sources
 
 include $(CLEAR_VARS)
 
-LOCAL_SRC_FILES := $(C_SOURCES) \
+LOCAL_SRC_FILES := \
+	$(C_SOURCES) \
 	$(NV30_C_SOURCES) \
 	$(NV50_CODEGEN_SOURCES) \
 	$(NV50_C_SOURES) \
 	$(NVC0_CODEGEN_SOURCES) \
 	$(NVC0_C_SOURCES)
 
-LOCAL_C_INCLUDES := $(DRM_TOP) \
-	$(DRM_TOP)/include/drm \
-	$(DRM_TOP)/nouveau
+LOCAL_C_INCLUDES := \
+	$(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_nouveau
 
+include external/stlport/libstlport.mk
 include $(GALLIUM_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)

src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp

@@ -26,6 +26,7 @@
 #include "codegen/nv50_ir_target_nvc0.h"
 
 #include <limits>
+#include <tr1/unordered_set>
 
 namespace nv50_ir {
 
@@ -148,7 +149,8 @@ private:
    bool insertTextureBarriers(Function *);
    inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
    void findFirstUses(const Instruction *tex, const Instruction *def,
-                      std::list<TexUse>&);
+                      std::list<TexUse>&,
+                      std::tr1::unordered_set<const Instruction *>&);
    void findOverwritingDefs(const Instruction *tex, Instruction *insn,
                             const BasicBlock *term,
                             std::list<TexUse>&);
@@ -230,15 +232,29 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
 }
 
 void
-NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
-                                  const Instruction *insn,
-                                  std::list<TexUse> &uses)
+NVC0LegalizePostRA::findFirstUses(
+      const Instruction *texi,
+      const Instruction *insn,
+      std::list<TexUse> &uses,
+      std::tr1::unordered_set<const Instruction *>& visited)
 {
    for (int d = 0; insn->defExists(d); ++d) {
       Value *v = insn->getDef(d);
       for (Value::UseIterator u = v->uses.begin(); u != v->uses.end(); ++u) {
          Instruction *usei = (*u)->getInsn();
 
+         // NOTE: In case of a loop that overwrites a value but never uses
+         // it, it can happen that we have a cycle of uses that consists only
+         // of phis and no-op moves and will thus cause an infinite loop here
+         // since these are not considered actual uses.
+         // The most obvious (and perhaps the only) way to prevent this is to
+         // remember which instructions we've already visited.
+
+         if (visited.find(usei) != visited.end())
+            continue;
+
+         visited.insert(usei);
+
          if (usei->op == OP_PHI || usei->op == OP_UNION) {
             // need a barrier before WAW cases
             for (int s = 0; usei->srcExists(s); ++s) {
@@ -253,11 +269,11 @@ NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
              usei->op == OP_PHI ||
              usei->op == OP_UNION) {
             // these uses don't manifest in the machine code
-            findFirstUses(texi, usei, uses);
+            findFirstUses(texi, usei, uses, visited);
          } else
          if (usei->op == OP_MOV && usei->getDef(0)->equals(usei->getSrc(0)) &&
              usei->subOp != NV50_IR_SUBOP_MOV_FINAL) {
-            findFirstUses(texi, usei, uses);
+            findFirstUses(texi, usei, uses, visited);
          } else {
             addTexUse(uses, usei, insn);
          }
@@ -313,8 +329,10 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
    uses = new std::list<TexUse>[texes.size()];
    if (!uses)
       return false;
-   for (size_t i = 0; i < texes.size(); ++i)
-      findFirstUses(texes[i], texes[i], uses[i]);
+   for (size_t i = 0; i < texes.size(); ++i) {
+      std::tr1::unordered_set<const Instruction *> visited;
+      findFirstUses(texes[i], texes[i], uses[i], visited);
+   }
 
    // determine the barrier level at each use
    for (size_t i = 0; i < texes.size(); ++i) {

src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

@@ -560,6 +560,10 @@ ConstantFolding::expr(Instruction *i,
       ImmediateValue src0;
       if (i->src(0).getImmediate(src0))
          expr(i, src0, *i->getSrc(1)->asImm());
+      if (i->saturate && !prog->getTarget()->isSatSupported(i)) {
+         bld.setPosition(i, false);
+         i->setSrc(1, bld.loadImm(NULL, res.data.u32));
+      }
    } else {
       i->op = i->saturate ? OP_SAT : OP_MOV; /* SAT handled by unary() */
    }

src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp

@@ -25,6 +25,7 @@
 
 #include <stack>
 #include <limits>
+#include <tr1/unordered_set>
 
 namespace nv50_ir {
 
@@ -1544,6 +1545,11 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
       LValue *lval = it->first->asLValue();
       Symbol *mem = it->second ? it->second->asSym() : NULL;
 
+      // Keep track of which instructions to delete later. Deleting them
+      // inside the loop is unsafe since a single instruction may have
+      // multiple destinations that all need to be spilled (like OP_SPLIT).
+      std::tr1::unordered_set<Instruction *> to_del;
+
       for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
            ++d) {
          Value *slot = mem ?
@@ -1576,7 +1582,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
             d = lval->defs.erase(d);
             --d;
             if (slot->reg.file == FILE_MEMORY_LOCAL)
-               delete_Instruction(func->getProgram(), defi);
+               to_del.insert(defi);
             else
                defi->setDef(0, slot);
          } else {
@@ -1584,6 +1590,9 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
          }
       }
 
+      for (std::tr1::unordered_set<Instruction *>::const_iterator it = to_del.begin();
+           it != to_del.end(); ++it)
+         delete_Instruction(func->getProgram(), *it);
    }
 
    // TODO: We're not trying to reuse old slots in a potential next iteration.
@@ -1654,6 +1663,10 @@ RegAlloc::execFunc()
            ret && i <= func->loopNestingBound;
            sequence = func->cfg.nextSequence(), ++i)
          ret = buildLiveSets(BasicBlock::get(func->cfg.getRoot()));
+      // reset marker
+      for (ArrayList::Iterator bi = func->allBBlocks.iterator();
+           !bi.end(); bi.next())
+         BasicBlock::get(bi)->liveSet.marker = false;
       if (!ret)
          break;
       func->orderInstructions(this->insns);

src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp

@@ -448,7 +448,7 @@ TargetNV50::isModSupported(const Instruction *insn, int s, Modifier mod) const
          return false;
       }
    }
-   if (s > 3)
+   if (s >= 3)
       return false;
    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 }

src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

@@ -417,7 +417,7 @@ TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
          return false;
       }
    }
-   if (s > 3)
+   if (s >= 3)
       return false;
    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 }

src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp

@@ -254,7 +254,9 @@ bool BitSet::resize(unsigned int nBits)
       return false;
    }
    if (n > p)
-      memset(&data[4 * p + 4], 0, (n - p) * 4);
+      memset(&data[p], 0, (n - p) * 4);
+   if (nBits < size && (nBits % 32))
+      data[(nBits + 31) / 32 - 1] &= (1 << (nBits % 32)) - 1;
 
    size = nBits;
    return true;
@@ -274,8 +276,8 @@ bool BitSet::allocate(unsigned int nBits, bool zero)
    if (zero)
       memset(data, 0, (size + 7) / 8);
    else
-   if (nBits)
-      data[(size + 31) / 32 - 1] = 0; // clear unused bits (e.g. for popCount)
+   if (size % 32) // clear unused bits (e.g. for popCount)
+      data[(size + 31) / 32 - 1] &= (1 << (size % 32)) - 1;
 
    return data;
 }

src/gallium/drivers/nouveau/codegen/nv50_ir_util.h

@@ -484,6 +484,7 @@ public:
          FREE(data);
    }
 
+   // allocate will keep old data iff size is unchanged
    bool allocate(unsigned int nBits, bool zero);
    bool resize(unsigned int nBits); // keep old data, zero additional bits
 

src/gallium/drivers/nouveau/nouveau_vp3_video.h

@@ -39,6 +39,8 @@ struct nouveau_vp3_video_buffer {
 #define VP_OFFSET 0x200
 #define COMM_OFFSET 0x500
 
+#define NOUVEAU_VP3_BSP_RESERVED_SIZE 0x700
+
 #define NOUVEAU_VP3_DEBUG_FENCE 0
 
 #if NOUVEAU_VP3_DEBUG_FENCE

src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c

@@ -78,10 +78,10 @@ struct mpeg4_picparm_vp {
 	uint8_t top_field_first; // bool, written to vuc
 
 	uint8_t pad4[3]; // 59, 5a, 5b, contains garbage on blob
-	uint32_t pad5[0x10]; // 5c...9c non-inclusive, but WHY?
 
-	uint32_t intra[0x10]; // 9c
-	uint32_t non_intra[0x10]; // bc
+	uint32_t intra[0x10]; // 5c
+	uint32_t non_intra[0x10]; // 9c
+	uint32_t pad5[0x10]; // bc what does this do?
 	// udc..uff pad?
 };
 
@@ -196,11 +196,15 @@ nouveau_vp3_handle_references(struct nouveau_vp3_decoder *dec, struct nouveau_vp
    /* Try to find a real empty spot first, there should be one..
     */
    for (i = 0; i < dec->base.max_references + 1; ++i) {
-      if (dec->refs[i].last_used != seq) {
+      if (dec->refs[i].vidbuf == target) {
          empty_spot = i;
          break;
-      }
+      } else if (!dec->refs[i].last_used) {
+         empty_spot = i;
+      } else if (empty_spot == ~0U && dec->refs[i].last_used != seq)
+         empty_spot = i;
    }
+
    assert(empty_spot < dec->base.max_references+1);
    dec->refs[empty_spot].last_used = seq;
 //   debug_printf("Kicked %p to add %p to slot %i\n", dec->refs[empty_spot].vidbuf, target, empty_spot);
@@ -267,7 +271,6 @@ nouveau_vp3_fill_picparm_mpeg4_vp(struct nouveau_vp3_decoder *dec,
 {
    struct mpeg4_picparm_vp pic_vp_stub = {}, *pic_vp = &pic_vp_stub;
    uint32_t ring, ret = 0x01014; // !async_shutdown << 16 | watchdog << 12 | irq_record << 4 | unk;
-   assert(!(dec->base.width & 0xf));
    *is_ref = desc->vop_coding_type <= 1;
 
    pic_vp->width = dec->base.width;
@@ -463,14 +466,45 @@ void nouveau_vp3_vp_caps(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    case PIPE_VIDEO_FORMAT_MPEG12:
       *caps = nouveau_vp3_fill_picparm_mpeg12_vp(dec, desc.mpeg12, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
+      switch (desc.mpeg12->picture_structure) {
+      case PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_TOP:
+         dec->refs[target->valid_ref].decoded_top = 1;
+         break;
+      case PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_BOTTOM:
+         dec->refs[target->valid_ref].decoded_bottom = 1;
+         break;
+      default:
+         dec->refs[target->valid_ref].decoded_top = 1;
+         dec->refs[target->valid_ref].decoded_bottom = 1;
+         break;
+      }
       return;
    case PIPE_VIDEO_FORMAT_MPEG4:
       *caps = nouveau_vp3_fill_picparm_mpeg4_vp(dec, desc.mpeg4, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
+      // XXX: Correct?
+      if (!desc.mpeg4->interlaced) {
+         dec->refs[target->valid_ref].decoded_top = 1;
+         dec->refs[target->valid_ref].decoded_bottom = 1;
+      } else if (desc.mpeg4->top_field_first) {
+         if (!dec->refs[target->valid_ref].decoded_top)
+            dec->refs[target->valid_ref].decoded_top = 1;
+         else
+            dec->refs[target->valid_ref].decoded_bottom = 1;
+      } else {
+         if (!dec->refs[target->valid_ref].decoded_bottom)
+            dec->refs[target->valid_ref].decoded_bottom = 1;
+         else
+            dec->refs[target->valid_ref].decoded_top = 1;
+      }
       return;
    case PIPE_VIDEO_FORMAT_VC1: {
       *caps = nouveau_vp3_fill_picparm_vc1_vp(dec, desc.vc1, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
+      if (desc.vc1->frame_coding_mode == 3)
+         debug_printf("Field-Interlaced possibly incorrectly handled\n");
+      dec->refs[target->valid_ref].decoded_top = 1;
+      dec->refs[target->valid_ref].decoded_bottom = 1;
       return;
    }
    case PIPE_VIDEO_FORMAT_MPEG4_AVC: {

src/gallium/drivers/nouveau/nv50/nv50_state.c

@@ -585,9 +585,12 @@ nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
          nv50_screen_tsc_unlock(nv50->screen, old);
    }
    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
-   for (; i < nv50->num_samplers[s]; ++i)
-      if (nv50->samplers[s][i])
+   for (; i < nv50->num_samplers[s]; ++i) {
+      if (nv50->samplers[s][i]) {
          nv50_screen_tsc_unlock(nv50->screen, nv50->samplers[s][i]);
+         nv50->samplers[s][i] = NULL;
+      }
+   }
 
    nv50->num_samplers[s] = nr;
 

src/gallium/drivers/nouveau/nv50/nv50_state_validate.c

@@ -54,8 +54,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       assert(mt->layout_3d || !array_mode || array_size == 1);
 
       BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
-      PUSH_DATAh(push, bo->offset + sf->offset);
-      PUSH_DATA (push, bo->offset + sf->offset);
+      PUSH_DATAh(push, mt->base.address + sf->offset);
+      PUSH_DATA (push, mt->base.address + sf->offset);
       PUSH_DATA (push, nv50_format_table[sf->base.format].rt);
       if (likely(nouveau_bo_memtype(bo))) {
          PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
@@ -97,8 +97,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       int unk = mt->base.base.target == PIPE_TEXTURE_3D || sf->depth == 1;
 
       BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-      PUSH_DATAh(push, bo->offset + sf->offset);
-      PUSH_DATA (push, bo->offset + sf->offset);
+      PUSH_DATAh(push, mt->base.address + sf->offset);
+      PUSH_DATA (push, mt->base.address + sf->offset);
       PUSH_DATA (push, nv50_format_table[fb->zsbuf->format].rt);
       PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
       PUSH_DATA (push, mt->layer_stride >> 2);

src/gallium/drivers/nouveau/nv50/nv50_surface.c

@@ -114,8 +114,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       PUSH_DATA (push, mt->level[level].pitch);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, bo->offset + offset);
-      PUSH_DATA (push, bo->offset + offset);
+      PUSH_DATAh(push, mt->base.address + offset);
+      PUSH_DATA (push, mt->base.address + offset);
    } else {
       BEGIN_NV04(push, SUBC_2D(mthd), 5);
       PUSH_DATA (push, format);
@@ -126,8 +126,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, bo->offset + offset);
-      PUSH_DATA (push, bo->offset + offset);
+      PUSH_DATAh(push, mt->base.address + offset);
+      PUSH_DATA (push, mt->base.address + offset);
    }
 
 #if 0
@@ -299,8 +299,8 @@ nv50_clear_render_target(struct pipe_context *pipe,
    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
    PUSH_DATA (push, 1);
    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
-   PUSH_DATAh(push, bo->offset + sf->offset);
-   PUSH_DATA (push, bo->offset + sf->offset);
+   PUSH_DATAh(push, mt->base.address + sf->offset);
+   PUSH_DATA (push, mt->base.address + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);
@@ -381,8 +381,8 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
    nv50->scissors_dirty |= 1;
 
    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-   PUSH_DATAh(push, bo->offset + sf->offset);
-   PUSH_DATA (push, bo->offset + sf->offset);
+   PUSH_DATAh(push, mt->base.address + sf->offset);
+   PUSH_DATA (push, mt->base.address + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);

src/gallium/drivers/nouveau/nv50/nv50_transfer.c

@@ -24,6 +24,8 @@ nv50_m2mf_rect_setup(struct nv50_m2mf_rect *rect,
    rect->bo = mt->base.bo;
    rect->domain = mt->base.domain;
    rect->base = mt->level[l].offset;
+   if (mt->base.bo->offset != mt->base.address)
+      rect->base += mt->base.address - mt->base.bo->offset;
    rect->pitch = mt->level[l].pitch;
    if (util_format_is_plain(res->format)) {
       rect->width = w << mt->ms_x;

src/gallium/drivers/nouveau/nv50/nv84_video.c

@@ -482,12 +482,14 @@ nv84_create_decoder(struct pipe_context *context,
       mip.level[0].pitch = surf.width * 4;
       mip.base.domain = NOUVEAU_BO_VRAM;
       mip.base.bo = dec->mbring;
+      mip.base.address = dec->mbring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760);
       surf.offset = dec->vpring->size / 2 - 0x1000;
       surf.width = 1024;
       surf.height = 1;
       mip.level[0].pitch = surf.width * 4;
       mip.base.bo = dec->vpring;
+      mip.base.address = dec->vpring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
       surf.offset = dec->vpring->size - 0x1000;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
@@ -683,17 +685,14 @@ nv84_video_buffer_create(struct pipe_context *pipe,
                       bo_size, &cfg, &buffer->full))
       goto error;
 
-   mt0->base.bo = buffer->interlaced;
+   nouveau_bo_ref(buffer->interlaced, &mt0->base.bo);
    mt0->base.domain = NOUVEAU_BO_VRAM;
-   mt0->base.offset = 0;
-   mt0->base.address = buffer->interlaced->offset + mt0->base.offset;
-   nouveau_bo_ref(buffer->interlaced, &empty);
+   mt0->base.address = buffer->interlaced->offset;
 
-   mt1->base.bo = buffer->interlaced;
+   nouveau_bo_ref(buffer->interlaced, &mt1->base.bo);
    mt1->base.domain = NOUVEAU_BO_VRAM;
-   mt1->base.offset = mt0->layer_stride * 2;
-   mt1->base.address = buffer->interlaced->offset + mt1->base.offset;
-   nouveau_bo_ref(buffer->interlaced, &empty);
+   mt1->base.offset = mt0->total_size;
+   mt1->base.address = buffer->interlaced->offset + mt0->total_size;
 
    memset(&sv_templ, 0, sizeof(sv_templ));
    for (component = 0, i = 0; i < 2; ++i ) {

src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c

@@ -42,8 +42,8 @@ nv98_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    struct nouveau_pushbuf *push = dec->pushbuf[0];
    enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
    uint32_t bsp_addr, comm_addr, inter_addr;
-   uint32_t slice_size, bucket_size, ring_size;
-   uint32_t caps;
+   uint32_t slice_size, bucket_size, ring_size, bsp_size;
+   uint32_t caps, i;
    int ret;
    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
@@ -65,6 +65,41 @@ nv98_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    fence_extra = 4;
 #endif
 
+   bsp_size = NOUVEAU_VP3_BSP_RESERVED_SIZE;
+   for (i = 0; i < num_buffers; i++)
+      bsp_size += num_bytes[i];
+   bsp_size += 256; /* the 4 end markers */
+
+   if (!bsp_bo || bsp_size > bsp_bo->size) {
+      struct nouveau_bo *tmp_bo = NULL;
+
+      /* round up to the nearest mb */
+      bsp_size += (1 << 20) - 1;
+      bsp_size &= ~((1 << 20) - 1);
+
+      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_size, NULL, &tmp_bo);
+      if (ret) {
+         debug_printf("reallocating bsp %u -> %u failed with %i\n",
+                      bsp_bo ? (unsigned)bsp_bo->size : 0, bsp_size, ret);
+         return -1;
+      }
+      nouveau_bo_ref(NULL, &bsp_bo);
+      bo_refs[0].bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
+   }
+
+   if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
+      struct nouveau_bo *tmp_bo = NULL;
+
+      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, NULL, &tmp_bo);
+      if (ret) {
+         debug_printf("reallocating inter %u -> %u failed with %i\n",
+                      inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
+         return -1;
+      }
+      nouveau_bo_ref(NULL, &inter_bo);
+      bo_refs[1].bo = dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
+   }
+
    ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
    if (ret) {
       debug_printf("map failed: %i %s\n", ret, strerror(-ret));

src/gallium/drivers/nouveau/nv50/nv98_video_vp.c

@@ -59,7 +59,6 @@ static void dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32
 static void
 nv98_decoder_kick_ref(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target)
 {
-   dec->refs[target->valid_ref].vidbuf = NULL;
    dec->refs[target->valid_ref].last_used = 0;
 //   debug_printf("Unreffed %p\n", target);
 }

src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c

@@ -261,7 +261,6 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
 
    if (pt->usage == PIPE_USAGE_STAGING) {
       switch (pt->target) {
-      case PIPE_TEXTURE_1D:
       case PIPE_TEXTURE_2D:
       case PIPE_TEXTURE_RECT:
          if (pt->last_level == 0 &&

src/gallium/drivers/nouveau/nvc0/nvc0_video.c

@@ -173,16 +173,12 @@ nvc0_create_decoder(struct pipe_context *context,
       ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
                            0x100, 4 << 20, &cfg, &dec->inter_bo[0]);
    if (!ret) {
-      if (!kepler)
-         nouveau_bo_ref(dec->inter_bo[0], &dec->inter_bo[1]);
-      else
-         ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
-                              0x100, dec->inter_bo[0]->size, &cfg,
-                              &dec->inter_bo[1]);
+      ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
+                           0x100, dec->inter_bo[0]->size, &cfg,
+                           &dec->inter_bo[1]);
    }
    if (ret)
       goto fail;
-
    switch (u_reduce_video_profile(templ->profile)) {
    case PIPE_VIDEO_FORMAT_MPEG12: {
       codec = 1;

src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c

@@ -42,8 +42,8 @@ nvc0_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    struct nouveau_pushbuf *push = dec->pushbuf[0];
    enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
    uint32_t bsp_addr, comm_addr, inter_addr;
-   uint32_t slice_size, bucket_size, ring_size;
-   uint32_t caps;
+   uint32_t slice_size, bucket_size, ring_size, bsp_size;
+   uint32_t caps, i;
    int ret;
    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
@@ -65,6 +65,49 @@ nvc0_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    fence_extra = 4;
 #endif
 
+   bsp_size = NOUVEAU_VP3_BSP_RESERVED_SIZE;
+   for (i = 0; i < num_buffers; i++)
+      bsp_size += num_bytes[i];
+   bsp_size += 256; /* the 4 end markers */
+
+   if (!bsp_bo || bsp_size > bsp_bo->size) {
+      union nouveau_bo_config cfg;
+      struct nouveau_bo *tmp_bo = NULL;
+
+      cfg.nvc0.tile_mode = 0x10;
+      cfg.nvc0.memtype = 0xfe;
+
+      /* round up to the nearest mb */
+      bsp_size += (1 << 20) - 1;
+      bsp_size &= ~((1 << 20) - 1);
+
+      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_size, &cfg, &tmp_bo);
+      if (ret) {
+         debug_printf("reallocating bsp %u -> %u failed with %i\n",
+                      bsp_bo ? (unsigned)bsp_bo->size : 0, bsp_size, ret);
+         return -1;
+      }
+      nouveau_bo_ref(NULL, &bsp_bo);
+      bo_refs[0].bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
+   }
+
+   if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
+      union nouveau_bo_config cfg;
+      struct nouveau_bo *tmp_bo = NULL;
+
+      cfg.nvc0.tile_mode = 0x10;
+      cfg.nvc0.memtype = 0xfe;
+
+      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, &cfg, &tmp_bo);
+      if (ret) {
+         debug_printf("reallocating inter %u -> %u failed with %i\n",
+                      inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
+         return -1;
+      }
+      nouveau_bo_ref(NULL, &inter_bo);
+      bo_refs[1].bo = dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
+   }
+
    ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
    if (ret) {
       debug_printf("map failed: %i %s\n", ret, strerror(-ret));

src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c

@@ -59,7 +59,6 @@ static void dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32
 static void
 nvc0_decoder_kick_ref(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target)
 {
-   dec->refs[target->valid_ref].vidbuf = NULL;
    dec->refs[target->valid_ref].last_used = 0;
 //   debug_printf("Unreffed %p\n", target);
 }

src/gallium/drivers/r300/Android.mk

@@ -34,8 +34,7 @@ LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/glsl \
 	$(MESA_TOP)/src/mesa \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm
+	$(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_r300
 

src/gallium/drivers/r600/Android.mk

@@ -30,7 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES) $(CXX_SOURCES)
 
-LOCAL_C_INCLUDES := $(DRM_TOP)
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_r600
 

src/gallium/drivers/r600/evergreen_compute.c

@@ -881,9 +881,6 @@ void evergreen_init_compute_state_functions(struct r600_context *ctx)
 	ctx->b.b.set_global_binding = evergreen_set_global_binding;
 	ctx->b.b.launch_grid = evergreen_launch_grid;
 
-	/* We always use at least one vertex buffer for parameters (id = 1)*/
-	ctx->cs_vertex_buffer_state.enabled_mask =
-	ctx->cs_vertex_buffer_state.dirty_mask = 0x2;
 }
 
 struct pipe_resource *r600_compute_global_buffer_create(

src/gallium/drivers/r600/r600_shader.c

@@ -997,6 +997,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx)
 				alu.src[0].sel = ctx->src[i].sel;
 				alu.src[0].chan = k;
 				alu.src[0].rel = ctx->src[i].rel;
+				alu.src[0].kc_bank = ctx->src[i].kc_bank;
 				alu.dst.sel = treg;
 				alu.dst.chan = k;
 				alu.dst.write = 1;

src/gallium/drivers/radeon/Android.mk

@@ -0,0 +1,38 @@
+# Mesa 3-D graphics library
+#
+# Copyright (C) 2011 Chia-I Wu <olvaffe@gmail.com>
+# Copyright (C) 2011 LunarG Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := $(C_SOURCES)
+
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
+
+LOCAL_MODULE := libmesa_pipe_radeon
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

src/gallium/drivers/radeon/r600_pipe_common.c

@@ -437,7 +437,20 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	//TODO: select these params by asic
 	switch (param) {
 	case PIPE_COMPUTE_CAP_IR_TARGET: {
-		const char *gpu = r600_get_llvm_processor_name(rscreen->family);
+		const char *gpu;
+		switch(rscreen->family) {
+		/* Clang < 3.6 is missing Hainan in its list of
+		 * GPUs, so we need to use the name of a similar GPU.
+		 */
+#if HAVE_LLVM < 0x0306
+		case CHIP_HAINAN:
+			gpu = "oland";
+			break;
+#endif
+		default:
+			gpu = r600_get_llvm_processor_name(rscreen->family);
+			break;
+		}
 		if (ret) {
 			sprintf(ret, "%s-r600--", gpu);
 		}
@@ -478,13 +491,21 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 		if (ret) {
 			uint64_t *max_global_size = ret;
-			/* XXX: This is what the proprietary driver reports, we
-			 * may want to use a different value. */
-			/* XXX: Not sure what to put here for SI. */
-			if (rscreen->chip_class >= SI)
-				*max_global_size = 2000000000;
-			else
-				*max_global_size = 201326592;
+			uint64_t max_mem_alloc_size;
+
+			r600_get_compute_param(screen,
+				PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
+				&max_mem_alloc_size);
+
+			/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
+			 * 1/4 of the MAX_GLOBAL_SIZE.  Since the
+			 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
+			 * make sure we never report more than
+			 * 4 * MAX_MEM_ALLOC_SIZE.
+			 */
+			*max_global_size = MIN2(4 * max_mem_alloc_size,
+				rscreen->info.gart_size +
+				rscreen->info.vram_size);
 		}
 		return sizeof(uint64_t);
 
@@ -508,13 +529,11 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 		if (ret) {
 			uint64_t max_global_size;
 			uint64_t *max_mem_alloc_size = ret;
-			r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
-			/* OpenCL requres this value be at least
-			 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
-			 * I'm really not sure what value to report here, but
-			 * MAX_GLOBAL_SIZE / 4 seems resonable.
+
+			/* XXX: The limit in older kernels is 256 MB.  We
+			 * should add a query here for newer kernels.
 			 */
-			*max_mem_alloc_size = max_global_size / 4;
+			*max_mem_alloc_size = 256 * 1024 * 1024;
 		}
 		return sizeof(uint64_t);
 

src/gallium/drivers/radeon/r600_query.c

@@ -786,12 +786,40 @@ void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
 	assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
 }
 
+static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx)
+{
+	struct r600_query *query;
+	unsigned num_dw = 0;
+
+	LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
+		/* begin + end */
+		num_dw += query->num_cs_dw * 2;
+
+		/* Workaround for the fact that
+		 * num_cs_dw_nontimer_queries_suspend is incremented for every
+		 * resumed query, which raises the bar in need_cs_space for
+		 * queries about to be resumed.
+		 */
+		num_dw += query->num_cs_dw;
+	}
+	/* primitives generated query */
+	num_dw += ctx->streamout.enable_atom.num_dw;
+	/* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
+	num_dw += 13;
+
+	return num_dw;
+}
+
 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
 {
 	struct r600_query *query;
 
 	assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
 
+	/* Check CS space here. Resuming must not be interrupted by flushes. */
+	ctx->need_gfx_cs_space(&ctx->b,
+			       r600_queries_num_cs_dw_for_resuming(ctx), TRUE);
+
 	LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
 		r600_emit_query_begin(ctx, query);
 	}

src/gallium/drivers/radeon/r600_texture.c

@@ -389,7 +389,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 				      struct r600_cmask_info *out)
 {
 	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
-	unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
+	unsigned num_pipes = rscreen->tiling_info.num_channels;
 	unsigned cl_width, cl_height;
 
 	switch (num_pipes) {
@@ -487,7 +487,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 {
 	unsigned cl_width, cl_height, width, height;
 	unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
-	unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
+	unsigned num_pipes = rscreen->tiling_info.num_channels;
 
 	/* HTILE is broken with 1D tiling on old kernels and CIK. */
 	if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&

src/gallium/drivers/radeonsi/Android.mk

@@ -30,7 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES :=
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_pipe_radeonsi
 

src/gallium/drivers/radeonsi/si_blit.c

@@ -60,9 +60,16 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
 	util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader);
 	util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader);
 	util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
+	if (sctx->queued.named.sample_mask) {
+		util_blitter_save_sample_mask(sctx->blitter,
+					      sctx->queued.named.sample_mask->sample_mask);
+	}
 	if (sctx->queued.named.viewport) {
 		util_blitter_save_viewport(sctx->blitter, &sctx->queued.named.viewport->viewport);
 	}
+	if (sctx->queued.named.scissor) {
+		util_blitter_save_scissor(sctx->blitter, &sctx->queued.named.scissor->scissor);
+	}
 	util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
 	util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
 				     (struct pipe_stream_output_target**)sctx->b.streamout.targets);

src/gallium/drivers/radeonsi/si_compute.c

@@ -100,7 +100,7 @@ static void si_set_global_binding(
 
 	if (!resources) {
 		for (i = first; i < first + n; i++) {
-			program->global_buffers[i] = NULL;
+			pipe_resource_reference(&program->global_buffers[i], NULL);
 		}
 		return;
 	}
@@ -108,7 +108,7 @@ static void si_set_global_binding(
 	for (i = first; i < first + n; i++) {
 		uint64_t va;
 		uint32_t offset;
-		program->global_buffers[i] = resources[i];
+		pipe_resource_reference(&program->global_buffers[i], resources[i]);
 		va = r600_resource_va(ctx->screen, resources[i]);
 		offset = util_le32_to_cpu(*handles[i]);
 		va += offset;
@@ -288,8 +288,8 @@ static void si_launch_grid(
 	}
 #endif
 
-	FREE(pm4);
 	FREE(kernel_args);
+	si_pm4_free_state(sctx, pm4, ~0);
 }
 
 

src/gallium/drivers/radeonsi/si_descriptors.c

@@ -987,9 +987,9 @@ void si_init_all_descriptors(struct si_context *sctx)
 
 		si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
 
-		sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
-		sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
-		sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
+		sctx->atoms.s.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
+		sctx->atoms.s.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
+		sctx->atoms.s.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
 	}
 
 

src/gallium/drivers/radeonsi/si_hw_context.c

@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
 	}
 
 	/* Count in framebuffer cache flushes at the end of CS. */
-	num_dw += ctx->atoms.cache_flush->num_dw;
+	num_dw += ctx->atoms.s.cache_flush->num_dw;
 
 #if SI_TRACE_CS
 	if (ctx->screen->b.trace_bo) {

src/gallium/drivers/radeonsi/si_pipe.c

@@ -23,6 +23,7 @@
 
 #include "si_pipe.h"
 #include "si_public.h"
+#include "sid.h"
 
 #include "radeon/radeon_uvd.h"
 #include "util/u_blitter.h"
@@ -39,6 +40,8 @@ static void si_destroy_context(struct pipe_context *context)
 
 	si_release_all_descriptors(sctx);
 
+	pipe_resource_reference(&sctx->esgs_ring.buffer, NULL);
+	pipe_resource_reference(&sctx->gsvs_ring.buffer, NULL);
 	pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
 	r600_resource_reference(&sctx->border_color_table, NULL);
 
@@ -105,10 +108,10 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, void *
 
 	/* Initialize cache_flush. */
 	sctx->cache_flush = si_atom_cache_flush;
-	sctx->atoms.cache_flush = &sctx->cache_flush;
+	sctx->atoms.s.cache_flush = &sctx->cache_flush;
 
-	sctx->atoms.streamout_begin = &sctx->b.streamout.begin_atom;
-	sctx->atoms.streamout_enable = &sctx->b.streamout.enable_atom;
+	sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
+	sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
 
 	switch (sctx->b.chip_class) {
 	case SI:
@@ -384,6 +387,57 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 	r600_destroy_common_screen(&sscreen->b);
 }
 
+#define SI_TILE_MODE_COLOR_2D_8BPP  14
+
+/* Initialize pipe config. This is especially important for GPUs
+ * with 16 pipes and more where it's initialized incorrectly by
+ * the TILING_CONFIG ioctl. */
+static bool si_initialize_pipe_config(struct si_screen *sscreen)
+{
+	unsigned mode2d;
+
+	/* This is okay, because there can be no 2D tiling without
+	 * the tile mode array, so we won't need the pipe config.
+	 * Return "success".
+	 */
+	if (!sscreen->b.info.si_tile_mode_array_valid)
+		return true;
+
+	/* The same index is used for the 2D mode on CIK too. */
+	mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP];
+
+	switch (G_009910_PIPE_CONFIG(mode2d)) {
+	case V_02803C_ADDR_SURF_P2:
+		sscreen->b.tiling_info.num_channels = 2;
+		break;
+	case V_02803C_X_ADDR_SURF_P4_8X16:
+	case V_02803C_X_ADDR_SURF_P4_16X16:
+	case V_02803C_X_ADDR_SURF_P4_16X32:
+	case V_02803C_X_ADDR_SURF_P4_32X32:
+		sscreen->b.tiling_info.num_channels = 4;
+		break;
+	case V_02803C_X_ADDR_SURF_P8_16X16_8X16:
+	case V_02803C_X_ADDR_SURF_P8_16X32_8X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_8X16:
+	case V_02803C_X_ADDR_SURF_P8_16X32_16X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_16X16:
+	case V_02803C_X_ADDR_SURF_P8_32X32_16X32:
+	case V_02803C_X_ADDR_SURF_P8_32X64_32X32:
+		sscreen->b.tiling_info.num_channels = 8;
+		break;
+	case V_02803C_X_ADDR_SURF_P16_32X32_8X16:
+	case V_02803C_X_ADDR_SURF_P16_32X32_16X16:
+		sscreen->b.tiling_info.num_channels = 16;
+		break;
+	default:
+		assert(0);
+		fprintf(stderr, "radeonsi: Unknown pipe config %i.\n",
+			G_009910_PIPE_CONFIG(mode2d));
+		return false;
+	}
+	return true;
+}
+
 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 {
 	struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
@@ -399,7 +453,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 	sscreen->b.b.is_format_supported = si_is_format_supported;
 	sscreen->b.b.resource_create = r600_resource_create_common;
 
-	if (!r600_common_screen_init(&sscreen->b, ws)) {
+	if (!r600_common_screen_init(&sscreen->b, ws) ||
+	    !si_initialize_pipe_config(sscreen)) {
 		FREE(sscreen);
 		return NULL;
 	}

src/gallium/drivers/radeonsi/si_pipe.h

@@ -114,7 +114,7 @@ struct si_context {
 			struct r600_atom *streamout_begin;
 			struct r600_atom *streamout_enable; /* must be after streamout_begin */
 			struct r600_atom *framebuffer;
-		};
+		} s;
 		struct r600_atom *array[0];
 	} atoms;
 

src/gallium/drivers/radeonsi/si_shader.c

@@ -2616,5 +2616,8 @@ out:
 
 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
 {
+	if (shader->gs_copy_shader)
+		si_pipe_shader_destroy(ctx, shader->gs_copy_shader);
+
 	r600_resource_reference(&shader->bo, NULL);
 }

src/gallium/drivers/radeonsi/si_state.c

@@ -458,18 +458,20 @@ static void si_set_scissor_states(struct pipe_context *ctx,
                                   const struct pipe_scissor_state *state)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
-	struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+	struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
+	struct si_pm4_state *pm4 = &scissor->pm4;
 
-	if (pm4 == NULL)
+	if (scissor == NULL)
 		return;
 
+	scissor->scissor = *state;
 	si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
 		       S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
 		       S_028250_WINDOW_OFFSET_DISABLE(1));
 	si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
 		       S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
 
-	si_pm4_set_state(sctx, scissor, pm4);
+	si_pm4_set_state(sctx, scissor, scissor);
 }
 
 static void si_set_viewport_states(struct pipe_context *ctx,
@@ -2242,9 +2244,10 @@ static void si_delete_shader_selector(struct pipe_context *ctx,
 
 	while (p) {
 		c = p->next_variant;
-		if (sel->type == PIPE_SHADER_GEOMETRY)
+		if (sel->type == PIPE_SHADER_GEOMETRY) {
 			si_pm4_delete_state(sctx, gs, p->pm4);
-		else if (sel->type == PIPE_SHADER_FRAGMENT)
+			si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
+		} else if (sel->type == PIPE_SHADER_FRAGMENT)
 			si_pm4_delete_state(sctx, ps, p->pm4);
 		else if (p->key.vs.as_es)
 			si_pm4_delete_state(sctx, es, p->pm4);
@@ -2257,7 +2260,7 @@ static void si_delete_shader_selector(struct pipe_context *ctx,
 
 	free(sel->tokens);
 	free(sel);
- }
+}
 
 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
 {
@@ -2823,16 +2826,18 @@ static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
-	struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+	struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
+	struct si_pm4_state *pm4 = &state->pm4;
 	uint16_t mask = sample_mask;
 
-        if (pm4 == NULL)
+        if (state == NULL)
                 return;
 
+	state->sample_mask = mask;
 	si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
 	si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
 
-	si_pm4_set_state(sctx, sample_mask, pm4);
+	si_pm4_set_state(sctx, sample_mask, state);
 }
 
 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
@@ -2959,7 +2964,7 @@ void si_init_state_functions(struct si_context *sctx)
 {
 	int i;
 
-	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.framebuffer, si_emit_framebuffer_state, 0);
+	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
 
 	sctx->b.b.create_blend_state = si_create_blend_state;
 	sctx->b.b.bind_blend_state = si_bind_blend_state;

src/gallium/drivers/radeonsi/si_state.h

@@ -38,6 +38,16 @@ struct si_state_blend {
 	bool			alpha_to_one;
 };
 
+struct si_state_sample_mask {
+	struct si_pm4_state	pm4;
+	uint16_t		sample_mask;
+};
+
+struct si_state_scissor {
+	struct si_pm4_state		pm4;
+	struct pipe_scissor_state	scissor;
+};
+
 struct si_state_viewport {
 	struct si_pm4_state		pm4;
 	struct pipe_viewport_state	viewport;
@@ -81,8 +91,8 @@ union si_state {
 		struct si_state_blend		*blend;
 		struct si_pm4_state		*blend_color;
 		struct si_pm4_state		*clip;
-		struct si_pm4_state		*sample_mask;
-		struct si_pm4_state		*scissor;
+		struct si_state_sample_mask	*sample_mask;
+		struct si_state_scissor		*scissor;
 		struct si_state_viewport	*viewport;
 		struct si_state_rasterizer	*rasterizer;
 		struct si_state_dsa		*dsa;

src/gallium/drivers/radeonsi/si_state_draw.c

@@ -428,13 +428,10 @@ static bool si_update_draw_info_state(struct si_context *sctx,
 		bool ia_switch_on_eop = wd_switch_on_eop;
 		unsigned primgroup_size = 64;
 
-		/* Hawaii hangs if instancing is enabled and each instance
-		 * is smaller than a prim group and WD_SWITCH_ON_EOP is 0.
+		/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
 		 * We don't know that for indirect drawing, so treat it as
 		 * always problematic. */
-		if (sctx->b.family == CHIP_HAWAII &&
-		    ((info->instance_count > 1 &&
-		      u_prims_for_vertices(info->mode, info->count) < primgroup_size))) {
+		if (sctx->b.family == CHIP_HAWAII && info->instance_count > 1) {
 			wd_switch_on_eop = true;
 			ia_switch_on_eop = true;
 		}
@@ -984,7 +981,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
 	/* Check flush flags. */
 	if (sctx->b.flags)
-		sctx->atoms.cache_flush->dirty = true;
+		sctx->atoms.s.cache_flush->dirty = true;
 
 	si_need_cs_space(sctx, 0, TRUE);
 

src/gallium/state_trackers/clover/api/queue.cpp

@@ -58,7 +58,11 @@ clRetainCommandQueue(cl_command_queue d_q) try {
 
 CLOVER_API cl_int
 clReleaseCommandQueue(cl_command_queue d_q) try {
-   if (obj(d_q).release())
+   auto &q = obj(d_q);
+
+   q.flush();
+
+   if (q.release())
       delete pobj(d_q);
 
    return CL_SUCCESS;

src/gallium/state_trackers/dri/common/dri_screen.c

@@ -205,37 +205,6 @@ dri_fill_in_modes(struct dri_screen *screen)
    return (const __DRIconfig **)configs;
 }
 
-/* The Gallium way to force MSAA. */
-DEBUG_GET_ONCE_NUM_OPTION(msaa, "GALLIUM_MSAA", 0);
-
-/* The NVIDIA way to force MSAA. The same variable is used by the NVIDIA
- * driver. */
-DEBUG_GET_ONCE_NUM_OPTION(msaa_nv, "__GL_FSAA_MODE", 0);
-
-static void
-dri_force_msaa_visual(struct st_visual *stvis,
-                      struct pipe_screen *screen)
-{
-   int i;
-   int samples = debug_get_option_msaa();
-
-   if (!samples)
-      samples = debug_get_option_msaa_nv();
-
-   if (samples <= 1)
-      return; /* nothing to do */
-
-   /* Choose a supported sample count greater than or equal to samples. */
-   for (i = samples; i <= MSAA_VISUAL_MAX_SAMPLES; i++) {
-      if (screen->is_format_supported(screen, stvis->color_format,
-                                      PIPE_TEXTURE_2D, i,
-                                      PIPE_BIND_RENDER_TARGET)) {
-         stvis->samples = i;
-         break;
-      }
-   }
-}
-
 /**
  * Roughly the converse of dri_fill_in_modes.
  */
@@ -260,10 +229,6 @@ dri_fill_st_visual(struct st_visual *stvis, struct dri_screen *screen,
    if (mode->sampleBuffers) {
       stvis->samples = mode->samples;
    }
-   else {
-      /* This must be done after stvis->color_format is set. */
-      dri_force_msaa_visual(stvis, screen->base.screen);
-   }
 
    switch (mode->depthBits) {
    default:

src/gallium/state_trackers/egl/android/native_android.cpp

@@ -147,10 +147,6 @@ get_pipe_format(int native)
    case HAL_PIXEL_FORMAT_BGRA_8888:
       fmt = PIPE_FORMAT_B8G8R8A8_UNORM;
       break;
-   case HAL_PIXEL_FORMAT_RGBA_5551:
-      /* fmt = PIPE_FORMAT_A1B5G5R5_UNORM; */
-   case HAL_PIXEL_FORMAT_RGBA_4444:
-      /* fmt = PIPE_FORMAT_A4B4G4R4_UNORM; */
    default:
       ALOGE("unsupported native format 0x%x", native);
       fmt = PIPE_FORMAT_NONE;

src/gallium/state_trackers/xa/xa_renderer.c

@@ -530,11 +530,22 @@ renderer_draw_yuv(struct xa_context *r,
                          src_x, src_y, src_w, src_h,
                          dst_x, dst_y, dst_w, dst_h, srf);
 
+   if (!r->scissor_valid) {
+       r->scissor.minx = 0;
+       r->scissor.miny = 0;
+       r->scissor.maxx = r->dst->tex->width0;
+       r->scissor.maxy = r->dst->tex->height0;
+   }
+
+   r->pipe->set_scissor_states(r->pipe, 0, 1, &r->scissor);
+
    cso_set_vertex_elements(r->cso, num_attribs, r->velems);
    util_draw_user_vertex_buffer(r->cso, r->buffer, PIPE_PRIM_QUADS,
                                 4,	/* verts */
                                 num_attribs);	/* attribs/vert */
    r->buffer_size = 0;
+
+   xa_scissor_reset(r);
 }
 
 void

src/gallium/state_trackers/xa/xa_yuv.c

@@ -146,6 +146,7 @@ xa_yuv_planar_blit(struct xa_context *r,
 	int w = box->x2 - box->x1;
 	int h = box->y2 - box->y1;
 
+        xa_scissor_update(r, x, y, box->x2, box->y2);
 	renderer_draw_yuv(r,
 			  (float)src_x + scale_x * (x - dst_x),
 			  (float)src_y + scale_y * (y - dst_y),

src/gallium/targets/egl-static/Android.mk

@@ -52,6 +52,9 @@ LOCAL_C_INCLUDES += \
 	$(DRM_TOP)
 endif
 
+ifneq ($(filter freedreno, $(MESA_GPU_DRIVERS)),)
+LOCAL_CFLAGS += -DGALLIUM_FREEDRENO
+endif
 ifneq ($(filter i915g, $(MESA_GPU_DRIVERS)),)
 LOCAL_CFLAGS += -D_EGL_PIPE_I915=1
 endif

src/gallium/winsys/freedreno/drm/Android.mk

@@ -0,0 +1,37 @@
+# Copyright (C) 2014 Emil Velikov <emil.l.velikov@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := $(C_SOURCES)
+
+LOCAL_C_INCLUDES := \
+	$(TARGET_OUT_HEADERS)/libdrm \
+	$(TARGET_OUT_HEADERS)/freedreno
+
+LOCAL_MODULE := libmesa_winsys_freedreno
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

src/gallium/winsys/nouveau/drm/Android.mk

@@ -30,10 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES := \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm \
-	$(DRM_TOP)/nouveau
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_winsys_nouveau
 

src/gallium/winsys/radeon/drm/Android.mk

@@ -30,9 +30,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
-LOCAL_C_INCLUDES := \
-	$(DRM_TOP) \
-	$(DRM_TOP)/include/drm
+LOCAL_C_INCLUDES := $(TARGET_OUT_HEADERS)/libdrm
 
 LOCAL_MODULE := libmesa_winsys_radeon
 

src/gallium/winsys/radeon/drm/radeon_drm_cs.c

@@ -155,7 +155,7 @@ static struct radeon_winsys_cs *
 radeon_drm_cs_create(struct radeon_winsys *rws,
                      enum ring_type ring_type,
                      void (*flush)(void *ctx, unsigned flags,
-				   struct pipe_fence_handle **fence),
+                                   struct pipe_fence_handle **fence),
                      void *flush_ctx,
                      struct radeon_winsys_cs_handle *trace_buf)
 {
@@ -196,10 +196,10 @@ radeon_drm_cs_create(struct radeon_winsys *rws,
 #define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
 
 static INLINE void update_reloc(struct drm_radeon_cs_reloc *reloc,
-				enum radeon_bo_domain rd,
-				enum radeon_bo_domain wd,
-				unsigned priority,
-				enum radeon_bo_domain *added_domains)
+                                enum radeon_bo_domain rd,
+                                enum radeon_bo_domain wd,
+                                unsigned priority,
+                                enum radeon_bo_domain *added_domains)
 {
     *added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
 
@@ -434,33 +434,37 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
 
     switch (cs->base.ring_type) {
     case RING_DMA:
-	    /* pad DMA ring to 8 DWs */
-	    if (cs->ws->info.chip_class <= SI) {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
-	    } else {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0x00000000); /* NOP packet */
-	    }
-	    break;
+        /* pad DMA ring to 8 DWs */
+        if (cs->ws->info.chip_class <= SI) {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
+        } else {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0x00000000); /* NOP packet */
+        }
+        break;
     case RING_GFX:
-	    /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
-	     * r6xx, requires at least 4 dw alignment to avoid a hw bug.
-	     */
-	    if (cs->ws->info.chip_class <= SI) {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
-	    } else {
-		    while (rcs->cdw & 7)
-			    OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
-	    }
-	    break;
+        /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
+         * r6xx, requires at least 4 dw alignment to avoid a hw bug.
+         * hawaii with old firmware needs type2 nop packet.
+         * accel_working2 with value 3 indicates the new firmware.
+         */
+        if (cs->ws->info.chip_class <= SI ||
+            (cs->ws->info.family == CHIP_HAWAII &&
+             cs->ws->accel_working2 < 3)) {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
+        } else {
+            while (rcs->cdw & 7)
+                OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
+        }
+        break;
     case RING_UVD:
-            while (rcs->cdw & 15)
-		OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
-	    break;
+        while (rcs->cdw & 15)
+            OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
+        break;
     default:
-	    break;
+        break;
     }
 
     if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {

src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

@@ -382,6 +382,16 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
                          &ws->info.r600_max_pipes);
 
+    radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
+                         &ws->accel_working2);
+    if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
+        fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
+                "returned accel_working2 value %u is smaller than 2. "
+                "Please install a newer kernel.\n",
+                ws->accel_working2);
+        return FALSE;
+    }
+
     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
                              ws->info.si_tile_mode_array)) {
         ws->info.si_tile_mode_array_valid = TRUE;

src/gallium/winsys/radeon/drm/radeon_drm_winsys.h

@@ -55,6 +55,7 @@ struct radeon_drm_winsys {
     enum radeon_generation gen;
     struct radeon_info info;
     uint32_t va_start;
+    uint32_t accel_working2;
 
     struct pb_manager *kman;
     struct pb_manager *cman;

src/gallium/winsys/svga/drm/vmw_screen_dri.c

@@ -238,7 +238,7 @@ out_mip:
 
 static struct svga_winsys_surface *
 vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
-			    struct winsys_handle *whandle,
+                            struct winsys_handle *whandle,
 			    SVGA3dSurfaceFormat *format)
 {
     struct vmw_svga_winsys_surface *vsrf;
@@ -248,7 +248,8 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
     struct drm_vmw_surface_arg *req = &arg.req;
     struct drm_vmw_surface_create_req *rep = &arg.rep;
     uint32_t handle = 0;
-    SVGA3dSize size;
+    struct drm_vmw_size size;
+    SVGA3dSize base_size;
     int ret;
     int i;
 
@@ -274,7 +275,7 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
 
     memset(&arg, 0, sizeof(arg));
     req->sid = handle;
-    rep->size_addr = (size_t)&size;
+    rep->size_addr = (unsigned long)&size;
 
     ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_REF_SURFACE,
 			      &arg, sizeof(arg));
@@ -324,7 +325,11 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
     *format = rep->format;
 
     /* Estimate usage, for early flushing. */
-    vsrf->size = svga3dsurface_get_serialized_size(rep->format, size,
+
+    base_size.width = size.width;
+    base_size.height = size.height;
+    base_size.depth = size.depth;
+    vsrf->size = svga3dsurface_get_serialized_size(rep->format, base_size,
                                                    rep->mip_levels[0],
                                                    FALSE);
 

src/glsl/Android.mk

@@ -39,12 +39,12 @@ LOCAL_SRC_FILES := \
 	$(LIBGLSL_FILES)
 
 LOCAL_C_INCLUDES := \
-	external/astl/include \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/mesa
 
 LOCAL_MODULE := libmesa_glsl
 
+include external/stlport/libstlport.mk
 include $(LOCAL_PATH)/Android.gen.mk
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)

src/mesa/drivers/common/meta.c

@@ -2741,9 +2741,9 @@ _mesa_meta_blit_shader_table_cleanup(struct blit_shader_table *table)
 static GLenum
 get_temp_image_type(struct gl_context *ctx, mesa_format format)
 {
-   GLenum baseFormat;
-
-   baseFormat = _mesa_get_format_base_format(format);
+   const GLenum baseFormat = _mesa_get_format_base_format(format);
+   const GLint format_red_bits = _mesa_get_format_bits(format, GL_RED_BITS);
+   GLenum datatype = _mesa_get_format_datatype(format);
 
    switch (baseFormat) {
    case GL_RGBA:
@@ -2754,18 +2754,15 @@ get_temp_image_type(struct gl_context *ctx, mesa_format format)
    case GL_LUMINANCE:
    case GL_LUMINANCE_ALPHA:
    case GL_INTENSITY:
-      if (ctx->DrawBuffer->Visual.redBits <= 8) {
+      if (datatype == GL_INT || datatype == GL_UNSIGNED_INT) {
+         return datatype;
+      } else if (format_red_bits <= 8) {
          return GL_UNSIGNED_BYTE;
-      } else if (ctx->DrawBuffer->Visual.redBits <= 16) {
+      } else if (format_red_bits <= 16) {
          return GL_UNSIGNED_SHORT;
-      } else {
-         GLenum datatype = _mesa_get_format_datatype(format);
-         if (datatype == GL_INT || datatype == GL_UNSIGNED_INT)
-            return datatype;
-         return GL_FLOAT;
       }
+      return GL_FLOAT;
    case GL_DEPTH_COMPONENT: {
-      GLenum datatype = _mesa_get_format_datatype(format);
       if (datatype == GL_FLOAT)
          return GL_FLOAT;
       else

src/mesa/drivers/common/meta_blit.c

@@ -325,10 +325,12 @@ setup_glsl_blit_framebuffer(struct gl_context *ctx,
                             struct gl_renderbuffer *src_rb,
                             GLenum target)
 {
+   unsigned texcoord_size;
+
    /* target = GL_TEXTURE_RECTANGLE is not supported in GLES 3.0 */
    assert(_mesa_is_desktop_gl(ctx) || target == GL_TEXTURE_2D);
 
-   unsigned texcoord_size = 2 + (src_rb->Depth > 1 ? 1 : 0);
+   texcoord_size = 2 + (src_rb->Depth > 1 ? 1 : 0);
 
    _mesa_meta_setup_vertex_objects(&blit->VAO, &blit->VBO, true,
                                    2, texcoord_size, 0);

src/mesa/drivers/common/meta_generate_mipmap.c

@@ -43,6 +43,7 @@
 #include "main/varray.h"
 #include "main/viewport.h"
 #include "drivers/common/meta.h"
+#include "program/prog_instruction.h"
 
 
 /**
@@ -168,6 +169,8 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
    GLenum faceTarget;
    GLuint dstLevel;
    GLuint samplerSave;
+   GLint swizzle[4];
+   GLboolean swizzleSaved = GL_FALSE;
 
    if (fallback_required(ctx, target, texObj)) {
       _mesa_generate_mipmap(ctx, target, texObj);
@@ -231,6 +234,13 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
 
    _mesa_TexParameteri(target, GL_GENERATE_MIPMAP, GL_FALSE);
 
+   if (texObj->_Swizzle != SWIZZLE_NOOP) {
+      static const GLint swizzleNoop[4] = { GL_RED, GL_GREEN, GL_BLUE, GL_ALPHA };
+      memcpy(swizzle, texObj->Swizzle, sizeof(swizzle));
+      swizzleSaved = GL_TRUE;
+      _mesa_TexParameteriv(target, GL_TEXTURE_SWIZZLE_RGBA, swizzleNoop);
+   }
+
    /* Silence valgrind warnings about reading uninitialized stack. */
    memset(verts, 0, sizeof(verts));
 
@@ -347,4 +357,6 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
    _mesa_TexParameteri(target, GL_TEXTURE_MAX_LEVEL, maxLevelSave);
    if (genMipmapSave)
       _mesa_TexParameteri(target, GL_GENERATE_MIPMAP, genMipmapSave);
+   if (swizzleSaved)
+      _mesa_TexParameteriv(target, GL_TEXTURE_SWIZZLE_RGBA, swizzle);
 }

src/mesa/drivers/dri/i915/Android.mk

@@ -42,7 +42,7 @@ LOCAL_C_INCLUDES := \
 	$(DRM_TOP)/intel
 
 LOCAL_SRC_FILES := \
-	$(i915_C_FILES)
+	$(i915_FILES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := \
 	$(MESA_DRI_WHOLE_STATIC_LIBRARIES)

src/mesa/drivers/dri/i915/intel_screen.c

@@ -616,6 +616,8 @@ intel_create_image_from_fds(__DRIscreen *screen,
       return NULL;
    }
 
+   intel_setup_image_from_dimensions(image);
+
    image->planar_format = f;
    for (i = 0; i < f->nplanes; i++) {
       index = f->planes[i].buffer_index;

src/mesa/drivers/dri/i965/brw_clip_unfilled.c

@@ -197,7 +197,7 @@ static void compute_offset( struct brw_clip_compile *c )
    struct brw_reg dir = c->reg.dir;
 
    brw_math_invert(p, get_element(off, 2), get_element(dir, 2));
-   brw_MUL(p, vec2(off), dir, get_element(off, 2));
+   brw_MUL(p, vec2(off), vec2(dir), get_element(off, 2));
 
    brw_CMP(p,
 	   vec1(brw_null_reg()),
@@ -208,8 +208,8 @@ static void compute_offset( struct brw_clip_compile *c )
    brw_SEL(p, vec1(off), brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1)));
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 
-   brw_MUL(p, vec1(off), off, brw_imm_f(c->key.offset_factor));
-   brw_ADD(p, vec1(off), off, brw_imm_f(c->key.offset_units));
+   brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor));
+   brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units));
 }
 
 

src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

@@ -273,6 +273,10 @@ vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
    if (has_source_modifiers && value.type != inst->src[arg].type)
       return false;
 
+   if (has_source_modifiers &&
+       inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
+      return false;
+
    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
                         inst->opcode == BRW_OPCODE_MAD ||
                         inst->opcode == BRW_OPCODE_BFE ||

src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

@@ -2478,7 +2478,7 @@ vec4_visitor::visit(ir_texture *ir)
       } else if (ir->op == ir_txf_ms) {
          emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
                   sample_index));
-         if (brw->gen >= 7)
+         if (brw->gen >= 7) {
             /* MCS data is in the first channel of `mcs`, but we need to get it into
              * the .y channel of the second vec4 of params, so replicate .x across
              * the whole vec4 and then mask off everything except .y
@@ -2486,6 +2486,7 @@ vec4_visitor::visit(ir_texture *ir)
             mcs.swizzle = BRW_SWIZZLE_XXXX;
             emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
                      mcs));
+         }
          inst->mlen++;
       } else if (ir->op == ir_txd) {
 	 const glsl_type *type = lod_type;

src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp

@@ -183,7 +183,9 @@ gen8_vec4_generator::generate_gs_set_vertex_count(struct brw_reg eot_mrf_header,
    /* Move the vertex count into the second MRF for the EOT write. */
    assert(eot_mrf_header.file == BRW_MESSAGE_REGISTER_FILE);
    int dst_nr = GEN7_MRF_HACK_START + eot_mrf_header.nr + 1;
-   MOV(retype(brw_vec8_grf(dst_nr, 0), BRW_REGISTER_TYPE_UD), src);
+   gen8_instruction *inst =
+      MOV(retype(brw_vec8_grf(dst_nr, 0), BRW_REGISTER_TYPE_UD), src);
+   gen8_set_mask_control(inst, BRW_MASK_DISABLE);
 }
 
 void
@@ -894,6 +896,7 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
       default_state.predicate = ir->predicate;
       default_state.predicate_inverse = ir->predicate_inverse;
       default_state.saturate = ir->saturate;
+      default_state.mask_control = ir->force_writemask_all;
 
       const unsigned pre_emit_nr_inst = nr_inst;
 

src/mesa/drivers/dri/i965/intel_mipmap_tree.c

@@ -242,6 +242,26 @@ intel_miptree_create_layout(struct brw_context *brw,
        _mesa_get_format_name(format),
        first_level, last_level, depth0, mt);
 
+   if (target == GL_TEXTURE_1D_ARRAY) {
+      /* For a 1D Array texture the OpenGL API will treat the height0
+       * parameter as the number of array slices. For Intel hardware, we treat
+       * the 1D array as a 2D Array with a height of 1.
+       *
+       * So, when we first come through this path to create a 1D Array
+       * texture, height0 stores the number of slices, and depth0 is 1. In
+       * this case, we want to swap height0 and depth0.
+       *
+       * Since some miptrees will be created based on the base miptree, we may
+       * come through this path and see height0 as 1 and depth0 being the
+       * number of slices. In this case we don't need to do the swap.
+       */
+      assert(height0 == 1 || depth0 == 1);
+      if (height0 > 1) {
+         depth0 = height0;
+         height0 = 1;
+      }
+   }
+
    mt->target = target;
    mt->format = format;
    mt->first_level = first_level;

src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c

@@ -86,6 +86,7 @@ nouveau_bufferobj_data(struct gl_context *ctx, GLenum target, GLsizeiptrARB size
 	/* Free previous storage */
 	nouveau_bo_ref(NULL, &nbo->bo);
 	free(nbo->sys);
+	nbo->sys = NULL;
 
 	if (target == GL_ELEMENT_ARRAY_BUFFER_ARB ||
 	    (size < 512 && usage == GL_DYNAMIC_DRAW_ARB) ||

src/mesa/drivers/dri/nouveau/nouveau_render_t.c

@@ -56,21 +56,21 @@
  */
 #define EMIT_VBO(out, ctx, start, delta, n) do {			\
 		struct nouveau_render_state *render = to_render_state(ctx); \
-		int npush = n;						\
+		int _npush = n;						\
 									\
-		while (npush) {						\
-			int npack = MIN2(npush, MAX_PACKET * MAX_OUT_##out); \
-			npush -= npack;					\
+		while (_npush) {						\
+			int _npack = MIN2(_npush, MAX_PACKET * MAX_OUT_##out); \
+			_npush -= _npack;					\
 									\
-			BATCH_PACKET_##out((npack + MAX_OUT_##out - 1)	\
+			BATCH_PACKET_##out((_npack + MAX_OUT_##out - 1)	\
 					   / MAX_OUT_##out);		\
-			while (npack) {					\
-				int nout = MIN2(npack, MAX_OUT_##out);	\
-				npack -= nout;				\
+			while (_npack) {				\
+				int _nout = MIN2(_npack, MAX_OUT_##out);\
+				_npack -= _nout;			\
 									\
 				OUT_INDICES_##out(render, start, delta, \
-						  nout);		\
-				start += nout;				\
+						  _nout);		\
+				start += _nout;				\
 			}						\
 		}							\
 	} while (0)

src/mesa/drivers/dri/nouveau/nouveau_state.c

@@ -492,6 +492,7 @@ nouveau_update_state(struct gl_context *ctx, GLbitfield new_state)
 
 	_swrast_InvalidateState(ctx, new_state);
 	_tnl_InvalidateState(ctx, new_state);
+	_vbo_InvalidateState(ctx, new_state);
 
 	nouveau_state_emit(ctx);
 }

src/mesa/drivers/dri/nouveau/nv04_state_fb.c

@@ -93,6 +93,7 @@ nv04_emit_framebuffer(struct gl_context *ctx, int emit)
 
 	/* Recompute the scissor state. */
 	context_dirty(ctx, SCISSOR);
+	context_dirty(ctx, CONTROL);
 }
 
 void

src/mesa/drivers/dri/nouveau/nv04_state_raster.c

@@ -123,6 +123,7 @@ void
 nv04_emit_control(struct gl_context *ctx, int emit)
 {
 	struct nv04_context *nv04 = to_nv04_context(ctx);
+	struct gl_framebuffer *fb = ctx->DrawBuffer;
 	int cull = ctx->Polygon.CullFaceMode;
 	int front = ctx->Polygon.FrontFace;
 
@@ -146,9 +147,9 @@ nv04_emit_control(struct gl_context *ctx, int emit)
 				 NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW;
 
 	/* Depth test. */
-	if (ctx->Depth.Test)
+	if (ctx->Depth.Test && fb->Visual.depthBits > 0)
 		nv04->ctrl[0] |= NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE;
-	if (ctx->Depth.Mask)
+	if (ctx->Depth.Mask && fb->Visual.depthBits > 0)
 		nv04->ctrl[0] |= NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE;
 
 	nv04->ctrl[0] |= get_comparison_op(ctx->Depth.Func) << 16;
@@ -174,7 +175,7 @@ nv04_emit_control(struct gl_context *ctx, int emit)
 	if (ctx->Stencil.WriteMask[0])
 		nv04->ctrl[0] |= NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE;
 
-	if (ctx->Stencil.Enabled)
+	if (ctx->Stencil._Enabled)
 		nv04->ctrl[1] |= NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE;
 
 	nv04->ctrl[1] |= get_comparison_op(ctx->Stencil.Function[0]) << 4 |

src/mesa/drivers/dri/nouveau/nv10_state_fb.c

@@ -152,6 +152,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 
 	context_dirty(ctx, VIEWPORT);
 	context_dirty(ctx, SCISSOR);
+	context_dirty(ctx, DEPTH);
 }
 
 void