docs: add sha256 checksums for 17.1.10

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
docs: add release notes for 17.1.10
2017-09-25 17:00:35 +00:00 · 2017-09-25 15:18:34 +00:00 · 2017-09-25 15:11:05 +00:00 · 2017-09-21 09:29:27 +02:00 · 2017-09-21 09:29:27 +02:00 · 2017-09-20 22:54:12 +02:00
46 changed files with 777 additions and 83 deletions
--- a/.travis.yml
+++ b/.travis.yml
@@ -38,6 +38,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS=""
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--disable-libunwind"
      addons:
        apt:
          packages:
@@ -62,6 +63,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS="swr"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -77,6 +79,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Gallium Drivers Other"
        - BUILD=make
@@ -89,6 +92,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS="i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -104,6 +108,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        # NOTE: Analogous to SWR above, building Clover is quite slow.
        - LABEL="make Gallium ST Clover"
@@ -121,6 +126,7 @@ matrix:
        # Regardless - we're doing a quick build test here.
        - GALLIUM_DRIVERS="i915"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -140,11 +146,14 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Gallium ST Other"
        - BUILD=make
        - MAKEFLAGS="-j4"
        - MAKE_CHECK_COMMAND="true"
+        - LLVM_VERSION=3.3
+        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
        - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
        - DRI_DRIVERS=""
        - GALLIUM_ST="--enable-dri --disable-opencl --enable-xa --enable-nine --enable-xvmc --enable-vdpau --enable-va --enable-omx --enable-gallium-osmesa"
@@ -153,9 +162,12 @@ matrix:
        # Regardless - we're doing a quick build test here.
        - GALLIUM_DRIVERS="i915,swrast"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          packages:
+            # We actually want to test against llvm-3.3
+            - llvm-3.3-dev
            # Nine requires gcc 4.6... which is the one we have right ?
            - libxvmc-dev
            # Build locally, for now.
@@ -170,6 +182,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Vulkan"
        - BUILD=make
@@ -182,6 +195,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS=""
        - VULKAN_DRIVERS="intel,radeon"
+        - LIBUNWIND_FLAGS="--disable-libunwind"
      addons:
        apt:
          sources:
@@ -359,6 +373,7 @@ script:
      export CC="$CC -isystem`pwd`";

      ./autogen.sh --enable-debug
+        $LIBUNWIND_FLAGS
        $DRI_LOADERS
        --with-dri-drivers=$DRI_DRIVERS
        $GALLIUM_ST
--- a/Makefile.am
+++ b/Makefile.am
@@ -41,6 +41,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-xa \
 	--enable-xvmc \
 	--enable-llvm-shared-libs \
+	--enable-libunwind \
 	--with-platforms=x11,wayland,drm,surfaceless \
 	--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
 	--with-gallium-drivers=i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr,etnaviv,imx \
--- a/2
+++ b/2
@@ -1 +1 @@
-17.1.8
+17.1.10
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -194,7 +194,111 @@ f24cf82d6db290a88abfff0669d2c5e2aa463901 i965/tex: Don't pass samples to miptree
 #         which did not land in branch.
 54c41af0aa92333579a72830254ac3aaa9f4aea1 i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.

-# fixes: Depend on earlier commit 04a40f7d2a that did not land in
+# fixes: Depends on earlier commit 04a40f7d2a that did not land in
 #        branch and which exposes new API.
 3a5e3aa5a53cff55a5e31766d713a41ffa5a93d7 egl/drm: Fix misused x and y offsets in swrast_put_image2()
 fe2a6281b3b299998fe7399e7dbcc2077d773824 egl/drm: Fix misused x and y offsets in swrast_get_image()
+
+# stable: 17.2 nomination only.
+0ac78dc92582a59d4319ebce019b4caa41fb432d util: move string_to_uint_map to glsl
+
+# stable: 17.2 nomination only.
+88cdf16871a0f1cd8ec3844072051ee38e945600 llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSOR
+
+# stable: 17.2 nomination only.
+dc9e08b0c3b04ba77ed59b8700e9f43edccb3168 freedreno: skip batch-cache for compute shaders
+
+# stable: 17.2 nomination only.
+d118ff876559e468d2d243470947eee53171fe57 radv: disable 1d/2d linear optimisation on gfx9.
+
+# stable: 17.2 nomination only.
+6d929d3f85604768971d04fa2548f02ffca1696e radv/gfx9: set descriptor up for base_mip to level range.
+
+# stable: 17.2 nomination only.
+e38685cc62e2a452521c49a3ad09d82495c6b1d0 Revert "radv: disable support for VEGA for now."
+
+# stable: 17.2 nomination only. Depends on earlier commit 43ef75b394f
+#         which did not land in branch.
+63e79a8a777b36ecb30a1f6900e6b638cb32fc5f nir: Fix system_value_from_intrinsic for subgroups
+
+# stable: 17.2 nomination only. Depends on earlier commit f37ede40bad
+#         which did not land in branch.
+52b65dfda84e4d433a332dd84596eef054eb5cbb i965: Fix crash in fallback GTT mapping.
+
+# stable: 17.2 nomination only. Depends on earlier commit 5b62eb237c52
+#         which did not land in branch.
+34124e412f00432ba8b3b8d16e3f2168aa596622 radeonsi/gfx9: always flush DB metadata on framebuffer changes
+
+# fixes: Depends on earlier commit 78bef01da2b that did not land in
+#        branch.
+ff23e03d60d264a64fce340c132404c6070050a0 radv: Fix vkCopyImage with both depth and stencil aspects.
+
+# fixes: References 166823bf but it is not really a bug fix, just an
+#        enhancement.
+45c5c444518b7e83d9accd9f44702fa49282a3b8 radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug
+
+# stable: 17.2 nomination only.
+e4018fdd85d8b58250c2cff8cdf4edd6b2b3c70b st/mesa: skip draw calls with pipe_draw_info::count == 0
+
+# stable: 17.2 nomination only.
+76ac8fafadca86941f2723f7f7176b22112f5c0c radv/winsys: use amdgpu_bo_va_op_raw.
+e8d57802fea60d4b353761ba1bdb08545733c007 radv/gfx9: allocate events from uncached VA space
+
+# stable: 17.2 nomination only.
+219d29e4d83d8c901f127c8a004c45c23c15751e radv: use simpler indirect packet 3 if possible.
+
+# fixes: References 391673af but it is not really a bug fix.
+17dd4856a68621ab7107975df8239fb2963a57bb radeonsi: don't always apply the PrimID instancing bug workaround on SI
+
+# stable: 17.2 nomination only. Depends on earlier commit 4fab67a4415
+#         which did not land in branch.
+d496780fb2c7f2cf0e32b6a79dc528e5156dfcb3 intel/eu/validate: Look up types on demand in execution_type()
+
+# stable: 17.2 nomination only.
+2f5b4490b59062f224e73f7a2d5cc0d8bd8eaa7b radv: don't use iview for meta image width/height.
+1bcb953e16600e0d9329b678a6eacee98d326547 radv: handle GFX9 1D textures
+
+# stable: 17.2 nomination only.
+ebd2a5354df64ef504f1e213afd2d6ab9d69a776 radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
+
+# stable: 17.2 nomination only.
+3633bae36b56a8667d31096b3c3472ab388c4fbf radv/gfx9: fix image resource handling.
+
+# fixes: It only fixes documentation.
+85b66d20969685c26d3f7d22b6fc7b988872fa88 docs/egl: remove reference to EGL_DRIVERS_PATH
+
+# fixes: We don't really want to disable something unless it is
+#        causing a big problem.
+bee83b26611c0a4a554aa37c59187351242e82fd radv: Disable multilayer & multilevel DCC.
+
+# fixes: Depends on earlier commit dfc06d2fac that did not land in
+#        branch.
+1a172fb113554fa03053052b161d5e22fc2fcb1f radv: Don't allocate CMASK for linear images.
+
+# stable: 17.2 nomination only. Depends on earlier commit f187a4932
+#         which did not land in branch.
+cffc0ae0d9e572a82ce88c09e6ee8e2ed2a9be91 ac/surface: match Z and stencil tile config
+
+# stable: 17.2. nomination only.
+64d9bd149aa7f5a09f73cae07499577933722fb2 radv/nir: call opt_remove_phis after trivial continues.
+
+# fixes: Depends on earlier commit 13a28ff2368 that did not land in
+#        branch.
+94736d31c364635a76a11e0bd4f046a42d2221d5 amd/common: add workaround for cube map array layer clamping
+
+# stable: 17.2 nomination only. Depends on earlier commit 5cb2eee557
+#         which did not land in branch.
+6fb0c1013b3578c5bd264efaa99a6d68418ccfb1 radeonsi: workaround for gather4 on integer cube maps
+
+# stable: 17.2 nomination only.
+c1b01370486d203a6bccff2161afb288cfda1de3 Scons: Add LLVM 5.0 support
+
+# stable: 17.2 nomination only.
+c4ac522511d20683c09441a9e96ddfbc1b540c00 ac/surface: handle S8 on gfx9
+
+# fixes:  This commit addressed an earlier commit 1bcb953e166 which did not
+#         land in branch.
+979978ee06867a531b8d56cee252f5c83920a339 radv: Check for GFX9 for 1D arrays in image_size intrinsic.
+
+# This commit is causing several regressions on i965 driver
+15cae12804ef288c7fb4cb9a38f7e32e6d8c4dc1 glsl/linker: fix output variable overlap check
--- a/configure.ac
+++ b/configure.ac
@@ -793,6 +793,27 @@ AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES -DHAVE_SYS_SYSCTL_H"])
 AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
 AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])

+AC_MSG_CHECKING([whether strtod has locale support])
+AC_LINK_IFELSE([AC_LANG_SOURCE([[
+    #define _GNU_SOURCE
+    #include <stdlib.h>
+    #include <locale.h>
+    #ifdef HAVE_XLOCALE_H
+    #include <xlocale.h>
+    #endif
+    int main() {
+       locale_t loc = newlocale(LC_CTYPE_MASK, "C", NULL);
+       const char *s = "1.0";
+       char *end;
+       double d = strtod_l(s, end, loc);
+       float f = strtof_l(s, end, loc);
+       freelocale(loc);
+       return 0;
+    }]])],
+  [DEFINES="$DEFINES -DHAVE_STRTOD_L"];
+   AC_MSG_RESULT([yes]),
+   AC_MSG_RESULT([no]))
+
 dnl Check to see if dlopen is in default libraries (like Solaris, which
 dnl has it in libc), or if libdl is needed to get it.
 AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
--- a/docs/relnotes/17.1.10.html
+++ b/docs/relnotes/17.1.10.html
@@ -0,0 +1,155 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.10 Release Notes / September 25, 2017</h1>
+
+<p>
+Mesa 17.1.10 is a bug fix release which fixes bugs found since the 17.1.9 release.
+</p>
+<p>
+Mesa 17.1.10 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+a48ce6b643a728b2b0f926151930525b3670fbff1fb688527fd9051eab9f30a4  mesa-17.1.10.tar.gz
+cbc0d681cc4df47d8deb5a36f45b420978128522fd665b2cd4c7096316f11bdb  mesa-17.1.10.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102844">Bug 102844</a> - memory leak with glDeleteProgram for shader program type GL_COMPUTE_SHADER</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alexandre Demers (1):</p>
+<ul>
+  <li>osmesa: link with libunwind if enabled (v2)</li>
+</ul>
+
+<p>Andres Gomez (12):</p>
+<ul>
+  <li>docs: add sha256 checksums for 17.1.9</li>
+  <li>cherry-ignore: add "st/mesa: skip draw calls with pipe_draw_info::count == 0"</li>
+  <li>cherry-ignore: add "radv: use amdgpu_bo_va_op_raw."</li>
+  <li>cherry-ignore: add "radv: use simpler indirect packet 3 if possible."</li>
+  <li>cherry-ignore: add "radeonsi: don't always apply the PrimID instancing bug workaround on SI"</li>
+  <li>cherry-ignore: add "intel/eu/validate: Look up types on demand in execution_type()"</li>
+  <li>cherry-ignore: add "radv: gfx9 fixes"</li>
+  <li>cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d arrays/3d images"</li>
+  <li>cherry-ignore: add "radv/gfx9: fix image resource handling."</li>
+  <li>cherry-ignore: add "docs/egl: remove reference to EGL_DRIVERS_PATH"</li>
+  <li>cherry-ignore: add "radv: Disable multilayer &amp; multilevel DCC."</li>
+  <li>cherry-ignore: add "radv: Don't allocate CMASK for linear images."</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+  <li>radv/ac: bump params array for image atomic comp swap</li>
+  <li>st/glsl-&gt;tgsi: fix u64 to bool comparisons.</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+  <li>egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension</li>
+  <li>automake: enable libunwind in `make distcheck'</li>
+</ul>
+
+<p>Eric Anholt (3):</p>
+<ul>
+  <li>broadcom/vc4: Fix use-after-free for flushing when writing to a texture.</li>
+  <li>broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear.</li>
+  <li>broadcom/vc4: Fix use-after-free when deleting a program.</li>
+</ul>
+
+<p>George Kyriazis (1):</p>
+<ul>
+  <li>swr: invalidate attachment on transition change</li>
+</ul>
+
+<p>Gert Wollny (2):</p>
+<ul>
+  <li>travis: force llvm-3.3 for "make Gallium ST Other"</li>
+  <li>travis: Add libunwind-dev to gallium/make builds</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>i965/blorp: Set r8stencil_needs_update when writing stencil</li>
+</ul>
+
+<p>Juan A. Suarez Romero (9):</p>
+<ul>
+  <li>cherry-ignore: add "ac/surface: match Z and stencil tile config"</li>
+  <li>cherry-ignore: add "radv/nir: call opt_remove_phis after trivial continues."</li>
+  <li>cherry-ignore: add "amd/common: add workaround for cube map array layer clamping"</li>
+  <li>cherry-ignore: add "radeonsi: workaround for gather4 on integer cube maps"</li>
+  <li>cherry-ignore: add "Scons: Add LLVM 5.0 support"</li>
+  <li>cherry-ignore: add "ac/surface: handle S8 on gfx9"</li>
+  <li>cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size intrinsic."</li>
+  <li>cherry-ignore: add "glsl/linker: fix output variable overlap check"</li>
+  <li>Update version to 17.1.10</li>
+</ul>
+
+<p>Józef Kucia (1):</p>
+<ul>
+  <li>anv: Fix descriptors copying</li>
+</ul>
+
+<p>Matt Turner (2):</p>
+<ul>
+  <li>util: Link libmesautil into u_atomic_test</li>
+  <li>util/u_atomic: Add implementation of __sync_val_compare_and_swap_8</li>
+</ul>
+
+<p>Nicolai HÃÂ¤hnle (1):</p>
+<ul>
+  <li>radeonsi: apply a mask to gl_SampleMaskIn in the PS prolog</li>
+</ul>
+
+<p>Nicolai Hähnle (4):</p>
+<ul>
+  <li>st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index</li>
+  <li>amd/common: round cube array slice in ac_prepare_cube_coords</li>
+  <li>radeonsi: set MIP_POINT_PRECLAMP to 0</li>
+  <li>radeonsi: fix array textures layer coordinate</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>mesa: free current ComputeProgram state in _mesa_free_context_data</li>
+</ul>
+
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/17.1.8.html
+++ b/docs/relnotes/17.1.8.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+faa59a677e88fd5224cdfebcdb6ca9ad3e3c64bd562baa8d5c3c1faeef1066b6  mesa-17.1.8.tar.gz
+75ed2eaeae26ddd536150f294386468ae2e1a7717948c41cd14b7875be5269db  mesa-17.1.8.tar.xz
 </pre>


--- a/docs/relnotes/17.1.9.html
+++ b/docs/relnotes/17.1.9.html
@@ -0,0 +1,144 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.9 Release Notes / September 8, 2017</h1>
+
+<p>
+Mesa 17.1.9 is a bug fix release which fixes bugs found since the 17.1.8 release.
+</p>
+<p>
+Mesa 17.1.9 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+4325401b07b5f44759da781bc8d7c0a4a7244e09a702d16c037090986e07ee22  mesa-17.1.9.tar.gz
+5f51ad94341696097d5df7b838183534478216858ac0fc8de183671a36ffea1a  mesa-17.1.9.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100613">Bug 100613</a> - Regression in Mesa 17 on s390x (zSystems)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102454">Bug 102454</a> - glibc 2.26 doesn't provide anymore xlocale.h</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102467">Bug 102467</a> - src/mesa/state_tracker/st_cb_readpixels.c:178]: (warning) Redundant assignment</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Andres Gomez (8):</p>
+<ul>
+  <li>docs: add sha256 checksums for 17.1.8</li>
+  <li>cherry-ignore: added 17.2 nominations.</li>
+  <li>cherry-ignore: add "nir: Fix system_value_from_intrinsic for subgroups"</li>
+  <li>cherry-ignore: add "i965: Fix crash in fallback GTT mapping."</li>
+  <li>cherry-ignore: add "radeonsi/gfx9: always flush DB metadata on framebuffer changes"</li>
+  <li>cherry-ignore: add "radv: Fix vkCopyImage with both depth and stencil aspects."</li>
+  <li>cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug"</li>
+  <li>Update version to 17.1.9</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+  <li>radv: Fix off by one in MAX_VBS assert.</li>
+  <li>radv: Fix sparse BO mapping merging.</li>
+  <li>radv: Actually set the cmd_buffer usage_flags.</li>
+</ul>
+
+<p>Ben Crocker (1):</p>
+<ul>
+  <li>llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load</li>
+</ul>
+
+<p>Charmaine Lee (1):</p>
+<ul>
+  <li>vbo: fix offset in minmax cache key</li>
+</ul>
+
+<p>Christian Gmeiner (1):</p>
+<ul>
+  <li>etnaviv: use correct param for etna_compatible_rs_format(..)</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>egl: don't NULL deref the .get_capabilities function pointer</li>
+  <li>egl/wayland: plug leaks in dri2_wl_create_window_surface() error path</li>
+  <li>egl/wayland: polish object teardown in dri2_wl_destroy_surface</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+  <li>util: improve compiler guard</li>
+</ul>
+
+<p>Grazvydas Ignotas (2):</p>
+<ul>
+  <li>radv: clear dynamic_shader_stages on create</li>
+  <li>radv: don't assert on empty hash table</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+  <li>glsl: fix counting of vertex shader output slots used by explicit vars</li>
+  <li>st/mesa: fix handling of vertex array double inputs</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>anv/formats: Nicely handle unknown VkFormat enums</li>
+  <li>spirv: Add support for the HelperInvocation builtin</li>
+</ul>
+
+<p>Karol Herbst (1):</p>
+<ul>
+  <li>nvc0: write 0 to pipeline_statistics.cs_invocations</li>
+</ul>
+
+<p>Michael Olbrich (1):</p>
+<ul>
+  <li>egl/dri2: only destroy created objects</li>
+</ul>
+
+<p>Ray Strode (1):</p>
+<ul>
+  <li>gallivm: correct channel shift logic on big endian</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>st/mesa: fix view template initialization in try_pbo_readpixels</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -146,6 +146,19 @@ def check_cc(env, cc, expr, cpp_opt = '-E'):
    return result


+def check_functions(env, functions):
+    '''Check if all of the functions exist'''
+
+    conf = SCons.Script.Configure(env)
+    have_functions = True
+
+    for function in functions:
+        if not conf.CheckFunc(function):
+            have_functions = False
+
+    env = conf.Finish()
+    return have_functions
+
 def check_prog(env, prog):
    """Check whether this program exists."""

@@ -330,6 +343,9 @@ def generate(env):
            cppdefines += ['HAVE_XLOCALE_H']
        env = conf.Finish()

+        if check_functions(env, ['strtod_l', 'strtof_l']):
+            cppdefines += ['HAVE_STRTOD_L']
+
    if platform == 'windows':
        cppdefines += [
            'WIN32',
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -327,7 +327,7 @@ static void build_cube_select(LLVMBuilderRef builder,

 void
 ac_prepare_cube_coords(struct ac_llvm_context *ctx,
-		       bool is_deriv, bool is_array,
+		       bool is_deriv, bool is_array, bool is_lod,
 		       LLVMValueRef *coords_arg,
 		       LLVMValueRef *derivs_arg)
 {
@@ -337,6 +337,11 @@ ac_prepare_cube_coords(struct ac_llvm_context *ctx,
 	LLVMValueRef coords[3];
 	LLVMValueRef invma;

+	if (is_array && !is_lod) {
+		coords_arg[3] = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32,
+						   &coords_arg[3], 1, 0);
+	}
+
 	build_cube_intrinsic(ctx, coords_arg, &selcoords);

 	invma = ac_build_intrinsic(ctx, "llvm.fabs.f32",
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -82,7 +82,7 @@ ac_build_fdiv(struct ac_llvm_context *ctx,

 void
 ac_prepare_cube_coords(struct ac_llvm_context *ctx,
-		       bool is_deriv, bool is_array,
+		       bool is_deriv, bool is_array, bool is_lod,
 		       LLVMValueRef *coords_arg,
 		       LLVMValueRef *derivs_arg);

--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3355,7 +3355,7 @@ static void visit_image_store(struct nir_to_llvm_context *ctx,
 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
                                       nir_intrinsic_instr *instr)
 {
-	LLVMValueRef params[6];
+	LLVMValueRef params[7];
 	int param_count = 0;
 	const nir_variable *var = instr->variables[0]->var;

@@ -4333,15 +4333,13 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
 	}

 	if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
-		if (instr->is_array && instr->op != nir_texop_lod)
-			coords[3] = apply_round_slice(ctx, coords[3]);
 		for (chan = 0; chan < instr->coord_components; chan++)
 			coords[chan] = to_float(ctx, coords[chan]);
 		if (instr->coord_components == 3)
 			coords[3] = LLVMGetUndef(ctx->f32);
 		ac_prepare_cube_coords(&ctx->ac,
 			instr->op == nir_texop_txd, instr->is_array,
-			coords, derivs);
+			instr->op == nir_texop_lod, coords, derivs);
 		if (num_deriv_comp)
 			num_deriv_comp--;
 	}
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1839,6 +1839,7 @@ VkResult radv_BeginCommandBuffer(

 	memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
 	cmd_buffer->state.last_primitive_reset_en = -1;
+	cmd_buffer->usage_flags = pBeginInfo->flags;

 	/* setup initial configuration into command buffer */
 	if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
@@ -1884,7 +1885,7 @@ void radv_CmdBindVertexBuffers(
 	/* We have to defer setting up vertex buffer since we need the buffer
 	 * stride from the pipeline. */

-	assert(firstBinding + bindingCount < MAX_VBS);
+	assert(firstBinding + bindingCount <= MAX_VBS);
 	for (uint32_t i = 0; i < bindingCount; i++) {
 		vb[firstBinding + i].buffer = radv_buffer_from_handle(pBuffers[i]);
 		vb[firstBinding + i].offset = pOffsets[i];
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -66,6 +66,7 @@ VkResult radv_CreateDescriptorSetLayout(

 	set_layout->binding_count = max_binding + 1;
 	set_layout->shader_stages = 0;
+	set_layout->dynamic_shader_stages = 0;
 	set_layout->size = 0;

 	memset(set_layout->binding, 0, size - sizeof(struct radv_descriptor_set_layout));
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -117,6 +117,9 @@ radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache *cache,
 	const uint32_t mask = cache->table_size - 1;
 	const uint32_t start = (*(uint32_t *) sha1);

+	if (cache->table_size == 0)
+		return NULL;
+
 	for (uint32_t i = 0; i < cache->table_size; i++) {
 		const uint32_t index = (start + i) & mask;
 		struct cache_entry *entry = cache->hash_table[index];
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -149,6 +149,7 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo *_parent,
 	if (parent->ranges[first].bo == bo && (!bo || offset - bo_offset == parent->ranges[first].offset - parent->ranges[first].bo_offset)) {
 		size += offset - parent->ranges[first].offset;
 		offset = parent->ranges[first].offset;
+		bo_offset = parent->ranges[first].bo_offset;
 		remove_first = true;
 	}

--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -2017,7 +2017,8 @@ reserved_varying_slot(struct gl_linked_shader *stage,
      var_slot = var->data.location - VARYING_SLOT_VAR0;

      unsigned num_elements = get_varying_type(var, stage->Stage)
-         ->count_attribute_slots(stage->Stage == MESA_SHADER_VERTEX);
+         ->count_attribute_slots(io_mode == ir_var_shader_in &&
+                                 stage->Stage == MESA_SHADER_VERTEX);
      for (unsigned i = 0; i < num_elements; i++) {
         if (var_slot >= 0 && var_slot < MAX_VARYINGS_INCL_PATCH)
            slots |= UINT64_C(1) << var_slot;
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1004,6 +1004,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
      *location = FRAG_RESULT_DEPTH;
      assert(*mode == nir_var_shader_out);
      break;
+   case SpvBuiltInHelperInvocation:
+      *location = SYSTEM_VALUE_HELPER_INVOCATION;
+      set_mode_system_value(mode);
+      break;
   case SpvBuiltInNumWorkgroups:
      *location = SYSTEM_VALUE_NUM_WORK_GROUPS;
      set_mode_system_value(mode);
@@ -1040,7 +1044,6 @@ vtn_get_builtin_location(struct vtn_builder *b,
      *location = SYSTEM_VALUE_DRAW_ID;
      set_mode_system_value(mode);
      break;
-   case SpvBuiltInHelperInvocation:
   default:
      unreachable("unsupported builtin");
   }
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -681,7 +681,8 @@ dri2_setup_screen(_EGLDisplay *disp)
      disp->Extensions.KHR_wait_sync = EGL_TRUE;
      if (dri2_dpy->fence->get_fence_from_cl_event)
         disp->Extensions.KHR_cl_event2 = EGL_TRUE;
-      if (dri2_dpy->fence->base.version >= 2) {
+      if (dri2_dpy->fence->base.version >= 2 &&
+          dri2_dpy->fence->get_capabilities) {
         unsigned capabilities =
            dri2_dpy->fence->get_capabilities(dri2_dpy->dri_screen);
         disp->Extensions.ANDROID_native_fence_sync =
@@ -935,9 +936,12 @@ dri2_display_release(_EGLDisplay *disp)
          wl_drm_destroy(dri2_dpy->wl_drm);
      if (dri2_dpy->wl_shm)
          wl_shm_destroy(dri2_dpy->wl_shm);
-      wl_registry_destroy(dri2_dpy->wl_registry);
-      wl_event_queue_destroy(dri2_dpy->wl_queue);
-      wl_proxy_wrapper_destroy(dri2_dpy->wl_dpy_wrapper);
+      if (dri2_dpy->wl_registry)
+         wl_registry_destroy(dri2_dpy->wl_registry);
+      if (dri2_dpy->wl_queue)
+         wl_event_queue_destroy(dri2_dpy->wl_queue);
+      if (dri2_dpy->wl_dpy_wrapper)
+         wl_proxy_wrapper_destroy(dri2_dpy->wl_dpy_wrapper);
      if (dri2_dpy->own_device) {
         wl_display_disconnect(dri2_dpy->wl_dpy);
      }
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -174,7 +174,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
   dri2_surf->wl_surface_wrapper = wl_proxy_create_wrapper(window->surface);
   if (!dri2_surf->wl_surface_wrapper) {
      _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
-      goto cleanup_drm;
+      goto cleanup_dpy_wrapper;
   }
   wl_proxy_set_queue((struct wl_proxy *)dri2_surf->wl_surface_wrapper,
                      dri2_surf->wl_queue);
@@ -200,7 +200,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
                                                  dri2_surf);
    if (dri2_surf->dri_drawable == NULL) {
      _eglError(EGL_BAD_ALLOC, "createNewDrawable");
-       goto cleanup_surf;
+       goto cleanup_surf_wrapper;
    }

   dri2_wl_swap_interval(drv, disp, &dri2_surf->base,
@@ -208,6 +208,10 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,

   return &dri2_surf->base;

+ cleanup_surf_wrapper:
+   wl_proxy_wrapper_destroy(dri2_surf->wl_surface_wrapper);
+ cleanup_dpy_wrapper:
+   wl_proxy_wrapper_destroy(dri2_surf->wl_dpy_wrapper);
 cleanup_drm:
   if (dri2_surf->wl_drm_wrapper)
      wl_proxy_wrapper_destroy(dri2_surf->wl_drm_wrapper);
@@ -278,10 +282,10 @@ dri2_wl_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf)
      dri2_surf->wl_win->destroy_window_callback = NULL;
   }

-   if (dri2_surf->wl_drm_wrapper)
-      wl_proxy_wrapper_destroy(dri2_surf->wl_drm_wrapper);
   wl_proxy_wrapper_destroy(dri2_surf->wl_surface_wrapper);
   wl_proxy_wrapper_destroy(dri2_surf->wl_dpy_wrapper);
+   if (dri2_surf->wl_drm_wrapper)
+      wl_proxy_wrapper_destroy(dri2_surf->wl_drm_wrapper);
   wl_event_queue_destroy(dri2_surf->wl_queue);

   free(surf);
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1334,6 +1334,7 @@ static const __DRIextension *dri3_image_loader_extensions[] = {
   &dri3_image_loader_extension.base,
   &image_lookup_extension.base,
   &use_invalidate.base,
+   &background_callable_extension.base,
   NULL,
 };

--- a/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
@@ -650,7 +650,13 @@ lp_build_fetch_rgba_soa(struct gallivm_state *gallivm,
         for (i = 0; i < format_desc->nr_channels; i++) {
            struct util_format_channel_description chan_desc = format_desc->channel[i];
            unsigned blockbits = type.width;
-            unsigned vec_nr = chan_desc.shift / type.width;
+            unsigned vec_nr;
+
+#ifdef PIPE_ARCH_BIG_ENDIAN
+            vec_nr = (format_desc->block.bits - (chan_desc.shift + chan_desc.size)) / type.width;
+#else
+            vec_nr = chan_desc.shift / type.width;
+#endif
            chan_desc.shift %= type.width;

            output[i] = lp_build_extract_soa_chan(&bld,
--- a/src/gallium/auxiliary/gallivm/lp_bld_gather.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_gather.c
@@ -234,13 +234,39 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm,
          */
         res = LLVMBuildZExt(gallivm->builder, res, dst_elem_type, "");

-         if (vector_justify) {
 #ifdef PIPE_ARCH_BIG_ENDIAN
+         if (vector_justify) {
         res = LLVMBuildShl(gallivm->builder, res,
                            LLVMConstInt(dst_elem_type,
                                         dst_type.width - src_width, 0), "");
-#endif
         }
+         if (src_width == 48) {
+            /* Load 3x16 bit vector.
+             * The sequence of loads on big-endian hardware proceeds as follows.
+             * 16-bit fields are denoted by X, Y, Z, and 0.  In memory, the sequence
+             * of three fields appears in the order X, Y, Z.
+             *
+             * Load 32-bit word: 0.0.X.Y
+             * Load 16-bit halfword: 0.0.0.Z
+             * Rotate left: 0.X.Y.0
+             * Bitwise OR: 0.X.Y.Z
+             *
+             * The order in which we need the fields in the result is 0.Z.Y.X,
+             * the same as on little-endian; permute 16-bit fields accordingly
+             * within 64-bit register:
+             */
+            LLVMValueRef shuffles[4] = {
+               lp_build_const_int32(gallivm, 2),
+               lp_build_const_int32(gallivm, 1),
+               lp_build_const_int32(gallivm, 0),
+               lp_build_const_int32(gallivm, 3),
+            };
+            res = LLVMBuildBitCast(gallivm->builder, res,
+                                   lp_build_vec_type(gallivm, lp_type_uint_vec(16, 4*16)), "");
+            res = LLVMBuildShuffleVector(gallivm->builder, res, res, LLVMConstVector(shuffles, 4), "");
+            res = LLVMBuildBitCast(gallivm->builder, res, dst_elem_type, "");
+         }
+#endif
      }
   }
   return res;
--- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
@@ -398,7 +398,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
   }

   unsigned src_format = etna_compatible_rs_format(blit_info->src.format);
-   unsigned dst_format = etna_compatible_rs_format(blit_info->src.format);
+   unsigned dst_format = etna_compatible_rs_format(blit_info->dst.format);
   if (translate_rs_format(src_format) == ETNA_NO_MATCH ||
       translate_rs_format(dst_format) == ETNA_NO_MATCH ||
       blit_info->scissor_enable || blit_info->src.box.x != 0 ||
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
@@ -346,6 +346,7 @@ nvc0_hw_get_query_result(struct nvc0_context *nvc0, struct nvc0_query *q,
   case PIPE_QUERY_PIPELINE_STATISTICS:
      for (i = 0; i < 10; ++i)
         res64[i] = data64[i * 2] - data64[24 + i * 2];
+      result->pipeline_statistics.cs_invocations = 0;
      break;
   case NVC0_HW_QUERY_TFB_BUFFER_OFFSET:
      res32[0] = hq->data[1];
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -85,10 +85,10 @@ static void si_build_ps_prolog_function(struct si_shader_context *ctx,
 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
 					union si_shader_part_key *key);

-/* Ideally pass the sample mask input to the PS epilog as v13, which
+/* Ideally pass the sample mask input to the PS epilog as v14, which
 * is its usual location, so that the shader doesn't have to add v_mov.
 */
-#define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
+#define PS_EPILOG_SAMPLEMASK_MIN_LOC 14

 /* The VS location of the PrimitiveID input is the same in the epilog,
 * so that the main shader part doesn't have to move it.
@@ -4655,12 +4655,22 @@ static void tex_fetch_args(
 	if (target == TGSI_TEXTURE_CUBE ||
 	    target == TGSI_TEXTURE_CUBE_ARRAY ||
 	    target == TGSI_TEXTURE_SHADOWCUBE ||
-	    target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
+	    target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 		ac_prepare_cube_coords(&ctx->ac,
 				       opcode == TGSI_OPCODE_TXD,
 				       target == TGSI_TEXTURE_CUBE_ARRAY ||
 				       target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
+				       opcode == TGSI_OPCODE_LODQ,
 				       coords, derivs);
+	} else if (tgsi_is_array_sampler(target) &&
+		   opcode != TGSI_OPCODE_TXF &&
+		   opcode != TGSI_OPCODE_TXF_LZ &&
+		   ctx->screen->b.chip_class <= VI) {
+		unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
+		coords[array_coord] =
+			ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
+					   &coords[array_coord], 1, 0);
+	}

 	if (opcode == TGSI_OPCODE_TXD)
 		for (int i = 0; i < num_deriv_channels * 2; i++)
@@ -5809,6 +5819,7 @@ static void create_function(struct si_shader_context *ctx)
 		params[SI_PARAM_FRONT_FACE] = ctx->i32;
 		shader->info.face_vgpr_index = 20;
 		params[SI_PARAM_ANCILLARY] = ctx->i32;
+		shader->info.ancillary_vgpr_index = 21;
 		params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
 		params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
 		num_params = SI_PARAM_POS_FIXED_PT+1;
@@ -5876,6 +5887,7 @@ static void create_function(struct si_shader_context *ctx)
 				      S_0286D0_LINEAR_CENTER_ENA(1) |
 				      S_0286D0_LINEAR_CENTROID_ENA(1) |
 				      S_0286D0_FRONT_FACE_ENA(1) |
+				      S_0286D0_ANCILLARY_ENA(1) |
 				      S_0286D0_POS_FIXED_PT_ENA(1));
 	} else if (ctx->type == PIPE_SHADER_COMPUTE) {
 		si_llvm_add_attribute(ctx->main_fn,
@@ -7145,6 +7157,7 @@ static void si_get_ps_prolog_key(struct si_shader *shader,
 		 key->ps_prolog.states.force_linear_center_interp ||
 		 key->ps_prolog.states.bc_optimize_for_persp ||
 		 key->ps_prolog.states.bc_optimize_for_linear);
+	key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;

 	if (info->colors_read) {
 		unsigned *color = shader->selector->color_attr_index;
@@ -7254,7 +7267,8 @@ static bool si_need_ps_prolog(const union si_shader_part_key *key)
 	       key->ps_prolog.states.force_linear_center_interp ||
 	       key->ps_prolog.states.bc_optimize_for_persp ||
 	       key->ps_prolog.states.bc_optimize_for_linear ||
-	       key->ps_prolog.states.poly_stipple;
+	       key->ps_prolog.states.poly_stipple ||
+	       key->ps_prolog.states.samplemask_log_ps_iter;
 }

 /**
@@ -7720,6 +7734,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 	if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		shader->info.num_input_vgprs = 0;
 		shader->info.face_vgpr_index = -1;
+		shader->info.ancillary_vgpr_index = -1;

 		if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
 			shader->info.num_input_vgprs += 2;
@@ -7749,8 +7764,10 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 			shader->info.face_vgpr_index = shader->info.num_input_vgprs;
 			shader->info.num_input_vgprs += 1;
 		}
-		if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
+		if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
+			shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
 			shader->info.num_input_vgprs += 1;
+		}
 		if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
 			shader->info.num_input_vgprs += 1;
 		if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
@@ -8395,6 +8412,54 @@ static void si_build_ps_prolog_function(struct si_shader_context *ctx,
 		}
 	}

+	/* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
+	 * says:
+	 *
+	 *    "When per-sample shading is active due to the use of a fragment
+	 *     input qualified by sample or due to the use of the gl_SampleID
+	 *     or gl_SamplePosition variables, only the bit for the current
+	 *     sample is set in gl_SampleMaskIn. When state specifies multiple
+	 *     fragment shader invocations for a given fragment, the sample
+	 *     mask for any single fragment shader invocation may specify a
+	 *     subset of the covered samples for the fragment. In this case,
+	 *     the bit corresponding to each covered sample will be set in
+	 *     exactly one fragment shader invocation."
+	 *
+	 * The samplemask loaded by hardware is always the coverage of the
+	 * entire pixel/fragment, so mask bits out based on the sample ID.
+	 */
+	if (key->ps_prolog.states.samplemask_log_ps_iter) {
+		/* The bit pattern matches that used by fixed function fragment
+		 * processing. */
+		static const uint16_t ps_iter_masks[] = {
+			0xffff, /* not used */
+			0x5555,
+			0x1111,
+			0x0101,
+			0x0001,
+		};
+		assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
+
+		uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
+		unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
+					  key->ps_prolog.ancillary_vgpr_index;
+		LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
+		LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
+
+		samplemask = LLVMBuildBitCast(gallivm->builder, samplemask, ctx->i32, "");
+		samplemask = LLVMBuildAnd(
+			gallivm->builder,
+			samplemask,
+			LLVMBuildShl(gallivm->builder,
+				     LLVMConstInt(ctx->i32, ps_iter_mask, false),
+				     sampleid, ""),
+			"");
+		samplemask = LLVMBuildBitCast(gallivm->builder, samplemask, ctx->f32, "");
+
+		ret = LLVMBuildInsertValue(gallivm->builder, ret, samplemask,
+					   ancillary_vgpr + 1, "");
+	}
+
 	/* Tell LLVM to insert WQM instruction sequence when needed. */
 	if (key->ps_prolog.wqm) {
 		LLVMAddTargetDependentFunctionAttr(func,
@@ -8592,6 +8657,12 @@ static bool si_shader_select_ps_parts(struct si_screen *sscreen,
 		assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
 	}

+	/* Samplemask fixup requires the sample ID. */
+	if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
+		shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
+		assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
+	}
+
 	/* The sample mask input is always enabled, because the API shader always
 	 * passes it through to the epilog. Disable it here if it's unused.
 	 */
@@ -8669,6 +8740,7 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 		shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
 		shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
 		shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
+		shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
 		memcpy(shader->info.vs_output_param_offset,
 		       mainp->info.vs_output_param_offset,
 		       sizeof(mainp->info.vs_output_param_offset));
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -371,6 +371,7 @@ struct si_ps_prolog_bits {
 	unsigned	force_linear_center_interp:1;
 	unsigned	bc_optimize_for_persp:1;
 	unsigned	bc_optimize_for_linear:1;
+	unsigned	samplemask_log_ps_iter:3;
 };

 /* Common PS bits between the shader key and the epilog key. */
@@ -409,6 +410,7 @@ union si_shader_part_key {
 		unsigned	colors_read:8; /* color input components read */
 		unsigned	num_interp_inputs:5; /* BCOLOR is at this location */
 		unsigned	face_vgpr_index:5;
+		unsigned	ancillary_vgpr_index:5;
 		unsigned	wqm:1;
 		char		color_attr_index[2];
 		char		color_interp_vgpr_index[2]; /* -1 == constant */
@@ -503,7 +505,8 @@ struct si_shader_info {
 	ubyte			vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 	ubyte			num_input_sgprs;
 	ubyte			num_input_vgprs;
-	char			face_vgpr_index;
+	signed char		face_vgpr_index;
+	signed char		ancillary_vgpr_index;
 	bool			uses_instanceid;
 	ubyte			nr_pos_exports;
 	ubyte			nr_param_exports;
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3613,7 +3613,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
 			  S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
 			  S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
 			  S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
-			  S_008F38_MIP_POINT_PRECLAMP(1) |
+			  S_008F38_MIP_POINT_PRECLAMP(0) |
 			  S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
 			  S_008F38_FILTER_PREC_FIX(1) |
 			  S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1154,6 +1154,12 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
 							     sctx->framebuffer.nr_samples <= 1;
 			key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;

+			if (sctx->ps_iter_samples > 1 &&
+			    sel->info.reads_samplemask) {
+				key->part.ps.prolog.samplemask_log_ps_iter =
+					util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
+			}
+
 			if (rs->force_persample_interp &&
 			    rs->multisample_enable &&
 			    sctx->framebuffer.nr_samples > 1 &&
--- a/src/gallium/drivers/swr/swr_draw.cpp
+++ b/src/gallium/drivers/swr/swr_draw.cpp
@@ -210,6 +210,25 @@ swr_finish(struct pipe_context *pipe)
   swr_fence_reference(pipe->screen, &fence, NULL);
 }

+/*
+ * Invalidate tiles so they can be reloaded back when needed
+ */
+void
+swr_invalidate_render_target(struct pipe_context *pipe,
+                             uint32_t attachment,
+                             uint16_t width, uint16_t height)
+{
+   struct swr_context *ctx = swr_context(pipe);
+
+   /* grab the rect from the passed in arguments */
+   swr_update_draw_context(ctx);
+   SWR_RECT full_rect =
+      {0, 0, (int32_t)width, (int32_t)height};
+   SwrInvalidateTiles(ctx->swrContext,
+                      1 << attachment,
+                      full_rect);
+}
+

 /*
 * Store SWR HotTiles back to renderTarget surface.
--- a/src/gallium/drivers/swr/swr_resource.h
+++ b/src/gallium/drivers/swr/swr_resource.h
@@ -96,6 +96,10 @@ swr_resource_data(struct pipe_resource *resource)
 }


+void swr_invalidate_render_target(struct pipe_context *pipe,
+                                  uint32_t attachment,
+                                  uint16_t width, uint16_t height);
+
 void swr_store_render_target(struct pipe_context *pipe,
                             uint32_t attachment,
                             enum SWR_TILE_STATE post_tile_state);
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -948,6 +948,11 @@ swr_change_rt(struct swr_context *ctx,
       * INVALID so they are reloaded from surface. */
      swr_store_render_target(&ctx->pipe, attachment, SWR_TILE_INVALID);
      need_fence = true;
+   } else {
+      /* if no previous attachment, invalidate tiles that may be marked
+       * RESOLVED because of an old attachment */
+      swr_invalidate_render_target(&ctx->pipe, attachment, sf->width, sf->height);
+      /* no need to set fence here */
   }

   /* Make new attachment */
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -495,6 +495,37 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
        struct vc4_context *vc4 = vc4_context(pctx);
        struct vc4_job *job = vc4_get_job_for_fbo(vc4);

+        if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+                struct vc4_resource *rsc =
+                        vc4_resource(vc4->framebuffer.zsbuf->texture);
+                unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
+
+                /* Clearing ZS will clear both Z and stencil, so if we're
+                 * trying to clear just one then we need to draw a quad to do
+                 * it instead.  We need to do this before setting up
+                 * tile-based clears in vc4->job, because the blitter may
+                 * submit the current job.
+                 */
+                if ((zsclear == PIPE_CLEAR_DEPTH ||
+                     zsclear == PIPE_CLEAR_STENCIL) &&
+                    (rsc->initialized_buffers & ~(zsclear | job->cleared)) &&
+                    util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) {
+                        perf_debug("Partial clear of Z+stencil buffer, "
+                                   "drawing a quad instead of fast clearing\n");
+                        vc4_blitter_save(vc4);
+                        util_blitter_clear(vc4->blitter,
+                                           vc4->framebuffer.width,
+                                           vc4->framebuffer.height,
+                                           1,
+                                           zsclear,
+                                           NULL, depth, stencil);
+                        buffers &= ~zsclear;
+                        if (!buffers)
+                                return;
+                        job = vc4_get_job_for_fbo(vc4);
+                }
+        }
+
        /* We can't flag new buffers for clearing once we've queued draws.  We
         * could avoid this by using the 3d engine to clear.
         */
@@ -530,29 +561,6 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
        if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
                struct vc4_resource *rsc =
                        vc4_resource(vc4->framebuffer.zsbuf->texture);
-                unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
-
-                /* Clearing ZS will clear both Z and stencil, so if we're
-                 * trying to clear just one then we need to draw a quad to do
-                 * it instead.
-                 */
-                if ((zsclear == PIPE_CLEAR_DEPTH ||
-                     zsclear == PIPE_CLEAR_STENCIL) &&
-                    (rsc->initialized_buffers & ~(zsclear | job->cleared)) &&
-                    util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) {
-                        perf_debug("Partial clear of Z+stencil buffer, "
-                                   "drawing a quad instead of fast clearing\n");
-                        vc4_blitter_save(vc4);
-                        util_blitter_clear(vc4->blitter,
-                                           vc4->framebuffer.width,
-                                           vc4->framebuffer.height,
-                                           1,
-                                           zsclear,
-                                           NULL, depth, stencil);
-                        buffers &= ~zsclear;
-                        if (!buffers)
-                                return;
-                }

                /* Though the depth buffer is stored with Z in the high 24,
                 * for this field we just need to store it in the low 24.
@@ -564,7 +572,7 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
                if (buffers & PIPE_CLEAR_STENCIL)
                        job->clear_stencil = stencil;

-                rsc->initialized_buffers |= zsclear;
+                rsc->initialized_buffers |= (buffers & PIPE_CLEAR_DEPTHSTENCIL);
        }

        job->draw_min_x = 0;
--- a/src/gallium/drivers/vc4/vc4_job.c
+++ b/src/gallium/drivers/vc4/vc4_job.c
@@ -117,12 +117,17 @@ vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
                struct vc4_job *job = entry->data;

                struct vc4_bo **referenced_bos = job->bo_pointers.base;
+                bool found = false;
                for (int i = 0; i < cl_offset(&job->bo_handles) / 4; i++) {
                        if (referenced_bos[i] == rsc->bo) {
-                                vc4_job_submit(vc4, job);
-                                continue;
+                                found = true;
+                                break;
                        }
                }
+                if (found) {
+                        vc4_job_submit(vc4, job);
+                        continue;
+                }

                /* Also check for the Z/color buffers, since the references to
                 * those are only added immediately before submit.
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2763,11 +2763,11 @@ vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
        vc4->dirty |= VC4_DIRTY_COMPILED_FS;

        if (vc4->rasterizer->base.flatshade &&
-            old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
+            (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
                vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
        }

-        if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
+        if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
                vc4->dirty |= VC4_DIRTY_FS_INPUTS;
 }

@@ -2877,6 +2877,7 @@ fs_inputs_compare(const void *key1, const void *key2)

 static void
 delete_from_cache_if_matches(struct hash_table *ht,
+                             struct vc4_compiled_shader **last_compile,
                             struct hash_entry *entry,
                             struct vc4_uncompiled_shader *so)
 {
@@ -2886,6 +2887,10 @@ delete_from_cache_if_matches(struct hash_table *ht,
                struct vc4_compiled_shader *shader = entry->data;
                _mesa_hash_table_remove(ht, entry);
                vc4_bo_unreference(&shader->bo);
+
+                if (shader == *last_compile)
+                        *last_compile = NULL;
+
                ralloc_free(shader);
        }
 }
@@ -2897,10 +2902,14 @@ vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
        struct vc4_uncompiled_shader *so = hwcso;

        struct hash_entry *entry;
-        hash_table_foreach(vc4->fs_cache, entry)
-                delete_from_cache_if_matches(vc4->fs_cache, entry, so);
-        hash_table_foreach(vc4->vs_cache, entry)
-                delete_from_cache_if_matches(vc4->vs_cache, entry, so);
+        hash_table_foreach(vc4->fs_cache, entry) {
+                delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
+                                             entry, so);
+        }
+        hash_table_foreach(vc4->vs_cache, entry) {
+                delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
+                                             entry, so);
+        }

        ralloc_free(so->base.ir.nir);
        free(so);
--- a/src/gallium/targets/osmesa/Makefile.am
+++ b/src/gallium/targets/osmesa/Makefile.am
@@ -66,7 +66,8 @@ lib@OSMESA_LIB@_la_LIBADD = \
 	$(top_builddir)/src/mapi/glapi/libglapi.la \
 	$(SHARED_GLAPI_LIB) \
 	$(OSMESA_LIB_DEPS) \
-	$(CLOCK_LIB)
+	$(CLOCK_LIB) \
+	$(LIBUNWIND_LIBS)

 if HAVE_GALLIUM_LLVM
 AM_CPPFLAGS += -DGALLIUM_LLVMPIPE
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -767,7 +767,7 @@ void anv_UpdateDescriptorSets(

   for (uint32_t i = 0; i < descriptorCopyCount; i++) {
      const VkCopyDescriptorSet *copy = &pDescriptorCopies[i];
-      ANV_FROM_HANDLE(anv_descriptor_set, src, copy->dstSet);
+      ANV_FROM_HANDLE(anv_descriptor_set, src, copy->srcSet);
      ANV_FROM_HANDLE(anv_descriptor_set, dst, copy->dstSet);

      const struct anv_descriptor_set_binding_layout *src_layout =
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -251,6 +251,15 @@ static const struct anv_format anv_formats[] = {

 #undef fmt

+static bool
+format_supported(VkFormat vk_format)
+{
+   if (vk_format >= ARRAY_SIZE(anv_formats))
+      return false;
+
+   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
+}
+
 /**
 * Exactly one bit must be set in \a aspect.
 */
@@ -258,10 +267,10 @@ struct anv_format
 anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
               VkImageAspectFlags aspect, VkImageTiling tiling)
 {
-   struct anv_format format = anv_formats[vk_format];
+   if (!format_supported(vk_format))
+      return anv_formats[VK_FORMAT_UNDEFINED];

-   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
-      return format;
+   struct anv_format format = anv_formats[vk_format];

   if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
      assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -397,7 +406,7 @@ anv_physical_device_get_format_properties(struct anv_physical_device *physical_d
      gen += 5;

   VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;
-   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED) {
+   if (!format_supported(format)) {
      /* Nothing to do here */
   } else if (vk_format_is_depth_or_stencil(format)) {
      tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
@@ -495,7 +504,7 @@ anv_get_image_format_properties(
   uint32_t maxArraySize;
   VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT;

-   if (anv_formats[info->format].isl_format == ISL_FORMAT_UNSUPPORTED)
+   if (!format_supported(info->format))
      goto unsupported;

   anv_physical_device_get_format_properties(physical_device, info->format,
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -147,6 +147,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
                       unsigned start_layer, unsigned num_layers,
                       struct isl_surf tmp_surfs[2])
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
       mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
      const unsigned num_samples = MAX2(1, mt->num_samples);
@@ -192,6 +194,10 @@ blorp_surf_for_miptree(struct brw_context *brw,
   struct isl_surf *aux_surf = &tmp_surfs[1];
   intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);

+   if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
+       devinfo->gen <= 7)
+      mt->r8stencil_needs_update = true;
+
   if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
      if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
         /* If we're not going to use it as a depth buffer, resolve HiZ */
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1312,6 +1312,8 @@ _mesa_free_context_data( struct gl_context *ctx )
   _mesa_reference_program(ctx, &ctx->FragmentProgram._Current, NULL);
   _mesa_reference_program(ctx, &ctx->FragmentProgram._TexEnvProgram, NULL);

+   _mesa_reference_program(ctx, &ctx->ComputeProgram._Current, NULL);
+
   _mesa_reference_vao(ctx, &ctx->Array.VAO, NULL);
   _mesa_reference_vao(ctx, &ctx->Array.DefaultVAO, NULL);

--- a/src/mesa/state_tracker/st_cb_readpixels.c
+++ b/src/mesa/state_tracker/st_cb_readpixels.c
@@ -175,7 +175,7 @@ try_pbo_readpixels(struct st_context *st, struct st_renderbuffer *strb,

      if (view_target != PIPE_TEXTURE_3D) {
         templ.u.tex.first_layer = surface->u.tex.first_layer;
-         templ.u.tex.last_layer = templ.u.tex.last_layer;
+         templ.u.tex.last_layer = templ.u.tex.first_layer;
      } else {
         addr.constants.layer_offset = surface->u.tex.first_layer;
      }
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -445,6 +445,7 @@ public:
   st_src_reg st_src_reg_for_double(double val);
   st_src_reg st_src_reg_for_float(float val);
   st_src_reg st_src_reg_for_int(int val);
+   st_src_reg st_src_reg_for_int64(int64_t val);
   st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);

   /**
@@ -1211,6 +1212,19 @@ glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
   return src;
 }

+st_src_reg
+glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
+{
+   st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
+   union gl_constant_value uval[2];
+
+   memcpy(uval, &val, sizeof(uval));
+   src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
+   src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
+
+   return src;
+}
+
 st_src_reg
 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
 {
@@ -2459,7 +2473,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
      break;
   }
   case ir_unop_i642b:
-      emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int(0));
+      emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int64(0));
      break;
   case ir_unop_i642f:
      emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
@@ -2748,7 +2762,9 @@ glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)

   this->result = st_src_reg(entry->file, entry->index, var->type,
                             entry->component, entry->array_id);
-   if (this->shader->Stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in && var->type->is_double())
+   if (this->shader->Stage == MESA_SHADER_VERTEX &&
+       var->data.mode == ir_var_shader_in &&
+       var->type->without_array()->is_double())
      this->result.is_double_vertex_input = true;
   if (!native_integers)
      this->result.type = GLSL_TYPE_FLOAT;
@@ -2838,7 +2854,7 @@ glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
   ir->array->accept(this);
   src = this->result;

-   if (ir->array->ir_type != ir_type_dereference_array) {
+   if (!src.has_index2) {
      switch (this->prog->Target) {
      case GL_TESS_CONTROL_PROGRAM_NV:
         is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
--- a/src/mesa/vbo/vbo_minmax_index.c
+++ b/src/mesa/vbo/vbo_minmax_index.c
@@ -244,6 +244,7 @@ vbo_get_minmax_index(struct gl_context *ctx,
   const int index_size = vbo_sizeof_ib_type(ib->type);
   const char *indices;
   GLuint i;
+   GLintptr offset = 0;

   indices = (char *) ib->ptr + prim->start * index_size;
   if (_mesa_is_bufferobj(ib->obj)) {
@@ -253,7 +254,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
                                min_index, max_index))
         return;

-      indices = ctx->Driver.MapBufferRange(ctx, (GLintptr) indices, size,
+      offset = (GLintptr) indices;
+      indices = ctx->Driver.MapBufferRange(ctx, offset, size,
                                           GL_MAP_READ_BIT, ib->obj,
                                           MAP_INTERNAL);
   }
@@ -336,8 +338,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
   }

   if (_mesa_is_bufferobj(ib->obj)) {
-      vbo_minmax_cache_store(ctx, ib->obj, ib->type, prim->start, count,
-                             *min_index, *max_index);
+      vbo_minmax_cache_store(ctx, ib->obj, ib->type, offset,
+                             count, *min_index, *max_index);
      ctx->Driver.UnmapBuffer(ctx, ib->obj, MAP_INTERNAL);
   }
 }
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -48,6 +48,7 @@ libmesautil_la_LIBADD = \
 	$(CLOCK_LIB) \
 	$(ZLIB_LIBS)

+u_atomic_test_LDADD = libmesautil.la
 roundeven_test_LDADD = -lm

 check_PROGRAMS = u_atomic_test roundeven_test
--- a/src/util/strtod.c
+++ b/src/util/strtod.c
@@ -26,12 +26,12 @@

 #include <stdlib.h>

-#ifdef _GNU_SOURCE
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
 #include <locale.h>
 #ifdef HAVE_XLOCALE_H
 #include <xlocale.h>
-static locale_t loc;
 #endif
+static locale_t loc;
 #endif

 #include "strtod.h"
@@ -40,7 +40,7 @@ static locale_t loc;
 void
 _mesa_locale_init(void)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
   loc = newlocale(LC_CTYPE_MASK, "C", NULL);
 #endif
 }
@@ -48,7 +48,7 @@ _mesa_locale_init(void)
 void
 _mesa_locale_fini(void)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
   freelocale(loc);
 #endif
 }
@@ -60,7 +60,7 @@ _mesa_locale_fini(void)
 double
 _mesa_strtod(const char *s, char **end)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
   return strtod_l(s, end, loc);
 #else
   return strtod(s, end);
@@ -75,7 +75,7 @@ _mesa_strtod(const char *s, char **end)
 float
 _mesa_strtof(const char *s, char **end)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
   return strtof_l(s, end, loc);
 #elif defined(HAVE_STRTOF)
   return strtof(s, end);
--- a/src/util/u_atomic.c
+++ b/src/util/u_atomic.c
@@ -60,6 +60,20 @@ __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
   return r;
 }

+WEAK uint64_t
+__sync_val_compare_and_swap_8(uint64_t *ptr, uint64_t oldval, uint64_t newval)
+{
+   uint64_t r;
+
+   pthread_mutex_lock(&sync_mutex);
+   r = *ptr;
+   if (*ptr == oldval)
+      *ptr = newval;
+   pthread_mutex_unlock(&sync_mutex);
+
+   return r;
+}
+
 WEAK uint64_t
 __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
 {
@@ -1 +1 @@
 .1.8
 .1.10