docs: add sha256 checksums for 17.1.10

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
docs: add release notes for 17.1.10
2017-09-25 17:00:35 +00:00 · 2017-09-25 15:18:34 +00:00 · 2017-09-25 15:11:05 +00:00 · 2017-09-21 09:29:27 +02:00 · 2017-09-21 09:29:27 +02:00 · 2017-09-20 22:54:12 +02:00
27 changed files with 462 additions and 51 deletions
--- a/.travis.yml
+++ b/.travis.yml
@@ -38,6 +38,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS=""
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--disable-libunwind"
      addons:
        apt:
          packages:
@@ -62,6 +63,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS="swr"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -77,6 +79,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Gallium Drivers Other"
        - BUILD=make
@@ -89,6 +92,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS="i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -104,6 +108,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        # NOTE: Analogous to SWR above, building Clover is quite slow.
        - LABEL="make Gallium ST Clover"
@@ -121,6 +126,7 @@ matrix:
        # Regardless - we're doing a quick build test here.
        - GALLIUM_DRIVERS="i915"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          sources:
@@ -140,11 +146,14 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Gallium ST Other"
        - BUILD=make
        - MAKEFLAGS="-j4"
        - MAKE_CHECK_COMMAND="true"
+        - LLVM_VERSION=3.3
+        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
        - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
        - DRI_DRIVERS=""
        - GALLIUM_ST="--enable-dri --disable-opencl --enable-xa --enable-nine --enable-xvmc --enable-vdpau --enable-va --enable-omx --enable-gallium-osmesa"
@@ -153,9 +162,12 @@ matrix:
        # Regardless - we're doing a quick build test here.
        - GALLIUM_DRIVERS="i915,swrast"
        - VULKAN_DRIVERS=""
+        - LIBUNWIND_FLAGS="--enable-libunwind"
      addons:
        apt:
          packages:
+            # We actually want to test against llvm-3.3
+            - llvm-3.3-dev
            # Nine requires gcc 4.6... which is the one we have right ?
            - libxvmc-dev
            # Build locally, for now.
@@ -170,6 +182,7 @@ matrix:
            - libexpat1-dev
            - libx11-xcb-dev
            - libelf-dev
+            - libunwind8-dev
    - env:
        - LABEL="make Vulkan"
        - BUILD=make
@@ -182,6 +195,7 @@ matrix:
        - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
        - GALLIUM_DRIVERS=""
        - VULKAN_DRIVERS="intel,radeon"
+        - LIBUNWIND_FLAGS="--disable-libunwind"
      addons:
        apt:
          sources:
@@ -359,6 +373,7 @@ script:
      export CC="$CC -isystem`pwd`";

      ./autogen.sh --enable-debug
+        $LIBUNWIND_FLAGS
        $DRI_LOADERS
        --with-dri-drivers=$DRI_DRIVERS
        $GALLIUM_ST
--- a/Makefile.am
+++ b/Makefile.am
@@ -41,6 +41,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-xa \
 	--enable-xvmc \
 	--enable-llvm-shared-libs \
+	--enable-libunwind \
 	--with-platforms=x11,wayland,drm,surfaceless \
 	--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
 	--with-gallium-drivers=i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr,etnaviv,imx \
--- a/2
+++ b/2
@@ -1 +1 @@
-17.1.9
+17.1.10
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -236,3 +236,69 @@ ff23e03d60d264a64fce340c132404c6070050a0 radv: Fix vkCopyImage with both depth a
 # fixes: References 166823bf but it is not really a bug fix, just an
 #        enhancement.
 45c5c444518b7e83d9accd9f44702fa49282a3b8 radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug
+
+# stable: 17.2 nomination only.
+e4018fdd85d8b58250c2cff8cdf4edd6b2b3c70b st/mesa: skip draw calls with pipe_draw_info::count == 0
+
+# stable: 17.2 nomination only.
+76ac8fafadca86941f2723f7f7176b22112f5c0c radv/winsys: use amdgpu_bo_va_op_raw.
+e8d57802fea60d4b353761ba1bdb08545733c007 radv/gfx9: allocate events from uncached VA space
+
+# stable: 17.2 nomination only.
+219d29e4d83d8c901f127c8a004c45c23c15751e radv: use simpler indirect packet 3 if possible.
+
+# fixes: References 391673af but it is not really a bug fix.
+17dd4856a68621ab7107975df8239fb2963a57bb radeonsi: don't always apply the PrimID instancing bug workaround on SI
+
+# stable: 17.2 nomination only. Depends on earlier commit 4fab67a4415
+#         which did not land in branch.
+d496780fb2c7f2cf0e32b6a79dc528e5156dfcb3 intel/eu/validate: Look up types on demand in execution_type()
+
+# stable: 17.2 nomination only.
+2f5b4490b59062f224e73f7a2d5cc0d8bd8eaa7b radv: don't use iview for meta image width/height.
+1bcb953e16600e0d9329b678a6eacee98d326547 radv: handle GFX9 1D textures
+
+# stable: 17.2 nomination only.
+ebd2a5354df64ef504f1e213afd2d6ab9d69a776 radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
+
+# stable: 17.2 nomination only.
+3633bae36b56a8667d31096b3c3472ab388c4fbf radv/gfx9: fix image resource handling.
+
+# fixes: It only fixes documentation.
+85b66d20969685c26d3f7d22b6fc7b988872fa88 docs/egl: remove reference to EGL_DRIVERS_PATH
+
+# fixes: We don't really want to disable something unless it is
+#        causing a big problem.
+bee83b26611c0a4a554aa37c59187351242e82fd radv: Disable multilayer & multilevel DCC.
+
+# fixes: Depends on earlier commit dfc06d2fac that did not land in
+#        branch.
+1a172fb113554fa03053052b161d5e22fc2fcb1f radv: Don't allocate CMASK for linear images.
+
+# stable: 17.2 nomination only. Depends on earlier commit f187a4932
+#         which did not land in branch.
+cffc0ae0d9e572a82ce88c09e6ee8e2ed2a9be91 ac/surface: match Z and stencil tile config
+
+# stable: 17.2. nomination only.
+64d9bd149aa7f5a09f73cae07499577933722fb2 radv/nir: call opt_remove_phis after trivial continues.
+
+# fixes: Depends on earlier commit 13a28ff2368 that did not land in
+#        branch.
+94736d31c364635a76a11e0bd4f046a42d2221d5 amd/common: add workaround for cube map array layer clamping
+
+# stable: 17.2 nomination only. Depends on earlier commit 5cb2eee557
+#         which did not land in branch.
+6fb0c1013b3578c5bd264efaa99a6d68418ccfb1 radeonsi: workaround for gather4 on integer cube maps
+
+# stable: 17.2 nomination only.
+c1b01370486d203a6bccff2161afb288cfda1de3 Scons: Add LLVM 5.0 support
+
+# stable: 17.2 nomination only.
+c4ac522511d20683c09441a9e96ddfbc1b540c00 ac/surface: handle S8 on gfx9
+
+# fixes:  This commit addressed an earlier commit 1bcb953e166 which did not
+#         land in branch.
+979978ee06867a531b8d56cee252f5c83920a339 radv: Check for GFX9 for 1D arrays in image_size intrinsic.
+
+# This commit is causing several regressions on i965 driver
+15cae12804ef288c7fb4cb9a38f7e32e6d8c4dc1 glsl/linker: fix output variable overlap check
--- a/docs/relnotes/17.1.10.html
+++ b/docs/relnotes/17.1.10.html
@@ -0,0 +1,155 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.10 Release Notes / September 25, 2017</h1>
+
+<p>
+Mesa 17.1.10 is a bug fix release which fixes bugs found since the 17.1.9 release.
+</p>
+<p>
+Mesa 17.1.10 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+a48ce6b643a728b2b0f926151930525b3670fbff1fb688527fd9051eab9f30a4  mesa-17.1.10.tar.gz
+cbc0d681cc4df47d8deb5a36f45b420978128522fd665b2cd4c7096316f11bdb  mesa-17.1.10.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102844">Bug 102844</a> - memory leak with glDeleteProgram for shader program type GL_COMPUTE_SHADER</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alexandre Demers (1):</p>
+<ul>
+  <li>osmesa: link with libunwind if enabled (v2)</li>
+</ul>
+
+<p>Andres Gomez (12):</p>
+<ul>
+  <li>docs: add sha256 checksums for 17.1.9</li>
+  <li>cherry-ignore: add "st/mesa: skip draw calls with pipe_draw_info::count == 0"</li>
+  <li>cherry-ignore: add "radv: use amdgpu_bo_va_op_raw."</li>
+  <li>cherry-ignore: add "radv: use simpler indirect packet 3 if possible."</li>
+  <li>cherry-ignore: add "radeonsi: don't always apply the PrimID instancing bug workaround on SI"</li>
+  <li>cherry-ignore: add "intel/eu/validate: Look up types on demand in execution_type()"</li>
+  <li>cherry-ignore: add "radv: gfx9 fixes"</li>
+  <li>cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d arrays/3d images"</li>
+  <li>cherry-ignore: add "radv/gfx9: fix image resource handling."</li>
+  <li>cherry-ignore: add "docs/egl: remove reference to EGL_DRIVERS_PATH"</li>
+  <li>cherry-ignore: add "radv: Disable multilayer &amp; multilevel DCC."</li>
+  <li>cherry-ignore: add "radv: Don't allocate CMASK for linear images."</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+  <li>radv/ac: bump params array for image atomic comp swap</li>
+  <li>st/glsl-&gt;tgsi: fix u64 to bool comparisons.</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+  <li>egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension</li>
+  <li>automake: enable libunwind in `make distcheck'</li>
+</ul>
+
+<p>Eric Anholt (3):</p>
+<ul>
+  <li>broadcom/vc4: Fix use-after-free for flushing when writing to a texture.</li>
+  <li>broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear.</li>
+  <li>broadcom/vc4: Fix use-after-free when deleting a program.</li>
+</ul>
+
+<p>George Kyriazis (1):</p>
+<ul>
+  <li>swr: invalidate attachment on transition change</li>
+</ul>
+
+<p>Gert Wollny (2):</p>
+<ul>
+  <li>travis: force llvm-3.3 for "make Gallium ST Other"</li>
+  <li>travis: Add libunwind-dev to gallium/make builds</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>i965/blorp: Set r8stencil_needs_update when writing stencil</li>
+</ul>
+
+<p>Juan A. Suarez Romero (9):</p>
+<ul>
+  <li>cherry-ignore: add "ac/surface: match Z and stencil tile config"</li>
+  <li>cherry-ignore: add "radv/nir: call opt_remove_phis after trivial continues."</li>
+  <li>cherry-ignore: add "amd/common: add workaround for cube map array layer clamping"</li>
+  <li>cherry-ignore: add "radeonsi: workaround for gather4 on integer cube maps"</li>
+  <li>cherry-ignore: add "Scons: Add LLVM 5.0 support"</li>
+  <li>cherry-ignore: add "ac/surface: handle S8 on gfx9"</li>
+  <li>cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size intrinsic."</li>
+  <li>cherry-ignore: add "glsl/linker: fix output variable overlap check"</li>
+  <li>Update version to 17.1.10</li>
+</ul>
+
+<p>Józef Kucia (1):</p>
+<ul>
+  <li>anv: Fix descriptors copying</li>
+</ul>
+
+<p>Matt Turner (2):</p>
+<ul>
+  <li>util: Link libmesautil into u_atomic_test</li>
+  <li>util/u_atomic: Add implementation of __sync_val_compare_and_swap_8</li>
+</ul>
+
+<p>Nicolai HÃÂ¤hnle (1):</p>
+<ul>
+  <li>radeonsi: apply a mask to gl_SampleMaskIn in the PS prolog</li>
+</ul>
+
+<p>Nicolai Hähnle (4):</p>
+<ul>
+  <li>st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index</li>
+  <li>amd/common: round cube array slice in ac_prepare_cube_coords</li>
+  <li>radeonsi: set MIP_POINT_PRECLAMP to 0</li>
+  <li>radeonsi: fix array textures layer coordinate</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>mesa: free current ComputeProgram state in _mesa_free_context_data</li>
+</ul>
+
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/17.1.9.html
+++ b/docs/relnotes/17.1.9.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+4325401b07b5f44759da781bc8d7c0a4a7244e09a702d16c037090986e07ee22  mesa-17.1.9.tar.gz
+5f51ad94341696097d5df7b838183534478216858ac0fc8de183671a36ffea1a  mesa-17.1.9.tar.xz
 </pre>


--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -327,7 +327,7 @@ static void build_cube_select(LLVMBuilderRef builder,

 void
 ac_prepare_cube_coords(struct ac_llvm_context *ctx,
-		       bool is_deriv, bool is_array,
+		       bool is_deriv, bool is_array, bool is_lod,
 		       LLVMValueRef *coords_arg,
 		       LLVMValueRef *derivs_arg)
 {
@@ -337,6 +337,11 @@ ac_prepare_cube_coords(struct ac_llvm_context *ctx,
 	LLVMValueRef coords[3];
 	LLVMValueRef invma;

+	if (is_array && !is_lod) {
+		coords_arg[3] = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32,
+						   &coords_arg[3], 1, 0);
+	}
+
 	build_cube_intrinsic(ctx, coords_arg, &selcoords);

 	invma = ac_build_intrinsic(ctx, "llvm.fabs.f32",
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -82,7 +82,7 @@ ac_build_fdiv(struct ac_llvm_context *ctx,

 void
 ac_prepare_cube_coords(struct ac_llvm_context *ctx,
-		       bool is_deriv, bool is_array,
+		       bool is_deriv, bool is_array, bool is_lod,
 		       LLVMValueRef *coords_arg,
 		       LLVMValueRef *derivs_arg);

--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3355,7 +3355,7 @@ static void visit_image_store(struct nir_to_llvm_context *ctx,
 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
                                       nir_intrinsic_instr *instr)
 {
-	LLVMValueRef params[6];
+	LLVMValueRef params[7];
 	int param_count = 0;
 	const nir_variable *var = instr->variables[0]->var;

@@ -4333,15 +4333,13 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
 	}

 	if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
-		if (instr->is_array && instr->op != nir_texop_lod)
-			coords[3] = apply_round_slice(ctx, coords[3]);
 		for (chan = 0; chan < instr->coord_components; chan++)
 			coords[chan] = to_float(ctx, coords[chan]);
 		if (instr->coord_components == 3)
 			coords[3] = LLVMGetUndef(ctx->f32);
 		ac_prepare_cube_coords(&ctx->ac,
 			instr->op == nir_texop_txd, instr->is_array,
-			coords, derivs);
+			instr->op == nir_texop_lod, coords, derivs);
 		if (num_deriv_comp)
 			num_deriv_comp--;
 	}
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1334,6 +1334,7 @@ static const __DRIextension *dri3_image_loader_extensions[] = {
   &dri3_image_loader_extension.base,
   &image_lookup_extension.base,
   &use_invalidate.base,
+   &background_callable_extension.base,
   NULL,
 };

--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -85,10 +85,10 @@ static void si_build_ps_prolog_function(struct si_shader_context *ctx,
 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
 					union si_shader_part_key *key);

-/* Ideally pass the sample mask input to the PS epilog as v13, which
+/* Ideally pass the sample mask input to the PS epilog as v14, which
 * is its usual location, so that the shader doesn't have to add v_mov.
 */
-#define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
+#define PS_EPILOG_SAMPLEMASK_MIN_LOC 14

 /* The VS location of the PrimitiveID input is the same in the epilog,
 * so that the main shader part doesn't have to move it.
@@ -4655,12 +4655,22 @@ static void tex_fetch_args(
 	if (target == TGSI_TEXTURE_CUBE ||
 	    target == TGSI_TEXTURE_CUBE_ARRAY ||
 	    target == TGSI_TEXTURE_SHADOWCUBE ||
-	    target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
+	    target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
 		ac_prepare_cube_coords(&ctx->ac,
 				       opcode == TGSI_OPCODE_TXD,
 				       target == TGSI_TEXTURE_CUBE_ARRAY ||
 				       target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
+				       opcode == TGSI_OPCODE_LODQ,
 				       coords, derivs);
+	} else if (tgsi_is_array_sampler(target) &&
+		   opcode != TGSI_OPCODE_TXF &&
+		   opcode != TGSI_OPCODE_TXF_LZ &&
+		   ctx->screen->b.chip_class <= VI) {
+		unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
+		coords[array_coord] =
+			ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
+					   &coords[array_coord], 1, 0);
+	}

 	if (opcode == TGSI_OPCODE_TXD)
 		for (int i = 0; i < num_deriv_channels * 2; i++)
@@ -5809,6 +5819,7 @@ static void create_function(struct si_shader_context *ctx)
 		params[SI_PARAM_FRONT_FACE] = ctx->i32;
 		shader->info.face_vgpr_index = 20;
 		params[SI_PARAM_ANCILLARY] = ctx->i32;
+		shader->info.ancillary_vgpr_index = 21;
 		params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
 		params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
 		num_params = SI_PARAM_POS_FIXED_PT+1;
@@ -5876,6 +5887,7 @@ static void create_function(struct si_shader_context *ctx)
 				      S_0286D0_LINEAR_CENTER_ENA(1) |
 				      S_0286D0_LINEAR_CENTROID_ENA(1) |
 				      S_0286D0_FRONT_FACE_ENA(1) |
+				      S_0286D0_ANCILLARY_ENA(1) |
 				      S_0286D0_POS_FIXED_PT_ENA(1));
 	} else if (ctx->type == PIPE_SHADER_COMPUTE) {
 		si_llvm_add_attribute(ctx->main_fn,
@@ -7145,6 +7157,7 @@ static void si_get_ps_prolog_key(struct si_shader *shader,
 		 key->ps_prolog.states.force_linear_center_interp ||
 		 key->ps_prolog.states.bc_optimize_for_persp ||
 		 key->ps_prolog.states.bc_optimize_for_linear);
+	key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;

 	if (info->colors_read) {
 		unsigned *color = shader->selector->color_attr_index;
@@ -7254,7 +7267,8 @@ static bool si_need_ps_prolog(const union si_shader_part_key *key)
 	       key->ps_prolog.states.force_linear_center_interp ||
 	       key->ps_prolog.states.bc_optimize_for_persp ||
 	       key->ps_prolog.states.bc_optimize_for_linear ||
-	       key->ps_prolog.states.poly_stipple;
+	       key->ps_prolog.states.poly_stipple ||
+	       key->ps_prolog.states.samplemask_log_ps_iter;
 }

 /**
@@ -7720,6 +7734,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 	if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		shader->info.num_input_vgprs = 0;
 		shader->info.face_vgpr_index = -1;
+		shader->info.ancillary_vgpr_index = -1;

 		if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
 			shader->info.num_input_vgprs += 2;
@@ -7749,8 +7764,10 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 			shader->info.face_vgpr_index = shader->info.num_input_vgprs;
 			shader->info.num_input_vgprs += 1;
 		}
-		if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
+		if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
+			shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
 			shader->info.num_input_vgprs += 1;
+		}
 		if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
 			shader->info.num_input_vgprs += 1;
 		if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
@@ -8395,6 +8412,54 @@ static void si_build_ps_prolog_function(struct si_shader_context *ctx,
 		}
 	}

+	/* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
+	 * says:
+	 *
+	 *    "When per-sample shading is active due to the use of a fragment
+	 *     input qualified by sample or due to the use of the gl_SampleID
+	 *     or gl_SamplePosition variables, only the bit for the current
+	 *     sample is set in gl_SampleMaskIn. When state specifies multiple
+	 *     fragment shader invocations for a given fragment, the sample
+	 *     mask for any single fragment shader invocation may specify a
+	 *     subset of the covered samples for the fragment. In this case,
+	 *     the bit corresponding to each covered sample will be set in
+	 *     exactly one fragment shader invocation."
+	 *
+	 * The samplemask loaded by hardware is always the coverage of the
+	 * entire pixel/fragment, so mask bits out based on the sample ID.
+	 */
+	if (key->ps_prolog.states.samplemask_log_ps_iter) {
+		/* The bit pattern matches that used by fixed function fragment
+		 * processing. */
+		static const uint16_t ps_iter_masks[] = {
+			0xffff, /* not used */
+			0x5555,
+			0x1111,
+			0x0101,
+			0x0001,
+		};
+		assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
+
+		uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
+		unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
+					  key->ps_prolog.ancillary_vgpr_index;
+		LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
+		LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
+
+		samplemask = LLVMBuildBitCast(gallivm->builder, samplemask, ctx->i32, "");
+		samplemask = LLVMBuildAnd(
+			gallivm->builder,
+			samplemask,
+			LLVMBuildShl(gallivm->builder,
+				     LLVMConstInt(ctx->i32, ps_iter_mask, false),
+				     sampleid, ""),
+			"");
+		samplemask = LLVMBuildBitCast(gallivm->builder, samplemask, ctx->f32, "");
+
+		ret = LLVMBuildInsertValue(gallivm->builder, ret, samplemask,
+					   ancillary_vgpr + 1, "");
+	}
+
 	/* Tell LLVM to insert WQM instruction sequence when needed. */
 	if (key->ps_prolog.wqm) {
 		LLVMAddTargetDependentFunctionAttr(func,
@@ -8592,6 +8657,12 @@ static bool si_shader_select_ps_parts(struct si_screen *sscreen,
 		assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
 	}

+	/* Samplemask fixup requires the sample ID. */
+	if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
+		shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
+		assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
+	}
+
 	/* The sample mask input is always enabled, because the API shader always
 	 * passes it through to the epilog. Disable it here if it's unused.
 	 */
@@ -8669,6 +8740,7 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 		shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
 		shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
 		shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
+		shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
 		memcpy(shader->info.vs_output_param_offset,
 		       mainp->info.vs_output_param_offset,
 		       sizeof(mainp->info.vs_output_param_offset));
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -371,6 +371,7 @@ struct si_ps_prolog_bits {
 	unsigned	force_linear_center_interp:1;
 	unsigned	bc_optimize_for_persp:1;
 	unsigned	bc_optimize_for_linear:1;
+	unsigned	samplemask_log_ps_iter:3;
 };

 /* Common PS bits between the shader key and the epilog key. */
@@ -409,6 +410,7 @@ union si_shader_part_key {
 		unsigned	colors_read:8; /* color input components read */
 		unsigned	num_interp_inputs:5; /* BCOLOR is at this location */
 		unsigned	face_vgpr_index:5;
+		unsigned	ancillary_vgpr_index:5;
 		unsigned	wqm:1;
 		char		color_attr_index[2];
 		char		color_interp_vgpr_index[2]; /* -1 == constant */
@@ -503,7 +505,8 @@ struct si_shader_info {
 	ubyte			vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 	ubyte			num_input_sgprs;
 	ubyte			num_input_vgprs;
-	char			face_vgpr_index;
+	signed char		face_vgpr_index;
+	signed char		ancillary_vgpr_index;
 	bool			uses_instanceid;
 	ubyte			nr_pos_exports;
 	ubyte			nr_param_exports;
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3613,7 +3613,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
 			  S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
 			  S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
 			  S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
-			  S_008F38_MIP_POINT_PRECLAMP(1) |
+			  S_008F38_MIP_POINT_PRECLAMP(0) |
 			  S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
 			  S_008F38_FILTER_PREC_FIX(1) |
 			  S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1154,6 +1154,12 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
 							     sctx->framebuffer.nr_samples <= 1;
 			key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;

+			if (sctx->ps_iter_samples > 1 &&
+			    sel->info.reads_samplemask) {
+				key->part.ps.prolog.samplemask_log_ps_iter =
+					util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
+			}
+
 			if (rs->force_persample_interp &&
 			    rs->multisample_enable &&
 			    sctx->framebuffer.nr_samples > 1 &&
--- a/src/gallium/drivers/swr/swr_draw.cpp
+++ b/src/gallium/drivers/swr/swr_draw.cpp
@@ -210,6 +210,25 @@ swr_finish(struct pipe_context *pipe)
   swr_fence_reference(pipe->screen, &fence, NULL);
 }

+/*
+ * Invalidate tiles so they can be reloaded back when needed
+ */
+void
+swr_invalidate_render_target(struct pipe_context *pipe,
+                             uint32_t attachment,
+                             uint16_t width, uint16_t height)
+{
+   struct swr_context *ctx = swr_context(pipe);
+
+   /* grab the rect from the passed in arguments */
+   swr_update_draw_context(ctx);
+   SWR_RECT full_rect =
+      {0, 0, (int32_t)width, (int32_t)height};
+   SwrInvalidateTiles(ctx->swrContext,
+                      1 << attachment,
+                      full_rect);
+}
+

 /*
 * Store SWR HotTiles back to renderTarget surface.
--- a/src/gallium/drivers/swr/swr_resource.h
+++ b/src/gallium/drivers/swr/swr_resource.h
@@ -96,6 +96,10 @@ swr_resource_data(struct pipe_resource *resource)
 }


+void swr_invalidate_render_target(struct pipe_context *pipe,
+                                  uint32_t attachment,
+                                  uint16_t width, uint16_t height);
+
 void swr_store_render_target(struct pipe_context *pipe,
                             uint32_t attachment,
                             enum SWR_TILE_STATE post_tile_state);
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -948,6 +948,11 @@ swr_change_rt(struct swr_context *ctx,
       * INVALID so they are reloaded from surface. */
      swr_store_render_target(&ctx->pipe, attachment, SWR_TILE_INVALID);
      need_fence = true;
+   } else {
+      /* if no previous attachment, invalidate tiles that may be marked
+       * RESOLVED because of an old attachment */
+      swr_invalidate_render_target(&ctx->pipe, attachment, sf->width, sf->height);
+      /* no need to set fence here */
   }

   /* Make new attachment */
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -495,6 +495,37 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
        struct vc4_context *vc4 = vc4_context(pctx);
        struct vc4_job *job = vc4_get_job_for_fbo(vc4);

+        if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+                struct vc4_resource *rsc =
+                        vc4_resource(vc4->framebuffer.zsbuf->texture);
+                unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
+
+                /* Clearing ZS will clear both Z and stencil, so if we're
+                 * trying to clear just one then we need to draw a quad to do
+                 * it instead.  We need to do this before setting up
+                 * tile-based clears in vc4->job, because the blitter may
+                 * submit the current job.
+                 */
+                if ((zsclear == PIPE_CLEAR_DEPTH ||
+                     zsclear == PIPE_CLEAR_STENCIL) &&
+                    (rsc->initialized_buffers & ~(zsclear | job->cleared)) &&
+                    util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) {
+                        perf_debug("Partial clear of Z+stencil buffer, "
+                                   "drawing a quad instead of fast clearing\n");
+                        vc4_blitter_save(vc4);
+                        util_blitter_clear(vc4->blitter,
+                                           vc4->framebuffer.width,
+                                           vc4->framebuffer.height,
+                                           1,
+                                           zsclear,
+                                           NULL, depth, stencil);
+                        buffers &= ~zsclear;
+                        if (!buffers)
+                                return;
+                        job = vc4_get_job_for_fbo(vc4);
+                }
+        }
+
        /* We can't flag new buffers for clearing once we've queued draws.  We
         * could avoid this by using the 3d engine to clear.
         */
@@ -530,29 +561,6 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
        if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
                struct vc4_resource *rsc =
                        vc4_resource(vc4->framebuffer.zsbuf->texture);
-                unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
-
-                /* Clearing ZS will clear both Z and stencil, so if we're
-                 * trying to clear just one then we need to draw a quad to do
-                 * it instead.
-                 */
-                if ((zsclear == PIPE_CLEAR_DEPTH ||
-                     zsclear == PIPE_CLEAR_STENCIL) &&
-                    (rsc->initialized_buffers & ~(zsclear | job->cleared)) &&
-                    util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) {
-                        perf_debug("Partial clear of Z+stencil buffer, "
-                                   "drawing a quad instead of fast clearing\n");
-                        vc4_blitter_save(vc4);
-                        util_blitter_clear(vc4->blitter,
-                                           vc4->framebuffer.width,
-                                           vc4->framebuffer.height,
-                                           1,
-                                           zsclear,
-                                           NULL, depth, stencil);
-                        buffers &= ~zsclear;
-                        if (!buffers)
-                                return;
-                }

                /* Though the depth buffer is stored with Z in the high 24,
                 * for this field we just need to store it in the low 24.
@@ -564,7 +572,7 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
                if (buffers & PIPE_CLEAR_STENCIL)
                        job->clear_stencil = stencil;

-                rsc->initialized_buffers |= zsclear;
+                rsc->initialized_buffers |= (buffers & PIPE_CLEAR_DEPTHSTENCIL);
        }

        job->draw_min_x = 0;
--- a/src/gallium/drivers/vc4/vc4_job.c
+++ b/src/gallium/drivers/vc4/vc4_job.c
@@ -117,12 +117,17 @@ vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
                struct vc4_job *job = entry->data;

                struct vc4_bo **referenced_bos = job->bo_pointers.base;
+                bool found = false;
                for (int i = 0; i < cl_offset(&job->bo_handles) / 4; i++) {
                        if (referenced_bos[i] == rsc->bo) {
-                                vc4_job_submit(vc4, job);
-                                continue;
+                                found = true;
+                                break;
                        }
                }
+                if (found) {
+                        vc4_job_submit(vc4, job);
+                        continue;
+                }

                /* Also check for the Z/color buffers, since the references to
                 * those are only added immediately before submit.
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2763,11 +2763,11 @@ vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
        vc4->dirty |= VC4_DIRTY_COMPILED_FS;

        if (vc4->rasterizer->base.flatshade &&
-            old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
+            (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
                vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
        }

-        if (old_fs && vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
+        if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
                vc4->dirty |= VC4_DIRTY_FS_INPUTS;
 }

@@ -2877,6 +2877,7 @@ fs_inputs_compare(const void *key1, const void *key2)

 static void
 delete_from_cache_if_matches(struct hash_table *ht,
+                             struct vc4_compiled_shader **last_compile,
                             struct hash_entry *entry,
                             struct vc4_uncompiled_shader *so)
 {
@@ -2886,6 +2887,10 @@ delete_from_cache_if_matches(struct hash_table *ht,
                struct vc4_compiled_shader *shader = entry->data;
                _mesa_hash_table_remove(ht, entry);
                vc4_bo_unreference(&shader->bo);
+
+                if (shader == *last_compile)
+                        *last_compile = NULL;
+
                ralloc_free(shader);
        }
 }
@@ -2897,10 +2902,14 @@ vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
        struct vc4_uncompiled_shader *so = hwcso;

        struct hash_entry *entry;
-        hash_table_foreach(vc4->fs_cache, entry)
-                delete_from_cache_if_matches(vc4->fs_cache, entry, so);
-        hash_table_foreach(vc4->vs_cache, entry)
-                delete_from_cache_if_matches(vc4->vs_cache, entry, so);
+        hash_table_foreach(vc4->fs_cache, entry) {
+                delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
+                                             entry, so);
+        }
+        hash_table_foreach(vc4->vs_cache, entry) {
+                delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
+                                             entry, so);
+        }

        ralloc_free(so->base.ir.nir);
        free(so);
--- a/src/gallium/targets/osmesa/Makefile.am
+++ b/src/gallium/targets/osmesa/Makefile.am
@@ -66,7 +66,8 @@ lib@OSMESA_LIB@_la_LIBADD = \
 	$(top_builddir)/src/mapi/glapi/libglapi.la \
 	$(SHARED_GLAPI_LIB) \
 	$(OSMESA_LIB_DEPS) \
-	$(CLOCK_LIB)
+	$(CLOCK_LIB) \
+	$(LIBUNWIND_LIBS)

 if HAVE_GALLIUM_LLVM
 AM_CPPFLAGS += -DGALLIUM_LLVMPIPE
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -767,7 +767,7 @@ void anv_UpdateDescriptorSets(

   for (uint32_t i = 0; i < descriptorCopyCount; i++) {
      const VkCopyDescriptorSet *copy = &pDescriptorCopies[i];
-      ANV_FROM_HANDLE(anv_descriptor_set, src, copy->dstSet);
+      ANV_FROM_HANDLE(anv_descriptor_set, src, copy->srcSet);
      ANV_FROM_HANDLE(anv_descriptor_set, dst, copy->dstSet);

      const struct anv_descriptor_set_binding_layout *src_layout =
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -147,6 +147,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
                       unsigned start_layer, unsigned num_layers,
                       struct isl_surf tmp_surfs[2])
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
       mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
      const unsigned num_samples = MAX2(1, mt->num_samples);
@@ -192,6 +194,10 @@ blorp_surf_for_miptree(struct brw_context *brw,
   struct isl_surf *aux_surf = &tmp_surfs[1];
   intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);

+   if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
+       devinfo->gen <= 7)
+      mt->r8stencil_needs_update = true;
+
   if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
      if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
         /* If we're not going to use it as a depth buffer, resolve HiZ */
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1312,6 +1312,8 @@ _mesa_free_context_data( struct gl_context *ctx )
   _mesa_reference_program(ctx, &ctx->FragmentProgram._Current, NULL);
   _mesa_reference_program(ctx, &ctx->FragmentProgram._TexEnvProgram, NULL);

+   _mesa_reference_program(ctx, &ctx->ComputeProgram._Current, NULL);
+
   _mesa_reference_vao(ctx, &ctx->Array.VAO, NULL);
   _mesa_reference_vao(ctx, &ctx->Array.DefaultVAO, NULL);

--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -445,6 +445,7 @@ public:
   st_src_reg st_src_reg_for_double(double val);
   st_src_reg st_src_reg_for_float(float val);
   st_src_reg st_src_reg_for_int(int val);
+   st_src_reg st_src_reg_for_int64(int64_t val);
   st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);

   /**
@@ -1211,6 +1212,19 @@ glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
   return src;
 }

+st_src_reg
+glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
+{
+   st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
+   union gl_constant_value uval[2];
+
+   memcpy(uval, &val, sizeof(uval));
+   src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
+   src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
+
+   return src;
+}
+
 st_src_reg
 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
 {
@@ -2459,7 +2473,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
      break;
   }
   case ir_unop_i642b:
-      emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int(0));
+      emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int64(0));
      break;
   case ir_unop_i642f:
      emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
@@ -2840,7 +2854,7 @@ glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
   ir->array->accept(this);
   src = this->result;

-   if (ir->array->ir_type != ir_type_dereference_array) {
+   if (!src.has_index2) {
      switch (this->prog->Target) {
      case GL_TESS_CONTROL_PROGRAM_NV:
         is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -48,6 +48,7 @@ libmesautil_la_LIBADD = \
 	$(CLOCK_LIB) \
 	$(ZLIB_LIBS)

+u_atomic_test_LDADD = libmesautil.la
 roundeven_test_LDADD = -lm

 check_PROGRAMS = u_atomic_test roundeven_test
--- a/src/util/u_atomic.c
+++ b/src/util/u_atomic.c
@@ -60,6 +60,20 @@ __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
   return r;
 }

+WEAK uint64_t
+__sync_val_compare_and_swap_8(uint64_t *ptr, uint64_t oldval, uint64_t newval)
+{
+   uint64_t r;
+
+   pthread_mutex_lock(&sync_mutex);
+   r = *ptr;
+   if (*ptr == oldval)
+      *ptr = newval;
+   pthread_mutex_unlock(&sync_mutex);
+
+   return r;
+}
+
 WEAK uint64_t
 __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
 {
Author	SHA1	Message	Date
Juan A. Suarez Romero	60df95c6bd	docs: add sha256 checksums for 17.1.10 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-25 17:00:35 +00:00
Juan A. Suarez Romero	834d6c60db	docs: add release notes for 17.1.10 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-25 15:18:34 +00:00
Juan A. Suarez Romero	a883f756e4	Update version to 17.1.10 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-25 15:11:05 +00:00
Tapani Pälli	6dc71ce3cc	mesa: free current ComputeProgram state in _mesa_free_context_data This is already done for other programs stages, fixes a leak when using compute programs. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102844 Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit `589457d97f`)	2017-09-21 09:29:27 +02:00
Alexandre Demers	b92a4dff92	osmesa: link with libunwind if enabled (v2) Fixes linking error in libOSmesa when using libunwind. CXXLD libOSMesa.la src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `symbol_name_cached': ./src/gallium/auxiliary/util/u_debug_stack.c:87: undefined reference to `_ULx86_64_get_proc_name' src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `debug_backtrace_capture': ./src/gallium/auxiliary/util/u_debug_stack.c:114: undefined reference to `_Ux86_64_getcontext' ./src/gallium/auxiliary/util/u_debug_stack.c:115: undefined reference to `_ULx86_64_init_local' ./src/gallium/auxiliary/util/u_debug_stack.c:117: undefined reference to `_ULx86_64_step' ./src/gallium/auxiliary/util/u_debug_stack.c:123: undefined reference to `_ULx86_64_get_reg' ./src/gallium/auxiliary/util/u_debug_stack.c:124: undefined reference to `_ULx86_64_get_proc_info' ./src/gallium/auxiliary/util/u_debug_stack.c:120: undefined reference to `_ULx86_64_step' collect2: error: ld returned 1 exit status v2 : Fixes title and adds the original error it is fixing. Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com> (cherry picked from commit `a958a30827`)	2017-09-21 09:29:27 +02:00
Juan A. Suarez Romero	2a000ed782	cherry-ignore: add "glsl/linker: fix output variable overlap check" This commit is causing several regressions on i965 driver. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:12 +02:00
Nicolai Hähnle	0ec2f628d1	radeonsi: fix array textures layer coordinate Like for cube map (array) gather, we need to round to nearest on <= VI. Fixes tests in dEQP-GLES3.functional.shaders.texture_functions.texture.* Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `87f7c7bd65`) [Juan A. Suarez: apply patch over si_shader.c] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c	2017-09-20 22:54:12 +02:00
Nicolai Hähnle	96f815aeab	radeonsi: set MIP_POINT_PRECLAMP to 0 This fixes a bug with nearest ("point") mip selection when the fractional part of max_lod is in (0.5,1). In this case, the spec mandates that we still select the mip level ceil(max_lod) in the clamping case. However, MIP_POINT_PRECLAMP will clamp before the mip selection, which is wrong. Supposedly this setting was originally copied from the closed Vulkan driver, but as far as I can tell, closed Vulkan was actually changed back recently :) Fixes dEQP-GLES3.functional.texture.mipmap.2d.max_lod.{nearest,linear}_nearest Fixes: `f7420ef5b4` ("radeonsi: enable some sampler fields to match the closed driver") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `704ddbcdf6`)	2017-09-20 22:54:12 +02:00
Józef Kucia	f46c17bb97	anv: Fix descriptors copying Trivial. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit `65a09f98ad`)	2017-09-20 22:54:12 +02:00
George Kyriazis	8ae081a57e	swr: invalidate attachment on transition change Consider the following RT attachment order: 1. Attach surfaces attachments 0 & 1, and render with them 2. Detach 0 & 1 3. Re-attach 0 & 1 to different surfaces 4. Render with the new attachment The definition of a tile being resolved is that local changes have been flushed out to the surface, hence there is no need to reload the tile before it's written to. For an invalid tile, the tile has to be reloaded from the surface before rendering. Stage (2) was marking hot tiles for attachements 0 & 1 as RESOLVED, which means that the hot tiles can be written out to memory with no need to read them back in (they are "clean"). They need to be marked as resolved here, because a surface may be destroyed after a detach, and we don't want to have un-resolved tiles that may force a readback from a NULL (destroyed) surface. (Part of a destroy is detach all attachments first) Stage (3), during the no att -> att transition, we need to realize that the "new" surface tiles need to be fetched fresh from the new surface, instead of using the resolved tiles, that belong to a stale attachment. This is done by marking the hot tiles as invalid in stage (3), when we realize that a new attachment is being made, so that they are re-fetched during rendering in stage (4). Also note that hot tiles are indexed by attachment. - Fixes VTK dual depth-peeling tests. - No piglit changes Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com> (cherry picked from commit `08cb8cf256`)	2017-09-20 22:54:11 +02:00
Eric Anholt	4e10705200	broadcom/vc4: Fix use-after-free when deleting a program. By leaving the compiled shader in the context's stage state, the next compile of a new FS would look in the old compiled FS for figuring out whether to set various dirty flags for the VS compile. Clear out the pointer when deleting the program, and make sure that we always mark the state as dirty if the previous program had been lost. Fixes valgrind warnings on glsl-max-varyings. Fixes: `2350569a78` ("vc4: Avoid VS shader recompiles by keeping a set of FS inputs seen so far.") (cherry picked from commit `3752ad28f2`)	2017-09-20 22:54:11 +02:00
Eric Anholt	f6469ac143	broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear. The blitter will bind just the depth buffer, which flushes the current job if we had both a color and depth/stencil. If the clear was doing partial depth/stencil (quad-based) and color (tile-based), we'd go on to try to set up the rest of the tile clear in the now flushed job. Instead, move the partial clear up before we start setting up the job for the current FBO state, and re-fetch the job if we're continuing on to a tile-based clear. Fixes valgrind failures in fbo-depthtex. Fixes: `9421a6065c` ("vc4: Fix fallback to quad clears of depth in GLX.") (cherry picked from commit `9940fb4205`)	2017-09-20 22:54:11 +02:00
Eric Anholt	727a6a8cdd	broadcom/vc4: Fix use-after-free for flushing when writing to a texture. I was trying to continue the hash table loop, not the inner loop. This tended to work out, because we would have just freed the job struct. Fixes some valgrind failures in fbo-depthtex. Fixes: `f597ac3966` ("vc4: Implement job shuffling") (cherry picked from commit `d88a75182d`)	2017-09-20 22:54:11 +02:00
Juan A. Suarez Romero	700099df4f	cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size intrinsic." fixes: This commit addressed an earlier commit `1bcb953e16` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:11 +02:00
Dave Airlie	136c3c79b3	st/glsl->tgsi: fix u64 to bool comparisons. Otherwise we end up using a 32-bit comparison which didn't end well. Timothy caught this while playing around with some opt passes. Fixes: `278580729a` (st/glsl_to_tgsi: add support for 64-bit integers) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit `a7a7bf21bd`)	2017-09-20 22:54:11 +02:00
Juan A. Suarez Romero	ea5b52b100	cherry-ignore: add "ac/surface: handle S8 on gfx9" stable: 17.2 nomination only. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:11 +02:00
Juan A. Suarez Romero	0cf7c0c0ca	cherry-ignore: add "Scons: Add LLVM 5.0 support" stable: 17.2 nomination only. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:11 +02:00
Juan A. Suarez Romero	ccd74e4ada	cherry-ignore: add "radeonsi: workaround for gather4 on integer cube maps" stable: 17.2 nomination only. Depends on earlier commit `5cb2eee557` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:11 +02:00
Matt Turner	38f5a2204c	util/u_atomic: Add implementation of __sync_val_compare_and_swap_8 Needed for 32-bit PowerPC. Cc: "17.2" <mesa-stable@lists.freedesktop.org> Fixes: `a6a38a038b` ("util/u_atomic: provide 64bit atomics where they're missing") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `1bbe180873`)	2017-09-20 22:54:11 +02:00
Matt Turner	b55385ac60	util: Link libmesautil into u_atomic_test Platforms without particular atomic operations require the implementations in u_atomic.c Cc: "17.2" <mesa-stable@lists.freedesktop.org> Fixes: `a6a38a038b` ("util/u_atomic: provide 64bit atomics where they're missing") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `d075a4089e`) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/util/Makefile.am	2017-09-20 22:54:11 +02:00
Juan A. Suarez Romero	d6a5e80e8a	cherry-ignore: add "amd/common: add workaround for cube map array layer clamping" fixes: Depends on earlier commit `13a28ff236` that did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 22:54:11 +02:00
Nicolai Hähnle	f9a5844445	amd/common: round cube array slice in ac_prepare_cube_coords The NIR-to-LLVM pass already does this; now the same fix covers radeonsi as well. Fixes various tests of dEQP-GLES31.functional.texture.filtering.cube_array.combinations.* Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `e0af3bed2c`) [Juan A. Suarez: resolve trivial conflicts. Apply patch into si_shader.c] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/common/ac_nir_to_llvm.c src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c	2017-09-20 22:54:11 +02:00
Jason Ekstrand	1fb09613fc	i965/blorp: Set r8stencil_needs_update when writing stencil This fixes a crash on Haswell when we try to upload a stencil texture with blorp. It would also be a problem if someone tried to texture from stencil after glBlitFramebuffers. Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (cherry picked from commit `a43d379000`) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/brw_blorp.c	2017-09-20 22:54:11 +02:00
Emil Velikov	a13241d28b	automake: enable libunwind in `make distcheck' Enable the toggle to catch when the library is missing from the link path. Better to test, fail and address before releasing Mesa ;-) Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit `9aba643e3c`)	2017-09-20 22:54:11 +02:00
Gert Wollny	634f70ddbf	travis: Add libunwind-dev to gallium/make builds libunwind is a optional dependency used by the gallium aux module (libgallium) and consequently the final binaries must be linked against it. To test whether the library is properly specified in the link pass add it to the travis-ci build environment and force its use. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `39fe51c1e3`)	2017-09-20 10:02:33 +02:00
Gert Wollny	b181a5bb8a	travis: force llvm-3.3 for "make Gallium ST Other" In Ubuntu Trusty the default version of llvm is 3.4 and the build was actually randomly picking 3.5 or 3.9. Adding libunwind would then result is build success or failure depending of what version was picked. Install the llvm-3.3-dev package and force its use: On one hand it is the minimum required version we want to the build test against, and on the other hand forcing the version stabilizes the build. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `d3675812b5`)	2017-09-20 10:02:33 +02:00
Juan A. Suarez Romero	367c38d1d3	cherry-ignore: add "radv/nir: call opt_remove_phis after trivial continues." stable: 17.2. nomination only. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 10:02:33 +02:00
Juan A. Suarez Romero	bb3aa93e71	cherry-ignore: add "ac/surface: match Z and stencil tile config" stable: 17.2 nomination only. Depends on earlier commit `f187a4932` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-09-20 10:02:33 +02:00
Nicolai HÃÂ¤hnle	f348cd1430	radeonsi: apply a mask to gl_SampleMaskIn in the PS prolog gl_SampleMaskIn is supposed to contain set bits only for the samples that are covered by the current fragment shader invocation, but the VGPR initialization hardware loads the set of all bits that are covered at the current pixel. Fixes various tests in dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.* Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `92c4277990`) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/gallium/drivers/radeonsi/si_shader.c	2017-09-20 10:02:33 +02:00
Andres Gomez	09cce2b046	cherry-ignore: add "radv: Don't allocate CMASK for linear images." fixes: Depends on earlier commit `dfc06d2fac` that did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	a4ee736861	cherry-ignore: add "radv: Disable multilayer & multilevel DCC." fixes: We don't really want to disable something unless it is causing a big problem. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	b0f779acff	cherry-ignore: add "docs/egl: remove reference to EGL_DRIVERS_PATH" fixes: It only fixes documentation. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	f875097523	cherry-ignore: add "radv/gfx9: fix image resource handling." stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Dave Airlie	3a92f04d0e	radv/ac: bump params array for image atomic comp swap For the comp_swap case this was overflowing and crashing sometimes. Fixes: dEQP-VK.image.atomic_operations.compare_exchange.* Cc: "17.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `aba441be44`)	2017-09-19 16:22:03 +02:00
Andres Gomez	e0fcfe6ce1	cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d arrays/3d images" stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	832c111461	cherry-ignore: add "radv: gfx9 fixes" stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	0bc268fc07	cherry-ignore: add "intel/eu/validate: Look up types on demand in execution_type()" stable: 17.2 nomination only. Depends on earlier commit `4fab67a441` which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	572848e361	cherry-ignore: add "radeonsi: don't always apply the PrimID instancing bug workaround on SI" fixes: References `391673af` but it is not really a bug fix. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Emil Velikov	6fa40b1643	egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension Fixes: `3b7b6adf3a` ("egl: Implement __DRI_BACKGROUND_CALLABLE") Cc: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `f24bc18162`)	2017-09-19 16:22:03 +02:00
Nicolai Hähnle	2c47bbb08a	st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index Don't get distracted by record dereferences between array references. Fixes dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.* Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `03203b7448`)	2017-09-19 16:22:03 +02:00
Andres Gomez	5c22ee7220	cherry-ignore: add "radv: use simpler indirect packet 3 if possible." stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	eae6798a91	cherry-ignore: add "radv: use amdgpu_bo_va_op_raw." stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	e09bd9fa6a	cherry-ignore: add "st/mesa: skip draw calls with pipe_draw_info::count == 0" stable: 17.2 nomination only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-19 16:22:03 +02:00
Andres Gomez	aad527c3c3	docs: add sha256 checksums for 17.1.9 Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-09-09 02:09:33 +03:00
@@ -1 +1 @@
 .1.9
 .1.10