docs: add sha256 checksums for 17.2.8

Signed-off-by: Andres Gomez <agomez@igalia.com>
docs: add release notes for 17.2.8
2017-12-23 00:54:11 +02:00 · 2017-12-22 22:39:47 +02:00 · 2017-12-22 22:34:12 +02:00 · 2017-12-20 19:40:38 +02:00 · 2017-12-20 19:40:38 +02:00 · 2017-12-20 19:40:38 +02:00
18 changed files with 299 additions and 65 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-17.2.7
+17.2.8
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -139,3 +139,23 @@ a31d0382084c8aa860ffcef9b12592c5c44e192f Revert "intel/fs: Use a pure vertical s
 # stable: The commit depends on at least one other that did not land in
 #          branch - 8b3a2578519.
 010214b403de1b5e25a549372ba6192b89e05d06 radeonsi: allow DMABUF exports for local buffers
+
+# stable: This commit addressed earlier commit ead0dfe31ec7 which did
+#         not land in branch.
+709f5bdc4a2bf31f422f5cf60797224c0463c10a swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.
+
+# stable: 17.3 nomination only.
+bf0904e31fb7d9cd8932d582076c8d7beb02ba89 winsys/amdgpu: disable local BOs again due to worse performance
+35c3cbad3c30ad3d40a6811dd6ca2286e013bfc5 radeonsi: don't call force_dcc_off for buffers
+
+# fixes:  This commit addressed earlier commit d1c9f30d7ff7 which did
+#         not land in branch.
+1bdeac545f4ea9f7ca6947f5da7fcf4f5b3010dc radv: port merge tess info from anv
+
+# extra:  The commit just references a fix for an additional change in its v2.
+c1ff99fd70cd2ceb2cac4723e4fd5efc93834746 main: Clear shader program data whenever ProgramBinary is called
+
+# extra:  The commit references a previous commit in which the changes
+#         should have been included but, as clarified by the
+#         developer, it is not needed for stable.
+71e630753ebbee82e8f8709da5488296b2c070c8 r600: set DX10_CLAMP for compute shader too
--- a/docs/relnotes/17.2.7.html
+++ b/docs/relnotes/17.2.7.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+e8d837a1cd55014e636e9caf6c75cfbe1b3e4be9ab3fa125f5ef38398aa12e97  mesa-17.2.7.tar.gz
+50cfdea8df55045797b4d0409591c04c784d9551c4da09b8178874dbe5a37a68  mesa-17.2.7.tar.xz
 </pre>


--- a/docs/relnotes/17.2.8.html
+++ b/docs/relnotes/17.2.8.html
@@ -0,0 +1,112 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.2.8 Release Notes / December 22, 2017</h1>
+
+<p>
+Mesa 17.2.8 is a bug fix release which fixes bugs found since the 17.2.7 release.
+</p>
+<p>
+Mesa 17.2.8 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+c715c3a3d6fe26a69c096f573ec416e038a548f0405e3befedd5136517527a84  mesa-17.2.8.tar.gz
+6e940345cceaadfd805d701ed2b956589fa77fe8c39991da30ed51ea6b9d095f  mesa-17.2.8.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102710">Bug 102710</a> - vkCmdBlitImage with arrayLayers &gt; 1 fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103007">Bug 103007</a> - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103544">Bug 103544</a> - Graphical glitches r600 in game this war of mine linux native</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103579">Bug 103579</a> - Vertex shader causes compiler to crash in SPIRV-to-NIR</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Andres Gomez (6):</p>
+<ul>
+  <li>cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.</li>
+  <li>cherry-ignore: added 17.3 nominations.</li>
+  <li>cherry-ignore: radv: port merge tess info from anv</li>
+  <li>cherry-ignore: main: Clear shader program data whenever ProgramBinary is called</li>
+  <li>cherry-ignore: r600: set DX10_CLAMP for compute shader too</li>
+  <li>Update version to 17.2.8</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (2):</p>
+<ul>
+  <li>spirv: Fix loading an entire block at once.</li>
+  <li>radv: Fix multi-layer blits.</li>
+</ul>
+
+<p>Brian Paul (2):</p>
+<ul>
+  <li>xlib: call _mesa_warning() instead of fprintf()</li>
+  <li>gallium/aux: include nr_samples in util_resource_size() computation</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>docs: add sha256 checksums for 17.2.7</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>i965/vec4: use a temp register to compute offsets for pull loads</li>
+</ul>
+
+<p>Leo Liu (1):</p>
+<ul>
+  <li>radeon/vce: move destroy command before feedback command</li>
+</ul>
+
+<p>Matt Turner (2):</p>
+<ul>
+  <li>util: Assume little endian in the absence of platform-specific handling</li>
+  <li>util: Add a SHA1 unit test program</li>
+</ul>
+
+<p>Roland Scheidegger (2):</p>
+<ul>
+  <li>r600: use min_dx10/max_dx10 instead of min/max</li>
+  <li>r600: use DX10_CLAMP bit in shader setup</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -269,8 +269,8 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
               VkOffset3D src_offset_1,
               struct radv_image *dest_image,
               struct radv_image_view *dest_iview,
-               VkOffset3D dest_offset_0,
-               VkOffset3D dest_offset_1,
+               VkOffset2D dest_offset_0,
+               VkOffset2D dest_offset_1,
               VkRect2D dest_box,
               VkFilter blit_filter)
 {
@@ -517,21 +517,6 @@ void radv_CmdBlitImage(
 	for (unsigned r = 0; r < regionCount; r++) {
 		const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
 		const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
-		struct radv_image_view src_iview;
-		radv_image_view_init(&src_iview, cmd_buffer->device,
-				     &(VkImageViewCreateInfo) {
-					     .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
-						     .image = srcImage,
-						     .viewType = radv_meta_get_view_type(src_image),
-						     .format = src_image->vk_format,
-						     .subresourceRange = {
-						     .aspectMask = src_res->aspectMask,
-						     .baseMipLevel = src_res->mipLevel,
-						     .levelCount = 1,
-						     .baseArrayLayer = src_res->baseArrayLayer,
-						     .layerCount = 1
-					     },
-				     });

 		unsigned dst_start, dst_end;
 		if (dest_image->type == VK_IMAGE_TYPE_3D) {
@@ -578,18 +563,17 @@ void radv_CmdBlitImage(
 		dest_box.extent.width = abs(dst_x1 - dst_x0);
 		dest_box.extent.height = abs(dst_y1 - dst_y0);

-		struct radv_image_view dest_iview;
 		const unsigned num_layers = dst_end - dst_start;
 		for (unsigned i = 0; i < num_layers; i++) {
-			const VkOffset3D dest_offset_0 = {
+			struct radv_image_view dest_iview, src_iview;
+
+			const VkOffset2D dest_offset_0 = {
 				.x = dst_x0,
 				.y = dst_y0,
-				.z = dst_start + i ,
 			};
-			const VkOffset3D dest_offset_1 = {
+			const VkOffset2D dest_offset_1 = {
 				.x = dst_x1,
 				.y = dst_y1,
-				.z = dst_start + i ,
 			};
 			VkOffset3D src_offset_0 = {
 				.x = src_x0,
@@ -601,9 +585,10 @@ void radv_CmdBlitImage(
 				.y = src_y1,
 				.z = src_start + i * src_z_step,
 			};
-			const uint32_t dest_array_slice =
-				radv_meta_get_iview_layer(dest_image, dst_res,
-							  &dest_offset_0);
+			const uint32_t dest_array_slice = dst_start + i;
+
+			/* 3D images have just 1 layer */
+			const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;

 			radv_image_view_init(&dest_iview, cmd_buffer->device,
 					     &(VkImageViewCreateInfo) {
@@ -619,6 +604,20 @@ void radv_CmdBlitImage(
 							     .layerCount = 1
 						     },
 					     });
+			radv_image_view_init(&src_iview, cmd_buffer->device,
+					     &(VkImageViewCreateInfo) {
+						.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+							.image = srcImage,
+							.viewType = radv_meta_get_view_type(src_image),
+							.format = src_image->vk_format,
+							.subresourceRange = {
+							.aspectMask = src_res->aspectMask,
+							.baseMipLevel = src_res->mipLevel,
+							.levelCount = 1,
+							.baseArrayLayer = src_array_slice,
+							.layerCount = 1
+						},
+					});
 			meta_emit_blit(cmd_buffer,
 				       src_image, &src_iview,
 				       src_offset_0, src_offset_1,
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -513,35 +513,38 @@ vtn_pointer_to_offset(struct vtn_builder *b, struct vtn_pointer *ptr,
   *index_out = get_vulkan_resource_index(b, ptr, &type, &idx);

   nir_ssa_def *offset = nir_imm_int(&b->nb, 0);
-   for (; idx < ptr->chain->length; idx++) {
-      enum glsl_base_type base_type = glsl_get_base_type(type->type);
-      switch (base_type) {
-      case GLSL_TYPE_UINT:
-      case GLSL_TYPE_INT:
-      case GLSL_TYPE_UINT64:
-      case GLSL_TYPE_INT64:
-      case GLSL_TYPE_FLOAT:
-      case GLSL_TYPE_DOUBLE:
-      case GLSL_TYPE_BOOL:
-      case GLSL_TYPE_ARRAY:
-         offset = nir_iadd(&b->nb, offset,
-                           vtn_access_link_as_ssa(b, ptr->chain->link[idx],
-                                                  type->stride));

-         type = type->array_element;
-         break;
+   if (ptr->chain) {
+      for (; idx < ptr->chain->length; idx++) {
+         enum glsl_base_type base_type = glsl_get_base_type(type->type);
+         switch (base_type) {
+         case GLSL_TYPE_UINT:
+         case GLSL_TYPE_INT:
+         case GLSL_TYPE_UINT64:
+         case GLSL_TYPE_INT64:
+         case GLSL_TYPE_FLOAT:
+         case GLSL_TYPE_DOUBLE:
+         case GLSL_TYPE_BOOL:
+         case GLSL_TYPE_ARRAY:
+            offset = nir_iadd(&b->nb, offset,
+                              vtn_access_link_as_ssa(b, ptr->chain->link[idx],
+                                                     type->stride));

-      case GLSL_TYPE_STRUCT: {
-         assert(ptr->chain->link[idx].mode == vtn_access_mode_literal);
-         unsigned member = ptr->chain->link[idx].id;
-         offset = nir_iadd(&b->nb, offset,
-                           nir_imm_int(&b->nb, type->offsets[member]));
-         type = type->members[member];
-         break;
-      }
+            type = type->array_element;
+            break;

-      default:
-         unreachable("Invalid type for deref");
+         case GLSL_TYPE_STRUCT: {
+            assert(ptr->chain->link[idx].mode == vtn_access_mode_literal);
+            unsigned member = ptr->chain->link[idx].id;
+            offset = nir_iadd(&b->nb, offset,
+                              nir_imm_int(&b->nb, type->offsets[member]));
+            type = type->members[member];
+            break;
+         }
+
+         default:
+            unreachable("Invalid type for deref");
+         }
      }
   }

--- a/src/gallium/auxiliary/util/u_resource.c
+++ b/src/gallium/auxiliary/util/u_resource.c
@@ -42,6 +42,7 @@ util_resource_size(const struct pipe_resource *res)
   unsigned depth = res->depth0;
   unsigned size = 0;
   unsigned level;
+   unsigned samples = MAX2(1, res->nr_samples);

   for (level = 0; level <= res->last_level; level++) {
      unsigned slices;
@@ -54,7 +55,7 @@ util_resource_size(const struct pipe_resource *res)
         slices = res->array_size;

      size += (util_format_get_nblocksy(res->format, height) *
-               util_format_get_stride(res->format, width) * slices);
+               util_format_get_stride(res->format, width) * slices * samples);

      width  = u_minify(width, 1);
      height = u_minify(height, 1);
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3230,6 +3230,7 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader
 	r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
 			 S_028844_NUM_GPRS(rshader->bc.ngpr) |
 			 S_028844_PRIME_CACHE_ON_DRAW(1) |
+			 S_028844_DX10_CLAMP(1) |
 			 S_028844_STACK_SIZE(rshader->bc.nstack));
 	/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */

@@ -3250,6 +3251,7 @@ void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader

 	r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
 			       S_028890_NUM_GPRS(rshader->bc.ngpr) |
+			       S_028890_DX10_CLAMP(1) |
 			       S_028890_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
 			       shader->bo->gpu_address >> 8);
@@ -3312,6 +3314,7 @@ void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader

 	r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
 			       S_028878_NUM_GPRS(rshader->bc.ngpr) |
+			       S_028878_DX10_CLAMP(1) |
 			       S_028878_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
 			       shader->bo->gpu_address >> 8);
@@ -3352,6 +3355,7 @@ void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader
 			       S_0286C4_VS_EXPORT_COUNT(nparams - 1));
 	r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
 			       S_028860_NUM_GPRS(rshader->bc.ngpr) |
+			       S_028860_DX10_CLAMP(1) |
 			       S_028860_STACK_SIZE(rshader->bc.nstack));
 	if (rshader->vs_position_window_space) {
 		r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
@@ -3386,6 +3390,7 @@ void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader
 	r600_init_command_buffer(cb, 32);
 	r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
 			       S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
+			       S_0288BC_DX10_CLAMP(1) |
 			       S_0288BC_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
 			       shader->bo->gpu_address >> 8);
@@ -3399,6 +3404,7 @@ void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader
 	r600_init_command_buffer(cb, 32);
 	r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
 			       S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
+			       S_0288D4_DX10_CLAMP(1) |
 			       S_0288D4_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
 			       shader->bo->gpu_address >> 8);
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -9091,8 +9091,9 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
 	[TGSI_OPCODE_DP3]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DP4]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DST]	= { ALU_OP0_NOP, tgsi_opdst},
-	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN, tgsi_op2},
-	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX, tgsi_op2},
+	/* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
+	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN_DX10, tgsi_op2},
+	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX_DX10, tgsi_op2},
 	[TGSI_OPCODE_SLT]	= { ALU_OP2_SETGT, tgsi_op2_swap},
 	[TGSI_OPCODE_SGE]	= { ALU_OP2_SETGE, tgsi_op2},
 	[TGSI_OPCODE_MAD]	= { ALU_OP3_MULADD_IEEE, tgsi_op3},
@@ -9289,8 +9290,8 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
 	[TGSI_OPCODE_DP3]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DP4]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DST]	= { ALU_OP0_NOP, tgsi_opdst},
-	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN, tgsi_op2},
-	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX, tgsi_op2},
+	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN_DX10, tgsi_op2},
+	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX_DX10, tgsi_op2},
 	[TGSI_OPCODE_SLT]	= { ALU_OP2_SETGT, tgsi_op2_swap},
 	[TGSI_OPCODE_SGE]	= { ALU_OP2_SETGE, tgsi_op2},
 	[TGSI_OPCODE_MAD]	= { ALU_OP3_MULADD_IEEE, tgsi_op3},
@@ -9512,8 +9513,8 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
 	[TGSI_OPCODE_DP3]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DP4]	= { ALU_OP2_DOT4_IEEE, tgsi_dp},
 	[TGSI_OPCODE_DST]	= { ALU_OP0_NOP, tgsi_opdst},
-	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN, tgsi_op2},
-	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX, tgsi_op2},
+	[TGSI_OPCODE_MIN]	= { ALU_OP2_MIN_DX10, tgsi_op2},
+	[TGSI_OPCODE_MAX]	= { ALU_OP2_MAX_DX10, tgsi_op2},
 	[TGSI_OPCODE_SLT]	= { ALU_OP2_SETGT, tgsi_op2_swap},
 	[TGSI_OPCODE_SGE]	= { ALU_OP2_SETGE, tgsi_op2},
 	[TGSI_OPCODE_MAD]	= { ALU_OP3_MULADD_IEEE, tgsi_op3},
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2546,6 +2546,12 @@ void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
 	r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
 	r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
 			 S_028850_NUM_GPRS(rshader->bc.ngpr) |
+	/*
+	 * docs are misleading about the dx10_clamp bit. This only affects
+	 * instructions using CLAMP dst modifier, in which case they will
+	 * return 0 with this set for a NaN (otherwise NaN).
+	 */
+			 S_028850_DX10_CLAMP(1) |
 			 S_028850_STACK_SIZE(rshader->bc.nstack) |
 			 S_028850_UNCACHED_FIRST_INST(ufi));
 	r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
@@ -2595,6 +2601,7 @@ void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
 			       S_0286C4_VS_EXPORT_COUNT(nparams - 1));
 	r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
 			       S_028868_NUM_GPRS(rshader->bc.ngpr) |
+			       S_028868_DX10_CLAMP(1) |
 			       S_028868_STACK_SIZE(rshader->bc.nstack));
 	if (rshader->vs_position_window_space) {
 		r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
@@ -2679,6 +2686,7 @@ void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha

 	r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
 			       S_02887C_NUM_GPRS(rshader->bc.ngpr) |
+			       S_02887C_DX10_CLAMP(1) |
 			       S_02887C_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
 	/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
@@ -2693,6 +2701,7 @@ void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *sha

 	r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
 			       S_028890_NUM_GPRS(rshader->bc.ngpr) |
+			       S_028890_DX10_CLAMP(1) |
 			       S_028890_STACK_SIZE(rshader->bc.nstack));
 	r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
 	/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
--- a/src/gallium/drivers/r600/sb/sb_expr.cpp
+++ b/src/gallium/drivers/r600/sb/sb_expr.cpp
@@ -753,7 +753,9 @@ bool expr_handler::fold_alu_op2(alu_node& n) {
 				n.bc.src[0].abs == n.bc.src[1].abs) {
 			switch (n.bc.op) {
 			case ALU_OP2_MIN: // (MIN x, x) => (MOV x)
+			case ALU_OP2_MIN_DX10:
 			case ALU_OP2_MAX:
+			case ALU_OP2_MAX_DX10:
 				convert_to_mov(n, v0, n.bc.src[0].neg, n.bc.src[0].abs);
 				return fold_alu_op1(n);
 			case ALU_OP2_ADD:  // (ADD x, x) => (MUL x, 2)
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -252,8 +252,8 @@ static void rvce_destroy(struct pipe_video_codec *encoder)
 		rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
 		enc->fb = &fb;
 		enc->session(enc);
-		enc->feedback(enc);
 		enc->destroy(enc);
+		enc->feedback(enc);
 		flush(enc);
 		rvid_destroy_buffer(&fb);
 	}
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -888,7 +888,9 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
      if (const_offset) {
         offset_reg = brw_imm_ud(const_offset->u32[0] & ~15);
      } else {
-         offset_reg = get_nir_src(instr->src[1], nir_type_uint32, 1);
+         offset_reg = src_reg(this, glsl_type::uint_type);
+         emit(MOV(dst_reg(offset_reg),
+                  get_nir_src(instr->src[1], nir_type_uint32, 1)));
      }

      src_reg packed_consts;
--- a/src/mesa/drivers/x11/fakeglx.c
+++ b/src/mesa/drivers/x11/fakeglx.c
@@ -2836,7 +2836,8 @@ Fake_glXCreateContextAttribs(Display *dpy, GLXFBConfig config,
         profileFlags = attrib_list[i + 1];
         break;
      default:
-         fprintf(stderr, "Bad attribute in glXCreateContextAttribs()\n");
+         _mesa_warning(NULL, "Unexpected attribute 0x%x in "
+                       "glXCreateContextAttribs()\n", attrib_list[i]);
         return 0;
      }
   }
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -51,8 +51,9 @@ libmesautil_la_LIBADD = \

 u_atomic_test_LDADD = libmesautil.la
 roundeven_test_LDADD = -lm
+mesa_sha1_test_LDADD = libmesautil.la

-check_PROGRAMS = u_atomic_test roundeven_test
+check_PROGRAMS = u_atomic_test roundeven_test mesa-sha1_test
 TESTS = $(check_PROGRAMS)

 BUILT_SOURCES = $(MESA_UTIL_GENERATED_FILES)
--- a/src/util/SConscript
+++ b/src/util/SConscript
@@ -53,3 +53,10 @@ roundeven_test = env.Program(
    source = ['roundeven_test.c'],
 )
 env.UnitTest("roundeven_test", roundeven_test)
+
+env.Prepend(LIBS = [mesautil])
+mesa_sha1_test = env.Program(
+    target = 'mesa-sha1_test',
+    source = ['mesa-sha1_test.c'],
+)
+env.UnitTest("mesa-sha1_test", mesa_sha1_test)
--- a/src/util/mesa-sha1_test.c
+++ b/src/util/mesa-sha1_test.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "macros.h"
+#include "mesa-sha1.h"
+
+#define SHA1_LENGTH 40
+
+int main(int argc, char *argv[])
+{
+   static const struct {
+      const char *string;
+      const char *sha1;
+   } test_data[] = {
+      {"Mesa Rocks! 273", "7fb99737373d65a73f049cdabc01e73aa6bc60f3"},
+      {"Mesa Rocks! 300", "b2180263e37d3bed6a4be0afe41b1a82ebbcf4c3"},
+      {"Mesa Rocks! 583", "7fb9734108a62503e8a149c1051facd7fb112d05"},
+   };
+
+   bool failed = false;
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(test_data); i++) {
+      unsigned char sha1[20];
+      _mesa_sha1_compute(test_data[i].string, strlen(test_data[i].string),
+                         sha1);
+
+      char buf[41];
+      _mesa_sha1_format(buf, sha1);
+
+      if (memcmp(test_data[i].sha1, buf, SHA1_LENGTH) != 0) {
+         printf("For string \"%s\", length %zu:\n"
+                "\tExpected: %s\n\t     Got: %s\n",
+                test_data[i].string, strlen(test_data[i].string),
+                test_data[i].sha1, buf);
+         failed = true;
+      }
+   }
+
+   return failed;
+}
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -27,7 +27,7 @@
 #ifndef U_ENDIAN_H
 #define U_ENDIAN_H

-#if defined(__GLIBC__) || defined(ANDROID)
+#if defined(__GLIBC__) || defined(ANDROID) || defined(__CYGWIN__)
 #include <endian.h>

 #if __BYTE_ORDER == __LITTLE_ENDIAN
@@ -64,6 +64,10 @@
 # define PIPE_ARCH_BIG_ENDIAN
 #endif

+#elif defined(_MSC_VER)
+
+#define PIPE_ARCH_LITTLE_ENDIAN
+
 #endif

 #endif
Author	SHA1	Message	Date
Andres Gomez	3281775ab9	docs: add sha256 checksums for 17.2.8 Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-23 00:54:11 +02:00
Andres Gomez	3482790712	docs: add release notes for 17.2.8 Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-22 22:39:47 +02:00
Andres Gomez	fb618171b6	Update version to 17.2.8 Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-22 22:34:12 +02:00
Andres Gomez	d9dd945d5c	cherry-ignore: r600: set DX10_CLAMP for compute shader too extra: The commit references a previous commit in which the changes should have been included but, as clarified by the developer, it is not needed for stable. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-20 19:40:38 +02:00
Andres Gomez	03538c210f	cherry-ignore: main: Clear shader program data whenever ProgramBinary is called extra: The commit just references a fix for an additional change in its v2. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-20 19:40:38 +02:00
Andres Gomez	dd0b6dfd91	cherry-ignore: radv: port merge tess info from anv fixes: This commit addressed earlier commit `d1c9f30d7f` which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-20 19:40:38 +02:00
Andres Gomez	fb342ac0c8	cherry-ignore: added 17.3 nominations. stable: 17.3 nominations only. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-20 19:40:38 +02:00
Andres Gomez	aa8742864a	cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation override. stable: This commit addressed earlier commit `ead0dfe31e` which did not land in branch. Signed-off-by: Andres Gomez <agomez@igalia.com>	2017-12-20 19:40:38 +02:00
Iago Toral Quiroga	5226e37717	i965/vec4: use a temp register to compute offsets for pull loads 64-bit pull loads are implemented by emitting 2 separate 32-bit pull load messages, where the second message loads from an offset at +16B. That addition of 16B to the original offset should not alter the original offset register used as source for the pull load instruction though, since the compiler might use that same offset register in other instructions (for example, for other pull loads in the shader code that take that same offset as reference). If the pull load is 32-bit then we only need to emit one message and we don't need to do offset calculations, but in that case the optimizer should be able to drop the redundant MOV. Fixes the following test on Haswell: KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103007 (cherry picked from commit `8620f7ebbc`)	2017-12-20 19:40:38 +02:00
Bas Nieuwenhuizen	a8ee722262	radv: Fix multi-layer blits. We did not set the layer correctly for the dst, as we would keep using the base layer. Same for the source image. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710 CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `b42e106d4d`)	2017-12-20 19:40:38 +02:00
Brian Paul	334ae3b0d2	gallium/aux: include nr_samples in util_resource_size() computation This function is only used in two places: 1. VMware driver, but only for HUD reporting 2. st/nine state tracker, used for texture memory accounting Fixes: `a69efa9482` ("util: add new util_resource_size() function in u_resource.[ch]") Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `dde8309cde`)	2017-12-20 19:40:38 +02:00
Roland Scheidegger	3730b04e81	r600: use DX10_CLAMP bit in shader setup The docs are not very concise in what this really does, however both Alex Deucher and Nicolai Hähnle suggested this only really affects instructions using the CLAMP output modifier, and I've confirmed that with the newly changed piglit isinf_and_isnan test. So, with this bit set, if an instruction has the CLAMP modifier bit (which clamps to [0,1]) set, then NaNs will be converted to zero, otherwise the result will be NaN. D3D10 would require this, glsl doesn't have modifiers (with mesa clamp(x,0,1) would get converted to such a modifier) coupled with a whatever-floats-your-boat specified NaN behavior, but the clamp behavior should probably always be used (this also matches what a decomposition into min(1.0, max(x, 0.0)) would do, if min/max also adhere to the ieee spec of picking the non-nan result). Some apps may in fact rely on this, as this prevents misrenderings in This War of Mine since using ieee muls (`ce7a045fee`), without having to use clamped rcp opcode, which would also fix this bug there. radeonsi also seems to set this bit nowadays if I see that righ (albeit the llvm amdgpu code comment now says "Make clamp modifier on NaN input returns 0" instead of "Do not clamp NAN to 0" since it was changed, which also looks a bit misleading). v2: set it in all shader stages. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544 Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `3835009796`)	2017-12-20 19:40:38 +02:00
Roland Scheidegger	5ffdc3a2b2	r600: use min_dx10/max_dx10 instead of min/max I believe this is the safe thing to do, especially ever since the driver actually generates NaNs for muls too. The ISA docs are not very helpful here, however the dx10 versions will pick a non-nan result over a NaN one (this is also the ieee754 behavior), whereas the non-dx10 ones will pick the NaN (verified by newly changed piglit isinf-and-isnan test). Other "modern" drivers will most likely do the same. This was shown to make some difference for bug 103544, albeit it is not required to fix it. Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `aab0bfc648`)	2017-12-20 19:40:38 +02:00
Brian Paul	9f94d6aa65	xlib: call _mesa_warning() instead of fprintf() We use _mesa_warning() everywhere else in this code. Change requested by Rick Irons of Mathworks. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit `7a46063803`)	2017-12-20 19:40:38 +02:00
Bas Nieuwenhuizen	8f8b5c0ad3	spirv: Fix loading an entire block at once. There is no chain, so checking the length ends with a SEGFAULT. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103579 Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit `b926da241a`) [Andres Gomez: 16 bits types and vtn_assert/fail not yet in 17.2] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/compiler/spirv/vtn_variables.c	2017-12-20 19:40:38 +02:00
Leo Liu	2e6593806c	radeon/vce: move destroy command before feedback command VCE processing IBs starts from session and task info at first level, other commands processed subsequently. The task info for destroy is embedded to destroy command, resulting that feedback command is not properly procoessed. This is causing kernel spin VM fault messages on Polaris and Vega10 card when running ends at encode application. The fix is also verified on VCE physical mode card. Signed-off-by: Leo Liu <leo.liu@amd.com> Cc: mesa-stable@lists.freedesktop.org Acked-by: Christian König <christian.koenig@amd.com> (cherry picked from commit `6d74cb2570`)	2017-12-20 19:40:38 +02:00
Matt Turner	e0160dd368	util: Add a SHA1 unit test program Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `513d7ffa23`) (cherry picked from commit `60ed1a07f2`) Squashed with: util: scons: wire up the sha1 test Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Andres Gomez <agomez@igalia.com> (cherry picked from commit `5d03a68640`) (cherry picked from commit `455ff75892`)	2017-12-20 19:40:22 +02:00
Matt Turner	2186a9ee6b	util: Assume little endian in the absence of platform-specific handling (cherry picked from commit `6a353479a7`) Squashed with: util: Use preprocessor correctly Fixes: `6a353479a7` ("util: Assume little endian in the absence of platform-specific handling") (cherry picked from commit `b8cbad624b`) Squashed with: util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC MSVC doesn't support #warning?! Getting really tired of this. (cherry picked from commit `676761252b`) Squashed with: util: Also include endian.h on cygwin If u_endian.h can't determine the endianess, the default behaviour in sha1.c is to build for big-endian Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit `2c62ccb10a`)	2017-12-20 16:16:47 +02:00
Emil Velikov	9ca5f55786	docs: add sha256 checksums for 17.2.7 Signed-off-by: Emil Velikov <emil.velikov@collabora.com>	2017-12-14 13:49:09 +00:00
@@ -1 +1 @@
 .2.7
 .2.8