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Author SHA1 Message Date
Andres Gomez
ae52410bf0 docs: add release notes for 17.2.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-10 15:33:58 +02:00
Andres Gomez
2c582b4cf7 Update version to 17.2.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-10 15:24:51 +02:00
Andres Gomez
0195b78aa7 cherry-ignore: automake: include git_sha1.h.in in release tarball
fixes: This commit has more than one Fixes tag but the commit it
addresses didn't land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:45:28 +02:00
Andres Gomez
a23bd4ea87 cherry-ignore: added 17.3 nominations.
stable: 17.3 nominations only.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:44:48 +02:00
Andres Gomez
27cd0abe8e cherry-ignore: intel/fs: Alloc pull constants off mem_ctx
stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:44:44 +02:00
Andres Gomez
b5dc8c43aa cherry-ignore: etnaviv: don't do resolve-in-place without valid TS
stable: This commit addressed earlier commit 78ade65956 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:44:38 +02:00
Andres Gomez
526ecbe417 cherry-ignore: i965: fix blorp stage_prog_data->param leak
stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:42:55 +02:00
Andres Gomez
0d91d13564 cherry-ignore: radv: copy indirect lowering settings from radeonsi
fixes: remove 6ce550453f and 059434e1763, which were depending in now
backported 087e010b2b.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-11-07 18:35:54 +02:00
Tomasz Figa
fd0cf2c946 glsl: Allow precision mismatch on dead data with GLSL ES 1.00
Commit 259fc50545 added linker error for
mismatching uniform precision, as required by GLES 3.0 specification and
conformance test-suite.

Several Android applications, including Forge of Empires, have shaders
which violate this rule, on a dead varying that will be eliminated.
The problem affects a big number of applications using Cocos2D engine
and other GLES implementations accept this, this poses a serious
application compatibility issue.

Starting from GLSL ES 3.0, declarations with conflicting precision
qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
clearly specify the behavior, except that

  "Uniforms are defined to behave as if they are using the same storage in
  the vertex and fragment processors and may be implemented this way.
  If uniforms are used in both the vertex and fragment shaders, developers
  should be warned if the precisions are different. Conversion of
  precision should never be implicit."

The word "used" is not clear in this context and might refer to
 1) declared (same as GLES 3.x)
 2) referred after post-processing, or
 3) linked after all optimizations are done.

Looking at existing applications, 2) or 3) seems to be widely adopted.
To avoid compatibility issues, turn the error into a warning if GLSL ES
version is lower than 3.0 and the data is dead in at least one of the
shaders.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97532
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 0886be093f)
2017-11-07 18:35:54 +02:00
Bas Nieuwenhuizen
6a73458510 radv: Disallow indirect outputs for GS on GFX9 as well.
Since it also uses the output vector before writing to memory.

Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit c07d719e8b)
[Bas Nieuwenhuizen: resolve conflicts]

Conflicts:
        src/amd/vulkan/radv_shader.c
2017-11-07 18:35:54 +02:00
Bas Nieuwenhuizen
9ba45e7d33 radv: Don't use vgpr indexing for outputs on GFX9.
Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.

Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6ce550453f)
[Bas Nieuwenhuizen: resolve conflicts]

Conflicts:
        src/amd/vulkan/radv_shader.c
2017-11-07 18:35:54 +02:00
Timothy Arceri
662cff8fe4 radv: copy indirect lowering settings from radeonsi
It looks the original indirect mask was probably copied from
ANV.

Sascha Willems demo results:

tessellation ~4000 -> ~4200 fps

V2: continue lowering local indirects due to llvm deficiencies.

(cherry picked from commit 087e010b2b)
[Bas Nieuwenhuizen: patch is a backport for 17.2 of the cherry-pick above]
2017-11-07 18:35:54 +02:00
Dave Airlie
0b0b7f1833 radv: add initial copy descriptor support. (v2)
It appears the latest dota2 vulkan uses this,
and we get a hang in VR mode without it.

v2: remove finishme I left in after finishing.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4bcb48b831)
2017-11-07 18:35:54 +02:00
Dave Airlie
23eaeeb88a radv: free attachments on end command buffer.
If we allocate attachments in the begin command buffer due to the
render pass continue bit, we were leaking them.

Since renderpasses inside a cmd buffer malloc/free these properly,
and set to NULL, we just need to call free at end.

Fixes a memory leak with multithreading demo.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f0ae06a13c)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/amd/vulkan/radv_cmd_buffer.c
2017-11-07 18:35:54 +02:00
Dave Airlie
d8e0f66b55 i915g: make gears run again.
We need to validate some structs exist before we dirty the states, and
avoid the problem in some other places.

Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
(cherry picked from commit cc69f2385e)
2017-11-07 18:35:54 +02:00
Bas Nieuwenhuizen
bd2037da82 radv: Don't expose heaps with 0 memory.
It confuses CTS. This pregenerates the heap info into the
physical device, so we can use it for translating contiguous
indices into our "standard" ones.

This also makes the WSI a bit smarter in case the first preferred
heap does not exist.

Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 806721429a)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/amd/vulkan/radv_device.c
	src/amd/vulkan/radv_private.h
	src/amd/vulkan/radv_wsi.c
2017-11-07 18:35:54 +02:00
Eric Engestrom
388b68a61e vc4: fix release build
Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
to explicitly compile this code out.

Fixes: 3df7892878 "vc4: Drop reloc_count tracking for debug
       asserts on non-debug builds."
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 5d44e35a8f)
2017-11-07 18:35:54 +02:00
Gert Wollny
71a33028ba r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling
It is possible that the optimizer ends up in an infinite loop in
post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group()
does not find a proper scheduling. This can be deducted from
pending.count() being larger than zero and not getting smaller.

This patch works around this problem by signalling this failure so that the
optimizers bails out and the un-optimized shader is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 69eee511c6)
2017-11-07 18:35:53 +02:00
Neil Roberts
f33f5e9ad6 nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB
Previously the values were calculated by just shifting ~0 by the
invocation ID. This would end up including bits that are higher than
gl_SubGroupSizeARB. The corresponding CTS test effectively requires that
these high bits be zero so it was failing. There is a Piglit test as
well but this appears to checking the wrong values so it passes.

For the two greater-than bitmasks, this patch adds an extra mask with
(~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero.

Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Neil Roberts <nroberts@igalia.com>
(cherry picked from commit b697ece10a)
2017-11-07 18:35:53 +02:00
Nanley Chery
af1dc1cf87 i965: Check CCS_E compatibility for texture view rendering
Only use CCS_E to render to a texture that is CCS_E-compatible with the
original texture's miptree (linear) format. This prevents render
operations from writing data that can't be decoded with the original
miptree format.

On Gen10, with the new CCS_E-enabled formats handled, this enables the
driver to pass the arb_texture_view-rendering-formats piglit test.

v2. Add a TODO for texturing. (Jason)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 9e849eb8bb)
2017-11-07 18:35:53 +02:00
Topi Pohjolainen
3d7546a312 intel/compiler/gen9: Pixel shader header only workaround
Fixes intermittent GPU hangs on Broxton with an Intel internal
test case.

There are plenty of similar fragment shaders in piglit that do
not use any varyings and any uniforms. According to the
documentation special timing is needed between pipeline stages.
Apparently we just don't hit that with piglit. Even with the
failing test case one doesn't always get the hang.

Moreover, according to the error states the hang happens
significantly later than the execution of the problematic shader.
There are multiple render cycles (primitive submissions) in between.
I've also seen error states where the ACTHD points outside the
batch. Almost as if the hardware writes somewhere that gets used
later on. That would also explain why piglit doesn't suffer from
this - most tests kick off one render cycle and any corruption
is left unseen.

v2 (Ken): Instead of enabling push constants, enable one of the
          inputs (PSIZ).
v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe()
                 happy.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit 97e01adfd5)
2017-11-07 18:35:53 +02:00
Kenneth Graunke
67fc6d43bd mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.
According to the ARB_ES3_1_compatibility specification,
glGetFramebufferAttachmentParameteriv is supposed to accept BACK,
and it behaves exactly like BACK_LEFT.

Fixes a GL error in GFXBench 5 Aztec Ruins.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 4f538c3f99)
2017-11-07 18:35:53 +02:00
Tapani Pälli
71ea414782 i965: unref push_const_bo in intelDestroyContext
Valgrind shows that leak is caused by gen6_upload_push_constant, add
unref push_const_bo per stage to destructor to fix this (like done for
scratch_bo).

   ==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66
   ==10952==    at 0x4C30A1E: calloc (vg_replace_malloc.c:711)
   ==10952==    by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344)
   ==10952==    by 0x8C425C4: intel_upload_space (intel_upload.c:101)
   ==10952==    by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154)

v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil)

Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0b131ca427)
2017-11-07 18:35:53 +02:00
Jason Ekstrand
e7ddddc989 i965/miptree: Take an isl_format in render_aux_usage
Not all rendering matches the miptree format.  We allow rendering to
texture views so there are cases where it may not match.  In those
cases, our current scheme of just passing the value of ctx->sRGBEnabled
isn't viable.  Instead, just do what we do for texturing and pass the
view format in directly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 39c5c12f8f)
[Andres Gomez: remove code which was trivially modified previously]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/mesa/drivers/dri/i965/brw_draw.c
	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2017-11-07 18:35:53 +02:00
Jason Ekstrand
6dc8e69da6 i965/blorp: Use more temporary isl_format variables
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 78e50185d6)
2017-11-07 18:35:53 +02:00
Jason Ekstrand
78ff359d04 i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 94389943b6)
2017-11-07 18:35:53 +02:00
Jason Ekstrand
9e27cdc771 spirv: Claim support for the simple memory model
It's rather surprising that we've never actually hit this before.
Aparently, Ian's SPIR-V generator currently claims the Simple when you
don't do anything complex.  We really shouldn't assert-fail on it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8ab9820d34)
2017-11-07 18:35:53 +02:00
Leo Liu
1317bdc3a1 radeon/video: add gfx9 offsets when rejoin the video surface
For CPU access.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit ea3dc75d72)
2017-11-07 18:35:53 +02:00
Nicolai Hähnle
e95c4af12d amd/common/gfx9: workaround DCC corruption more conservatively
Fixes KHR-GL45.texture_swizzle.smoke and others on Vega.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f9ccfda9bc)
2017-11-07 18:35:53 +02:00
Marek Olšák
d132c0d792 ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 759526813b)
2017-11-07 18:35:53 +02:00
Marek Olšák
e28870b9fe st/dri: don't expose modifiers in EGL if the driver doesn't implement them
This unbreaks waffle/gbm (piglit/gbm) which fails initialization.

v2: also don't set queryDmaBufFormats

Reviewed-by: Daniel Stone <daniel@fooishbar.org>
(cherry picked from commit a65db0ad1c)
2017-11-07 18:35:53 +02:00
Andres Gomez
1b10d0851a docs: add sha256 checksums for 17.2.4
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-30 16:53:44 +02:00
Andres Gomez
a4b72e2643 docs: add release notes for 17.2.4
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-30 16:46:20 +02:00
Andres Gomez
fe9dc0fad6 Update version to 17.2.4
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-30 16:37:54 +02:00
Andres Gomez
162fa27b12 cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.
extra: Commit is not applicable when ade416d023 is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
b3207d9ff7 cherry-ignore: mesa/bufferobj: don't double negate the range
fixes: This commit addressed earlier commit 35ac13ed3 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
6cab29e973 cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.
fixes: Commit is not applicable when 6ce550453f is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
1c2f79066c cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.
fixes: Commit is not applicable when 087e010b2b is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
0c63d53765 cherry-ignore: added 17.3 nominations.
stable: 17.3 nominations only.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
52019bad1d cherry-ignore: glsl: fix derived cs variables
stable: Commit is too big for stable at this point.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Andres Gomez
9bdd943ff2 cherry-ignore: configure.ac: rework llvm detection and handling
stable: Commits are too invasive for 17.2.

Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-10-27 18:07:38 +03:00
Jason Ekstrand
1393d37d7b intel/eu: Use EXECUTE_1 for JMPI
The PRM says "The execution size must be 1."  In 73137997e2, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0).  Later, in dc2d3a7f5c, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator.  This commit fixes the
original bug and makes brw_JMPI just do the right thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e2
(cherry picked from commit 562b8d458c)
2017-10-27 18:07:38 +03:00
Jason Ekstrand
74f1903234 anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir
We currently have a bug where nir_lower_system_values gets called before
nir_lower_var_copies so it will miss any system value uses which come
from a copy_var intrinsic.  Moving it to after brw_preprocess_nir fixes
this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 279f8fb69c)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/intel/vulkan/anv_pipeline.c
2017-10-27 18:07:37 +03:00
Jason Ekstrand
aac0807f48 intel/fs: Handle flag read/write aliasing in needs_src_copy
In order to implement the ballot intrinsic, we do a MOV from flag
register to some GRF.  If that GRF is used in a SEL, cmod propagation
helpfully changes it into a MOV from the flag register with a cmod.
This is perfectly valid but when lower_simd_width comes along, it simply
splits into two instructions which both have conditional modifiers.
This is a problem since we're reading the flag register.  This commit
makes us check whether or not flags_written() overlaps with the flag
values that we are reading via the instruction source and, if we have
any interference, will force us to emit a copy of the source.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fa6e74e33e)
2017-10-27 18:07:37 +03:00
Jan Vesely
03f3899f99 clover: Fix compilation after clang r315871
v2: use a more generic compat function
v3: rename and formatting cleanup

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a6d38f476b)
2017-10-27 18:07:37 +03:00
Jason Ekstrand
87a9a989ee nir/intrinsics: Set the correct num_indices for load_output
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit c1b84256cc)
2017-10-27 18:07:37 +03:00
Matthew Nicholls
ce725baa7c ac/nir: generate correct instruction for atomic min/max on unsigned images
v2: fix silly typo

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 27a0b24bf2)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-10-27 18:07:37 +03:00
Bas Nieuwenhuizen
f46ba9ee35 ac/nir: Fix nir_texop_lod on GFX for 1D arrays.
Fixes: 1bcb953e16 'radv: handle GFX9 1D textures'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 2c5b43c87f)
2017-10-27 18:07:37 +03:00
Stefan Schake
2d51d41865 broadcom/vc4: Fix aliasing issue
This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.

Fixes: 14dc281c13 ("vc4: Enforce one-uniform-per-instruction after optimization.")
(cherry picked from commit e5fea0d621)
2017-10-27 18:07:37 +03:00
Kenneth Graunke
cbc081b871 i965: Revert absolute mode for constant buffer pointers.
The kernel doesn't initialize the value of the INSTPM or CS_DEBUG_MODE2
registers at context initialization time.  Instead, they're inherited
from whatever happened to be running on the GPU prior to first run of a
new context.  So, when we started setting these, other contexts in the
system started inheriting our values.  Since this controls whether
3DSTATE_CONSTANT_* takes a pointer or an offset, getting the wrong
setting is fatal for almost any process which isn't expecting this.

Unfortunately, VA-API and Beignet don't initialize this (nor does older
Mesa), so they will die horribly if we start doing this.  UXA and SNA
don't use any push constants, so they are unaffected.

Until we have some kind of solution to this problem, I'm going to revert
this patch and abandon using the feature for now.  It will lead to fewer
pushed UBO ranges on Broadwell+, which may lead to lower performance,
though I don't have any data on the impact.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102774
(cherry picked from commit 013d331220)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/mesa/drivers/dri/i965/brw_state_upload.c
	src/mesa/drivers/dri/i965/intel_screen.c
2017-10-27 18:07:24 +03:00
Michel Dänzer
546b4d455a st/mesa: Initialize textures array in st_framebuffer_validate
And just reference pipe_resources to it in the validate callbacks.

Avoids pipe_resource leaks when st_framebuffer_validate ends up calling
the validate callback multiple times, e.g. when a window is resized.

v2:
* Use generic stable tag instead of Fixes: tag, since the problem could
  already happen before the commit referenced in v1 (Thomas Hellstrom)
* Use memset to initialize the array on the stack instead of allocating
  the array with os_calloc.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
(cherry picked from commit 7561da367b)

Squashed with:

st/osmesa: include u_inlines.h for pipe_resource_reference

Fixes build failure due to unresolved symbol.

Fixes: 7561da367b "st/mesa: Initialize textures array in
                     st_framebuffer_validate"

Trivial.

(cherry picked from commit 8c9e7c9638)
2017-10-27 18:04:59 +03:00
Henri Verbeet
9cbf8c910e vulkan/wsi: Free the event in x11_manage_fifo_queues().
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
Fixes: e73d136a02 ("vulkan/wsi/x11: Implement FIFO mode.")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com
(cherry picked from commit 3de87f7cd7)
2017-10-27 18:04:59 +03:00
Dave Airlie
1eb4cbc934 radv/image: bump all the offset to uint64_t.
So one of the CTS tests tries to allocate a 16384x1 2048 array
texture. This overflows a bunch of calculations when we want it
tiled as the heights goes to 128.

addrlib returns us the correct size (16GB or so), but we mangle
it in the htile calcs due to the 32-bit offset fields, then
userspace gives us the reduced number and we try to allocate
it on a heap and things blow up.

We really need to give the app back the correct size for the
image so we can blow up properly in memory allocation later.

This should fix hangs in
dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint
since
Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.)

Now there's an open question if we should be enabling tc-compat
htile at all for shallow textures like the above.

This might cause some other wierd side effects in CTS even
without the tc compat so:
Cc: "17.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 35c66f3e40)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/amd/vulkan/radv_private.h
2017-10-27 18:04:59 +03:00
Marek Olšák
fba44d91d0 Revert "mesa: fix texture updates for ATI_fragment_shader"
This reverts commit 9d54025cd1.

It breaks KOTOR.

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 5d071bf04b)
2017-10-27 18:04:59 +03:00
Samuel Pitoiset
9cba4d491c radv: add the draw count buffer to the list of buffers
My guess is that the GPU is going to report VM faults if
vkCmdDrawIndirectCountAMD() (and friends) are used.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 3e5f27faf3)
2017-10-27 18:04:59 +03:00
Emil Velikov
facc851818 docs: add sha256 checksums for 17.2.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-19 13:28:13 +01:00
Emil Velikov
28dc4b64f2 docs: add release notes for 17.2.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-19 13:10:20 +01:00
Emil Velikov
ea38f4c33a Update version to 17.2.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-19 13:02:58 +01:00
Emil Velikov
23c08dabc3 eglmesaext: add forward declaration for struct wl_buffers
The user does not need to know the specifics of the struct, as only a
pointer to it is used.

Just forward declare the struct making the header self-contained.

v2: Remove deprecation warning text/bugzilla - patch does no help there.

Cc: Greg V <greg@unrelenting.technology>
Fixes: 5cddb1ce3c ("wayland: Add an extension to create wl_buffers from
EGLImages")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
(cherry picked from commit 66ebdfbd44)
2017-10-17 16:59:31 +01:00
Emil Velikov
dc9bd1dade wayland-drm: use a copy of the wayland_drm_callbacks struct
The callbacks may be called even when they are no longer valid.
Say, the user is dlclose(ing) libEGL while the buffers are being
destroyed.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Derek Foreman <derekf@osg.samsung.com>
(cherry picked from commit 0cfd6f6cfc)
2017-10-17 16:59:31 +01:00
Jason Ekstrand
d001ff1267 nir: Get rid of the variable on vote intrinsics
This looks like a copy+paste error.  They don't actually write into that
variable as would be implied by putting the return there.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 3442c9fc3e)
2017-10-17 16:59:31 +01:00
Jason Ekstrand
88a16c895b nir/opcodes: Fix constant-folding of ufind_msb
We didn't fold correctly in the case of 0x1 because we never let the
loop counter hit 0.  Switching it to bit >= 0 solves this problem.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit a0947921eb)
2017-10-17 16:59:31 +01:00
Jason Ekstrand
b640bf38ca glsl/blob: Return false from grow_to_fit if we've ever failed
Otherwise we could have a failure followed by a smaller write that
succeeds and get a corrupted blob.  If we ever OOM, we should stop.

v2 (Jason Ekstrand):
 - Initialize the new boolean member in create_blob

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit e03717efbd)
2017-10-17 16:59:31 +01:00
Jason Ekstrand
4d1ae3283c glsl/blob: Return false from ensure_can_read on overrun
Otherwise, if you have a large read fail and then try to do a small
read, the small read may succeed even though it's at the wrong offset.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 7118851374)
2017-10-17 16:59:31 +01:00
Eric Engestrom
d56aa9fe43 scons: use python3-compatible print()
These changes were generated using python's `2to3` tool.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102852
Reported-by: Alex Granni <liviuprodea@yahoo.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 7d48219b3a)
2017-10-17 16:59:31 +01:00
Bas Nieuwenhuizen
3b657e4ff5 radv: Only set the MTYPE flags on GFX9+.
Older kernels fail the va_op with this flag set. If the kernel
supports GFX9 usefully, it will also support this flag.

Fixes: e8d57802fe "radv/gfx9: allocate events from uncached VA space"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 96f80c8d4d)
2017-10-17 16:59:31 +01:00
Daniel Stone
99d3661bce egl/wayland: Don't use dmabuf with no modifiers
The dmabuf interface requires a valid modifier to be sent. If we don't
explicitly get a modifier from the driver, we can't know what to send;
it must be inferred from legacy side-channels (or assumed to linear, if
none exists).

If we have no modifier, then we can only have a single-plane format
anyway, so fall back to the old wl_drm buffer import path.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Andy Furniss <adf.lists@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit b65d6dafd6)
2017-10-17 16:59:31 +01:00
Daniel Stone
0f6e89dfe0 egl/wayland: Check queryImage return for wl_buffer
When creating a wl_buffer from a DRIImage, we extract all the DRIImage
information via queryImage. Check whether or not it actually succeeds,
either bailing out if the query was critical, or providing sensible
fallbacks for information which was not available in older DRIImage
versions.

Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them")
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Andy Furniss <adf.lists@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 6273d2f269)
2017-10-17 16:59:31 +01:00
Emil Velikov
bee97ec32e swr/rast: do not crash on NULL strings returned by getenv
The current convenience function GetEnv feeds the results of getenv
directly into std::string(). That is a bad idea, since the variable
may be unset, thus we feed NULL into the C++ construct.

The latter of which is not allowed and leads to a crash.

v2: Better variable name, implicit char* -> std::string conversion (Eric)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101832
Fixes: a25093de71 ("swr/rast: Implement JIT shader caching to disk")
Cc: Tim Rowley <timothy.o.rowley@intel.com>
Cc: Laurent Carlier <lordheavym@gmail.com>
Cc: Bernhard Rosenkraenzer <bero@lindev.ch>
[Emil Velikov: make an actual commit from the misc diff]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Laurent Carlier <lordheavym@gmail.com> (v1)
(cherry picked from commit 21e271024d)
2017-10-17 16:59:31 +01:00
Nicolai Hähnle
9f4b0a336c radeonsi: clamp border colors for upgraded depth textures
The hardware does this automatically for unorm formats, but we need to
do it manually for unorm depth formats that have been upgraded to
Z32_FLOAT.

Fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth
and others.

Fixes: d4d9ec55c5 ("radeonsi: implement TC-compatible HTILE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 6eb9483912)
2017-10-17 16:59:31 +01:00
Nicolai Hähnle
74a28d85de radeonsi: clamp depth comparison value only for fixed point formats
The hardware usually does this automatically. However, we upgrade
depth to Z32_FLOAT to enable TC-compatible HTILE, which means the
hardware no longer clamps the comparison value for us.

The only way to tell in the shader whether a clamp is required
seems to be to communicate an additional bit in the descriptor
table. While VI has some unused bits in the resource descriptor,
those bits have unfortunately all been used in gfx9. So we use
an unused bit in the sampler state instead.

Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f
and many other tests in dEQP-GLES3.functional.texture.shadow.*

Fixes: d4d9ec55c5 ("radeonsi: implement TC-compatible HTILE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 4c56e07029)
[Emil Velikov: handle lack of dirty_mask in original patch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeonsi/si_descriptors.c
2017-10-17 16:59:31 +01:00
Nicolai Hähnle
f805a61e04 st/glsl_to_tgsi: fix a use-after-free in merge_two_dsts
Found by address sanitizer.

The loop here tries to be safe, but in doing so, it ends up doing
exactly the wrong thing: the safe foreach is for when the loop
variable (inst) could be deleted and nothing else. However, this
particular can delete inst's successor, but not inst itself.

Fixes: 8c6a0ebaad ("st/mesa: add st fp64 support (v7.1)")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 2703fa613b)
2017-10-17 16:59:31 +01:00
Lionel Landwerlin
6957dfb0d8 anv: bo_cache: allow importing a BO larger than needed
It's not a problem if a BO has been allocated larger than we need it
to be.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102940
Fixes: 818b857914 ("anv: Use the BO cache for DeviceMemory allocations")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit c0a4f56fb9)
2017-10-17 16:59:31 +01:00
Nicolai Hähnle
410f4dbcb1 st/glsl_to_tgsi: fix indirect access to 64-bit integer
Make sure we actually allocate two adjacent TGSI temporaries. The
current code fails e.g. when an arithmetic operation has two
operands with indirect accesses.

I will send out a new piglit test
(arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 541208cf13)
2017-10-17 16:59:31 +01:00
Ilia Mirkin
d22e779d6a nv50,nvc0: fix push hint logic in presence of a start offset
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.

This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.

Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit b20bccbcac)
2017-10-17 16:59:31 +01:00
Dave Airlie
41ec2af2a8 radv: lower ffma in nir.
So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.

This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.

I'm reposting this one as Marek indicated he thinks this is what
we should be doing on AMD hw.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 2c61594d84)
[Emil Velikov: use correct file radv_shader.c -> radv_pipeline.c]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_shader.c
2017-10-17 16:59:31 +01:00
Alex Smith
0bd7be0142 radv: Add R16G16B16A16_SNORM fast clear support
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 25d76fd658)
2017-10-17 16:59:30 +01:00
Nicolai Hähnle
4bcadb533f st/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS
Applications might pass in a buffer that is sized too large and rely
on the extra space of the buffer not being overwritten.

Fixes dEQP-GLES31.functional.state_query.internal_format.partial_query.num_sample_counts

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 9a8f13a33b)
2017-10-17 16:59:30 +01:00
Ilia Mirkin
2eae2a6f0e nv50/ir: fix 64-bit integer shifts
TGSI was adjusted to always pass in 64-bit integers but nouveau was left
with the old semantics. Update to the new thing.

Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts)
Reported-by: Karol Herbst <karolherbst@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ce6da2a026)
2017-10-17 16:59:30 +01:00
Józef Kucia
077f925473 anv: Do not assert() on VK_ATTACHMENT_UNUSED
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 91ba331ef4)
2017-10-17 16:59:30 +01:00
Józef Kucia
2e92d16f9d spirv: Fix SpvOpAtomicISub
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit e0acb630a5)
2017-10-17 16:59:30 +01:00
Emil Velikov
83dcf9dc33 cherry-ignore: add "anv/wsi: Allocate enough memory for the entire image"
Addresses bug introduced with a feature patch, which is not in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-17 16:59:28 +01:00
Lionel Landwerlin
406e7e0e17 anv/cmd_buffer: Reset state in cmd_buffer_destroy
This ensures that everything gets cleaned up properly. In particular,
it fixes a memory leak where we were leaking the push constants
structs.

Valgrind stats on
dEQP-VK.pipeline.push_constant.graphics_pipeline.range_size_128 :

Before:
HEAP SUMMARY:
    in use at exit: 2,467,513 bytes in 1,305 blocks
  total heap usage: 697,853 allocs, 696,530 frees, 138,466,600 bytes allocated

LEAK SUMMARY:
   definitely lost: 1,068 bytes in 11 blocks
   indirectly lost: 24,669 bytes in 412 blocks
     possibly lost: 0 bytes in 0 blocks
   still reachable: 2,441,776 bytes in 882 blocks
        suppressed: 0 bytes in 0 blocks

After:
HEAP SUMMARY:
    in use at exit: 2,467,381 bytes in 1,304 blocks
  total heap usage: 697,853 allocs, 696,531 frees, 138,466,600 bytes allocated

LEAK SUMMARY:
   definitely lost: 936 bytes in 10 blocks
   indirectly lost: 24,669 bytes in 412 blocks
     possibly lost: 0 bytes in 0 blocks
   still reachable: 2,441,776 bytes in 882 blocks
        suppressed: 0 bytes in 0 blocks

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 0763f814d7)
2017-10-17 16:59:02 +01:00
Lionel Landwerlin
60466859fa anv/cmd_buffer: fix push descriptors with set > 0
When writing to set > 0, we were just wrongly writing to set 0. This
commit fixes this by lazily allocating each set as we write to them.

We didn't go for having them directly into the command buffer as this
would require an additional ~45Kb per command buffer.

v2: Allocate push descriptors from system memory rather than in BO
    streams. (Lionel)

Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Fixes: 9f60ed98e5 ("anv: add VK_KHR_push_descriptor support")
Reported-by: Daniel Ribeiro Maciel <daniel.maciel@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit d296dea54e)
2017-10-17 16:59:02 +01:00
Marek Olšák
014b5a7209 glsl_to_tgsi: fix instruction order for bindless textures
We emitted instructions loading the bindless handle after the memory
instruction.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 985338e2cb)
2017-10-17 16:59:02 +01:00
Jason Ekstrand
f9c4f22f5a intel/compiler: Don't propagate cmod into integer multiplies
No shader-db change on Sky Lake.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 7463d50580)
2017-10-17 16:59:02 +01:00
Jason Ekstrand
4ae1a62b26 intel/compiler: Don't cmod propagate into a saturated operation
Shader-db results on Sky Lake:

    total instructions in shared programs: 12954445 -> 12955125 (0.01%)
    instructions in affected programs: 141862 -> 142542 (0.48%)
    helped: 0
    HURT: 626

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit b91ecee04a)
2017-10-17 16:59:02 +01:00
Ben Crocker
ea3ad52ad3 gallivm/ppc64le: allow environmental control of Altivec code generation
In check_os_altivec_support(), allow control of Altivec (first PPC vector
instruction set) code generation via a new environmental control,
GALLIVM_ALTIVEC, which is expected to take on a value of 1 or 0.
The default is to enable Altivec code generation.

This environmental control of Altivec code generation is initially
available only #ifdef DEBUG.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 1359af930e)
2017-10-17 16:59:02 +01:00
Ben Crocker
3f5d2b768c gallivm/ppc64le: adjust VSX code generation control.
In lp_build_create_jit_compiler_for_module(), advance the minimum
version of LLVM for VSX code generation to 4.0; this is the minimum
revision at which several known VSX code generation bugs are fixed:

  https://llvm.org/bugs/show_bug.cgi?id=25503 (fixed in 3.8.1)
  https://llvm.org/bugs/show_bug.cgi?id=26775 (fixed in 3.8.1)
  https://llvm.org/bugs/show_bug.cgi?id=33531 (fixed in 4.0)

An llc performance bug introduced in LLVM 4.0,

  https://llvm.org/bugs/show_bug.cgi?id=34647

is still pending as of LLVM 5.0, but only has a pronounced effect on
one of the Piglit tests: ext_transform_feedback-max-varyings.

All changes tested via Piglit.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit e93f056a4e)
2017-10-17 16:59:02 +01:00
Ben Crocker
070d2dcfac gallivm: allow additional llc options
In init_native_targets, allow the passing of additional options to
the LLC compiler via new GALLIVM_LLC_OPTIONS environmental control.
This option is available only #ifdef DEBUG, initially.
At top, add #include <llvm-c/Support.h> for LLVMParseCommandLineOptions()
declaration.

v2: Fix compile error with old llvm versions (sroland)

Cc: "17.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 5c75f0c8bb)
2017-10-17 16:59:02 +01:00
Ben Crocker
1a8ccdc6e9 gallivm: fix typo in debug_printf message
In gallivm_compile_module, fix a typo in the
debug_printf("Invoke as \"llc ..." message.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 3a9feb4db8)
2017-10-17 16:59:02 +01:00
Leo Liu
608bea62ca st/va: don't re-allocate interlaced buffer with pakced format
It caused corruption, when vlVaPutImage putting raw data to the fields

v2: add RGB formats since it got uploaded here as well

Cc: mesa-stable@lists.freedesktop.org
Cc: Andy Furniss <adf.lists@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 0fa950ecd3)
2017-10-17 16:59:02 +01:00
Leo Liu
dc47b179ed st/vdpau: don't re-allocate interlaced buffer with packed YUV format
It caused corruption, when vlVdpVideoSurfacePutBitsYCbCr putting YUV to the fields

Cc: mesa-stable@lists.freedesktop.org
Cc: Andy Furniss <adf.lists@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 327480d10f)
2017-10-17 16:59:02 +01:00
Dave Airlie
1146591d4b radv: emit fmuladd instead of fma to llvm.
For Vulkan SPIR-V the spec states
fma() Inherited from OpFMul followed by OpFAdd.

Matt says the backend will do the right thing depending on the
hardware being compiled for, if you use the fmuladd intrinsic.

Using the Mad Max pts test, on high settings at 4K:
CHP: 55->60
HGDD: 46->50
LM: 55->60
No change on Stronghold.

Thanks to Feral for spending the time to track this down.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4e93d6baae)
[Emil Velikov: s/ac_to_float_type/to_float_type/]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-10-17 16:59:02 +01:00
Emil Velikov
76c6bbca7c cherry-ignore: add "anv: Remove unreachable cases from isl_format_for_size"
The commit causes a number of regressions with dEQP

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-17 16:57:45 +01:00
Lionel Landwerlin
3315bb4f08 intel: compiler: vec4: add missing default 0 lod
We set a similar default value for LOD in the fs backend for TXS/TXL.
Without this we end up generating invalid MOV with a null src.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit d3acc240d0)
2017-10-17 16:53:25 +01:00
Józef Kucia
cb72969d8b anv: Fix vkCmdFillBuffer()
The vkCmdFillBuffer() command fills a buffer with an uint32_t value.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 15fdbf9c39)
2017-10-11 17:44:36 +01:00
Marek Olšák
1093207463 st/mesa: don't use pipe_surface for passing information about EGLImage
Use st_egl_image instead. radeonsi doesn't like when we create
a pipe_surface with PIPE_FORMAT_NV12.

This fixes NV12 texturing on radeonsi using kmscube.

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 2d62817da9)
2017-10-11 17:44:36 +01:00
Bas Nieuwenhuizen
f5f515a023 nir/spirv: Allow loop breaks in a switch body.
Per the SPIR-V spec 2.11 Structured Control Flow:

"The only blocks in a construct that can branch outside the construct are

...
- a break block for the innermost loop it is inside of.
..."

With

"Break block: A block containing a branch to the Merge Block of a loop header's merge instruction."

Note that it puts no restriction on not being in an if or switch within the innermost loop.

This passes the loop_break block to the switch body so it can properly detect loop breaks.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit ef61d09d5b)
2017-10-11 17:44:36 +01:00
Rob Clark
18db986354 freedreno/a5xx: fix missing restore state
RB_CLEAR_CNTL seems to be in a funny state after boot (at least on
8x96/a530).

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit 7f3eab03fe)
2017-10-11 17:44:36 +01:00
Rob Clark
c386538036 freedreno/a5xx: align height to GMEM
Similar to the way width/pitch alignment works, it seems like we need to
do similar for height.  Otherwise the BLIT from system memory to GMEM
can over-fetch beyond the end of the buffer, triggering a fault.

I'm not sure if there is a better solution yet.  Possibly we could fall
back to pre-a5xx style DRAW packets for cases where BLIT might over-
fetch.  (We in theory have that problem already with rendering to higher
mipmap levels, although fortunately those tend to use GMEM bypass.)

This fixes issues reported with glamor.

Reported-by: don.harbin@linaro.org
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit 16ac70bdcf)
2017-10-11 17:44:36 +01:00
Nicolai Hähnle
d0b52003d0 radeonsi: fix maximum advertised point size / line width
The hardware registers store the half-size/width in 12.4 fixed point
format, so 8192 is the maximum.

Fixes dEQP-GLES3.functional.rasterization.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 30e37289ea)
2017-10-11 17:44:36 +01:00
Nicolai Hähnle
6e903ae7d5 radeonsi: deduce rast_prim correctly for tessellation point mode
Together with the previous patches, this fixes
dEQP-GLES31.functional.primitive_bounding_box.wide_points.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit a3fa3b2e02)
2017-10-11 17:44:36 +01:00
Nicolai Hähnle
6e3788e3b1 radeonsi: don't discard points and lines
This is a bit conservative, but a more precise solution requires access
to the rasterizer state. This is something to tackle after the fork between
r600 and radeonsi.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 4d74432dd3)
2017-10-11 17:44:36 +01:00
Nicolai Hähnle
05e2ed7889 radeonsi: move current_rast_prim to r600_common_context
We'll use it in the scissors / clip / guardband state.

v2: avoid a performance regression on r600 when applied to
    (pre-fork) stable branches

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f86a112b07)
2017-10-11 17:44:36 +01:00
Nicolai Hähnle
f2fc168517 glsl/lower_instruction: handle denorms and overflow in ldexp correctly
GLSL ES requires both, and while GLSL explicitly doesn't require correct
overflow handling, it does appear to require handling input inf/denorms
correctly.

Fixes dEQP-GLES31.functional.shaders.builtin_functions.precision.ldexp.*

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 93bf9c114b)
[Emil Velikov: init_num_operands() does not exist on branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/glsl/lower_instructions.cpp
2017-10-11 17:44:06 +01:00
Nicolai Hähnle
eac6932c66 util/queue: fix a race condition in the fence code
A tempting alternative fix would be adding a lock/unlock pair in
util_queue_fence_is_signalled. However, that wouldn't actually
improve anything in the semantics of util_queue_fence_is_signalled,
while making that test much more heavy-weight. So this lock/unlock
pair in util_queue_fence_destroy for "flushing out" other threads
that may still be in util_queue_fence_signal looks like the better
fix.

v2: rephrase the comment

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
(cherry picked from commit a208cd7ae4)
2017-10-11 17:22:55 +01:00
Nicolai Hähnle
7bedb1fd12 radeonsi/gfx9: fix geometry shaders without output vertices
Not that those are super common or useful, but hey! Fun corner cases
of the API...

Fixes dEQP-GLES31.functional.geometry_shading.emit.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 7dfa891f32)
2017-10-11 17:22:55 +01:00
Nicolai Hähnle
332f6e9b3b amd/common: fix build_cube_select
Fix the custom cube coord selection sequence to be identical to
the hardware v_cubesc/tc and OpenGL spec. Affects texture sampling
with user-provided derivatives.

Fixes dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 5be5c1e0fa)
2017-10-11 17:22:55 +01:00
Nicolai Hähnle
f5cbe1f9b8 st/glsl_to_tgsi: fix conditional assignments to packed shader outputs
Overriding the default (no-op) swizzle is clearly counter-productive,
since the whole point is putting the destination register as one of
the source operands so that it remains unmodified when the assignment
condition is false.

Fragment depth and stencil outputs are a special case due to how their
source swizzles are manipulated in translate_src when compiling to
TGSI.

Fixes dEQP-GLES2.functional.shaders.conditionals.if.*_vertex
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

(cherry picked from commit 8ea7d3a5c8)
2017-10-11 17:22:55 +01:00
Marek Olšák
f6d64c7dc1 mesa: fix texture updates for ATI_fragment_shader
Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 9d54025cd1)
2017-10-11 17:22:55 +01:00
Leo Liu
80db5b3420 st/va: use pipe transfer_map to map upload buffer
The function pipe_buffer_map() is only for linear pipe buffer,
with height as 0, and it's not for any 2D textures.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Thompson <sw@jkqxz.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 6ed61b8d3f)
2017-10-11 17:22:55 +01:00
Juan A. Suarez Romero
5a71ed6fa5 docs: add sha256 checksums for 17.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-10-02 18:10:02 +02:00
Juan A. Suarez Romero
bc12538a8e docs: add release notes for 17.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-10-02 17:26:10 +02:00
Juan A. Suarez Romero
98dce315c8 Update version to 17.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-10-02 17:15:13 +02:00
Bas Nieuwenhuizen
1535e8a5d4 radv: Check for GFX9 for 1D arrays in image_size intrinsic.
Only on GFX9 we implement them as 2D images.

This fixes:
dEQP-VK.image.image_size.1d_array.readonly_12x34
dEQP-VK.image.image_size.1d_array.readonly_1x1
dEQP-VK.image.image_size.1d_array.readonly_32x32
dEQP-VK.image.image_size.1d_array.readonly_7x1
dEQP-VK.image.image_size.1d_array.readonly_writeonly_12x34
dEQP-VK.image.image_size.1d_array.readonly_writeonly_1x1
dEQP-VK.image.image_size.1d_array.readonly_writeonly_32x32
dEQP-VK.image.image_size.1d_array.readonly_writeonly_7x1
dEQP-VK.image.image_size.1d_array.writeonly_12x34
dEQP-VK.image.image_size.1d_array.writeonly_1x1
dEQP-VK.image.image_size.1d_array.writeonly_32x32
dEQP-VK.image.image_size.1d_array.writeonly_7x1

Fixes: 1bcb953e16 "radv: handle GFX9 1D textures"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 979978ee06)
2017-10-02 17:12:17 +02:00
Nicolai Hähnle
a66a70480f radeonsi: fix a regression in integer cube map handling
A recent commit fixed the case of 8888 integer cube maps, which need the
workaround of replacing the data format with USCALED/SSCALED. However,
this broke the case of non-8888 integer cube maps; those still need the
fix of shifting the texture coordinates.

Fixes KHR-GL45.texture_gather.plain-gather-int-cube-array and similar.

Fixes: 6fb0c1013b ("radeonsi: workaround for gather4 on integer cube maps")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 6d23f7c65d)
2017-10-02 17:12:17 +02:00
Nicolai Hähnle
bd522741c4 amd/common: move ac_build_phi from radeonsi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 052b974fed)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/amd/common/ac_llvm_build.c
	src/amd/common/ac_llvm_build.h
2017-10-02 17:12:17 +02:00
Jason Ekstrand
b78c664115 vulkan/wsi/wayland: Return better error messages
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4fe3913b96)
2017-09-28 13:54:58 +00:00
Jason Ekstrand
2467b50e45 vulkan/wsi/wayland: Copy wl_proxy objects from oldSwapchain if available
This should save us some round trips while resizing.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 537b9bc3e4)
2017-09-28 13:54:58 +00:00
Jason Ekstrand
b5a70210af vulkan/wsi/wayland: Stop caching Wayland displays
We originally implemented caching to avoid unneeded round-trips to the
compositor when querying surface capabilities etc. to set up the
swapchain.  Unfortunately, this doesn't work if vkDestroyInstance is
called after the Wayland connection has been dropped.  In this case, we
end up trying to clean up already destroyed wl_proxy objects which leads
to crashes.  In particular most of dEQP-VK.wsi.wayland is crashing
thanks to this problem.

This commit gets rid of the cache and simply embeds the wsi_wl_display
struct in the swapchain.  While we're at it, we can get rid of the
wl_event_queue that we were storing in the swapchain because we can just
use the one in the embedded wsi_wl_display.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Bugzilla: https://bugs.freedesktop.org/102578
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4369102498)
2017-09-28 13:54:58 +00:00
Jason Ekstrand
5edc4dc080 vulkan/wsi/wayland: Refactor wsi_wl_display code
We convert it over to an inti/finish model and make create/destroy
wrappers for the former.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 77181d9580)
2017-09-28 13:54:57 +00:00
Ian Romanick
6587cbfca2 nv20: Fix GL_CLAMP
v2: Force T and R wrap modes to GL_CLAMP_TO_EDGE for 1D textures.
This fixes a regression in tex1d-2dborder.  The test uses a 1D texture
but it provides S and T texture coordinates.  Since the T wrap mode
would (correctly) be set to GL_CLAMP, the texture would gradually
blend (incorrectly) with the border color.

I also tried setting NV20_3D_TEX_FORMAT_DIMS_1D instead of
NV20_3D_TEX_FORMAT_DIMS_2D for 1D textures, but that did not help.

It is possible that the same problem exists for 2D textures with the
R-wrap mode, but I don't think there are any piglit tests for that.

No test changes on NV20 (10de:0201).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 953a3cf0fd)
2017-09-28 13:54:57 +00:00
Tomasz Figa
6b0ded06b1 egl/dri2: Implement swapInterval fallback in a conformant way
dri2_fallback_swap_interval() currently used to stub out swap interval
support in Android backend does nothing besides returning EGL_FALSE.
This causes at least one known application (Android Snapchat) to fail
due to an unexpected error and my loose interpretation of the EGL 1.5
specification justifies it. Relevant quote below:

    The function

        EGLBoolean eglSwapInterval(EGLDisplay dpy, EGLint interval);

    specifies the minimum number of video frame periods per buffer swap
    for the draw surface of the current context, for the current rendering
    API. [...]

    The parameter interval specifies the minimum number of video frames
    that are displayed before a buffer swap will occur. The interval
    specified by the function applies to the draw surface bound to the
    context that is current on the calling thread. [...] interval is
    silently clamped to minimum and maximum implementation dependent
    values before being stored; these values are defined by EGLConfig
    attributes EGL_MIN_SWAP_INTERVAL and EGL_MAX_SWAP_INTERVAL
    respectively.

    The default swap interval is 1.

Even though it does not specify the exact behavior if the platform does
not support changing the swap interval, the default assumed state is the
swap interval of 1, which I interpret as a value that eglSwapInterval()
should succeed if called with, even if there is no ability to change the
interval (but there is no change requested). Moreover, since the
behavior is defined to clamp the requested value to minimum and maximum
and at least the default value of 1 must be present in the range, the
implementation might be expected to have a valid range, which in case of
the feature being unsupported, would correspond to {1} and any request
might be expected to be clamped to this value.

This is further confirmed by the code in _eglSwapInterval() in
src/egl/main/eglsurface.c, which is the default fallback implementation
for EGL drivers not implementing its own. The problem with it is that
the DRI2 EGL driver provides its own implementation that calls into
platform backends, so we cannot just simply fall back to it.

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-09-28 13:54:57 +00:00
Boris Brezillon
d9aba007c0 broadcom/vc4: Fix infinite retry in vc4_bo_alloc()
cleared_and_retried is always reset to false when jumping to the retry
label, thus leading to an infinite retry loop.

Fix that by moving the cleared_and_retried variable definitions at the
beginning of the function.  While we're at it, move the create variable
with the other local variables and explicitly reset its content in the
retry path.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Fixes: 78087676c9 "vc4: Restructure the simulator mode."
(cherry picked from commit ef578906d8)
2017-09-28 13:54:57 +00:00
Eric Anholt
e22ab89f9f broadcom/vc4: Keep pipe_sampler_view->texture matching the original texture.
I was overwriting view->texture with the shadow resource when we need to
do shadow copies (retiling or baselevel rebase), but that tripped up some
critical new sanity checking in state_tracker (making sure that stObj->pt
hasn't changed from view->texture through TexImage-related paths).

To avoid that, move the shadow resource to the vc4_sampler_view struct.

Fixes: f0ecd36ef8 ("st/mesa: add an entirely separate codepath for setting up buffer views")
(cherry picked from commit 68c91a87d7)
2017-09-28 13:54:57 +00:00
Jason Ekstrand
1b100aae7b vulkan/wsi/wayland: Stop printing out the DRM device
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 016de7e155)
2017-09-28 13:54:57 +00:00
Kenneth Graunke
ec89ab30c9 i965/vec4: Fix swizzles on atomic sources.
Atomic operation sources are scalar values, but we were failing to
select the .x component of the second operand.  For example,

   atomicCounterCompSwapARB(counter, 5u, 10u)

would generate

   mov(8) vgrf4.x:D, 5D
   mov(8) vgrf5.x:D, 10D

   mov(8) vgrf9.x:UD, vgrf4.xyzw:D
   mov(8) vgrf9.y:UD, vgrf5.xyzw:D

which wrongly selects the .y component of vgrf5, so the actual 10u value
would get dead code eliminated.  The swizzle works for the other source,
but both of them ought to be .xxxx.

Fixes the compare and swap CTS tests in:
KHR-GL45.shader_atomic_counter_ops_tests.ShaderAtomicCounterOpsExchangeTestCase

Cc: "17.2 17.1 17.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 66342c997f)
2017-09-28 13:54:57 +00:00
Kenneth Graunke
8619a6b1cc i965/vec4: Actually handle atomic op intrinsics.
Embarassingly, someone enabled the ARB_shader_atomic_counter_ops
extension for Gen7+ but never added the intrinsics to the switch
statement in the vec4 backend, so they just hit an unreachable()
call and died.

Fixes: 40dd45d0c6 (i965: Enable ARB_shader_atomic_counter_ops)
Cc: "17.2 17.1 17.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit a62fe34098)
2017-09-28 13:54:57 +00:00
Samuel Pitoiset
47c8ffe719 radv: fix saved compute state when doing statistics/occlusion queries
We are pushing 16-bytes of constants, so we have to save/restore
the same amount of data to avoid data corruption.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4b407a62c7)
2017-09-28 13:54:57 +00:00
Grazvydas Ignotas
84f3374f1c configure: check if -latomic is needed for __atomic_*
On some platforms, gcc generates library calls when __atomic_* functions
are used, but does not link the required library (libatomic) automatically
(supposedly to allow the app to use some other atomics implementation?).

Detect this at configure time and add the library when needed. Tested
on armel (library was added) and on x86_64 (was not, as expected).

Some documentation on this is provided in GCC wiki:
https://gcc.gnu.org/wiki/Atomic/GCCMM

Fixes: 8915f0c0 "util: use GCC atomic intrinsics with explicit memory model"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102573
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 2ef7f23820)
2017-09-28 13:54:57 +00:00
Nicolai Hähnle
5e5882a7aa amd/addrlib: fix missing va_end() after va_copy()
There's no reason to use va_copy here.

CID: 1418113
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Fixes: e7fc664b91 ("winsys/amdgpu: add addrlib - texture
                              addressing and alignment calculator")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 34126ed248)
2017-09-28 13:54:57 +00:00
Juan A. Suarez Romero
89db1532fc cherry-ignore: add "radv: copy the number of viewports/scissors at pipeline bind time"
fixes: This commit addressed earlier commits dcf46e99 and 60878dd0 which
did not land in branch.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:57 +00:00
Nicolai Hähnle
5e8ddba33f radeonsi: set MIP_POINT_PRECLAMP to 0
This fixes a bug with nearest ("point") mip selection when the fractional
part of max_lod is in (0.5,1). In this case, the spec mandates that
we still select the mip level ceil(max_lod) in the clamping case. However,
MIP_POINT_PRECLAMP will clamp before the mip selection, which is wrong.

Supposedly this setting was originally copied from the closed Vulkan
driver, but as far as I can tell, closed Vulkan was actually changed back
recently :)

Fixes dEQP-GLES3.functional.texture.mipmap.2d.max_lod.{nearest,linear}_nearest

Fixes: f7420ef5b4 ("radeonsi: enable some sampler fields to match the closed driver")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 704ddbcdf6)
2017-09-28 13:54:57 +00:00
Eric Anholt
fc2b01adc9 broadcom/vc4: Fix use-after-free when deleting a program.
By leaving the compiled shader in the context's stage state, the next
compile of a new FS would look in the old compiled FS for figuring out
whether to set various dirty flags for the VS compile.  Clear out the
pointer when deleting the program, and make sure that we always mark the
state as dirty if the previous program had been lost.  Fixes valgrind
warnings on glsl-max-varyings.

Fixes: 2350569a78 ("vc4: Avoid VS shader recompiles by keeping a set of FS inputs seen so far.")
(cherry picked from commit 3752ad28f2)
2017-09-28 13:54:57 +00:00
Eric Anholt
fe53c8bc21 broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear.
The blitter will bind just the depth buffer, which flushes the current job
if we had both a color and depth/stencil.  If the clear was doing partial
depth/stencil (quad-based) and color (tile-based), we'd go on to try to
set up the rest of the tile clear in the now flushed job.

Instead, move the partial clear up before we start setting up the job for
the current FBO state, and re-fetch the job if we're continuing on to a
tile-based clear.  Fixes valgrind failures in fbo-depthtex.

Fixes: 9421a6065c ("vc4: Fix fallback to quad clears of depth in GLX.")
(cherry picked from commit 9940fb4205)
2017-09-28 13:54:57 +00:00
Eric Anholt
60efffcec0 broadcom/vc4: Fix use-after-free for flushing when writing to a texture.
I was trying to continue the hash table loop, not the inner loop.  This
tended to work out, because we would have *just* freed the job struct.
Fixes some valgrind failures in fbo-depthtex.

Fixes: f597ac3966 ("vc4: Implement job shuffling")
(cherry picked from commit d88a75182d)
2017-09-28 13:54:56 +00:00
Dave Airlie
5d1deeeab3 st/glsl->tgsi: fix u64 to bool comparisons.
Otherwise we end up using a 32-bit comparison which didn't end well.

Timothy caught this while playing around with some opt passes.

Fixes: 278580729a (st/glsl_to_tgsi: add support for 64-bit integers)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit a7a7bf21bd)
2017-09-28 13:54:56 +00:00
Juan A. Suarez Romero
dbccd8465d cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size intrinsic."
fixes: This commit addressed earlier commits 61ad2f13 and 6dcc54b4 which
did not land in branch

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:56 +00:00
Juan A. Suarez Romero
de44476572 cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug"
fixes: This commit addressed an earlier commit c7e9ebb3ab which did not
land in branch

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:56 +00:00
Leo Liu
2712e59538 st/va/postproc: use video original size for postprocessing
Otherwise the aligned size will make video scaled

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit eb51838771)
2017-09-28 13:54:56 +00:00
Samuel Iglesias Gonsálvez
e16c31f3fe anv: fix viewport transformation for z component
In Vulkan, for 'z' (depth) component, the scale and translate values
for the viewport transformation are:

pz = maxDepth - minDepth
oz = minDepth

zf = pz × zd + oz

Being zd, the third component in vertex's normalized device coordinates.

Fixes: dEQP-VK.draw.inverted_depth_ranges.*

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d2cd9deeb8)
2017-09-28 13:54:56 +00:00
David Airlie
dbf33a12e1 radv: add gfx9 scissor workaround
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3e54493265)
2017-09-28 13:54:56 +00:00
Lucas Stach
cd9d26c3ef etnaviv: fix 16bpp clears
util_pack_color may leave undefined values in the upper half of the packed
integer. As our hardware needs the upper 16 bits to mirror the lower 16bits,
this breaks clears of those formats if the undefined values aren't masked off.

I've only observed the issue with R5G6B5_UNORM surfaces, other 16bpp
formats seem to work fine.

Fixes: d6aa2ba2b2 (etnaviv: replace translate_clear_color with util_pack_color)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit e9d37d68cf)
2017-09-28 13:54:56 +00:00
Tim Rowley
b378fd5cf3 swr/rast: remove llvm fence/atomics from generated files
We currently don't use these instructions, and since their API
changed in llvm-5.0 having them in the autogen files broke the mesa
release tarballs which ship with generated autogen files.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102847
CC: mesa-stable@lists.freedesktop.org
Tested-by: Laurent Carlier <lordheavym@gmail.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit 066d1dc951)
2017-09-28 13:54:56 +00:00
Tapani Pälli
caff607bcb mesa: free current ComputeProgram state in _mesa_free_context_data
This is already done for other programs stages, fixes a leak when using
compute programs.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102844
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 589457d97f)
2017-09-28 13:54:56 +00:00
Nicolai Hähnle
737e2245ce radeonsi: fix array textures layer coordinate
Like for cube map (array) gather, we need to round to nearest on <= VI.

Fixes tests in dEQP-GLES3.functional.shaders.texture_functions.texture.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 87f7c7bd65)
2017-09-28 13:54:56 +00:00
Nicolai Hähnle
46cfefc5be glsl/linker: fix output variable overlap check
Prevent an overflow caused by too many output variables. To limit the
scope of the issue, write to the assigned array only for the non-ES
fragment shader path, which is the only place where it's needed.

Since the function will bail with an error when output variables with
overlapping components are found, (max # of FS outputs) * 4 is an upper
limit to the space we need.

Found by address sanitizer.

Fixes dEQP-GLES3.functional.attribute_location.bind_aliasing.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 15cae12804)

Squashed with commit:

glsl/linker: properly fix output variable overlap check

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102904
Fixes: 15cae12804 ("glsl/linker: fix output variable overlap check")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit df8767a14e)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:56 +00:00
Józef Kucia
6121bc3150 anv: Fix descriptors copying
Trivial.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 65a09f98ad)
2017-09-28 13:54:56 +00:00
Dave Airlie
488460b1ef ac/surface: handle S8 on gfx9
If we don't have a depth piece, we don't get a correct
swizzle mode and we hit an assert in addrlib.

In case of no depth get the preferrred swizzle mode for
stencil alone.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit c4ac522511)

Squashed with commit:

ac/surface: handle error when choosing preferred swizzle mode

CID: 1418140
Fixes: c4ac522511 ("ac/surface: handle S8 on gfx9")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit eb71394ff3)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:56 +00:00
Alexandru-Liviu Prodea
3c54a77d08 Scons: Add LLVM 5.0 support
1 new required library - LLVMBinaryFormat

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org=/show_bug.cgi?id=3D102318
Signed-off-by: Alexandru-Liviu Prodea <liviuprodea@yahoo.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c1b0137048)
2017-09-28 13:54:56 +00:00
Nicolai Hähnle
891627ec0f amd/common: add workaround for cube map array layer clamping
Fixes dEQP-GLES31.functional.texture.filtering.cube_array.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 94736d31c3)

Squashed with commit:

amd/common: add chip_class to ac_llvm_context

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 3db86d86ed)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-28 13:54:56 +00:00
Nicolai Hähnle
688f8415f7 amd/common: round cube array slice in ac_prepare_cube_coords
The NIR-to-LLVM pass already does this; now the same fix covers
radeonsi as well.

Fixes various tests of
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e0af3bed2c)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-09-28 13:54:55 +00:00
Nicolai Hähnle
54915ee52f radeonsi: workaround for gather4 on integer cube maps
This is the same workaround that radv already applied in commit
3ece76f03d ("radv/ac: gather4 cube workaround integer").

Fixes dEQP-GLES31.functional.texture.gather.basic.cube.rgba8i/ui.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 6fb0c1013b)
2017-09-28 13:54:55 +00:00
Jason Ekstrand
da517431f6 i965/blorp: Set r8stencil_needs_update when writing stencil
This fixes a crash on Haswell when we try to upload a stencil texture
with blorp.  It would also be a problem if someone tried to texture from
stencil after glBlitFramebuffers.

Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit a43d379000)
2017-09-28 13:54:55 +00:00
Matt Turner
3b4a6dbe93 util/u_atomic: Add implementation of __sync_val_compare_and_swap_8
Needed for 32-bit PowerPC.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Fixes: a6a38a038b ("util/u_atomic: provide 64bit atomics where
they're missing")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

(cherry picked from commit 1bbe180873)
2017-09-28 13:54:55 +00:00
Matt Turner
d2dca92a6c util: Link libmesautil into u_atomic_test
Platforms without particular atomic operations require the
implementations in u_atomic.c

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Fixes: a6a38a038b ("util/u_atomic: provide 64bit atomics where
they're missing")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit d075a4089e)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/util/Makefile.am
2017-09-28 13:54:55 +00:00
Emil Velikov
d41d54b061 automake: enable libunwind in `make distcheck'
Enable the toggle to catch when the library is missing from the link
path. Better to test, fail and address before releasing Mesa ;-)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 9aba643e3c)
2017-09-28 13:54:55 +00:00
Gert Wollny
5d16640ea1 travis: Add libunwind-dev to gallium/make builds
libunwind is a optional dependency used by the gallium aux module
(libgallium) and consequently the final binaries must be linked against
it. To test whether the library is properly specified in the link pass
add it to the travis-ci build environment and force its use.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 39fe51c1e3)
2017-09-26 12:17:33 +02:00
Gert Wollny
6024a95198 travis: force llvm-3.3 for "make Gallium ST Other"
In Ubuntu Trusty the default version of llvm is 3.4 and the build was
actually randomly picking 3.5 or 3.9. Adding libunwind would then result
is build success or failure depending of what version was picked.

Install the llvm-3.3-dev package and force its use: On one hand it is
the minimum required version we want to the build test against, and on
the other hand forcing the version stabilizes the build.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit d3675812b5)
2017-09-26 12:17:33 +02:00
Dave Airlie
996bf9c1cd radv/nir: call opt_remove_phis after trivial continues.
With the shaders in the ssao demo, the nir_opt_if wasn't
working properly without this, after this the if gets optimised
so that loop unrolling gets called.

(loop unrolling fails due to instruction count, but at least
it gets to do that.)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 64d9bd149a)
[Juan A. Suarez: apply patch over src/amd/vulkan/radv_pipeline.c]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/amd/vulkan/radv_shader.c
2017-09-26 12:17:33 +02:00
Emil Velikov
bd903d4ee1 docs: add sha256 checksums for 17.2.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-18 00:12:36 +01:00
Emil Velikov
d6d2b6b5ec docs: add release notes for 17.2.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-17 23:57:32 +01:00
Emil Velikov
cb778d563f Update version to 17.2.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-17 23:53:08 +01:00
Bas Nieuwenhuizen
7c3bd519e7 radv: Don't allocate CMASK for linear images.
We can't use it anyway in fast clears, and on GFX9 it seems to
actually hange the card if we specify it.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
(cherry picked from commit 1a172fb113)
2017-09-13 21:52:42 +01:00
Bas Nieuwenhuizen
c6b3732967 radv: Disable multilayer & multilevel DCC.
The current DCC init routine doesn't account for initializing a
single layer or level. Multilayer seems hard for small textures on
pre-GFX9 as tre metadata for the layers can be interleaved. For
GFX9 multilevel textures are a problem for similar reasons.

So just disable this for now, until we handle the texture modes
correctly.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
(cherry picked from commit bee83b2661)
2017-09-13 21:52:42 +01:00
Eric Engestrom
e012ade1cf docs/egl: remove reference to EGL_DRIVERS_PATH
Support for external egl drivers was dropped a few years ago.

Fixes: 209360bbb9 "egl/main: drop support for external egl drivers"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 85b66d2096)
2017-09-13 21:52:42 +01:00
Dave Airlie
41e691d605 radv/winsys: fix flags vs va_flags thinko.
Fixes: e8d57802f (radv/gfx9: allocate events from uncached VA space)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a5add6fb30)
2017-09-13 21:52:42 +01:00
Emil Velikov
b6ae4400fc egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension
Fixes: 3b7b6adf3a ("egl: Implement __DRI_BACKGROUND_CALLABLE")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f24bc18162)
2017-09-13 21:52:42 +01:00
Bas Nieuwenhuizen
c47914276e radv: Fix vkCopyImage with both depth and stencil aspects.
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ff23e03d60)
2017-09-13 21:52:42 +01:00
Bas Nieuwenhuizen
536f852d42 radv: Actually set the cmd_buffer usage_flags.
Otherwise, the simultaneous uage bit doesn't get set from the begin
info, which we need for batchchaining.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit dec7b38fe6)
2017-09-13 21:52:42 +01:00
Grazvydas Ignotas
fdc4f6e684 radv: don't assert on empty hash table
Currently if table_size is 0, it's falling through to:

unreachable("hash table should never be full");

But table_size can be 0 when RADV_DEBUG=nocache is set, or when the
table allocation fails (which is not considered an error).

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit b8dd69e1b4)
2017-09-13 21:52:42 +01:00
Eric Engestrom
8cf9e5ab56 mesa/st: remove unwanted backup file
Fixes: 0ac78dc925 "util: move string_to_uint_map to glsl"
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit ac0d8dc3fa)
2017-09-13 21:52:42 +01:00
Samuel Pitoiset
d5c71e44c4 radeonsi: update dirty_level_mask before dispatching
This fixes a rendering issue with Hitman when bindless textures
are enabled.

Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning from DB to texturing")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 59101e771d)
2017-09-13 21:52:42 +01:00
Nicolai Hähnle
53190187cc glsl: fix glsl_struct_field size calculations for shader cache
Found by address sanitizer:

==22621==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61400000cbd8 at pc 0x7f561610a4ff bp 0x7ffca85f9d50 sp 0x7ffca85f94f8
READ of size 344 at 0x61400000cbd8 thread T0
    #0 0x7f561610a4fe  (/usr/lib/x86_64-linux-gnu/libasan.so.3+0x5f4fe)
    #1 0x7f560bb305a5 in memcpy /usr/include/x86_64-linux-gnu/bits/string3.h:53
    #2 0x7f560bb305a5 in blob_write_bytes ../../../mesa-src/src/compiler/glsl/blob.c:136
    #3 0x7f560be7d7ff in encode_type_to_blob ../../../mesa-src/src/compiler/glsl/shader_cache.cpp:153
    #4 0x7f560be81222 in write_program_resource_data ../../../mesa-src/src/compiler/glsl/shader_cache.cpp:950
    #5 0x7f560be81222 in write_program_resource_list ../../../mesa-src/src/compiler/glsl/shader_cache.cpp:1118
    #6 0x7f560be81222 in shader_cache_write_program_metadata(gl_context*, gl_shader_program*) ../../../mesa-src/src/compiler/glsl/shader_cache.cpp:1407
    #7 0x7f560b825fdb in link_program ../../../mesa-src/src/mesa/main/shaderapi.c:1163

Fixes: 073a84ff60 ("glsl: stop adding pointers from glsl_struct_field to the cache")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 4da6cf6c98)
2017-09-13 21:52:42 +01:00
Emil Velikov
366e02f992 cherry-ignore: add EGL+gbm swast patches
They depend on an earlier commit which did not land in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-13 21:52:41 +01:00
Nicolai Hähnle
5cec093773 ac/surface: match Z and stencil tile config
Fixes various piglit tests on Stoney, see the comment.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit cffc0ae0d9)
[Emil Velikov: attribute for the different gfx6_surface_settings()]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/common/ac_surface.c
2017-09-13 21:52:02 +01:00
Nicolai Hähnle
69394e3517 radeonsi: apply a mask to gl_SampleMaskIn in the PS prolog
gl_SampleMaskIn is supposed to contain set bits only for the samples that
are covered by the current fragment shader invocation, but the VGPR
initialization hardware loads the set of all bits that are covered at the
current pixel.

Fixes various tests in
dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 92c4277990)
[Emil Velikov: attribute for the lack of add_arg*checked() API]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeonsi/si_shader.c
2017-09-13 21:52:02 +01:00
Timothy Arceri
c0c1e05fb6 glsl: stop adding pointers from bindless structs to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 4009370232)
2017-09-13 21:52:02 +01:00
Timothy Arceri
94b656cb5e glsl: stop adding pointers from shader_info to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit a6618afd27)
2017-09-13 21:52:02 +01:00
Timothy Arceri
5e0b556abc compiler: move pointers to the start of shader_info
This will allow us to easily skip them when writting the struct
to disk cache.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 3ea3f75723)
2017-09-13 21:52:02 +01:00
Timothy Arceri
f087dad40d glsl: always write a name/label string to the cache
In the following patch we will stop writing the pointer to cache.

Unfortunately adding empty strings to that cache seems to be the
only thing we can do here once we no longer have the pointers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 44918a1979)
2017-09-13 21:52:02 +01:00
Timothy Arceri
83bbfaddf1 glsl: don't write uniform storage offset if there isn't one
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 22154823d2)
2017-09-13 21:52:02 +01:00
Timothy Arceri
a8eea040cd glsl: add has_uniform_storage() helper to shader cache
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 2662269ad7)
2017-09-13 21:52:02 +01:00
Timothy Arceri
15ecbb2c07 glsl: stop adding pointers from glsl_struct_field to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 073a84ff60)
2017-09-13 21:52:02 +01:00
Timothy Arceri
7fef8d436a glsl: stop adding pointers from gl_shader_variable to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 37d453b55a)
2017-09-13 21:52:02 +01:00
Timothy Arceri
ea1bcfc063 glsl: allow NULL to be passed to encode_type_to_blob()
This will be used by the following commit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 37eb67714e)
2017-09-13 21:52:01 +01:00
Eric Engestrom
6e2b9fba21 util: improve compiler guard
Glibc 2.26 has dropped xlocale.h, but the functions needed (strtod_l()
and strdof_l()) can be found in stdlib.h.
Improve the detection method to allow newer builds to still make use of
the locale-setting.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102454
Cc: Laurent Carlier <lordheavym@gmail.com>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Laurent Carlier <lordheavym@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 49b428470e)
2017-09-13 21:52:01 +01:00
Kenneth Graunke
dcb634df92 i965: Set "Subslice Hashing Mode" to 16x16 on Apollolake.
As of 4.11, the kernel isn't bothering to set the subslice hashing mode
on Apollolake, leaving it at the default of 8x8.  (It initializes it to
16x4 on most platforms.)

Performance data for GPUTest Triangle on Apollolake at 1024x640:

   X-tiled RT:
   -----------
   8x8 -> 16x4:   2.4325%  +/- 0.383683% (n=107)
   8x8 -> 8x4:   -3.75105% +/- 0.592491% (n=40)
   8x8 -> 16x16:  6.17238% +/- 0.67157%  (n=30)

   Y-tiled RT:
   -----------
   8x8 -> 16x4:   1.30307%  +/- 0.297292% (n=205)
   8x8 -> 8x4:   -0.769282% +/- 0.729557% (n=35)
   8x8 -> 16x16:  3.00254%  +/- 0.715503% (n=40)

   8x MSAA RT (INTEL_FORCE_MSAA=8):
   --------------------------------
   8x8 -> 16x4:   1.38889% +/- 0.93729%  (n=7)
   8x8 -> 8x4:   -2.10643% +/- 1.15153%  (n=3)
   8x8 -> 16x16:  3.87183% +/- 1.08851%  (n=5)

Based on this, we choose 16x16 for Apollolake.

Skylake GT2 with X-tiled buffers appears to be a toss-up between 16x4
and 16x16, and with Y-tiled buffers it doesn't seem to really matter.
So we'll leave Skylake alone for now.

The hashing mode doesn't seem to make a measurable impact on more
complex benchmarks.

Acked-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit ebd2fd6ef3)
2017-09-13 21:52:01 +01:00
Dave Airlie
20be71ba7c radv/gfx9: fix image resource handling.
GFX9 changes how images are layed out, so this needs updating.

Fixes: dEQP-VK.query_pool.statistics_query.*

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3633bae36b)
2017-09-13 21:52:01 +01:00
Dave Airlie
a3d1ea347a radv/ac: bump params array for image atomic comp swap
For the comp_swap case this was overflowing and crashing
sometimes.

Fixes:
dEQP-VK.image.atomic_operations.compare_exchange.*

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit aba441be44)
2017-09-13 21:52:01 +01:00
Dave Airlie
dc640aab63 radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
This field covers the whole resource.

Fixes:
dEQP-VK.pipeline.image.suballocation.sampling_type.combined.view_type.3d.format.*
dEQP-VK.texture.filtering.3d.combinations.*

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ebd2a5354d)
2017-09-13 21:52:01 +01:00
Dave Airlie
c8076c8ea1 radv: handle GFX9 1D textures
As GFX9 can't handle 1D depth textures, radeonsi and
apparantly pro just update all 1D textures to 2D,
and work around it.

This ports the workarounds from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 1bcb953e16)

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-09-13 21:52:01 +01:00
Dave Airlie
62f0bb2a87 radv: don't use iview for meta image width/height.
Work out the width/height from the level manually, as on GFX9
we won't minify the iview width/height.

This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image* on gfx9

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 2f5b4490b5)
2017-09-13 21:52:01 +01:00
Emil Velikov
40f06286f9 cherry-ignore: add execution_type() fix to the list
As mentioned by Matt:
 "Without commit 4fab67a441, this patch isn't  needed at all."

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-13 21:50:49 +01:00
Nicolai Hähnle
0f79eb7abe st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index
Don't get distracted by record dereferences between array references.

Fixes dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 03203b7448)
2017-09-13 21:34:03 +01:00
Dave Airlie
54c5568fa9 radv: use simpler indirect packet 3 if possible.
This fixes some observed hangs on CIK GPUs.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 219d29e4d8)
[Emil Velikov: add the hunk in radv_emit_indirect_draw]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_cmd_buffer.c
2017-09-13 21:34:03 +01:00
Dave Airlie
c2f314d721 radv/gfx9: allocate events from uncached VA space
This copies what amdgpu-pro does, and allocates the memory
for an event with an uncached mtype.

This fixes hangs with:
dEQP-VK.api.command_buffers.record_simul_use_primary

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e8d57802fe)
2017-09-13 21:34:02 +01:00
Dave Airlie
fe04abc6e9 radv/winsys: use amdgpu_bo_va_op_raw.
This is a precursor to the gfx9 fix to use uncached for the event
memory. Move to the interface which allows setting the flags,
but wrap it to avoid having to copy it around the place.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 76ac8fafad)
2017-09-13 21:34:02 +01:00
Marek Olšák
0e305f0518 st/mesa: skip draw calls with pipe_draw_info::count == 0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit e4018fdd85)
2017-09-13 21:34:02 +01:00
Nicolai Hähnle
cb9dae484a radeonsi/gfx9: always flush DB metadata on framebuffer changes
This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 34124e412f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeonsi/si_pipe.h
	src/gallium/drivers/radeonsi/si_state.c
2017-09-13 21:34:02 +01:00
Dave Airlie
57ecf28668 Revert "radv: disable support for VEGA for now."
This reverts commit 611076a41a.

With the two previous commits, vega shouldn't be unstable,
doesn't pass CTS, but can do a complete run, and games shouldn't
hang anymore, so bring it back online.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e38685cc62)
2017-09-13 21:34:02 +01:00
Dave Airlie
78e2b539a4 radv/gfx9: set descriptor up for base_mip to level range.
This is required on GFX9, fixes a bug in Talos where all the
mipmaps overlay each other.

Just pushing this as well as it fixes Talos.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6d929d3f85)
2017-09-13 21:34:02 +01:00
Dave Airlie
86d4c203bd radv: disable 1d/2d linear optimisation on gfx9.
This causes hangs in some of the CTS tests with a 2d
1536x2 texture.

This fixes hangs with:
dEQP-VK.pipeline.image.suballocation.sampling_type.combined.iew_type.1d_aray.format.r4g4b4a4_unorm_pack16.count_1.size.512x1_array_of_3
if we reenable it, make sure these don't regress.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d118ff8765)
2017-09-13 21:34:02 +01:00
Jason Ekstrand
bda2975eef spirv: Add support for the HelperInvocation builtin
I have no idea how this got missed but it's been missing since forever.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit e439908af9)
2017-09-13 21:34:02 +01:00
Roland Scheidegger
a4dc18efca st/mesa: fix view template initialization in try_pbo_readpixels
I think this is what the code was meant to do, albeit as far as I can tell
the redundant initialization some analyzers complain about should work as
well just fine (only the first layer will be used, if the view contains one
or more layers doesn't really matter).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102467
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 2b2c61f0df)
2017-09-13 21:34:02 +01:00
Kenneth Graunke
8f77409e2b i965: Fix crash in fallback GTT mapping.
We can't perf_debug without a context.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
(cherry picked from commit 52b65dfda8)
2017-09-13 21:34:02 +01:00
Rob Clark
458f52618a freedreno: skip batch-cache for compute shaders
It is kind of pointless for compute, and avoids issues with apps kicking
off more than 32 compute shaders at once.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit dc9e08b0c3)
2017-09-13 21:34:02 +01:00
Karol Herbst
402b8073ad nvc0: write 0 to pipeline_statistics.cs_invocations
cs_invocations are currently unsupported, but leaving the field uninitialized
is even worse.

fixes on nvc0:
 * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values
 * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit b672c3833b)
2017-09-13 21:34:02 +01:00
Ben Crocker
6fe4852f59 llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load
Fix loading of a 3x16 vector as a single 48-bit load
on big-endian systems (PPC64, S390).

Roland Scheidegger's commit e827d91756
plus Ray Strode's patch reduce pre-Roland Piglit failures from ~4000 to ~2000.  This patch fixes
three of the four regressions observed by Ray:

- draw-vertices
- draw-vertices-half-float
- draw-vertices-half-float_gles2

One regression remains:
- draw-vertices-2101010

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 57c8ead0cd)
2017-09-13 21:34:02 +01:00
Ray Strode
d080f10fdf gallivm: correct channel shift logic on big endian
lp_build_fetch_rgba_soa fetches a texel from a texture.
Part of that process involves first gathering the element
together from memory into a packed format, and then breaking
out the individual color channels into separate, parallel
arrays.

The code fails to account for endianess when reading the packed
values.

This commit attempts to correct the problem by reversing the order
the packed values are read on big endian systems.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ray Strode <rstrode@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 75cb6e3617)
2017-09-13 21:34:02 +01:00
Jason Ekstrand
93b794f094 anv/formats: Nicely handle unknown VkFormat enums
This fixes some crashes in the dEQP-VK.memory.requirements.core.* tests.
I'm not sure whether or not passing out-of-bound formats into the query
is supposed to be allowed but there's no harm in protecting ourselves
from it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/101956
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 242211933a)

Squashed with:

anv: fix off by one in array check

`anv_formats[ARRAY_SIZE(anv_formats)]` is already one too far.
Spotted by Coverity.

CovID: 1417259
Fixes: 242211933a "anv/formats: Nicely handle unknown VkFormat enums"
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 0c7272a66c)
2017-09-13 21:33:55 +01:00
Charmaine Lee
520786586d vbo: fix offset in minmax cache key
Instead of saving primitive offset in the minmax cache key,
save the actual buffer offset which is used in the cache lookup.

Fixes rendering artifact seen with GoogleEarth when run with
VMware driver.

v2: Per Brian's comment, initialize offset to avoid compiler warning.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 2d93b462b4)

Squashed with:

vbo: fix build errors on android

incompatible pointer to integer conversion assigning to 'GLintptr' (aka 'int')
from 'const char *' [-Werror,-Wint-conversion]

      offset = indices;
             ^ ~~~~~~~

Fixes: 2d93b462b4 ("vbo: fix offset in minmax cache key")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 0986f68632)
2017-09-13 21:32:19 +01:00
Michael Olbrich
9ffe4cc6c0 egl/dri2: only destroy created objects
dri2_display_destroy may be called by dri2_initialize_wayland_drm() if
initialization fails. In this case, these objects may not be initialized.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 81d5c31631)
2017-09-13 21:05:57 +01:00
Brian Paul
2b0e70e2ae llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSOR
If llvmpipe_set_scissor_states() is never called, we still need to be sure
that derived scissor/clip state is updated.  As of commit 743ad599a9
that function might not be called.

Fixes regressed Piglit gl-1.0-scissor-offscreen -fbo -auto test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101709
Fixes: 743ad599a9 ("st/mesa: don't set 16 scissors and 16 viewports
if they're unused")
Cc: "17.2" <mesa-stable@lists.freedesktop.org>

(cherry picked from commit 88cdf16871)
2017-09-13 21:05:57 +01:00
Emil Velikov
3a9b2e0e7d cherry-ignore: ignore gfx9 tile swizzle fix
As mentioned by Dave and Bas, the patch is not applicable for 17.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-13 21:05:56 +01:00
Emil Velikov
188010c68d cherry-ignore: add getCapability patches
Adding extra infra is not acceptable for stable. Offending code has been
wrapped in a Android compile guard with an earlier commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-13 21:05:33 +01:00
Emil Velikov
b4473dd519 docs: add sha256 checksums for 17.2.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-04 18:24:29 +01:00
Emil Velikov
f5925b2897 docs: Update 17.2.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-04 18:16:16 +01:00
Emil Velikov
702950d1ad Update version to 17.2.0(final)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-04 15:16:21 +01:00
Emil Velikov
909f2b6aa2 Update version to 17.2.0-rc6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-31 10:06:29 +01:00
Emil Velikov
3666d9ab99 egl/wayland: make sure HAS_$FORMAT is set for wl_dmabuf
Otherwise eglCreateWaylandBufferFromImageWL will fail, since we
have no "supported" format.

Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 9e07005e87)
2017-08-29 19:14:14 +01:00
Emil Velikov
5303f0c246 egl/wayland: set correct format with wl_dmabuf as wl_drm is missing
For most/all cases today, we have wl_drm available alongside wl_dmabuf.
Yet in the long run, we want to make sure the latter can operate without
any traces of the former.

Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit da100fe697)
2017-08-29 19:14:13 +01:00
Emil Velikov
8d51747dc0 egl/wayland: polish object teardown in dri2_wl_destroy_surface
The wl_drm wrapper is created before the wl display/surface ones.
Thus make sure we destroy it after them. In reality it should not make
any difference either way.

Fixes: 03dd9a88b0 ("egl/wayland: Use per-surface event queues")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 1a8015e753)
2017-08-29 19:14:13 +01:00
Emil Velikov
3b41bef9a4 egl/wayland: plug leaks in dri2_wl_create_window_surface() error path
We forgot to teardown the wl display/surface wrappers.

Fixes: 03dd9a88b0 ("egl/wayland: Use per-surface event queues")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 83442112d7)
2017-08-29 19:14:13 +01:00
Grazvydas Ignotas
e040bdbc8a radv: clear dynamic_shader_stages on create
Valgrind reports it's being used uninitialized.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 7780374833)
2017-08-29 19:14:13 +01:00
Dave Airlie
e4c4b0dbcb radv/wsi: Compute correct row_pitch for GFX9.
(commit split out by Bas Nieuwenhuizen)

Fixes: 65477bae9c "radv: enable GFX9 on radv"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 9573bd70e1)
2017-08-29 19:14:13 +01:00
Emil Velikov
ca9817a6e8 egl: don't NULL deref the .get_capabilities function pointer
One could easily introduce version 3 of the DRI2fenceExtension,
extending the struct, while not implementing the above function.

Thus we'll end up with NULL pointer, and dereferencing it won't fare
too well.

Fixes: 0201f01dc4 ("egl: add EGL_ANDROID_native_fence_sync")
Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit f0d053cb6d)
2017-08-29 19:14:13 +01:00
Bas Nieuwenhuizen
df8e65feb7 radv: Fix sparse BO mapping merging.
If we merge a mapping with the mapping before it, we also need
to not only change the offset, but also the bo offset.

Fixes: 715df30a4e "radv/amdgpu: Add winsys implementation of virtual buffers."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 9b7e663da1)
2017-08-29 19:14:13 +01:00
Bas Nieuwenhuizen
ec94b874c4 radv: Fix off by one in MAX_VBS assert.
e.g. 0 + 32 <= 32 should be valid.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit fba0e07869)
2017-08-29 19:14:13 +01:00
Bas Nieuwenhuizen
17e5b0f1db radv: Don't set a new subpass on compute resolve.
We don't use the render path so totally unneeded.

Fixes: 19be95f71e "radv: add subpass resolve compute path"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit bd81cb3206)
2017-08-29 19:14:13 +01:00
Bas Nieuwenhuizen
69c793c0ce radv: Remove some intel comments from the resolve code.
These are clearly not applicable to radv.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit e5c4e10769)
2017-08-29 19:14:13 +01:00
Dave Airlie
b29987ace4 radv: don't crash if we have no framebuffer
Recording secondaries with no framebuffer attachment may
make this happen, though this might not be the complete solution.

(esp if someone does meta stuff in there, would we have to
save things, not sure).

Fixes: f4e499ec79 ("radv: add initial non-conformant radv vulkan driver")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4a091b0788)
2017-08-29 19:14:13 +01:00
Dave Airlie
22c1e2e966 radv: fix predication on gfx9
When I added gfx9 I did it wrong, this fixes it.

Fixes: 5247b311e9 "radv/gfx9: fix set predication packet."
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 12fd0f8dc1)
2017-08-29 19:14:13 +01:00
Timothy Arceri
f01cd4feeb mesa: fix ES only draw if we have vertex positions
This code was separated from the validation code so it could
use used with KHR_no_error paths. The return values were inverted
to reflect the name of the helper, but here the condtion was
mistakenly inverted rather than the return value.

Fixes: 4df2931a87 (mesa/vbo: move some Draw checks out of validation)

Reported-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit a4635c84dc)
2017-08-29 19:14:13 +01:00
Daniel Stone
c77ae9744e egl: Add dma_buf_import_modifiers for glvnd
Make sure we advertise the new entrypoints to libglvnd's EGL dispatch.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reported-by: Emmanuel Gil Peyrot <emmanuel.peyrot@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101982
Fixes: 4c412293d0 ("egl: advertise EGL_EXT_image_dma_buf_import_modifiers")
(cherry picked from commit 85ef0215dd)
2017-08-29 19:14:13 +01:00
Daniel Stone
5fdf832235 egl: Update headers from Khronos
Taken from egl-registry 7d68647c4dab.

Signed-off-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 2eee03b7a1)
2017-08-29 19:14:13 +01:00
Emil Velikov
46573f1028 util: move string_to_uint_map to glsl
The functionality is used by glsl and mesa. With the latter already
depending on the former.

With this in place the src/util/ static library libmesautil.la no longer
has a C++ dependency. Thus objects which use it (like libEGL) don't need
the C++ link.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101851
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Tested-by: James Harvey <lothmordor@gmail.com>
(cherry picked from commit 0ac78dc925)
2017-08-29 19:14:13 +01:00
Jason Ekstrand
1dfbfad0b9 nir: Fix system_value_from_intrinsic for subgroups
A couple of the cases were backwards

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 63e79a8a77)
2017-08-29 19:14:13 +01:00
Ilia Mirkin
289b2a8788 st/mesa: fix handling of vertex array double inputs
The is_double_vertex_input needs to be set for arrays of doubles as
well.

Fixes KHR-GL45.enhanced_layouts.varying_array_locations

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ae53bff8b1)
2017-08-29 19:14:13 +01:00
Ilia Mirkin
1960d8f0dd glsl: fix counting of vertex shader output slots used by explicit vars
The argument to count_attribute_slots should only be set to true for
vertex inputs, not for all vertex shader varyings.

Fixes KHR-GL45.enhanced_layouts.varying_locations

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit eefeff09a7)
2017-08-29 19:14:13 +01:00
Christian Gmeiner
2c964f68a8 etnaviv: use correct param for etna_compatible_rs_format(..)
Found by code inspection.

Fixes: c9e8b49b88 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 67fc3e37a7)
2017-08-29 19:14:13 +01:00
Kai Chen
5d5a13e375 egl/wayland: Use roundtrips when awaiting buffer release
In get_back_bo, we use wl_display_dispatch_queue() to block and wait for
a buffer release event. However, not all Wayland compositors flush the
client socket on posting a buffer-release event, so by only blocking
client-side, we may block indefinitely, or at least need to wait for an
input event / frame completion to arrive for the compositor to flush.

We now use dispatch_queue as a first pass, but if our entire buffer pool
is exhausted, use a roundtrip (an immediately-triggered wl_callback) to
ensure that the compositor flushes out our release event immediately.

[daniels: Modified comment and commit message.]

Signed-off-by: Kai Chen <kai.chen@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 151188d1e3)
2017-08-29 19:14:13 +01:00
Dave Airlie
9d6d567046 radv/gfx9: gfx9 has buffer sizing rules like pre-VI.
This fixes:
dEQP-VK.robustness.buffer_access.* on GFX9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 19f6906c1e)
2017-08-29 19:14:13 +01:00
Bas Nieuwenhuizen
6f0d910617 ac/nir: Cast sources of integer ops to int.
The int32->float semantic conversion got dropped in a testcase,
because the src was already float. On closer inspection I decided
to add a few more casts for integer op operands to be safe too.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 43595db302)
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-08-29 19:14:13 +01:00
Ilia Mirkin
a0b3095bb6 nv50/ir: properly set sType for TXF ops to U32
All of the coordinates and LOD args are integers for TXF. This mostly
doesn't matter, except for converting into a levelZero=true operation by
removing an explicit zero LOD. For the comparison against zero to work
properly, the sType of the instruction has to be set correctly.

Fixes: KHR-GL45.robust_buffer_access_behavior.texel_fetch
Reported-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 96be442b77)
2017-08-29 19:14:13 +01:00
Dave Airlie
c25e896810 radv/gfx9: don't expose linear depth on vega.
This just zeros out the linear flags for gfx9 + depth formats.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8985ad494b)
2017-08-29 19:14:13 +01:00
Dave Airlie
9172c7744a radv: don't degrade tiling mode for small compressed or depth texture.
This is what radeonsi does, so we should do the same, also vega
doesn't support linear depth textures anyways.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5d26e0baf2)
2017-08-29 19:14:12 +01:00
Dave Airlie
adce678550 radv/gfx9: only minify image view width/height/depth before gfx9.
For gfx9 the addressing for images has changed, so we need to
provide the hw with the level0, however we still need to scale
for format block differences (so our compressed upload paths still
work).

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit bae7723e13)
2017-08-29 19:14:12 +01:00
Dave Airlie
7f3555951e radv/image: don't rescale width/height if the format isn't changing
If the image view has the same format, we don't need to rescale
the w/h.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a74d987431)
2017-08-29 19:14:12 +01:00
Dave Airlie
bc39869414 radv: cleanup some image view descriptor setup.
Avoid passing the vulkan image creation into the image view descriptor
setup. This cleans up the usage of range inside the init, instead
using the properly inited values in the image view.

This is just a cleanup but some future vega changes will depend on it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5378b5d071)
2017-08-29 19:14:12 +01:00
Dave Airlie
93aee55a7f radv/gfx9: emit sx_mrt_blend registers
GFX9 needs the SX MRT blend registers programmed, port over
the code from radeonsi to workout the values from the blend
state, and program the registers on rbplus systems.

This fixes lots of:
dEQP-VK.pipeline.blend.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 9c080100d3)
2017-08-29 19:14:12 +01:00
Dave Airlie
996e3239c9 radv: bump space check for indexed draw.
For the GFX9 packet we need one more dword.

Fixes an assert in:
dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 864eb18527)
2017-08-29 19:14:12 +01:00
Dave Airlie
9b856ea323 radv/gfx9: fixup db/stencil disable.
This fixes disabled Z/stencil.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d987b4ab9e)
2017-08-29 19:14:12 +01:00
Dave Airlie
d8f8689101 radv/gfx9: fix level count in color register setup.
There was an off by one here.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 11834195e9)
2017-08-29 19:14:12 +01:00
Dave Airlie
dbca342014 radv/gfx9: use total levels in texture descriptor
We need to use all the levels when filling out the gfx9
descriptor.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit df09f1f3cd)
2017-08-29 19:14:12 +01:00
Kenneth Graunke
c0c03d0003 i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.
When changing fast clear colors, we need to emit new SURFACE_STATE
with the updated color at the next draw call.

Most things work today because the atoms that handle SURFACE_STATE
for images (mutable images, textures, render targets) also listen to
BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation.
However, this is overkill - most BLORP operations don't require us
to re-emit SURFACE_STATE.

One case where this is broken today is a fast clear to a different
color followed by a non-coherent framebuffer fetch.  The renderbuffer
read atom doesn't listen to BRW_NEW_BLORP, and would not get the new
fast clear color.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 54c41af0aa)
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
2017-08-29 19:14:12 +01:00
Marek Olšák
9013f80f67 radeonsi: emit VGT_REUSE_OFF in the right place
clip_regs aren't marked dirty when writes_viewport_index is changed.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 8dadb07790)
2017-08-29 19:14:12 +01:00
Marek Olšák
d93e6a0409 radeonsi/gfx9: properly handle imported textures with unexpected swizzle mode
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit fdef2f0fd1)
[Emil Velikov: r600_surface_import_metadata is not separate function,
tile_swizzle isn't in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeon/r600_texture.c
2017-08-29 19:14:12 +01:00
Marek Olšák
cf2f05ff91 radeonsi/gfx9: add a temporary workaround for a tessellation driver bug
The workaround will do for now. The root cause is still unknown.

This fixes new piglit: 16in-1out

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 166823bfd2)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
91715a3681 i965/clear: Quantize the depth clear value based on the format
In f9fd976e8a we changed the clear value to be stored as an
isl_color_value.  This had the side-effect same clear value check is now
happening directly between the f32[0] field of the isl_color_value and
ctx->Depth.Clear.  This isn't what we want for two reasons.  One is that
the comparison happens in floating point even for Z16 and Z24 formats.
Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float
formats, we were comparing as doubles and not floats.  This means that
the test basically always fails for anything other than 0.0f and 1.0f.
This caused a slight performance regression in Lightsmark 2008 because
it was using a depth clear value of 0.999 which can't be stored in a
32-bit float so we were doing unneeded resolves.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/101678
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 0ae9ce0f29)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/brw_clear.c
2017-08-29 18:37:57 +01:00
Rob Herring
9ba7693a9a Android: Fix LLVM duplicated symbols linking for N and M
Both statically linking libLLVMCore and dynamically linking libLLVM causes
duplicated symbols in gallium_dri.so and it fails to dlopen. We don't
really need to link libLLVMCore, but just need generated headers to be
built first. Dynamically linking to libLLVM instead is enough to do
that. Thanks to Qiang Yu for finding the root cause.

With this change, we can align all versions and just have libLLVM as a
shared lib dependency.

This also requires changes in the M and N versions of LLVM to export the
include paths for libLLVM. AOSP master is okay.

Fixes: 26aee6f4d5 ("Android: rework LLVM build support")
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
(cherry picked from commit 4734bfc02a)
2017-08-29 18:37:57 +01:00
Samuel Pitoiset
1f8cb4c243 radeonsi: update non-resident bindless descriptors if needed
Only resident bindless descriptors are currently updated and
re-uploaded, this makes sure that the non-resident ones are
also updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 2843c5d15c)
2017-08-29 18:37:57 +01:00
Topi Pohjolainen
da4d1fd084 intel/blorp: Adjust intra-tile x when faking rgb with red-only
v2 (Jason): Adjust directly in surf_fake_rgb_with_red()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit 393ec1a507)
2017-08-29 18:37:57 +01:00
Dave Airlie
7789126929 ac/nir: fixup layer/viewport export for GFX9.
GFX9 moved where the viewport index export goes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b040f51b61)
2017-08-29 18:37:57 +01:00
Christoph Haag
6389526ce5 mesa: only copy requested compressed teximage cubemap faces
This is analogous to commit 2259b11 which only fixed the regular case

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102308
Signed-off-by: Christoph Haag <haagch+mesadev@frickel.club>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 87556a650a)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
2813e83f6c i965/tex: Don't pass samples to miptree_create_for_teximage
In 76e2f390f9, when Topi switched num_samples from 0 to 1 for
single-sampled, he accidentally switched the last parameter in the call
to miptree_create_for_teximage from 0 to 1 thinking it was num_samples
when it was actually layout_flags.  Switching from 0 to 1 added the
MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a
busy BO instead of an idle one.  This caused the subsequent CPU upload
to consistently stall.  The end result was a 15% performance drop in the
SynMark v7 DrvRes microbenchmark.  This restores the old behavior and
fixes the performance regression.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes: 76e2f390f9
Bugzilla: https://bugs.freedesktop.org/102260
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit f24cf82d6d)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
ea5c466c91 i965/miptree: Return NONE from texture_aux_usage when fully resolved
This little optimization improves the performance of SynMark v7
TexFilterTri by almost 10% on Sky Lake GT4 among other improvements.
We've been doing it for some time but somehow it got dropped during
the miptree refactoring.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/102258
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 61d2f3f1c2)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
d174214218 i965: Stop looking at NewDriverState when emitting 3DSTATE_URB
Looking at NewDriverState is not safe in general.  The state atom system
is set up to ensure that new bits that get added to NewDriverState get
accumulated into the set of bits used when emitting atoms but it doesn't
go the other way.  If we read NewDriverState, we may not get the full
picture because the per-pipeline state (3D or compute) does not get
added to NewDriverState before state emit is done.  It's especially
dangerous to do this from BLORP (either explicitly or implicitly when
BLORP calls gen7_upload_urb) because that does not happen during one of
the normal state upload paths.

This commit solves the problem by whacking all of the per-shader-stage
URB sizes to zero whenever we change the total URB size.  We still have
to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but
the actual decision in gen7_upload_urb can now be based entirely on URB
sizes rather than on state atoms.  This also makes BLORP correct because
it just asks for a new URB config whenever the vsize is too small and so
any change to the total URB size will trigger blorp to re-emit as well
because 0 < vs_entry_size.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/102289
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d5e217dbfd)
2017-08-29 18:37:57 +01:00
Kenneth Graunke
a14dd9fff6 i965: Mark all EGLimages as non-coherent.
EGLimages are shared with external users, and we don't know what they're
going to do with them.  They might scan them out.  They might access
them in a way that doesn't work with our explicit clflushing.

It's safest to simply mark them non-coherent.

Chris Wilson caught this problem and wrote a similar (though less
aggressive) patch to solve it; the miptree code has since undergone
a lot of refactoring so I had to rewrite it.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit bc56dfbf3f)
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/intel_mipmap_tree.c
2017-08-29 18:37:57 +01:00
Jason Ekstrand
3e62ba0907 i965/miptree: Rework create flags
The only one of the three remaining flags that has anything whatsoever
to do with layout is TILING_NONE.  This commit renames them to
MIPTREE_CREATE_*, documents the meaning of each flag, and makes the
create functions take an actual enum type so GDB will print them nicely.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 24a0da338f)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
1011fd22ae i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)
The only force tiling flag we really care about is LAYOUT_TILING_NONE.
The others don't actually do anything but add confusion.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 55116839d9)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
dd03cb5c5e i965/miptree: Delete MIPTREE_LAYOUT_FOR_SCANOUT
The flag hasn't affected actual surface layout for some time.  The only
purpose it served was to set bo->cache_coherent = false on the BO used
to create the miptree.  This is fairly silly because we can just set
that directly from the caller where it makes much more sense.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit a5a673dfa7)
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/intel_mipmap_tree.c
2017-08-29 18:37:57 +01:00
Jason Ekstrand
046730b8a3 i965/miptree: Delete some unused layout flags
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 2bca18be44)
2017-08-29 18:37:57 +01:00
Jason Ekstrand
f83d979759 i965/miptree Remove layout_flags parameter form is_mcs_supported
The one caller of is_mcs_supported passes 0 in as the layout_flags
unconditionally.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 0e4d9a4b37)
2017-08-29 18:36:14 +01:00
Dave Airlie
2cdb51e76d radv: disable texture gather workaround on gfx9.
Not required anymore.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4c02e2bd95)
[Emil Velikov: chip_class is in ctx::options, not ctx::abi]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-29 16:18:49 +01:00
Emil Velikov
15f23fb855 Update version to 17.2.0-rc5
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-08-21 11:49:19 +01:00
Emil Velikov
dd4fafcfda cherry-ignore: ignore storage offset fixes
For stable the regressions were addressed by reverting the offending
commits - see previous commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-19 02:57:19 +01:00
Samuel Pitoiset
17a3e4891b Revert "mesa: stop assigning unused storage for non-bindless opaque types"
This reverts commit fcbb93e860 and
also  commit 7c5b204e38 to avoid
compilation errors.

Basically, the parameter indexes look wrong when a non-bindless
sampler is declared inside a nested struct (because it is skipped).
I think it's safer to just restore the previous behaviour which is
here since ages and also because the initial attempt is only a
little performance improvement.

This fixes a regression with
ES2-CTS.functional.shaders.struct.uniform.sampler_nested*.

Note: this patch is only for 17.2 since the fixes in master are rather
invasive. Namely:

365d34540f mesa: correctly calculate the storage offset for i915
de0e62e106 st/mesa: correctly calculate the storage offset

Fixes: fcbb93e860 ("mesa: stop assigning unused storage for non-bindless
opaque types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101983
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-08-19 02:57:19 +01:00
Jason Ekstrand
85cc3533fa i965/miptree: Set supports_fast_clear = false in make_shareable
The make_shareable function deletes the aux buffer and then whacks
aux_usage to ISL_AUX_USAGE_NONE but not unsetting supports_fast_clear.
Since we only look at supports_fast_clear to decide whether or not to do
fast clears, this was causing assertion failures.

Reported-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101925
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit e7a52cc381)
2017-08-19 02:57:19 +01:00
Eric Anholt
93bd5fbfe1 broadcom/vc4: Build the vc4_tiling_lt_neon.c with -mfpu=neon on ARM.
If you don't pass this, the compiler refuses to compile the assembly for
pre-v7 CPUs.  This also keeps us from building identical, non-NEON code on
aarch64 and x86.

Fixes: a373f77662 ("vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.")

v2: Fix Android build by just appending NEON_C_SOURCES when
    ARCH_ARM_HAVE_NEON.

Tested-by: Rob Herring <robh@kernel.org>
(cherry picked from commit bd5efbd70b)
[Emil Velikov: address libvc4_la_LIBADD conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/vc4/Makefile.am
2017-08-19 02:57:19 +01:00
Eric Anholt
833f12abdf configure.ac: Introduce HAVE_ARM_ASM/HAVE_AARCH64_ASM and the -D flags.
I've been trying to get away without these conditionals in vc4's NEON
code, but it meant compiling extra unused code on x86, and build failing
on ARMv6.

v2: Use the _arm/_arm64 flags to simplify detection (suggested by Rob),
    but hide the _arm version under ARCH_ARM_HAVE_NEON to keep from trying
    to build this stuff for armv5te.

Tested-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit ba8533b6ea)
2017-08-19 02:57:19 +01:00
Eric Anholt
1fc44a3ba0 util: Fix build on old glibc.
We need to link librt for u_thread.h's clock_gettime() call.

Fixes: b822d9dd67 ("gallium/util: move u_queue.{c,h} to src/util")
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit b94ddc181b)
2017-08-19 02:57:19 +01:00
Scott D Phillips
6ccb75e869 intel/genxml: Fix gen10 BLEND_STATE variable length packing
BLEND_STATE packing was modified to be variable-length in:

 9670124e31 genxml: Make BLEND_STATE command support variable length array.

The initial gen10.xml still had the old, fixed-length style
definition for BLEND_STATE. So gen10_upload_blend_state would
overwrite the packed BLEND_STATE_ENTRYs with its own fixed array
of all-zero entries when packing BLEND_STATE. This caused
BLEND_STATE upload to not work at all.

Fixes: aa416f515a ("i965/genxml: Add gen10.xml")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
(cherry picked from commit d6539608a4)
2017-08-19 02:57:19 +01:00
Chris Wilson
b4fec4271b i965: Always allow CPU readback of the scanout on LLC platforms
LLC platforms are magic in that reads from the CPU are always cache
coherent, or rather GPU writes that bypass LLC do still invalidate the
appropriate cache line.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 49eda75df6)
2017-08-19 02:57:19 +01:00
Ilia Mirkin
efb9b5740e glsl: add a few missing int64 constant propagation cases
Fixes KHR-GL45.shader_ballot_tests.ShaderBallotAvailability, which
causes some silly swizzles to appear, triggering this optimization to
get hit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 9c8f017f77)
2017-08-19 02:57:19 +01:00
Dave Airlie
e44393cb23 radv: disable support for VEGA for now.
I'm working on this, but I'm not sure I'll make 17.2 at this stage,
maybe 17.2.1.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 611076a41a)
2017-08-19 02:57:19 +01:00
Ilia Mirkin
81b5a6a85b nv50/ir: fix TXQ srcMask
src0.x is always read for the LOD, irrespective of which outputs are
read.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 934511d1f3)
2017-08-19 02:57:19 +01:00
Ilia Mirkin
5795e42116 nv50/ir: fix srcMask computation for TG4 and TXF
This affects which inputs are marked as used. In a situation where only
the texture instruction uses an input, it might have been ignored as
unused due to input masks.

Affects subtests of KHR-GL45.texture_cube_map_array.sampling

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 054c54d1be)
2017-08-19 02:57:19 +01:00
Frank Richter
42e8f3ccdf gallium/os: fix os_time_get_nano() to roll over less
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102241
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 7fb7287ce7)
2017-08-19 01:46:08 +01:00
Frank Richter
e452ed26ff st/wgl: check for negative delta in wait_swap_interval()
This can happen because of rollover.  See bug report for details.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102241
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit d90e05ad48)
2017-08-19 01:46:08 +01:00
Frank Richter
c7c6ba44ca st/mesa: fix a null pointer access
Fixes crash with llvmpipe on Windows.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102148
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 496a691e35)
2017-08-19 01:46:08 +01:00
Tim Rowley
bdab7c69f5 swr/rast: Fix invalid casting for calls to Interlocked* functions
CID: 1416243, 1416244, 1416255
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit b333bc753e)
[Emil Velikov: resolve trivial conflicts - LONG -> long]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/swr/rasterizer/core/api.cpp
	src/gallium/drivers/swr/rasterizer/core/threads.cpp
2017-08-19 01:45:47 +01:00
Ilia Mirkin
47507ec1fd glsl/ast: update rhs in addition to the var's constant_value
We continue in the code to do some more things with the rhs, including
setting a constant initializer. If the type is wrong, this causes some
confusion down the line, leading to assertions. This makes sure that the
rhs processing continues to flow as-if the type was correct to start
with (even though the state has been marked as an error state).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101766
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 978c4c597a)
2017-08-19 01:42:08 +01:00
Dave Airlie
3fb5cc2637 radv/gfx9: for fast clear use is_linear flag.
The legacy test won't work on gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 694d59fbaf)
2017-08-19 01:42:08 +01:00
David Airlie
42d6e7eba2 radv/gfx9: handle GFX9 opaque metadata
port the opaque metadata changes from radeonsi for gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e43cc3e3af)
2017-08-19 01:36:25 +01:00
David Airlie
f60ff71b6f radv: emit db_htile_surface reg on gfx9 as well
This is also a GFX9 register.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 674ecbfef2)
2017-08-19 01:36:25 +01:00
Dave Airlie
f70f216564 radv/gfx9: remove some leftover gfx6 descriptor setup.
We set this later in the non-gfx9 path, just remove these
bits from here.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit fc600eb98d)
2017-08-19 01:36:25 +01:00
Dave Airlie
827bf79052 radv/gfx9: fix set predication packet.
The predication packet changed format on GFX9, update the driver.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5247b311e9)
2017-08-19 01:36:25 +01:00
Marek Olšák
2b10b3a417 radeonsi: disable CE by default
It makes performance worse by a very small (hard to measure) amount.
We've done extensive profiling of this feature internally.

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 1ab7fed707)
2017-08-19 01:36:25 +01:00
Scott D Phillips
27e7a3a5ef i965/blorp: Correct type of src_format in call to intel_miptree_texture_aux_usage
intel_miptree_texture_aux_usage() takes an isl_format, but we are
passing a mesa_format. clang warns:

 brw_blorp.c:305:52: warning: implicit conversion from enumeration
    type 'mesa_format' to different enumeration type
    'enum isl_format' [-Wenum-conversion]
       intel_miptree_texture_aux_usage(brw, src_mt, src_format);
       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~              ^~~~~~~~~~

Fixes: fc1639e46d ("i965/blorp: Use texture/render_aux_usage for blits")
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit f7dfc44c61)
2017-08-19 01:36:25 +01:00
Ilia Mirkin
da005f5566 nv50/ir: clean up saturated values immediately
Since we don't iterate to a fixed point, we can end up in situations
where we have a SAT instruction + a long immediate. This is not legal.
However since it's immediately computable, just run unary straight away
to handle the situation.

Fixes: 24a799ad35 ("nv50/ir: fix ConstantFolding with saturation")
Reported-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 165e18dd21)
2017-08-19 01:36:25 +01:00
Jeremy Huddleston Sequoia
cc8ae8842b glxcmds: Fix a typo in the __APPLE__ codepath
s/DummyContext/dummyContext/

Regressed-in: 5d9b50e596
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
(cherry picked from commit c1c4c18a80)
2017-08-17 15:48:20 -07:00
Emil Velikov
3165f9877e Update version to 17.2.0-rc4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-12 17:04:27 +01:00
Dave Airlie
1e11687029 radv: force cs/ps/l2 flush at end of command stream. (v2)
This seems like a workaround, but we don't see the bug on CIK/VI.

On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.*
tests, when one tests complete, the first flush at the start of the next
test causes a VM fault as we've destroyed the VM, but we end up flushing
the compute shader then, and it must still be in the process of doing
something.

Could also be a kernel difference between SI and CIK.

v2: hit this with a bigger hammer. This fixes a bunch of hangs
in the vk cts with the robustness tests.

Fixes: f4e499ec79 ("radv: add initial non-conformant radv vulkan driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 82ba384c10)
2017-08-11 21:00:49 +01:00
Dave Airlie
ea595756f8 radv: fix MSAA on SI gpus.
This ports the workaround from radeonsi, that was missing in radv.

This fixes Talos rendering when MSAA is enabled on my Tahiti card.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8bf3930751)
2017-08-11 21:00:46 +01:00
Dave Airlie
ffd8120284 radv: fix f16->f32 denorm handling for SI/CIK. (v2)
This just copies the code from the -pro shaders,
and fixes the tests on CIK.

With this CIK passes the same set of conformance
tests as VI.

Fixes: 83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3f389f75b6)
2017-08-11 21:00:43 +01:00
Bas Nieuwenhuizen
9d65214f3d radv: Use the correct channel for alpha in resolve srgb conversion.
The argument here is a bitmask, so the old code selected .xy, which
got silently truncated to .x when constructing the vec4 from components,
instead of using .w.

Fixes: 588185eb6b "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit acba3a3151)
2017-08-11 21:00:40 +01:00
Bas Nieuwenhuizen
a57390cee0 radv: Only convert linear->srgb in compute resolves.
It justs works with the fragment shader resolve, so no need to do
a custom conversion. In fact with SRGB dest, it actually gives
wrong results.

Fixes: 69136f4e63 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 15e5a7a683)
2017-08-11 21:00:37 +01:00
Bas Nieuwenhuizen
8b706102eb radv: Don't use SRGB format for image stores during resolve.
These seem to store very bogus results. Luckily there is some code
that converts srgb->linear already, so just making the descriptor
format UNORM should work.

Fixes: 588185eb6b "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8286c3a49f)
2017-08-11 21:00:34 +01:00
Marek Olšák
7f5d86ebaa radeonsi/gfx9: use the VI codepath for clamping Z
This fixes corrupted shadows in Unigine Valley.
The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8
for depth.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 27fef5d52d)
2017-08-11 20:59:31 +01:00
Kenneth Graunke
1c1653d7b0 isl: Validate row pitch of stencil surfaces.
Also, silence an obnoxious finishme that started occurring for all
GL applications which use stencil after the i965 ISL conversion.

v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using
    separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using
    combined depth-stencil.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 5563872dbf)
2017-08-11 20:59:28 +01:00
Emil Velikov
d4100b0d09 egl: avoid eglCreatePlatform*Surface{EXT,} crash with invalid dpy
If we have an invalid display fed into the functions, the display lookup
will return NULL. Thus as we attempt to get the platform type, we'll
deref. it leading to a crash.

Keep in mind that this will not happen if Mesa is built without X11 or
when the legacy eglCreate*Surface codepaths are used.

A similar check was added with earlier commit 5e97b8f5ce ("egl: Fix
crashes in eglCreate*Surface), although it was only applicable when the
surfaceless platform is built.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 26fbb9eacd)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/egl/main/eglapi.c
2017-08-11 20:59:02 +01:00
Tim Rowley
bb6e5e5476 configure: remove trailing "-a" in swr architecture test
Fixes "configure: line 27326: test: argument expected"

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 4d9b0dcccb)
2017-08-11 20:58:19 +01:00
Marek Olšák
08d49e074d ac: fail shader compilation if libelf is replaced by an incompatible version
UE4Editor has this issue.

This commit prevents hangs (release build) or assertion failures (debug
build). It doesn't fix the editor, but catastrophic scenarios are
prevented.

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 4630ede102)
2017-08-11 20:58:14 +01:00
Karol Herbst
75f5abb82f nv50/ir: fix ConstantFolding with saturation
For mul(a, +-1) codegen can generate OP_MOV with a saturation flag
set which is ignored at emission. The same can happen with add(a, 0),
and others.

Adding an assert for detecting more of such issues.

Fixes wrongly rendered water in Hitman Absolution running under wine.
Also a few shaders in Mad Max and Alien Isolation produce such MOVs.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
[imirkin: generalize the fix for other cases]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 24a799ad35)
2017-08-11 20:57:54 +01:00
Alex Smith
f0b6298c05 radv: Fix decompression on multisampled depth buffers
Need to take the sample count into account in the depth decompress and
resummarize pipelines and render pass.

Fixes: f4e499ec79 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 2e9a13bf22)
2017-08-11 20:57:50 +01:00
Jason Ekstrand
ac04187e33 i965/miptree: Call alloc_aux in create_for_bo
Originally, I had moved it to the caller to make some things easier when
adding the CCS modifier.  However, this broke DRI2 because
intel_process_dri2_buffer calls intel_miptree_create_for_bo but never
calls intel_miptree_alloc_aux.  Also, in hindsight, it should be pretty
easy to make the CCS modifier stuff work even if create_for_bo allocates
the CCS when DISABLE_AUX is not set.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 8e5808fc0c)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/intel_mipmap_tree.c
2017-08-11 20:57:36 +01:00
Jason Ekstrand
b1514579c2 intel/isl: Don't align the height of the last array slice
We were calculating the total height of 2D surfaces by multiplying the
row pitch by the number of slices.  This means that we actually request
slightly more space than actually needed since the padding on the last
slice is unnecessary.  For tiled surfaces this is not likely to make a
difference.  For linear surfaces, on the other hand, this means we may
require additional memory.  In particular, this makes the i965 driver
reject EGL imports of buffers which do not have this extra padding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 4d27c6095e)
2017-08-11 20:52:22 +01:00
Jason Ekstrand
dc63c715cb intel/isl: Stop padding surfaces
The docs contain a bunch of commentary about the need to pad various
surfaces out to multiples of something or other.  However, all of those
requirements are about avoiding GTT errors due to missing pages when the
data port or sampler accesses slightly out-of-bounds.  However, because
the kernel already fills all the empty space in our GTT with the scratch
page, we never have to worry about faulting due to OOB reads.  There are
two caveats to this:

 1) There is some potential for issues with caches here if extra data
    ends up in a cache we don't expect due to OOB reads.  However,
    because we always trash the entire cache whenever we need to move
    anything between cache domains, this shouldn't be an issue.

 2) There is a potential issue if a surface gets placed at the very top
    of the GTT by the kernel.  In this case, the hardware could
    potentially end up trying to read past the top of the GTT.  If it
    nicely wraps around at the 48-bit (or 32-bit) boundary, then this
    shouldn't be an issue thanks to the scratch page.  If it doesn't,
    then we need to come up with something to handle it.

Up until some of the GL move to ISL, having the padding code in there
just caused us to harmlessly use a bit more memory in Vulkan.  However,
now that we're using ISL sizes to validate external dma-buf images,
these padding requirements are causing us to reject otherwise valid
images due to the size of the BO being too small.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c15b92ce11)
2017-08-11 20:52:19 +01:00
Jason Ekstrand
9d9ea2c5a4 anv/formats: Allow sampling on depth-only formats on gen7
We can't sample from depth-stencil formats but on gen7 but we can sample
from depth-only formats.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102024
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 06d3115bb9)
2017-08-11 20:52:16 +01:00
Dave Airlie
07b5c78836 radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)
This is a bug in the app, but I'd rather avoid hanging the GPU,
esp if someone is running in validation and it takes out their
development environment.

v2: get it right, reverse the polarity.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 36a1b61321)
2017-08-11 20:52:13 +01:00
Emil Velikov
59f7fdb85e egl/x11: don't leak xfixes_query in the error path
If we get a xfixes v1.x we'll error out, without freeing the
xfixes_query reply.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit c961b679fe)
2017-08-11 20:52:08 +01:00
Emil Velikov
29df4deef2 Update version to 17.2.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-07 12:45:40 +01:00
Jason Ekstrand
e4371d14f1 anv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
2017-08-05 00:09:26 +01:00
Tomasz Figa
0b2c034f64 st/dri: enable 32-bit RGBX/RGBA formats only on Android
X/GLX can't handle them. This removes almost 500 GLX visuals that were
incorrectly exposed.

This is a less invasive version of Marek's .getCapability series.
Note: the patch is not applicable for master, but only for the 17.2
branch.

Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
CC: <mesa-stable@lists.freedesktop.org>
Fixes: f33d8af7aa "st/dri: add 32-bit RGBX/RGBA formats"
[Emil Velikov: commit message polish]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-05 00:09:26 +01:00
Tim Rowley
f4e163094d swr/rast: fix scons gen_knobs.h dependency
Copy/paste error was duplicating a gen_knobs.cpp rule.

Fixes: 5079c277b5 ("swr: [scons] Fix windows build")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit e4a6ae06cf)
2017-08-05 00:09:26 +01:00
Timothy Arceri
4a181e6244 mesa/st: fix conditional jump depends on uninitialised value
Reported by valgrind at:
glsl_to_tgsi_visitor::visit(ir_expression*) (st_glsl_to_tgsi.cpp:1560)

When compiling the Deus Ex shaders.

Fixes: 28a5e7104 ("st/glsl_to_tgsi: handle precise modifier")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 06237fc9e1)
2017-08-05 00:09:26 +01:00
Scott D Phillips
8ef9fe7229 gles: Restore some lost typedefs
GLES/gl.h has historically provided some typedefs that are not
used in the API itself. Restore these typedefs that were lost to
avoid breaking applications.

These seem to be the only typedefs removed in the update.

Fixes: 7fd0817 "Update Khronos-supplied headers"

[Eric: added a big warning to revert this patch when pulling the updated header]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 3db05ed1d1)
2017-08-05 00:09:26 +01:00
Dave Airlie
4f872e62c2 Revert "st_glsl_to_tgsi: rewrite rename registers to use array fully."
This reverts commit 3008161d28,
which caused a regression for VMWare.

The initial code had some recursion in it, that I removed by accident
trying to add back the recursion broke lots of things, take the high
road and revert for now.

Fixes: 3008161d (st_glsl_to_tgsi: rewrite rename registers to use array fully.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b8bea9a050)
2017-08-05 00:09:26 +01:00
Dave Airlie
c5fac38ced radv: handle 10-bit format clamping workaround.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*
for a2r10g10b10 formats as destination on SI/CIK hardware.

This adds support to the meta program for emitting 10-bit
outputs, and adds 10-bit support to the fragment shader key.

It also only does the int8/10 on SI/CIK.

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit df61a05019)
2017-08-05 00:09:26 +01:00
Bas Nieuwenhuizen
579ecfd91e radv: Don't underflow non-visible VRAM size.
In some APU situations the reported visible size can be larger than
VRAM size. This properly clamps the value.

Surprisingly both CTS and spec seem to allow a heap type with size 0,
so this seemed like the easiest option to me.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: 4ae84efbc5 "radv: Use enum for memory heaps."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 8229706ad8)
2017-08-05 00:09:26 +01:00
Bruce Cherniak
6b279b3271 st/osmesa: add osmesa framebuffer iface hash table per st manager
Commit bbc29393d3 didn't include osmesa state_tracker.  This patch adds
necessary initialization.

Fixes crash in OSMesa initialization.

Created-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 9966c85e01)
2017-08-05 00:09:26 +01:00
Dave Airlie
6efb8d79a9 intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.
If dual object compile fails (as seems to happen with virgl a
fair bit, and does piglit even have any tests for it?), we end up
not restarting the pull params, so we call
vec4_visitor::move_uniform_array_access_to_pull_constant
a second time and it runs over the ends of the alloc.

Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test
running inside virgl on ivybridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 271fa3a684)
2017-08-05 00:09:25 +01:00
Chris Wilson
795b712bd7 i965/blit: Remember to include miptree buffer offset in relocs
Remember to add the offset to the start of the buffer in the relocation
or else we write 0xff into random bytes elsewhere.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fb63c43fd1)
2017-08-05 00:09:25 +01:00
Kenneth Graunke
43a2b178c2 i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.

Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):

intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 595a47b829)
2017-08-05 00:09:25 +01:00
Jason Ekstrand
d5def4f5a9 spirv: Fix SpvImageFormatR16ui
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 95c6a97464)
2017-08-05 00:09:25 +01:00
Thomas Hellstrom
f2a60ff20a dri3: Wait for all pending swapbuffers to be scheduled before touching the front
This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and
creation of fake front until all pending SwapBuffers have been committed to
hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 185ef06fd2)
2017-08-05 00:09:25 +01:00
Nicolai Hähnle
3c8673d420 gallium/radeon: fix ARB_query_buffer_object conversion to boolean
The issue here is that the immediate is treated as a 64-bit value,
and fetching it does not work reliably with swizzles that are different
from xy and zw.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit da83687c4b)
2017-08-05 00:09:25 +01:00
Dave Airlie
381ccaa1cb radeon/ac: use ds_swizzle for derivs on si/cik.
This looks like it's supported since llvm 3.9 at least,
so switch over radeonsi and radv to using it, -pro also
uses this. We can now drop creating lds for these operations
as the ds_swizzle operation doesn't actually write to lds at all.

Acked-by: Marek Olšák <marek.olsak@amd.com>
(stable requested due to fixing radv CIK conformance tests)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit cb6f16dce9)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2017-08-05 00:09:25 +01:00
Connor Abbott
2dd6030fbb ac/nir: fix lsb emission
This makes it match radeonsi. The LLVM backend itself will emit the
correct instruction, but LLVM might do incorrect optimizations since it
thinks the output is undefined when the input is 0, even though it's not
supposed to be. We really need a new intrinsic, or for the backend to
become smarter and recognize this pattern.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <basni@google.com>
(cherry picked from commit 6d731c5651)
2017-08-05 00:09:25 +01:00
Connor Abbott
a90d99f7a5 nir: fix algebraic optimizations
The optimizations are only valid for 32-bit integers. They were
mistakenly firing for 64-bit integers as well.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit de91461575)
2017-08-05 00:09:25 +01:00
Marek Olšák
6806773905 Revert "st/mesa: release sampler views when redefining a texture in st_context_teximage"
This reverts commit 5c1241268b.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101961

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d85802e501)
2017-08-05 00:09:25 +01:00
Nicolai Hähnle
3e872f4b53 radeonsi: ensure that temp array allocas are in the entry block
Otherwise, code generation fails. This has become necessary since some
shaders are wrapped in control flow.

Fixes: 081ac6e5c6 ("radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 2879a602dd)
2017-08-05 00:09:25 +01:00
Samuel Pitoiset
21ea75b3e9 mesa: fix mismatch when returning 64-bit bindless uniform handles
The slower convert-and-copy process performs a bad conversion
because it converts the value to signed 64-bit integer, but
bindless uniform handles are considered unsigned 64-bit.

This fixes "Check glUniform*() with mixed texture units/handles"
from arb_bindless_texture-uniform piglit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit b38c9c57f2)
2017-08-05 00:09:25 +01:00
Emil Velikov
58fe86a6d6 Update version to 17.2.0-rc2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-31 10:52:13 +01:00
Samuel Pitoiset
d466a70532 st/glsl_to_tgsi: fix getting the image type for array of structs
Since array splitting for AoA is disabled, we have to retrieve
the type of the first non-array type when an array of images is
declared inside a structure. Otherwise, it will hit an assert
in glsl_type::sampler_index() because it expects either a sampler
or an image type.

This fixes a regression in the following piglit test:
arb_bindless_texture/compiler/images/arrays-of-struct.frag

Fixes: 57165f2ef8 ("glsl: disable array splitting for AoA")
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f99e9335e2)
2017-07-31 10:26:27 +01:00
Marek Olšák
e62eddcdbe st/mesa: release sampler views when redefining a texture in st_context_teximage
Noticed randomly.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 5c1241268b)
2017-07-31 10:25:55 +01:00
Dave Airlie
6d07e58afb radv: for stencil only set Z tile mode index to same value
On SI this was causing a hang in
dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint

This was due to not handling the tile mode index for depth like
I fixed previously for new GPUs.

Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 800d162209)
2017-07-31 10:24:42 +01:00
Dave Airlie
f9e563597d virgl: drop precise modifier.
The host doesn't understand this yet, so drop it for now.

Fixes: virgl regressions.

Fixes: af22adee4f (tgsi: add precise flag to tgsi_instruction)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 554aa09440)
2017-07-31 10:23:09 +01:00
Marek Olšák
5b61ba4432 radeonsi: update dirty_level_mask only when flushing or unbinding framebuffer
This fixes corruption with bindless textures in Dawn Of War 3.

The do_update_surf_dirtiness mechanism was complicated and dirty_level_mask
was only updated after the first draw call. The problem is bindless textures
are checked for decompression every draw call and we would only decompress
after the first draw call. The solution is to set dirtiness after the last
draw call to the framebuffer, so the (unconditional) decompression of
bindless textures happens at the right time.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit f4d095cc65)
2017-07-31 10:21:17 +01:00
Marek Olšák
6625382b1c st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers
This fixes the black Feral launcher window.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
(cherry picked from commit 7257c171e9)
2017-07-31 10:20:44 +01:00
Nicolai Hähnle
2bca74253d radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)
With merged ESGS shaders, the GS part of a wave may be empty, and the
hardware gets confused if any GS messages are sent from that wave. Since
S_SENDMSG is executed even when EXEC = 0, we have to wrap even
non-monolithic GS shaders in an if-block, so that the entire shader and
hence the S_SENDMSG instructions are skipped in empty waves.

This change is not required for TCS/HS, but applying it there as well
simplifies the logic a bit.

Fixes GL45-CTS.geometry_shader.rendering.rendering.*

v2: ensure that the TCS epilog doesn't run for non-existing patches

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 081ac6e5c6)
2017-07-31 10:20:20 +01:00
Nicolai Hähnle
b36ff2d1f2 radeonsi/gfx9: fix vertex idx in ES with multiple waves per threadgroup
Cc: mesa-stable@lists.freedesktop.org
Reviewed: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 873789002f)
2017-07-31 10:20:12 +01:00
George Kyriazis
99b2613ce1 swr: fix transform feedback logic
The shader that is used to copy vertex data out of the vs/gs shaders to
the user-specified buffer (streamout or SO shader) was not using the
correct offsets.

Adjust the offsets that are used just for the SO shader:
- Make sure that position is handled in the same special way
  as in the vs/gs shaders
- Use the correct offset to be passed in the core
- consolidate register slot mapping logic into one function, since it's
  been calculated in 2 different places (one for calcuating the slot mask,
  and one for the register offsets themselves

Also make room for all attibutes in the backend vertex area.

Fixes:
- all vtk GL2PS tests
- 18 piglit tests (16 ext_transform_feedback tests,
  arb-quads-follow-provoking-vertex and primitive-type gl_points

v2:

- take care of more SGV slots in slot mapping logic
- trim feState.vsVertexSize
- fix GS interface and incorporate GS while calculating vsVertexSize

Note that vsVertexSize is used in the core as the one parameter that
controls vertex size between all stages, so it has to be adjusted appropriately
for the whole vs/gs/fs pipeline.

Also note that GS and SO is not fully implemented.  This will be addressed
later.

fixes:
- fixes total of 20 piglit tests

CC: 17.2 <mesa-stable@lists.freedesktop.org>

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit 194ff5eed1)
2017-07-31 10:19:55 +01:00
Dave Airlie
f9c7549605 radv/ac: port SI TC L1 write corruption fix.
This ports 72e46c988 to radv.
    radeonsi: apply a TC L1 write corruption workaround for SI

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e77ff11ffe)
2017-07-27 19:54:53 +01:00
Dave Airlie
2ce4f0afd3 radv/ac: realign SI workaround with radeonsi.
This ports: da7453666a
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.

Just noticed in passing.

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a81e99f50a)
2017-07-27 19:54:52 +01:00
Dave Airlie
546282e8bc radv: only report external semaphore info for opaque fd.
Until we support sync fd, don't report the info.

Fixes CTS dEQP-VK.api.external.semaphore.sync_fd.* from crashing.

Fixes: eaa56eab6 (radv: initial support for shared semaphores (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6cbc8cf178)
2017-07-27 19:54:52 +01:00
Dave Airlie
de55bc8f49 radv: fix buffer views on SI/CIK.
Fixes CTS dEQP-VK.memory.pipeline_barrier.host_write_uniform_texel_buffer.1024
on SI/CIK with radv.

Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ca82ef5ac7)
2017-07-27 19:54:52 +01:00
Daniel Stone
f0b7563a36 st/dri2: Return invalid modifier when no driver support
Always initialise whandle.modifier for DRIImage modifier queries, so if
the driver doesn't support it then we return false for the query.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: d33fe8b84e ("st/dri: enable DRIimage modifier queries")
(cherry picked from commit 45383d32d4)
2017-07-27 19:54:52 +01:00
Daniel Stone
5bee196840 st/dri: Check get-handle return value in queryImage
In the DRIImage queryImage hook, check if resource_get_handle() failed
and return FALSE if so.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit b4a18f13ce)
2017-07-27 19:54:52 +01:00
Daniel Stone
2a1792981c egl/wayland: Ignore invalid modifiers
If the underlying driver does not support modifiers, dmabuf will still
advertise formats through the 'modifier' event, but send them with an
invalid modifier. Ignore them if this is the case, rather than passing
them through to the driver.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
(cherry picked from commit dd072cf4b1)
2017-07-27 19:54:52 +01:00
Tim Rowley
a2b7477603 swr/rast: non-regex knob fallback code for gcc < 4.9
gcc prior to 4.9 didn't implement <regex>, causing a startup crash
in the swr knob parameter reading code.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit e21fc2c625)
2017-07-27 19:54:52 +01:00
Dave Airlie
3e777d5cab virgl: encode index buffer offset.
Fixes arb_vertex_buffer_object-combined-vertex-index

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit c4652a0a5b)
2017-07-27 19:54:52 +01:00
Marek Olšák
9bb6aa5794 ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older
v2: don't do it for compressed textures (bpp = 0)

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
(cherry picked from commit 5e81df0f10)
2017-07-27 19:54:52 +01:00
Marek Olšák
90bbcb93b1 radeonsi: decrease the number of compiler threads
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit ed2b3f5c81)
2017-07-27 19:54:52 +01:00
Marek Olšák
529c440dd3 gallium/radeon: make S_FIXED function signed and move it to shared code
This fixes a bug uncovered by:
    2412c4c81e
    util: Make CLAMP turn NaN into MIN.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 433f6f7ac9)
2017-07-27 19:54:52 +01:00
Charmaine Lee
94e0de90ee st/mesa: create framebuffer iface hash table per st manager
With commit 5124bf9823, a framebuffer interface hash table is
created in st_gl_api_create(), which is called in
dri_init_screen_helper() for each screen. When the hash table is
overwritten with multiple calls to st_gl_api_create(), it can cause
race condition. This patch fixes the problem by creating a
framebuffer interface hash table per state tracker manager.

Fixes crash with steam.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101876
Fixes: 5124bf9823 ("st/mesa: add destroy_drawable interface")
Tested-by: Christoph Haag <haagch@frickel.club>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit bbc29393d3)

Squashed with:

st/mesa: fix unconditional return in st_framebuffer_iface_remove

Noticed by James Legg @ Feral.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 914f11e75b)

Squashed with:

st/mesa: Fix inversed test in st_api_destroy_drawable

Fixes a drawable leak.

Fixes: bbc29393d3 ("st/mesa: create framebuffer iface hash table per
                      st manager")
Bugzilla: https://bugs.freedesktop.org/101930
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 57132d126f)
2017-07-27 19:54:24 +01:00
Grigori Goronzy
3180f0fa0d egl: move KHR_no_error vs debug/robustness check further down
We'll fail to flag an error if the context flags appear after the
no-error attribute in the context attribute list.

Delay the check to after attribute parsing to fix this.

Fixes: 4909519a66 ("egl: Add EGL_KHR_create_context_no_error support")
Cc: mesa-stable@lists.freedesktop.org
[Emil Velikov: add fixes/stable tags, commit message polish]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

(cherry picked from commit 39bf7756b9)
2017-07-27 18:56:45 +01:00
Nicolai Hähnle
e7f14a8b52 radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+
The number of supported waves per thread group has been reduced to 16
with gfx9. Trying to use 32 waves causes hangs, and barriers might
not work correctly with > 16 waves.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit a0e6b9a2db)
2017-07-27 18:56:45 +01:00
Nicolai Hähnle
7f5d9d7a6d radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI
The firmware version numbers for SI were wrong. The new numbers are probably
too conservative (we don't have a definitive answer by the firmware team),
but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
Tahiti (by Gustaw) and on Verde (by myself).

While this is technically adding a feature, it's a feature we thought we had
for a long time. The change is small enough and we're early enough in the 17.2
release cycle that it should still go in.

Reported-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 65fbaab0b7)
2017-07-27 18:56:45 +01:00
Iago Toral Quiroga
3d0960e761 anv: only expose up to 28 vertex attributes
The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs.
However, the maximum allowed value of "Vertex URB Entry Read Length"
in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements.
Because we also need to reserve a vertex buffer to upload
VertexIndex/InstanceIndex and another to upload DrawID when needed,
we can only expose 28.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 31f1863ace)
2017-07-27 18:56:45 +01:00
Iago Toral Quiroga
bdbd8ab517 anv/cmd_buffer: fix off by one error in assertion
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit a848e693ef)
2017-07-27 18:56:44 +01:00
Kenneth Graunke
47bca2cfa7 i965: Fix = vs == in MCS aux usage assert.
Caught by Coverity (CID 1415680).

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 698636cc97)
Fixes: 0f9b609cf4 ("i965/blorp: Do prepare/finish manually")
2017-07-27 18:54:41 +01:00
Kenneth Graunke
04bb687f04 i965: Fix offset addition in get_isl_surf.
Increase the value, not the pointer to the stack variable.

Caught by Coverity (CID 1415574).  Not shipped in a real release.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit f6e674fa51)
Fixes: 63a43f4161 ("i965: Refactor miptree to isl converter and adjustment")
2017-07-27 18:54:13 +01:00
Eric Anholt
4e0f29ed0b broadcom/vc4: Prefer blit via rendering to the software fallback.
I don't know how I managed to leave this here for so long.  Found when
working on a 1:1 overlapping blit extension for X11.

Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 93fec49a75)
2017-07-27 18:21:27 +01:00
Lionel Landwerlin
0ccb853cc0 i965: perf: flush batchbuffers at the beginning of queries
As Chris commented, it makes more sense to have batch buffer flushes
before the query. Usually applications like frame_retrace do a series
of queries and in that case, with flushes at the end of the queries,
we might still have the first query contained in 2 different batchs.
More generally it would be quite usual to have the query contained in
2 batch buffers because we never now what's the fill rate of the
current batch buffer.

If we move the flushing at the beginning of the queries, it's pretty
much guaranteed that queries will be contained in a single batch
buffer (unless the amount of commands is huge, but then it's only fair
to include reloading request times in the measurements).

Fixes: adafe4b733 ("i965: perf: minimize the chances to spread queries across batchbuffers")
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.2 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 9f439ae120)
2017-07-27 18:21:22 +01:00
Emil Velikov
a455f594bb Update version to 17.2.0-rc1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-24 16:59:32 +01:00
Emil Velikov
a955622c1a intel/blorp: ship blorp_genX_exec.h within the tarball
Fixes: c9cb37b2a6 ("intel/blorp: Add a partial resolve pass for MCS")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 5d47dd9c2a)
2017-07-24 16:59:32 +01:00
1477 changed files with 37457 additions and 108898 deletions

View File

@@ -33,7 +33,3 @@ indent_size = 2
[*.patch]
trim_trailing_whitespace = false
[meson.build,meson_options.txt]
indent_style = space
indent_size = 2

2
.gitignore vendored
View File

@@ -7,13 +7,11 @@
*.log
*.o
*.obj
*.orig
*.os
*.pc
*.pdb
*.pyc
*.pyo
*.rej
*.so
*.so.*
*.sw[a-z]

View File

@@ -20,13 +20,13 @@ env:
- XCBPROTO_VERSION=xcb-proto-1.11
- LIBXCB_VERSION=libxcb-1.11
- LIBXSHMFENCE_VERSION=libxshmfence-1.2
- LIBTXC_DXTN_VERSION=libtxc_dxtn-1.0.1
- LIBVDPAU_VERSION=libvdpau-1.1
- LIBVA_VERSION=libva-1.6.2
- LIBWAYLAND_VERSION=wayland-1.11.1
- WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
- PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
- LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
- PATH="$HOME/prefix/bin:$PATH"
matrix:
include:
@@ -37,7 +37,7 @@ matrix:
- MAKE_CHECK_COMMAND="make check"
- DRI_LOADERS="--enable-glx --enable-gbm --enable-egl --with-platforms=x11,drm,surfaceless,wayland --enable-osmesa"
- DRI_DRIVERS="i915,i965,radeon,r200,swrast,nouveau"
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
- GALLIUM_DRIVERS=""
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--disable-libunwind"
@@ -62,11 +62,9 @@ matrix:
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC="gcc-4.8"
- OVERRIDE_CXX="g++-4.8"
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
- GALLIUM_DRIVERS="swr"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
@@ -75,7 +73,6 @@ matrix:
sources:
- llvm-toolchain-trusty-3.9
packages:
- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
@@ -94,11 +91,9 @@ matrix:
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=3.9
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
- GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
@@ -107,7 +102,6 @@ matrix:
sources:
- llvm-toolchain-trusty-3.9
packages:
- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
@@ -121,108 +115,35 @@ matrix:
- libunwind8-dev
- env:
# NOTE: Analogous to SWR above, building Clover is quite slow.
- LABEL="make Gallium ST Clover LLVM-3.9"
- LABEL="make Gallium ST Clover"
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=3.9
- LLVM_VERSION=3.6
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.7
- OVERRIDE_CXX=g++-4.7
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_DRIVERS="r600,radeonsi"
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
# i915 most likely doesn't work with OpenCL.
# Regardless - we're doing a quick build test here.
- GALLIUM_DRIVERS="i915"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-3.9
- llvm-toolchain-trusty-3.6
packages:
- binutils-2.26
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.7
# From sources above
- llvm-3.9-dev
- clang-3.9
- libclang-3.9-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- env:
# NOTE: Analogous to SWR above, building Clover is quite slow.
- LABEL="make Gallium ST Clover LLVM-4.0"
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.8
- OVERRIDE_CXX=g++-4.8
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_DRIVERS="r600,radeonsi"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-4.0
packages:
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.8
# From sources above
- llvm-4.0-dev
- clang-4.0
- libclang-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- env:
# NOTE: Analogous to SWR above, building Clover is quite slow.
- LABEL="make Gallium ST Clover LLVM-5.0"
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=5.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.8
- OVERRIDE_CXX=g++-4.8
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_DRIVERS="r600,radeonsi"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-5.0
packages:
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.8
# From sources above
- llvm-5.0-dev
- clang-5.0
- libclang-5.0-dev
- llvm-3.6-dev
- clang-3.6
- libclang-3.6-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
@@ -239,7 +160,7 @@ matrix:
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --enable-xa --enable-nine --enable-xvmc --enable-vdpau --enable-va --enable-omx-bellagio --enable-gallium-osmesa"
- GALLIUM_ST="--enable-dri --disable-opencl --enable-xa --enable-nine --enable-xvmc --enable-vdpau --enable-va --enable-omx --enable-gallium-osmesa"
# We need swrast for osmesa and nine.
# i915 most likely doesn't work with most ST.
# Regardless - we're doing a quick build test here.
@@ -273,11 +194,9 @@ matrix:
- MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel check"
- LLVM_VERSION=3.9
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl --with-platforms=x11,wayland"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx --disable-gallium-osmesa"
- GALLIUM_DRIVERS=""
- VULKAN_DRIVERS="intel,radeon"
- LIBUNWIND_FLAGS="--disable-libunwind"
@@ -286,7 +205,6 @@ matrix:
sources:
- llvm-toolchain-trusty-3.9
packages:
- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
@@ -364,48 +282,10 @@ matrix:
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- env:
- LABEL="meson Vulkan"
- BUILD=meson
- MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
addons:
apt:
sources:
- llvm-toolchain-trusty-3.9
packages:
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
- llvm-3.9-dev
# Common
- xz-utils
- libexpat1-dev
- libelf-dev
- python3-pip
- env:
- LABEL="meson loaders/classic DRI"
- BUILD=meson
- MESON_OPTIONS="-Dvulkan-drivers= -Dgallium-drivers="
addons:
apt:
packages:
- xz-utils
- x11proto-xf86vidmode-dev
- libexpat1-dev
- libx11-xcb-dev
- libxdamage-dev
- libxfixes-dev
- python3-pip
install:
- pip install --user mako
# Install the latest meson from pip, since the version in the ubuntu repos is
# often quite old.
- if test "x$BUILD" = xmeson; then
pip3 install --user meson;
fi
# Since libdrm gets updated in configure.ac regularly, try to pick up the
# latest version from there.
- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
@@ -451,6 +331,19 @@ install:
- tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
- (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make install)
# libtxc-dxtn uses the patented S3 Texture Compression
# algorithm. Therefore, we don't want to use this library but it is
# still possible through setting the USE_TXC_DXTN variable to yes in
# the travis web UI.
#
# According to Wikipedia, the patent expires on October 2, 2017:
# https://en.wikipedia.org/wiki/S3_Texture_Compression#Patent
- if test "x$USE_TXC_DXTN" = xyes; then
wget https://people.freedesktop.org/~cbrill/libtxc_dxtn/$LIBTXC_DXTN_VERSION.tar.bz2;
tar -jxvf $LIBTXC_DXTN_VERSION.tar.bz2;
(cd $LIBTXC_DXTN_VERSION && ./configure --prefix=$HOME/prefix && make install);
fi
- wget http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
- tar -jxvf $LIBVDPAU_VERSION.tar.bz2
- (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make install)
@@ -467,11 +360,6 @@ install:
- tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
- (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && make install)
# Meson requires ninja >= 1.6, but trusty has 1.3.x
- wget https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
- unzip ninja-linux.zip
- mv ninja $HOME/prefix/bin/
# Generate the header since one is missing on the Travis instance
- mkdir -p linux
- printf "%s\n" \
@@ -490,9 +378,7 @@ script:
- if test "x$BUILD" = xmake; then
test -n "$OVERRIDE_CC" && export CC="$OVERRIDE_CC";
test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
test -n "$OVERRIDE_PATH" && export PATH="$OVERRIDE_PATH:$PATH";
export CFLAGS="$CFLAGS -isystem`pwd`";
export CC="$CC -isystem`pwd`";
./autogen.sh --enable-debug
$LIBUNWIND_FLAGS
@@ -511,9 +397,3 @@ script:
test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
fi
- if test "x$BUILD" = xmeson; then
export CFLAGS="$CFLAGS -isystem`pwd`";
meson _build $MESON_OPTIONS;
ninja -C _build;
fi

View File

@@ -32,6 +32,7 @@ LOCAL_C_INCLUDES += \
MESA_VERSION := $(shell cat $(MESA_TOP)/VERSION)
LOCAL_CFLAGS += \
-Wno-unused-parameter \
-Wno-date-time \
-Wno-pointer-arith \
-Wno-missing-field-initializers \
-Wno-initializer-overrides \
@@ -63,7 +64,7 @@ LOCAL_CFLAGS += \
-DHAVE___BUILTIN_CLZLL \
-DHAVE___BUILTIN_UNREACHABLE \
-DHAVE_PTHREAD=1 \
-DHAVE_DLADDR \
-DHAVE_DLOPEN \
-DHAVE_DL_ITERATE_PHDR \
-DMAJOR_IN_SYSMACROS \
-fvisibility=hidden \
@@ -97,9 +98,8 @@ LOCAL_CFLAGS += -DHAVE_LIBDRM
LOCAL_SHARED_LIBRARIES += libdrm
endif
LOCAL_CFLAGS_32 += -DDEFAULT_DRIVER_DIR=\"/vendor/lib/$(MESA_DRI_MODULE_REL_PATH)\"
LOCAL_CFLAGS_64 += -DDEFAULT_DRIVER_DIR=\"/vendor/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
LOCAL_PROPRIETARY_MODULE := true
LOCAL_CFLAGS_32 += -DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
LOCAL_CFLAGS_64 += -DDEFAULT_DRIVER_DIR=\"/system/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
# uncomment to keep the debug symbols
#LOCAL_STRIP_MODULE := false

View File

@@ -75,10 +75,6 @@ $(foreach d, $(BOARD_GPU_DRIVERS), \
MESA_BUILD_CLASSIC := $(strip $(foreach d, $(BOARD_GPU_DRIVERS), $(patsubst $(d).%,%, $(filter $(d).%, $(classic_drivers)))))
MESA_BUILD_GALLIUM := $(strip $(foreach d, $(BOARD_GPU_DRIVERS), $(patsubst $(d).%,%, $(filter $(d).%, $(gallium_drivers)))))
endif
ifeq ($(filter x86%,$(TARGET_ARCH)),)
MESA_BUILD_CLASSIC :=
endif
$(foreach d, $(MESA_BUILD_CLASSIC) $(MESA_BUILD_GALLIUM), $(eval $(d) := true))
# host and target must be the same arch to generate matypes.h
@@ -99,9 +95,7 @@ define mesa-build-with-llvm
$(eval LOCAL_CFLAGS += -DHAVE_LLVM=0x0307 -DMESA_LLVM_VERSION_PATCH=0)) \
$(if $(filter 7,$(MESA_ANDROID_MAJOR_VERSION)), \
$(eval LOCAL_CFLAGS += -DHAVE_LLVM=0x0308 -DMESA_LLVM_VERSION_PATCH=0)) \
$(if $(filter 8,$(MESA_ANDROID_MAJOR_VERSION)), \
$(eval LOCAL_CFLAGS += -DHAVE_LLVM=0x0309 -DMESA_LLVM_VERSION_PATCH=0)) \
$(if $(filter P,$(MESA_ANDROID_MAJOR_VERSION)), \
$(if $(filter O,$(MESA_ANDROID_MAJOR_VERSION)), \
$(eval LOCAL_CFLAGS += -DHAVE_LLVM=0x0309 -DMESA_LLVM_VERSION_PATCH=0)) \
$(eval LOCAL_SHARED_LIBRARIES += libLLVM)
endef

View File

@@ -54,11 +54,9 @@ EXTRA_DIST = \
common.py \
docs \
doxygen \
bin/git_sha1_gen.py \
bin/git_sha1_gen.sh \
scons \
SConstruct \
build-support/conftest.dyn \
build-support/conftest.map
SConstruct
noinst_HEADERS = \
include/c99_alloca.h \

View File

@@ -103,12 +103,6 @@ F: CleanSpec.mk
F: */Android.*mk
F: */Makefile.sources
MESON BUILD
R: Dylan Baker <dylan@pnwbakers.com>
R: Eric Engestrom <eric@engestrom.ch>
F: */meson.build
F: meson_options.txt
ANDROID EGL SUPPORT
R: Rob Herring <robh@kernel.org>
R: Tomasz Figa <tfiga@chromium.org>

View File

@@ -152,7 +152,8 @@ try:
except ImportError:
pass
else:
aliases = sorted(default_ans.keys())
aliases = default_ans.keys()
aliases.sort()
env.Help('\n')
env.Help('Recognized targets:\n')
for alias in aliases:

View File

@@ -1 +1 @@
17.3.0-rc6
17.2.5

86
bin/.cherry-ignore Normal file
View File

@@ -0,0 +1,86 @@
# fixes: The commits are too invasive for stable. Instead the offending patches
# causing regressions have been reverted.
365d34540f331df57780dddf8da87235be0a6bcb mesa: correctly calculate the storage offset for i915
de0e62e1065e2d9172acf3ab7c70bba0160125c8 st/mesa: correctly calculate the storage offset
# stable: Add loader::getCapability patches. It's rather invasive infra
# not suitable as a bugfix.
1bf703e4ea5c4f742bc7ba55d01e5afc3f4e11f9 dri_interface,egl,gallium: only expose RGBA visuals on Android
be5773fa8dfe9255d9abaf5c7d5bbbd2d922da08 Android: fix compile error for DRI2 loader getCapability
31a6750988d7dd431f72ff1ff11bfca83bde5d8c st/dri: NULL check before deref DRI loader .getCapability
# stable: The commit addresses code that did not land in the stable branch
31bb8517a194af733deefe2d821537d994d39365 radv/gfx9: fix tile swizzle handling for gfx9
# stable: Commit is not applicable when 4fab67a4415 is missing.
d496780fb2c7f2cf0e32b6a79dc528e5156dfcb3 intel/eu/validate: Look up types on demand in execution_type()
# fixes: Depend on preseding commit which adds new public GBM API
3a5e3aa5a53cff55a5e31766d713a41ffa5a93d7 egl/drm: Fix misused x and y offsets in swrast_put_image2()
fe2a6281b3b299998fe7399e7dbcc2077d773824 egl/drm: Fix misused x and y offsets in swrast_get_image()
# fixes: This commit addressed an earlier commit c7e9ebb3ab8 which did not
# land in branch
45c5c444518b7e83d9accd9f44702fa49282a3b8 radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug
# fixes: This commit addressed earlier commits 61ad2f13 and 6dcc54b4 which did
# not land in branch
979978ee06867a531b8d56cee252f5c83920a339 radv: Check for GFX9 for 1D arrays in image_size intrinsic.
# fixes: This commit addressed earlier commits dcf46e99 and 60878dd0 which did
# not land in branch
8e9e339c530c7b82b5a29d4b3183e8f5a01eae28 radv: copy the number of viewports/scissors at pipeline bind time
# stable: The commit regresses a few dEQP tests. Namely:
# dEQP-VK.api.copy_and_blit.core.buffer_to_buffer.partial
# dEQP-VK.api.copy_and_blit.dedicated_allocation.buffer_to_buffer.partial
14555d0b7a51bd3701764fd213c2459410143431 anv: Remove unreachable cases from isl_format_for_size()
# stable: The commit addresses earlier commit a62a9793357 which is no applicable
# for the stable branch
6c7720ed78db754d52f204cbb74897aa9e65ea7e anv/wsi: Allocate enough memory for the entire image
# stable: Commits are too invasive for 17.2.
98fdff7247b6877d028d33284f9cc63189ee204e configure.ac: factor out detection for old and buggy llvm
13a53c4f5cdd664fd155c9e78fb46a4387af006c configure.ac: rework llvm libs handling for 3.9+
a7ecf7b86f4eae59f3ceac2125e5d1725c403c07 Travis: add binutils 2.26 for a few more LLVM 3.9 builds
36d6d1e931936a80da327889862ba02942ac427b configure.ac: add llvm_add_optional_component helper
df3a43018020c16c1dfa88a76c9a84c9fb85be38 configure.ac: add missing LLVM components for OpenCL
# stable: Commit is too big for stable at this point.
4d24a7cb97641cacecd371d1968f6964785822e4 glsl: fix derived cs variables
# stable: 17.3 nomination only.
fee9d05e2136b2b7c5a1ad2be7180b99f733f539 radv: Update code pointer correctly if a variant is already created
# stable: 17.3 nomination only.
d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation like radeonsi.
# fixes: This commit addressed earlier commit 35ac13ed3 which did not
# land in branch.
11d688d9f0d2ee4d0178d1807c0075e5e8364b1d mesa/bufferobj: don't double negate the range
# extra: Commit is not applicable when ade416d0236 is missing.
07bfdb478bf844a0ac9cf3679f51f83c4abea5a1 broadcom/vc5: Propagate vc4 aliasing fix to vc5.
# stable: This commit addressed earlier commit 8d90e28839 which did
# not land in branch.
446c5726ecb968d06a6607e0df42be1cb74948c4 i965: fix blorp stage_prog_data->param leak
# stable: This commit addressed earlier commit 78ade659569 which did
# not land in branch.
8fbd82f464f26a56167f7962174b2b69756a105a etnaviv: don't do resolve-in-place without valid TS
# stable: This commit addressed earlier commit 8d90e28839 which did
# not land in branch.
7b4387519c382cffef9c62bbbbefcfe71cfde905 intel/fs: Alloc pull constants off mem_ctx
# stable: 17.3 nomination only.
3f8e3c2bd8f54ae6817f7496be47f4e1a8860d9c radeonsi: add a workaround for weird s_buffer_load_dword behavior on SI
# stable: 17.3 nomination only.
7dae419aa7c34af820c08896acef3b65d855188e Android: move drivers' symlinks to /vendor (v2)
# fixes: This commit has more than one Fixes tag but the commit it
# addresses didn't land in branch.
e17e8934f9e4b008bdfb4f9abd8ed4faa604c7d9 automake: include git_sha1.h.in in release tarball

View File

@@ -1,36 +0,0 @@
#!/usr/bin/env python
"""
Generate the contents of the git_sha1.h file.
The output of this script goes to stdout.
"""
import os
import os.path
import subprocess
import sys
def get_git_sha1():
"""Try to get the git SHA1 with git rev-parse."""
git_dir = os.path.join(os.path.dirname(sys.argv[0]), '..', '.git')
try:
git_sha1 = subprocess.check_output([
'git',
'--git-dir=' + git_dir,
'rev-parse',
'HEAD',
], stderr=open(os.devnull, 'w')).decode("ascii")
except:
# don't print anything if it fails
git_sha1 = ''
return git_sha1
git_sha1 = os.environ.get('MESA_GIT_SHA1_OVERRIDE', get_git_sha1())[:10]
if git_sha1:
git_sha1_h_in_path = os.path.join(os.path.dirname(sys.argv[0]),
'..', 'src', 'git_sha1.h.in')
with open(git_sha1_h_in_path , 'r') as git_sha1_h_in:
sys.stdout.write(git_sha1_h_in.read().replace('@VCS_TAG@', git_sha1))

12
bin/git_sha1_gen.sh Executable file
View File

@@ -0,0 +1,12 @@
#!/bin/sh
# run git from the sources directory
cd "$(dirname "$0")"
# don't print anything if git fails
if ! git_sha1=$(git --git-dir=../.git rev-parse --short=10 HEAD 2>/dev/null)
then
exit
fi
printf '#define MESA_GIT_SHA1 "git-%s"\n' "$git_sha1"

View File

@@ -1,55 +0,0 @@
#!/usr/bin/env python
# encoding=utf-8
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
"""Script to install megadriver symlinks for meson."""
from __future__ import print_function
import argparse
import os
import shutil
def main():
parser = argparse.ArgumentParser()
parser.add_argument('megadriver')
parser.add_argument('libdir')
parser.add_argument('drivers', nargs='+')
args = parser.parse_args()
to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), args.libdir)
master = os.path.join(to, os.path.basename(args.megadriver))
if not os.path.exists(to):
os.makedirs(to)
shutil.copy(args.megadriver, master)
for each in args.drivers:
driver = os.path.join(to, each)
if os.path.exists(driver):
os.unlink(driver)
print('installing {} to {}'.format(args.megadriver, to))
os.link(master, driver)
os.unlink(master)
if __name__ == '__main__':
main()

View File

@@ -1,3 +0,0 @@
{
radeon_drm_winsys_create;
};

View File

@@ -1,6 +0,0 @@
VERSION_1 {
global:
main;
local:
*;
};

View File

@@ -74,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
# in the first entry.
LIBDRM_REQUIRED=2.4.75
LIBDRM_RADEON_REQUIRED=2.4.71
LIBDRM_AMDGPU_REQUIRED=2.4.85
LIBDRM_AMDGPU_REQUIRED=2.4.82
LIBDRM_INTEL_REQUIRED=2.4.75
LIBDRM_NVVIEUX_REQUIRED=2.4.66
LIBDRM_NOUVEAU_REQUIRED=2.4.66
@@ -101,7 +101,7 @@ ZLIB_REQUIRED=1.2.3
dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_OPENCL=3.6.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=3.9.0
LLVM_REQUIRED_RADV=3.9.0
@@ -282,50 +282,85 @@ esac
AM_CONDITIONAL(HAVE_ANDROID, test "x$android" = xyes)
dnl
dnl Check compiler flags
dnl
AX_CHECK_COMPILE_FLAG([-Wall], [CFLAGS="$CFLAGS -Wall"])
AX_CHECK_COMPILE_FLAG([-Werror=implicit-function-declaration], [CFLAGS="$CFLAGS -Werror=implicit-function-declaration"])
AX_CHECK_COMPILE_FLAG([-Werror=missing-prototypes], [CFLAGS="$CFLAGS -Werror=missing-prototypes"])
AX_CHECK_COMPILE_FLAG([-Wmissing-prototypes], [CFLAGS="$CFLAGS -Wmissing-prototypes"])
AX_CHECK_COMPILE_FLAG([-fno-math-errno], [CFLAGS="$CFLAGS -fno-math-errno"])
AX_CHECK_COMPILE_FLAG([-fno-trapping-math], [CFLAGS="$CFLAGS -fno-trapping-math"])
AX_CHECK_COMPILE_FLAG([-fvisibility=hidden], [VISIBILITY_CFLAGS="-fvisibility=hidden"])
dnl
dnl Check C++ compiler flags
dnl
AC_LANG_PUSH([C++])
AX_CHECK_COMPILE_FLAG([-Wall], [CXXFLAGS="$CXXFLAGS -Wall"])
AX_CHECK_COMPILE_FLAG([-fno-math-errno], [CXXFLAGS="$CXXFLAGS -fno-math-errno"])
AX_CHECK_COMPILE_FLAG([-fno-trapping-math], [CXXFLAGS="$CXXFLAGS -fno-trapping-math"])
AX_CHECK_COMPILE_FLAG([-fvisibility=hidden], [VISIBILITY_CXXFLAGS="-fvisibility=hidden"])
AC_LANG_POP([C++])
# Flags to help ensure that certain portions of the code -- and only those
# portions -- can be built with MSVC:
# - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe, and
# - non-Linux/Posix OpenGL portions needs to build on MSVC 2013 (which
# supports most of C99)
# - the rest has no compiler compiler restrictions
AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith], [MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith"])
AX_CHECK_COMPILE_FLAG([-Werror=vla], [MSVC2013_COMPAT_CFLAGS="-Werror=vla"])
AC_LANG_PUSH([C++])
AX_CHECK_COMPILE_FLAG([-Werror=pointer-arith], [MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith"])
AX_CHECK_COMPILE_FLAG([-Werror=vla], [MSVC2013_COMPAT_CXXFLAGS="-Werror=vla"])
AC_LANG_POP([C++])
AC_SUBST([MSVC2013_COMPAT_CFLAGS])
AC_SUBST([MSVC2013_COMPAT_CXXFLAGS])
dnl Add flags for gcc and g++
if test "x$GCC" = xyes; then
CFLAGS="$CFLAGS -Wall"
if test "x$USE_GNU99" = xyes; then
CFLAGS="$CFLAGS -std=gnu99"
else
CFLAGS="$CFLAGS -std=c99"
fi
# Enable -Werror=implicit-function-declaration and
# -Werror=missing-prototypes, if available, or otherwise, just
# -Wmissing-prototypes. This is particularly useful to avoid
# generating a loadable driver module that has undefined symbols.
save_CFLAGS="$CFLAGS"
AC_MSG_CHECKING([whether $CC supports -Werror=missing-prototypes])
CFLAGS="$CFLAGS -Werror=implicit-function-declaration"
CFLAGS="$CFLAGS -Werror=missing-prototypes"
AC_LINK_IFELSE([AC_LANG_PROGRAM()],
AC_MSG_RESULT([yes]),
[CFLAGS="$save_CFLAGS -Wmissing-prototypes";
AC_MSG_RESULT([no])])
# Enable -fvisibility=hidden if using a gcc that supports it
save_CFLAGS="$CFLAGS"
AC_MSG_CHECKING([whether $CC supports -fvisibility=hidden])
VISIBILITY_CFLAGS="-fvisibility=hidden"
CFLAGS="$CFLAGS $VISIBILITY_CFLAGS"
AC_LINK_IFELSE([AC_LANG_PROGRAM()], AC_MSG_RESULT([yes]),
[VISIBILITY_CFLAGS=""; AC_MSG_RESULT([no])])
# Restore CFLAGS; VISIBILITY_CFLAGS are added to it where needed.
CFLAGS=$save_CFLAGS
# We don't want floating-point math functions to set errno or trap
CFLAGS="$CFLAGS -fno-math-errno -fno-trapping-math"
# Flags to help ensure that certain portions of the code -- and only those
# portions -- can be built with MSVC:
# - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe, and
# - non-Linux/Posix OpenGL portions needs to build on MSVC 2013 (which
# supports most of C99)
# - the rest has no compiler compiler restrictions
MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith"
MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith"
# Enable -Werror=vla if compiler supports it
save_CFLAGS="$CFLAGS"
AC_MSG_CHECKING([whether $CC supports -Werror=vla])
CFLAGS="$CFLAGS -Werror=vla"
AC_LINK_IFELSE([AC_LANG_PROGRAM()],
[MSVC2013_COMPAT_CFLAGS="$MSVC2013_COMPAT_CFLAGS -Werror=vla";
MSVC2013_COMPAT_CXXFLAGS="$MSVC2013_COMPAT_CXXFLAGS -Werror=vla";
AC_MSG_RESULT([yes])],
AC_MSG_RESULT([no]))
CFLAGS="$save_CFLAGS"
fi
if test "x$GXX" = xyes; then
CXXFLAGS="$CXXFLAGS -Wall"
# Enable -fvisibility=hidden if using a gcc that supports it
save_CXXFLAGS="$CXXFLAGS"
AC_MSG_CHECKING([whether $CXX supports -fvisibility=hidden])
VISIBILITY_CXXFLAGS="-fvisibility=hidden"
CXXFLAGS="$CXXFLAGS $VISIBILITY_CXXFLAGS"
AC_LANG_PUSH([C++])
AC_LINK_IFELSE([AC_LANG_PROGRAM()], AC_MSG_RESULT([yes]),
[VISIBILITY_CXXFLAGS="" ; AC_MSG_RESULT([no])])
AC_LANG_POP([C++])
# Restore CXXFLAGS; VISIBILITY_CXXFLAGS are added to it where needed.
CXXFLAGS=$save_CXXFLAGS
# We don't want floating-point math functions to set errno or trap
CXXFLAGS="$CXXFLAGS -fno-math-errno -fno-trapping-math"
fi
AC_SUBST([MSVC2013_COMPAT_CFLAGS])
AC_SUBST([MSVC2013_COMPAT_CXXFLAGS])
dnl even if the compiler appears to support it, using visibility attributes isn't
dnl going to do anything useful currently on cygwin apart from emit lots of warnings
@@ -339,10 +374,6 @@ esac
AC_SUBST([VISIBILITY_CFLAGS])
AC_SUBST([VISIBILITY_CXXFLAGS])
AX_CHECK_COMPILE_FLAG([-Wno-override-init], [WNO_OVERRIDE_INIT="-Wno-override-init"]) # gcc
AX_CHECK_COMPILE_FLAG([-Wno-initializer-overrides], [WNO_OVERRIDE_INIT="-Wno-initializer-overrides"]) # clang
AC_SUBST([WNO_OVERRIDE_INIT])
dnl
dnl Optional flags, check for compiler support
dnl
@@ -606,7 +637,16 @@ dnl Check if linker supports version scripts
dnl
AC_MSG_CHECKING([if the linker supports version-scripts])
save_LDFLAGS=$LDFLAGS
LDFLAGS="$LDFLAGS -Wl,--version-script=$srcdir/build-support/conftest.map"
LDFLAGS="$LDFLAGS -Wl,--version-script=conftest.map"
cat > conftest.map <<EOF
VERSION_1 {
global:
main;
local:
*;
};
EOF
AC_LINK_IFELSE(
[AC_LANG_SOURCE([int main() { return 0;}])],
[have_ld_version_script=yes;AC_MSG_RESULT(yes)],
@@ -619,7 +659,12 @@ dnl Check if linker supports dynamic list files
dnl
AC_MSG_CHECKING([if the linker supports --dynamic-list])
save_LDFLAGS=$LDFLAGS
LDFLAGS="$LDFLAGS -Wl,--dynamic-list=$srcdir/build-support/conftest.dyn"
LDFLAGS="$LDFLAGS -Wl,--dynamic-list=conftest.dyn"
cat > conftest.dyn <<EOF
{
radeon_drm_winsys_create;
};
EOF
AC_LINK_IFELSE(
[AC_LANG_SOURCE([int main() { return 0;}])],
[have_ld_dynamic_list=yes;AC_MSG_RESULT(yes)],
@@ -793,7 +838,6 @@ AC_CHECK_HEADER([xlocale.h], [DEFINES="$DEFINES -DHAVE_XLOCALE_H"])
AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES -DHAVE_SYS_SYSCTL_H"])
AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])
AC_CHECK_FUNC([memfd_create], [DEFINES="$DEFINES -DHAVE_MEMFD_CREATE"])
AC_MSG_CHECKING([whether strtod has locale support])
AC_LINK_IFELSE([AC_LANG_SOURCE([[
@@ -818,9 +862,9 @@ AC_LINK_IFELSE([AC_LANG_SOURCE([[
dnl Check to see if dlopen is in default libraries (like Solaris, which
dnl has it in libc), or if libdl is needed to get it.
AC_CHECK_FUNC([dlopen], [],
AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
[AC_CHECK_LIB([dl], [dlopen],
[DLOPEN_LIBS="-ldl"])])
[DEFINES="$DEFINES -DHAVE_DLOPEN"; DLOPEN_LIBS="-ldl"])])
AC_SUBST([DLOPEN_LIBS])
dnl Check if that library also has dladdr
@@ -942,15 +986,6 @@ llvm_add_component() {
fi
}
llvm_add_optional_component() {
new_llvm_component=$1
driver_name=$2
if $LLVM_CONFIG --components | grep -iqw $new_llvm_component ; then
LLVM_COMPONENTS="${LLVM_COMPONENTS} ${new_llvm_component}"
fi
}
llvm_add_default_components() {
driver_name=$1
@@ -961,7 +996,9 @@ llvm_add_default_components() {
llvm_add_component "mcjit" $driver_name
# Optional default components
llvm_add_optional_component "inteljitevents" $driver_name
if $LLVM_CONFIG --components | grep -iqw inteljitevents ; then
LLVM_COMPONENTS="$LLVM_COMPONENTS inteljitevents"
fi
}
llvm_add_target() {
@@ -1235,14 +1272,9 @@ AC_ARG_ENABLE([vdpau],
[enable_vdpau=auto])
AC_ARG_ENABLE([omx],
[AS_HELP_STRING([--enable-omx],
[DEPRECATED: Use --enable-omx-bellagio instead @<:@default=auto@:>@])],
[AC_MSG_ERROR([--enable-omx is deprecated. Use --enable-omx-bellagio instead.])],
[])
AC_ARG_ENABLE([omx-bellagio],
[AS_HELP_STRING([--enable-omx-bellagio],
[enable OpenMAX Bellagio library @<:@default=disabled@:>@])],
[enable_omx_bellagio="$enableval"],
[enable_omx_bellagio=no])
[enable OpenMAX library @<:@default=disabled@:>@])],
[enable_omx="$enableval"],
[enable_omx=no])
AC_ARG_ENABLE([va],
[AS_HELP_STRING([--enable-va],
[enable va library @<:@default=auto@:>@])],
@@ -1274,7 +1306,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast"
AC_ARG_WITH([gallium-drivers],
[AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@],
[comma delimited Gallium drivers list, e.g.
"i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,vc4,vc5,virgl,etnaviv,imx"
"i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,vc4,virgl,etnaviv,imx"
@<:@default=r300,r600,svga,swrast@:>@])],
[with_gallium_drivers="$withval"],
[with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"])
@@ -1293,7 +1325,7 @@ if test "x$enable_opengl" = xno -a \
"x$enable_xa" = xno -a \
"x$enable_xvmc" = xno -a \
"x$enable_vdpau" = xno -a \
"x$enable_omx_bellagio" = xno -a \
"x$enable_omx" = xno -a \
"x$enable_va" = xno -a \
"x$enable_opencl" = xno; then
AC_MSG_ERROR([at least one API should be enabled])
@@ -1384,10 +1416,18 @@ AC_ARG_ENABLE([libglvnd],
AM_CONDITIONAL(USE_LIBGLVND, test "x$enable_libglvnd" = xyes)
if test "x$enable_libglvnd" = xyes ; then
dnl XXX: update once we can handle more than libGL/glx.
dnl Namely: we should error out if neither of the glvnd enabled libraries
dnl are built
case "x$enable_glx" in
xno)
AC_MSG_ERROR([cannot build libglvnd without GLX])
;;
xxlib | xgallium-xlib )
AC_MSG_ERROR([cannot build libgvnd when Xlib-GLX or Gallium-Xlib-GLX is enabled])
;;
xdri)
;;
esac
PKG_CHECK_MODULES([GLVND], libglvnd >= 0.2.0)
@@ -1396,10 +1436,6 @@ if test "x$enable_libglvnd" = xyes ; then
DEFINES="${DEFINES} -DUSE_LIBGLVND=1"
DEFAULT_GL_LIB_NAME=GLX_mesa
if test "x$enable_glx" = xno -a "x$enable_egl" = xno; then
AC_MSG_ERROR([cannot build libglvnd without GLX or EGL])
fi
fi
AC_ARG_WITH([gl-lib-name],
@@ -1713,8 +1749,7 @@ for plat in $platforms; do
case "$plat" in
wayland)
PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >= $WAYLAND_REQUIRED])
PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >= $WAYLAND_REQUIRED])
PKG_CHECK_MODULES([WAYLAND], [wayland-client >= $WAYLAND_REQUIRED wayland-server >= $WAYLAND_REQUIRED])
if test "x$WAYLAND_SCANNER" = "x:"; then
AC_MSG_ERROR([wayland-scanner is needed to compile the wayland platform])
@@ -1722,7 +1757,7 @@ for plat in $platforms; do
if test "x$have_wayland_protocols" = xno; then
AC_MSG_ERROR([wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED is needed to compile the wayland platform])
fi
DEFINES="$DEFINES -DHAVE_WAYLAND_PLATFORM -DWL_HIDE_DEPRECATED"
DEFINES="$DEFINES -DHAVE_WAYLAND_PLATFORM"
;;
x11)
@@ -1812,11 +1847,6 @@ if test "x$with_dri_drivers" = xno; then
with_dri_drivers=''
fi
# Check for expat
PKG_CHECK_MODULES([EXPAT], [expat],,
[PKG_CHECK_MODULES([EXPAT], [expat21])]
)
dnl If $with_dri_drivers is yes, drivers will be added through
dnl platform checks. Set DEFINES and LIB_DEPS
if test "x$enable_dri" = xyes; then
@@ -1850,6 +1880,15 @@ if test "x$enable_dri" = xyes; then
with_dri_drivers="i915 i965 nouveau r200 radeon swrast"
fi
# Check for expat
PKG_CHECK_MODULES([EXPAT], [expat], [],
# expat version 2.0 and earlier do not provide expat.pc
[AC_CHECK_HEADER([expat.h],[],
[AC_MSG_ERROR([Expat headers required for DRI not found])])
AC_CHECK_LIB([expat],[XML_ParserCreate],[],
[AC_MSG_ERROR([Expat library required for DRI not found])])
EXPAT_LIBS="-lexpat"])
# put all the necessary libs together
DRI_LIB_DEPS="$DRI_LIB_DEPS $SELINUX_LIBS $LIBDRM_LIBS $EXPAT_LIBS -lm $PTHREAD_LIBS $DLOPEN_LIBS"
fi
@@ -2135,8 +2174,8 @@ if test -n "$with_gallium_drivers" -a "x$with_gallium_drivers" != xswrast; then
PKG_CHECK_EXISTS([vdpau >= $VDPAU_REQUIRED], [enable_vdpau=yes], [enable_vdpau=no])
fi
if test "x$enable_omx_bellagio" = xauto -a "x$have_omx_platform" = xyes; then
PKG_CHECK_EXISTS([libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED], [enable_omx_bellagio=yes], [enable_omx_bellagio=no])
if test "x$enable_omx" = xauto -a "x$have_omx_platform" = xyes; then
PKG_CHECK_EXISTS([libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED], [enable_omx=yes], [enable_omx=no])
fi
if test "x$enable_va" = xauto -a "x$have_va_platform" = xyes; then
@@ -2147,7 +2186,7 @@ fi
if test "x$enable_dri" = xyes -o \
"x$enable_xvmc" = xyes -o \
"x$enable_vdpau" = xyes -o \
"x$enable_omx_bellagio" = xyes -o \
"x$enable_omx" = xyes -o \
"x$enable_va" = xyes; then
need_gallium_vl=yes
fi
@@ -2155,11 +2194,9 @@ AM_CONDITIONAL(NEED_GALLIUM_VL, test "x$need_gallium_vl" = xyes)
if test "x$enable_xvmc" = xyes -o \
"x$enable_vdpau" = xyes -o \
"x$enable_omx_bellagio" = xyes -o \
"x$enable_omx" = xyes -o \
"x$enable_va" = xyes; then
if echo $platforms | grep -q "x11"; then
PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED])
fi
PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED])
need_gallium_vl_winsys=yes
fi
AM_CONDITIONAL(NEED_GALLIUM_VL_WINSYS, test "x$need_gallium_vl_winsys" = xyes)
@@ -2183,14 +2220,14 @@ if test "x$enable_vdpau" = xyes; then
fi
AM_CONDITIONAL(HAVE_ST_VDPAU, test "x$enable_vdpau" = xyes)
if test "x$enable_omx_bellagio" = xyes; then
if test "x$enable_omx" = xyes; then
if test "x$have_omx_platform" != xyes; then
AC_MSG_ERROR([OMX requires at least one of the x11 or drm platforms])
fi
PKG_CHECK_MODULES([OMX_BELLAGIO], [libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED])
gallium_st="$gallium_st omx_bellagio"
PKG_CHECK_MODULES([OMX], [libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED])
gallium_st="$gallium_st omx"
fi
AM_CONDITIONAL(HAVE_ST_OMX_BELLAGIO, test "x$enable_omx_bellagio" = xyes)
AM_CONDITIONAL(HAVE_ST_OMX, test "x$enable_omx" = xyes)
if test "x$enable_va" = xyes; then
if test "x$have_va_platform" != xyes; then
@@ -2286,16 +2323,13 @@ if test "x$enable_opencl" = xyes; then
llvm_add_default_components "opencl"
llvm_add_component "all-targets" "opencl"
llvm_add_component "coverage" "opencl"
llvm_add_component "linker" "opencl"
llvm_add_component "instrumentation" "opencl"
llvm_add_component "ipo" "opencl"
llvm_add_component "irreader" "opencl"
llvm_add_component "lto" "opencl"
llvm_add_component "option" "opencl"
llvm_add_component "objcarcopts" "opencl"
llvm_add_component "profiledata" "opencl"
llvm_add_optional_component "coroutines" "opencl"
dnl Check for Clang internal headers
if test -z "$CLANG_LIBDIR"; then
@@ -2355,15 +2389,15 @@ AC_ARG_WITH([vdpau-libdir],
[VDPAU_LIB_INSTALL_DIR='${libdir}/vdpau'])
AC_SUBST([VDPAU_LIB_INSTALL_DIR])
dnl Directory for OMX_BELLAGIO libs
dnl Directory for OMX libs
AC_ARG_WITH([omx-bellagio-libdir],
[AS_HELP_STRING([--with-omx-bellagio-libdir=DIR],
[directory for the OMX_BELLAGIO libraries])],
[OMX_BELLAGIO_LIB_INSTALL_DIR="$withval"],
[OMX_BELLAGIO_LIB_INSTALL_DIR=`$PKG_CONFIG --exists libomxil-bellagio && \
$PKG_CONFIG --define-variable=libdir=\$libdir --variable=pluginsdir libomxil-bellagio`])
AC_SUBST([OMX_BELLAGIO_LIB_INSTALL_DIR])
AC_ARG_WITH([omx-libdir],
[AS_HELP_STRING([--with-omx-libdir=DIR],
[directory for the OMX libraries])],
[OMX_LIB_INSTALL_DIR="$withval"],
[OMX_LIB_INSTALL_DIR=`$PKG_CONFIG --exists libomxil-bellagio && \
$PKG_CONFIG --define-variable=libdir=\$libdir --variable=pluginsdir libomxil-bellagio`])
AC_SUBST([OMX_LIB_INSTALL_DIR])
dnl Directory for VA libs
@@ -2533,7 +2567,7 @@ if test -n "$with_gallium_drivers"; then
AC_SUBST([SWR_CXX11_CXXFLAGS])
swr_require_cxx_feature_flags "AVX" "defined(__AVX__)" \
",-target-cpu=sandybridge,-mavx,-march=core-avx,-tp=sandybridge" \
",-mavx,-march=core-avx" \
SWR_AVX_CXXFLAGS
AC_SUBST([SWR_AVX_CXXFLAGS])
@@ -2545,21 +2579,21 @@ if test -n "$with_gallium_drivers"; then
;;
xavx2)
swr_require_cxx_feature_flags "AVX2" "defined(__AVX2__)" \
",-target-cpu=haswell,-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2,-tp=haswell" \
",-mavx2 -mfma -mbmi2 -mf16c,-march=core-avx2" \
SWR_AVX2_CXXFLAGS
AC_SUBST([SWR_AVX2_CXXFLAGS])
HAVE_SWR_AVX2=yes
;;
xknl)
swr_require_cxx_feature_flags "KNL" "defined(__AVX512F__) && defined(__AVX512ER__)" \
",-target-cpu=mic-knl,-march=knl,-xMIC-AVX512" \
",-march=knl,-xMIC-AVX512" \
SWR_KNL_CXXFLAGS
AC_SUBST([SWR_KNL_CXXFLAGS])
HAVE_SWR_KNL=yes
;;
xskx)
swr_require_cxx_feature_flags "SKX" "defined(__AVX512F__) && defined(__AVX512BW__)" \
",-target-cpu=x86-skylake,-march=skylake-avx512,-xCORE-AVX512" \
",-march=skylake-avx512,-xCORE-AVX512" \
SWR_SKX_CXXFLAGS
AC_SUBST([SWR_SKX_CXXFLAGS])
HAVE_SWR_SKX=yes
@@ -2588,14 +2622,6 @@ if test -n "$with_gallium_drivers"; then
DEFINES="$DEFINES -DUSE_VC4_SIMULATOR"],
[USE_VC4_SIMULATOR=no])
;;
xvc5)
HAVE_GALLIUM_VC5=yes
PKG_CHECK_MODULES([VC5_SIMULATOR], [v3dv3],
[USE_VC5_SIMULATOR=yes;
DEFINES="$DEFINES -DUSE_VC5_SIMULATOR"],
[AC_MSG_ERROR([vc5 requires the simulator])])
;;
xpl111)
HAVE_GALLIUM_PL111=yes
;;
@@ -2637,39 +2663,6 @@ if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_PL111" = xyes ; then
AC_MSG_ERROR([Building with pl111 requires vc4])
fi
detect_old_buggy_llvm() {
dnl llvm-config may not give the right answer when llvm is a built as a
dnl single shared library, so we must work the library name out for
dnl ourselves.
dnl (See https://llvm.org/bugs/show_bug.cgi?id=6823)
dnl We can't use $LLVM_VERSION because it has 'svn' stripped out,
LLVM_SO_NAME=LLVM-`$LLVM_CONFIG --version`
AS_IF([test -f "$LLVM_LIBDIR/lib$LLVM_SO_NAME.$IMP_LIB_EXT"], [llvm_have_one_so=yes])
if test "x$llvm_have_one_so" = xyes; then
dnl LLVM was built using auto*, so there is only one shared object.
LLVM_LIBS="-l$LLVM_SO_NAME"
else
dnl If LLVM was built with CMake, there will be one shared object per
dnl component.
AS_IF([test ! -f "$LLVM_LIBDIR/libLLVMTarget.$IMP_LIB_EXT"],
[AC_MSG_ERROR([Could not find llvm shared libraries:
Please make sure you have built llvm with the --enable-shared option
and that your llvm libraries are installed in $LLVM_LIBDIR
If you have installed your llvm libraries to a different directory you
can use the --with-llvm-prefix= configure flag to specify this directory.
NOTE: Mesa is attempting to use llvm shared libraries by default.
If you do not want to build with llvm shared libraries and instead want to
use llvm static libraries then add --disable-llvm-shared-libs to your configure
invocation and rebuild.])])
dnl We don't need to update LLVM_LIBS in this case because the LLVM
dnl install uses a shared object for each component and we have
dnl already added all of these objects to LLVM_LIBS.
fi
}
dnl
dnl Set defines and buildtime variables only when using LLVM.
dnl
@@ -2687,28 +2680,47 @@ if test "x$enable_llvm" = xyes; then
dnl this was causing the same libraries to be appear multiple times
dnl in LLVM_LIBS.
if test $LLVM_VERSION_MAJOR -ge 4 -o $LLVM_VERSION_MAJOR -eq 3 -a $LLVM_VERSION_MINOR -ge 9; then
if test "x$enable_llvm_shared_libs" = xyes; then
LLVM_LIBS="`$LLVM_CONFIG --link-shared --libs ${LLVM_COMPONENTS}`"
if ! $LLVM_CONFIG --libs ${LLVM_COMPONENTS} >/dev/null; then
AC_MSG_ERROR([Calling ${LLVM_CONFIG} failed])
fi
LLVM_LIBS="`$LLVM_CONFIG --libs ${LLVM_COMPONENTS}`"
dnl llvm-config may not give the right answer when llvm is a built as a
dnl single shared library, so we must work the library name out for
dnl ourselves.
dnl (See https://llvm.org/bugs/show_bug.cgi?id=6823)
if test "x$enable_llvm_shared_libs" = xyes; then
dnl We can't use $LLVM_VERSION because it has 'svn' stripped out,
LLVM_SO_NAME=LLVM-`$LLVM_CONFIG --version`
AS_IF([test -f "$LLVM_LIBDIR/lib$LLVM_SO_NAME.$IMP_LIB_EXT"], [llvm_have_one_so=yes])
if test "x$llvm_have_one_so" = xyes; then
dnl LLVM was built using auto*, so there is only one shared object.
LLVM_LIBS="-l$LLVM_SO_NAME"
else
dnl Invoking llvm-config with both -libs and --system-libs produces the
dnl two separate lines - each for the set of libraries.
dnl Call the program twice, effectively folding them into a single line.
LLVM_LIBS="`$LLVM_CONFIG --link-static --libs ${LLVM_COMPONENTS}`"
dnl We need to link to llvm system libs when using static libs
LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --link-static --system-libs`"
dnl If LLVM was built with CMake, there will be one shared object per
dnl component.
AS_IF([test ! -f "$LLVM_LIBDIR/libLLVMTarget.$IMP_LIB_EXT"],
[AC_MSG_ERROR([Could not find llvm shared libraries:
Please make sure you have built llvm with the --enable-shared option
and that your llvm libraries are installed in $LLVM_LIBDIR
If you have installed your llvm libraries to a different directory you
can use the --with-llvm-prefix= configure flag to specify this directory.
NOTE: Mesa is attempting to use llvm shared libraries by default.
If you do not want to build with llvm shared libraries and instead want to
use llvm static libraries then add --disable-llvm-shared-libs to your configure
invocation and rebuild.])])
dnl We don't need to update LLVM_LIBS in this case because the LLVM
dnl install uses a shared object for each component and we have
dnl already added all of these objects to LLVM_LIBS.
fi
else
LLVM_LIBS="`$LLVM_CONFIG --libs ${LLVM_COMPONENTS}`"
if test "x$enable_llvm_shared_libs" = xyes; then
detect_old_buggy_llvm
else
AC_MSG_WARN([Building mesa with statically linked LLVM may cause compilation issues])
dnl We need to link to llvm system libs when using static libs
dnl However, only llvm 3.5+ provides --system-libs
if test $LLVM_VERSION_MAJOR -ge 4 -o $LLVM_VERSION_MAJOR -eq 3 -a $LLVM_VERSION_MINOR -ge 5; then
LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --system-libs`"
fi
AC_MSG_WARN([Building mesa with statically linked LLVM may cause compilation issues])
dnl We need to link to llvm system libs when using static libs
dnl However, only llvm 3.5+ provides --system-libs
if test $LLVM_VERSION_MAJOR -ge 4 -o $LLVM_VERSION_MAJOR -eq 3 -a $LLVM_VERSION_MINOR -ge 5; then
LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --system-libs`"
fi
fi
fi
@@ -2719,7 +2731,8 @@ AM_CONDITIONAL(HAVE_GALLIUM_PL111, test "x$HAVE_GALLIUM_PL111" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_R300, test "x$HAVE_GALLIUM_R300" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_R600, test "x$HAVE_GALLIUM_R600" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_RADEONSI, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_RADEON_COMMON, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_RADEON_COMMON, test "x$HAVE_GALLIUM_R600" = xyes -o \
"x$HAVE_GALLIUM_RADEONSI" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_NOUVEAU, test "x$HAVE_GALLIUM_NOUVEAU" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_ETNAVIV, test "x$HAVE_GALLIUM_ETNAVIV" = xyes)
@@ -2731,7 +2744,6 @@ AM_CONDITIONAL(HAVE_GALLIUM_SWRAST, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes -o \
"x$HAVE_GALLIUM_LLVMPIPE" = xyes -o \
"x$HAVE_GALLIUM_SWR" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_VC4, test "x$HAVE_GALLIUM_VC4" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_VC5, test "x$HAVE_GALLIUM_VC5" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_VIRGL, test "x$HAVE_GALLIUM_VIRGL" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_STATIC_TARGETS, test "x$enable_shared_pipe_drivers" = xno)
@@ -2758,9 +2770,6 @@ AM_CONDITIONAL(HAVE_INTEL_VULKAN, test "x$HAVE_INTEL_VULKAN" = xyes)
AM_CONDITIONAL(HAVE_AMD_DRIVERS, test "x$HAVE_GALLIUM_RADEONSI" = xyes -o \
"x$HAVE_RADEON_VULKAN" = xyes)
AM_CONDITIONAL(HAVE_BROADCOM_DRIVERS, test "x$HAVE_GALLIUM_VC4" = xyes -o \
"x$HAVE_GALLIUM_VC5" = xyes)
AM_CONDITIONAL(HAVE_INTEL_DRIVERS, test "x$HAVE_INTEL_VULKAN" = xyes -o \
"x$HAVE_I965_DRI" = xyes)
@@ -2771,7 +2780,6 @@ AM_CONDITIONAL(NEED_WINSYS_XLIB, test "x$enable_glx" = xgallium-xlib)
AM_CONDITIONAL(HAVE_GALLIUM_COMPUTE, test x$enable_opencl = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_LLVM, test "x$enable_llvm" = xyes)
AM_CONDITIONAL(USE_VC4_SIMULATOR, test x$USE_VC4_SIMULATOR = xyes)
AM_CONDITIONAL(USE_VC5_SIMULATOR, test x$USE_VC5_SIMULATOR = xyes)
AM_CONDITIONAL(HAVE_LIBDRM, test "x$have_libdrm" = xyes)
AM_CONDITIONAL(HAVE_OSMESA, test "x$enable_osmesa" = xyes)
@@ -2885,13 +2893,12 @@ AC_CONFIG_FILES([Makefile
src/gallium/drivers/etnaviv/Makefile
src/gallium/drivers/imx/Makefile
src/gallium/drivers/vc4/Makefile
src/gallium/drivers/vc5/Makefile
src/gallium/drivers/virgl/Makefile
src/gallium/state_trackers/clover/Makefile
src/gallium/state_trackers/dri/Makefile
src/gallium/state_trackers/glx/xlib/Makefile
src/gallium/state_trackers/nine/Makefile
src/gallium/state_trackers/omx_bellagio/Makefile
src/gallium/state_trackers/omx/Makefile
src/gallium/state_trackers/osmesa/Makefile
src/gallium/state_trackers/va/Makefile
src/gallium/state_trackers/vdpau/Makefile
@@ -2901,7 +2908,7 @@ AC_CONFIG_FILES([Makefile
src/gallium/targets/d3dadapter9/d3d.pc
src/gallium/targets/dri/Makefile
src/gallium/targets/libgl-xlib/Makefile
src/gallium/targets/omx-bellagio/Makefile
src/gallium/targets/omx/Makefile
src/gallium/targets/opencl/Makefile
src/gallium/targets/opencl/mesa.icd
src/gallium/targets/osmesa/Makefile
@@ -2929,7 +2936,6 @@ AC_CONFIG_FILES([Makefile
src/gallium/winsys/sw/wrapper/Makefile
src/gallium/winsys/sw/xlib/Makefile
src/gallium/winsys/vc4/drm/Makefile
src/gallium/winsys/vc5/drm/Makefile
src/gallium/winsys/virgl/drm/Makefile
src/gallium/winsys/virgl/vtest/Makefile
src/gbm/Makefile
@@ -2950,6 +2956,7 @@ AC_CONFIG_FILES([Makefile
src/mesa/gl.pc
src/mesa/drivers/dri/dri.pc
src/mesa/drivers/dri/common/Makefile
src/mesa/drivers/dri/common/xmlpool/Makefile
src/mesa/drivers/dri/i915/Makefile
src/mesa/drivers/dri/i965/Makefile
src/mesa/drivers/dri/Makefile
@@ -2961,11 +2968,8 @@ AC_CONFIG_FILES([Makefile
src/mesa/drivers/osmesa/osmesa.pc
src/mesa/drivers/x11/Makefile
src/mesa/main/tests/Makefile
src/mesa/state_tracker/tests/Makefile
src/util/Makefile
src/util/tests/hash_table/Makefile
src/util/tests/string_buffer/Makefile
src/util/xmlpool/Makefile
src/vulkan/Makefile])
AC_OUTPUT
@@ -2974,8 +2978,6 @@ AC_OUTPUT
# source file
$SED -i -e 's/brw_blorp.cpp/brw_blorp.c/' src/mesa/drivers/dri/i965/.deps/brw_blorp.Plo
rm -f src/compiler/spirv/spirv_info.lo
echo "# dummy" > src/compiler/spirv/.deps/spirv_info.Plo
dnl
dnl Output some configuration info for the user

View File

@@ -130,6 +130,16 @@ mesa/demos repository.</p>
runtime</p>
<dl>
<dt><code>EGL_DRIVER</code></dt>
<dd>
<p>This variable specifies a full path to or the name of an EGL driver. It
forces the specified EGL driver to be loaded. It comes in handy when one wants
to test a specific driver. This variable is ignored for setuid/setgid
binaries.</p>
</dd>
<dt><code>EGL_PLATFORM</code></dt>
<dd>

View File

@@ -29,12 +29,12 @@ sometimes be useful for debugging end-user issues.
<li>LIBGL_DEBUG - If defined debug information will be printed to stderr.
If set to 'verbose' additional information will be printed.
<li>LIBGL_DRIVERS_PATH - colon-separated list of paths to search for DRI drivers
<li>LIBGL_ALWAYS_INDIRECT - if set to `true`, forces an indirect rendering context/connection.
<li>LIBGL_ALWAYS_SOFTWARE - if set to `true`, always use software rendering
<li>LIBGL_NO_DRAWARRAYS - if set to `true`, do not use DrawArrays GLX protocol (for debugging)
<li>LIBGL_ALWAYS_INDIRECT - forces an indirect rendering context/connection.
<li>LIBGL_ALWAYS_SOFTWARE - if set, always use software rendering
<li>LIBGL_NO_DRAWARRAYS - if set do not use DrawArrays GLX protocol (for debugging)
<li>LIBGL_SHOW_FPS - print framerate to stdout based on the number of glXSwapBuffers
calls per second.
<li>LIBGL_DRI3_DISABLE - disable DRI3 if set to `true`.
<li>LIBGL_DRI3_DISABLE - disable DRI3 if set (the value does not matter)
</ul>
@@ -46,7 +46,7 @@ sometimes be useful for debugging end-user issues.
<li>MESA_NO_MMX - if set, disables Intel MMX optimizations
<li>MESA_NO_3DNOW - if set, disables AMD 3DNow! optimizations
<li>MESA_NO_SSE - if set, disables Intel SSE optimizations
<li>MESA_NO_ERROR - if set to 1, error checking is disabled as per KHR_no_error.
<li>MESA_NO_ERROR - if set error checking is disabled as per KHR_no_error.
This will result in undefined behaviour for invalid use of the api, but
can reduce CPU use for apps that are known to be error free.</li>
<li>MESA_DEBUG - if set, error messages are printed to stderr. For example,
@@ -117,7 +117,7 @@ glGetString(GL_VERSION) for OpenGL ES.
glGetString(GL_SHADING_LANGUAGE_VERSION). Valid values are integers, such as
"130". Mesa will not really implement all the features of the given language version
if it's higher than what's normally reported. (for developers only)
<li>MESA_GLSL_CACHE_DISABLE - if set to `true`, disables the GLSL shader cache
<li>MESA_GLSL_CACHE_DISABLE - if set, disables the GLSL shader cache
<li>MESA_GLSL_CACHE_MAX_SIZE - if set, determines the maximum size of
the on-disk cache of compiled GLSL programs. Should be set to a number
optionally followed by 'K', 'M', or 'G' to specify a size in
@@ -133,8 +133,6 @@ that variable is set), or else within .cache/mesa within the user's
home directory.
<li>MESA_GLSL - <a href="shading.html#envvars">shading language compiler options</a>
<li>MESA_NO_MINMAX_CACHE - when set, the minmax index cache is globally disabled.
<li>MESA_SHADER_CAPTURE_PATH - see <a href="shading.html#capture">Capturing Shaders</a></li>
<li>MESA_SHADER_DUMP_PATH and MESA_SHADER_READ_PATH - see <a href="shading.html#replacement">Experimenting with Shader Replacements</a></li>
</ul>
@@ -192,13 +190,11 @@ See the <a href="xlibdriver.html">Xlib software driver page</a> for details.
<li>perfmon - emit messages about AMD_performance_monitor</li>
<li>pix - emit messages about pixel operations</li>
<li>prim - emit messages about drawing primitives</li>
<li>reemit - mark all state dirty on each draw call</li>
<li>sf - emit messages about the strips &amp; fans unit (for old gens, includes the SF program)</li>
<li>shader_time - record how much GPU time is spent in each shader</li>
<li>spill_fs - force spilling of all registers in the scalar backend (useful to debug spilling code)</li>
<li>spill_vec4 - force spilling of all registers in the vec4 backend (useful to debug spilling code)</li>
<li>state - emit messages about state flag tracking</li>
<li>submit - emit batchbuffer usage statistics</li>
<li>sync - after sending each batch, emit a message and wait for that batch to finish rendering</li>
<li>tcs - dump shader assembly for tessellation control shaders</li>
<li>tes - dump shader assembly for tessellation evaluation shaders</li>
@@ -244,7 +240,7 @@ Mesa EGL supports different sets of environment variables. See the
Use kill -10 <pid> to toggle the hud as desired.
<li>GALLIUM_HUD_DUMP_DIR - specifies a directory for writing the displayed
hud values into files.
<li>GALLIUM_DRIVER - useful in combination with LIBGL_ALWAYS_SOFTWARE=true for
<li>GALLIUM_DRIVER - useful in combination with LIBGL_ALWAYS_SOFTWARE=1 for
choosing one of the software renderers "softpipe", "llvmpipe" or "swr".
<li>GALLIUM_LOG_FILE - specifies a file for logging all errors, warnings, etc.
rather than stderr.

View File

@@ -131,7 +131,7 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
GL_ARB_texture_buffer_object_rgb32 DONE (i965/gen6+, llvmpipe, softpipe, swr)
GL_ARB_texture_cube_map_array DONE (i965/gen6+, nv50, llvmpipe, softpipe)
GL_ARB_texture_gather DONE (i965/gen6+, nv50, llvmpipe, softpipe, swr)
GL_ARB_texture_query_lod DONE (i965, nv50, llvmpipe, softpipe)
GL_ARB_texture_query_lod DONE (i965, nv50, softpipe)
GL_ARB_transform_feedback2 DONE (i965/gen6+, nv50, llvmpipe, softpipe, swr)
GL_ARB_transform_feedback3 DONE (i965/gen7+, llvmpipe, softpipe, swr)
@@ -221,22 +221,6 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
GL_KHR_robustness DONE (i965)
GL_EXT_shader_integer_mix DONE (all drivers that support GLSL)
GL 4.6, GLSL 4.60
GL_ARB_gl_spirv in progress (Nicolai Hähnle, Ian Romanick)
GL_ARB_indirect_parameters DONE (i965/gen7+, nvc0, radeonsi)
GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, llvmpipe, softpipe, swr)
GL_ARB_polygon_offset_clamp DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr)
GL_ARB_shader_atomic_counter_ops DONE (i965/gen7+, nvc0, radeonsi, softpipe)
GL_ARB_shader_draw_parameters DONE (i965, nvc0, radeonsi)
GL_ARB_shader_group_vote DONE (i965, nvc0, radeonsi)
GL_ARB_spirv_extensions in progress (Nicolai Hähnle, Ian Romanick)
GL_ARB_texture_filter_anisotropic DONE (i965, nv50, nvc0, r600, radeonsi, softpipe (*), llvmpipe (*))
GL_ARB_transform_feedback_overflow_query DONE (i965/gen6+, radeonsi, llvmpipe, softpipe)
GL_KHR_no_error started (Timothy Arceri)
(*) softpipe and llvmpipe advertise 16x anisotropy but simply ignore the setting
These are the extensions cherry-picked to make GLES 3.1
GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi
@@ -298,14 +282,20 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_compute_variable_group_size DONE (nvc0, radeonsi)
GL_ARB_ES3_2_compatibility DONE (i965/gen8+)
GL_ARB_fragment_shader_interlock not started
GL_ARB_gl_spirv not started
GL_ARB_gpu_shader_int64 DONE (i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe)
GL_ARB_indirect_parameters DONE (nvc0, radeonsi)
GL_ARB_parallel_shader_compile not started, but Chia-I Wu did some related work in 2014
GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, softpipe, swr)
GL_ARB_post_depth_coverage DONE (i965)
GL_ARB_robustness_isolation not started
GL_ARB_sample_locations not started
GL_ARB_seamless_cubemap_per_texture DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
GL_ARB_shader_atomic_counter_ops DONE (i965/gen7+, nvc0, radeonsi, softpipe)
GL_ARB_shader_ballot DONE (i965/gen8+, nvc0, radeonsi)
GL_ARB_shader_clock DONE (i965/gen7+, nv50, nvc0, radeonsi)
GL_ARB_shader_draw_parameters DONE (i965, nvc0, radeonsi)
GL_ARB_shader_group_vote DONE (i965, nvc0, radeonsi)
GL_ARB_shader_stencil_export DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr)
GL_ARB_shader_viewport_layer_array DONE (i965/gen6+, nvc0, radeonsi)
GL_ARB_sparse_buffer DONE (radeonsi/CIK+)
@@ -313,19 +303,15 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_sparse_texture2 not started
GL_ARB_sparse_texture_clamp not started
GL_ARB_texture_filter_minmax not started
GL_EXT_memory_object DONE (radeonsi)
GL_EXT_memory_object_fd DONE (radeonsi)
GL_EXT_memory_object_win32 not started
GL_EXT_semaphore not started
GL_EXT_semaphore_fd not started
GL_EXT_semaphore_win32 not started
GL_ARB_transform_feedback_overflow_query DONE (i965/gen6+)
GL_KHR_blend_equation_advanced_coherent DONE (i965/gen9+)
GL_KHR_no_error started (Timothy Arceri)
GL_KHR_texture_compression_astc_hdr DONE (i965/bxt)
GL_KHR_texture_compression_astc_sliced_3d DONE (i965/gen9+)
GL_OES_depth_texture_cube_map DONE (all drivers that support GLSL 1.30+)
GL_OES_EGL_image DONE (all drivers)
GL_OES_EGL_image_external_essl3 not started
GL_OES_required_internalformat DONE (all drivers)
GL_OES_required_internalformat not started - GLES2 extension based on OpenGL ES 3.0 feature
GL_OES_surfaceless_context DONE (all drivers)
GL_OES_texture_compression_astc DONE (core only)
GL_OES_texture_float DONE (i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
@@ -347,47 +333,6 @@ we DO NOT WANT implementations of these extensions for Mesa.
GL_ARB_shadow_ambient Superseded by GL_ARB_fragment_program
GL_ARB_vertex_blend Superseded by GL_ARB_vertex_program
Vulkan 1.0 -- all DONE: anv, radv
Khronos extensions that are not part of any Vulkan version:
VK_KHR_16bit_storage in progress (Alejandro)
VK_KHR_android_surface not started
VK_KHR_dedicated_allocation DONE (anv, radv)
VK_KHR_descriptor_update_template DONE (anv, radv)
VK_KHR_display not started
VK_KHR_display_swapchain not started
VK_KHR_external_fence not started
VK_KHR_external_fence_capabilities not started
VK_KHR_external_fence_fd not started
VK_KHR_external_fence_win32 not started
VK_KHR_external_memory DONE (anv, radv)
VK_KHR_external_memory_capabilities DONE (anv, radv)
VK_KHR_external_memory_fd DONE (anv, radv)
VK_KHR_external_memory_win32 not started
VK_KHR_external_semaphore DONE (radv)
VK_KHR_external_semaphore_capabilities DONE (radv)
VK_KHR_external_semaphore_fd DONE (radv)
VK_KHR_external_semaphore_win32 not started
VK_KHR_get_memory_requirements2 DONE (anv, radv)
VK_KHR_get_physical_device_properties2 DONE (anv, radv)
VK_KHR_get_surface_capabilities2 DONE (anv)
VK_KHR_incremental_present DONE (anv, radv)
VK_KHR_maintenance1 DONE (anv, radv)
VK_KHR_mir_surface not started
VK_KHR_push_descriptor DONE (anv, radv)
VK_KHR_sampler_mirror_clamp_to_edge DONE (anv, radv)
VK_KHR_shader_draw_parameters DONE (anv, radv)
VK_KHR_shared_presentable_image not started
VK_KHR_storage_buffer_storage_class DONE (anv, radv)
VK_KHR_surface DONE (anv, radv)
VK_KHR_swapchain DONE (anv, radv)
VK_KHR_variable_pointers DONE (anv, radv)
VK_KHR_wayland_surface DONE (anv, radv)
VK_KHR_win32_keyed_mutex not started
VK_KHR_win32_surface not started
VK_KHR_xcb_surface DONE (anv, radv)
VK_KHR_xlib_surface DONE (anv, radv)
A graphical representation of this information can be found at
https://mesamatrix.net/

View File

@@ -35,8 +35,17 @@ There are plenty of open bugs in the <a href="https://bugs.freedesktop.org/descr
Enable gcc -Wstrict-aliasing=2 -fstrict-aliasing and track down aliasing
issues in the code.
<li>
<b>Windows driver building, testing and maintenance.</b>
Fixing MSVC builds.
<li>
<b>Contribute more tests to
<a href="https://piglit.freedesktop.org/">Piglit</a>.</b>
<li>
<b>Automatic testing.
</b>
It would be great if someone would set up an automated system for grabbing
the latest Mesa code and run tests (such as piglit) then report issues to
the mailing list.
</ol>
<p>
@@ -49,16 +58,24 @@ You can find some further To-do lists here:
<ul>
<li><a href="https://cgit.freedesktop.org/mesa/mesa/tree/docs/features.txt">
<b>features.txt</b></a> - Status of OpenGL 3.x / 4.x features in Mesa.</li>
<li><a href="https://dri.freedesktop.org/wiki/MissingFunctionality">
<b>MissingFunctionality</b></a> - Detailed information about missing OpenGL features.</li>
</ul>
<p>
<b>Legacy Driver specific To-Do lists:</b>
<b>Driver specific To-Do lists:</b>
</p>
<ul>
<li><a href="https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/docs/llvm-todo.txt">
<b>LLVMpipe</b></a> - Software driver using LLVM for runtime code generation.</li>
<li><a href="https://dri.freedesktop.org/wiki/RadeonsiToDo">
<b>radeonsi</b></a> - Driver for AMD Southern Island.</li>
<li><a href="https://dri.freedesktop.org/wiki/R600ToDo">
<b>r600g</b></a> - Driver for ATI/AMD R600 - Northern Island.</li>
<li><a href="https://dri.freedesktop.org/wiki/R300ToDo">
<b>r300g</b></a> - Driver for ATI R300 - R500.</li>
<li><a href="https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/i915/TODO">
<b>i915g</b></a> - Driver for Intel i915/i945.</li>
</ul>
<p>

View File

@@ -16,61 +16,6 @@
<h1>News</h1>
<h2>October 19, 2017</h2>
<p>
<a href="relnotes/17.2.3.html">Mesa 17.2.3</a> is released.
This is a bug-fix release.
</p>
<h2>October 2, 2017</h2>
<p>
<a href="relnotes/17.2.2.html">Mesa 17.2.2</a> is released.
This is a bug-fix release.
</p>
<h2>September 25, 2017</h2>
<p>
<a href="relnotes/17.1.10.html">Mesa 17.1.10</a> is released.
This is a bug-fix release.
</p>
<h2>September 17, 2017</h2>
<p>
<a href="relnotes/17.2.1.html">Mesa 17.2.1</a> is released.
This is a bug-fix release.
</p>
<h2>September 8, 2017</h2>
<p>
<a href="relnotes/17.1.9.html">Mesa 17.1.9</a> is released.
This is a bug-fix release.
</p>
<h2>September 4, 2017</h2>
<p>
<a href="relnotes/17.2.0.html">Mesa 17.2.0</a> is released. This is a
new development release. See the release notes for more information
about the release.
</p>
<h2>August 28, 2017</h2>
<p>
<a href="relnotes/17.1.8.html">Mesa 17.1.8</a> is released.
This is a bug-fix release.
</p>
<h2>August 21, 2017</h2>
<p>
<a href="relnotes/17.1.7.html">Mesa 17.1.7</a> is released.
This is a bug-fix release.
</p>
<h2>August 7, 2017</h2>
<p>
<a href="relnotes/17.1.6.html">Mesa 17.1.6</a> is released.
This is a bug-fix release.
</p>
<h2>July 14, 2017</h2>
<p>
<a href="relnotes/17.1.5.html">Mesa 17.1.5</a> is released.

View File

@@ -59,7 +59,7 @@ to learn if it is thread safe.
Indirect Rendering
You can force indirect rendering mode by setting the LIBGL_ALWAYS_INDIRECT
environment variable to `true`. Hardware acceleration will not be used.
environment variable. Hardware acceleration will not be used.

View File

@@ -32,11 +32,11 @@ It's the fastest software rasterizer for Mesa.
<ul>
<li>
<p>For x86 or amd64 processors, 64-bit mode is recommended.</p>
<p>An x86 or amd64 processor; 64-bit mode recommended.</p>
<p>
Support for SSE2 is strongly encouraged. Support for SSE3 and SSE4.1 will
yield the most efficient code. The fewer features the CPU has the more
likely it is that you will run into underperforming, buggy, or incomplete code.
likely is that you run into underperforming, buggy, or incomplete code.
</p>
<p>
See /proc/cpuinfo to know what your CPU supports.
@@ -50,12 +50,6 @@ It's the fastest software rasterizer for Mesa.
<pre>
aptitude install llvm-dev
</pre>
<p>
If you want development snapshot builds of LLVM for Debian and derived
distributions like Ubuntu, you can use the APT repository at <a
href="https://apt.llvm.org/" title="Debian Development packages for LLVM"
>apt.llvm.org</a>, which are maintained by Debian's LLVM maintainer.
</p>
<p>
For a RPM-based distribution do:
</p>
@@ -234,8 +228,8 @@ build/linux-???-debug/gallium/drivers/llvmpipe:
</ul>
<p>
Some of these tests can output results and benchmarks to a tab-separated file
for later analysis, e.g.:
Some of this tests can output results and benchmarks to a tab-separated-file
for posterior analysis, e.g.:
</p>
<pre>
build/linux-x86_64-debug/gallium/drivers/llvmpipe/lp_test_blend -o blend.tsv
@@ -246,8 +240,8 @@ for later analysis, e.g.:
<ul>
<li>
When looking at this code for the first time, start in lp_state_fs.c, and
then skim through the lp_bld_* functions called there, and the comments
When looking to this code by the first time start in lp_state_fs.c, and
then skim through the lp_bld_* functions called in there, and the comments
at the top of the lp_bld_*.c functions.
</li>
<li>

View File

@@ -39,73 +39,54 @@ if you'd like to nominate a patch in the next stable release.
<th>Notes</th>
</tr>
<tr>
<td rowspan="4">17.2</td>
<td>2017-10-27</td>
<td>17.2.4</td>
<td rowspan="3">17.1</td>
<td>2017-07-28</td>
<td>17.1.6</td>
<td>Emil Velikov</td>
<td></td>
</tr>
<tr>
<td>2017-08-11</td>
<td>17.1.7</td>
<td>Juan A. Suarez Romero</td>
<td></td>
</tr>
<tr>
<td>2017-08-25</td>
<td>17.1.8</td>
<td>Andres Gomez</td>
<td></td>
<td>Final planned release for the 17.1 series</td>
</tr>
<tr>
<td>2017-11-10</td>
<td>17.2.5</td>
<td>Andres Gomez</td>
<td></td>
</tr>
<tr>
<td>2017-11-24</td>
<td>17.2.6</td>
<td>Andres Gomez</td>
<td></td>
</tr>
<tr>
<td>2017-12-08</td>
<td>17.2.7</td>
<td>Emil Velikov</td>
<td>Final planned release for the 17.2 series</td>
</tr>
<tr>
<td rowspan="7">17.3</td>
<td>2017-10-20</td>
<td>17.3.0-rc1</td>
<td rowspan="5">17.2</td>
<td>2017-07-21</td>
<td>17.2.0-rc1</td>
<td>Emil Velikov</td>
<td></td>
</tr>
<tr>
<td>2017-10-27</td>
<td>17.3.0-rc2</td>
<td>2017-07-28</td>
<td>17.2.0-rc2</td>
<td>Emil Velikov</td>
<td></td>
</tr>
<tr>
<td>2017-11-03</td>
<td>17.3.0-rc3</td>
<td>2017-08-04</td>
<td>17.2.0-rc3</td>
<td>Emil Velikov</td>
<td></td>
</tr>
<tr>
<td>2017-11-10</td>
<td>17.3.0-rc4</td>
<td>2017-08-11</td>
<td>17.2.0-rc4</td>
<td>Emil Velikov</td>
<td>May be promoted to 17.3.0 final</td>
<td>May be promoted to 17.2.0 final</td>
</tr>
<tr>
<td>2017-11-24</td>
<td>17.3.1</td>
<td>Andres Gomez</td>
<td></td>
</tr>
<tr>
<td>2017-12-08</td>
<td>17.3.2</td>
<td>2017-08-25</td>
<td>17.2.1</td>
<td>Emil Velikov</td>
<td></td>
</tr>
<tr>
<td>2017-12-22</td>
<td>17.3.3</td>
<td>Emil Velikov</td>
<td></td>
</tr>
</table>
</div>

View File

@@ -428,7 +428,6 @@ Here is one solution that I've been using.
</p>
<pre>
# Set MAKEFLAGS if you haven't already
git clean -fXd; git clean -nxd
read # quick cross check any outstanding files
export __version=`cat VERSION`
@@ -437,12 +436,9 @@ Here is one solution that I've been using.
chmod 755 -fR $__build_root; rm -rf $__build_root
mkdir -p $__build_root &amp;&amp; cd $__build_root
# For the native builds - such as distcheck, scons, sanity test, you
# may want to specify which LLVM to use:
# For the distcheck, you may want to specify which LLVM to use:
# export LLVM_CONFIG=/usr/lib/llvm-3.9/bin/llvm-config
# Do a full distcheck
$__mesa_root/autogen.sh &amp;&amp; make distcheck
$__mesa_root/autogen.sh &amp;&amp; make -j2 distcheck
# Build check the tarballs (scons, linux)
tar -xaf mesa-$__version.tar.xz &amp;&amp; cd mesa-$__version
@@ -450,27 +446,27 @@ Here is one solution that I've been using.
cd .. &amp;&amp; rm -rf mesa-$__version
# Build check the tarballs (scons, windows/mingw)
# Temporary drop LLVM_CONFIG, unless you have a Windows/mingw one.
# save_LLVM_CONFIG=`echo $LLVM_CONFIG`; unset LLVM_CONFIG
# You may need to unset LLVM if you set it before:
# unset LLVM_CONFIG
tar -xaf mesa-$__version.tar.xz &amp;&amp; cd mesa-$__version
scons platform=windows toolchain=crossmingw
cd .. &amp;&amp; rm -rf mesa-$__version
# Test the automake binaries
tar -xaf mesa-$__version.tar.xz &amp;&amp; cd mesa-$__version
# Restore LLVM_CONFIG, if applicable:
# export LLVM_CONFIG=`echo $save_LLVM_CONFIG`; unset save_LLVM_CONFIG
# You may want to specify which LLVM to use:
./configure \
--with-dri-drivers=i965,swrast \
--with-gallium-drivers=swrast \
--with-vulkan-drivers=intel \
--enable-llvm-shared-libs \
--enable-llvm \
--with-llvm-prefix=/usr/lib/llvm-3.9 \
--enable-glx-tls \
--enable-gbm \
--enable-egl \
--with-platforms=x11,drm,wayland,surfaceless
make &amp;&amp; DESTDIR=`pwd`/test make install
make -j2 &amp;&amp; DESTDIR=`pwd`/test make -j6 install
__glxinfo_cmd='glxinfo 2>&amp;1 | egrep -o "Mesa.*|Gallium.*|.*dri\.so"'
__glxgears_cmd='glxgears 2>&amp;1 | grep -v "configuration file"'
__es2info_cmd='es2_info 2>&amp;1 | egrep "GL_VERSION|GL_RENDERER|.*dri\.so"'
@@ -483,12 +479,12 @@ Here is one solution that I've been using.
eval $__glxgears_cmd
eval $__es2info_cmd
eval $__es2gears_cmd
export LIBGL_ALWAYS_SOFTWARE=true
export LIBGL_ALWAYS_SOFTWARE=1
eval $__glxinfo_cmd
eval $__glxgears_cmd
eval $__es2info_cmd
eval $__es2gears_cmd
export LIBGL_ALWAYS_SOFTWARE=true
export LIBGL_ALWAYS_SOFTWARE=1
export GALLIUM_DRIVER=softpipe
eval $__glxinfo_cmd
eval $__glxgears_cmd

View File

@@ -21,15 +21,6 @@ The release notes summarize what's new or changed in each Mesa release.
</p>
<ul>
<li><a href="relnotes/17.2.3.html">17.2.3 release notes</a>
<li><a href="relnotes/17.2.2.html">17.2.2 release notes</a>
<li><a href="relnotes/17.1.10.html">17.1.10 release notes</a>
<li><a href="relnotes/17.2.1.html">17.2.1 release notes</a>
<li><a href="relnotes/17.1.9.html">17.1.9 release notes</a>
<li><a href="relnotes/17.2.0.html">17.2.0 release notes</a>
<li><a href="relnotes/17.1.8.html">17.1.8 release notes</a>
<li><a href="relnotes/17.1.7.html">17.1.7 release notes</a>
<li><a href="relnotes/17.1.6.html">17.1.6 release notes</a>
<li><a href="relnotes/17.1.5.html">17.1.5 release notes</a>
<li><a href="relnotes/17.1.4.html">17.1.4 release notes</a>
<li><a href="relnotes/17.1.3.html">17.1.3 release notes</a>

View File

@@ -1,155 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.1.10 Release Notes / September 25, 2017</h1>
<p>
Mesa 17.1.10 is a bug fix release which fixes bugs found since the 17.1.9 release.
</p>
<p>
Mesa 17.1.10 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
a48ce6b643a728b2b0f926151930525b3670fbff1fb688527fd9051eab9f30a4 mesa-17.1.10.tar.gz
cbc0d681cc4df47d8deb5a36f45b420978128522fd665b2cd4c7096316f11bdb mesa-17.1.10.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102844">Bug 102844</a> - memory leak with glDeleteProgram for shader program type GL_COMPUTE_SHADER</li>
</ul>
<h2>Changes</h2>
<p>Alexandre Demers (1):</p>
<ul>
<li>osmesa: link with libunwind if enabled (v2)</li>
</ul>
<p>Andres Gomez (12):</p>
<ul>
<li>docs: add sha256 checksums for 17.1.9</li>
<li>cherry-ignore: add "st/mesa: skip draw calls with pipe_draw_info::count == 0"</li>
<li>cherry-ignore: add "radv: use amdgpu_bo_va_op_raw."</li>
<li>cherry-ignore: add "radv: use simpler indirect packet 3 if possible."</li>
<li>cherry-ignore: add "radeonsi: don't always apply the PrimID instancing bug workaround on SI"</li>
<li>cherry-ignore: add "intel/eu/validate: Look up types on demand in execution_type()"</li>
<li>cherry-ignore: add "radv: gfx9 fixes"</li>
<li>cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d arrays/3d images"</li>
<li>cherry-ignore: add "radv/gfx9: fix image resource handling."</li>
<li>cherry-ignore: add "docs/egl: remove reference to EGL_DRIVERS_PATH"</li>
<li>cherry-ignore: add "radv: Disable multilayer &amp; multilevel DCC."</li>
<li>cherry-ignore: add "radv: Don't allocate CMASK for linear images."</li>
</ul>
<p>Dave Airlie (2):</p>
<ul>
<li>radv/ac: bump params array for image atomic comp swap</li>
<li>st/glsl-&gt;tgsi: fix u64 to bool comparisons.</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension</li>
<li>automake: enable libunwind in `make distcheck'</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>broadcom/vc4: Fix use-after-free for flushing when writing to a texture.</li>
<li>broadcom/vc4: Fix use-after-free trying to mix a quad and tile clear.</li>
<li>broadcom/vc4: Fix use-after-free when deleting a program.</li>
</ul>
<p>George Kyriazis (1):</p>
<ul>
<li>swr: invalidate attachment on transition change</li>
</ul>
<p>Gert Wollny (2):</p>
<ul>
<li>travis: force llvm-3.3 for "make Gallium ST Other"</li>
<li>travis: Add libunwind-dev to gallium/make builds</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>i965/blorp: Set r8stencil_needs_update when writing stencil</li>
</ul>
<p>Juan A. Suarez Romero (9):</p>
<ul>
<li>cherry-ignore: add "ac/surface: match Z and stencil tile config"</li>
<li>cherry-ignore: add "radv/nir: call opt_remove_phis after trivial continues."</li>
<li>cherry-ignore: add "amd/common: add workaround for cube map array layer clamping"</li>
<li>cherry-ignore: add "radeonsi: workaround for gather4 on integer cube maps"</li>
<li>cherry-ignore: add "Scons: Add LLVM 5.0 support"</li>
<li>cherry-ignore: add "ac/surface: handle S8 on gfx9"</li>
<li>cherry-ignore: add "radv: Check for GFX9 for 1D arrays in image_size intrinsic."</li>
<li>cherry-ignore: add "glsl/linker: fix output variable overlap check"</li>
<li>Update version to 17.1.10</li>
</ul>
<p>Józef Kucia (1):</p>
<ul>
<li>anv: Fix descriptors copying</li>
</ul>
<p>Matt Turner (2):</p>
<ul>
<li>util: Link libmesautil into u_atomic_test</li>
<li>util/u_atomic: Add implementation of __sync_val_compare_and_swap_8</li>
</ul>
<p>Nicolai Hähnle (1):</p>
<ul>
<li>radeonsi: apply a mask to gl_SampleMaskIn in the PS prolog</li>
</ul>
<p>Nicolai Hähnle (4):</p>
<ul>
<li>st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index</li>
<li>amd/common: round cube array slice in ac_prepare_cube_coords</li>
<li>radeonsi: set MIP_POINT_PRECLAMP to 0</li>
<li>radeonsi: fix array textures layer coordinate</li>
</ul>
<p>Tapani Pälli (1):</p>
<ul>
<li>mesa: free current ComputeProgram state in _mesa_free_context_data</li>
</ul>
</div>
</body>
</html>

View File

@@ -1,225 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.1.6 Release Notes / August 7, 2017</h1>
<p>
Mesa 17.1.6 is a bug fix release which fixes bugs found since the 17.1.5 release.
</p>
<p>
Mesa 17.1.6 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
971831bc1e748b3e8367eee6b9eb509bad2970e3c2f8520ad25f5caa12ca5491 mesa-17.1.6.tar.gz
0686deadde1f126b20aa67e47e8c50502043eee4ecdf60d5009ffda3cebfee50 mesa-17.1.6.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97957">Bug 97957</a> - Awful screen tearing in a separate X server with DRI3</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101683">Bug 101683</a> - Some games hang while loading when compositing is shut off or absent</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101867">Bug 101867</a> - Launch options window renders black in Feral Games in current Mesa trunk</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (1):</p>
<ul>
<li>docs: add sha256 checksums for 17.1.5</li>
</ul>
<p>Bas Nieuwenhuizen (1):</p>
<ul>
<li>radv: Don't underflow non-visible VRAM size.</li>
</ul>
<p>Brian Paul (1):</p>
<ul>
<li>svga: fix texture swizzle writemasking</li>
</ul>
<p>Chad Versace (1):</p>
<ul>
<li>anv/image: Fix VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT</li>
</ul>
<p>Chris Wilson (1):</p>
<ul>
<li>i965: Resolve framebuffers before signaling the fence</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>nir: fix algebraic optimizations</li>
</ul>
<p>Daniel Stone (1):</p>
<ul>
<li>st/dri: Check get-handle return value in queryImage</li>
</ul>
<p>Dave Airlie (5):</p>
<ul>
<li>radv: fix non-0 based layer clears.</li>
<li>radv: fix buffer views on SI/CIK.</li>
<li>radv/ac: realign SI workaround with radeonsi.</li>
<li>radv/ac: port SI TC L1 write corruption fix.</li>
<li>radv: for stencil only set Z tile mode index to same value</li>
</ul>
<p>Emil Velikov (23):</p>
<ul>
<li>cherry-ignore: add "anv: Round u_vector element sizes to a power of two"</li>
<li>anv: advertise v6 of the wayland surface extension</li>
<li>radv: advertise v6 of the wayland surface extension</li>
<li>swrast: add dri2ConfigQueryExtension to the correct extension list</li>
<li>cherry-ignore: add "anv: Transition MCS buffers from the undefined layout"</li>
<li>swr: don't forget to link AVX/AVX2 against pthreads</li>
<li>cherry-ignore: add "i965: Fix offset addition in get_isl_surf"</li>
<li>cherry-ignore: add "i965: Fix = vs == in MCS aux usage assert."</li>
<li>cherry-ignore: add a couple of radeon commits</li>
<li>cherry-ignore: add "swr/rast: non-regex knob fallback code for gcc &lt; 4.9"</li>
<li>cherry-ignore: add "swr: fix transform feedback logic"</li>
<li>cherry-ignore: add a couple of radeonsi/gfx9 commits</li>
<li>cherry-ignore: ignore reverted st/mesa commit</li>
<li>cherry-ignore: add bindless textures fix</li>
<li>cherry-ignore: add "st/glsl_to_tgsi: fix getting the image type for array of structs"</li>
<li>cherry-ignore: add yet another bindless textures fix</li>
<li>bin/cherry-ignore: add radeonsi "fix of a fix"</li>
<li>travis: lower SWR requirement to GCC 4.8, aka std=c++11</li>
<li>i965: use strtol to convert the integer deviceID override</li>
<li>swr: remove unneeded fallback strcasecmp define</li>
<li>cherry-ignore: add a bunch more commits to the list</li>
<li>fixup! cherry-ignore: add a bunch more commits to the list</li>
<li>Update version to 17.1.6</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>broadcom/vc4: Prefer blit via rendering to the software fallback.</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>configure: only install khrplatform.h if needed</li>
</ul>
<p>Iago Toral Quiroga (2):</p>
<ul>
<li>anv/cmd_buffer: fix off by one error in assertion</li>
<li>anv: only expose up to 28 vertex attributes</li>
</ul>
<p>Ilia Mirkin (1):</p>
<ul>
<li>nv50/ir: fix threads calculation for non-compute shaders</li>
</ul>
<p>Jason Ekstrand (5):</p>
<ul>
<li>anv/cmd_buffer: Properly handle render passes with 0 attachments</li>
<li>anv: Stop leaking the no_aux sampler surface state</li>
<li>anv/image: Add INPUT_ATTACHMENT to the list of required usages</li>
<li>nir/vars_to_ssa: Handle missing struct members in foreach_deref_node</li>
<li>spirv: Fix SpvImageFormatR16ui</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>anv/pipeline: use unsigned long long constant to check enable vertex inputs</li>
<li>anv/pipeline: do not use BITFIELD64_BIT()</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>nir: Use nir_src_copy instead of direct assignments.</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>i965: perf: flush batchbuffers at the beginning of queries</li>
</ul>
<p>Lucas Stach (1):</p>
<ul>
<li>etnaviv: fix memory leak when BO allocation fails</li>
</ul>
<p>Marek Olšák (2):</p>
<ul>
<li>st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers</li>
<li>gallium/radeon: make S_FIXED function signed and move it to shared code</li>
</ul>
<p>Mark Thompson (1):</p>
<ul>
<li>st/va: Fix scaling list ordering for H.265</li>
</ul>
<p>Nicolai Hähnle (4):</p>
<ul>
<li>radeonsi/gfx9: fix crash building monolithic merged ES-GS shader</li>
<li>radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI</li>
<li>radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+</li>
<li>gallium/radeon: fix ARB_query_buffer_object conversion to boolean</li>
</ul>
<p>Thomas Hellstrom (2):</p>
<ul>
<li>loader/dri3: Use dri3_find_back in loader_dri3_swap_buffers_msc</li>
<li>dri3: Wait for all pending swapbuffers to be scheduled before touching the front</li>
</ul>
<p>Tim Rowley (3):</p>
<ul>
<li>gallium/util: fix nondeterministic avx512 detection</li>
<li>swr/rast: quit using linux-specific gettid()</li>
<li>swr/rast: fix scons gen_knobs.h dependency</li>
</ul>
<p>Timothy Arceri (1):</p>
<ul>
<li>nir: fix nir_opt_copy_prop_vars() for arrays of arrays</li>
</ul>
<p>Wladimir J. van der Laan (1):</p>
<ul>
<li>etnaviv: Clear lbl_usage array correctly</li>
</ul>
</div>
</body>
</html>

View File

@@ -1,148 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.1.7 Release Notes / August 21, 2017</h1>
<p>
Mesa 17.1.7 is a bug fix release which fixes bugs found since the 17.1.6 release.
</p>
<p>
Mesa 17.1.7 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
7ca484fe3194e8185d9a20261845bfd284cc40d0f3fda690d317f85ac7b91af5 mesa-17.1.7.tar.gz
69f472a874b1122404fa0bd13e2d6bf87eb3b9ad9c21d2f39872a96d83d9e5f5 mesa-17.1.7.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101334">Bug 101334</a> - AMD SI cards: Some vulkan apps freeze the system</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101766">Bug 101766</a> - Assertion `!&quot;invalid type&quot;' failed when constant expression involves literal of different type</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102024">Bug 102024</a> - FORMAT_FEATURE_SAMPLED_IMAGE_BIT not supported for D16_UNORM and D32_SFLOAT</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102148">Bug 102148</a> - Crash when running qopenglwidget example on mesa llvmpipe win32</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102241">Bug 102241</a> - gallium/wgl: SwapBuffers freezing regularly with swap interval enabled</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (8):</p>
<ul>
<li>cherry-ignore: add "swr: use the correct variable for no undefined symbols"</li>
<li>cherry-ignore: add "radeon/ac: use ds_swizzle for derivs on si/cik."</li>
<li>cherry-ignore: add "configure: remove trailing "-a" in swr architecture teststable: 17.2 nomination only."</li>
<li>cherry-ignore: added 17.2 nominations.</li>
<li>cherry-ignore: add "radv: Handle VK_ATTACHMENT_UNUSED in color attachments."</li>
<li>cherry-ignore: add "virgl: drop precise modifier."</li>
<li>cherry-ignore: add "radv: handle 10-bit format clamping workaround."</li>
<li>Update version to 17.1.7</li>
</ul>
<p>Chris Wilson (1):</p>
<ul>
<li>i965/blit: Remember to include miptree buffer offset in relocs</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>ac/nir: fix lsb emission</li>
</ul>
<p>Dave Airlie (5):</p>
<ul>
<li>intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.</li>
<li>radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)</li>
<li>radv: fix f16-&gt;f32 denorm handling for SI/CIK. (v2)</li>
<li>radv: fix MSAA on SI gpus.</li>
<li>radv: force cs/ps/l2 flush at end of command stream. (v2)</li>
</ul>
<p>Emil Velikov (3):</p>
<ul>
<li>docs: add sha256 checksums for 17.1.6</li>
<li>egl/x11: don't leak xfixes_query in the error path</li>
<li>egl: avoid eglCreatePlatform*Surface{EXT,} crash with invalid dpy</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>util: Fix build on old glibc.</li>
</ul>
<p>Frank Richter (3):</p>
<ul>
<li>st/mesa: fix a null pointer access</li>
<li>st/wgl: check for negative delta in wait_swap_interval()</li>
<li>gallium/os: fix os_time_get_nano() to roll over less</li>
</ul>
<p>Ilia Mirkin (3):</p>
<ul>
<li>glsl/ast: update rhs in addition to the var's constant_value</li>
<li>nv50/ir: fix srcMask computation for TG4 and TXF</li>
<li>nv50/ir: fix TXQ srcMask</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>anv/formats: Allow sampling on depth-only formats on gen7</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nv50/ir: fix ConstantFolding with saturation</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.</li>
</ul>
<p>Marek Olšák (2):</p>
<ul>
<li>ac: fail shader compilation if libelf is replaced by an incompatible version</li>
<li>radeonsi: disable CE by default</li>
</ul>
<p>Tim Rowley (1):</p>
<ul>
<li>swr/rast: Fix invalid casting for calls to Interlocked* functions</li>
</ul>
</div>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.1.8 Release Notes / August 28, 2017</h1>
<p>
Mesa 17.1.8 is a bug fix release which fixes bugs found since the 17.1.7 release.
</p>
<p>
Mesa 17.1.8 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
faa59a677e88fd5224cdfebcdb6ca9ad3e3c64bd562baa8d5c3c1faeef1066b6 mesa-17.1.8.tar.gz
75ed2eaeae26ddd536150f294386468ae2e1a7717948c41cd14b7875be5269db mesa-17.1.8.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101910">Bug 101910</a> - [BYT] ES31-CTS.functional.copy_image.non_compressed.viewclass_96_bits.rgb32f_rgb32f</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102308">Bug 102308</a> - segfault in glCompressedTextureSubImage3D</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (6):</p>
<ul>
<li>docs: add sha256 checksums for 17.1.7</li>
<li>cherry-ignore: cherry-ignore: added 17.2 nominations.</li>
<li>cherry-ignore: add "i965/tex: Don't pass samples to miptree_create_for_teximage"</li>
<li>cherry-ignore: add "i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit."</li>
<li>cherry-ignore: add "egl/drm: Fix misused x and y offsets in swrast_*_image*"</li>
<li>Update version to 17.1.8</li>
</ul>
<p>Christoph Haag (1):</p>
<ul>
<li>mesa: only copy requested compressed teximage cubemap faces</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>radv: don't crash if we have no framebuffer</li>
</ul>
<p>Ilia Mirkin (2):</p>
<ul>
<li>glsl: add a few missing int64 constant propagation cases</li>
<li>nv50/ir: properly set sType for TXF ops to U32</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>i965: Stop looking at NewDriverState when emitting 3DSTATE_URB</li>
</ul>
<p>Kai Chen (1):</p>
<ul>
<li>egl/wayland: Use roundtrips when awaiting buffer release</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>i965: perf: minimize the chances to spread queries across batchbuffers</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>radeonsi/gfx9: add a temporary workaround for a tessellation driver bug</li>
</ul>
<p>Tim Rowley (1):</p>
<ul>
<li>swr/rast: switch gen_knobs.cpp license</li>
</ul>
<p>Topi Pohjolainen (1):</p>
<ul>
<li>intel/blorp: Adjust intra-tile x when faking rgb with red-only</li>
</ul>
</div>
</body>
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.1.9 Release Notes / September 8, 2017</h1>
<p>
Mesa 17.1.9 is a bug fix release which fixes bugs found since the 17.1.8 release.
</p>
<p>
Mesa 17.1.9 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
4325401b07b5f44759da781bc8d7c0a4a7244e09a702d16c037090986e07ee22 mesa-17.1.9.tar.gz
5f51ad94341696097d5df7b838183534478216858ac0fc8de183671a36ffea1a mesa-17.1.9.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100613">Bug 100613</a> - Regression in Mesa 17 on s390x (zSystems)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102454">Bug 102454</a> - glibc 2.26 doesn't provide anymore xlocale.h</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102467">Bug 102467</a> - src/mesa/state_tracker/st_cb_readpixels.c:178]: (warning) Redundant assignment</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (8):</p>
<ul>
<li>docs: add sha256 checksums for 17.1.8</li>
<li>cherry-ignore: added 17.2 nominations.</li>
<li>cherry-ignore: add "nir: Fix system_value_from_intrinsic for subgroups"</li>
<li>cherry-ignore: add "i965: Fix crash in fallback GTT mapping."</li>
<li>cherry-ignore: add "radeonsi/gfx9: always flush DB metadata on framebuffer changes"</li>
<li>cherry-ignore: add "radv: Fix vkCopyImage with both depth and stencil aspects."</li>
<li>cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug"</li>
<li>Update version to 17.1.9</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Fix off by one in MAX_VBS assert.</li>
<li>radv: Fix sparse BO mapping merging.</li>
<li>radv: Actually set the cmd_buffer usage_flags.</li>
</ul>
<p>Ben Crocker (1):</p>
<ul>
<li>llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load</li>
</ul>
<p>Charmaine Lee (1):</p>
<ul>
<li>vbo: fix offset in minmax cache key</li>
</ul>
<p>Christian Gmeiner (1):</p>
<ul>
<li>etnaviv: use correct param for etna_compatible_rs_format(..)</li>
</ul>
<p>Emil Velikov (3):</p>
<ul>
<li>egl: don't NULL deref the .get_capabilities function pointer</li>
<li>egl/wayland: plug leaks in dri2_wl_create_window_surface() error path</li>
<li>egl/wayland: polish object teardown in dri2_wl_destroy_surface</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>util: improve compiler guard</li>
</ul>
<p>Grazvydas Ignotas (2):</p>
<ul>
<li>radv: clear dynamic_shader_stages on create</li>
<li>radv: don't assert on empty hash table</li>
</ul>
<p>Ilia Mirkin (2):</p>
<ul>
<li>glsl: fix counting of vertex shader output slots used by explicit vars</li>
<li>st/mesa: fix handling of vertex array double inputs</li>
</ul>
<p>Jason Ekstrand (2):</p>
<ul>
<li>anv/formats: Nicely handle unknown VkFormat enums</li>
<li>spirv: Add support for the HelperInvocation builtin</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nvc0: write 0 to pipeline_statistics.cs_invocations</li>
</ul>
<p>Michael Olbrich (1):</p>
<ul>
<li>egl/dri2: only destroy created objects</li>
</ul>
<p>Ray Strode (1):</p>
<ul>
<li>gallivm: correct channel shift logic on big endian</li>
</ul>
<p>Roland Scheidegger (1):</p>
<ul>
<li>st/mesa: fix view template initialization in try_pbo_readpixels</li>
</ul>
</div>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.2.4 Release Notes / October 30, 2017</h1>
<p>
Mesa 17.2.4 is a bug fix release which fixes bugs found since the 17.2.3 release.
</p>
<p>
Mesa 17.2.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
cb266edc5cf7226219ebaf556ca2e03dff282e0324d20afd80423a5754d1272c mesa-17.2.4.tar.gz
5ba408fecd6e1132e5490eec1a2f04466214e4c65c8b89b331be844768c2e550 mesa-17.2.4.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102774">Bug 102774</a> - [BDW] [Bisected] Absolute constant buffers break VAAPI in mpv</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103388">Bug 103388</a> - Linking libcltgsi.la (llvm/codegen/libclllvm_la-common.lo) fails with &quot;error: no match for 'operator-'&quot; with GCC-7, Mesa from Git and current LLVM revisions</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (8):</p>
<ul>
<li>cherry-ignore: configure.ac: rework llvm detection and handling</li>
<li>cherry-ignore: glsl: fix derived cs variables</li>
<li>cherry-ignore: added 17.3 nominations.</li>
<li>cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.</li>
<li>cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.</li>
<li>cherry-ignore: mesa/bufferobj: don't double negate the range</li>
<li>cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.</li>
<li>Update version to 17.2.4</li>
</ul>
<p>Bas Nieuwenhuizen (1):</p>
<ul>
<li>ac/nir: Fix nir_texop_lod on GFX for 1D arrays.</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>radv/image: bump all the offset to uint64_t.</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>docs: add sha256 checksums for 17.2.3</li>
</ul>
<p>Henri Verbeet (1):</p>
<ul>
<li>vulkan/wsi: Free the event in x11_manage_fifo_queues().</li>
</ul>
<p>Jan Vesely (1):</p>
<ul>
<li>clover: Fix compilation after clang r315871</li>
</ul>
<p>Jason Ekstrand (4):</p>
<ul>
<li>nir/intrinsics: Set the correct num_indices for load_output</li>
<li>intel/fs: Handle flag read/write aliasing in needs_src_copy</li>
<li>anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir</li>
<li>intel/eu: Use EXECUTE_1 for JMPI</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>i965: Revert absolute mode for constant buffer pointers.</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>Revert "mesa: fix texture updates for ATI_fragment_shader"</li>
</ul>
<p>Matthew Nicholls (1):</p>
<ul>
<li>ac/nir: generate correct instruction for atomic min/max on unsigned images</li>
</ul>
<p>Michel Dänzer (1):</p>
<ul>
<li>st/mesa: Initialize textures array in st_framebuffer_validate</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: add the draw count buffer to the list of buffers</li>
</ul>
<p>Stefan Schake (1):</p>
<ul>
<li>broadcom/vc4: Fix aliasing issue</li>
</ul>
</div>
</body>
</html>

155
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.2.5 Release Notes / November 10, 2017</h1>
<p>
Mesa 17.2.5 is a bug fix release which fixes bugs found since the 17.2.4 release.
</p>
<p>
Mesa 17.2.5 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97532">Bug 97532</a> - Regression: GLB 2.7 &amp; Glmark-2 GLES versions segfault due to linker precision error (259fc505) on dead variable</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102680">Bug 102680</a> - [OpenGL CTS] KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks fails</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102809">Bug 102809</a> - Rust shadows(?) flash random colours</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103142">Bug 103142</a> - R600g+sb: optimizer apparently stuck in an endless loop</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (8):</p>
<ul>
<li>docs: add sha256 checksums for 17.2.4</li>
<li>cherry-ignore: radv: copy indirect lowering settings from radeonsi</li>
<li>cherry-ignore: i965: fix blorp stage_prog_data-&gt;param leak</li>
<li>cherry-ignore: etnaviv: don't do resolve-in-place without valid TS</li>
<li>cherry-ignore: intel/fs: Alloc pull constants off mem_ctx</li>
<li>cherry-ignore: added 17.3 nominations.</li>
<li>cherry-ignore: automake: include git_sha1.h.in in release tarball</li>
<li>Update version to 17.2.5</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Don't expose heaps with 0 memory.</li>
<li>radv: Don't use vgpr indexing for outputs on GFX9.</li>
<li>radv: Disallow indirect outputs for GS on GFX9 as well.</li>
</ul>
<p>Dave Airlie (3):</p>
<ul>
<li>i915g: make gears run again.</li>
<li>radv: free attachments on end command buffer.</li>
<li>radv: add initial copy descriptor support. (v2)</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>vc4: fix release build</li>
</ul>
<p>Gert Wollny (1):</p>
<ul>
<li>r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling</li>
</ul>
<p>Jason Ekstrand (4):</p>
<ul>
<li>spirv: Claim support for the simple memory model</li>
<li>i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees</li>
<li>i965/blorp: Use more temporary isl_format variables</li>
<li>i965/miptree: Take an isl_format in render_aux_usage</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.</li>
</ul>
<p>Leo Liu (1):</p>
<ul>
<li>radeon/video: add gfx9 offsets when rejoin the video surface</li>
</ul>
<p>Marek Olšák (2):</p>
<ul>
<li>st/dri: don't expose modifiers in EGL if the driver doesn't implement them</li>
<li>ac/surface/gfx9: don't allow DCC for the smallest mipmap levels</li>
</ul>
<p>Nanley Chery (1):</p>
<ul>
<li>i965: Check CCS_E compatibility for texture view rendering</li>
</ul>
<p>Neil Roberts (1):</p>
<ul>
<li>nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB</li>
</ul>
<p>Nicolai Hähnle (1):</p>
<ul>
<li>amd/common/gfx9: workaround DCC corruption more conservatively</li>
</ul>
<p>Tapani Pälli (1):</p>
<ul>
<li>i965: unref push_const_bo in intelDestroyContext</li>
</ul>
<p>Timothy Arceri (1):</p>
<ul>
<li>radv: copy indirect lowering settings from radeonsi</li>
</ul>
<p>Tomasz Figa (1):</p>
<ul>
<li>glsl: Allow precision mismatch on dead data with GLSL ES 1.00</li>
</ul>
<p>Topi Pohjolainen (1):</p>
<ul>
<li>intel/compiler/gen9: Pixel shader header only workaround</li>
</ul>
</div>
</body>
</html>

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@@ -1,72 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.3.0 Release Notes / TBD</h1>
<p>
Mesa 17.3.0 is a new development release.
People who are concerned with stability and reliability should stick
with a previous release or wait for Mesa 17.3.1.
</p>
<p>
Mesa 17.3.0 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<p>
Note: some of the new features are only available with certain drivers.
</p>
<ul>
<li>libtxc_dxtn is now integrated into Mesa. GL_EXT_texture_compression_s3tc and GL_ANGLE_texture_compression_dxt are now always enabled on drivers that support them</li>
<li>GL_ARB_indirect_parameters on i965/gen7+</li>
<li>GL_ARB_polygon_offset_clamp on i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr</li>
<li>GL_ARB_transform_feedback_overflow_query on radeonsi</li>
<li>GL_ARB_texture_filter_anisotropic on i965, nv50, nvc0, r600, radeonsi</li>
<li>GL_EXT_memory_object on radeonsi</li>
<li>GL_EXT_memory_object_fd on radeonsi</li>
<li>EGL_ANDROID_native_fence_sync on radeonsi with a future kernel (possibly 4.15)</li>
<li>EGL_IMG_context_priority on i965</li>
</ul>
<h2>Bug fixes</h2>
<ul>
TBD
</ul>
<h2>Changes</h2>
<ul>
TBD
</ul>
</div>
</body>
</html>

View File

@@ -64,9 +64,9 @@ execution. These are generally used for debugging.
Example: export MESA_GLSL=dump,nopt
</p>
<h3 id="replacement">Experimenting with Shader Replacements</h3>
<p>
Shaders can be dumped and replaced on runtime for debugging purposes. This
Shaders can be dumped and replaced on runtime for debugging purposes. Mesa
needs to be configured with '--with-sha1' to enable this functionality. This
feature is not currently supported by SCons build.
This is controlled via following environment variables:
@@ -76,22 +76,7 @@ This is controlled via following environment variables:
</ul>
Note, path set must exist before running for dumping or replacing to work.
When both are set, these paths should be different so the dumped shaders do
not clobber the replacement shaders. Also, the filenames of the replacement shaders
should match the filenames of the corresponding dumped shaders.
</p>
<h3 id="capture">Capturing Shaders</h3>
<p>
Setting <b>MESA_SHADER_CAPTURE_PATH</b> to a directory will cause the compiler
to write <tt>.shader_test</tt> files for use with
<a href="https://cgit.freedesktop.org/mesa/shader-db">shader-db</a>, a tool
which compiler developers can use to gather statistics about shaders
(instructions, cycles, memory accesses, and so on).
</p>
<p>
Notably, this captures linked GLSL shaders - with all stages together -
as well as ARB programs.
not clobber the replacement shaders.
</p>
<h2 id="support">GLSL Version</h2>

View File

@@ -145,7 +145,7 @@ each directory.
<li><b>xvmc</b> - XvMC state tracker
<li><b>vdpau</b> - VDPAU state tracker
<li><b>va</b> - VA-API state tracker
<li><b>omx_bellagio</b> - OpenMAX Bellagio state tracker
<li><b>omx</b> - OpenMAX state tracker
</ul>
<li><b>winsys</b> -
<ul>

View File

@@ -133,7 +133,7 @@ New Tokens
GetFloatv and GetIntegerv:
FRAGMENT_PROGRAM_POSITION_MESA 0x8bb0
VERTEX_PROGRAM_POSITION_MESA 0x8bb5
VERTEX_PROGRAM_POSITION_MESA 0x8bb4
Accepted by the <pname> parameter of GetPointerv:

View File

@@ -46,14 +46,14 @@ GL_MESA_shader_debug.spec: (obsolete)
GL_DEBUG_ASSERT_MESA 0x875B
GL_MESA_program_debug: (obsolete)
GL_FRAGMENT_PROGRAM_POSITION_MESA 0x8BB0
GL_FRAGMENT_PROGRAM_CALLBACK_MESA 0x8BB1
GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA 0x8BB2
GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA 0x8BB3
GL_VERTEX_PROGRAM_POSITION_MESA 0x8BB4
GL_VERTEX_PROGRAM_CALLBACK_MESA 0x8BB5
GL_VERTEX_PROGRAM_CALLBACK_FUNC_MESA 0x8BB6
GL_VERTEX_PROGRAM_CALLBACK_DATA_MESA 0x8BB7
GL_FRAGMENT_PROGRAM_CALLBACK_MESA 0x????
GL_VERTEX_PROGRAM_CALLBACK_MESA 0x????
GL_FRAGMENT_PROGRAM_POSITION_MESA 0x????
GL_VERTEX_PROGRAM_POSITION_MESA 0x????
GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA 0x????
GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA 0x????
GL_VERTEX_PROGRAM_CALLBACK_FUNC_MESA 0x????
GL_VERTEX_PROGRAM_CALLBACK_DATA_MESA 0x????
GL_MESAX_texture_stack:
GL_TEXTURE_1D_STACK_MESAX 0x8759
@@ -63,11 +63,6 @@ GL_MESAX_texture_stack:
GL_TEXTURE_1D_STACK_BINDING_MESAX 0x875D
GL_TEXTURE_2D_STACK_BINDING_MESAX 0x875E
GL_MESA_tile_raster_order
GL_TILE_RASTER_ORDER_FIXED_MESA 0x8BB8
GL_TILE_RASTER_ORDER_INCREASING_X_MESA 0x8BB9
GL_TILE_RASTER_ORDER_INCREASING_Y_MESA 0x8BBA
EGL_MESA_drm_image
EGL_DRM_BUFFER_FORMAT_MESA 0x31D0
EGL_DRM_BUFFER_USE_MESA 0x31D1

View File

@@ -151,18 +151,6 @@ Whenever possible and applicable, test the patch with
to check for regressions.
</p>
<p>
As mentioned at the begining, patches should be bisectable.
A good way to test this is to make use of the `git rebase` command,
to run your tests on each commit. Assuming your branch is based off
<code>origin/master</code>, you can run:
<pre>
$ git rebase --interactive --exec "make check" origin/master
</pre>
replacing <code>"make check"</code> with whatever other test you want to
run.
</p>
<h2 id="mailing">Mailing Patches</h2>

View File

@@ -97,7 +97,8 @@ typedef void *EGLNativeWindowType;
#elif defined(__ANDROID__) || defined(ANDROID)
struct ANativeWindow;
#include <android/native_window.h>
struct egl_native_pixmap_t;
typedef struct ANativeWindow* EGLNativeWindowType;

View File

@@ -578,17 +578,15 @@ GLAPI void APIENTRY glGetCompressedTexImage (GLenum target, GLint level, void *i
#define GL_TEXTURE_DEPTH_SIZE 0x884A
#define GL_TEXTURE_COMPARE_MODE 0x884C
#define GL_TEXTURE_COMPARE_FUNC 0x884D
#define GL_BLEND_COLOR 0x8005
#define GL_BLEND_EQUATION 0x8009
#define GL_FUNC_ADD 0x8006
#define GL_FUNC_SUBTRACT 0x800A
#define GL_FUNC_REVERSE_SUBTRACT 0x800B
#define GL_MIN 0x8007
#define GL_MAX 0x8008
#define GL_CONSTANT_COLOR 0x8001
#define GL_ONE_MINUS_CONSTANT_COLOR 0x8002
#define GL_CONSTANT_ALPHA 0x8003
#define GL_ONE_MINUS_CONSTANT_ALPHA 0x8004
#define GL_FUNC_ADD 0x8006
#define GL_FUNC_REVERSE_SUBTRACT 0x800B
#define GL_FUNC_SUBTRACT 0x800A
#define GL_MIN 0x8007
#define GL_MAX 0x8008
typedef void (APIENTRYP PFNGLBLENDFUNCSEPARATEPROC) (GLenum sfactorRGB, GLenum dfactorRGB, GLenum sfactorAlpha, GLenum dfactorAlpha);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSPROC) (GLenum mode, const GLint *first, const GLsizei *count, GLsizei drawcount);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSPROC) (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei drawcount);
@@ -2895,42 +2893,6 @@ GLAPI void APIENTRY glTextureBarrier (void);
#endif
#endif /* GL_VERSION_4_5 */
#ifndef GL_VERSION_4_6
#define GL_VERSION_4_6 1
#define GL_SHADER_BINARY_FORMAT_SPIR_V 0x9551
#define GL_SPIR_V_BINARY 0x9552
#define GL_PARAMETER_BUFFER 0x80EE
#define GL_PARAMETER_BUFFER_BINDING 0x80EF
#define GL_CONTEXT_FLAG_NO_ERROR_BIT 0x00000008
#define GL_VERTICES_SUBMITTED 0x82EE
#define GL_PRIMITIVES_SUBMITTED 0x82EF
#define GL_VERTEX_SHADER_INVOCATIONS 0x82F0
#define GL_TESS_CONTROL_SHADER_PATCHES 0x82F1
#define GL_TESS_EVALUATION_SHADER_INVOCATIONS 0x82F2
#define GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED 0x82F3
#define GL_FRAGMENT_SHADER_INVOCATIONS 0x82F4
#define GL_COMPUTE_SHADER_INVOCATIONS 0x82F5
#define GL_CLIPPING_INPUT_PRIMITIVES 0x82F6
#define GL_CLIPPING_OUTPUT_PRIMITIVES 0x82F7
#define GL_POLYGON_OFFSET_CLAMP 0x8E1B
#define GL_SPIR_V_EXTENSIONS 0x9553
#define GL_NUM_SPIR_V_EXTENSIONS 0x9554
#define GL_TEXTURE_MAX_ANISOTROPY 0x84FE
#define GL_MAX_TEXTURE_MAX_ANISOTROPY 0x84FF
#define GL_TRANSFORM_FEEDBACK_OVERFLOW 0x82EC
#define GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW 0x82ED
typedef void (APIENTRYP PFNGLSPECIALIZESHADERPROC) (GLuint shader, const GLchar *pEntryPoint, GLuint numSpecializationConstants, const GLuint *pConstantIndex, const GLuint *pConstantValue);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTPROC) (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTPROC) (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLPOLYGONOFFSETCLAMPPROC) (GLfloat factor, GLfloat units, GLfloat clamp);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glSpecializeShader (GLuint shader, const GLchar *pEntryPoint, GLuint numSpecializationConstants, const GLuint *pConstantIndex, const GLuint *pConstantValue);
GLAPI void APIENTRY glMultiDrawArraysIndirectCount (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCount (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glPolygonOffsetClamp (GLfloat factor, GLfloat units, GLfloat clamp);
#endif
#endif /* GL_VERSION_4_6 */
#ifndef GL_ARB_ES2_compatibility
#define GL_ARB_ES2_compatibility 1
#endif /* GL_ARB_ES2_compatibility */
@@ -3344,17 +3306,19 @@ GLAPI void APIENTRY glProgramUniform4ui64vARB (GLuint program, GLint location, G
#ifndef GL_ARB_imaging
#define GL_ARB_imaging 1
#define GL_BLEND_COLOR 0x8005
#define GL_BLEND_EQUATION 0x8009
#endif /* GL_ARB_imaging */
#ifndef GL_ARB_indirect_parameters
#define GL_ARB_indirect_parameters 1
#define GL_PARAMETER_BUFFER_ARB 0x80EE
#define GL_PARAMETER_BUFFER_BINDING_ARB 0x80EF
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTARBPROC) (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTARBPROC) (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTARBPROC) (GLenum mode, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTARBPROC) (GLenum mode, GLenum type, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMultiDrawArraysIndirectCountARB (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCountARB (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawArraysIndirectCountARB (GLenum mode, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCountARB (GLenum mode, GLenum type, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
#endif
#endif /* GL_ARB_indirect_parameters */
@@ -3432,10 +3396,6 @@ GLAPI void APIENTRY glMaxShaderCompilerThreadsARB (GLuint count);
#define GL_PIXEL_UNPACK_BUFFER_BINDING_ARB 0x88EF
#endif /* GL_ARB_pixel_buffer_object */
#ifndef GL_ARB_polygon_offset_clamp
#define GL_ARB_polygon_offset_clamp 1
#endif /* GL_ARB_polygon_offset_clamp */
#ifndef GL_ARB_post_depth_coverage
#define GL_ARB_post_depth_coverage 1
#endif /* GL_ARB_post_depth_coverage */
@@ -3665,10 +3625,6 @@ GLAPI void APIENTRY glTexPageCommitmentARB (GLenum target, GLint level, GLint xo
#define GL_ARB_sparse_texture_clamp 1
#endif /* GL_ARB_sparse_texture_clamp */
#ifndef GL_ARB_spirv_extensions
#define GL_ARB_spirv_extensions 1
#endif /* GL_ARB_spirv_extensions */
#ifndef GL_ARB_stencil_texturing
#define GL_ARB_stencil_texturing 1
#endif /* GL_ARB_stencil_texturing */
@@ -3734,10 +3690,6 @@ GLAPI void APIENTRY glTexBufferARB (GLenum target, GLenum internalformat, GLuint
#define GL_UNSIGNED_INT_SAMPLER_CUBE_MAP_ARRAY_ARB 0x900F
#endif /* GL_ARB_texture_cube_map_array */
#ifndef GL_ARB_texture_filter_anisotropic
#define GL_ARB_texture_filter_anisotropic 1
#endif /* GL_ARB_texture_filter_anisotropic */
#ifndef GL_ARB_texture_filter_minmax
#define GL_ARB_texture_filter_minmax 1
#define GL_TEXTURE_REDUCTION_MODE_ARB 0x9366
@@ -3899,16 +3851,6 @@ GLAPI void APIENTRY glBlendBarrierKHR (void);
#define GL_CONTEXT_FLAG_NO_ERROR_BIT_KHR 0x00000008
#endif /* GL_KHR_no_error */
#ifndef GL_KHR_parallel_shader_compile
#define GL_KHR_parallel_shader_compile 1
#define GL_MAX_SHADER_COMPILER_THREADS_KHR 0x91B0
#define GL_COMPLETION_STATUS_KHR 0x91B1
typedef void (APIENTRYP PFNGLMAXSHADERCOMPILERTHREADSKHRPROC) (GLuint count);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMaxShaderCompilerThreadsKHR (GLuint count);
#endif
#endif /* GL_KHR_parallel_shader_compile */
#ifndef GL_KHR_robust_buffer_access_behavior
#define GL_KHR_robust_buffer_access_behavior 1
#endif /* GL_KHR_robust_buffer_access_behavior */
@@ -4810,12 +4752,6 @@ GLAPI void APIENTRY glBlendBarrierNV (void);
#define GL_BLEND_ADVANCED_COHERENT_NV 0x9285
#endif /* GL_NV_blend_equation_advanced_coherent */
#ifndef GL_NV_blend_minmax_factor
#define GL_NV_blend_minmax_factor 1
#define GL_FACTOR_MIN_AMD 0x901C
#define GL_FACTOR_MAX_AMD 0x901D
#endif /* GL_NV_blend_minmax_factor */
#ifndef GL_NV_clip_space_w_scaling
#define GL_NV_clip_space_w_scaling 1
#define GL_VIEWPORT_POSITION_W_SCALE_NV 0x937C
@@ -5506,10 +5442,6 @@ GLAPI void APIENTRY glTextureBarrierNV (void);
#endif
#endif /* GL_NV_texture_barrier */
#ifndef GL_NV_texture_rectangle_compressed
#define GL_NV_texture_rectangle_compressed 1
#endif /* GL_NV_texture_rectangle_compressed */
#ifndef GL_NV_uniform_buffer_unified_memory
#define GL_NV_uniform_buffer_unified_memory 1
#define GL_UNIFORM_BUFFER_UNIFIED_NV 0x936E

View File

@@ -51,7 +51,7 @@ extern "C" {
#define GLAPI extern
#endif
#define GL_GLEXT_VERSION 20171010
#define GL_GLEXT_VERSION 20170608
/* Generated C header for:
* API: gl
@@ -353,17 +353,15 @@ GLAPI void APIENTRY glMultTransposeMatrixd (const GLdouble *m);
#define GL_TEXTURE_FILTER_CONTROL 0x8500
#define GL_DEPTH_TEXTURE_MODE 0x884B
#define GL_COMPARE_R_TO_TEXTURE 0x884E
#define GL_BLEND_COLOR 0x8005
#define GL_BLEND_EQUATION 0x8009
#define GL_FUNC_ADD 0x8006
#define GL_FUNC_SUBTRACT 0x800A
#define GL_FUNC_REVERSE_SUBTRACT 0x800B
#define GL_MIN 0x8007
#define GL_MAX 0x8008
#define GL_CONSTANT_COLOR 0x8001
#define GL_ONE_MINUS_CONSTANT_COLOR 0x8002
#define GL_CONSTANT_ALPHA 0x8003
#define GL_ONE_MINUS_CONSTANT_ALPHA 0x8004
#define GL_FUNC_ADD 0x8006
#define GL_FUNC_REVERSE_SUBTRACT 0x800B
#define GL_FUNC_SUBTRACT 0x800A
#define GL_MIN 0x8007
#define GL_MAX 0x8008
typedef void (APIENTRYP PFNGLBLENDFUNCSEPARATEPROC) (GLenum sfactorRGB, GLenum dfactorRGB, GLenum sfactorAlpha, GLenum dfactorAlpha);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSPROC) (GLenum mode, const GLint *first, const GLsizei *count, GLsizei drawcount);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSPROC) (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei drawcount);
@@ -2867,42 +2865,6 @@ GLAPI void APIENTRY glTextureBarrier (void);
#endif
#endif /* GL_VERSION_4_5 */
#ifndef GL_VERSION_4_6
#define GL_VERSION_4_6 1
#define GL_SHADER_BINARY_FORMAT_SPIR_V 0x9551
#define GL_SPIR_V_BINARY 0x9552
#define GL_PARAMETER_BUFFER 0x80EE
#define GL_PARAMETER_BUFFER_BINDING 0x80EF
#define GL_CONTEXT_FLAG_NO_ERROR_BIT 0x00000008
#define GL_VERTICES_SUBMITTED 0x82EE
#define GL_PRIMITIVES_SUBMITTED 0x82EF
#define GL_VERTEX_SHADER_INVOCATIONS 0x82F0
#define GL_TESS_CONTROL_SHADER_PATCHES 0x82F1
#define GL_TESS_EVALUATION_SHADER_INVOCATIONS 0x82F2
#define GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED 0x82F3
#define GL_FRAGMENT_SHADER_INVOCATIONS 0x82F4
#define GL_COMPUTE_SHADER_INVOCATIONS 0x82F5
#define GL_CLIPPING_INPUT_PRIMITIVES 0x82F6
#define GL_CLIPPING_OUTPUT_PRIMITIVES 0x82F7
#define GL_POLYGON_OFFSET_CLAMP 0x8E1B
#define GL_SPIR_V_EXTENSIONS 0x9553
#define GL_NUM_SPIR_V_EXTENSIONS 0x9554
#define GL_TEXTURE_MAX_ANISOTROPY 0x84FE
#define GL_MAX_TEXTURE_MAX_ANISOTROPY 0x84FF
#define GL_TRANSFORM_FEEDBACK_OVERFLOW 0x82EC
#define GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW 0x82ED
typedef void (APIENTRYP PFNGLSPECIALIZESHADERPROC) (GLuint shader, const GLchar *pEntryPoint, GLuint numSpecializationConstants, const GLuint *pConstantIndex, const GLuint *pConstantValue);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTPROC) (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTPROC) (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLPOLYGONOFFSETCLAMPPROC) (GLfloat factor, GLfloat units, GLfloat clamp);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glSpecializeShader (GLuint shader, const GLchar *pEntryPoint, GLuint numSpecializationConstants, const GLuint *pConstantIndex, const GLuint *pConstantValue);
GLAPI void APIENTRY glMultiDrawArraysIndirectCount (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCount (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glPolygonOffsetClamp (GLfloat factor, GLfloat units, GLfloat clamp);
#endif
#endif /* GL_VERSION_4_6 */
#ifndef GL_ARB_ES2_compatibility
#define GL_ARB_ES2_compatibility 1
#endif /* GL_ARB_ES2_compatibility */
@@ -3506,6 +3468,8 @@ typedef unsigned short GLhalfARB;
#ifndef GL_ARB_imaging
#define GL_ARB_imaging 1
#define GL_BLEND_COLOR 0x8005
#define GL_BLEND_EQUATION 0x8009
#define GL_CONVOLUTION_1D 0x8010
#define GL_CONVOLUTION_2D 0x8011
#define GL_SEPARABLE_2D 0x8012
@@ -3642,11 +3606,11 @@ GLAPI void APIENTRY glResetMinmax (GLenum target);
#define GL_ARB_indirect_parameters 1
#define GL_PARAMETER_BUFFER_ARB 0x80EE
#define GL_PARAMETER_BUFFER_BINDING_ARB 0x80EF
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTARBPROC) (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTARBPROC) (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWARRAYSINDIRECTCOUNTARBPROC) (GLenum mode, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
typedef void (APIENTRYP PFNGLMULTIDRAWELEMENTSINDIRECTCOUNTARBPROC) (GLenum mode, GLenum type, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMultiDrawArraysIndirectCountARB (GLenum mode, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCountARB (GLenum mode, GLenum type, const void *indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawArraysIndirectCountARB (GLenum mode, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
GLAPI void APIENTRY glMultiDrawElementsIndirectCountARB (GLenum mode, GLenum type, GLintptr indirect, GLintptr drawcount, GLsizei maxdrawcount, GLsizei stride);
#endif
#endif /* GL_ARB_indirect_parameters */
@@ -3923,10 +3887,6 @@ GLAPI void APIENTRY glPointParameterfvARB (GLenum pname, const GLfloat *params);
#define GL_COORD_REPLACE_ARB 0x8862
#endif /* GL_ARB_point_sprite */
#ifndef GL_ARB_polygon_offset_clamp
#define GL_ARB_polygon_offset_clamp 1
#endif /* GL_ARB_polygon_offset_clamp */
#ifndef GL_ARB_post_depth_coverage
#define GL_ARB_post_depth_coverage 1
#endif /* GL_ARB_post_depth_coverage */
@@ -4330,10 +4290,6 @@ GLAPI void APIENTRY glTexPageCommitmentARB (GLenum target, GLint level, GLint xo
#define GL_ARB_sparse_texture_clamp 1
#endif /* GL_ARB_sparse_texture_clamp */
#ifndef GL_ARB_spirv_extensions
#define GL_ARB_spirv_extensions 1
#endif /* GL_ARB_spirv_extensions */
#ifndef GL_ARB_stencil_texturing
#define GL_ARB_stencil_texturing 1
#endif /* GL_ARB_stencil_texturing */
@@ -4486,10 +4442,6 @@ GLAPI void APIENTRY glGetCompressedTexImageARB (GLenum target, GLint level, void
#define GL_DOT3_RGBA_ARB 0x86AF
#endif /* GL_ARB_texture_env_dot3 */
#ifndef GL_ARB_texture_filter_anisotropic
#define GL_ARB_texture_filter_anisotropic 1
#endif /* GL_ARB_texture_filter_anisotropic */
#ifndef GL_ARB_texture_filter_minmax
#define GL_ARB_texture_filter_minmax 1
#define GL_TEXTURE_REDUCTION_MODE_ARB 0x9366
@@ -4995,16 +4947,6 @@ GLAPI void APIENTRY glBlendBarrierKHR (void);
#define GL_CONTEXT_FLAG_NO_ERROR_BIT_KHR 0x00000008
#endif /* GL_KHR_no_error */
#ifndef GL_KHR_parallel_shader_compile
#define GL_KHR_parallel_shader_compile 1
#define GL_MAX_SHADER_COMPILER_THREADS_KHR 0x91B0
#define GL_COMPLETION_STATUS_KHR 0x91B1
typedef void (APIENTRYP PFNGLMAXSHADERCOMPILERTHREADSKHRPROC) (GLuint count);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMaxShaderCompilerThreadsKHR (GLuint count);
#endif
#endif /* GL_KHR_parallel_shader_compile */
#ifndef GL_KHR_robust_buffer_access_behavior
#define GL_KHR_robust_buffer_access_behavior 1
#endif /* GL_KHR_robust_buffer_access_behavior */
@@ -5709,10 +5651,6 @@ GLAPI void APIENTRY glSetMultisamplefvAMD (GLenum pname, GLuint index, const GLf
#define GL_AMD_shader_explicit_vertex_parameter 1
#endif /* GL_AMD_shader_explicit_vertex_parameter */
#ifndef GL_AMD_shader_image_load_store_lod
#define GL_AMD_shader_image_load_store_lod 1
#endif /* GL_AMD_shader_image_load_store_lod */
#ifndef GL_AMD_shader_stencil_export
#define GL_AMD_shader_stencil_export 1
#endif /* GL_AMD_shader_stencil_export */
@@ -7307,17 +7245,6 @@ GLAPI void APIENTRY glDrawRangeElementsEXT (GLenum mode, GLuint start, GLuint en
#endif
#endif /* GL_EXT_draw_range_elements */
#ifndef GL_EXT_external_buffer
#define GL_EXT_external_buffer 1
typedef void *GLeglClientBufferEXT;
typedef void (APIENTRYP PFNGLBUFFERSTORAGEEXTERNALEXTPROC) (GLenum target, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
typedef void (APIENTRYP PFNGLNAMEDBUFFERSTORAGEEXTERNALEXTPROC) (GLuint buffer, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glBufferStorageExternalEXT (GLenum target, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
GLAPI void APIENTRY glNamedBufferStorageExternalEXT (GLuint buffer, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
#endif
#endif /* GL_EXT_external_buffer */
#ifndef GL_EXT_fog_coord
#define GL_EXT_fog_coord 1
#define GL_FOG_COORDINATE_SOURCE_EXT 0x8450
@@ -9224,13 +9151,6 @@ GLAPI void APIENTRY glResizeBuffersMESA (void);
#define GL_MESA_shader_integer_functions 1
#endif /* GL_MESA_shader_integer_functions */
#ifndef GL_MESA_tile_raster_order
#define GL_MESA_tile_raster_order 1
#define GL_TILE_RASTER_ORDER_FIXED_MESA 0x8BB8
#define GL_TILE_RASTER_ORDER_INCREASING_X_MESA 0x8BB9
#define GL_TILE_RASTER_ORDER_INCREASING_Y_MESA 0x8BBA
#endif /* GL_MESA_tile_raster_order */
#ifndef GL_MESA_window_pos
#define GL_MESA_window_pos 1
typedef void (APIENTRYP PFNGLWINDOWPOS2DMESAPROC) (GLdouble x, GLdouble y);
@@ -9457,10 +9377,6 @@ GLAPI void APIENTRY glBlendBarrierNV (void);
#define GL_BLEND_ADVANCED_COHERENT_NV 0x9285
#endif /* GL_NV_blend_equation_advanced_coherent */
#ifndef GL_NV_blend_minmax_factor
#define GL_NV_blend_minmax_factor 1
#endif /* GL_NV_blend_minmax_factor */
#ifndef GL_NV_blend_square
#define GL_NV_blend_square 1
#endif /* GL_NV_blend_square */
@@ -10541,32 +10457,6 @@ GLAPI void APIENTRY glPrimitiveRestartIndexNV (GLuint index);
#endif
#endif /* GL_NV_primitive_restart */
#ifndef GL_NV_query_resource
#define GL_NV_query_resource 1
#define GL_QUERY_RESOURCE_TYPE_VIDMEM_ALLOC_NV 0x9540
#define GL_QUERY_RESOURCE_MEMTYPE_VIDMEM_NV 0x9542
#define GL_QUERY_RESOURCE_SYS_RESERVED_NV 0x9544
#define GL_QUERY_RESOURCE_TEXTURE_NV 0x9545
#define GL_QUERY_RESOURCE_RENDERBUFFER_NV 0x9546
#define GL_QUERY_RESOURCE_BUFFEROBJECT_NV 0x9547
typedef GLint (APIENTRYP PFNGLQUERYRESOURCENVPROC) (GLenum queryType, GLint tagId, GLuint bufSize, GLint *buffer);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI GLint APIENTRY glQueryResourceNV (GLenum queryType, GLint tagId, GLuint bufSize, GLint *buffer);
#endif
#endif /* GL_NV_query_resource */
#ifndef GL_NV_query_resource_tag
#define GL_NV_query_resource_tag 1
typedef void (APIENTRYP PFNGLGENQUERYRESOURCETAGNVPROC) (GLsizei n, GLint *tagIds);
typedef void (APIENTRYP PFNGLDELETEQUERYRESOURCETAGNVPROC) (GLsizei n, const GLint *tagIds);
typedef void (APIENTRYP PFNGLQUERYRESOURCETAGNVPROC) (GLint tagId, const GLchar *tagString);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glGenQueryResourceTagNV (GLsizei n, GLint *tagIds);
GLAPI void APIENTRY glDeleteQueryResourceTagNV (GLsizei n, const GLint *tagIds);
GLAPI void APIENTRY glQueryResourceTagNV (GLint tagId, const GLchar *tagString);
#endif
#endif /* GL_NV_query_resource_tag */
#ifndef GL_NV_register_combiners
#define GL_NV_register_combiners 1
#define GL_REGISTER_COMBINERS_NV 0x8522
@@ -10843,10 +10733,6 @@ GLAPI void APIENTRY glTextureImage3DMultisampleCoverageNV (GLuint texture, GLenu
#define GL_MAX_RECTANGLE_TEXTURE_SIZE_NV 0x84F8
#endif /* GL_NV_texture_rectangle */
#ifndef GL_NV_texture_rectangle_compressed
#define GL_NV_texture_rectangle_compressed 1
#endif /* GL_NV_texture_rectangle_compressed */
#ifndef GL_NV_texture_shader
#define GL_NV_texture_shader 1
#define GL_OFFSET_TEXTURE_RECTANGLE_NV 0x864C

View File

@@ -34,7 +34,7 @@ extern "C" {
** https://github.com/KhronosGroup/OpenGL-Registry
*/
#define GLX_GLXEXT_VERSION 20170728
#define GLX_GLXEXT_VERSION 20170606
/* Generated C header for:
* API: glx

View File

@@ -48,8 +48,6 @@ typedef unsigned int drm_drawable_t;
typedef struct drm_clip_rect drm_clip_rect_t;
#endif
#include <stdint.h>
/**
* \name DRI interface structures
*
@@ -726,26 +724,11 @@ struct __DRIuseInvalidateExtensionRec {
#define __DRI_ATTRIB_TEXTURE_2D_BIT 0x02
#define __DRI_ATTRIB_TEXTURE_RECTANGLE_BIT 0x04
/* __DRI_ATTRIB_SWAP_METHOD */
/* Note that with the exception of __DRI_ATTRIB_SWAP_NONE, we need to define
* the same tokens as GLX. This is because old and current X servers will
* transmit the driconf value grabbed from the AIGLX driver untranslated as
* the GLX fbconfig value. __DRI_ATTRIB_SWAP_NONE is only used by dri drivers
* to signal to the dri core that the driconfig is single-buffer.
*/
#define __DRI_ATTRIB_SWAP_NONE 0x0000
#define __DRI_ATTRIB_SWAP_EXCHANGE 0x8061
#define __DRI_ATTRIB_SWAP_COPY 0x8062
#define __DRI_ATTRIB_SWAP_UNDEFINED 0x8063
/**
* This extension defines the core DRI functionality.
*
* Version >= 2 indicates that getConfigAttrib with __DRI_ATTRIB_SWAP_METHOD
* returns a reliable value.
*/
#define __DRI_CORE "DRI_Core"
#define __DRI_CORE_VERSION 2
#define __DRI_CORE_VERSION 1
struct __DRIcoreExtensionRec {
__DRIextension base;
@@ -984,15 +967,7 @@ struct __DRIbufferRec {
};
#define __DRI_DRI2_LOADER "DRI_DRI2Loader"
#define __DRI_DRI2_LOADER_VERSION 4
enum dri_loader_cap {
/* Whether the loader handles RGBA channel ordering correctly. If not,
* only BGRA ordering can be exposed.
*/
DRI_LOADER_CAP_RGBA_ORDERING,
};
#define __DRI_DRI2_LOADER_VERSION 3
struct __DRIdri2LoaderExtensionRec {
__DRIextension base;
@@ -1042,18 +1017,6 @@ struct __DRIdri2LoaderExtensionRec {
int *width, int *height,
unsigned int *attachments, int count,
int *out_count, void *loaderPrivate);
/**
* Return a loader capability value. If the loader doesn't know the enum,
* it will return 0.
*
* \param loaderPrivate The last parameter of createNewScreen or
* createNewScreen2.
* \param cap See the enum.
*
* \since 4
*/
unsigned (*getCapability)(void *loaderPrivate, enum dri_loader_cap cap);
};
/**
@@ -1100,12 +1063,6 @@ struct __DRIdri2LoaderExtensionRec {
#define __DRI_CTX_RESET_LOSE_CONTEXT 1
/*@}*/
#define __DRI_CTX_ATTRIB_PRIORITY 4
#define __DRI_CTX_PRIORITY_LOW 0
#define __DRI_CTX_PRIORITY_MEDIUM 1
#define __DRI_CTX_PRIORITY_HIGH 2
/**
* \name Reasons that __DRIdri2Extension::createContextAttribs might fail
*/
@@ -1186,7 +1143,7 @@ struct __DRIdri2ExtensionRec {
* extensions.
*/
#define __DRI_IMAGE "DRI_IMAGE"
#define __DRI_IMAGE_VERSION 17
#define __DRI_IMAGE_VERSION 15
/**
* These formats correspond to the similarly named MESA_FORMAT_*
@@ -1198,7 +1155,7 @@ struct __DRIdri2ExtensionRec {
* by the driver (YUV planar formats) but serve as a base image for
* creating sub-images for the different planes within the image.
*
* R8, GR88 and NONE should not be used with createImageFromName or
* R8, GR88 and NONE should not be used with createImageFormName or
* createImage, and are returned by query from sub images created with
* createImageFromNames (NONE, see above) and fromPlane (R8 & GR88).
*/
@@ -1219,7 +1176,7 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_USE_SHARE 0x0001
#define __DRI_IMAGE_USE_SCANOUT 0x0002
#define __DRI_IMAGE_USE_CURSOR 0x0004 /* Deprecated */
#define __DRI_IMAGE_USE_CURSOR 0x0004 /* Depricated */
#define __DRI_IMAGE_USE_LINEAR 0x0008
/* The buffer will only be read by an external process after SwapBuffers,
* in contrary to gbm buffers, front buffers and fake front buffers, which
@@ -1366,13 +1323,6 @@ enum __DRIChromaSiting {
#define __BLIT_FLAG_FLUSH 0x0001
#define __BLIT_FLAG_FINISH 0x0002
/**
* queryDmaBufFormatModifierAttribs attributes
*/
/* Available in version 16 */
#define __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT 0x0001
typedef struct __DRIimageRec __DRIimage;
typedef struct __DRIimageExtensionRec __DRIimageExtension;
struct __DRIimageExtensionRec {
@@ -1383,7 +1333,6 @@ struct __DRIimageExtensionRec {
int name, int pitch,
void *loaderPrivate);
/* Deprecated since version 17; see createImageFromRenderbuffer2 */
__DRIimage *(*createImageFromRenderbuffer)(__DRIcontext *context,
int renderbuffer,
void *loaderPrivate);
@@ -1614,40 +1563,6 @@ struct __DRIimageExtensionRec {
int max, uint64_t *modifiers,
unsigned int *external_only,
int *count);
/**
* dmabuf format modifier attribute query for a given format and modifier.
*
* \param fourcc The format to query. If this format is not supported by
* the driver, return false.
* \param modifier The modifier to query. If this format+modifier is not
* supported by the driver, return false.
* \param attrib The __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB to query.
* \param value A pointer to where to store the result of the query.
*
* Returns true upon success.
*
* \since 16
*/
GLboolean (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
uint32_t fourcc, uint64_t modifier,
int attrib, uint64_t *value);
/**
* Create a DRI image from the given renderbuffer.
*
* \param context the current DRI context
* \param renderbuffer the GL name of the renderbuffer
* \param loaderPrivate for callbacks into the loader related to the image
* \param error will be set to one of __DRI_IMAGE_ERROR_xxx
* \return the newly created image on success, or NULL otherwise
*
* \since 17
*/
__DRIimage *(*createImageFromRenderbuffer2)(__DRIcontext *context,
int renderbuffer,
void *loaderPrivate,
unsigned *error);
};
@@ -1720,29 +1635,13 @@ typedef struct __DRInoErrorExtensionRec {
*
* This extension provides the XML string containing driver options for use by
* the loader in supporting the driconf application.
*
* v2:
* - Add the getXml getter function which allows the driver more flexibility in
* how the XML is provided.
* - Deprecate the direct xml pointer. It is only provided as a fallback for
* older versions of libGL and must not be used by clients that are aware of
* the newer version. Future driver versions may set it to NULL.
*/
#define __DRI_CONFIG_OPTIONS "DRI_ConfigOptions"
#define __DRI_CONFIG_OPTIONS_VERSION 2
#define __DRI_CONFIG_OPTIONS_VERSION 1
typedef struct __DRIconfigOptionsExtensionRec {
__DRIextension base;
const char *xml; /**< deprecated since v2, use getXml instead */
/**
* Get an XML string that describes available driver options for use by a
* config application.
*
* The returned string must be heap-allocated. The caller is responsible for
* freeing it.
*/
char *(*getXml)(const char *driver_name);
const char *xml;
} __DRIconfigOptionsExtension;
/**
@@ -1788,14 +1687,6 @@ typedef struct __DRIDriverVtableExtensionRec {
*/
#define __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB 0x000c
/* Bitmaks of supported/available context priorities - must match
* __EGL_CONTEXT_PRIORITY_LOW_BIT et al
*/
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY 0x000d
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW (1 << 0)
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM (1 << 1)
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH (1 << 2)
typedef struct __DRI2rendererQueryExtensionRec __DRI2rendererQueryExtension;
struct __DRI2rendererQueryExtensionRec {
__DRIextension base;
@@ -1820,7 +1711,7 @@ struct __DRIimageList {
};
#define __DRI_IMAGE_LOADER "DRI_IMAGE_LOADER"
#define __DRI_IMAGE_LOADER_VERSION 3
#define __DRI_IMAGE_LOADER_VERSION 1
struct __DRIimageLoaderExtensionRec {
__DRIextension base;
@@ -1856,28 +1747,6 @@ struct __DRIimageLoaderExtensionRec {
* into __DRIdri2ExtensionRec::createNewDrawable
*/
void (*flushFrontBuffer)(__DRIdrawable *driDrawable, void *loaderPrivate);
/**
* Return a loader capability value. If the loader doesn't know the enum,
* it will return 0.
*
* \since 2
*/
unsigned (*getCapability)(void *loaderPrivate, enum dri_loader_cap cap);
/**
* Flush swap buffers
*
* Make sure any outstanding swap buffers have been submitted to the
* device.
*
* \param driDrawable Drawable whose swaps need to be flushed
* \param loaderPrivate Loader's private data that was previously passed
* into __DRIdri2ExtensionRec::createNewDrawable
*
* \since 3
*/
void (*flushSwapBuffers)(__DRIdrawable *driDrawable, void *loaderPrivate);
};
/**

View File

@@ -58,16 +58,12 @@ extern "C" {
#endif
/* Forward declarations to avoid inclusion of GL/glx.h */
#ifndef GLX_H
struct _XDisplay;
struct __GLXcontextRec;
#endif
/* Forward declarations to avoid inclusion of EGL/egl.h */
#ifndef __egl_h_
typedef void *EGLDisplay;
typedef void *EGLContext;
#endif
/** Returned error codes. */
enum {

View File

@@ -39,7 +39,7 @@ extern "C" {
#include <windows.h>
#endif
#define WGL_WGLEXT_VERSION 20170817
#define WGL_WGLEXT_VERSION 20170606
/* Generated C header for:
* API: wgl

View File

@@ -38,7 +38,7 @@ extern "C" {
#define GL_APIENTRYP GL_APIENTRY*
#endif
/* Generated on date 20170804 */
/* Generated on date 20170606 */
/* Generated C header for:
* API: gles2
@@ -324,12 +324,12 @@ GL_APICALL GLboolean GL_APIENTRY glIsEnablediOES (GLenum target, GLuint index);
typedef void (GL_APIENTRYP PFNGLDRAWELEMENTSBASEVERTEXOESPROC) (GLenum mode, GLsizei count, GLenum type, const void *indices, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLDRAWRANGEELEMENTSBASEVERTEXOESPROC) (GLenum mode, GLuint start, GLuint end, GLsizei count, GLenum type, const void *indices, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXOESPROC) (GLenum mode, GLsizei count, GLenum type, const void *indices, GLsizei instancecount, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLMULTIDRAWELEMENTSBASEVERTEXEXTPROC) (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
typedef void (GL_APIENTRYP PFNGLMULTIDRAWELEMENTSBASEVERTEXOESPROC) (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
#ifdef GL_GLEXT_PROTOTYPES
GL_APICALL void GL_APIENTRY glDrawElementsBaseVertexOES (GLenum mode, GLsizei count, GLenum type, const void *indices, GLint basevertex);
GL_APICALL void GL_APIENTRY glDrawRangeElementsBaseVertexOES (GLenum mode, GLuint start, GLuint end, GLsizei count, GLenum type, const void *indices, GLint basevertex);
GL_APICALL void GL_APIENTRY glDrawElementsInstancedBaseVertexOES (GLenum mode, GLsizei count, GLenum type, const void *indices, GLsizei instancecount, GLint basevertex);
GL_APICALL void GL_APIENTRY glMultiDrawElementsBaseVertexEXT (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
GL_APICALL void GL_APIENTRY glMultiDrawElementsBaseVertexOES (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
#endif
#endif /* GL_OES_draw_elements_base_vertex */
@@ -1311,10 +1311,12 @@ GL_APICALL GLboolean GL_APIENTRY glIsEnablediEXT (GLenum target, GLuint index);
typedef void (GL_APIENTRYP PFNGLDRAWELEMENTSBASEVERTEXEXTPROC) (GLenum mode, GLsizei count, GLenum type, const void *indices, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLDRAWRANGEELEMENTSBASEVERTEXEXTPROC) (GLenum mode, GLuint start, GLuint end, GLsizei count, GLenum type, const void *indices, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLDRAWELEMENTSINSTANCEDBASEVERTEXEXTPROC) (GLenum mode, GLsizei count, GLenum type, const void *indices, GLsizei instancecount, GLint basevertex);
typedef void (GL_APIENTRYP PFNGLMULTIDRAWELEMENTSBASEVERTEXEXTPROC) (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
#ifdef GL_GLEXT_PROTOTYPES
GL_APICALL void GL_APIENTRY glDrawElementsBaseVertexEXT (GLenum mode, GLsizei count, GLenum type, const void *indices, GLint basevertex);
GL_APICALL void GL_APIENTRY glDrawRangeElementsBaseVertexEXT (GLenum mode, GLuint start, GLuint end, GLsizei count, GLenum type, const void *indices, GLint basevertex);
GL_APICALL void GL_APIENTRY glDrawElementsInstancedBaseVertexEXT (GLenum mode, GLsizei count, GLenum type, const void *indices, GLsizei instancecount, GLint basevertex);
GL_APICALL void GL_APIENTRY glMultiDrawElementsBaseVertexEXT (GLenum mode, const GLsizei *count, GLenum type, const void *const*indices, GLsizei primcount, const GLint *basevertex);
#endif
#endif /* GL_EXT_draw_elements_base_vertex */
@@ -1338,17 +1340,6 @@ GL_APICALL void GL_APIENTRY glDrawTransformFeedbackInstancedEXT (GLenum mode, GL
#endif
#endif /* GL_EXT_draw_transform_feedback */
#ifndef GL_EXT_external_buffer
#define GL_EXT_external_buffer 1
typedef void *GLeglClientBufferEXT;
typedef void (GL_APIENTRYP PFNGLBUFFERSTORAGEEXTERNALEXTPROC) (GLenum target, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
typedef void (GL_APIENTRYP PFNGLNAMEDBUFFERSTORAGEEXTERNALEXTPROC) (GLuint buffer, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
#ifdef GL_GLEXT_PROTOTYPES
GL_APICALL void GL_APIENTRY glBufferStorageExternalEXT (GLenum target, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
GL_APICALL void GL_APIENTRY glNamedBufferStorageExternalEXT (GLuint buffer, GLintptr offset, GLsizeiptr size, GLeglClientBufferEXT clientBuffer, GLbitfield flags);
#endif
#endif /* GL_EXT_external_buffer */
#ifndef GL_EXT_float_blend
#define GL_EXT_float_blend 1
#endif /* GL_EXT_float_blend */
@@ -2010,42 +2001,18 @@ GL_APICALL void GL_APIENTRY glTexBufferRangeEXT (GLenum target, GLenum internalf
#define GL_TEXTURE_ASTC_DECODE_PRECISION_EXT 0x8F69
#endif /* GL_EXT_texture_compression_astc_decode_mode */
#ifndef GL_EXT_texture_compression_bptc
#define GL_EXT_texture_compression_bptc 1
#define GL_COMPRESSED_RGBA_BPTC_UNORM_EXT 0x8E8C
#define GL_COMPRESSED_SRGB_ALPHA_BPTC_UNORM_EXT 0x8E8D
#define GL_COMPRESSED_RGB_BPTC_SIGNED_FLOAT_EXT 0x8E8E
#define GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT_EXT 0x8E8F
#endif /* GL_EXT_texture_compression_bptc */
#ifndef GL_EXT_texture_compression_dxt1
#define GL_EXT_texture_compression_dxt1 1
#define GL_COMPRESSED_RGB_S3TC_DXT1_EXT 0x83F0
#define GL_COMPRESSED_RGBA_S3TC_DXT1_EXT 0x83F1
#endif /* GL_EXT_texture_compression_dxt1 */
#ifndef GL_EXT_texture_compression_rgtc
#define GL_EXT_texture_compression_rgtc 1
#define GL_COMPRESSED_RED_RGTC1_EXT 0x8DBB
#define GL_COMPRESSED_SIGNED_RED_RGTC1_EXT 0x8DBC
#define GL_COMPRESSED_RED_GREEN_RGTC2_EXT 0x8DBD
#define GL_COMPRESSED_SIGNED_RED_GREEN_RGTC2_EXT 0x8DBE
#endif /* GL_EXT_texture_compression_rgtc */
#ifndef GL_EXT_texture_compression_s3tc
#define GL_EXT_texture_compression_s3tc 1
#define GL_COMPRESSED_RGBA_S3TC_DXT3_EXT 0x83F2
#define GL_COMPRESSED_RGBA_S3TC_DXT5_EXT 0x83F3
#endif /* GL_EXT_texture_compression_s3tc */
#ifndef GL_EXT_texture_compression_s3tc_srgb
#define GL_EXT_texture_compression_s3tc_srgb 1
#define GL_COMPRESSED_SRGB_S3TC_DXT1_EXT 0x8C4C
#define GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT 0x8C4D
#define GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT 0x8C4E
#define GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT 0x8C4F
#endif /* GL_EXT_texture_compression_s3tc_srgb */
#ifndef GL_EXT_texture_cube_map_array
#define GL_EXT_texture_cube_map_array 1
#define GL_TEXTURE_CUBE_MAP_ARRAY_EXT 0x9009
@@ -2438,12 +2405,6 @@ GL_APICALL void GL_APIENTRY glBlendBarrierNV (void);
#define GL_BLEND_ADVANCED_COHERENT_NV 0x9285
#endif /* GL_NV_blend_equation_advanced_coherent */
#ifndef GL_NV_blend_minmax_factor
#define GL_NV_blend_minmax_factor 1
#define GL_FACTOR_MIN_AMD 0x901C
#define GL_FACTOR_MAX_AMD 0x901D
#endif /* GL_NV_blend_minmax_factor */
#ifndef GL_NV_conditional_render
#define GL_NV_conditional_render 1
#define GL_QUERY_WAIT_NV 0x8E13
@@ -3117,14 +3078,6 @@ GL_APICALL void GL_APIENTRY glGetProgramResourcefvNV (GLuint program, GLenum pro
#define GL_SHARED_EDGE_NV 0xC0
#endif /* GL_NV_path_rendering_shared_edge */
#ifndef GL_NV_pixel_buffer_object
#define GL_NV_pixel_buffer_object 1
#define GL_PIXEL_PACK_BUFFER_NV 0x88EB
#define GL_PIXEL_UNPACK_BUFFER_NV 0x88EC
#define GL_PIXEL_PACK_BUFFER_BINDING_NV 0x88ED
#define GL_PIXEL_UNPACK_BUFFER_BINDING_NV 0x88EF
#endif /* GL_NV_pixel_buffer_object */
#ifndef GL_NV_polygon_mode
#define GL_NV_polygon_mode 1
#define GL_POLYGON_MODE_NV 0x0B40

View File

@@ -3,9 +3,6 @@ required by the anv & i965 drivers to communicate with the kernel.
Whenever either of those driver needs new definitions for new kernel
APIs, these files should be updated.
These files in master should only be updated once the changes have landed
in the drm-next tree.
You can copy files installed after running this from the kernel
repository, at version the drivers require :
@@ -13,9 +10,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
The last update was done at the following kernel commit :
commit 7846b12fe0b5feab5446d892f41b5140c1419109
Merge: 7ebdb0d d78acfe
commit 6d61e70ccc21606ffb8a0a03bd3aba24f659502b
Merge: 338ffbf7cb5e c0bc126f97fb
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Aug 29 10:38:14 2017 +1000
Date: Tue Jun 27 07:24:49 2017 +1000
Merge branch 'drm-vmwgfx-next' of git://people.freedesktop.org/~syeh/repos_linux into drm-next
Backmerge tag 'v4.12-rc7' into drm-next

View File

@@ -694,7 +694,6 @@ struct drm_prime_handle {
struct drm_syncobj_create {
__u32 handle;
#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
};
@@ -713,24 +712,6 @@ struct drm_syncobj_handle {
__u32 pad;
};
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
struct drm_syncobj_wait {
__u64 handles;
/* absolute timeout */
__s64 timeout_nsec;
__u32 count_handles;
__u32 flags;
__u32 first_signaled; /* only valid when not waiting all */
__u32 pad;
};
struct drm_syncobj_array {
__u64 handles;
__u32 count_handles;
__u32 pad;
};
#if defined(__cplusplus)
}
#endif
@@ -853,9 +834,6 @@ extern "C" {
#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
/**
* Device specific ioctls should only be in their respective headers

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@@ -185,8 +185,6 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
/* add more to the end as needed */
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
#define fourcc_mod_code(vendor, val) \
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
@@ -198,15 +196,6 @@ extern "C" {
* authoritative source for all of these.
*/
/*
* Invalid Modifier
*
* This modifier can be used as a sentinel to terminate the format modifiers
* list, or to initialize a variable with an invalid modifier. It might also be
* used to report an error back to userspace for certain APIs.
*/
#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
/*
* Linear Layout
*
@@ -263,26 +252,6 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
/*
* Intel color control surface (CCS) for render compression
*
* The framebuffer format must be one of the 8:8:8:8 RGB formats.
* The main surface will be plane index 0 and must be Y/Yf-tiled,
* the CCS will be plane index 1.
*
* Each CCS tile matches a 1024x512 pixel area of the main surface.
* To match certain aspects of the 3D hardware the CCS is
* considered to be made up of normal 128Bx32 Y tiles, Thus
* the CCS pitch must be specified in multiples of 128 bytes.
*
* In reality the CCS tile appears to be a 64Bx64 Y tile, composed
* of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
* But that fact is not relevant unless the memory is accessed
* directly.
*/
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*

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@@ -712,56 +712,6 @@ struct drm_mode_atomic {
__u64 user_data;
};
struct drm_format_modifier_blob {
#define FORMAT_BLOB_CURRENT 1
/* Version of this blob format */
__u32 version;
/* Flags */
__u32 flags;
/* Number of fourcc formats supported */
__u32 count_formats;
/* Where in this blob the formats exist (in bytes) */
__u32 formats_offset;
/* Number of drm_format_modifiers */
__u32 count_modifiers;
/* Where in this blob the modifiers exist (in bytes) */
__u32 modifiers_offset;
/* __u32 formats[] */
/* struct drm_format_modifier modifiers[] */
};
struct drm_format_modifier {
/* Bitmask of formats in get_plane format list this info applies to. The
* offset allows a sliding window of which 64 formats (bits).
*
* Some examples:
* In today's world with < 65 formats, and formats 0, and 2 are
* supported
* 0x0000000000000005
* ^-offset = 0, formats = 5
*
* If the number formats grew to 128, and formats 98-102 are
* supported with the modifier:
*
* 0x0000003c00000000 0000000000000000
* ^
* |__offset = 64, formats = 0x3c00000000
*
*/
__u64 formats;
__u32 offset;
__u32 pad;
/* The modifier that applies to the >get_plane format list bitmask. */
__u64 modifier;
};
/**
* Create a new 'blob' data property, copying length bytes from data pointer,
* and returning new blob ID.

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@@ -260,8 +260,6 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
#define DRM_I915_PERF_OPEN 0x36
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -317,8 +315,6 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -397,20 +393,10 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
/*
* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
* priorities and the driver will attempt to execute batches in priority order.
* The param returns a capability bitmask, nonzero implies that the scheduler
* is enabled, with different features present according to the mask.
*
* The initial priority for each batch is supplied by the context and is
* controlled via I915_CONTEXT_PARAM_PRIORITY.
*/
#define I915_PARAM_HAS_SCHEDULER 41
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
@@ -445,11 +431,6 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
* drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
*/
#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
typedef struct drm_i915_getparam {
__s32 param;
/*
@@ -831,17 +812,6 @@ struct drm_i915_gem_exec_object2 {
__u64 rsvd2;
};
struct drm_i915_gem_exec_fence {
/**
* User's handle for a drm_syncobj to wait on or signal.
*/
__u32 handle;
#define I915_EXEC_FENCE_WAIT (1<<0)
#define I915_EXEC_FENCE_SIGNAL (1<<1)
__u32 flags;
};
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
@@ -856,11 +826,7 @@ struct drm_i915_gem_execbuffer2 {
__u32 DR1;
__u32 DR4;
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
* struct drm_i915_gem_exec_fence *fences.
*/
/** This is a struct drm_clip_rect *cliprects */
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (7<<0)
#define I915_EXEC_DEFAULT (0<<0)
@@ -961,14 +927,7 @@ struct drm_i915_gem_execbuffer2 {
* element).
*/
#define I915_EXEC_BATCH_FIRST (1<<18)
/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
* define an array of i915_gem_exec_fence structures which specify a set of
* dma fences to wait upon or signal.
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1318,16 +1277,14 @@ struct drm_i915_reg_read {
* be specified
*/
__u64 offset;
#define I915_REG_READ_8B_WA (1ul << 0)
__u64 val; /* Return value */
};
/* Known registers:
*
* Render engine timestamp - 0x2358 + 64bit - gen7+
* - Note this register returns an invalid value if using the default
* single instruction 8byte read, in order to workaround that pass
* flag I915_REG_READ_8B_WA in offset field.
* single instruction 8byte read, in order to workaround that use
* offset (0x2538 | 1) instead.
*
*/
@@ -1370,10 +1327,6 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
#define I915_CONTEXT_PARAM_BANNABLE 0x5
#define I915_CONTEXT_PARAM_PRIORITY 0x6
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
__u64 value;
};
@@ -1514,27 +1467,6 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
/**
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
char uuid[36];
__u32 n_mux_regs;
__u32 n_boolean_regs;
__u32 n_flex_regs;
/*
* These fields are pointers to tuples of u32 values (register
* address, value). For example the expected length of the buffer
* pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
*/
__u64 mux_regs_ptr;
__u64 boolean_regs_ptr;
__u64 flex_regs_ptr;
};
#if defined(__cplusplus)
}
#endif

View File

@@ -40,7 +40,6 @@ extern "C" {
#define DRM_VC4_GET_PARAM 0x07
#define DRM_VC4_SET_TILING 0x08
#define DRM_VC4_GET_TILING 0x09
#define DRM_VC4_LABEL_BO 0x0a
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -52,7 +51,6 @@ extern "C" {
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
struct drm_vc4_submit_rcl_surface {
__u32 hindex; /* Handle index, or ~0 if not present. */
@@ -155,16 +153,6 @@ struct drm_vc4_submit_cl {
__u32 pad:24;
#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
/* By default, the kernel gets to choose the order that the tiles are
* rendered in. If this is set, then the tiles will be rendered in a
* raster order, with the right-to-left vs left-to-right and
* top-to-bottom vs bottom-to-top dictated by
* VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
* blits to be implemented using the 3D engine.
*/
#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
__u32 flags;
/* Returned value of the seqno of this render job (for the
@@ -304,7 +292,6 @@ struct drm_vc4_get_hang_state {
#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
struct drm_vc4_get_param {
__u32 param;
@@ -324,15 +311,6 @@ struct drm_vc4_set_tiling {
__u64 modifier;
};
/**
* struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
*/
struct drm_vc4_label_bo {
__u32 handle;
__u32 len;
__u64 name;
};
#if defined(__cplusplus)
}
#endif

View File

@@ -1,68 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
inc_drm_uapi = include_directories('drm-uapi')
inc_vulkan = include_directories('vulkan')
if with_gles1
install_headers(
'GLES/egl.h', 'GLES/gl.h', 'GLES/glext.h', 'GLES/glplatform.h',
subdir : 'GLES',
)
endif
if with_gles2
install_headers(
'GLES2/gl2.h', 'GLES2/gl2ext.h', 'GLES2/gl2platform.h',
subdir : 'GLES2',
)
install_headers(
'GLES3/gl3.h', 'GLES3/gl32.h', 'GLES3/gl32.h', 'GLES3/gl3ext.h',
'GLES3/gl3platform.h',
subdir : 'GLES3',
)
endif
if with_gles1 or with_gles2 # or with_egl
install_headers('KHR/khrplatform.h', subdir : 'KHR')
endif
if with_opengl
install_headers(
'GL/gl.h', 'GL/glext.h', 'GL/glcorearb.h', 'GL/gl_mangle.h',
subdir : 'GL',
)
endif
if with_glx != 'disabled'
install_headers('GL/glx.h', 'GL/glext.h', 'GL/glx_mangle.h', subdir : 'GL')
endif
if with_osmesa
install_headers('GL/osmesa.h', subdir : 'GL')
endif
if with_egl
install_headers(
'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 'EGL/eglmesaext.h',
'EGL/eglplatform.h',
subdir : 'EGL',
)
endif

View File

@@ -151,7 +151,7 @@ CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1")
CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1")
CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
CHIPSET(0x5917, kbl_gt2, "Intel(R) UHD Graphics 620 (Kabylake GT2)")
CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5")
CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
@@ -160,8 +160,8 @@ CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")
CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3")
CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)")
CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3)")
CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")

View File

@@ -1,96 +0,0 @@
/*
* Copyright 2015 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VK_ANDROID_NATIVE_BUFFER_H__
#define __VK_ANDROID_NATIVE_BUFFER_H__
/* MESA: A hack to avoid #ifdefs in driver code. */
#ifdef ANDROID
#include <system/window.h>
#include <vulkan/vulkan.h>
#else
typedef void *buffer_handle_t;
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define VK_ANDROID_native_buffer 1
#define VK_ANDROID_NATIVE_BUFFER_EXTENSION_NUMBER 11
#define VK_ANDROID_NATIVE_BUFFER_SPEC_VERSION 5
#define VK_ANDROID_NATIVE_BUFFER_EXTENSION_NAME "VK_ANDROID_native_buffer"
#define VK_ANDROID_NATIVE_BUFFER_ENUM(type,id) ((type)(1000000000 + (1000 * (VK_ANDROID_NATIVE_BUFFER_EXTENSION_NUMBER - 1)) + (id)))
#define VK_STRUCTURE_TYPE_NATIVE_BUFFER_ANDROID VK_ANDROID_NATIVE_BUFFER_ENUM(VkStructureType, 0)
typedef struct {
VkStructureType sType; // must be VK_STRUCTURE_TYPE_NATIVE_BUFFER_ANDROID
const void* pNext;
// Buffer handle and stride returned from gralloc alloc()
buffer_handle_t handle;
int stride;
// Gralloc format and usage requested when the buffer was allocated.
int format;
int usage;
} VkNativeBufferANDROID;
typedef VkResult (VKAPI_PTR *PFN_vkGetSwapchainGrallocUsageANDROID)(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage);
typedef VkResult (VKAPI_PTR *PFN_vkAcquireImageANDROID)(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence);
typedef VkResult (VKAPI_PTR *PFN_vkQueueSignalReleaseImageANDROID)(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkGetSwapchainGrallocUsageANDROID(
VkDevice device,
VkFormat format,
VkImageUsageFlags imageUsage,
int* grallocUsage
);
VKAPI_ATTR VkResult VKAPI_CALL vkAcquireImageANDROID(
VkDevice device,
VkImage image,
int nativeFenceFd,
VkSemaphore semaphore,
VkFence fence
);
VKAPI_ATTR VkResult VKAPI_CALL vkQueueSignalReleaseImageANDROID(
VkQueue queue,
uint32_t waitSemaphoreCount,
const VkSemaphore* pWaitSemaphores,
VkImage image,
int* pNativeFenceFd
);
// -- DEPRECATED --
VKAPI_ATTR VkResult VKAPI_CALL vkImportNativeFenceANDROID(
VkDevice device,
VkSemaphore semaphore,
int nativeFenceFd
);
VKAPI_ATTR VkResult VKAPI_CALL vkQueueSignalNativeFenceANDROID(
VkQueue queue,
int* pNativeFenceFd
);
// ----------------
#endif
#ifdef __cplusplus
}
#endif
#endif // __VK_ANDROID_NATIVE_BUFFER_H__

View File

@@ -34,16 +34,16 @@ extern "C" {
(((major) << 22) | ((minor) << 12) | (patch))
// DEPRECATED: This define has been removed. Specific version defines (e.g. VK_API_VERSION_1_0), or the VK_MAKE_VERSION macro, should be used instead.
//#define VK_API_VERSION VK_MAKE_VERSION(1, 0, 0) // Patch version should always be set to 0
//#define VK_API_VERSION VK_MAKE_VERSION(1, 0, 0)
// Vulkan 1.0 version number
#define VK_API_VERSION_1_0 VK_MAKE_VERSION(1, 0, 0)// Patch version should always be set to 0
#define VK_API_VERSION_1_0 VK_MAKE_VERSION(1, 0, 0)
#define VK_VERSION_MAJOR(version) ((uint32_t)(version) >> 22)
#define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
#define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
// Version of this file
#define VK_HEADER_VERSION 63
#define VK_HEADER_VERSION 54
#define VK_NULL_HANDLE 0
@@ -147,7 +147,6 @@ typedef enum VkResult {
VK_ERROR_INVALID_SHADER_NV = -1000012000,
VK_ERROR_OUT_OF_POOL_MEMORY_KHR = -1000069000,
VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR = -1000072003,
VK_ERROR_NOT_PERMITTED_EXT = -1000174001,
VK_RESULT_BEGIN_RANGE = VK_ERROR_FRAGMENTED_POOL,
VK_RESULT_END_RANGE = VK_INCOMPLETE,
VK_RESULT_RANGE_SIZE = (VK_INCOMPLETE - VK_ERROR_FRAGMENTED_POOL + 1),
@@ -242,16 +241,16 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_SPARSE_IMAGE_FORMAT_PROPERTIES_2_KHR = 1000059007,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SPARSE_IMAGE_FORMAT_INFO_2_KHR = 1000059008,
VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_FLAGS_INFO_KHX = 1000060000,
VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHX = 1000060001,
VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_INFO_KHX = 1000060002,
VK_STRUCTURE_TYPE_DEVICE_GROUP_RENDER_PASS_BEGIN_INFO_KHX = 1000060003,
VK_STRUCTURE_TYPE_DEVICE_GROUP_COMMAND_BUFFER_BEGIN_INFO_KHX = 1000060004,
VK_STRUCTURE_TYPE_DEVICE_GROUP_SUBMIT_INFO_KHX = 1000060005,
VK_STRUCTURE_TYPE_DEVICE_GROUP_BIND_SPARSE_INFO_KHX = 1000060006,
VK_STRUCTURE_TYPE_ACQUIRE_NEXT_IMAGE_INFO_KHX = 1000060010,
VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_DEVICE_GROUP_INFO_KHX = 1000060013,
VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_DEVICE_GROUP_INFO_KHX = 1000060014,
VK_STRUCTURE_TYPE_DEVICE_GROUP_PRESENT_CAPABILITIES_KHX = 1000060007,
VK_STRUCTURE_TYPE_IMAGE_SWAPCHAIN_CREATE_INFO_KHX = 1000060008,
VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_SWAPCHAIN_INFO_KHX = 1000060009,
VK_STRUCTURE_TYPE_ACQUIRE_NEXT_IMAGE_INFO_KHX = 1000060010,
VK_STRUCTURE_TYPE_DEVICE_GROUP_PRESENT_INFO_KHX = 1000060011,
VK_STRUCTURE_TYPE_DEVICE_GROUP_SWAPCHAIN_CREATE_INFO_KHX = 1000060012,
VK_STRUCTURE_TYPE_VALIDATION_FLAGS_EXT = 1000061000,
@@ -294,7 +293,7 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_LIMITS_NVX = 1000086004,
VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_FEATURES_NVX = 1000086005,
VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_W_SCALING_STATE_CREATE_INFO_NV = 1000087000,
VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT = 1000090000,
VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT = 1000090000,
VK_STRUCTURE_TYPE_DISPLAY_POWER_INFO_EXT = 1000091000,
VK_STRUCTURE_TYPE_DEVICE_EVENT_INFO_EXT = 1000091001,
VK_STRUCTURE_TYPE_DISPLAY_EVENT_INFO_EXT = 1000091002,
@@ -314,10 +313,6 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_FENCE_GET_WIN32_HANDLE_INFO_KHR = 1000114002,
VK_STRUCTURE_TYPE_IMPORT_FENCE_FD_INFO_KHR = 1000115000,
VK_STRUCTURE_TYPE_FENCE_GET_FD_INFO_KHR = 1000115001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR = 1000117000,
VK_STRUCTURE_TYPE_RENDER_PASS_INPUT_ATTACHMENT_ASPECT_CREATE_INFO_KHR = 1000117001,
VK_STRUCTURE_TYPE_IMAGE_VIEW_USAGE_CREATE_INFO_KHR = 1000117002,
VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR = 1000117003,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SURFACE_INFO_2_KHR = 1000119000,
VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_KHR = 1000119001,
VK_STRUCTURE_TYPE_SURFACE_FORMAT_2_KHR = 1000119002,
@@ -328,33 +323,16 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_MEMORY_DEDICATED_ALLOCATE_INFO_KHR = 1000127001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT = 1000130000,
VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT = 1000130001,
VK_STRUCTURE_TYPE_SAMPLE_LOCATIONS_INFO_EXT = 1000143000,
VK_STRUCTURE_TYPE_RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT = 1000143001,
VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT = 1000143002,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT = 1000143003,
VK_STRUCTURE_TYPE_MULTISAMPLE_PROPERTIES_EXT = 1000143004,
VK_STRUCTURE_TYPE_BUFFER_MEMORY_REQUIREMENTS_INFO_2_KHR = 1000146000,
VK_STRUCTURE_TYPE_IMAGE_MEMORY_REQUIREMENTS_INFO_2_KHR = 1000146001,
VK_STRUCTURE_TYPE_IMAGE_SPARSE_MEMORY_REQUIREMENTS_INFO_2_KHR = 1000146002,
VK_STRUCTURE_TYPE_MEMORY_REQUIREMENTS_2_KHR = 1000146003,
VK_STRUCTURE_TYPE_SPARSE_IMAGE_MEMORY_REQUIREMENTS_2_KHR = 1000146004,
VK_STRUCTURE_TYPE_IMAGE_FORMAT_LIST_CREATE_INFO_KHR = 1000147000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BLEND_OPERATION_ADVANCED_FEATURES_EXT = 1000148000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BLEND_OPERATION_ADVANCED_PROPERTIES_EXT = 1000148001,
VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_ADVANCED_STATE_CREATE_INFO_EXT = 1000148002,
VK_STRUCTURE_TYPE_PIPELINE_COVERAGE_TO_COLOR_STATE_CREATE_INFO_NV = 1000149000,
VK_STRUCTURE_TYPE_PIPELINE_COVERAGE_MODULATION_STATE_CREATE_INFO_NV = 1000152000,
VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_CREATE_INFO_KHR = 1000156000,
VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO_KHR = 1000156001,
VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR = 1000156002,
VK_STRUCTURE_TYPE_IMAGE_PLANE_MEMORY_REQUIREMENTS_INFO_KHR = 1000156003,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES_KHR = 1000156004,
VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_IMAGE_FORMAT_PROPERTIES_KHR = 1000156005,
VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR = 1000157000,
VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_INFO_KHR = 1000157001,
VK_STRUCTURE_TYPE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160000,
VK_STRUCTURE_TYPE_SHADER_MODULE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160001,
VK_STRUCTURE_TYPE_DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT = 1000174000,
VK_STRUCTURE_TYPE_BEGIN_RANGE = VK_STRUCTURE_TYPE_APPLICATION_INFO,
VK_STRUCTURE_TYPE_END_RANGE = VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO,
VK_STRUCTURE_TYPE_RANGE_SIZE = (VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO - VK_STRUCTURE_TYPE_APPLICATION_INFO + 1),
@@ -575,40 +553,6 @@ typedef enum VkFormat {
VK_FORMAT_PVRTC1_4BPP_SRGB_BLOCK_IMG = 1000054005,
VK_FORMAT_PVRTC2_2BPP_SRGB_BLOCK_IMG = 1000054006,
VK_FORMAT_PVRTC2_4BPP_SRGB_BLOCK_IMG = 1000054007,
VK_FORMAT_G8B8G8R8_422_UNORM_KHR = 1000156000,
VK_FORMAT_B8G8R8G8_422_UNORM_KHR = 1000156001,
VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR = 1000156002,
VK_FORMAT_G8_B8R8_2PLANE_420_UNORM_KHR = 1000156003,
VK_FORMAT_G8_B8_R8_3PLANE_422_UNORM_KHR = 1000156004,
VK_FORMAT_G8_B8R8_2PLANE_422_UNORM_KHR = 1000156005,
VK_FORMAT_G8_B8_R8_3PLANE_444_UNORM_KHR = 1000156006,
VK_FORMAT_R10X6_UNORM_PACK16_KHR = 1000156007,
VK_FORMAT_R10X6G10X6_UNORM_2PACK16_KHR = 1000156008,
VK_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16_KHR = 1000156009,
VK_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16_KHR = 1000156010,
VK_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16_KHR = 1000156011,
VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_420_UNORM_3PACK16_KHR = 1000156012,
VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16_KHR = 1000156013,
VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_422_UNORM_3PACK16_KHR = 1000156014,
VK_FORMAT_G10X6_B10X6R10X6_2PLANE_422_UNORM_3PACK16_KHR = 1000156015,
VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_444_UNORM_3PACK16_KHR = 1000156016,
VK_FORMAT_R12X4_UNORM_PACK16_KHR = 1000156017,
VK_FORMAT_R12X4G12X4_UNORM_2PACK16_KHR = 1000156018,
VK_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16_KHR = 1000156019,
VK_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16_KHR = 1000156020,
VK_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16_KHR = 1000156021,
VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_420_UNORM_3PACK16_KHR = 1000156022,
VK_FORMAT_G12X4_B12X4R12X4_2PLANE_420_UNORM_3PACK16_KHR = 1000156023,
VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_422_UNORM_3PACK16_KHR = 1000156024,
VK_FORMAT_G12X4_B12X4R12X4_2PLANE_422_UNORM_3PACK16_KHR = 1000156025,
VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_444_UNORM_3PACK16_KHR = 1000156026,
VK_FORMAT_G16B16G16R16_422_UNORM_KHR = 1000156027,
VK_FORMAT_B16G16R16G16_422_UNORM_KHR = 1000156028,
VK_FORMAT_G16_B16_R16_3PLANE_420_UNORM_KHR = 1000156029,
VK_FORMAT_G16_B16R16_2PLANE_420_UNORM_KHR = 1000156030,
VK_FORMAT_G16_B16_R16_3PLANE_422_UNORM_KHR = 1000156031,
VK_FORMAT_G16_B16R16_2PLANE_422_UNORM_KHR = 1000156032,
VK_FORMAT_G16_B16_R16_3PLANE_444_UNORM_KHR = 1000156033,
VK_FORMAT_BEGIN_RANGE = VK_FORMAT_UNDEFINED,
VK_FORMAT_END_RANGE = VK_FORMAT_ASTC_12x12_SRGB_BLOCK,
VK_FORMAT_RANGE_SIZE = (VK_FORMAT_ASTC_12x12_SRGB_BLOCK - VK_FORMAT_UNDEFINED + 1),
@@ -677,8 +621,6 @@ typedef enum VkImageLayout {
VK_IMAGE_LAYOUT_PREINITIALIZED = 8,
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR = 1000001002,
VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR = 1000111000,
VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR = 1000117000,
VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR = 1000117001,
VK_IMAGE_LAYOUT_BEGIN_RANGE = VK_IMAGE_LAYOUT_UNDEFINED,
VK_IMAGE_LAYOUT_END_RANGE = VK_IMAGE_LAYOUT_PREINITIALIZED,
VK_IMAGE_LAYOUT_RANGE_SIZE = (VK_IMAGE_LAYOUT_PREINITIALIZED - VK_IMAGE_LAYOUT_UNDEFINED + 1),
@@ -909,7 +851,6 @@ typedef enum VkDynamicState {
VK_DYNAMIC_STATE_STENCIL_REFERENCE = 8,
VK_DYNAMIC_STATE_VIEWPORT_W_SCALING_NV = 1000087000,
VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 1000099000,
VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT = 1000143000,
VK_DYNAMIC_STATE_BEGIN_RANGE = VK_DYNAMIC_STATE_VIEWPORT,
VK_DYNAMIC_STATE_END_RANGE = VK_DYNAMIC_STATE_STENCIL_REFERENCE,
VK_DYNAMIC_STATE_RANGE_SIZE = (VK_DYNAMIC_STATE_STENCIL_REFERENCE - VK_DYNAMIC_STATE_VIEWPORT + 1),
@@ -1068,8 +1009,6 @@ typedef enum VkObjectType {
VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_KHR = 1000085000,
VK_OBJECT_TYPE_OBJECT_TABLE_NVX = 1000086000,
VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX = 1000086001,
VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION_KHR = 1000156000,
VK_OBJECT_TYPE_VALIDATION_CACHE_EXT = 1000160000,
VK_OBJECT_TYPE_BEGIN_RANGE = VK_OBJECT_TYPE_UNKNOWN,
VK_OBJECT_TYPE_END_RANGE = VK_OBJECT_TYPE_COMMAND_POOL,
VK_OBJECT_TYPE_RANGE_SIZE = (VK_OBJECT_TYPE_COMMAND_POOL - VK_OBJECT_TYPE_UNKNOWN + 1),
@@ -1096,13 +1035,6 @@ typedef enum VkFormatFeatureFlagBits {
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR = 0x00004000,
VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR = 0x00008000,
VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT = 0x00010000,
VK_FORMAT_FEATURE_MIDPOINT_CHROMA_SAMPLES_BIT_KHR = 0x00020000,
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT_KHR = 0x00040000,
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT_KHR = 0x00080000,
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_CHROMA_RECONSTRUCTION_EXPLICIT_BIT_KHR = 0x00100000,
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_CHROMA_RECONSTRUCTION_EXPLICIT_FORCEABLE_BIT_KHR = 0x00200000,
VK_FORMAT_FEATURE_DISJOINT_BIT_KHR = 0x00400000,
VK_FORMAT_FEATURE_COSITED_CHROMA_SAMPLES_BIT_KHR = 0x00800000,
VK_FORMAT_FEATURE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} VkFormatFeatureFlagBits;
typedef VkFlags VkFormatFeatureFlags;
@@ -1128,11 +1060,6 @@ typedef enum VkImageCreateFlagBits {
VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT = 0x00000010,
VK_IMAGE_CREATE_BIND_SFR_BIT_KHX = 0x00000040,
VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT_KHR = 0x00000020,
VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR = 0x00000080,
VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR = 0x00000100,
VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT = 0x00001000,
VK_IMAGE_CREATE_DISJOINT_BIT_KHR = 0x00000200,
VK_IMAGE_CREATE_ALIAS_BIT_KHR = 0x00000400,
VK_IMAGE_CREATE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} VkImageCreateFlagBits;
typedef VkFlags VkImageCreateFlags;
@@ -1206,9 +1133,6 @@ typedef enum VkImageAspectFlagBits {
VK_IMAGE_ASPECT_DEPTH_BIT = 0x00000002,
VK_IMAGE_ASPECT_STENCIL_BIT = 0x00000004,
VK_IMAGE_ASPECT_METADATA_BIT = 0x00000008,
VK_IMAGE_ASPECT_PLANE_0_BIT_KHR = 0x00000010,
VK_IMAGE_ASPECT_PLANE_1_BIT_KHR = 0x00000020,
VK_IMAGE_ASPECT_PLANE_2_BIT_KHR = 0x00000040,
VK_IMAGE_ASPECT_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} VkImageAspectFlagBits;
typedef VkFlags VkImageAspectFlags;
@@ -1442,27 +1366,6 @@ typedef enum VkStencilFaceFlagBits {
} VkStencilFaceFlagBits;
typedef VkFlags VkStencilFaceFlags;
typedef struct VkApplicationInfo {
VkStructureType sType;
const void* pNext;
const char* pApplicationName;
uint32_t applicationVersion;
const char* pEngineName;
uint32_t engineVersion;
uint32_t apiVersion;
} VkApplicationInfo;
typedef struct VkInstanceCreateInfo {
VkStructureType sType;
const void* pNext;
VkInstanceCreateFlags flags;
const VkApplicationInfo* pApplicationInfo;
uint32_t enabledLayerCount;
const char* const* ppEnabledLayerNames;
uint32_t enabledExtensionCount;
const char* const* ppEnabledExtensionNames;
} VkInstanceCreateInfo;
typedef void* (VKAPI_PTR *PFN_vkAllocationFunction)(
void* pUserData,
size_t size,
@@ -1492,6 +1395,29 @@ typedef void (VKAPI_PTR *PFN_vkInternalFreeNotification)(
VkInternalAllocationType allocationType,
VkSystemAllocationScope allocationScope);
typedef void (VKAPI_PTR *PFN_vkVoidFunction)(void);
typedef struct VkApplicationInfo {
VkStructureType sType;
const void* pNext;
const char* pApplicationName;
uint32_t applicationVersion;
const char* pEngineName;
uint32_t engineVersion;
uint32_t apiVersion;
} VkApplicationInfo;
typedef struct VkInstanceCreateInfo {
VkStructureType sType;
const void* pNext;
VkInstanceCreateFlags flags;
const VkApplicationInfo* pApplicationInfo;
uint32_t enabledLayerCount;
const char* const* ppEnabledLayerNames;
uint32_t enabledExtensionCount;
const char* const* ppEnabledExtensionNames;
} VkInstanceCreateInfo;
typedef struct VkAllocationCallbacks {
void* pUserData;
PFN_vkAllocationFunction pfnAllocation;
@@ -1732,7 +1658,6 @@ typedef struct VkPhysicalDeviceMemoryProperties {
VkMemoryHeap memoryHeaps[VK_MAX_MEMORY_HEAPS];
} VkPhysicalDeviceMemoryProperties;
typedef void (VKAPI_PTR *PFN_vkVoidFunction)(void);
typedef struct VkDeviceQueueCreateInfo {
VkStructureType sType;
const void* pNext;
@@ -3508,7 +3433,6 @@ typedef enum VkColorSpaceKHR {
VK_COLOR_SPACE_ADOBERGB_LINEAR_EXT = 1000104011,
VK_COLOR_SPACE_ADOBERGB_NONLINEAR_EXT = 1000104012,
VK_COLOR_SPACE_PASS_THROUGH_EXT = 1000104013,
VK_COLOR_SPACE_EXTENDED_SRGB_NONLINEAR_EXT = 1000104014,
VK_COLOR_SPACE_BEGIN_RANGE_KHR = VK_COLOR_SPACE_SRGB_NONLINEAR_KHR,
VK_COLOR_SPACE_END_RANGE_KHR = VK_COLOR_SPACE_SRGB_NONLINEAR_KHR,
VK_COLOR_SPACE_RANGE_SIZE_KHR = (VK_COLOR_SPACE_SRGB_NONLINEAR_KHR - VK_COLOR_SPACE_SRGB_NONLINEAR_KHR + 1),
@@ -4850,62 +4774,6 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetFenceFdKHR(
int* pFd);
#endif
#define VK_KHR_maintenance2 1
#define VK_KHR_MAINTENANCE2_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE2_EXTENSION_NAME "VK_KHR_maintenance2"
typedef enum VkPointClippingBehaviorKHR {
VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR = 0,
VK_POINT_CLIPPING_BEHAVIOR_USER_CLIP_PLANES_ONLY_KHR = 1,
VK_POINT_CLIPPING_BEHAVIOR_BEGIN_RANGE_KHR = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR,
VK_POINT_CLIPPING_BEHAVIOR_END_RANGE_KHR = VK_POINT_CLIPPING_BEHAVIOR_USER_CLIP_PLANES_ONLY_KHR,
VK_POINT_CLIPPING_BEHAVIOR_RANGE_SIZE_KHR = (VK_POINT_CLIPPING_BEHAVIOR_USER_CLIP_PLANES_ONLY_KHR - VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR + 1),
VK_POINT_CLIPPING_BEHAVIOR_MAX_ENUM_KHR = 0x7FFFFFFF
} VkPointClippingBehaviorKHR;
typedef enum VkTessellationDomainOriginKHR {
VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR = 0,
VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT_KHR = 1,
VK_TESSELLATION_DOMAIN_ORIGIN_BEGIN_RANGE_KHR = VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR,
VK_TESSELLATION_DOMAIN_ORIGIN_END_RANGE_KHR = VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT_KHR,
VK_TESSELLATION_DOMAIN_ORIGIN_RANGE_SIZE_KHR = (VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT_KHR - VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR + 1),
VK_TESSELLATION_DOMAIN_ORIGIN_MAX_ENUM_KHR = 0x7FFFFFFF
} VkTessellationDomainOriginKHR;
typedef struct VkPhysicalDevicePointClippingPropertiesKHR {
VkStructureType sType;
void* pNext;
VkPointClippingBehaviorKHR pointClippingBehavior;
} VkPhysicalDevicePointClippingPropertiesKHR;
typedef struct VkInputAttachmentAspectReferenceKHR {
uint32_t subpass;
uint32_t inputAttachmentIndex;
VkImageAspectFlags aspectMask;
} VkInputAttachmentAspectReferenceKHR;
typedef struct VkRenderPassInputAttachmentAspectCreateInfoKHR {
VkStructureType sType;
const void* pNext;
uint32_t aspectReferenceCount;
const VkInputAttachmentAspectReferenceKHR* pAspectReferences;
} VkRenderPassInputAttachmentAspectCreateInfoKHR;
typedef struct VkImageViewUsageCreateInfoKHR {
VkStructureType sType;
const void* pNext;
VkImageUsageFlags usage;
} VkImageViewUsageCreateInfoKHR;
typedef struct VkPipelineTessellationDomainOriginStateCreateInfoKHR {
VkStructureType sType;
const void* pNext;
VkTessellationDomainOriginKHR domainOrigin;
} VkPipelineTessellationDomainOriginStateCreateInfoKHR;
#define VK_KHR_get_surface_capabilities2 1
#define VK_KHR_GET_SURFACE_CAPABILITIES_2_SPEC_VERSION 1
#define VK_KHR_GET_SURFACE_CAPABILITIES_2_EXTENSION_NAME "VK_KHR_get_surface_capabilities2"
@@ -4959,7 +4827,7 @@ typedef struct VkPhysicalDeviceVariablePointerFeaturesKHR {
#define VK_KHR_dedicated_allocation 1
#define VK_KHR_DEDICATED_ALLOCATION_SPEC_VERSION 3
#define VK_KHR_DEDICATED_ALLOCATION_SPEC_VERSION 1
#define VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME "VK_KHR_dedicated_allocation"
typedef struct VkMemoryDedicatedRequirementsKHR {
@@ -4983,11 +4851,6 @@ typedef struct VkMemoryDedicatedAllocateInfoKHR {
#define VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME "VK_KHR_storage_buffer_storage_class"
#define VK_KHR_relaxed_block_layout 1
#define VK_KHR_RELAXED_BLOCK_LAYOUT_SPEC_VERSION 1
#define VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME "VK_KHR_relaxed_block_layout"
#define VK_KHR_get_memory_requirements2 1
#define VK_KHR_GET_MEMORY_REQUIREMENTS_2_SPEC_VERSION 1
#define VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME "VK_KHR_get_memory_requirements2"
@@ -5045,152 +4908,6 @@ VKAPI_ATTR void VKAPI_CALL vkGetImageSparseMemoryRequirements2KHR(
VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements);
#endif
#define VK_KHR_image_format_list 1
#define VK_KHR_IMAGE_FORMAT_LIST_SPEC_VERSION 1
#define VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME "VK_KHR_image_format_list"
typedef struct VkImageFormatListCreateInfoKHR {
VkStructureType sType;
const void* pNext;
uint32_t viewFormatCount;
const VkFormat* pViewFormats;
} VkImageFormatListCreateInfoKHR;
#define VK_KHR_sampler_ycbcr_conversion 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkSamplerYcbcrConversionKHR)
#define VK_KHR_SAMPLER_YCBCR_CONVERSION_SPEC_VERSION 1
#define VK_KHR_SAMPLER_YCBCR_CONVERSION_EXTENSION_NAME "VK_KHR_sampler_ycbcr_conversion"
typedef enum VkSamplerYcbcrModelConversionKHR {
VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY_KHR = 0,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_IDENTITY_KHR = 1,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_709_KHR = 2,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_601_KHR = 3,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_2020_KHR = 4,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_BEGIN_RANGE_KHR = VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY_KHR,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_END_RANGE_KHR = VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_2020_KHR,
VK_SAMPLER_YCBCR_MODEL_CONVERSION_RANGE_SIZE_KHR = (VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_2020_KHR - VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY_KHR + 1),
VK_SAMPLER_YCBCR_MODEL_CONVERSION_MAX_ENUM_KHR = 0x7FFFFFFF
} VkSamplerYcbcrModelConversionKHR;
typedef enum VkSamplerYcbcrRangeKHR {
VK_SAMPLER_YCBCR_RANGE_ITU_FULL_KHR = 0,
VK_SAMPLER_YCBCR_RANGE_ITU_NARROW_KHR = 1,
VK_SAMPLER_YCBCR_RANGE_BEGIN_RANGE_KHR = VK_SAMPLER_YCBCR_RANGE_ITU_FULL_KHR,
VK_SAMPLER_YCBCR_RANGE_END_RANGE_KHR = VK_SAMPLER_YCBCR_RANGE_ITU_NARROW_KHR,
VK_SAMPLER_YCBCR_RANGE_RANGE_SIZE_KHR = (VK_SAMPLER_YCBCR_RANGE_ITU_NARROW_KHR - VK_SAMPLER_YCBCR_RANGE_ITU_FULL_KHR + 1),
VK_SAMPLER_YCBCR_RANGE_MAX_ENUM_KHR = 0x7FFFFFFF
} VkSamplerYcbcrRangeKHR;
typedef enum VkChromaLocationKHR {
VK_CHROMA_LOCATION_COSITED_EVEN_KHR = 0,
VK_CHROMA_LOCATION_MIDPOINT_KHR = 1,
VK_CHROMA_LOCATION_BEGIN_RANGE_KHR = VK_CHROMA_LOCATION_COSITED_EVEN_KHR,
VK_CHROMA_LOCATION_END_RANGE_KHR = VK_CHROMA_LOCATION_MIDPOINT_KHR,
VK_CHROMA_LOCATION_RANGE_SIZE_KHR = (VK_CHROMA_LOCATION_MIDPOINT_KHR - VK_CHROMA_LOCATION_COSITED_EVEN_KHR + 1),
VK_CHROMA_LOCATION_MAX_ENUM_KHR = 0x7FFFFFFF
} VkChromaLocationKHR;
typedef struct VkSamplerYcbcrConversionCreateInfoKHR {
VkStructureType sType;
const void* pNext;
VkFormat format;
VkSamplerYcbcrModelConversionKHR ycbcrModel;
VkSamplerYcbcrRangeKHR ycbcrRange;
VkComponentMapping components;
VkChromaLocationKHR xChromaOffset;
VkChromaLocationKHR yChromaOffset;
VkFilter chromaFilter;
VkBool32 forceExplicitReconstruction;
} VkSamplerYcbcrConversionCreateInfoKHR;
typedef struct VkSamplerYcbcrConversionInfoKHR {
VkStructureType sType;
const void* pNext;
VkSamplerYcbcrConversionKHR conversion;
} VkSamplerYcbcrConversionInfoKHR;
typedef struct VkBindImagePlaneMemoryInfoKHR {
VkStructureType sType;
const void* pNext;
VkImageAspectFlagBits planeAspect;
} VkBindImagePlaneMemoryInfoKHR;
typedef struct VkImagePlaneMemoryRequirementsInfoKHR {
VkStructureType sType;
const void* pNext;
VkImageAspectFlagBits planeAspect;
} VkImagePlaneMemoryRequirementsInfoKHR;
typedef struct VkPhysicalDeviceSamplerYcbcrConversionFeaturesKHR {
VkStructureType sType;
void* pNext;
VkBool32 samplerYcbcrConversion;
} VkPhysicalDeviceSamplerYcbcrConversionFeaturesKHR;
typedef struct VkSamplerYcbcrConversionImageFormatPropertiesKHR {
VkStructureType sType;
void* pNext;
uint32_t combinedImageSamplerDescriptorCount;
} VkSamplerYcbcrConversionImageFormatPropertiesKHR;
typedef VkResult (VKAPI_PTR *PFN_vkCreateSamplerYcbcrConversionKHR)(VkDevice device, const VkSamplerYcbcrConversionCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversionKHR* pYcbcrConversion);
typedef void (VKAPI_PTR *PFN_vkDestroySamplerYcbcrConversionKHR)(VkDevice device, VkSamplerYcbcrConversionKHR ycbcrConversion, const VkAllocationCallbacks* pAllocator);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkCreateSamplerYcbcrConversionKHR(
VkDevice device,
const VkSamplerYcbcrConversionCreateInfoKHR* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkSamplerYcbcrConversionKHR* pYcbcrConversion);
VKAPI_ATTR void VKAPI_CALL vkDestroySamplerYcbcrConversionKHR(
VkDevice device,
VkSamplerYcbcrConversionKHR ycbcrConversion,
const VkAllocationCallbacks* pAllocator);
#endif
#define VK_KHR_bind_memory2 1
#define VK_KHR_BIND_MEMORY_2_SPEC_VERSION 1
#define VK_KHR_BIND_MEMORY_2_EXTENSION_NAME "VK_KHR_bind_memory2"
typedef struct VkBindBufferMemoryInfoKHR {
VkStructureType sType;
const void* pNext;
VkBuffer buffer;
VkDeviceMemory memory;
VkDeviceSize memoryOffset;
} VkBindBufferMemoryInfoKHR;
typedef struct VkBindImageMemoryInfoKHR {
VkStructureType sType;
const void* pNext;
VkImage image;
VkDeviceMemory memory;
VkDeviceSize memoryOffset;
} VkBindImageMemoryInfoKHR;
typedef VkResult (VKAPI_PTR *PFN_vkBindBufferMemory2KHR)(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfoKHR* pBindInfos);
typedef VkResult (VKAPI_PTR *PFN_vkBindImageMemory2KHR)(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfoKHR* pBindInfos);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkBindBufferMemory2KHR(
VkDevice device,
uint32_t bindInfoCount,
const VkBindBufferMemoryInfoKHR* pBindInfos);
VKAPI_ATTR VkResult VKAPI_CALL vkBindImageMemory2KHR(
VkDevice device,
uint32_t bindInfoCount,
const VkBindImageMemoryInfoKHR* pBindInfos);
#endif
#define VK_EXT_debug_report 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkDebugReportCallbackEXT)
@@ -5234,12 +4951,10 @@ typedef enum VkDebugReportObjectTypeEXT {
VK_DEBUG_REPORT_OBJECT_TYPE_DISPLAY_MODE_KHR_EXT = 30,
VK_DEBUG_REPORT_OBJECT_TYPE_OBJECT_TABLE_NVX_EXT = 31,
VK_DEBUG_REPORT_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX_EXT = 32,
VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT = 33,
VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_KHR_EXT = 1000085000,
VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION_KHR_EXT = 1000156000,
VK_DEBUG_REPORT_OBJECT_TYPE_BEGIN_RANGE_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,
VK_DEBUG_REPORT_OBJECT_TYPE_END_RANGE_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT,
VK_DEBUG_REPORT_OBJECT_TYPE_RANGE_SIZE_EXT = (VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT - VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT + 1),
VK_DEBUG_REPORT_OBJECT_TYPE_END_RANGE_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX_EXT,
VK_DEBUG_REPORT_OBJECT_TYPE_RANGE_SIZE_EXT = (VK_DEBUG_REPORT_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX_EXT - VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT + 1),
VK_DEBUG_REPORT_OBJECT_TYPE_MAX_ENUM_EXT = 0x7FFFFFFF
} VkDebugReportObjectTypeEXT;
@@ -5264,6 +4979,7 @@ typedef VkBool32 (VKAPI_PTR *PFN_vkDebugReportCallbackEXT)(
const char* pMessage,
void* pUserData);
typedef struct VkDebugReportCallbackCreateInfoEXT {
VkStructureType sType;
const void* pNext;
@@ -5305,11 +5021,6 @@ VKAPI_ATTR void VKAPI_CALL vkDebugReportMessageEXT(
#define VK_NV_GLSL_SHADER_EXTENSION_NAME "VK_NV_glsl_shader"
#define VK_EXT_depth_range_unrestricted 1
#define VK_EXT_DEPTH_RANGE_UNRESTRICTED_SPEC_VERSION 1
#define VK_EXT_DEPTH_RANGE_UNRESTRICTED_EXTENSION_NAME "VK_EXT_depth_range_unrestricted"
#define VK_IMG_filter_cubic 1
#define VK_IMG_FILTER_CUBIC_SPEC_VERSION 1
#define VK_IMG_FILTER_CUBIC_EXTENSION_NAME "VK_IMG_filter_cubic"
@@ -5377,31 +5088,31 @@ typedef struct VkDebugMarkerMarkerInfoEXT {
} VkDebugMarkerMarkerInfoEXT;
typedef VkResult (VKAPI_PTR *PFN_vkDebugMarkerSetObjectTagEXT)(VkDevice device, const VkDebugMarkerObjectTagInfoEXT* pTagInfo);
typedef VkResult (VKAPI_PTR *PFN_vkDebugMarkerSetObjectNameEXT)(VkDevice device, const VkDebugMarkerObjectNameInfoEXT* pNameInfo);
typedef void (VKAPI_PTR *PFN_vkCmdDebugMarkerBeginEXT)(VkCommandBuffer commandBuffer, const VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
typedef VkResult (VKAPI_PTR *PFN_vkDebugMarkerSetObjectTagEXT)(VkDevice device, VkDebugMarkerObjectTagInfoEXT* pTagInfo);
typedef VkResult (VKAPI_PTR *PFN_vkDebugMarkerSetObjectNameEXT)(VkDevice device, VkDebugMarkerObjectNameInfoEXT* pNameInfo);
typedef void (VKAPI_PTR *PFN_vkCmdDebugMarkerBeginEXT)(VkCommandBuffer commandBuffer, VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
typedef void (VKAPI_PTR *PFN_vkCmdDebugMarkerEndEXT)(VkCommandBuffer commandBuffer);
typedef void (VKAPI_PTR *PFN_vkCmdDebugMarkerInsertEXT)(VkCommandBuffer commandBuffer, const VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
typedef void (VKAPI_PTR *PFN_vkCmdDebugMarkerInsertEXT)(VkCommandBuffer commandBuffer, VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkDebugMarkerSetObjectTagEXT(
VkDevice device,
const VkDebugMarkerObjectTagInfoEXT* pTagInfo);
VkDebugMarkerObjectTagInfoEXT* pTagInfo);
VKAPI_ATTR VkResult VKAPI_CALL vkDebugMarkerSetObjectNameEXT(
VkDevice device,
const VkDebugMarkerObjectNameInfoEXT* pNameInfo);
VkDebugMarkerObjectNameInfoEXT* pNameInfo);
VKAPI_ATTR void VKAPI_CALL vkCmdDebugMarkerBeginEXT(
VkCommandBuffer commandBuffer,
const VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
VKAPI_ATTR void VKAPI_CALL vkCmdDebugMarkerEndEXT(
VkCommandBuffer commandBuffer);
VKAPI_ATTR void VKAPI_CALL vkCmdDebugMarkerInsertEXT(
VkCommandBuffer commandBuffer,
const VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
VkDebugMarkerMarkerInfoEXT* pMarkerInfo);
#endif
#define VK_AMD_gcn_shader 1
@@ -5488,11 +5199,6 @@ typedef struct VkTextureLODGatherFormatPropertiesAMD {
#define VK_AMD_shader_image_load_store_lod 1
#define VK_AMD_SHADER_IMAGE_LOAD_STORE_LOD_SPEC_VERSION 1
#define VK_AMD_SHADER_IMAGE_LOAD_STORE_LOD_EXTENSION_NAME "VK_AMD_shader_image_load_store_lod"
#define VK_KHX_multiview 1
#define VK_KHX_MULTIVIEW_SPEC_VERSION 1
#define VK_KHX_MULTIVIEW_EXTENSION_NAME "VK_KHX_multiview"
@@ -5644,9 +5350,9 @@ typedef struct VkWin32KeyedMutexAcquireReleaseInfoNV {
#endif /* VK_USE_PLATFORM_WIN32_KHR */
#define VK_KHX_device_group 1
#define VK_KHX_DEVICE_GROUP_SPEC_VERSION 2
#define VK_KHX_DEVICE_GROUP_EXTENSION_NAME "VK_KHX_device_group"
#define VK_MAX_DEVICE_GROUP_SIZE_KHX 32
#define VK_KHX_DEVICE_GROUP_SPEC_VERSION 1
#define VK_KHX_DEVICE_GROUP_EXTENSION_NAME "VK_KHX_device_group"
typedef enum VkPeerMemoryFeatureFlagBitsKHX {
@@ -5680,6 +5386,28 @@ typedef struct VkMemoryAllocateFlagsInfoKHX {
uint32_t deviceMask;
} VkMemoryAllocateFlagsInfoKHX;
typedef struct VkBindBufferMemoryInfoKHX {
VkStructureType sType;
const void* pNext;
VkBuffer buffer;
VkDeviceMemory memory;
VkDeviceSize memoryOffset;
uint32_t deviceIndexCount;
const uint32_t* pDeviceIndices;
} VkBindBufferMemoryInfoKHX;
typedef struct VkBindImageMemoryInfoKHX {
VkStructureType sType;
const void* pNext;
VkImage image;
VkDeviceMemory memory;
VkDeviceSize memoryOffset;
uint32_t deviceIndexCount;
const uint32_t* pDeviceIndices;
uint32_t SFRRectCount;
const VkRect2D* pSFRRects;
} VkBindImageMemoryInfoKHX;
typedef struct VkDeviceGroupRenderPassBeginInfoKHX {
VkStructureType sType;
const void* pNext;
@@ -5712,22 +5440,6 @@ typedef struct VkDeviceGroupBindSparseInfoKHX {
uint32_t memoryDeviceIndex;
} VkDeviceGroupBindSparseInfoKHX;
typedef struct VkBindBufferMemoryDeviceGroupInfoKHX {
VkStructureType sType;
const void* pNext;
uint32_t deviceIndexCount;
const uint32_t* pDeviceIndices;
} VkBindBufferMemoryDeviceGroupInfoKHX;
typedef struct VkBindImageMemoryDeviceGroupInfoKHX {
VkStructureType sType;
const void* pNext;
uint32_t deviceIndexCount;
const uint32_t* pDeviceIndices;
uint32_t SFRRectCount;
const VkRect2D* pSFRRects;
} VkBindImageMemoryDeviceGroupInfoKHX;
typedef struct VkDeviceGroupPresentCapabilitiesKHX {
VkStructureType sType;
const void* pNext;
@@ -5774,12 +5486,14 @@ typedef struct VkDeviceGroupSwapchainCreateInfoKHX {
typedef void (VKAPI_PTR *PFN_vkGetDeviceGroupPeerMemoryFeaturesKHX)(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlagsKHX* pPeerMemoryFeatures);
typedef VkResult (VKAPI_PTR *PFN_vkBindBufferMemory2KHX)(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfoKHX* pBindInfos);
typedef VkResult (VKAPI_PTR *PFN_vkBindImageMemory2KHX)(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfoKHX* pBindInfos);
typedef void (VKAPI_PTR *PFN_vkCmdSetDeviceMaskKHX)(VkCommandBuffer commandBuffer, uint32_t deviceMask);
typedef void (VKAPI_PTR *PFN_vkCmdDispatchBaseKHX)(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ);
typedef VkResult (VKAPI_PTR *PFN_vkGetDeviceGroupPresentCapabilitiesKHX)(VkDevice device, VkDeviceGroupPresentCapabilitiesKHX* pDeviceGroupPresentCapabilities);
typedef VkResult (VKAPI_PTR *PFN_vkGetDeviceGroupSurfacePresentModesKHX)(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHX* pModes);
typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDevicePresentRectanglesKHX)(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pRectCount, VkRect2D* pRects);
typedef VkResult (VKAPI_PTR *PFN_vkAcquireNextImage2KHX)(VkDevice device, const VkAcquireNextImageInfoKHX* pAcquireInfo, uint32_t* pImageIndex);
typedef void (VKAPI_PTR *PFN_vkCmdDispatchBaseKHX)(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ);
typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDevicePresentRectanglesKHX)(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pRectCount, VkRect2D* pRects);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR void VKAPI_CALL vkGetDeviceGroupPeerMemoryFeaturesKHX(
@@ -5789,19 +5503,20 @@ VKAPI_ATTR void VKAPI_CALL vkGetDeviceGroupPeerMemoryFeaturesKHX(
uint32_t remoteDeviceIndex,
VkPeerMemoryFeatureFlagsKHX* pPeerMemoryFeatures);
VKAPI_ATTR VkResult VKAPI_CALL vkBindBufferMemory2KHX(
VkDevice device,
uint32_t bindInfoCount,
const VkBindBufferMemoryInfoKHX* pBindInfos);
VKAPI_ATTR VkResult VKAPI_CALL vkBindImageMemory2KHX(
VkDevice device,
uint32_t bindInfoCount,
const VkBindImageMemoryInfoKHX* pBindInfos);
VKAPI_ATTR void VKAPI_CALL vkCmdSetDeviceMaskKHX(
VkCommandBuffer commandBuffer,
uint32_t deviceMask);
VKAPI_ATTR void VKAPI_CALL vkCmdDispatchBaseKHX(
VkCommandBuffer commandBuffer,
uint32_t baseGroupX,
uint32_t baseGroupY,
uint32_t baseGroupZ,
uint32_t groupCountX,
uint32_t groupCountY,
uint32_t groupCountZ);
VKAPI_ATTR VkResult VKAPI_CALL vkGetDeviceGroupPresentCapabilitiesKHX(
VkDevice device,
VkDeviceGroupPresentCapabilitiesKHX* pDeviceGroupPresentCapabilities);
@@ -5811,16 +5526,25 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetDeviceGroupSurfacePresentModesKHX(
VkSurfaceKHR surface,
VkDeviceGroupPresentModeFlagsKHX* pModes);
VKAPI_ATTR VkResult VKAPI_CALL vkAcquireNextImage2KHX(
VkDevice device,
const VkAcquireNextImageInfoKHX* pAcquireInfo,
uint32_t* pImageIndex);
VKAPI_ATTR void VKAPI_CALL vkCmdDispatchBaseKHX(
VkCommandBuffer commandBuffer,
uint32_t baseGroupX,
uint32_t baseGroupY,
uint32_t baseGroupZ,
uint32_t groupCountX,
uint32_t groupCountY,
uint32_t groupCountZ);
VKAPI_ATTR VkResult VKAPI_CALL vkGetPhysicalDevicePresentRectanglesKHX(
VkPhysicalDevice physicalDevice,
VkSurfaceKHR surface,
uint32_t* pRectCount,
VkRect2D* pRects);
VKAPI_ATTR VkResult VKAPI_CALL vkAcquireNextImage2KHX(
VkDevice device,
const VkAcquireNextImageInfoKHX* pAcquireInfo,
uint32_t* pImageIndex);
#endif
#define VK_EXT_validation_flags 1
@@ -5915,7 +5639,7 @@ VKAPI_ATTR VkResult VKAPI_CALL vkEnumeratePhysicalDeviceGroupsKHX(
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkObjectTableNVX)
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkIndirectCommandsLayoutNVX)
#define VK_NVX_DEVICE_GENERATED_COMMANDS_SPEC_VERSION 3
#define VK_NVX_DEVICE_GENERATED_COMMANDS_SPEC_VERSION 1
#define VK_NVX_DEVICE_GENERATED_COMMANDS_EXTENSION_NAME "VK_NVX_device_generated_commands"
@@ -6205,7 +5929,6 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetRandROutputDisplayEXT(
#define VK_EXT_display_surface_counter 1
#define VK_EXT_DISPLAY_SURFACE_COUNTER_SPEC_VERSION 1
#define VK_EXT_DISPLAY_SURFACE_COUNTER_EXTENSION_NAME "VK_EXT_display_surface_counter"
#define VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_EXT
typedef enum VkSurfaceCounterFlagBitsEXT {
@@ -6481,7 +6204,7 @@ VKAPI_ATTR void VKAPI_CALL vkCmdSetDiscardRectangleEXT(
#endif
#define VK_EXT_swapchain_colorspace 1
#define VK_EXT_SWAPCHAIN_COLOR_SPACE_SPEC_VERSION 3
#define VK_EXT_SWAPCHAIN_COLOR_SPACE_SPEC_VERSION 2
#define VK_EXT_SWAPCHAIN_COLOR_SPACE_EXTENSION_NAME "VK_EXT_swapchain_colorspace"
@@ -6605,96 +6328,6 @@ typedef struct VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT {
#define VK_AMD_GPU_SHADER_INT16_EXTENSION_NAME "VK_AMD_gpu_shader_int16"
#define VK_AMD_mixed_attachment_samples 1
#define VK_AMD_MIXED_ATTACHMENT_SAMPLES_SPEC_VERSION 1
#define VK_AMD_MIXED_ATTACHMENT_SAMPLES_EXTENSION_NAME "VK_AMD_mixed_attachment_samples"
#define VK_AMD_shader_fragment_mask 1
#define VK_AMD_SHADER_FRAGMENT_MASK_SPEC_VERSION 1
#define VK_AMD_SHADER_FRAGMENT_MASK_EXTENSION_NAME "VK_AMD_shader_fragment_mask"
#define VK_EXT_shader_stencil_export 1
#define VK_EXT_SHADER_STENCIL_EXPORT_SPEC_VERSION 1
#define VK_EXT_SHADER_STENCIL_EXPORT_EXTENSION_NAME "VK_EXT_shader_stencil_export"
#define VK_EXT_sample_locations 1
#define VK_EXT_SAMPLE_LOCATIONS_SPEC_VERSION 1
#define VK_EXT_SAMPLE_LOCATIONS_EXTENSION_NAME "VK_EXT_sample_locations"
typedef struct VkSampleLocationEXT {
float x;
float y;
} VkSampleLocationEXT;
typedef struct VkSampleLocationsInfoEXT {
VkStructureType sType;
const void* pNext;
VkSampleCountFlagBits sampleLocationsPerPixel;
VkExtent2D sampleLocationGridSize;
uint32_t sampleLocationsCount;
const VkSampleLocationEXT* pSampleLocations;
} VkSampleLocationsInfoEXT;
typedef struct VkAttachmentSampleLocationsEXT {
uint32_t attachmentIndex;
VkSampleLocationsInfoEXT sampleLocationsInfo;
} VkAttachmentSampleLocationsEXT;
typedef struct VkSubpassSampleLocationsEXT {
uint32_t subpassIndex;
VkSampleLocationsInfoEXT sampleLocationsInfo;
} VkSubpassSampleLocationsEXT;
typedef struct VkRenderPassSampleLocationsBeginInfoEXT {
VkStructureType sType;
const void* pNext;
uint32_t attachmentInitialSampleLocationsCount;
const VkAttachmentSampleLocationsEXT* pAttachmentInitialSampleLocations;
uint32_t postSubpassSampleLocationsCount;
const VkSubpassSampleLocationsEXT* pPostSubpassSampleLocations;
} VkRenderPassSampleLocationsBeginInfoEXT;
typedef struct VkPipelineSampleLocationsStateCreateInfoEXT {
VkStructureType sType;
const void* pNext;
VkBool32 sampleLocationsEnable;
VkSampleLocationsInfoEXT sampleLocationsInfo;
} VkPipelineSampleLocationsStateCreateInfoEXT;
typedef struct VkPhysicalDeviceSampleLocationsPropertiesEXT {
VkStructureType sType;
void* pNext;
VkSampleCountFlags sampleLocationSampleCounts;
VkExtent2D maxSampleLocationGridSize;
float sampleLocationCoordinateRange[2];
uint32_t sampleLocationSubPixelBits;
VkBool32 variableSampleLocations;
} VkPhysicalDeviceSampleLocationsPropertiesEXT;
typedef struct VkMultisamplePropertiesEXT {
VkStructureType sType;
void* pNext;
VkExtent2D maxSampleLocationGridSize;
} VkMultisamplePropertiesEXT;
typedef void (VKAPI_PTR *PFN_vkCmdSetSampleLocationsEXT)(VkCommandBuffer commandBuffer, const VkSampleLocationsInfoEXT* pSampleLocationsInfo);
typedef void (VKAPI_PTR *PFN_vkGetPhysicalDeviceMultisamplePropertiesEXT)(VkPhysicalDevice physicalDevice, VkSampleCountFlagBits samples, VkMultisamplePropertiesEXT* pMultisampleProperties);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR void VKAPI_CALL vkCmdSetSampleLocationsEXT(
VkCommandBuffer commandBuffer,
const VkSampleLocationsInfoEXT* pSampleLocationsInfo);
VKAPI_ATTR void VKAPI_CALL vkGetPhysicalDeviceMultisamplePropertiesEXT(
VkPhysicalDevice physicalDevice,
VkSampleCountFlagBits samples,
VkMultisamplePropertiesEXT* pMultisampleProperties);
#endif
#define VK_EXT_blend_operation_advanced 1
#define VK_EXT_BLEND_OPERATION_ADVANCED_SPEC_VERSION 2
#define VK_EXT_BLEND_OPERATION_ADVANCED_EXTENSION_NAME "VK_EXT_blend_operation_advanced"
@@ -6788,102 +6421,6 @@ typedef struct VkPipelineCoverageModulationStateCreateInfoNV {
#define VK_NV_FILL_RECTANGLE_EXTENSION_NAME "VK_NV_fill_rectangle"
#define VK_EXT_post_depth_coverage 1
#define VK_EXT_POST_DEPTH_COVERAGE_SPEC_VERSION 1
#define VK_EXT_POST_DEPTH_COVERAGE_EXTENSION_NAME "VK_EXT_post_depth_coverage"
#define VK_EXT_validation_cache 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkValidationCacheEXT)
#define VK_EXT_VALIDATION_CACHE_SPEC_VERSION 1
#define VK_EXT_VALIDATION_CACHE_EXTENSION_NAME "VK_EXT_validation_cache"
typedef enum VkValidationCacheHeaderVersionEXT {
VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT = 1,
VK_VALIDATION_CACHE_HEADER_VERSION_BEGIN_RANGE_EXT = VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT,
VK_VALIDATION_CACHE_HEADER_VERSION_END_RANGE_EXT = VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT,
VK_VALIDATION_CACHE_HEADER_VERSION_RANGE_SIZE_EXT = (VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT - VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT + 1),
VK_VALIDATION_CACHE_HEADER_VERSION_MAX_ENUM_EXT = 0x7FFFFFFF
} VkValidationCacheHeaderVersionEXT;
typedef VkFlags VkValidationCacheCreateFlagsEXT;
typedef struct VkValidationCacheCreateInfoEXT {
VkStructureType sType;
const void* pNext;
VkValidationCacheCreateFlagsEXT flags;
size_t initialDataSize;
const void* pInitialData;
} VkValidationCacheCreateInfoEXT;
typedef struct VkShaderModuleValidationCacheCreateInfoEXT {
VkStructureType sType;
const void* pNext;
VkValidationCacheEXT validationCache;
} VkShaderModuleValidationCacheCreateInfoEXT;
typedef VkResult (VKAPI_PTR *PFN_vkCreateValidationCacheEXT)(VkDevice device, const VkValidationCacheCreateInfoEXT* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkValidationCacheEXT* pValidationCache);
typedef void (VKAPI_PTR *PFN_vkDestroyValidationCacheEXT)(VkDevice device, VkValidationCacheEXT validationCache, const VkAllocationCallbacks* pAllocator);
typedef VkResult (VKAPI_PTR *PFN_vkMergeValidationCachesEXT)(VkDevice device, VkValidationCacheEXT dstCache, uint32_t srcCacheCount, const VkValidationCacheEXT* pSrcCaches);
typedef VkResult (VKAPI_PTR *PFN_vkGetValidationCacheDataEXT)(VkDevice device, VkValidationCacheEXT validationCache, size_t* pDataSize, void* pData);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkCreateValidationCacheEXT(
VkDevice device,
const VkValidationCacheCreateInfoEXT* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkValidationCacheEXT* pValidationCache);
VKAPI_ATTR void VKAPI_CALL vkDestroyValidationCacheEXT(
VkDevice device,
VkValidationCacheEXT validationCache,
const VkAllocationCallbacks* pAllocator);
VKAPI_ATTR VkResult VKAPI_CALL vkMergeValidationCachesEXT(
VkDevice device,
VkValidationCacheEXT dstCache,
uint32_t srcCacheCount,
const VkValidationCacheEXT* pSrcCaches);
VKAPI_ATTR VkResult VKAPI_CALL vkGetValidationCacheDataEXT(
VkDevice device,
VkValidationCacheEXT validationCache,
size_t* pDataSize,
void* pData);
#endif
#define VK_EXT_shader_viewport_index_layer 1
#define VK_EXT_SHADER_VIEWPORT_INDEX_LAYER_SPEC_VERSION 1
#define VK_EXT_SHADER_VIEWPORT_INDEX_LAYER_EXTENSION_NAME "VK_EXT_shader_viewport_index_layer"
#define VK_EXT_global_priority 1
#define VK_EXT_GLOBAL_PRIORITY_SPEC_VERSION 1
#define VK_EXT_GLOBAL_PRIORITY_EXTENSION_NAME "VK_EXT_global_priority"
typedef enum VkQueueGlobalPriorityEXT {
VK_QUEUE_GLOBAL_PRIORITY_LOW = 128,
VK_QUEUE_GLOBAL_PRIORITY_MEDIUM = 256,
VK_QUEUE_GLOBAL_PRIORITY_HIGH = 512,
VK_QUEUE_GLOBAL_PRIORITY_REALTIME = 1024,
VK_QUEUE_GLOBAL_PRIORITY_BEGIN_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_LOW,
VK_QUEUE_GLOBAL_PRIORITY_END_RANGE_EXT = VK_QUEUE_GLOBAL_PRIORITY_REALTIME,
VK_QUEUE_GLOBAL_PRIORITY_RANGE_SIZE_EXT = (VK_QUEUE_GLOBAL_PRIORITY_REALTIME - VK_QUEUE_GLOBAL_PRIORITY_LOW + 1),
VK_QUEUE_GLOBAL_PRIORITY_MAX_ENUM_EXT = 0x7FFFFFFF
} VkQueueGlobalPriorityEXT;
typedef struct VkDeviceQueueGlobalPriorityCreateInfoEXT {
VkStructureType sType;
const void* pNext;
VkQueueGlobalPriorityEXT globalPriority;
} VkDeviceQueueGlobalPriorityCreateInfoEXT;
#ifdef __cplusplus
}
#endif

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@@ -1,74 +0,0 @@
# ===========================================================================
# http://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html
# ===========================================================================
#
# SYNOPSIS
#
# AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT])
#
# DESCRIPTION
#
# Check whether the given FLAG works with the current language's compiler
# or gives an error. (Warnings, however, are ignored)
#
# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on
# success/failure.
#
# If EXTRA-FLAGS is defined, it is added to the current language's default
# flags (e.g. CFLAGS) when the check is done. The check is thus made with
# the flags: "CFLAGS EXTRA-FLAGS FLAG". This can for example be used to
# force the compiler to issue an error when a bad flag is given.
#
# INPUT gives an alternative input source to AC_COMPILE_IFELSE.
#
# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this
# macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG.
#
# LICENSE
#
# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de>
# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com>
#
# This program is free software: you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation, either version 3 of the License, or (at your
# option) any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
# Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program. If not, see <http://www.gnu.org/licenses/>.
#
# As a special exception, the respective Autoconf Macro's copyright owner
# gives unlimited permission to copy, distribute and modify the configure
# scripts that are the output of Autoconf when processing the Macro. You
# need not follow the terms of the GNU General Public License when using
# or distributing such scripts, even though portions of the text of the
# Macro appear in them. The GNU General Public License (GPL) does govern
# all other use of the material that constitutes the Autoconf Macro.
#
# This special exception to the GPL applies to versions of the Autoconf
# Macro released by the Autoconf Archive. When you make and distribute a
# modified version of the Autoconf Macro, you may extend this special
# exception to the GPL to apply to your modified version as well.
#serial 3
AC_DEFUN([AX_CHECK_COMPILE_FLAG],
[AC_PREREQ(2.59)dnl for _AC_LANG_PREFIX
AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl
AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [
ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS
_AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1"
AC_COMPILE_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])],
[AS_VAR_SET(CACHEVAR,[yes])],
[AS_VAR_SET(CACHEVAR,[no])])
_AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags])
AS_IF([test x"AS_VAR_GET(CACHEVAR)" = xyes],
[m4_default([$2], :)],
[m4_default([$3], :)])
AS_VAR_POPDEF([CACHEVAR])dnl
])dnl AX_CHECK_COMPILE_FLAGS

View File

@@ -1,815 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
project('mesa', ['c', 'cpp'], version : '17.3.0-devel', license : 'MIT',
default_options : ['c_std=c99', 'cpp_std=c++11'])
error('The meson build is unsupported for building mesa 17.3.x releases.')
# Arguments for the preprocessor, put these in a separate array from the C and
# C++ (cpp in meson terminology) arguments since they need to be added to the
# default arguments for both C and C++.
pre_args = [
'-D__STDC_CONSTANT_MACROS',
'-D__STDC_FORMAT_MACROS',
'-D__STDC_LIMIT_MACROS',
'-DVERSION="@0@"'.format(meson.project_version()),
'-DPACKAGE_VERSION=VERSION',
'-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa"',
'-D_GNU_SOURCE',
]
with_vulkan_icd_dir = get_option('vulkan-icd-dir')
with_tests = get_option('build-tests')
with_valgrind = get_option('valgrind')
with_asm = get_option('asm')
with_llvm = get_option('llvm')
if get_option('texture-float')
pre_args += '-DTEXTURE_FLOAT_ENABLED'
message('WARNING: Floating-point texture enabled. Please consult docs/patents.txt and your lawyer before building mesa.')
endif
# XXX: yeah, do these
with_appledri = false
with_windowsdri = false
dri_drivers_path = get_option('dri-drivers-path')
if dri_drivers_path == ''
dri_drivers_path = join_paths(get_option('libdir'), 'dri')
endif
with_gles1 = get_option('gles1')
with_gles2 = get_option('gles2')
with_opengl = get_option('opengl')
with_any_opengl = with_opengl or with_gles1 or with_gles2
# Only build shared_glapi if at least one OpenGL API is enabled
with_shared_glapi = get_option('shared-glapi') and with_any_opengl
# TODO: these will need options, but at the moment they just control header
# installs
with_osmesa = false
# shared-glapi is required if at least two OpenGL APIs are being built
if not with_shared_glapi
if ((with_gles1 and with_gles2) or (with_gles1 and with_opengl)
or (with_gles2 and with_opengl))
error('shared-glapi required for building two or more of OpenGL, OpenGL ES 1.x, OpenGL ES 2.x')
endif
endif
# We require OpenGL for OpenGL ES
if (with_gles1 or with_gles2) and not with_opengl
error('building OpenGL ES without OpenGL is not supported.')
endif
with_dri = false
with_dri_i915 = false
with_dri_i965 = false
with_dri_swrast = false
_drivers = get_option('dri-drivers')
if _drivers != ''
_split = _drivers.split(',')
with_dri_i915 = _split.contains('i915')
with_dri_i965 = _split.contains('i965')
with_dri_swrast = _split.contains('swrast')
with_dri = true
endif
with_gallium = false
with_gallium_pl111 = false
with_gallium_radeonsi = false
with_gallium_nouveau = false
with_gallium_softpipe = false
with_gallium_vc4 = false
with_gallium_vc5 = false
_drivers = get_option('gallium-drivers')
if _drivers != ''
_split = _drivers.split(',')
with_gallium_pl111 = _split.contains('pl111')
with_gallium_radeonsi = _split.contains('radeonsi')
with_gallium_nouveau = _split.contains('nouveau')
with_gallium_softpipe = _split.contains('swrast')
with_gallium_vc4 = _split.contains('vc4')
with_gallium_vc5 = _split.contains('vc5')
with_gallium = true
with_dri = true
endif
if not (with_dri or with_gallium)
with_gles1 = false
with_gles2 = false
with_opengl = false
with_any_opengl = false
with_shared_glapi = false
endif
if with_dri_swrast and with_gallium_softpipe
error('Only one swrast provider can be built')
endif
dep_libdrm_intel = []
if with_dri_i915
dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
endif
# TODO: other OSes
with_dri_platform = 'drm'
# TODO: android platform
with_platform_wayland = false
with_platform_x11 = false
with_platform_drm = false
with_platform_surfaceless = false
egl_native_platform = ''
_platforms = get_option('platforms')
if _platforms != ''
_split = _platforms.split(',')
with_platform_x11 = _split.contains('x11')
with_platform_wayland = _split.contains('wayland')
with_platform_drm = _split.contains('drm')
with_platform_surfaceless = _split.contains('surfaceless')
egl_native_platform = _split[0]
endif
with_gbm = get_option('gbm')
if with_gbm == 'auto' and with_dri # TODO: or gallium
with_gbm = host_machine.system() == 'linux'
elif with_gbm == 'yes'
if not ['linux', 'bsd'].contains(host_machine.system())
error('GBM only supports unix-like platforms')
endif
with_gbm = true
else
with_gbm = false
endif
_egl = get_option('egl')
if _egl == 'auto'
with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
elif _egl == 'yes'
if not with_dri
error('EGL requires dri')
elif not with_shared_glapi
error('EGL requires shared-glapi')
elif egl_native_platform == ''
error('No platforms specified, consider -Dplatforms=drm,x11 at least')
endif
with_egl = true
else
with_egl = false
endif
# TODO: or virgl
if with_egl and with_gallium_radeonsi and not (with_platform_drm or with_platform_surfaceless)
error('RadeonSI requires drm or surfaceless platform when using EGL')
endif
pre_args += '-DGLX_USE_TLS'
with_glx = get_option('glx')
if with_glx != 'disabled'
if not (with_platform_x11 and with_any_opengl)
if with_glx == 'auto'
with_glx = 'disabled'
else
error('Cannot build GLX support without X11 platform support and at least one OpenGL API')
endif
elif with_glx == 'gallium-xlib'
if not with_gallium
error('Gallium-xlib based GLX requires at least one gallium driver')
elif with_dri
error('gallium-xlib conflicts with any dri driver')
endif
elif with_glx == 'dri' and not with_dri
error('dri based GLX requires at least one DRI driver')
elif with_glx == 'auto'
if with_dri
with_glx = 'dri'
elif with_gallium
with_glx = 'gallium-xlib'
elif with_platform_x11 and with_any_opengl
with_glx = 'xlib'
else
with_glx = 'disabled'
endif
endif
endif
with_glvnd = get_option('glvnd')
if with_glvnd and with_glx != 'dri'
message('glvnd requires dri based glx')
endif
# TODO: toggle for this
with_glx_direct = true
if with_vulkan_icd_dir == ''
with_vulkan_icd_dir = join_paths(get_option('datadir'), 'vulkan/icd.d')
endif
with_intel_vk = false
with_amd_vk = false
with_any_vk = false
_vulkan_drivers = get_option('vulkan-drivers')
if _vulkan_drivers != ''
_split = _vulkan_drivers.split(',')
with_intel_vk = _split.contains('intel')
with_amd_vk = _split.contains('amd')
with_any_vk = with_amd_vk or with_intel_vk
if not (with_platform_x11 or with_platform_wayland)
error('Vulkan requires at least one platform (x11, wayland)')
endif
endif
with_dri2 = (with_dri or with_any_vk) and with_dri_platform == 'drm'
with_dri3 = get_option('dri3')
if with_dri3 == 'auto'
if host_machine.system() == 'linux' and with_dri2
with_dri3 = true
else
with_dri3 = false
endif
elif with_dri3 == 'yes'
with_dri3 = true
else
with_dri3 = false
endif
if with_any_vk and (with_platform_x11 and not with_dri3)
error('Vulkan drivers require dri3 for X11 support')
endif
if with_dri or with_gallium
if with_glx == 'disabled' and not with_egl
error('building dri or gallium drivers require at least one window system')
endif
endif
with_gallium_xvmc = false
with_gallium_vdpau = false
with_gallium_omx = false # this is bellagio
with_gallium_va = false
with_gallium_media = false
dep_va = []
_drivers = get_option('gallium-media')
if _drivers != ''
_split = _drivers.split(',')
with_gallium_xvmc = _split.contains('xvmc')
with_gallium_vdpau = _split.contains('vdpau')
with_gallium_omx = _split.contains('omx')
with_gallium_va = _split.contains('va')
with_gallium_media = (with_gallium_xvmc or with_gallium_vdpau or
with_gallium_omx or with_gallium_va)
endif
gl_pkgconfig_c_flags = []
if with_platform_x11
if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
pre_args += '-DHAVE_X11_PLATFORM'
endif
if with_glx == 'xlib'
# TODO
error('TODO')
elif with_glx == 'gallium-xlib'
# TODO
error('TODO')
else
pre_args += '-DGLX_INDIRECT_RENDERING'
if with_glx_direct
pre_args += '-DGLX_DIRECT_RENDERING'
endif
if with_dri_platform == 'drm'
pre_args += '-DGLX_USE_DRM'
endif
endif
else
pre_args += '-DMESA_EGL_NO_X11_HEADERS'
gl_pkgconfig_c_flags += '-DMESA_EGL_NO_X11_HEADERS'
endif
if with_platform_drm
if with_egl and not with_gbm
error('EGL drm platform requires gbm')
endif
pre_args += '-DHAVE_DRM_PLATFORM'
endif
if with_platform_surfaceless
pre_args += '-DHAVE_SURFACELESS_PLATFORM'
endif
prog_python2 = find_program('python2')
has_mako = run_command(prog_python2, '-c', 'import mako')
if has_mako.returncode() != 0
error('Python (2.x) mako module required to build mesa.')
endif
cc = meson.get_compiler('c')
if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
error('When using GCC, version 4.4.6 or later is required.')
endif
# Define DEBUG for debug and debugoptimized builds
if get_option('buildtype').startswith('debug')
pre_args += '-DDEBUG'
endif
if get_option('shader-cache')
pre_args += '-DENABLE_SHADER_CACHE'
elif with_amd_vk
error('Radv requires shader cache support')
endif
# Check for GCC style builtins
foreach b : ['bswap32', 'bswap64', 'clz', 'clzll', 'ctz', 'expect', 'ffs',
'ffsll', 'popcount', 'popcountll', 'unreachable']
if cc.has_function(b)
pre_args += '-DHAVE___BUILTIN_@0@'.format(b.to_upper())
endif
endforeach
# check for GCC __attribute__
foreach a : ['const', 'flatten', 'malloc', 'pure', 'unused',
'warn_unused_result', 'weak',]
if cc.compiles('int foo(void) __attribute__((@0@));'.format(a),
name : '__attribute__((@0@))'.format(a))
pre_args += '-DHAVE_FUNC_ATTRIBUTE_@0@'.format(a.to_upper())
endif
endforeach
if cc.compiles('int foo(const char *p, ...) __attribute__((format(printf, 1, 2)));',
name : '__attribute__((format(...)))')
pre_args += '-DHAVE_FUNC_ATTRIBUTE_FORMAT'
endif
if cc.compiles('struct __attribute__((packed)) foo { int bar; };',
name : '__attribute__((packed))')
pre_args += '-DHAVE_FUNC_ATTRIBUTE_PACKED'
endif
if cc.compiles('int *foo(void) __attribute__((returns_nonnull));',
name : '__attribute__((returns_nonnull))')
pre_args += '-DHAVE_FUNC_ATTRIBUTE_NONNULL'
endif
if cc.compiles('''int foo_def(void) __attribute__((visibility("default")));
int foo_hid(void) __attribute__((visibility("hidden")));
int foo_int(void) __attribute__((visibility("internal")));
int foo_pro(void) __attribute__((visibility("protected")));''',
name : '__attribute__((visibility(...)))')
pre_args += '-DHAVE_FUNC_ATTRIBUTE_VISBILITY'
endif
if cc.compiles('int foo(void) { return 0; } int bar(void) __attribute__((alias("foo")));',
name : '__attribute__((alias(...)))')
pre_args += '-DHAVE_FUNC_ATTRIBUTE_ALIAS'
endif
# TODO: this is very incomplete
if host_machine.system() == 'linux'
pre_args += '-D_GNU_SOURCE'
endif
# Check for generic C arguments
c_args = []
foreach a : ['-Wall', '-Werror=implicit-function-declaration',
'-Werror=missing-prototypes', '-fno-math-errno',
'-fno-trapping-math', '-Qunused-arguments']
if cc.has_argument(a)
c_args += a
endif
endforeach
c_vis_args = []
if cc.has_argument('-fvisibility=hidden')
c_vis_args += '-fvisibility=hidden'
endif
# Check for generic C++ arguments
cpp = meson.get_compiler('cpp')
cpp_args = []
foreach a : ['-Wall', '-fno-math-errno', '-fno-trapping-math',
'-Qunused-arguments', '-Wno-non-virtual-dtor']
if cpp.has_argument(a)
cpp_args += a
endif
endforeach
cpp_vis_args = []
if cpp.has_argument('-fvisibility=hidden')
cpp_vis_args += '-fvisibility=hidden'
endif
# Check for C and C++ arguments for MSVC2013 compatibility. These are only used
# in parts of the mesa code base that need to compile with old versions of
# MSVC, mainly common code
c_msvc_compat_args = []
cpp_msvc_compat_args = []
foreach a : ['-Werror=pointer-arith', '-Werror=vla']
if cc.has_argument(a)
c_msvc_compat_args += a
endif
if cpp.has_argument(a)
cpp_msvc_compat_args += a
endif
endforeach
no_override_init_args = []
foreach a : ['-Wno-override-init', '-Wno-initializer-overrides']
if cc.has_argument(a)
no_override_init_args += a
endif
endforeach
# TODO: SSE41 (which is only required for core mesa)
# Check for GCC style atomics
if cc.compiles('int main() { int n; return __atomic_load_n(&n, __ATOMIC_ACQUIRE); }',
name : 'GCC atomic builtins')
pre_args += '-DUSE_GCC_ATOMIC_BUILTINS'
endif
if not cc.links('''#include <stdint.h>
uint64_t v;
int main() {
return __sync_add_and_fetch(&v, (uint64_t)1);
}''',
name : 'GCC 64bit atomics')
pre_args += '-DMISSING_64_BIT_ATOMICS'
endif
# TODO: endian
# TODO: powr8
# TODO: shared/static? Is this even worth doing?
# I don't think that I need to set any of the debug stuff, I think meson
# handles that for us
# TODO: ldflags
# TODO: texture-float (gallium/mesa only)
# TODO: cross-compiling. I don't think this is relavent to meson
# FIXME: enable asm when cross compiler
# This is doable (autotools does it), but it's not of immediate concern
if meson.is_cross_build()
message('Cross compiling, disabling asm')
with_asm = false
endif
with_asm_arch = ''
if with_asm
# TODO: SPARC and PPC
if host_machine.cpu_family() == 'x86'
if ['linux', 'bsd'].contains(host_machine.system()) # FIXME: hurd?
with_asm_arch = 'x86'
pre_args += ['-DUSE_X86_ASM', '-DUSE_MMX_ASM', '-DUSE_3DNOW_ASM',
'-DUSE_SSE_ASM']
endif
elif host_machine.cpu_family() == 'x86_64'
if host_machine.system() == 'linux'
with_asm_arch = 'x86_64'
pre_args += ['-DUSE_X86_64_ASM']
endif
elif host_machine.cpu_family() == 'arm'
if host_machine.system() == 'linux'
with_asm_arch = 'arm'
pre_args += ['-DUSE_ARM_ASM']
endif
elif host_machine.cpu_family() == 'aarch64'
if host_machine.system() == 'linux'
with_asm_arch = 'aarch64'
pre_args += ['-DUSE_AARCH64_ASM']
endif
endif
endif
# Check for standard headers and functions
if cc.has_header_symbol('sys/sysmacros.h', 'major')
pre_args += '-DMAJOR_IN_SYSMACROS'
elif cc.has_header_symbol('sys/mkdev.h', 'major')
pre_args += '-DMAJOR_IN_MKDEV'
endif
foreach h : ['xlocale.h', 'sys/sysctl.h']
if cc.has_header(h)
pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
endif
endforeach
foreach f : ['strtof', 'mkostemp', 'posix_memalign']
if cc.has_function(f)
pre_args += '-DHAVE_@0@'.format(f.to_upper())
endif
endforeach
# strtod locale support
if cc.links('''
#define _GNU_SOURCE
#include <stdlib.h>
#include <locale.h>
#ifdef HAVE_XLOCALE_H
#include <xlocale.h>
#endif
int main() {
locale_t loc = newlocale(LC_CTYPE_MASK, "C", NULL);
const char *s = "1.0";
char *end;
double d = strtod_l(s, end, loc);
float f = strtod_l(s, end, loc);
freelocale(loc);
return 0;
}''',
extra_args : pre_args,
name : 'strtod has locale support')
pre_args += '-DHAVE_STRTOD_L'
endif
# Check for some linker flags
ld_args_bsymbolic = []
if cc.links('int main() { return 0; }', args : '-Wl,-Bsymbolic', name : 'Bsymbolic')
ld_args_bsymbolic += '-Wl,-Bsymbolic'
endif
ld_args_gc_sections = []
if cc.links('static char unused() { return 5; } int main() { return 0; }',
args : '-Wl,--gc-sections', name : 'gc-sections')
ld_args_gc_sections += '-Wl,--gc-sections'
endif
with_ld_version_script = false
if cc.links('int main() { return 0; }',
args : '-Wl,--version-script=@0@'.format(
join_paths(meson.source_root(), 'build-support/conftest.map')),
name : 'version-script')
with_ld_version_script = true
endif
with_ld_dynamic_list = false
if cc.links('int main() { return 0; }',
args : '-Wl,--dynamic-list=@0@'.format(
join_paths(meson.source_root(), 'build-support/conftest.dyn')),
name : 'dynamic-list')
with_ld_dynamic_list = true
endif
# check for dl support
if cc.has_function('dlopen')
dep_dl = []
else
dep_dl = cc.find_library('dl')
endif
if cc.has_function('dladdr', dependencies : dep_dl)
# This is really only required for megadrivers
pre_args += '-DHAVE_DLADDR'
endif
if cc.has_function('dl_iterate_phdr')
pre_args += '-DHAVE_DL_ITERATE_PHDR'
else
# TODO: this is required for vulkan
endif
# Determine whether or not the rt library is needed for time functions
if cc.has_function('clock_gettime')
dep_clock = []
else
dep_clock = cc.find_library('rt')
endif
with_gallium_drisw_kms = false
dep_libdrm = dependency('libdrm', version : '>= 2.4.75',
required : with_dri2 or with_dri3)
if dep_libdrm.found()
pre_args += '-DHAVE_LIBDRM'
if with_dri_platform == 'drm' and with_dri
with_gallium_drisw_kms = true
endif
endif
# TODO: some of these may be conditional
dep_zlib = dependency('zlib', version : '>= 1.2.3')
dep_thread = dependency('threads')
if dep_thread.found() and host_machine.system() == 'linux'
pre_args += '-DHAVE_PTHREAD'
endif
dep_elf = dependency('libelf', required : false)
if not dep_elf.found() and (with_amd_vk or with_gallium_radeonsi) # TODO: clover, r600
dep_elf = cc.find_library('elf')
endif
dep_expat = dependency('expat')
# this only exists on linux so either this is linux and it will be found, or
# its not linux and and wont
dep_m = cc.find_library('m', required : false)
dep_libdrm_amdgpu = []
dep_libdrm_radeon = []
dep_libdrm_nouveau = []
if with_amd_vk or with_gallium_radeonsi
dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.85')
endif
if with_gallium_radeonsi # older radeon too
dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= 2.4.71')
endif
if with_gallium_nouveau
dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
endif
llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
if with_amd_vk
llvm_modules += ['amdgpu', 'bitreader', 'ipo']
endif
dep_llvm = dependency(
'llvm', version : '>= 3.9.0', required : with_amd_vk, modules : llvm_modules,
)
if with_llvm
if dep_llvm.found()
_llvm_version = dep_llvm.version().split('.')
# Development versions of LLVM have an 'svn' suffix, we don't want that for
# our version checks.
_llvm_patch = _llvm_version[2]
if _llvm_patch.endswith('svn')
_llvm_patch = _llvm_patch.split('s')[0]
endif
pre_args += [
'-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], _llvm_patch),
'-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
]
else
if with_gallium_softpipe
error('Cannot find LLVM to build LLVMPipe. If you wanted softpipe pass -Dllvm=false to meson')
elif with_amd_vk or with_gallium_radeonsi # etc
error('The following drivers requires LLVM: Radv, RadeonSI. One of these is enabled, but LLVM was not found.')
endif
endif
elif with_amd_vk or with_gallium_radeonsi
error('The following drivers requires LLVM: Radv, RadeonSI. One of these is enabled, but LLVM is disabled.')
endif
dep_glvnd = []
if with_glvnd
dep_glvnd = dependency('libglvnd', version : '>= 0.2.0')
pre_args += '-DUSE_LIBGLVND=1'
endif
# TODO: make this conditional
dep_valgrind = dependency('valgrind', required : false)
if dep_valgrind.found() and with_valgrind
pre_args += '-DHAVE_VALGRIND'
endif
# pthread stubs. Lets not and say we didn't
prog_bison = find_program('bison', required : with_any_opengl)
prog_flex = find_program('flex', required : with_any_opengl)
# TODO: selinux
dep_selinux = []
# TODO: llvm-prefix and llvm-shared-libs
dep_unwind = dependency('libunwind', required : false)
if dep_unwind.found()
pre_args += '-DHAVE_LIBUNWIND'
endif
# TODO: flags for opengl, gles, dri
# TODO: gallium-hud
# TODO: glx provider
# TODO: osmesa provider
# TODO: symbol mangling
if with_platform_wayland
prog_wl_scanner = find_program('wayland-scanner')
dep_wl_protocols = dependency('wayland-protocols', version : '>= 1.8')
dep_wayland_client = dependency('wayland-client', version : '>=1.11')
dep_wayland_server = dependency('wayland-server', version : '>=1.11')
wayland_dmabuf_xml = join_paths(
dep_wl_protocols.get_pkgconfig_variable('pkgdatadir'), 'unstable',
'linux-dmabuf', 'linux-dmabuf-unstable-v1.xml'
)
pre_args += ['-DHAVE_WAYLAND_PLATFORM', '-DWL_HIDE_DEPRECATED']
else
prog_wl_scanner = []
dep_wl_protocols = []
dep_wayland_client = []
dep_wayland_server = []
wayland_dmabuf_xml = ''
endif
dep_x11 = []
dep_xext = []
dep_xdamage = []
dep_xfixes = []
dep_x11_xcb = []
dep_xcb_glx = []
dep_xcb_dri2 = []
dep_xcb_dri3 = []
dep_dri2proto = []
dep_glproto = []
dep_xf86vm = []
dep_xcb_dri3 = []
dep_xcb_present = []
dep_xcb_sync = []
dep_xcb_xfixes = []
dep_xshmfence = []
if with_platform_x11
if with_glx == 'dri' and with_dri_platform == 'drm'
dep_x11 = dependency('x11')
dep_xext = dependency('xext')
dep_xdamage = dependency('xdamage', version : '>= 1.1')
dep_xfixes = dependency('xfixes')
dep_xcb_glx = dependency('xcb-glx', version : '>= 1.8.1')
dep_xf86vm = dependency('xxf86vm', required : false)
endif
if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
dep_xcb = dependency('xcb')
dep_x11_xcb = dependency('x11-xcb')
dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
if with_dri3
pre_args += '-DHAVE_DRI3'
dep_xcb_dri3 = dependency('xcb-dri3')
dep_xcb_present = dependency('xcb-present')
dep_xcb_sync = dependency('xcb-sync')
dep_xshmfence = dependency('xshmfence', version : '>= 1.1')
endif
endif
if with_glx != 'disabled'
dep_dri2proto = dependency('dri2proto', version : '>= 2.8')
dep_glproto = dependency('glproto', version : '>= 1.4.14')
endif
if with_egl
dep_xcb_xfixes = dependency('xcb-xfixes')
endif
endif
# TODO: osmesa
# TODO: vallium G3DVL
# TODO: nine
# TODO: clover
# TODO: gallium tests
# TODO: various libdirs
# TODO: swr
# TODO: gallium driver dirs
# FIXME: this is a workaround for #2326
prog_touch = find_program('touch')
dummy_cpp = custom_target(
'dummy_cpp',
output : 'dummy.cpp',
command : [prog_touch, '@OUTPUT@'],
)
foreach a : pre_args
add_project_arguments(a, language : ['c', 'cpp'])
endforeach
foreach a : c_args
add_project_arguments(a, language : ['c'])
endforeach
foreach a : cpp_args
add_project_arguments(a, language : ['cpp'])
endforeach
inc_include = include_directories('include')
gl_priv_reqs = [
'x11', 'xext', 'xdamage >= 1.1', 'xfixes', 'x11-xcb', 'xcb',
'xcb-glx >= 1.8.1', 'libdrm >= 2.4.75',
]
if dep_xf86vm != [] and dep_xf86vm.found()
gl_priv_reqs += 'xf86vm'
endif
if with_dri_platform == 'drm'
gl_priv_reqs += 'xcb-dri2 >= 1.8'
endif
gl_priv_libs = []
if dep_thread.found()
gl_priv_libs += ['-lpthread', '-pthread']
endif
if dep_m.found()
gl_priv_libs += '-lm'
endif
if dep_dl.found()
gl_priv_libs += '-ldl'
endif
pkg = import('pkgconfig')
subdir('include')
subdir('src')

View File

@@ -1,156 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
option(
'platforms',
type : 'string',
value : 'x11,wayland,drm,surfaceless',
description : 'comma separated list of window systems to support. wayland, x11, surfaceless, drm, etc.'
)
option(
'dri3',
type : 'combo',
value : 'auto',
choices : ['auto', 'yes', 'no'],
description : 'enable support for dri3'
)
option(
'dri-drivers',
type : 'string',
value : 'i915,i965',
description : 'comma separated list of dri drivers to build.'
)
option(
'dri-drivers-path',
type : 'string',
value : '',
description : 'Location of dri drivers. Default: $libdir/dri.'
)
option(
'gallium-drivers',
type : 'string',
value : 'pl111,radeonsi,nouveau,swrast,vc4',
description : 'comma separated list of gallium drivers to build.'
)
option(
'gallium-media',
type : 'string',
value : '',
description : 'comma separated list of gallium media APIs to build (omx,va,vdpau,xvmc).'
)
option(
'vulkan-drivers',
type : 'string',
value : 'intel,amd',
description : 'comma separated list of vulkan drivers to build.'
)
option(
'shader-cache',
type : 'boolean',
value : true,
description : 'Build with on-disk shader cache support'
)
option(
'vulkan-icd-dir',
type : 'string',
value : '',
description : 'Location relative to prefix to put vulkan icds on install. Default: $datadir/vulkan/icd.d'
)
option(
'shared-glapi',
type : 'boolean',
value : true,
description : 'Whether to build a shared or static glapi'
)
option(
'gles1',
type : 'boolean',
value : true,
description : 'Build support for OpenGL ES 1.x'
)
option(
'gles2',
type : 'boolean',
value : true,
description : 'Build support for OpenGL ES 2.x and 3.x'
)
option(
'opengl',
type : 'boolean',
value : true,
description : 'Build support for OpenGL (all versions)'
)
option(
'gbm',
type : 'combo',
value : 'auto',
choices : ['auto', 'yes', 'no'],
description : 'Build support for gbm platform'
)
option(
'glx',
type : 'combo',
value : 'auto',
choices : ['auto', 'disabled', 'dri', 'xlib', 'gallium-xlib'],
description : 'Build support for GLX platform'
)
option(
'egl',
type : 'combo',
value : 'auto',
choices : ['auto', 'yes', 'no'],
description : 'Build support for EGL platform'
)
option(
'glvnd',
type : 'boolean',
value : false,
description : 'Enable GLVND support.'
)
option(
'asm',
type : 'boolean',
value : true,
description : 'Build assembly code if possible'
)
option(
'llvm',
type : 'boolean',
value : true,
description : 'Build with LLVM support.'
)
option(
'valgrind',
type : 'boolean',
value : true,
description : 'Build with valgrind support if possible'
)
option(
'build-tests',
type : 'boolean',
value : false,
description : 'Build unit tests. Currently this will build *all* unit tests, which may build more than expected.'
)
option(
'texture-float',
type : 'boolean',
value : false,
description : 'Enable floating point textures and renderbuffers. This option may be patent encumbered, please read docs/patents.txt and consult with your lawyer before turning this on.'
)

View File

@@ -83,7 +83,7 @@ def shlib_emitter(target, source, env):
no_import_lib = env.get('no_import_lib', 0)
if not dll:
raise SCons.Errors.UserError("A shared library should have exactly one target with the suffix: %s" % env.subst("$SHLIBSUFFIX"))
raise SCons.Errors.UserError, "A shared library should have exactly one target with the suffix: %s" % env.subst("$SHLIBSUFFIX")
if not no_import_lib and \
not env.FindIxes(target, 'LIBPREFIX', 'LIBSUFFIX'):

View File

@@ -113,7 +113,7 @@ def python_scan(node, env, path):
finder = modulefinder.ModuleFinder(path=path)
finder.run_script(node.abspath)
results = []
for name, mod in finder.modules.items():
for name, mod in finder.modules.iteritems():
if mod.__file__ is None:
continue
assert os.path.exists(mod.__file__)
@@ -189,7 +189,7 @@ def _pkg_check_modules(env, name, modules):
except OSError:
return
prefix = name + '_'
for flag_name, flag_value in flags.items():
for flag_name, flag_value in flags.iteritems():
assert '_' not in flag_name
env[prefix + flag_name] = flag_value
@@ -222,7 +222,7 @@ def pkg_use_modules(env, names):
raise Exception('Attempt to use unavailable module %s' % name)
flags = {}
for flag_name, flag_value in env.Dictionary().items():
for flag_name, flag_value in env.Dictionary().iteritems():
if flag_name.startswith(prefix):
flag_name = flag_name[len(prefix):]
if '_' not in flag_name:
@@ -262,7 +262,7 @@ def parse_source_list(env, filename, names=None):
symbols = names
else:
symbols = list(sym_table.keys())
symbols = sym_table.keys()
# convert the symbol table to source lists
src_lists = {}

View File

@@ -51,7 +51,7 @@ def generate(env):
elif env['machine'] == 'x86_64':
target_cpu = 'x64'
else:
raise SCons.Errors.InternalError("Unsupported target machine")
raise SCons.Errors.InternalError, "Unsupported target machine"
include_dir = os.path.join(dxsdk_root, 'Include')
lib_dir = os.path.join(dxsdk_root, 'Lib', target_cpu)

View File

@@ -193,15 +193,15 @@ def generate(env):
env.Tool(env['toolchain'])
# Allow override compiler and specify additional flags from environment
if 'CC' in os.environ:
if os.environ.has_key('CC'):
env['CC'] = os.environ['CC']
if 'CFLAGS' in os.environ:
if os.environ.has_key('CFLAGS'):
env['CCFLAGS'] += SCons.Util.CLVar(os.environ['CFLAGS'])
if 'CXX' in os.environ:
if os.environ.has_key('CXX'):
env['CXX'] = os.environ['CXX']
if 'CXXFLAGS' in os.environ:
if os.environ.has_key('CXXFLAGS'):
env['CXXFLAGS'] += SCons.Util.CLVar(os.environ['CXXFLAGS'])
if 'LDFLAGS' in os.environ:
if os.environ.has_key('LDFLAGS'):
env['LINKFLAGS'] += SCons.Util.CLVar(os.environ['LDFLAGS'])
# Detect gcc/clang not by executable name, but through pre-defined macros

View File

@@ -50,7 +50,7 @@ def generate(env):
llvm_dir = None
else:
if not os.path.isdir(llvm_dir):
raise SCons.Errors.InternalError("Specified LLVM directory not found")
raise SCons.Errors.InternalError, "Specified LLVM directory not found"
if env['debug']:
llvm_subdir = 'Debug'
@@ -61,7 +61,7 @@ def generate(env):
if not os.path.isdir(llvm_bin_dir):
llvm_bin_dir = os.path.join(llvm_dir, 'bin')
if not os.path.isdir(llvm_bin_dir):
raise SCons.Errors.InternalError("LLVM binary directory not found")
raise SCons.Errors.InternalError, "LLVM binary directory not found"
env.PrependENVPath('PATH', llvm_bin_dir)

View File

@@ -21,7 +21,7 @@
.PHONY: git_sha1.h.tmp
git_sha1.h.tmp:
@$(PYTHON2) $(top_srcdir)/bin/git_sha1_gen.py > $@
@sh $(top_srcdir)/bin/git_sha1_gen.sh > $@
git_sha1.h: git_sha1.h.tmp
@echo "updating git_sha1.h"
@@ -33,7 +33,7 @@ git_sha1.h: git_sha1.h.tmp
BUILT_SOURCES = git_sha1.h
CLEANFILES = $(BUILT_SOURCES)
EXTRA_DIST = git_sha1.h.in
EXTRA_DIST =
SUBDIRS = . gtest util mapi/glapi/gen mapi
@@ -64,7 +64,7 @@ endif
# include only conditionally ?
SUBDIRS += compiler
## Optionally required by GBM, EGL
## Optionally required by GBM, EGL and Vulkan
if HAVE_PLATFORM_WAYLAND
SUBDIRS += egl/wayland/wayland-drm
endif
@@ -72,9 +72,7 @@ endif
if HAVE_VULKAN_COMMON
SUBDIRS += vulkan
endif
EXTRA_DIST += vulkan/registry/vk.xml
EXTRA_DIST += vulkan/registry/vk_android_native_buffer.xml
if HAVE_AMD_DRIVERS
SUBDIRS += amd
@@ -84,7 +82,7 @@ if HAVE_INTEL_DRIVERS
SUBDIRS += intel
endif
if HAVE_BROADCOM_DRIVERS
if HAVE_GALLIUM_VC4
SUBDIRS += broadcom
endif

View File

@@ -1,14 +1,12 @@
import filecmp
import os
import subprocess
from sys import executable as python_cmd
Import('*')
if env['platform'] == 'windows':
SConscript('getopt/SConscript')
SConscript('util/xmlpool/SConscript')
SConscript('util/SConscript')
SConscript('compiler/SConscript')
@@ -26,7 +24,7 @@ def write_git_sha1_h_file(filename):
tempfile = "git_sha1.h.tmp"
with open(tempfile, "w") as f:
args = [ python_cmd, Dir('#').abspath + '/bin/git_sha1_gen.py' ]
args = [ 'sh', Dir('#').abspath + '/bin/git_sha1_gen.sh' ]
try:
subprocess.Popen(args, stdout=f).wait()
except:

View File

@@ -31,8 +31,7 @@ LOCAL_MODULE := libmesa_amd_common
LOCAL_SRC_FILES := \
$(AMD_COMMON_FILES) \
$(AMD_COMPILER_FILES) \
$(AMD_DEBUG_FILES) \
$(AMD_NIR_FILES)
$(AMD_DEBUG_FILES)
LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU # instructs LLVM to declare LLVMInitializeAMDGPU* functions
@@ -44,7 +43,7 @@ LOCAL_GENERATED_SOURCES := $(addprefix $(intermediates)/, $(AMD_GENERATED_FILES)
$(LOCAL_GENERATED_SOURCES): PRIVATE_PYTHON := $(MESA_PYTHON2)
$(LOCAL_GENERATED_SOURCES): PRIVATE_CUSTOM_TOOL = $(PRIVATE_PYTHON) $^ > $@
$(intermediates)/common/sid_tables.h: $(LOCAL_PATH)/common/sid_tables.py $(LOCAL_PATH)/common/sid.h $(LOCAL_PATH)/common/gfx9d.h
$(intermediates)/common/sid_tables.h: $(LOCAL_PATH)/common/sid_tables.py $(MESA_TOP)/src/amd/common/sid.h
$(transform-generated-source)
LOCAL_C_INCLUDES := \

View File

@@ -58,8 +58,13 @@ common_libamd_common_la_SOURCES = \
$(AMD_COMMON_FILES) \
$(AMD_COMPILER_FILES) \
$(AMD_DEBUG_FILES) \
$(AMD_GENERATED_FILES) \
$(AMD_NIR_FILES)
$(AMD_GENERATED_FILES)
# nir_to_llvm requires LLVM 3.9, which is only required as a minimum when
# radv is built.
if HAVE_RADEON_VULKAN
common_libamd_common_la_SOURCES += $(AMD_NIR_FILES)
endif
endif
common_libamd_common_la_LIBADD = $(LIBELF_LIBS)

View File

@@ -1,6 +1,7 @@
COMMON_HEADER_FILES = \
common/gfx9d.h \
common/sid.h \
common/r600d_common.h \
common/amd_family.h \
common/amd_kernel_code_t.h \
common/amdgpu_id.h
@@ -47,7 +48,6 @@ AMD_COMPILER_FILES = \
common/ac_llvm_helper.cpp \
common/ac_llvm_util.c \
common/ac_llvm_util.h \
common/ac_shader_abi.h \
common/ac_shader_info.c \
common/ac_shader_info.h

View File

@@ -1675,37 +1675,3 @@ ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
return returnCode;
}
/**
****************************************************************************************************
* Addr2IsValidDisplaySwizzleMode
*
* @brief
* Return whether the swizzle mode is supported by DCE / DCN.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
ADDR_HANDLE hLib,
AddrSwizzleMode swizzleMode,
UINT_32 bpp,
bool *result)
{
ADDR_E_RETURNCODE returnCode;
V2::Lib* pLib = V2::Lib::GetLib(hLib);
if (pLib != NULL)
{
ADDR2_COMPUTE_SURFACE_INFO_INPUT in;
in.swizzleMode = swizzleMode;
in.bpp = bpp;
*result = pLib->IsValidDisplaySwizzleMode(&in);
returnCode = ADDR_OK;
}
else
{
returnCode = ADDR_ERROR;
}
return returnCode;
}

View File

@@ -3653,20 +3653,6 @@ ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
/**
****************************************************************************************************
* Addr2IsValidDisplaySwizzleMode
*
* @brief
* Return whether the swizzle mode is supported by DCE / DCN.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
ADDR_HANDLE hLib,
AddrSwizzleMode swizzleMode,
UINT_32 bpp,
bool *result);
#if defined(__cplusplus)
}
#endif

View File

@@ -36,30 +36,22 @@
#include "addrinterface.h"
// ADDR_LNX_KERNEL_BUILD is for internal build
// Moved from addrinterface.h so __KERNEL__ is not needed any more
#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__))
#include "lnx_common_defs.h" // ported from cmmqs
#elif !defined(__APPLE__) || defined(HAVE_TSERVER)
#include <assert.h>
#include <stdlib.h>
#include <string.h>
#endif
#if BRAHMA_BUILD && !defined(DEBUG)
#ifdef NDEBUG
#define DEBUG 0
#else
#define DEBUG 1
#endif
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
// Platform specific debug break defines
////////////////////////////////////////////////////////////////////////////////////////////////////
#if DEBUG
#if defined(__GNUC__)
#define ADDR_DBG_BREAK() assert(false)
#define ADDR_DBG_BREAK()
#elif defined(__APPLE__)
#define ADDR_DBG_BREAK() { IOPanic("");}
#else
@@ -79,21 +71,21 @@
#define ADDR_ANALYSIS_ASSUME(expr) do { (void)(expr); } while (0)
#endif
#if BRAHMA_BUILD
#define ADDR_ASSERT(__e) assert(__e)
#elif DEBUG
#if DEBUG
#define ADDR_ASSERT(__e) \
do { \
ADDR_ANALYSIS_ASSUME(__e); \
if ( !((__e) ? TRUE : FALSE)) { ADDR_DBG_BREAK(); } \
} while (0)
#define ADDR_ASSERT_ALWAYS() ADDR_DBG_BREAK()
#define ADDR_UNHANDLED_CASE() ADDR_ASSERT(!"Unhandled case")
#define ADDR_NOT_IMPLEMENTED() ADDR_ASSERT(!"Not implemented");
#else //DEBUG
#define ADDR_ASSERT(__e) ADDR_ANALYSIS_ASSUME(__e)
#define ADDR_ASSERT_ALWAYS()
#define ADDR_UNHANDLED_CASE()
#define ADDR_NOT_IMPLEMENTED()
#endif //DEBUG
#define ADDR_ASSERT_ALWAYS() ADDR_DBG_BREAK()
#define ADDR_UNHANDLED_CASE() ADDR_ASSERT(!"Unhandled case")
#define ADDR_NOT_IMPLEMENTED() ADDR_ASSERT(!"Not implemented");
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////

View File

@@ -178,13 +178,6 @@ public:
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
virtual BOOL_32 IsValidDisplaySwizzleMode(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);

View File

@@ -268,8 +268,7 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeCmaskInfo(
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut ///< [out] output structure
) const
{
// TODO: Clarify with AddrLib team
// ADDR_ASSERT(pIn->resourceType == ADDR_RSRC_TEX_2D);
ADDR_ASSERT(pIn->resourceType == ADDR_RSRC_TEX_2D);
UINT_32 numPipeTotal = GetPipeNumForMetaAddressing(pIn->cMaskFlags.pipeAligned,
pIn->swizzleMode);

View File

@@ -97,9 +97,6 @@ public:
return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
}
virtual BOOL_32 IsValidDisplaySwizzleMode(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
protected:
Gfx9Lib(const Client* pClient);
virtual ~Gfx9Lib();
@@ -408,6 +405,8 @@ private:
UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
Gfx9ChipSettings m_settings;
};

View File

@@ -1,63 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
files_addrlib = files(
'addrinterface.cpp',
'addrinterface.h',
'addrtypes.h',
'core/addrcommon.h',
'core/addrelemlib.cpp',
'core/addrelemlib.h',
'core/addrlib.cpp',
'core/addrlib.h',
'core/addrlib1.cpp',
'core/addrlib1.h',
'core/addrlib2.cpp',
'core/addrlib2.h',
'core/addrobject.cpp',
'core/addrobject.h',
'gfx9/chip/gfx9_enum.h',
'gfx9/coord.cpp',
'gfx9/coord.h',
'gfx9/gfx9addrlib.cpp',
'gfx9/gfx9addrlib.h',
'gfx9/rbmap.cpp',
'gfx9/rbmap.h',
'inc/chip/gfx9/gfx9_gb_reg.h',
'inc/chip/r800/si_gb_reg.h',
'inc/lnx_common_defs.h',
'r800/chip/si_ci_vi_merged_enum.h',
'r800/ciaddrlib.cpp',
'r800/ciaddrlib.h',
'r800/egbaddrlib.cpp',
'r800/egbaddrlib.h',
'r800/siaddrlib.cpp',
'r800/siaddrlib.h',
)
libamdgpu_addrlib = static_library(
'addrlib',
files_addrlib,
include_directories : include_directories(
'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
'../common', '../../'),
cpp_args : [cpp_vis_args, '-DBRAHMA_BUILD=1'],
build_by_default : false,
)

View File

@@ -747,7 +747,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
ADDR_ASSERT(((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex)) || pOut->tileIndex == Depth1DThinIndex);
ADDR_ASSERT((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex));
depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
}

View File

@@ -1,3 +0,0 @@
[*.{c,h}]
indent_style = tab
indent_size = tab

View File

@@ -252,7 +252,6 @@ void ac_shader_binary_read_config(struct ac_shader_binary *binary,
case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
case R_00B848_COMPUTE_PGM_RSRC1:
case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
conf->float_mode = G_00B028_FLOAT_MODE(value);

View File

@@ -36,32 +36,31 @@ struct ac_shader_reloc {
};
struct ac_shader_binary {
unsigned code_size;
unsigned config_size;
/** The number of bytes of config information for each global symbol.
*/
unsigned config_size_per_symbol;
unsigned rodata_size;
unsigned global_symbol_count;
unsigned reloc_count;
/** Shader code */
unsigned char *code;
unsigned code_size;
/** Config/Context register state that accompanies this shader.
* This is a stream of dword pairs. First dword contains the
* register address, the second dword contains the value.*/
unsigned char *config;
unsigned config_size;
/** The number of bytes of config information for each global symbol.
*/
unsigned config_size_per_symbol;
/** Constant data accessed by the shader. This will be uploaded
* into a constant buffer. */
unsigned char *rodata;
unsigned rodata_size;
/** List of symbol offsets for the shader */
uint64_t *global_symbol_offsets;
unsigned global_symbol_count;
struct ac_shader_reloc *relocs;
unsigned reloc_count;
/** Disassembled shader in a string. */
char *disasm_string;

View File

@@ -26,24 +26,11 @@
#include "ac_debug.h"
#ifdef HAVE_VALGRIND
#include <valgrind.h>
#include <memcheck.h>
#define VG(x) x
#else
#define VG(x)
#endif
#include <inttypes.h>
#include "sid.h"
#include "gfx9d.h"
#include "sid_tables.h"
#include "util/u_math.h"
#include "util/u_memory.h"
#include "util/u_string.h"
#include <assert.h>
/* Parsed IBs are difficult to read without colors. Use "less -R file" to
* read them, or use "aha -b -f file" to convert them to html.
@@ -56,21 +43,6 @@
#define INDENT_PKT 8
struct ac_ib_parser {
FILE *f;
uint32_t *ib;
unsigned num_dw;
const int *trace_ids;
unsigned trace_id_count;
enum chip_class chip_class;
ac_debug_addr_callback addr_callback;
void *addr_callback_data;
unsigned cur_dw;
};
static void ac_do_parse_ib(FILE *f, struct ac_ib_parser *ib);
static void print_spaces(FILE *f, unsigned num)
{
fprintf(f, "%*s", num, "");
@@ -103,108 +75,65 @@ static void print_named_value(FILE *file, const char *name, uint32_t value,
print_value(file, value, bits);
}
static const struct si_reg *find_register(const struct si_reg *table,
unsigned table_size,
unsigned offset)
void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
uint32_t field_mask)
{
for (unsigned i = 0; i < table_size; i++) {
const struct si_reg *reg = &table[i];
int r, f;
if (reg->offset == offset)
return reg;
}
return NULL;
}
void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
uint32_t value, uint32_t field_mask)
{
const struct si_reg *reg = NULL;
if (chip_class >= GFX9)
reg = find_register(gfx9d_reg_table, ARRAY_SIZE(gfx9d_reg_table), offset);
if (!reg)
reg = find_register(sid_reg_table, ARRAY_SIZE(sid_reg_table), offset);
if (reg) {
for (r = 0; r < ARRAY_SIZE(sid_reg_table); r++) {
const struct si_reg *reg = &sid_reg_table[r];
const char *reg_name = sid_strings + reg->name_offset;
bool first_field = true;
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
reg_name);
if (reg->offset == offset) {
bool first_field = true;
if (!reg->num_fields) {
print_value(file, value, 32);
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
reg_name);
if (!reg->num_fields) {
print_value(file, value, 32);
return;
}
for (f = 0; f < reg->num_fields; f++) {
const struct si_field *field = sid_fields_table + reg->fields_offset + f;
const int *values_offsets = sid_strings_offsets + field->values_offset;
uint32_t val = (value & field->mask) >>
(ffs(field->mask) - 1);
if (!(field->mask & field_mask))
continue;
/* Indent the field. */
if (!first_field)
print_spaces(file,
INDENT_PKT + strlen(reg_name) + 4);
/* Print the field. */
fprintf(file, "%s = ", sid_strings + field->name_offset);
if (val < field->num_values && values_offsets[val] >= 0)
fprintf(file, "%s\n", sid_strings + values_offsets[val]);
else
print_value(file, val,
util_bitcount(field->mask));
first_field = false;
}
return;
}
for (unsigned f = 0; f < reg->num_fields; f++) {
const struct si_field *field = sid_fields_table + reg->fields_offset + f;
const int *values_offsets = sid_strings_offsets + field->values_offset;
uint32_t val = (value & field->mask) >>
(ffs(field->mask) - 1);
if (!(field->mask & field_mask))
continue;
/* Indent the field. */
if (!first_field)
print_spaces(file,
INDENT_PKT + strlen(reg_name) + 4);
/* Print the field. */
fprintf(file, "%s = ", sid_strings + field->name_offset);
if (val < field->num_values && values_offsets[val] >= 0)
fprintf(file, "%s\n", sid_strings + values_offsets[val]);
else
print_value(file, val,
util_bitcount(field->mask));
first_field = false;
}
return;
}
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " <- 0x%08x\n", offset, value);
}
static uint32_t ac_ib_get(struct ac_ib_parser *ib)
static void ac_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
unsigned reg_offset)
{
uint32_t v = 0;
if (ib->cur_dw < ib->num_dw) {
v = ib->ib[ib->cur_dw];
#ifdef HAVE_VALGRIND
/* Help figure out where garbage data is written to IBs.
*
* Arguably we should do this already when the IBs are written,
* see RADEON_VALGRIND. The problem is that client-requests to
* Valgrind have an overhead even when Valgrind isn't running,
* and radeon_emit is performance sensitive...
*/
if (VALGRIND_CHECK_VALUE_IS_DEFINED(v))
fprintf(ib->f, COLOR_RED "Valgrind: The next DWORD is garbage"
COLOR_RESET "\n");
#endif
fprintf(ib->f, "\n\035#%08x ", v);
} else {
fprintf(ib->f, "\n\035#???????? ");
}
ib->cur_dw++;
return v;
}
static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset,
struct ac_ib_parser *ib)
{
unsigned reg_dw = ac_ib_get(ib);
unsigned reg = ((reg_dw & 0xFFFF) << 2) + reg_offset;
unsigned index = reg_dw >> 28;
unsigned reg = ((ib[1] & 0xFFFF) << 2) + reg_offset;
unsigned index = ib[1] >> 28;
int i;
if (index != 0) {
@@ -213,16 +142,17 @@ static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset
}
for (i = 0; i < count; i++)
ac_dump_reg(f, ib->chip_class, reg + i*4, ac_ib_get(ib), ~0);
ac_dump_reg(f, reg + i*4, ib[2+i], ~0);
}
static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
int *current_trace_id)
static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
int trace_id, enum chip_class chip_class,
ac_debug_addr_callback addr_callback,
void *addr_callback_data)
{
unsigned first_dw = ib->cur_dw;
int count = PKT_COUNT_G(header);
unsigned op = PKT3_IT_OPCODE_G(header);
const char *predicate = PKT3_PREDICATE(header) ? "(predicate)" : "";
unsigned count = PKT_COUNT_G(ib[0]);
unsigned op = PKT3_IT_OPCODE_G(ib[0]);
const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
int i;
/* Print the name first. */
@@ -249,213 +179,180 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
/* Print the contents. */
switch (op) {
case PKT3_SET_CONTEXT_REG:
ac_parse_set_reg_packet(f, count, SI_CONTEXT_REG_OFFSET, ib);
ac_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
break;
case PKT3_SET_CONFIG_REG:
ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib);
ac_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
break;
case PKT3_SET_UCONFIG_REG:
ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
ac_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
break;
case PKT3_SET_SH_REG:
ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
ac_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
break;
case PKT3_ACQUIRE_MEM:
ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
ac_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
ac_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
print_named_value(f, "POLL_INTERVAL", ib[6], 16);
break;
case PKT3_SURFACE_SYNC:
if (ib->chip_class >= CIK) {
ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
if (chip_class >= CIK) {
ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[3], ~0);
} else {
ac_dump_reg(f, ib->chip_class, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
ac_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
ac_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
}
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
print_named_value(f, "POLL_INTERVAL", ib[4], 16);
break;
case PKT3_EVENT_WRITE: {
uint32_t event_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
case PKT3_EVENT_WRITE:
ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "INV_L2", (event_dw >> 20) & 0x1, 1);
print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
if (count > 0) {
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_HI", ac_ib_get(ib), 16);
print_named_value(f, "ADDRESS_LO", ib[2], 32);
print_named_value(f, "ADDRESS_HI", ib[3], 16);
}
break;
}
case PKT3_EVENT_WRITE_EOP: {
uint32_t event_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
case PKT3_EVENT_WRITE_EOP:
ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (event_dw >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (event_dw >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (event_dw >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (event_dw >> 17) & 0x1, 1);
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
uint32_t addr_hi_dw = ac_ib_get(ib);
print_named_value(f, "ADDRESS_HI", addr_hi_dw, 16);
print_named_value(f, "DST_SEL", (addr_hi_dw >> 16) & 0x3, 2);
print_named_value(f, "INT_SEL", (addr_hi_dw >> 24) & 0x7, 3);
print_named_value(f, "DATA_SEL", addr_hi_dw >> 29, 3);
print_named_value(f, "DATA_LO", ac_ib_get(ib), 32);
print_named_value(f, "DATA_HI", ac_ib_get(ib), 32);
print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
print_named_value(f, "ADDRESS_LO", ib[2], 32);
print_named_value(f, "ADDRESS_HI", ib[3], 16);
print_named_value(f, "DST_SEL", (ib[3] >> 16) & 0x3, 2);
print_named_value(f, "INT_SEL", (ib[3] >> 24) & 0x7, 3);
print_named_value(f, "DATA_SEL", ib[3] >> 29, 3);
print_named_value(f, "DATA_LO", ib[4], 32);
print_named_value(f, "DATA_HI", ib[5], 32);
break;
}
case PKT3_RELEASE_MEM: {
uint32_t event_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
case PKT3_RELEASE_MEM:
ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
S_028A90_EVENT_TYPE(~0));
print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (event_dw >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (event_dw >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (event_dw >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (event_dw >> 17) & 0x1, 1);
print_named_value(f, "TC_NC_ACTION_ENA", (event_dw >> 19) & 0x1, 1);
print_named_value(f, "TC_WC_ACTION_ENA", (event_dw >> 20) & 0x1, 1);
print_named_value(f, "TC_MD_ACTION_ENA", (event_dw >> 21) & 0x1, 1);
uint32_t sel_dw = ac_ib_get(ib);
print_named_value(f, "DST_SEL", (sel_dw >> 16) & 0x3, 2);
print_named_value(f, "INT_SEL", (sel_dw >> 24) & 0x7, 3);
print_named_value(f, "DATA_SEL", sel_dw >> 29, 3);
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_HI", ac_ib_get(ib), 32);
print_named_value(f, "DATA_LO", ac_ib_get(ib), 32);
print_named_value(f, "DATA_HI", ac_ib_get(ib), 32);
print_named_value(f, "CTXID", ac_ib_get(ib), 32);
print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 0x1, 1);
print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 1);
print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 1);
print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
print_named_value(f, "TC_NC_ACTION_ENA", (ib[1] >> 19) & 0x1, 1);
print_named_value(f, "TC_WC_ACTION_ENA", (ib[1] >> 20) & 0x1, 1);
print_named_value(f, "TC_MD_ACTION_ENA", (ib[1] >> 21) & 0x1, 1);
print_named_value(f, "DST_SEL", (ib[2] >> 16) & 0x3, 2);
print_named_value(f, "INT_SEL", (ib[2] >> 24) & 0x7, 3);
print_named_value(f, "DATA_SEL", ib[2] >> 29, 3);
print_named_value(f, "ADDRESS_LO", ib[3], 32);
print_named_value(f, "ADDRESS_HI", ib[4], 32);
print_named_value(f, "DATA_LO", ib[5], 32);
print_named_value(f, "DATA_HI", ib[6], 32);
print_named_value(f, "CTXID", ib[7], 32);
break;
}
case PKT3_WAIT_REG_MEM:
print_named_value(f, "OP", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_LO", ac_ib_get(ib), 32);
print_named_value(f, "ADDRESS_HI", ac_ib_get(ib), 32);
print_named_value(f, "REF", ac_ib_get(ib), 32);
print_named_value(f, "MASK", ac_ib_get(ib), 32);
print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
print_named_value(f, "OP", ib[1], 32);
print_named_value(f, "ADDRESS_LO", ib[2], 32);
print_named_value(f, "ADDRESS_HI", ib[3], 32);
print_named_value(f, "REF", ib[4], 32);
print_named_value(f, "MASK", ib[5], 32);
print_named_value(f, "POLL_INTERVAL", ib[6], 16);
break;
case PKT3_DRAW_INDEX_AUTO:
ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
break;
case PKT3_DRAW_INDEX_2:
ac_dump_reg(f, ib->chip_class, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
ac_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
ac_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
break;
case PKT3_INDEX_TYPE:
ac_dump_reg(f, ib->chip_class, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
break;
case PKT3_NUM_INSTANCES:
ac_dump_reg(f, ib->chip_class, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
break;
case PKT3_WRITE_DATA:
ac_dump_reg(f, ib->chip_class, R_370_CONTROL, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0);
/* The payload is written automatically */
ac_dump_reg(f, R_370_CONTROL, ib[1], ~0);
ac_dump_reg(f, R_371_DST_ADDR_LO, ib[2], ~0);
ac_dump_reg(f, R_372_DST_ADDR_HI, ib[3], ~0);
for (i = 2; i < count; i++) {
print_spaces(f, INDENT_PKT);
fprintf(f, "0x%08x\n", ib[2+i]);
}
break;
case PKT3_CP_DMA:
ac_dump_reg(f, ib->chip_class, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_410_CP_DMA_WORD0, ib[1], ~0);
ac_dump_reg(f, R_411_CP_DMA_WORD1, ib[2], ~0);
ac_dump_reg(f, R_412_CP_DMA_WORD2, ib[3], ~0);
ac_dump_reg(f, R_413_CP_DMA_WORD3, ib[4], ~0);
ac_dump_reg(f, R_414_COMMAND, ib[5], ~0);
break;
case PKT3_DMA_DATA:
ac_dump_reg(f, ib->chip_class, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0);
ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
ac_dump_reg(f, R_500_DMA_DATA_WORD0, ib[1], ~0);
ac_dump_reg(f, R_501_SRC_ADDR_LO, ib[2], ~0);
ac_dump_reg(f, R_502_SRC_ADDR_HI, ib[3], ~0);
ac_dump_reg(f, R_503_DST_ADDR_LO, ib[4], ~0);
ac_dump_reg(f, R_504_DST_ADDR_HI, ib[5], ~0);
ac_dump_reg(f, R_414_COMMAND, ib[6], ~0);
break;
case PKT3_INDIRECT_BUFFER_SI:
case PKT3_INDIRECT_BUFFER_CONST:
case PKT3_INDIRECT_BUFFER_CIK: {
uint32_t base_lo_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
uint32_t base_hi_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_3F1_IB_BASE_HI, base_hi_dw, ~0);
uint32_t control_dw = ac_ib_get(ib);
ac_dump_reg(f, ib->chip_class, R_3F2_CONTROL, control_dw, ~0);
case PKT3_INDIRECT_BUFFER_CIK:
ac_dump_reg(f, R_3F0_IB_BASE_LO, ib[1], ~0);
ac_dump_reg(f, R_3F1_IB_BASE_HI, ib[2], ~0);
ac_dump_reg(f, R_3F2_CONTROL, ib[3], ~0);
if (!ib->addr_callback)
break;
if (addr_callback) {
uint64_t addr = ((uint64_t)ib[2] << 32) | ib[1];
void *data = addr_callback(addr_callback_data, addr);
const char *name = G_3F2_CHAIN(ib[3]) ? "chained" : "nested";
uint64_t addr = ((uint64_t)base_hi_dw << 32) | base_lo_dw;
void *data = ib->addr_callback(ib->addr_callback_data, addr);
if (!data)
break;
if (G_3F2_CHAIN(control_dw)) {
ib->ib = data;
ib->num_dw = G_3F2_IB_SIZE(control_dw);
ib->cur_dw = 0;
return;
if (data)
ac_parse_ib(f, data, G_3F2_IB_SIZE(ib[3]),
trace_id, name, chip_class,
addr_callback, addr_callback_data);
}
struct ac_ib_parser ib_recurse;
memcpy(&ib_recurse, ib, sizeof(ib_recurse));
ib_recurse.ib = data;
ib_recurse.num_dw = G_3F2_IB_SIZE(control_dw);
ib_recurse.cur_dw = 0;
if(ib_recurse.trace_id_count) {
if (*current_trace_id == *ib->trace_ids) {
++ib_recurse.trace_ids;
--ib_recurse.trace_id_count;
} else {
ib_recurse.trace_id_count = 0;
}
}
fprintf(f, "\n\035>------------------ nested begin ------------------\n");
ac_do_parse_ib(f, &ib_recurse);
fprintf(f, "\n\035<------------------- nested end -------------------\n");
break;
}
case PKT3_CLEAR_STATE:
case PKT3_INCREMENT_DE_COUNTER:
case PKT3_PFP_SYNC_ME:
break;
case PKT3_NOP:
if (header == 0xffff1000) {
if (ib[0] == 0xffff1000) {
count = -1; /* One dword NOP. */
} else if (count == 0 && ib->cur_dw < ib->num_dw &&
AC_IS_TRACE_POINT(ib->ib[ib->cur_dw])) {
unsigned packet_id = AC_GET_TRACE_POINT_ID(ib->ib[ib->cur_dw]);
break;
} else if (count == 0 && AC_IS_TRACE_POINT(ib[1])) {
unsigned packet_id = AC_GET_TRACE_POINT_ID(ib[1]);
print_spaces(f, INDENT_PKT);
fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
if (!ib->trace_id_count)
if (trace_id == -1)
break; /* tracing was disabled */
*current_trace_id = packet_id;
print_spaces(f, INDENT_PKT);
if (packet_id < *ib->trace_ids)
if (packet_id < trace_id)
fprintf(f, COLOR_RED
"This trace point was reached by the CP."
COLOR_RESET "\n");
else if (packet_id == *ib->trace_ids)
else if (packet_id == trace_id)
fprintf(f, COLOR_RED
"!!!!! This is the last trace point that "
"was reached by the CP !!!!!"
COLOR_RESET "\n");
else if (packet_id+1 == *ib->trace_ids)
else if (packet_id+1 == trace_id)
fprintf(f, COLOR_RED
"!!!!! This is the first trace point that "
"was NOT been reached by the CP !!!!!"
@@ -467,127 +364,17 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
COLOR_RESET "\n");
break;
}
break;
}
/* print additional dwords */
while (ib->cur_dw <= first_dw + count)
ac_ib_get(ib);
if (ib->cur_dw > first_dw + count + 1)
fprintf(f, COLOR_RED "\n!!!!! count in header too low !!!!!"
COLOR_RESET "\n");
}
/**
* Parse and print an IB into a file.
*/
static void ac_do_parse_ib(FILE *f, struct ac_ib_parser *ib)
{
int current_trace_id = -1;
while (ib->cur_dw < ib->num_dw) {
uint32_t header = ac_ib_get(ib);
unsigned type = PKT_TYPE_G(header);
switch (type) {
case 3:
ac_parse_packet3(f, header, ib, &current_trace_id);
break;
case 2:
/* type-2 nop */
if (header == 0x80000000) {
fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
break;
}
/* fall through */
default:
fprintf(f, "Unknown packet type %i\n", type);
break;
/* fall through, print all dwords */
default:
for (i = 0; i < count+1; i++) {
print_spaces(f, INDENT_PKT);
fprintf(f, "0x%08x\n", ib[1+i]);
}
}
}
static void format_ib_output(FILE *f, char *out)
{
unsigned depth = 0;
for (;;) {
char op = 0;
if (out[0] == '\n' && out[1] == '\035')
out++;
if (out[0] == '\035') {
op = out[1];
out += 2;
}
if (op == '<')
depth--;
unsigned indent = 4 * depth;
if (op != '#')
indent += 9;
if (indent)
print_spaces(f, indent);
char *end = util_strchrnul(out, '\n');
fwrite(out, end - out, 1, f);
fputc('\n', f); /* always end with a new line */
if (!*end)
break;
out = end + 1;
if (op == '>')
depth++;
}
}
/**
* Parse and print an IB into a file.
*
* \param f file
* \param ib_ptr IB
* \param num_dw size of the IB
* \param chip_class chip class
* \param trace_ids the last trace IDs that are known to have been reached
* and executed by the CP, typically read from a buffer
* \param trace_id_count The number of entries in the trace_ids array.
* \param addr_callback Get a mapped pointer of the IB at a given address. Can
* be NULL.
* \param addr_callback_data user data for addr_callback
*/
void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_ids,
unsigned trace_id_count, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data)
{
struct ac_ib_parser ib = {};
ib.ib = ib_ptr;
ib.num_dw = num_dw;
ib.trace_ids = trace_ids;
ib.trace_id_count = trace_id_count;
ib.chip_class = chip_class;
ib.addr_callback = addr_callback;
ib.addr_callback_data = addr_callback_data;
char *out;
size_t outsize;
FILE *memf = open_memstream(&out, &outsize);
ib.f = memf;
ac_do_parse_ib(memf, &ib);
fclose(memf);
if (out) {
format_ib_output(f, out);
free(out);
}
if (ib.cur_dw > ib.num_dw) {
printf("\nPacket ends after the end of IB.\n");
exit(1);
}
ib += count + 2;
*num_dw -= count + 2;
return ib;
}
/**
@@ -597,203 +384,46 @@ void ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_i
* \param ib IB
* \param num_dw size of the IB
* \param chip_class chip class
* \param trace_ids the last trace IDs that are known to have been reached
* \param trace_id the last trace ID that is known to have been reached
* and executed by the CP, typically read from a buffer
* \param trace_id_count The number of entries in the trace_ids array.
* \param addr_callback Get a mapped pointer of the IB at a given address. Can
* be NULL.
* \param addr_callback_data user data for addr_callback
*/
void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
unsigned trace_id_count, const char *name,
enum chip_class chip_class, ac_debug_addr_callback addr_callback,
void *addr_callback_data)
void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
const char *name, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data)
{
fprintf(f, "------------------ %s begin ------------------\n", name);
ac_parse_ib_chunk(f, ib, num_dw, trace_ids, trace_id_count,
chip_class, addr_callback, addr_callback_data);
while (num_dw > 0) {
unsigned type = PKT_TYPE_G(ib[0]);
fprintf(f, "------------------- %s end -------------------\n\n", name);
}
/**
* Parse dmesg and return TRUE if a VM fault has been detected.
*
* \param chip_class chip class
* \param old_dmesg_timestamp previous dmesg timestamp parsed at init time
* \param out_addr detected VM fault addr
*/
bool ac_vm_fault_occured(enum chip_class chip_class,
uint64_t *old_dmesg_timestamp, uint64_t *out_addr)
{
char line[2000];
unsigned sec, usec;
int progress = 0;
uint64_t dmesg_timestamp = 0;
bool fault = false;
FILE *p = popen("dmesg", "r");
if (!p)
return false;
while (fgets(line, sizeof(line), p)) {
char *msg, len;
if (!line[0] || line[0] == '\n')
continue;
/* Get the timestamp. */
if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
static bool hit = false;
if (!hit) {
fprintf(stderr, "%s: failed to parse line '%s'\n",
__func__, line);
hit = true;
}
continue;
}
dmesg_timestamp = sec * 1000000ull + usec;
/* If just updating the timestamp. */
if (!out_addr)
continue;
/* Process messages only if the timestamp is newer. */
if (dmesg_timestamp <= *old_dmesg_timestamp)
continue;
/* Only process the first VM fault. */
if (fault)
continue;
/* Remove trailing \n */
len = strlen(line);
if (len && line[len-1] == '\n')
line[len-1] = 0;
/* Get the message part. */
msg = strchr(line, ']');
if (!msg)
continue;
msg++;
const char *header_line, *addr_line_prefix, *addr_line_format;
if (chip_class >= GFX9) {
/* Match this:
* ..: [gfxhub] VMC page fault (src_id:0 ring:158 vm_id:2 pas_id:0)
* ..: at page 0x0000000219f8f000 from 27
* ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
*/
header_line = "VMC page fault";
addr_line_prefix = " at page";
addr_line_format = "%"PRIx64;
} else {
header_line = "GPU fault detected:";
addr_line_prefix = "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
addr_line_format = "%"PRIX64;
}
switch (progress) {
case 0:
if (strstr(msg, header_line))
progress = 1;
switch (type) {
case 3:
ib = ac_parse_packet3(f, ib, &num_dw, trace_id,
chip_class, addr_callback,
addr_callback_data);
break;
case 1:
msg = strstr(msg, addr_line_prefix);
if (msg) {
msg = strstr(msg, "0x");
if (msg) {
msg += 2;
if (sscanf(msg, addr_line_format, out_addr) == 1)
fault = true;
}
case 2:
/* type-2 nop */
if (ib[0] == 0x80000000) {
fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
ib++;
num_dw--;
break;
}
progress = 0;
break;
/* fall through */
default:
progress = 0;
}
}
pclose(p);
if (dmesg_timestamp > *old_dmesg_timestamp)
*old_dmesg_timestamp = dmesg_timestamp;
return fault;
}
static int compare_wave(const void *p1, const void *p2)
{
struct ac_wave_info *w1 = (struct ac_wave_info *)p1;
struct ac_wave_info *w2 = (struct ac_wave_info *)p2;
/* Sort waves according to PC and then SE, SH, CU, etc. */
if (w1->pc < w2->pc)
return -1;
if (w1->pc > w2->pc)
return 1;
if (w1->se < w2->se)
return -1;
if (w1->se > w2->se)
return 1;
if (w1->sh < w2->sh)
return -1;
if (w1->sh > w2->sh)
return 1;
if (w1->cu < w2->cu)
return -1;
if (w1->cu > w2->cu)
return 1;
if (w1->simd < w2->simd)
return -1;
if (w1->simd > w2->simd)
return 1;
if (w1->wave < w2->wave)
return -1;
if (w1->wave > w2->wave)
return 1;
return 0;
}
/* Return wave information. "waves" should be a large enough array. */
unsigned ac_get_wave_info(struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP])
{
char line[2000];
unsigned num_waves = 0;
FILE *p = popen("umr -wa", "r");
if (!p)
return 0;
if (!fgets(line, sizeof(line), p) ||
strncmp(line, "SE", 2) != 0) {
pclose(p);
return 0;
}
while (fgets(line, sizeof(line), p)) {
struct ac_wave_info *w;
uint32_t pc_hi, pc_lo, exec_hi, exec_lo;
assert(num_waves < AC_MAX_WAVES_PER_CHIP);
w = &waves[num_waves];
if (sscanf(line, "%u %u %u %u %u %x %x %x %x %x %x %x",
&w->se, &w->sh, &w->cu, &w->simd, &w->wave,
&w->status, &pc_hi, &pc_lo, &w->inst_dw0,
&w->inst_dw1, &exec_hi, &exec_lo) == 12) {
w->pc = ((uint64_t)pc_hi << 32) | pc_lo;
w->exec = ((uint64_t)exec_hi << 32) | exec_lo;
w->matched = false;
num_waves++;
fprintf(f, "Unknown packet type %i\n", type);
return;
}
}
qsort(waves, num_waves, sizeof(struct ac_wave_info), compare_wave);
pclose(p);
return num_waves;
fprintf(f, "------------------- %s end -------------------\n", name);
if (num_dw < 0) {
printf("Packet ends after the end of IB.\n");
exit(0);
}
fprintf(f, "\n");
}

View File

@@ -28,7 +28,6 @@
#include <stdint.h>
#include <stdio.h>
#include <stdbool.h>
#include "amd_family.h"
@@ -36,36 +35,12 @@
#define AC_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
#define AC_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
#define AC_MAX_WAVES_PER_CHIP (64 * 40)
struct ac_wave_info {
unsigned se; /* shader engine */
unsigned sh; /* shader array */
unsigned cu; /* compute unit */
unsigned simd;
unsigned wave;
uint32_t status;
uint64_t pc; /* program counter */
uint32_t inst_dw0;
uint32_t inst_dw1;
uint64_t exec;
bool matched; /* whether the wave is used by a currently-bound shader */
};
typedef void *(*ac_debug_addr_callback)(void *data, uint64_t addr);
void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
uint32_t value, uint32_t field_mask);
void ac_parse_ib_chunk(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
unsigned trace_id_count, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data);
void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
unsigned trace_id_count, const char *name, enum chip_class chip_class,
void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
uint32_t field_mask);
void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, int trace_id,
const char *name, enum chip_class chip_class,
ac_debug_addr_callback addr_callback, void *addr_callback_data);
bool ac_vm_fault_occured(enum chip_class chip_class,
uint64_t *old_dmesg_timestamp, uint64_t *out_addr);
unsigned ac_get_wave_info(struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]);
#endif

View File

@@ -100,6 +100,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
uint32_t unused_feature;
int r, i, j;
drmDevicePtr devinfo;
@@ -175,24 +176,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
&info->me_fw_version,
&info->me_fw_feature);
&info->me_fw_version, &unused_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
&info->pfp_fw_version,
&info->pfp_fw_feature);
&info->pfp_fw_version, &unused_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
&info->ce_fw_version,
&info->ce_fw_feature);
&info->ce_fw_version, &unused_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
return false;
@@ -269,8 +267,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
vce.available_rings ? vce_version : 0;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
@@ -318,30 +314,3 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return true;
}
void ac_compute_driver_uuid(char *uuid, size_t size)
{
char amd_uuid[] = "AMD-MESA-DRV";
assert(size >= sizeof(amd_uuid));
memset(uuid, 0, size);
strncpy(uuid, amd_uuid, size);
}
void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
{
uint32_t *uint_uuid = (uint32_t*)uuid;
assert(size >= sizeof(uint32_t)*4);
/**
* Use the device info directly instead of using a sha1. GL/VK UUIDs
* are 16 byte vs 20 byte for sha1, and the truncation that would be
* required would get rid of part of the little entropy we have.
* */
memset(uuid, 0, size);
uint_uuid[0] = info->pci_domain;
uint_uuid[1] = info->pci_bus;
uint_uuid[2] = info->pci_dev;
uint_uuid[3] = info->pci_func;
}

View File

@@ -26,7 +26,6 @@
#ifndef AC_GPU_INFO_H
#define AC_GPU_INFO_H
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "amd_family.h"
@@ -66,11 +65,8 @@ struct radeon_info {
uint32_t uvd_fw_version;
uint32_t vce_fw_version;
uint32_t me_fw_version;
uint32_t me_fw_feature;
uint32_t pfp_fw_version;
uint32_t pfp_fw_feature;
uint32_t ce_fw_version;
uint32_t ce_fw_feature;
uint32_t vce_harvest_config;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
@@ -81,8 +77,6 @@ struct radeon_info {
uint32_t drm_patchlevel;
bool has_userptr;
bool has_syncobj;
bool has_sync_file;
bool has_ctx_priority;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
@@ -112,10 +106,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo);
void ac_compute_driver_uuid(char *uuid, size_t size);
void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
#ifdef __cplusplus
}
#endif

View File

@@ -36,7 +36,6 @@
#include "ac_exp_param.h"
#include "util/bitscan.h"
#include "util/macros.h"
#include "util/u_atomic.h"
#include "sid.h"
#include "shader_enums.h"
@@ -92,92 +91,6 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
}
unsigned
ac_get_type_size(LLVMTypeRef type)
{
LLVMTypeKind kind = LLVMGetTypeKind(type);
switch (kind) {
case LLVMIntegerTypeKind:
return LLVMGetIntTypeWidth(type) / 8;
case LLVMFloatTypeKind:
return 4;
case LLVMDoubleTypeKind:
case LLVMPointerTypeKind:
return 8;
case LLVMVectorTypeKind:
return LLVMGetVectorSize(type) *
ac_get_type_size(LLVMGetElementType(type));
case LLVMArrayTypeKind:
return LLVMGetArrayLength(type) *
ac_get_type_size(LLVMGetElementType(type));
default:
assert(0);
return 0;
}
}
static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
{
if (t == ctx->f16 || t == ctx->i16)
return ctx->i16;
else if (t == ctx->f32 || t == ctx->i32)
return ctx->i32;
else if (t == ctx->f64 || t == ctx->i64)
return ctx->i64;
else
unreachable("Unhandled integer size");
}
LLVMTypeRef
ac_to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
{
if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
LLVMTypeRef elem_type = LLVMGetElementType(t);
return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
LLVMGetVectorSize(t));
}
return to_integer_type_scalar(ctx, t);
}
LLVMValueRef
ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
{
LLVMTypeRef type = LLVMTypeOf(v);
return LLVMBuildBitCast(ctx->builder, v, ac_to_integer_type(ctx, type), "");
}
static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
{
if (t == ctx->i16 || t == ctx->f16)
return ctx->f16;
else if (t == ctx->i32 || t == ctx->f32)
return ctx->f32;
else if (t == ctx->i64 || t == ctx->f64)
return ctx->f64;
else
unreachable("Unhandled float size");
}
LLVMTypeRef
ac_to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
{
if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
LLVMTypeRef elem_type = LLVMGetElementType(t);
return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
LLVMGetVectorSize(t));
}
return to_float_type_scalar(ctx, t);
}
LLVMValueRef
ac_to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
{
LLVMTypeRef type = LLVMTypeOf(v);
return LLVMBuildBitCast(ctx->builder, v, ac_to_float_type(ctx, type), "");
}
LLVMValueRef
ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
LLVMTypeRef return_type, LLVMValueRef *params,
@@ -215,6 +128,20 @@ ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
return call;
}
static LLVMValueRef bitcast_to_float(struct ac_llvm_context *ctx,
LLVMValueRef value)
{
LLVMTypeRef type = LLVMTypeOf(value);
LLVMTypeRef new_type;
if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
new_type = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
else
new_type = ctx->f32;
return LLVMBuildBitCast(ctx->builder, value, new_type, "");
}
/**
* Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
* intrinsic names).
@@ -266,117 +193,18 @@ ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
return phi;
}
/* Prevent optimizations (at least of memory accesses) across the current
* point in the program by emitting empty inline assembly that is marked as
* having side effects.
*
* Optionally, a value can be passed through the inline assembly to prevent
* LLVM from hoisting calls to ReadNone functions.
*/
void
ac_build_optimization_barrier(struct ac_llvm_context *ctx,
LLVMValueRef *pvgpr)
{
static int counter = 0;
LLVMBuilderRef builder = ctx->builder;
char code[16];
snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
if (!pvgpr) {
LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
LLVMBuildCall(builder, inlineasm, NULL, 0, "");
} else {
LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
LLVMValueRef vgpr = *pvgpr;
LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
unsigned vgpr_size = ac_get_type_size(vgpr_type);
LLVMValueRef vgpr0;
assert(vgpr_size % 4 == 0);
vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
*pvgpr = vgpr;
}
}
LLVMValueRef
ac_build_ballot(struct ac_llvm_context *ctx,
LLVMValueRef value)
{
LLVMValueRef args[3] = {
value,
ctx->i32_0,
LLVMConstInt(ctx->i32, LLVMIntNE, 0)
};
/* We currently have no other way to prevent LLVM from lifting the icmp
* calls to a dominating basic block.
*/
ac_build_optimization_barrier(ctx, &args[0]);
if (LLVMTypeOf(args[0]) != ctx->i32)
args[0] = LLVMBuildBitCast(ctx->builder, args[0], ctx->i32, "");
return ac_build_intrinsic(ctx,
"llvm.amdgcn.icmp.i32",
ctx->i64, args, 3,
AC_FUNC_ATTR_NOUNWIND |
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
}
LLVMValueRef
ac_build_vote_all(struct ac_llvm_context *ctx, LLVMValueRef value)
{
LLVMValueRef active_set = ac_build_ballot(ctx, ctx->i32_1);
LLVMValueRef vote_set = ac_build_ballot(ctx, value);
return LLVMBuildICmp(ctx->builder, LLVMIntEQ, vote_set, active_set, "");
}
LLVMValueRef
ac_build_vote_any(struct ac_llvm_context *ctx, LLVMValueRef value)
{
LLVMValueRef vote_set = ac_build_ballot(ctx, value);
return LLVMBuildICmp(ctx->builder, LLVMIntNE, vote_set,
LLVMConstInt(ctx->i64, 0, 0), "");
}
LLVMValueRef
ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value)
{
LLVMValueRef active_set = ac_build_ballot(ctx, ctx->i32_1);
LLVMValueRef vote_set = ac_build_ballot(ctx, value);
LLVMValueRef all = LLVMBuildICmp(ctx->builder, LLVMIntEQ,
vote_set, active_set, "");
LLVMValueRef none = LLVMBuildICmp(ctx->builder, LLVMIntEQ,
vote_set,
LLVMConstInt(ctx->i64, 0, 0), "");
return LLVMBuildOr(ctx->builder, all, none, "");
}
LLVMValueRef
ac_build_gather_values_extended(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count,
unsigned value_stride,
bool load,
bool always_vector)
bool load)
{
LLVMBuilderRef builder = ctx->builder;
LLVMValueRef vec = NULL;
unsigned i;
if (value_count == 1 && !always_vector) {
if (value_count == 1) {
if (load)
return LLVMBuildLoad(builder, values[0], "");
return values[0];
@@ -401,7 +229,7 @@ ac_build_gather_values(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count)
{
return ac_build_gather_values_extended(ctx, values, value_count, 1, false, false);
return ac_build_gather_values_extended(ctx, values, value_count, 1, false);
}
LLVMValueRef
@@ -452,13 +280,12 @@ build_cube_intrinsic(struct ac_llvm_context *ctx,
* selcoords.ma; i.e., a positive out_ma means that coords is pointed towards
* the selcoords major axis.
*/
static void build_cube_select(struct ac_llvm_context *ctx,
static void build_cube_select(LLVMBuilderRef builder,
const struct cube_selection_coords *selcoords,
const LLVMValueRef *coords,
LLVMValueRef *out_st,
LLVMValueRef *out_ma)
{
LLVMBuilderRef builder = ctx->builder;
LLVMTypeRef f32 = LLVMTypeOf(coords[0]);
LLVMValueRef is_ma_positive;
LLVMValueRef sgn_ma;
@@ -495,9 +322,9 @@ static void build_cube_select(struct ac_llvm_context *ctx,
/* Select ma */
tmp = LLVMBuildSelect(builder, is_ma_z, coords[2],
LLVMBuildSelect(builder, is_ma_y, coords[1], coords[0], ""), "");
tmp = ac_build_intrinsic(ctx, "llvm.fabs.f32",
ctx->f32, &tmp, 1, AC_FUNC_ATTR_READNONE);
*out_ma = LLVMBuildFMul(builder, tmp, LLVMConstReal(f32, 2.0), "");
sgn = LLVMBuildSelect(builder, is_ma_positive,
LLVMConstReal(f32, 2.0), LLVMConstReal(f32, -2.0), "");
*out_ma = LLVMBuildFMul(builder, tmp, sgn, "");
}
void
@@ -585,7 +412,7 @@ ac_prepare_cube_coords(struct ac_llvm_context *ctx,
* seems awfully quiet about how textureGrad for cube
* maps should be handled.
*/
build_cube_select(ctx, &selcoords, &derivs_arg[axis * 3],
build_cube_select(builder, &selcoords, &derivs_arg[axis * 3],
deriv_st, &deriv_ma);
deriv_ma = LLVMBuildFMul(builder, deriv_ma, invma, "");
@@ -717,42 +544,34 @@ ac_build_indexed_store(struct ac_llvm_context *ctx,
* \param base_ptr Where the array starts.
* \param index The element index into the array.
* \param uniform Whether the base_ptr and index can be assumed to be
* dynamically uniform (i.e. load to an SGPR)
* \param invariant Whether the load is invariant (no other opcodes affect it)
* dynamically uniform
*/
static LLVMValueRef
ac_build_load_custom(struct ac_llvm_context *ctx, LLVMValueRef base_ptr,
LLVMValueRef index, bool uniform, bool invariant)
LLVMValueRef
ac_build_indexed_load(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index,
bool uniform)
{
LLVMValueRef pointer, result;
LLVMValueRef pointer;
pointer = ac_build_gep0(ctx, base_ptr, index);
if (uniform)
LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
result = LLVMBuildLoad(ctx->builder, pointer, "");
if (invariant)
LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
return LLVMBuildLoad(ctx->builder, pointer, "");
}
/**
* Do a load from &base_ptr[index], but also add a flag that it's loading
* a constant from a dynamically uniform index.
*/
LLVMValueRef
ac_build_indexed_load_const(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index)
{
LLVMValueRef result = ac_build_indexed_load(ctx, base_ptr, index, true);
LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
return result;
}
LLVMValueRef ac_build_load(struct ac_llvm_context *ctx, LLVMValueRef base_ptr,
LLVMValueRef index)
{
return ac_build_load_custom(ctx, base_ptr, index, false, false);
}
LLVMValueRef ac_build_load_invariant(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index)
{
return ac_build_load_custom(ctx, base_ptr, index, false, true);
}
LLVMValueRef ac_build_load_to_sgpr(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index)
{
return ac_build_load_custom(ctx, base_ptr, index, true, true);
}
/* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
* The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
* or v4i32 (num_channels=3,4).
@@ -768,13 +587,10 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
bool glc,
bool slc,
bool writeonly_memory,
bool swizzle_enable_hint)
bool has_add_tid)
{
/* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
* (voffset is swizzled, but soffset isn't swizzled).
* llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
*/
if (!swizzle_enable_hint) {
/* TODO: Fix stores with ADD_TID and remove the "has_add_tid" flag. */
if (!has_add_tid) {
/* Split 3 channel stores, becase LLVM doesn't support 3-channel
* intrinsics. */
if (num_channels == 3) {
@@ -788,11 +604,11 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,
soffset, inst_offset, glc, slc,
writeonly_memory, swizzle_enable_hint);
writeonly_memory, has_add_tid);
ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
soffset, inst_offset + 8,
glc, slc,
writeonly_memory, swizzle_enable_hint);
writeonly_memory, has_add_tid);
return;
}
@@ -808,7 +624,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
offset = LLVMBuildAdd(ctx->builder, offset, voffset, "");
LLVMValueRef args[] = {
ac_to_float(ctx, vdata),
bitcast_to_float(ctx, vdata),
LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, ""),
LLVMConstInt(ctx->i32, 0, 0),
offset,
@@ -1025,6 +841,7 @@ ac_get_thread_id(struct ac_llvm_context *ctx)
*/
LLVMValueRef
ac_build_ddxy(struct ac_llvm_context *ctx,
bool has_ds_bpermute,
uint32_t mask,
int idx,
LLVMValueRef val)
@@ -1032,7 +849,7 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
LLVMValueRef tl, trbl, args[2];
LLVMValueRef result;
if (ctx->chip_class >= VI) {
if (has_ds_bpermute) {
LLVMValueRef thread_id, tl_tid, trbl_tid;
thread_id = ac_get_thread_id(ctx);
@@ -1059,7 +876,7 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
} else {
uint32_t masks[2] = {};
uint32_t masks[2];
switch (mask) {
case AC_TID_MASK_TOP_LEFT:
@@ -1078,8 +895,6 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
masks[0] = 0x80a0;
masks[1] = 0x80f5;
break;
default:
assert(0);
}
args[0] = val;
@@ -1168,13 +983,6 @@ ac_build_umsb(struct ac_llvm_context *ctx,
LLVMConstInt(ctx->i32, -1, true), msb, "");
}
LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
LLVMValueRef b)
{
LLVMValueRef cmp = LLVMBuildICmp(ctx->builder, LLVMIntULE, a, b, "");
return LLVMBuildSelect(ctx->builder, cmp, a, b, "");
}
LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
{
if (HAVE_LLVM >= 0x0500) {
@@ -1266,7 +1074,7 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
a->opcode == ac_image_get_lod;
if (sample)
args[num_args++] = ac_to_float(ctx, a->addr);
args[num_args++] = bitcast_to_float(ctx, a->addr);
else
args[num_args++] = a->addr;
@@ -1734,11 +1542,3 @@ void ac_optimize_vs_outputs(struct ac_llvm_context *ctx,
*num_param_exports = exports.num;
}
}
void ac_init_exec_full_mask(struct ac_llvm_context *ctx)
{
LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
ac_build_intrinsic(ctx,
"llvm.amdgcn.init.exec", ctx->voidt,
&full_mask, 1, AC_FUNC_ATTR_CONVERGENT);
}

View File

@@ -71,13 +71,6 @@ void
ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
enum chip_class chip_class);
unsigned ac_get_type_size(LLVMTypeRef type);
LLVMTypeRef ac_to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
LLVMValueRef ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v);
LLVMTypeRef ac_to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
LLVMValueRef ac_to_float(struct ac_llvm_context *ctx, LLVMValueRef v);
LLVMValueRef
ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
LLVMTypeRef return_type, LLVMValueRef *params,
@@ -90,24 +83,12 @@ ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
unsigned count_incoming, LLVMValueRef *values,
LLVMBasicBlockRef *blocks);
void ac_build_optimization_barrier(struct ac_llvm_context *ctx,
LLVMValueRef *pvgpr);
LLVMValueRef ac_build_ballot(struct ac_llvm_context *ctx, LLVMValueRef value);
LLVMValueRef ac_build_vote_all(struct ac_llvm_context *ctx, LLVMValueRef value);
LLVMValueRef ac_build_vote_any(struct ac_llvm_context *ctx, LLVMValueRef value);
LLVMValueRef ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value);
LLVMValueRef
ac_build_gather_values_extended(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count,
unsigned value_stride,
bool load,
bool always_vector);
bool load);
LLVMValueRef
ac_build_gather_values(struct ac_llvm_context *ctx,
LLVMValueRef *values,
@@ -150,12 +131,14 @@ ac_build_indexed_store(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index,
LLVMValueRef value);
LLVMValueRef ac_build_load(struct ac_llvm_context *ctx, LLVMValueRef base_ptr,
LLVMValueRef index);
LLVMValueRef ac_build_load_invariant(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index);
LLVMValueRef ac_build_load_to_sgpr(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index);
LLVMValueRef
ac_build_indexed_load(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index,
bool uniform);
LLVMValueRef
ac_build_indexed_load_const(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr, LLVMValueRef index);
void
ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
@@ -168,7 +151,7 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
bool glc,
bool slc,
bool writeonly_memory,
bool swizzle_enable_hint);
bool has_add_tid);
LLVMValueRef
ac_build_buffer_load(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
@@ -197,6 +180,7 @@ ac_get_thread_id(struct ac_llvm_context *ctx);
LLVMValueRef
ac_build_ddxy(struct ac_llvm_context *ctx,
bool has_ds_bpermute,
uint32_t mask,
int idx,
LLVMValueRef val);
@@ -221,7 +205,6 @@ LLVMValueRef ac_build_umsb(struct ac_llvm_context *ctx,
LLVMValueRef arg,
LLVMTypeRef dst_type);
LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a, LLVMValueRef b);
LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value);
struct ac_export_args {
@@ -281,7 +264,6 @@ void ac_optimize_vs_outputs(struct ac_llvm_context *ac,
uint8_t *vs_output_param_offset,
uint32_t num_outputs,
uint8_t *num_param_exports);
void ac_init_exec_full_mask(struct ac_llvm_context *ctx);
#ifdef __cplusplus
}
#endif

File diff suppressed because it is too large Load Diff

View File

@@ -30,14 +30,12 @@
#include "amd_family.h"
#include "../vulkan/radv_descriptor_set.h"
#include "ac_shader_info.h"
#include "compiler/shader_enums.h"
#include "shader_enums.h"
struct ac_shader_binary;
struct ac_shader_config;
struct nir_shader;
struct radv_pipeline_layout;
struct ac_llvm_context;
struct ac_shader_abi;
struct ac_vs_variant_key {
uint32_t instance_rate_inputs;
@@ -52,35 +50,28 @@ struct ac_tes_variant_key {
};
struct ac_tcs_variant_key {
struct ac_vs_variant_key vs_key;
unsigned primitive_mode;
unsigned input_vertices;
uint32_t tes_reads_tess_factors:1;
};
struct ac_fs_variant_key {
uint32_t col_format;
uint32_t is_int8;
uint32_t is_int10;
uint32_t multisample : 1;
};
struct ac_shader_variant_key {
union {
struct ac_vs_variant_key vs;
struct ac_fs_variant_key fs;
struct ac_tes_variant_key tes;
struct ac_tcs_variant_key tcs;
};
bool has_multiview_view_index;
union ac_shader_variant_key {
struct ac_vs_variant_key vs;
struct ac_fs_variant_key fs;
struct ac_tes_variant_key tes;
struct ac_tcs_variant_key tcs;
};
struct ac_nir_compiler_options {
struct radv_pipeline_layout *layout;
struct ac_shader_variant_key key;
union ac_shader_variant_key key;
bool unsafe_math;
bool supports_spill;
bool clamp_shadow_reference;
enum radeon_family family;
enum chip_class chip_class;
};
@@ -96,8 +87,7 @@ enum ac_ud_index {
AC_UD_SCRATCH_RING_OFFSETS = 0,
AC_UD_PUSH_CONSTANTS = 1,
AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
AC_UD_VIEW_INDEX = 3,
AC_UD_SHADER_START = 4,
AC_UD_SHADER_START = 3,
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_LS_TCS_IN_LAYOUT,
@@ -106,13 +96,13 @@ enum ac_ud_index {
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
AC_UD_CS_MAX_UD,
AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
AC_UD_GS_MAX_UD,
AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
AC_UD_TCS_MAX_UD,
AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
AC_UD_TES_MAX_UD,
AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
};
/* descriptor index into scratch ring offsets */
@@ -157,7 +147,7 @@ struct ac_shader_variant_info {
unsigned num_input_sgprs;
unsigned num_input_vgprs;
bool need_indirect_descriptor_sets;
struct {
union {
struct {
struct ac_vs_output_info outinfo;
struct ac_es_output_info es_info;
@@ -178,6 +168,7 @@ struct ac_shader_variant_info {
bool writes_sample_mask;
bool early_fragment_test;
bool writes_memory;
bool force_persample;
bool prim_id_input;
bool layer_input;
} fs;
@@ -219,8 +210,7 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
struct ac_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
struct nir_shader *nir,
const struct ac_nir_compiler_options *options,
bool dump_shader);
@@ -232,8 +222,4 @@ void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
const struct ac_nir_compiler_options *options,
bool dump_shader);
struct nir_to_llvm_context;
void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
struct nir_shader *nir, struct nir_to_llvm_context *nctx);
#endif /* AC_NIR_TO_LLVM_H */

View File

@@ -1,97 +0,0 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef AC_SHADER_ABI_H
#define AC_SHADER_ABI_H
#include <llvm-c/Core.h>
enum ac_descriptor_type {
AC_DESC_IMAGE,
AC_DESC_FMASK,
AC_DESC_SAMPLER,
AC_DESC_BUFFER,
};
/* Document the shader ABI during compilation. This is what allows radeonsi and
* radv to share a compiler backend.
*/
struct ac_shader_abi {
LLVMValueRef base_vertex;
LLVMValueRef start_instance;
LLVMValueRef draw_id;
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
LLVMValueRef frag_pos[4];
LLVMValueRef front_face;
LLVMValueRef ancillary;
LLVMValueRef sample_coverage;
/* For VS and PS: pre-loaded shader inputs.
*
* Currently only used for NIR shaders; indexed by variables'
* driver_location.
*/
LLVMValueRef *inputs;
void (*emit_outputs)(struct ac_shader_abi *abi,
unsigned max_outputs,
LLVMValueRef *addrs);
LLVMValueRef (*load_ubo)(struct ac_shader_abi *abi, LLVMValueRef index);
/**
* Load the descriptor for the given buffer.
*
* \param buffer the buffer as presented in NIR: this is the descriptor
* in Vulkan, and the buffer index in OpenGL/Gallium
* \param write whether buffer contents will be written
*/
LLVMValueRef (*load_ssbo)(struct ac_shader_abi *abi,
LLVMValueRef buffer, bool write);
/**
* Load a descriptor associated to a sampler.
*
* \param descriptor_set the descriptor set index (only for Vulkan)
* \param base_index the base index of the sampler variable
* \param constant_index constant part of an array index (or 0, if the
* sampler variable is not an array)
* \param index non-constant part of an array index (may be NULL)
* \param desc_type the type of descriptor to load
* \param image whether the descriptor is loaded for an image operation
*/
LLVMValueRef (*load_sampler_desc)(struct ac_shader_abi *abi,
unsigned descriptor_set,
unsigned base_index,
unsigned constant_index,
LLVMValueRef index,
enum ac_descriptor_type desc_type,
bool image, bool write);
/* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi currently
* uses it due to promoting D16 to D32, but radv needs it off. */
bool clamp_shadow_reference;
};
#endif /* AC_SHADER_ABI_H */

View File

@@ -39,21 +39,9 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, struct ac_shader_info *info)
case nir_intrinsic_load_draw_id:
info->vs.needs_draw_id = true;
break;
case nir_intrinsic_load_instance_id:
info->vs.needs_instance_id = true;
break;
case nir_intrinsic_load_num_work_groups:
info->cs.grid_components_used = instr->num_components;
break;
case nir_intrinsic_load_sample_id:
info->ps.force_persample = true;
break;
case nir_intrinsic_load_sample_pos:
info->ps.force_persample = true;
break;
case nir_intrinsic_load_view_index:
info->needs_multiview_view_index = true;
break;
case nir_intrinsic_vulkan_resource_index:
info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
break;
@@ -67,18 +55,9 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, struct ac_shader_info *info)
case nir_intrinsic_image_atomic_xor:
case nir_intrinsic_image_atomic_exchange:
case nir_intrinsic_image_atomic_comp_swap:
case nir_intrinsic_image_size: {
const struct glsl_type *type = instr->variables[0]->var->type;
if(instr->variables[0]->deref.child)
type = instr->variables[0]->deref.child->type;
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
info->ps.uses_input_attachments = true;
case nir_intrinsic_image_size:
mark_sampler_desc(instr->variables[0]->var, info);
break;
}
default:
break;
}
@@ -116,7 +95,7 @@ gather_info_input_decl(nir_shader *nir,
nir_variable *var,
struct ac_shader_info *info)
{
switch (nir->info.stage) {
switch (nir->stage) {
case MESA_SHADER_VERTEX:
info->vs.has_vertex_buffers = true;
break;

View File

@@ -30,16 +30,12 @@ struct ac_nir_compiler_options;
struct ac_shader_info {
bool needs_push_constants;
uint32_t desc_set_used_mask;
bool needs_multiview_view_index;
struct {
bool has_vertex_buffers; /* needs vertex buffers and base/start */
bool needs_draw_id;
bool needs_instance_id;
} vs;
struct {
bool force_persample;
bool needs_sample_positions;
bool uses_input_attachments;
} ps;
struct {
uint8_t grid_components_used;

View File

@@ -30,7 +30,6 @@
#include "amdgpu_id.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
#include "util/u_atomic.h"
#include "util/u_math.h"
#include <errno.h>
@@ -407,16 +406,12 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
}
/**
* This must be called after the first level is computed.
*
* Copy surface-global settings like pipe/bank config from level 0 surface
* computation, and compute tile swizzle.
* computation.
*/
static int gfx6_surface_settings(ADDR_HANDLE addrlib,
const struct radeon_info *info,
const struct ac_surf_config *config,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
struct radeon_surf *surf)
static void gfx6_surface_settings(const struct radeon_info* info,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
struct radeon_surf *surf)
{
surf->surf_alignment = csio->baseAlign;
surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
@@ -433,36 +428,6 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
} else {
surf->u.legacy.macro_tile_index = 0;
}
/* Compute tile swizzle. */
/* TODO: fix tile swizzle with mipmapping for SI */
if ((info->chip_class >= CIK || config->info.levels == 1) &&
config->info.surf_index &&
surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
(config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
AddrBaseSwizzleIn.tileMode = csio->tileMode;
int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
&AddrBaseSwizzleOut);
if (r != ADDR_OK)
return r;
assert(AddrBaseSwizzleOut.tileSwizzle <=
u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
}
return 0;
}
/**
@@ -675,7 +640,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
}
}
surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
@@ -719,10 +683,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
assert(stencil_tile_idx >= 0);
}
r = gfx6_surface_settings(addrlib, info, config,
&AddrSurfInfoOut, surf);
if (r)
return r;
gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
}
}
@@ -755,12 +716,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
}
if (level == 0) {
if (only_stencil) {
r = gfx6_surface_settings(addrlib, info, config,
&AddrSurfInfoOut, surf);
if (r)
return r;
}
if (only_stencil)
gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
@@ -776,16 +733,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
* complicated.
*/
if (surf->dcc_size && config->info.levels > 1) {
/* The smallest miplevels that are never compressed by DCC
* still read the DCC buffer via TC if the base level uses DCC,
* and for some reason the DCC buffer needs to be larger if
* the miptree uses non-zero tile_swizzle. Otherwise there are
* VM faults.
*
* "dcc_alignment * 4" was determined by trial and error.
*/
surf->dcc_size = align64(surf->surf_size >> 8,
surf->dcc_alignment * 4);
info->pipe_interleave_bytes *
info->num_tile_pipes);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
@@ -795,9 +745,20 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->htile_size *= 2;
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
/* workout base swizzle */
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
}
return 0;
}
@@ -1140,7 +1101,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
}
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
surf->num_dcc_levels = 0;
surf->surf_size = 0;
@@ -1177,14 +1137,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
/* Query whether the surface is displayable. */
bool displayable = false;
r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
surf->bpe * 8, &displayable);
if (r)
return r;
surf->is_displayable = displayable;
switch (surf->u.gfx9.surf.swizzle_mode) {
/* S = standard. */
case ADDR_SW_256B_S:

View File

@@ -62,12 +62,12 @@ enum radeon_micro_mode {
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
#define RADEON_SURF_SHAREABLE (1 << 26)
struct legacy_surf_level {
uint64_t offset;
@@ -97,6 +97,7 @@ struct legacy_surf_layout {
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
uint8_t tile_swizzle;
struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
@@ -130,12 +131,11 @@ struct gfx9_surf_layout {
struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */
uint16_t surf_pitch; /* in blocks */
uint16_t surf_height;
uint64_t surf_offset; /* 0 unless imported with an offset */
/* The size of the 2D plane containing all mipmap levels. */
uint64_t surf_slice_size;
uint16_t surf_pitch; /* in blocks */
uint16_t surf_height;
/* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
uint32_t offset[RADEON_SURF_MAX_LEVELS];
@@ -160,9 +160,6 @@ struct radeon_surf {
*/
unsigned num_dcc_levels:4;
unsigned is_linear:1;
unsigned has_stencil:1;
/* This might be true even if micro_tile_mode isn't displayable or rotated. */
unsigned is_displayable:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3;
uint32_t flags;
@@ -171,21 +168,6 @@ struct radeon_surf {
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
* The value is the same for all mipmap levels. Supported tile modes:
* - GFX6: Only macro tiling.
* - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
*
* Only these surfaces are allowed to set it:
* - color (if it doesn't have to be displayable)
* - DCC (same tile swizzle as color)
* - FMASK
* - CMASK if it's TC-compatible or if the gen is GFX9
* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
*/
uint8_t tile_swizzle;
uint64_t surf_size;
uint64_t dcc_size;
uint64_t htile_size;
@@ -213,10 +195,10 @@ struct ac_surf_info {
uint32_t width;
uint32_t height;
uint32_t depth;
uint32_t surf_index;
uint8_t samples;
uint8_t levels;
uint16_t array_size;
uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
};
struct ac_surf_config {

View File

@@ -1,63 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
inc_amd_common = include_directories('.')
sid_tables_h = custom_target(
'sid_tables_h',
input : ['sid_tables.py', 'sid.h', 'gfx9d.h'],
output : 'sid_tables.h',
command : [prog_python2, '@INPUT@'],
capture : true,
)
amd_common_files = files(
'ac_binary.c',
'ac_binary.h',
'ac_exp_param.h',
'ac_llvm_build.c',
'ac_llvm_build.h',
'ac_llvm_helper.cpp',
'ac_llvm_util.c',
'ac_llvm_util.h',
'ac_shader_abi.h',
'ac_shader_info.c',
'ac_shader_info.h',
'ac_nir_to_llvm.c',
'ac_nir_to_llvm.h',
'ac_gpu_info.c',
'ac_gpu_info.h',
'ac_surface.c',
'ac_surface.h',
'ac_debug.c',
'ac_debug.h',
)
libamd_common = static_library(
'amd_common',
[amd_common_files, sid_tables_h, nir_opcodes_h],
include_directories : [inc_common, inc_compiler, inc_nir, inc_mesa, inc_mapi,
inc_amd],
dependencies : [dep_llvm, dep_thread, dep_elf, dep_libdrm_amdgpu,
dep_valgrind],
c_args : [c_vis_args],
cpp_args : [cpp_vis_args],
build_by_default : false,
)

View File

@@ -0,0 +1,298 @@
/*
* Copyright 2013 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Marek Olšák <maraeo@gmail.com>
*/
#ifndef R600D_COMMON_H
#define R600D_COMMON_H
#define R600_CONFIG_REG_OFFSET 0x08000
#define R600_CONTEXT_REG_OFFSET 0x28000
#define SI_SH_REG_OFFSET 0x0000B000
#define SI_SH_REG_END 0x0000C000
#define CIK_UCONFIG_REG_OFFSET 0x00030000
#define CIK_UCONFIG_REG_END 0x00038000
#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
#define PKT3_NOP 0x10
#define PKT3_SET_PREDICATION 0x20
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3) << 1)
#define STRMOUT_OFFSET_FROM_PACKET 0
#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
#define STRMOUT_OFFSET_FROM_MEM 2
#define STRMOUT_OFFSET_NONE 3
#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3) << 8)
#define PKT3_WAIT_REG_MEM 0x3C
#define WAIT_REG_MEM_EQUAL 3
#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
#define PKT3_COPY_DATA 0x40
#define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
#define COPY_DATA_REG 0
#define COPY_DATA_MEM 1
#define COPY_DATA_PERF 4
#define COPY_DATA_IMM 5
#define COPY_DATA_TIMESTAMP 9
#define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8)
#define COPY_DATA_MEM_ASYNC 5
#define COPY_DATA_COUNT_SEL (1 << 16)
#define COPY_DATA_WR_CONFIRM (1 << 20)
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47
#define EOP_DATA_SEL(x) ((x) << 29)
/* 0 - discard
* 1 - send low 32bit data
* 2 - send 64bit data
* 3 - send 64bit GPU counter value
* 4 - send 64bit sys counter value
*/
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ */
#define PKT3_SET_CONFIG_REG 0x68
#define PKT3_SET_CONTEXT_REG 0x69
#define PKT3_STRMOUT_BASE_UPDATE 0x72 /* r700 only */
#define PKT3_SURFACE_BASE_UPDATE 0x73 /* r600 only */
#define SURFACE_BASE_UPDATE_DEPTH (1 << 0)
#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x))
#define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1)
#define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x))
#define PKT3_SET_SH_REG 0x76 /* SI and later */
#define PKT3_SET_UCONFIG_REG 0x79 /* CIK and later */
#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS1 0x1 /* EG and later */
#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS2 0x2 /* EG and later */
#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS3 0x3 /* EG and later */
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
#define EVENT_TYPE_PERFCOUNTER_START 0x17
#define EVENT_TYPE_PERFCOUNTER_STOP 0x18
#define EVENT_TYPE_PIPELINESTAT_START 25
#define EVENT_TYPE_PIPELINESTAT_STOP 26
#define EVENT_TYPE_PERFCOUNTER_SAMPLE 0x1B
#define EVENT_TYPE_SAMPLE_PIPELINESTAT 30
#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
#define EVENT_TYPE_BOTTOM_OF_PIPE_TS 40
#define EVENT_TYPE_FLUSH_AND_INV_DB_META 0x2c /* supported on r700+ */
#define EVENT_TYPE_FLUSH_AND_INV_CB_META 46 /* supported on r700+ */
#define EVENT_TYPE(x) ((x) << 0)
#define EVENT_INDEX(x) ((x) << 8)
/* 0 - any non-TS event
* 1 - ZPASS_DONE
* 2 - SAMPLE_PIPELINESTAT
* 3 - SAMPLE_STREAMOUTSTAT*
* 4 - *S_PARTIAL_FLUSH
* 5 - TS events
*/
#define PREDICATION_OP_CLEAR 0x0
#define PREDICATION_OP_ZPASS 0x1
#define PREDICATION_OP_PRIMCOUNT 0x2
#define PRED_OP(x) ((x) << 16)
#define PREDICATION_CONTINUE (1 << 31)
#define PREDICATION_HINT_WAIT (0 << 12)
#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
#define PREDICATION_DRAW_VISIBLE (1 << 8)
/* R600-R700*/
#define R_008490_CP_STRMOUT_CNTL 0x008490
#define S_008490_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0)
#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
#define S_028AB0_STREAMOUT(x) (((unsigned)(x) & 0x1) << 0)
#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
#define C_028AB0_STREAMOUT 0xFFFFFFFE
#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
#define S_028B20_BUFFER_0_EN(x) (((unsigned)(x) & 0x1) << 0)
#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
#define S_028B20_BUFFER_1_EN(x) (((unsigned)(x) & 0x1) << 1)
#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
#define S_028B20_BUFFER_2_EN(x) (((unsigned)(x) & 0x1) << 2)
#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
#define S_028B20_BUFFER_3_EN(x) (((unsigned)(x) & 0x1) << 3)
#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0
#define V_0280A0_SWAP_STD 0x00000000
#define V_0280A0_SWAP_ALT 0x00000001
#define V_0280A0_SWAP_STD_REV 0x00000002
#define V_0280A0_SWAP_ALT_REV 0x00000003
/* EG+ */
#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0)
#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94
#define S_028B94_STREAMOUT_0_EN(x) (((unsigned)(x) & 0x1) << 0)
#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1)
#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE
#define S_028B94_STREAMOUT_1_EN(x) (((unsigned)(x) & 0x1) << 1)
#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1)
#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD
#define S_028B94_STREAMOUT_2_EN(x) (((unsigned)(x) & 0x1) << 2)
#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1)
#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB
#define S_028B94_STREAMOUT_3_EN(x) (((unsigned)(x) & 0x1) << 3)
#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1)
#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7
#define S_028B94_RAST_STREAM(x) (((unsigned)(x) & 0x07) << 4)
#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07)
#define C_028B94_RAST_STREAM 0xFFFFFF8F
#define S_028B94_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x0F) << 8) /* SI+ */
#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F)
#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF
#define S_028B94_USE_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x1) << 31) /* SI+ */
#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1)
#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF
#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98
#define S_028B98_STREAM_0_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 0)
#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F)
#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0
#define S_028B98_STREAM_1_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 4)
#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F)
#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F
#define S_028B98_STREAM_2_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 8)
#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F)
#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF
#define S_028B98_STREAM_3_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 12)
#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1) << 16)
#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1) << 25)
#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1) << 26)
#define CM_R_028804_DB_EQAA 0x00028804
#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) & 0x07) << 0)
#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07)
#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8
#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) & 0x07) << 4)
#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07)
#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F
#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 8)
#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07)
#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF
#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 12)
#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF
#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1) << 16)
#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF
#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1) << 17)
#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF
#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1) << 18)
#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF
#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1) << 19)
#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF
#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1) << 20)
#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF
#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1) << 21)
#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF
#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) & 0x07) << 24)
#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07)
#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF
#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1) << 27)
#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1)
#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF
#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc
#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1) << 9)
#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10)
#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11)
#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12)
#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 0)
#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4)
#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F) << 13)
#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07) << 20)
#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03) << 24)
#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8
#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
#define EG_S_028C70_FAST_CLEAR(x) (((unsigned)(x) & 0x1) << 17)
#define SI_S_028C70_FAST_CLEAR(x) (((unsigned)(x) & 0x1) << 13)
/*CIK+*/
#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC
#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8
#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
#define S_028250_TL_X(x) (((unsigned)(x) & 0x7FFF) << 0)
#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
#define C_028250_TL_X 0xFFFF8000
#define S_028250_TL_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
#define C_028250_TL_Y 0x8000FFFF
#define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31)
#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
#define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0)
#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
#define C_028254_BR_X 0xFFFF8000
#define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
#define C_028254_BR_Y 0x8000FFFF
#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
#endif

View File

@@ -113,13 +113,6 @@
#define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CONST 0x33
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3) << 1)
#define STRMOUT_OFFSET_FROM_PACKET 0
#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
#define STRMOUT_OFFSET_FROM_MEM 2
#define STRMOUT_OFFSET_NONE 3
#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3) << 8)
#define PKT3_DRAW_INDEX_OFFSET_2 0x35
#define PKT3_WRITE_DATA 0x37
#define R_370_CONTROL 0x370 /* 0x[packet number][word index] */
@@ -144,7 +137,6 @@
#define PKT3_MPEG_INDEX 0x3A /* not on CIK */
#define PKT3_WAIT_REG_MEM 0x3C
#define WAIT_REG_MEM_EQUAL 3
#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
#define PKT3_MEM_WRITE 0x3D /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */
#define R_3F0_IB_BASE_LO 0x3F0
@@ -164,7 +156,6 @@
#define COPY_DATA_IMM 5
#define COPY_DATA_TIMESTAMP 9
#define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8)
#define COPY_DATA_MEM_ASYNC 5
#define COPY_DATA_COUNT_SEL (1 << 16)
#define COPY_DATA_WR_CONFIRM (1 << 20)
#define PKT3_PFP_SYNC_ME 0x42
@@ -173,14 +164,6 @@
#define PKT3_COND_WRITE 0x45
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
#define EOP_INT_SEL(x) ((x) << 24)
#define EOP_INT_SEL_NONE 0
#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
#define EOP_DATA_SEL(x) ((x) << 29)
#define EOP_DATA_SEL_DISCARD 0
#define EOP_DATA_SEL_VALUE_32BIT 1
#define EOP_DATA_SEL_VALUE_64BIT 2
#define EOP_DATA_SEL_TIMESTAMP 3
/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
* DST_SEL=MC. Only CIK chips are affected.

View File

@@ -25,12 +25,8 @@ CopyRight = '''
*/
'''
import collections
import functools
import itertools
import os.path
import re
import sys
import re
class StringTable:
@@ -135,203 +131,91 @@ class Field:
self.s_name = s_name
self.name = strip_prefix(s_name)
self.values = []
def format(self, string_table, idx_table):
if len(self.values):
values_offsets = []
for value in self.values:
while value[1] >= len(values_offsets):
values_offsets.append(-1)
values_offsets[value[1]] = string_table.add(strip_prefix(value[0]))
return '{%s, %s(~0u), %s, %s}' % (
string_table.add(self.name), self.s_name,
len(values_offsets), idx_table.add(values_offsets))
else:
return '{%s, %s(~0u)}' % (string_table.add(self.name), self.s_name)
def __eq__(self, other):
return (self.s_name == other.s_name and
self.name == other.name and
len(self.values) == len(other.values) and
all(a[0] == b[0] and a[1] == b[1] for a, b, in zip(self.values, other.values)))
def __ne__(self, other):
return not (self == other)
class FieldTable:
"""
A class for collecting multiple arrays of register fields in a single big
array that is used by indexing (to avoid relocations in the resulting binary)
"""
def __init__(self):
self.table = []
self.idxs = set()
self.name_to_idx = collections.defaultdict(lambda: [])
def add(self, array):
"""
Add an array of Field objects, and return the index of where to find
the array in the table.
"""
# Check if we can find the array in the table already
for base_idx in self.name_to_idx.get(array[0].name, []):
if base_idx + len(array) > len(self.table):
continue
for i, a in enumerate(array):
b = self.table[base_idx + i]
if a != b:
break
else:
return base_idx
base_idx = len(self.table)
self.idxs.add(base_idx)
for field in array:
self.name_to_idx[field.name].append(len(self.table))
self.table.append(field)
return base_idx
def emit(self, filp, string_table, idx_table):
"""
Write
static const struct si_field sid_fields_table[] = { ... };
to filp.
"""
idxs = sorted(self.idxs) + [len(self.table)]
filp.write('static const struct si_field sid_fields_table[] = {\n')
for start, end in zip(idxs, idxs[1:]):
filp.write('\t/* %s */\n' % (start))
for field in self.table[start:end]:
filp.write('\t%s,\n' % (field.format(string_table, idx_table)))
filp.write('};\n')
self.varname_values = '%s__%s__values' % (reg.r_name.lower(), self.name.lower())
class Reg:
def __init__(self, r_name):
self.r_name = r_name
self.name = strip_prefix(r_name)
self.fields = []
def __eq__(self, other):
if not isinstance(other, Reg):
return False
return (self.r_name == other.r_name and
self.name == other.name and
len(self.fields) == len(other.fields) and
all(a == b for a, b in zip(self.fields, other.fields)))
def __ne__(self, other):
return not (self == other)
self.own_fields = True
def strip_prefix(s):
'''Strip prefix in the form ._.*_, e.g. R_001234_'''
return s[s[2:].find('_')+3:]
def parse(filename, regs, packets):
stream = open(filename)
class Asic:
"""
Store the registers of one ASIC class / group of classes.
"""
def __init__(self, name):
self.name = name
self.registers = []
for line in stream:
if not line.startswith('#define '):
continue
def parse(self, filp, packets, older_asics):
"""
Parse registers from the given header file. Packets are separately
stored in the packets array.
"""
for line in filp:
if not line.startswith('#define '):
continue
line = line[8:].strip()
line = line[8:].strip()
if line.startswith('R_'):
name = line.split()[0]
if line.startswith('R_'):
name = line.split()[0]
for it in regs:
if it.r_name == name:
reg = it
break
else:
reg = Reg(name)
regs.append(reg)
for it in self.registers:
if it.r_name == name:
sys.exit('Duplicate register define: %s' % (name))
else:
reg = Reg(name)
self.registers.append(reg)
elif line.startswith('S_'):
name = line[:line.find('(')]
elif line.startswith('S_'):
name = line[:line.find('(')]
for it in reg.fields:
if it.s_name == name:
field = it
break
else:
field = Field(reg, name)
reg.fields.append(field)
for it in reg.fields:
if it.s_name == name:
sys.exit('Duplicate field define: %s' % (name))
else:
field = Field(reg, name)
reg.fields.append(field)
elif line.startswith('V_'):
split = line.split()
name = split[0]
value = int(split[1], 0)
elif line.startswith('V_'):
split = line.split()
name = split[0]
value = int(split[1], 0)
for (n,v) in field.values:
if n == name:
if v != value:
sys.exit('Value mismatch: name = ' + name)
for (n,v) in field.values:
if n == name:
sys.exit('Duplicate value define: name = ' + name)
field.values.append((name, value))
field.values.append((name, value))
elif line.startswith('PKT3_') and line.find('0x') != -1 and line.find('(') == -1:
packets.append(line.split()[0])
elif line.startswith('PKT3_') and line.find('0x') != -1 and line.find('(') == -1:
packets.append(line.split()[0])
# Copy fields to indexed registers which have their fields only defined
# at register index 0.
# For example, copy fields from CB_COLOR0_INFO to CB_COLORn_INFO, n > 0.
match_number = re.compile('[0-9]+')
reg_dict = dict()
# Copy values for corresponding fields from older ASICs if they were
# not redefined
for reg in self.registers:
old_reg = False
for field in reg.fields:
if len(field.values) > 0:
continue
if old_reg is False:
for old_reg in itertools.chain(
*(asic.registers for asic in reversed(older_asics))):
if old_reg.name == reg.name:
break
else:
old_reg = None
if old_reg is not None:
for old_field in old_reg.fields:
if old_field.name == field.name:
field.values = old_field.values
break
# Create a dict of registers with fields and '0' in their name
for reg in regs:
if len(reg.fields) and reg.name.find('0') != -1:
reg_dict[reg.name] = reg
# Copy fields to indexed registers which have their fields only defined
# at register index 0.
# For example, copy fields from CB_COLOR0_INFO to CB_COLORn_INFO, n > 0.
match_number = re.compile('[0-9]+')
reg_dict = dict()
# Create a dict of registers with fields and '0' in their name
for reg in self.registers:
if len(reg.fields) and reg.name.find('0') != -1:
reg_dict[reg.name] = reg
# Assign fields
for reg in self.registers:
if not len(reg.fields):
reg0 = reg_dict.get(match_number.sub('0', reg.name))
if reg0 != None:
reg.fields = reg0.fields
# Assign fields
for reg in regs:
if not len(reg.fields):
reg0 = reg_dict.get(match_number.sub('0', reg.name))
if reg0 != None:
reg.fields = reg0.fields
reg.fields_owner = reg0
reg.own_fields = False
def write_tables(asics, packets):
def write_tables(regs, packets):
strings = StringTable()
strings_offsets = IntTable("int")
fields = FieldTable()
print '/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */'
print
@@ -366,28 +250,40 @@ struct si_packet3 {
print '};'
print
regs = {}
for asic in asics:
print 'static const struct si_reg %s_reg_table[] = {' % (asic.name)
for reg in asic.registers:
# Only output a register that was changed or added relative to
# the previous generation
previous = regs.get(reg.r_name, None)
if previous == reg:
continue
print 'static const struct si_field sid_fields_table[] = {'
if len(reg.fields):
print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
len(reg.fields), fields.add(reg.fields))
else:
print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name)
fields_idx = 0
for reg in regs:
if len(reg.fields) and reg.own_fields:
print '\t/* %s */' % (fields_idx)
regs[reg.r_name] = reg
print '};'
print
reg.fields_idx = fields_idx
fields.emit(sys.stdout, strings, strings_offsets)
for field in reg.fields:
if len(field.values):
values_offsets = []
for value in field.values:
while value[1] >= len(values_offsets):
values_offsets.append(-1)
values_offsets[value[1]] = strings.add(strip_prefix(value[0]))
print '\t{%s, %s(~0u), %s, %s},' % (
strings.add(field.name), field.s_name,
len(values_offsets), strings_offsets.add(values_offsets))
else:
print '\t{%s, %s(~0u)},' % (strings.add(field.name), field.s_name)
fields_idx += 1
print '};'
print
print 'static const struct si_reg sid_reg_table[] = {'
for reg in regs:
if len(reg.fields):
print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
len(reg.fields), reg.fields_idx if reg.own_fields else reg.fields_owner.fields_idx)
else:
print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name)
print '};'
print
strings.emit(sys.stdout, "sid_strings")
@@ -401,16 +297,11 @@ struct si_packet3 {
def main():
asics = []
regs = []
packets = []
for arg in sys.argv[1:]:
basename = os.path.basename(arg)
m = re.match(r'(.*)\.h', basename)
asic = Asic(m.group(1))
with open(arg) as filp:
asic.parse(filp, packets, asics)
asics.append(asic)
write_tables(asics, packets)
parse(arg, regs, packets)
write_tables(regs, packets)
if __name__ == '__main__':

View File

@@ -1,27 +0,0 @@
# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
inc_amd = include_directories('.')
subdir('addrlib')
subdir('common')
if with_amd_vk
subdir('vulkan')
endif

View File

@@ -1,3 +0,0 @@
[*.{c,h}]
indent_style = tab
indent_size = tab

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