docs: add release notes for 18.0.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Update version to 18.0.5
2018-06-03 09:26:20 +00:00 · 2018-06-03 09:20:57 +00:00 · 2018-05-30 10:06:43 +02:00 · 2018-05-30 10:06:43 +02:00 · 2018-05-30 10:06:43 +02:00 · 2018-05-30 10:06:43 +02:00
31 changed files with 392 additions and 117 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-18.0.4
+18.0.5
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -65,3 +65,26 @@ b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7 radv/resolve: do fmask decompress on al

 # stable: There is a specific port for this patch for stable branch.
 3d4d388e3929d7948b62d90867357aecbfba5aeb radv: Fix up 2_10_10_10 alpha sign.
+
+# stable: The commit requires earlier commit af4e9295fe which did not land in
+#         branch.
+816f2dc67da72be8993e724aeda4c2ec2f5a2978 i965/miptree: Fix handling of uninitialized MCS buffers
+
+# stable: Explicit 18.1 only nominations
+549e54270ba3a519b46a1fbffa4aa6b628a052d3 radv: fix VK_EXT_descriptor_indexing
+
+# fixes: The commit fixes earlier commits 19a91841c3 and 9987a072cb which did
+#        not land in branch.
+d89f58a6b8436b59dcf3b896c0ccddabed3f78fd mesa/st: handle vert_attrib_mask in nir case too
+
+# stable: Tegra support is not part of the current branch
+bd3e97e5aad7800b8e17ed10d34a070926691945 tegra: Remove usage of non-stable UAPI
+9603d81df05105857b676f20dff964ef3ab0ecff tegra: Fix scanout resources without modifiers
+9e539012dfaa848fc4cfde83c3f3a83fee274ca4 tegra: Treat resources with modifiers as scanout
+
+# stable: The commit requires earlier commit 19a91841c3 which did not land in
+#         branch.
+a7d0c53ab89ca86b705014925214101f5bc4187f st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)
+
+# stable: Explicit 18.1 only nomination
+30918b77ac82ba1da7764c0375233656e0ebf9f9 nv30: ensure that displayable formats are marked accordingly
--- a/docs/relnotes/18.0.4.html
+++ b/docs/relnotes/18.0.4.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  mesa-18.0.4.tar.gz
+1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  mesa-18.0.4.tar.xz
 </pre>


--- a/docs/relnotes/18.0.5.html
+++ b/docs/relnotes/18.0.5.html
@@ -0,0 +1,161 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.0.5 Release Notes / June 3, 2018</h1>
+
+<p>
+Mesa 18.0.5 is a bug fix release which fixes bugs found since the 18.0.4 release.
+</p>
+<p>
+Mesa 18.0.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78097">Bug 78097</a> - glUniform1ui and friends not supported by display lists</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102390">Bug 102390</a> - centroid interpolation causes broken attribute values</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105351">Bug 105351</a> - [Gen6+] piglit's arb_shader_image_load_store-host-mem-barrier fails with a glGetTexSubImage fallback path</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106090">Bug 106090</a> - Compiling compute shader crashes RADV</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106315">Bug 106315</a> - The witness + dxvk suffers flickering garbage</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106465">Bug 106465</a> - No test for Image Load/Store on format-incompatible texture buffer</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106479">Bug 106479</a> - NDEBUG not defined for libamdgpu_addrlib</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106481">Bug 106481</a> - No test for Image Load/Store on texture buffer sized greater than MAX_TEXTURE_BUFFER_SIZE_ARB</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106504">Bug 106504</a> - vulkan SPIR-V parsing failed at ../src/compiler/spirv/vtn_cfg.c:381</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106587">Bug 106587</a> - Dota2 is very dark when using vulkan render on a Intel &lt;&lt; AMD prime setup</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106629">Bug 106629</a> - [SNB,IVB,HSW,BDW] dEQP-EGL.functional.image.create.gles2_cubemap_negative_z_rgb_read_pixels</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+  <li>i965/glk: Add l3 banks count for 2x6 configuration</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (2):</p>
+<ul>
+  <li>amd/addrlib: Use defines in autotools build.</li>
+  <li>radv: Fix SRGB compute copies.</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>tgsi/scan: add hw atomic to the list of memory accessing files</li>
+</ul>
+
+<p>Francisco Jerez (4):</p>
+<ul>
+  <li>Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"</li>
+  <li>i965: Move buffer texture size calculation into a common helper function.</li>
+  <li>i965: Handle non-zero texture buffer offsets in buffer object range calculation.</li>
+  <li>i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.</li>
+</ul>
+
+<p>Jan Vesely (1):</p>
+<ul>
+  <li>eg/compute: Use reference counting to handle compute memory pool.</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0</li>
+  <li>intel/blorp: Support blits and clears on surfaces with offsets</li>
+</ul>
+
+<p>Jose Dapena Paz (1):</p>
+<ul>
+  <li>mesa: do not leak ctx-&gt;Shader.ReferencedProgram references</li>
+</ul>
+
+<p>Juan A. Suarez Romero (8):</p>
+<ul>
+  <li>docs: add sha256 checksums for 18.0.4</li>
+  <li>cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers</li>
+  <li>cherry-ignore: add explicit 18.1 only nominations</li>
+  <li>cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too</li>
+  <li>cherry-ignore: Tegra is not supported</li>
+  <li>cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)</li>
+  <li>cherry-ignore: nv30: ensure that displayable formats are marked accordingly</li>
+  <li>Update version to 18.0.5</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>st/mesa: simplify lastLevel determination in st_finalize_texture</li>
+  <li>radeonsi: fix incorrect parentheses around VS-PS varying elimination</li>
+  <li>mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>dri3: Stricter SBC wraparound handling</li>
+</ul>
+
+<p>Nanley Chery (1):</p>
+<ul>
+  <li>i965/miptree: Zero-initialize CCS_D buffers</li>
+</ul>
+
+<p>Samuel Pitoiset (2):</p>
+<ul>
+  <li>spirv: fix visiting inner loops with same break/continue block</li>
+  <li>radv: fix centroid interpolation</li>
+</ul>
+
+<p>Stuart Young (1):</p>
+<ul>
+  <li>etnaviv: Fix missing rnndb file in tarballs</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>mesa: add glUniform*ui{v} support to display lists</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/src/amd/Makefile.addrlib.am
+++ b/src/amd/Makefile.addrlib.am
@@ -22,6 +22,7 @@
 ADDRLIB_LIBS = addrlib/libamdgpu_addrlib.la

 addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
+	$(DEFINES) \
 	-I$(top_srcdir)/src/ \
 	-I$(srcdir)/common \
 	-I$(srcdir)/addrlib \
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5523,9 +5523,6 @@ static void
 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
                        struct nir_shader *nir)
 {
-	if (!ctx->options->key.fs.multisample)
-		return;
-
 	bool uses_center = false;
 	bool uses_centroid = false;
 	nir_foreach_variable(variable, &nir->inputs) {
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -93,6 +93,8 @@ blit_surf_for_image_level_layer(struct radv_image *image,
 	    !(image->surface.htile_size && image->tc_compatible_htile))
 		format = vk_format_for_size(vk_format_get_blocksize(format));

+	format = vk_format_no_srgb(format);
+
 	return (struct radv_meta_blit2d_surf) {
 		.format = format,
 		.bs = vk_format_get_blocksize(format),
--- a/src/amd/vulkan/vk_format.h
+++ b/src/amd/vulkan/vk_format.h
@@ -416,6 +416,46 @@ vk_format_is_srgb(VkFormat format)
 	return desc->colorspace == VK_FORMAT_COLORSPACE_SRGB;
 }

+static inline VkFormat
+vk_format_no_srgb(VkFormat format)
+{
+	switch(format) {
+	case VK_FORMAT_R8_SRGB:
+		return VK_FORMAT_R8_UNORM;
+	case VK_FORMAT_R8G8_SRGB:
+		return VK_FORMAT_R8G8_UNORM;
+	case VK_FORMAT_R8G8B8_SRGB:
+		return VK_FORMAT_R8G8B8_UNORM;
+	case VK_FORMAT_B8G8R8_SRGB:
+		return VK_FORMAT_B8G8R8_UNORM;
+	case VK_FORMAT_R8G8B8A8_SRGB:
+		return VK_FORMAT_R8G8B8A8_UNORM;
+	case VK_FORMAT_B8G8R8A8_SRGB:
+		return VK_FORMAT_B8G8R8A8_UNORM;
+	case VK_FORMAT_A8B8G8R8_SRGB_PACK32:
+		return VK_FORMAT_A8B8G8R8_UNORM_PACK32;
+	case VK_FORMAT_BC1_RGB_SRGB_BLOCK:
+		return VK_FORMAT_BC1_RGB_UNORM_BLOCK;
+	case VK_FORMAT_BC1_RGBA_SRGB_BLOCK:
+		return VK_FORMAT_BC1_RGBA_UNORM_BLOCK;
+	case VK_FORMAT_BC2_SRGB_BLOCK:
+		return VK_FORMAT_BC2_UNORM_BLOCK;
+	case VK_FORMAT_BC3_SRGB_BLOCK:
+		return VK_FORMAT_BC3_UNORM_BLOCK;
+	case VK_FORMAT_BC7_SRGB_BLOCK:
+		return VK_FORMAT_BC7_UNORM_BLOCK;
+	case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
+		return VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK;
+	case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
+		return VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK;
+	case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
+		return VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK;
+	default:
+		assert(!vk_format_is_srgb(format));
+		return format;
+	}
+}
+
 static inline VkFormat
 vk_format_stencil_only(VkFormat format)
 {
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -374,6 +374,19 @@ vtn_cfg_walk_blocks(struct vtn_builder *b, struct list_head *cf_list,
         vtn_cfg_walk_blocks(b, &loop->cont_body, new_loop_cont, NULL, NULL,
                             new_loop_break, NULL, block);

+         enum vtn_branch_type branch_type =
+            vtn_get_branch_type(b, new_loop_break, switch_case, switch_break,
+                                loop_break, loop_cont);
+
+         if (branch_type != vtn_branch_type_none) {
+            /* Stop walking through the CFG when this inner loop's break block
+             * ends up as the same block as the outer loop's continue block
+             * because we are already going to visit it.
+             */
+            vtn_assert(branch_type == vtn_branch_type_loop_continue);
+            return;
+         }
+
         block = new_loop_break;
         continue;
      }
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -50,7 +50,8 @@ is_memory_file(unsigned file)
   return file == TGSI_FILE_SAMPLER ||
          file == TGSI_FILE_SAMPLER_VIEW ||
          file == TGSI_FILE_IMAGE ||
-          file == TGSI_FILE_BUFFER;
+          file == TGSI_FILE_BUFFER ||
+          file == TGSI_FILE_HW_ATOMIC;
 }


--- a/src/gallium/drivers/etnaviv/Makefile.sources
+++ b/src/gallium/drivers/etnaviv/Makefile.sources
@@ -6,6 +6,7 @@ C_SOURCES :=  \
 	hw/state_3d.xml.h \
 	hw/state_blt.xml.h \
 	hw/state.xml.h \
+	hw/texdesc_3d.xml.h \
 	\
 	etnaviv_asm.c \
 	etnaviv_asm.h \
--- a/src/gallium/drivers/etnaviv/meson.build
+++ b/src/gallium/drivers/etnaviv/meson.build
@@ -26,6 +26,7 @@ files_etnaviv = files(
  'hw/state_3d.xml.h',
  'hw/state_blt.xml.h',
  'hw/state.xml.h',
+  'hw/texdesc_3d.xml.h',
  'etnaviv_asm.c',
  'etnaviv_asm.h',
  'etnaviv_blend.c',
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -91,10 +91,7 @@ void compute_memory_pool_delete(struct compute_memory_pool* pool)
 {
 	COMPUTE_DBG(pool->screen, "* compute_memory_pool_delete()\n");
 	free(pool->shadow);
-	if (pool->bo) {
-		pool->screen->b.b.resource_destroy((struct pipe_screen *)
-			pool->screen, (struct pipe_resource *)pool->bo);
-	}
+	pipe_resource_reference(&pool->bo, NULL);
 	/* In theory, all of the items were freed in compute_memory_free.
 	 * Just delete the list heads
 	 */
@@ -213,10 +210,8 @@ int compute_memory_grow_defrag_pool(struct compute_memory_pool *pool,

 			compute_memory_defrag(pool, src, dst, pipe);

-			pool->screen->b.b.resource_destroy(
-					(struct pipe_screen *)pool->screen,
-					src);
-
+			/* Release the old buffer */
+			pipe_resource_reference(&pool->bo, NULL);
 			pool->bo = temp;
 			pool->size_in_dw = new_size_in_dw;
 		}
@@ -230,9 +225,8 @@ int compute_memory_grow_defrag_pool(struct compute_memory_pool *pool,
 				return -1;

 			pool->size_in_dw = new_size_in_dw;
-			pool->screen->b.b.resource_destroy(
-					(struct pipe_screen *)pool->screen,
-					(struct pipe_resource *)pool->bo);
+			/* Release the old buffer */
+			pipe_resource_reference(&pool->bo, NULL);
 			pool->bo = r600_compute_buffer_alloc_vram(pool->screen, pool->size_in_dw * 4);
 			compute_memory_shadow(pool, pipe, 0);

--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -122,7 +122,8 @@ static void evergreen_set_rat(struct r600_pipe_compute *pipe,
 	rat_templ.u.tex.first_layer = 0;
 	rat_templ.u.tex.last_layer = 0;

-	/* Add the RAT the list of color buffers */
+	/* Add the RAT the list of color buffers. Drop the old buffer first. */
+	pipe_surface_reference(&pipe->ctx->framebuffer.state.cbufs[id], NULL);
 	pipe->ctx->framebuffer.state.cbufs[id] = pipe->ctx->b.b.create_surface(
 		(struct pipe_context *)pipe->ctx,
 		(struct pipe_resource *)bo, &rat_templ);
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1193,8 +1193,8 @@ static void si_shader_selector_key_hw_vs(struct si_context *sctx,
 	uint64_t inputs_read = 0;

 	/* ignore POSITION, PSIZE */
-	outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
-			     (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
+	outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0)) |
+			     (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0)));

 	if (!ps_disabled) {
 		inputs_read = ps->inputs_read;
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -137,6 +137,28 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
    */
   if (is_render_target && blorp->isl_dev->info->gen <= 6)
      info->view.array_len = MIN2(info->view.array_len, 512);
+
+   if (surf->tile_x_sa || surf->tile_y_sa) {
+      /* This is only allowed on simple 2D surfaces without MSAA */
+      assert(info->surf.dim == ISL_SURF_DIM_2D);
+      assert(info->surf.samples == 1);
+      assert(info->surf.levels == 1);
+      assert(info->surf.logical_level0_px.array_len == 1);
+      assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+      info->tile_x_sa = surf->tile_x_sa;
+      info->tile_y_sa = surf->tile_y_sa;
+
+      /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
+       * place the image at the tile boundary and offset our sampling or
+       * rendering.  For this reason, we need to grow the image by the offset
+       * to ensure that the hardware doesn't think we've gone past the edge.
+       */
+      info->surf.logical_level0_px.w += surf->tile_x_sa;
+      info->surf.logical_level0_px.h += surf->tile_y_sa;
+      info->surf.phys_level0_sa.w += surf->tile_x_sa;
+      info->surf.phys_level0_sa.h += surf->tile_y_sa;
+   }
 }


--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -109,6 +109,9 @@ struct blorp_surf
    * that it contains a swizzle of RGBA and resource min LOD of 0.
    */
   struct blorp_address clear_color_addr;
+
+   /* Only allowed for simple 2D non-MSAA surfaces */
+   uint32_t tile_x_sa, tile_y_sa;
 };

 void
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2413,7 +2413,9 @@ blorp_copy(struct blorp_batch *batch,
                               dst_layer, ISL_FORMAT_UNSUPPORTED, true);

   struct brw_blorp_blit_prog_key wm_prog_key = {
-      .shader_type = BLORP_SHADER_TYPE_BLIT
+      .shader_type = BLORP_SHADER_TYPE_BLIT,
+      .need_src_offset = src_surf->tile_x_sa || src_surf->tile_y_sa,
+      .need_dst_offset = dst_surf->tile_x_sa || dst_surf->tile_y_sa,
   };

   const struct isl_format_layout *src_fmtl =
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -438,6 +438,15 @@ blorp_clear(struct blorp_batch *batch,
      params.x1 = x1;
      params.y1 = y1;

+      if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
+         assert(params.dst.surf.samples == 1);
+         assert(num_layers == 1);
+         params.x0 += params.dst.tile_x_sa;
+         params.y0 += params.dst.tile_y_sa;
+         params.x1 += params.dst.tile_x_sa;
+         params.y1 += params.dst.tile_y_sa;
+      }
+
      /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
       * Convert them to a single slice on gen4.
       */
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -632,10 +632,10 @@ static const struct gen_device_info gen_device_info_glk = {
   .l3_banks = 2,
 };

-/*TODO: Initialize l3_banks when we know the number. */
 static const struct gen_device_info gen_device_info_glk_2x6 = {
   GEN9_LP_FEATURES_2X6,
   .is_geminilake = true,
+   .l3_banks = 2,
 };

 static const struct gen_device_info gen_device_info_cfl_gt1 = {
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3696,6 +3696,7 @@ brw_rounding_mode(struct brw_codegen *p,
   if (bits != BRW_CR0_RND_MODE_MASK) {
      brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
                               brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
+      brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);

      /* From the Skylake PRM, Volume 7, page 760:
       *  "Implementation Restriction on Register Access: When the control
@@ -3710,6 +3711,7 @@ brw_rounding_mode(struct brw_codegen *p,
   if (bits) {
      brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
                              brw_imm_ud(bits));
+      brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
      brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
   }
 }
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -365,9 +365,18 @@ dri3_handle_present_event(struct loader_dri3_drawable *draw,
       * checking for wrap.
       */
      if (ce->kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP) {
-         draw->recv_sbc = (draw->send_sbc & 0xffffffff00000000LL) | ce->serial;
-         if (draw->recv_sbc > draw->send_sbc)
-            draw->recv_sbc -= 0x100000000;
+         uint64_t recv_sbc = (draw->send_sbc & 0xffffffff00000000LL) | ce->serial;
+
+         /* Only assume wraparound if that results in exactly the previous
+          * SBC + 1, otherwise ignore received SBC > sent SBC (those are
+          * probably from a previous loader_dri3_drawable instance) to avoid
+          * calculating bogus target MSC values in loader_dri3_swap_buffers_msc
+          */
+         if (recv_sbc <= draw->send_sbc)
+            draw->recv_sbc = recv_sbc;
+         else if (recv_sbc == (draw->recv_sbc + 0x100000001ULL))
+            draw->recv_sbc = recv_sbc - 0x100000000ULL;
+
         switch (ce->mode) {
         case XCB_PRESENT_COMPLETE_MODE_FLIP:
            draw->flipping = true;
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -148,6 +148,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
         .mocs = brw_get_bo_mocs(devinfo, mt->bo),
      },
      .aux_usage = aux_usage,
+      .tile_x_sa = mt->level[*level].level_x,
+      .tile_y_sa = mt->level[*level].level_y,
   };

   struct isl_surf *aux_surf = NULL;
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -602,26 +602,15 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
                         .mocs = brw_get_bo_mocs(devinfo, bo));
 }

-void
-brw_update_buffer_texture_surface(struct gl_context *ctx,
-                                  unsigned unit,
-                                  uint32_t *surf_offset)
+static unsigned
+buffer_texture_range_size(struct brw_context *brw,
+                          struct gl_texture_object *obj)
 {
-   struct brw_context *brw = brw_context(ctx);
-   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
-   struct intel_buffer_object *intel_obj =
-      intel_buffer_object(tObj->BufferObject);
-   uint32_t size = tObj->BufferSize;
-   struct brw_bo *bo = NULL;
-   mesa_format format = tObj->_BufferObjectFormat;
-   const enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
-   int texel_size = _mesa_get_format_bytes(format);
-
-   if (intel_obj) {
-      size = MIN2(size, intel_obj->Base.Size);
-      bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size,
-                                  false);
-   }
+   assert(obj->Target == GL_TEXTURE_BUFFER);
+   const unsigned texel_size = _mesa_get_format_bytes(obj->_BufferObjectFormat);
+   const unsigned buffer_size = (!obj->BufferObject ? 0 :
+                                 obj->BufferObject->Size);
+   const unsigned buffer_offset = MIN2(buffer_size, obj->BufferOffset);

   /* The ARB_texture_buffer_specification says:
    *
@@ -639,7 +628,29 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
    * so that when ISL divides by stride to obtain the number of texels, that
    * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
    */
-   size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned) texel_size);
+   return MIN3((unsigned)obj->BufferSize,
+               buffer_size - buffer_offset,
+               brw->ctx.Const.MaxTextureBufferSize * texel_size);
+}
+
+void
+brw_update_buffer_texture_surface(struct gl_context *ctx,
+                                  unsigned unit,
+                                  uint32_t *surf_offset)
+{
+   struct brw_context *brw = brw_context(ctx);
+   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
+   struct intel_buffer_object *intel_obj =
+      intel_buffer_object(tObj->BufferObject);
+   const unsigned size = buffer_texture_range_size(brw, tObj);
+   struct brw_bo *bo = NULL;
+   mesa_format format = tObj->_BufferObjectFormat;
+   const enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
+   int texel_size = _mesa_get_format_bytes(format);
+
+   if (intel_obj)
+      bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size,
+                                  false);

   if (isl_format == ISL_FORMAT_UNSUPPORTED) {
      _mesa_problem(NULL, "bad format %s for texture buffer\n",
@@ -1426,8 +1437,7 @@ update_buffer_image_param(struct brw_context *brw,
                          unsigned surface_idx,
                          struct brw_image_param *param)
 {
-   struct gl_buffer_object *obj = u->TexObj->BufferObject;
-   const uint32_t size = MIN2((uint32_t)u->TexObj->BufferSize, obj->Size);
+   const unsigned size = buffer_texture_range_size(brw, u->TexObj);
   update_default_image_param(brw, u, surface_idx, param);

   param->size[0] = size / _mesa_get_format_bytes(u->_ActualFormat);
@@ -1459,14 +1469,17 @@ update_image_surface(struct brw_context *brw,
      const unsigned format = get_image_format(brw, u->_ActualFormat, access);

      if (obj->Target == GL_TEXTURE_BUFFER) {
-         struct intel_buffer_object *intel_obj =
-            intel_buffer_object(obj->BufferObject);
         const unsigned texel_size = (format == ISL_FORMAT_RAW ? 1 :
                                      _mesa_get_format_bytes(u->_ActualFormat));
+         const unsigned buffer_size = buffer_texture_range_size(brw, obj);
+         struct brw_bo *const bo = !obj->BufferObject ? NULL :
+            intel_bufferobj_buffer(brw, intel_buffer_object(obj->BufferObject),
+                                   obj->BufferOffset, buffer_size,
+                                   access != GL_READ_ONLY);

         brw_emit_buffer_surface_state(
-            brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
-            format, intel_obj->Base.Size, texel_size,
+            brw, surf_offset, bo, obj->BufferOffset,
+            format, buffer_size, texel_size,
            access != GL_READ_ONLY ? RELOC_WRITE : 0);

         update_buffer_image_param(brw, u, surface_idx, param);
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1767,13 +1767,11 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
    * A CCS value of 0 indicates that the corresponding block is in the
    * pass-through state which is what we want.
    *
-    * For CCS_D, on the other hand, we don't care as we're about to perform a
-    * fast-clear operation.  In that case, being hot in caches more useful.
+    * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
+    * bits in the aux buffer.
    */
-   const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
-                                BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
-   mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
-                                        &temp_ccs_surf, alloc_flags, mt);
+   mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
+                                        BO_ALLOC_ZEROED, mt);
   if (!mt->mcs_buf) {
      free(aux_state);
      return false;
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -6606,7 +6606,7 @@ save_Uniform1ui(GLint location, GLuint x)
      n[2].i = x;
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform1ui(ctx->Exec, (location, x));*/
+      CALL_Uniform1ui(ctx->Exec, (location, x));
   }
 }

@@ -6623,7 +6623,7 @@ save_Uniform2ui(GLint location, GLuint x, GLuint y)
      n[3].i = y;
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform2ui(ctx->Exec, (location, x, y));*/
+      CALL_Uniform2ui(ctx->Exec, (location, x, y));
   }
 }

@@ -6641,7 +6641,7 @@ save_Uniform3ui(GLint location, GLuint x, GLuint y, GLuint z)
      n[4].i = z;
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform3ui(ctx->Exec, (location, x, y, z));*/
+      CALL_Uniform3ui(ctx->Exec, (location, x, y, z));
   }
 }

@@ -6660,7 +6660,7 @@ save_Uniform4ui(GLint location, GLuint x, GLuint y, GLuint z, GLuint w)
      n[5].i = w;
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform4ui(ctx->Exec, (location, x, y, z, w));*/
+      CALL_Uniform4ui(ctx->Exec, (location, x, y, z, w));
   }
 }

@@ -6679,7 +6679,7 @@ save_Uniform1uiv(GLint location, GLsizei count, const GLuint *v)
      save_pointer(&n[3], memdup(v, count * 1 * sizeof(*v)));
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform1uiv(ctx->Exec, (location, count, v));*/
+      CALL_Uniform1uiv(ctx->Exec, (location, count, v));
   }
 }

@@ -6696,7 +6696,7 @@ save_Uniform2uiv(GLint location, GLsizei count, const GLuint *v)
      save_pointer(&n[3], memdup(v, count * 2 * sizeof(*v)));
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform2uiv(ctx->Exec, (location, count, v));*/
+      CALL_Uniform2uiv(ctx->Exec, (location, count, v));
   }
 }

@@ -6713,7 +6713,7 @@ save_Uniform3uiv(GLint location, GLsizei count, const GLuint *v)
      save_pointer(&n[3], memdup(v, count * 3 * sizeof(*v)));
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform3uiv(ctx->Exec, (location, count, v));*/
+      CALL_Uniform3uiv(ctx->Exec, (location, count, v));
   }
 }

@@ -6730,7 +6730,7 @@ save_Uniform4uiv(GLint location, GLsizei count, const GLuint *v)
      save_pointer(&n[3], memdup(v, count * 4 * sizeof(*v)));
   }
   if (ctx->ExecuteFlag) {
-      /*CALL_Uniform4uiv(ctx->Exec, (location, count, v));*/
+      CALL_Uniform4uiv(ctx->Exec, (location, count, v));
   }
 }

@@ -8742,34 +8742,29 @@ execute_list(struct gl_context *ctx, GLuint list)
            CALL_Uniform4iv(ctx->Exec, (n[1].i, n[2].i, get_pointer(&n[3])));
            break;
         case OPCODE_UNIFORM_1UI:
-            /*CALL_Uniform1uiARB(ctx->Exec, (n[1].i, n[2].i));*/
+            CALL_Uniform1ui(ctx->Exec, (n[1].i, n[2].i));
            break;
         case OPCODE_UNIFORM_2UI:
-            /*CALL_Uniform2uiARB(ctx->Exec, (n[1].i, n[2].i, n[3].i));*/
+            CALL_Uniform2ui(ctx->Exec, (n[1].i, n[2].i, n[3].i));
            break;
         case OPCODE_UNIFORM_3UI:
-            /*CALL_Uniform3uiARB(ctx->Exec, (n[1].i, n[2].i, n[3].i, n[4].i));*/
+            CALL_Uniform3ui(ctx->Exec, (n[1].i, n[2].i, n[3].i, n[4].i));
            break;
         case OPCODE_UNIFORM_4UI:
-            /*CALL_Uniform4uiARB(ctx->Exec,
-                              (n[1].i, n[2].i, n[3].i, n[4].i, n[5].i));
-            */
+            CALL_Uniform4ui(ctx->Exec,
+                            (n[1].i, n[2].i, n[3].i, n[4].i, n[5].i));
            break;
         case OPCODE_UNIFORM_1UIV:
-            /*CALL_Uniform1uivARB(ctx->Exec, (n[1].i, n[2].i,
-                                              get_pointer(&n[3])));*/
+            CALL_Uniform1uiv(ctx->Exec, (n[1].i, n[2].i, get_pointer(&n[3])));
            break;
         case OPCODE_UNIFORM_2UIV:
-            /*CALL_Uniform2uivARB(ctx->Exec, (n[1].i, n[2].i,
-                                              get_pointer(&n[3])));*/
+            CALL_Uniform2uiv(ctx->Exec, (n[1].i, n[2].i, get_pointer(&n[3])));
            break;
         case OPCODE_UNIFORM_3UIV:
-            /*CALL_Uniform3uivARB(ctx->Exec, (n[1].i, n[2].i,
-                                              get_pointer(&n[3])));*/
+            CALL_Uniform3uiv(ctx->Exec, (n[1].i, n[2].i, get_pointer(&n[3])));
            break;
         case OPCODE_UNIFORM_4UIV:
-            /*CALL_Uniform4uivARB(ctx->Exec, (n[1].i, n[2].i,
-                                              get_pointer(&n[3])));*/
+            CALL_Uniform4uiv(ctx->Exec, (n[1].i, n[2].i, get_pointer(&n[3])));
            break;
         case OPCODE_UNIFORM_MATRIX22:
            CALL_UniformMatrix2fv(ctx->Exec,
@@ -9949,7 +9944,6 @@ _mesa_initialize_save_table(const struct gl_context *ctx)
   SET_ClearBufferuiv(table, save_ClearBufferuiv);
   SET_ClearBufferfv(table, save_ClearBufferfv);
   SET_ClearBufferfi(table, save_ClearBufferfi);
-#if 0
   SET_Uniform1ui(table, save_Uniform1ui);
   SET_Uniform2ui(table, save_Uniform2ui);
   SET_Uniform3ui(table, save_Uniform3ui);
@@ -9958,16 +9952,6 @@ _mesa_initialize_save_table(const struct gl_context *ctx)
   SET_Uniform2uiv(table, save_Uniform2uiv);
   SET_Uniform3uiv(table, save_Uniform3uiv);
   SET_Uniform4uiv(table, save_Uniform4uiv);
-#else
-   (void) save_Uniform1ui;
-   (void) save_Uniform2ui;
-   (void) save_Uniform3ui;
-   (void) save_Uniform4ui;
-   (void) save_Uniform1uiv;
-   (void) save_Uniform2uiv;
-   (void) save_Uniform3uiv;
-   (void) save_Uniform4uiv;
-#endif

   /* These are: */
   SET_BeginTransformFeedback(table, save_BeginTransformFeedback);
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -563,6 +563,8 @@ _mesa_bytes_per_vertex_attrib(GLint comps, GLenum type)
         return sizeof(GLuint);
      else
         return -1;
+   case GL_UNSIGNED_INT64_ARB:
+      return comps * 8;
   default:
      return -1;
   }
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -159,6 +159,9 @@ _mesa_free_shader_state(struct gl_context *ctx)
 {
   for (int i = 0; i < MESA_SHADER_STAGES; i++) {
      _mesa_reference_program(ctx, &ctx->Shader.CurrentProgram[i], NULL);
+      _mesa_reference_shader_program(ctx,
+                                     &ctx->Shader.ReferencedPrograms[i],
+                                     NULL);
   }
   _mesa_reference_shader_program(ctx, &ctx->Shader.ActiveProgram, NULL);

--- a/src/mesa/main/shaderimage.c
+++ b/src/mesa/main/shaderimage.c
@@ -477,13 +477,6 @@ _mesa_is_image_unit_valid(struct gl_context *ctx, struct gl_image_unit *u)
   if (!t)
      return GL_FALSE;

-   /* The GL 4.5 Core spec doesn't say anything about buffers. In practice,
-    * the image buffer format is always compatible with the underlying
-    * buffer storage.
-    */
-   if (t->Target == GL_TEXTURE_BUFFER)
-      return GL_TRUE;
-
   if (!t->_BaseComplete && !t->_MipmapComplete)
       _mesa_test_texobj_completeness(ctx, t);

@@ -497,14 +490,20 @@ _mesa_is_image_unit_valid(struct gl_context *ctx, struct gl_image_unit *u)
       u->_Layer >= _mesa_get_texture_layers(t, u->Level))
      return GL_FALSE;

-   struct gl_texture_image *img = (t->Target == GL_TEXTURE_CUBE_MAP ?
-                                   t->Image[u->_Layer][u->Level] :
-                                   t->Image[0][u->Level]);
+   if (t->Target == GL_TEXTURE_BUFFER) {
+      tex_format = _mesa_get_shader_image_format(t->BufferObjectFormat);

-   if (!img || img->Border || img->NumSamples > ctx->Const.MaxImageSamples)
-      return GL_FALSE;
+   } else {
+      struct gl_texture_image *img = (t->Target == GL_TEXTURE_CUBE_MAP ?
+                                      t->Image[u->_Layer][u->Level] :
+                                      t->Image[0][u->Level]);
+
+      if (!img || img->Border || img->NumSamples > ctx->Const.MaxImageSamples)
+         return GL_FALSE;
+
+      tex_format = _mesa_get_shader_image_format(img->InternalFormat);
+   }

-   tex_format = _mesa_get_shader_image_format(img->InternalFormat);
   if (!tex_format)
      return GL_FALSE;

--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2471,19 +2471,10 @@ st_finalize_texture(struct gl_context *ctx,
   if (tObj->Immutable)
      return GL_TRUE;

-   if (_mesa_is_texture_complete(tObj, &tObj->Sampler)) {
-      /* The texture is complete and we know exactly how many mipmap levels
-       * are present/needed.  This is conditional because we may be called
-       * from the st_generate_mipmap() function when the texture object is
-       * incomplete.  In that case, we'll have set stObj->lastLevel before
-       * we get here.
-       */
-      if (stObj->base.Sampler.MinFilter == GL_LINEAR ||
-          stObj->base.Sampler.MinFilter == GL_NEAREST)
-         stObj->lastLevel = stObj->base.BaseLevel;
-      else
-         stObj->lastLevel = stObj->base._MaxLevel;
-   }
+   if (tObj->_MipmapComplete)
+      stObj->lastLevel = stObj->base._MaxLevel;
+   else if (tObj->_BaseComplete)
+      stObj->lastLevel = stObj->base.BaseLevel;

   /* Skip the loop over images in the common case of no images having
    * changed.  But if the GL_BASE_LEVEL or GL_MAX_LEVEL change to something we
--- a/src/mesa/vbo/vbo_context.h
+++ b/src/mesa/vbo/vbo_context.h
@@ -190,8 +190,8 @@ vbo_attrtype_to_double_flag(GLenum format)
   case GL_FLOAT:
   case GL_INT:
   case GL_UNSIGNED_INT:
-   case GL_UNSIGNED_INT64_ARB:
      return GL_FALSE;
+   case GL_UNSIGNED_INT64_ARB:
   case GL_DOUBLE:
      return GL_TRUE;
   default:
Author	SHA1	Message	Date
Juan A. Suarez Romero	ca0037aaef	docs: add release notes for 18.0.5 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-06-03 09:26:20 +00:00
Juan A. Suarez Romero	3f4da760f9	Update version to 18.0.5 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-06-03 09:20:57 +00:00
Juan A. Suarez Romero	7c644f48a1	cherry-ignore: nv30: ensure that displayable formats are marked accordingly stable: Explicit 18.1 only nomination. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-30 10:06:43 +02:00
Juan A. Suarez Romero	dfa3a7ee37	cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2) stable: The commit requires earlier commit `19a91841c3` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-30 10:06:43 +02:00
Marek Olšák	81bd117b3c	mesa: handle GL_UNSIGNED_INT64_ARB properly (v2) Bindless texture handles can be passed via vertex attribs using this type. This fixes a bunch of bindless piglit tests on radeonsi. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (cherry picked from commit `a8e1413876`) [Juan A. Suarez: resolve trivial conflict] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/mesa/vbo/vbo_private.h	2018-05-30 10:06:43 +02:00
Juan A. Suarez Romero	714dabe317	cherry-ignore: Tegra is not supported stable: Tegra support was not added in the current branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-30 10:06:43 +02:00
Jason Ekstrand	aac580f7bb	intel/blorp: Support blits and clears on surfaces with offsets For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit `ae514ca695`)	2018-05-28 10:39:48 +02:00
Marek Olšák	38aeeee511	radeonsi: fix incorrect parentheses around VS-PS varying elimination I don't know if it caused issues. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit `92ea9329e5`)	2018-05-28 10:39:48 +02:00
Marek Olšák	8cf02769f5	st/mesa: simplify lastLevel determination in st_finalize_texture This fixes shader images where we always bind stObj->pt and not individual gl_texture_images. Roughly based on i965 commit `845ad2667a` which does a similar thing but for a different reason. This fixes GL CTS assertion failures introduced by Ilia. Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit `a4ba7cd6a2`)	2018-05-28 10:39:48 +02:00
Jose Dapena Paz	1939affe51	mesa: do not leak ctx->Shader.ReferencedProgram references When glUseProgram is used, references to the included shaders are added in ctx->Shader.ReferencedProgram. But those references are not decreased when the shader data is deallocated. Thus, those shaders are leaked. Explicitely remove the pending references to these shaders. Fixes: `e6506b3cd2` ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use") Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit `6c61c31dc2`)	2018-05-25 09:59:18 +02:00
Francisco Jerez	42fa7cf2bb	i965: Use intel_bufferobj_buffer() wrapper in image surface state setup. Instead of directly using intel_obj->buffer. Among other things intel_bufferobj_buffer() will update intel_buffer_object:: gpu_active_start/end, which are used by glBufferSubData() to decide which path to take. Fixes a failure in the Piglit ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests, which could be reproduced with a non-standard glGetTexSubImage implementation (see bug report). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351 Reported-by: Nanley Chery <nanleychery@gmail.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit `936cd3c87a`)	2018-05-24 10:35:26 +00:00
Francisco Jerez	86e749a96e	i965: Handle non-zero texture buffer offsets in buffer object range calculation. Otherwise the specified surface state will allow the GPU to access memory up to BufferOffset bytes past the end of the buffer. Found by inspection. v2: Protect against out-of-range BufferOffset (Nanley). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit `e989acb03b`)	2018-05-24 10:35:26 +00:00
Francisco Jerez	03eaee1529	i965: Move buffer texture size calculation into a common helper function. The buffer texture size calculations (should be easy enough, right?) are repeated in three different places, each of them subtly broken in a different way. E.g. the image load/store path was never fixed to clamp to MaxTextureBufferSize, and none of them are taking into account the buffer offset correctly. It's easier to fix it all in one place. Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481 Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit `156d2c6e62`)	2018-05-24 10:35:26 +00:00
Francisco Jerez	8d5f09e8ef	Revert "mesa: simplify _mesa_is_image_unit_valid for buffers" This reverts commit `c0ed52f614`. It was preventing the image format validation from being done on buffer textures, which is required to ensure that the application doesn't attempt to bind a buffer texture with an internal format incompatible with the image unit format (e.g. of different texel size), which is not allowed by the spec (it's not allowed for any texture target, whether or not there is spec wording restricting this behavior specifically for buffer textures) and will cause the driver to calculate texel bounds incorrectly and potentially crash instead of the expected behavior. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465 Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (cherry picked from commit `5a68147803`)	2018-05-24 10:35:26 +00:00
Jason Ekstrand	a93a86a434	intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0 Fixes: `d6cd14f213` "i965/fs: Define new shader opcode to..." Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> (cherry picked from commit `417b9e5770`)	2018-05-23 16:28:02 +02:00
Dave Airlie	6a0c2860e7	tgsi/scan: add hw atomic to the list of memory accessing files This fixes 4 out of 5 cases in: arb_framebuffer_no_attachments-atomic on cayman. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org> (cherry picked from commit `f2f464de57`)	2018-05-23 16:28:02 +02:00
Michel Dänzer	b582b8fc93	dri3: Stricter SBC wraparound handling Prevents corrupting the upper 32 bits of draw->recv_sbc when draw->send_sbc resets to 0 (which currently happens when the window is unbound from a context and bound to one again), which in turn caused loader_dri3_swap_buffers_msc to calculate target_msc with corrupted upper 32 bits. This resulted in hangs with the Xorg modesetting driver as of xserver 1.20 (older versions and other drivers ignored the upper 32 bits of the target MSC, which is why this wasn't noticed earlier). Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/106351 Tested-by: Mike Lothian <mike@fireburn.co.uk> (cherry picked from commit `fe2edb25dd`) [Juan A. Suarez: resolve trivial conflicts] Conflicts: src/loader/loader_dri3_helper.c	2018-05-23 16:28:02 +02:00
Samuel Pitoiset	96b1ac39d5	radv: fix centroid interpolation It's legal to set the centroid and sample interpolation modes when MSAA disabled. So, we have to initialize the centroid inputs because the hardware doesn't. This fixes rendering issues with DXVK and The Witness, World of Warcraft, Trackmania and probably more games. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390 CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit `73df16dcee`) [Juan A. Suarez: apply change in src/amd/common/ac_nir_to_llvm.c] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c	2018-05-22 13:03:34 +02:00
Anuj Phogat	f844591ee3	i965/glk: Add l3 banks count for 2x6 configuration 2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <clayton.a.craft@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Clayton Craft <clayton.a.craft@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: `eb23be1d97` "i965: Add and initialize l3_banks field for gen7+" Cc: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit `0748383a60`)	2018-05-22 13:03:34 +02:00
Timothy Arceri	620be4d431	mesa: add glUniform*ui{v} support to display lists Fixes: `a017c7ecb7` "mesa: display list support for uint uniforms" Reviewed-by: Marek Olšák <marek.olsak@amd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097 (cherry picked from commit `f71714022b`)	2018-05-22 13:03:34 +02:00
Juan A. Suarez Romero	5443d85870	cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too fixes: The commit fixes earlier commits `19a91841c3` and `9987a072cb` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-22 13:03:34 +02:00
Bas Nieuwenhuizen	5cef37e909	radv: Fix SRGB compute copies. SRGB stores are broken. We had compensation code in the resolve path but none in the copy path. Since we don't want any conversion and it does not matter for DCC, just make everything UNORM instead. This happened to cause wrong colors for the PRIME path, as that uses image->buffer copies which always use the compute path. CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587 Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `a63a0960e3`)	2018-05-22 13:03:34 +02:00
Juan A. Suarez Romero	e7b5064045	cherry-ignore: add explicit 18.1 only nominations Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-22 13:03:34 +02:00
Bas Nieuwenhuizen	6ce8a775a7	amd/addrlib: Use defines in autotools build. Otherwise stuff like NDEBUG would not be passed through. CC: <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit `62e0e089d7`)	2018-05-22 13:03:34 +02:00
Nanley Chery	3b7134c535	i965/miptree: Zero-initialize CCS_D buffers Before this patch, the aux_state was actually AUX_INVALID because the BO was never defined. This was fine on single slice miptrees because we would fast-clear the resource right after creation. For multi-slice miptrees on SKL+ however, this results in undefined behavior when accessing a non-base slice. Here's a specific example: 1) Fast clear level 0 * Undefined CCS_D buffer allocated in "PASS_THROUGH" state. * Level 0 transitions to the CLEAR state. 2) Render to level 1 * Level 1 may have a 2-bit pattern of 2's. * Rendering with a 2 in the CCS is undefined. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit `8a9491058d`) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Conflicts: src/mesa/drivers/dri/i965/intel_mipmap_tree.c	2018-05-22 13:03:34 +02:00
Juan A. Suarez Romero	544a383858	cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers stable: The commit requires earlier commit `af4e9295fe` which did not land in branch. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-22 13:03:34 +02:00
Stuart Young	f084db8870	etnaviv: Fix missing rnndb file in tarballs Seems that when the rnndb files for etniviv were updated/included back in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and meson.build. This was all during the conversion to meson, so it apears to have slipped through the cracks. As such, this file has been missing from the official tarballs since inclusion in Mesa, so the git trees and tarballs differ. Found due to lintian errors in the Debian packages. Fixes: `f1e1c60ff6` ("etnaviv: Update from rnndb") Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> (cherry picked from commit `f806cc9eb6`)	2018-05-22 13:03:34 +02:00
Jan Vesely	712456cb38	eg/compute: Use reference counting to handle compute memory pool. Use pipe_reference to release old RAT surfaces. RAT surface adds a reference to pool bo, so use reference counting for pool->bo as well. v2: Use the same pattern for both defrag paths Drop confusing comment CC: <mesa-stable@lists.freedesktop.org> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `f3521ce2c4`)	2018-05-22 13:03:34 +02:00
Samuel Pitoiset	0f7b29aa93	spirv: fix visiting inner loops with same break/continue block We should stop walking through the CFG when the inner loop's break block ends up as the same block as the outer loop's continue block because we are already going to visit it. This fixes the following assertion which ends up by crashing in RADV or ANV: SPIR-V parsing FAILED: In file ../src/compiler/spirv/vtn_cfg.c:381 block->node.link.next == NULL 0 bytes into the SPIR-V binary This also fixes a crash with a camera shader from SteamVR. v2: make use of vtn_get_branch_type() and add an assertion Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504 CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit `6bde8c5608`)	2018-05-22 13:03:34 +02:00
Juan A. Suarez Romero	69ef6e4a75	docs: add sha256 checksums for 18.0.4 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2018-05-17 18:40:11 +00:00
@@ -1 +1 @@
 .0.4
 .0.5