docs: Update 18.0.0 release notes

Note: the file was originally 17.4.0, yet git stuggles to detect the
move :-\

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

.mailmap

@@ -148,8 +148,6 @@ Emil Velikov <emil.l.velikov@gmail.com> <emil.velikov@collabora.com>
 
 Eric Anholt <eric@anholt.net> Eric Anholt <anholt@FreeBSD.org>
 
-Eric Engestrom <eric@engestrom.ch> <eric.engestrom@imgtec.com>
-
 Eugeni Dodonov <eugeni.dodonov@intel.com> <eugeni@mandriva.com>
 
 Fabian Bieler <der.fabe@gmx.net> <fabianbieler@fastmail.fm>

.travis.yml

@@ -17,8 +17,8 @@ env:
     - DRI2PROTO_VERSION=dri2proto-2.8
     - LIBPCIACCESS_VERSION=libpciaccess-0.13.4
     - LIBDRM_VERSION=libdrm-2.4.74
-    - XCBPROTO_VERSION=xcb-proto-1.13
-    - LIBXCB_VERSION=libxcb-1.13
+    - XCBPROTO_VERSION=xcb-proto-1.11
+    - LIBXCB_VERSION=libxcb-1.11
     - LIBXSHMFENCE_VERSION=libxshmfence-1.2
     - LIBVDPAU_VERSION=libvdpau-1.1
     - LIBVA_VERSION=libva-1.6.2
@@ -39,12 +39,12 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-4.0
+            - llvm-toolchain-trusty-3.9
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-4.0-dev
+            - llvm-3.9-dev
             # Common
             - xz-utils
             - libexpat1-dev
@@ -92,10 +92,12 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=4.0
+        - LLVM_VERSION=3.9
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - OVERRIDE_CC="gcc-4.8"
         - OVERRIDE_CXX="g++-4.8"
+        # New binutils linker is required for llvm-3.9
+        - OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -105,41 +107,13 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-4.0
+            - llvm-toolchain-trusty-3.9
           packages:
+            - binutils-2.26
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-4.0-dev
-            # Common
-            - xz-utils
-            - x11proto-xf86vidmode-dev
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-    - env:
-        - LABEL="make Gallium Drivers RadeonSI"
-        - BUILD=make
-        - MAKEFLAGS="-j4"
-        - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=4.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-        - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
-        - DRI_DRIVERS=""
-        - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="radeonsi"
-        - VULKAN_DRIVERS=""
-        - LIBUNWIND_FLAGS="--enable-libunwind"
-      addons:
-        apt:
-          sources:
-            - llvm-toolchain-trusty-4.0
-          packages:
-            # LLVM packaging is broken and misses these dependencies
-            - libedit-dev
-            # From sources above
-            - llvm-4.0-dev
+            - llvm-3.9-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -159,7 +133,7 @@ matrix:
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
+        - GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
@@ -194,7 +168,7 @@ matrix:
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="r600"
+        - GALLIUM_DRIVERS="r600,radeonsi"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
@@ -331,8 +305,10 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel check"
-        - LLVM_VERSION=4.0
+        - LLVM_VERSION=3.9
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+        # New binutils linker is required for llvm-3.9
+        - OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl --with-platforms=x11,wayland"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -342,12 +318,13 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-4.0
+            - llvm-toolchain-trusty-3.9
           packages:
+            - binutils-2.26
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-4.0-dev
+            - llvm-3.9-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -399,7 +376,7 @@ matrix:
         - BUILD=scons
         - SCONSFLAGS="-j4"
         - SCONS_TARGET="swr=1"
-        - LLVM_VERSION=4.0
+        - LLVM_VERSION=3.9
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         # Keep it symmetrical to the make build. There's no actual SWR, yet.
         - SCONS_CHECK_COMMAND="true"
@@ -408,13 +385,13 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-4.0
+            - llvm-toolchain-trusty-3.9
           packages:
             - scons
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-4.0-dev
+            - llvm-3.9-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -428,11 +405,6 @@ matrix:
         - MAKE_CHECK_COMMAND="make check"
         - DRI_LOADERS="--with-platforms=x11 --disable-egl"
       os: osx
-    - env:
-        - LABEL="macOS meson"
-        - BUILD=meson
-        - MESON_OPTIONS="-Degl=false"
-      os: osx
 
 before_install:
   - |

Android.common.mk

@@ -70,7 +70,6 @@ LOCAL_CFLAGS += \
 	-DHAVE_DLADDR \
 	-DHAVE_DL_ITERATE_PHDR \
 	-DHAVE_LINUX_FUTEX_H \
-	-DHAVE_ENDIAN_H \
 	-DHAVE_ZLIB \
 	-DMAJOR_IN_SYSMACROS \
 	-fvisibility=hidden \

Makefile.am

@@ -45,7 +45,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-libunwind \
 	--with-platforms=x11,wayland,drm,surfaceless \
 	--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
-	--with-gallium-drivers=i915,nouveau,r300,pl111,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv,imx \
+	--with-gallium-drivers=i915,nouveau,r300,pl111,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr,etnaviv,imx \
 	--with-vulkan-drivers=intel,radeon
 
 ACLOCAL_AMFLAGS = -I m4
@@ -64,8 +64,7 @@ EXTRA_DIST = \
 	meson_options.txt \
 	bin/meson.build \
 	include/meson.build \
-	bin/install_megadrivers.py \
-	bin/meson_get_version.py
+	bin/install_megadrivers.py
 
 noinst_HEADERS = \
 	include/c99_alloca.h \
@@ -76,14 +75,12 @@ noinst_HEADERS = \
 	include/drm-uapi/drm_fourcc.h \
 	include/drm-uapi/drm_mode.h \
 	include/drm-uapi/i915_drm.h \
-	include/drm-uapi/tegra_drm.h \
 	include/drm-uapi/vc4_drm.h \
 	include/D3D9 \
 	include/GL/wglext.h \
 	include/HaikuGL \
 	include/no_extern_c.h \
-	include/pci_ids \
-	include/vulkan
+	include/pci_ids
 
 # We list some directories in EXTRA_DIST, but don't actually want to include
 # the .gitignore files in the tarball.

VERSION

@@ -1 +1 @@
-18.1.0-rc1
+18.0.0

appveyor.yml

@@ -35,13 +35,13 @@ clone_depth: 100
 
 cache:
 - win_flex_bison-2.5.9.zip
-- llvm-3.3.1-msvc2015-mtd.7z
+- llvm-3.3.1-msvc2013-mtd.7z
 
-os: Visual Studio 2015
+os: Visual Studio 2013
 
 environment:
   WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip
-  LLVM_ARCHIVE: llvm-3.3.1-msvc2015-mtd.7z
+  LLVM_ARCHIVE: llvm-3.3.1-msvc2013-mtd.7z
 
 install:
 # Check pip
@@ -69,10 +69,10 @@ install:
 - set LLVM=%CD%\llvm
 
 build_script:
-- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1
+- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=12.0 llvm=1
 
 after_build:
-- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1 check
+- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=12.0 llvm=1 check
 
 
 # It's possible to setup notification here, as described in

bin/.cherry-ignore

@@ -0,0 +1,6 @@
+# fixes: The following commits were applied without the "cherry-picked from" tag
+50265cd9ee4caffee853700bdcd75b92eedc0e7b automake: anv: ship anv_extensions_gen.py in the tarball
+ac4437b20b87c7285b89466f05b51518ae616873 automake: small cleanup after the meson.build inclusion
+
+# stable: The KHX extension is disabled all together in the stable branches.
+2ffe395cba0f7b3c1f1c41062f4376eae3a188b5 radv: Don't expose VK_KHX_multiview on android.

bin/install_megadrivers.py

@@ -58,7 +58,7 @@ def main():
             while ext != '.so':
                 if os.path.exists(name):
                     os.unlink(name)
-                os.symlink(each, name)
+                os.symlink(driver, name)
                 name, ext = os.path.splitext(name)
         finally:
             os.chdir(ret)

configure.ac

@@ -74,27 +74,24 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.91
+LIBDRM_AMDGPU_REQUIRED=2.4.89
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
-LIBDRM_FREEDRENO_REQUIRED=2.4.91
-LIBDRM_ETNAVIV_REQUIRED=2.4.89
+LIBDRM_FREEDRENO_REQUIRED=2.4.89
+LIBDRM_ETNAVIV_REQUIRED=2.4.82
 
 dnl Versions for external dependencies
 DRI2PROTO_REQUIRED=2.8
 GLPROTO_REQUIRED=1.4.14
 LIBOMXIL_BELLAGIO_REQUIRED=0.0
-LIBOMXIL_TIZONIA_REQUIRED=0.10.0
 LIBVA_REQUIRED=0.38.0
 VDPAU_REQUIRED=1.1
 WAYLAND_REQUIRED=1.11
 WAYLAND_PROTOCOLS_REQUIRED=1.8
 XCB_REQUIRED=1.9.3
 XCBDRI2_REQUIRED=1.8
-XCBDRI3_MODIFIERS_REQUIRED=1.13
 XCBGLX_REQUIRED=1.8.1
-XCBPRESENT_MODIFIERS_REQUIRED=1.13
 XDAMAGE_REQUIRED=1.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
@@ -106,9 +103,9 @@ dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
 LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
-LLVM_REQUIRED_RADEONSI=4.0.0
-LLVM_REQUIRED_RADV=4.0.0
-LLVM_REQUIRED_SWR=4.0.0
+LLVM_REQUIRED_RADEONSI=3.9.0
+LLVM_REQUIRED_RADV=3.9.0
+LLVM_REQUIRED_SWR=3.9.0
 
 dnl Check for progs
 AC_PROG_CPP
@@ -119,7 +116,6 @@ dnl other CC/CXX flags related help
 AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only needed if not
                               enabled by default and different  from -std=c++11)])
 AM_PROG_CC_C_O
-AC_PROG_NM
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
 AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
@@ -454,6 +450,7 @@ if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
         LIBATOMIC_LIBS="-latomic"
     fi
 fi
+AM_CONDITIONAL([GCC_ATOMIC_BUILTINS_SUPPORTED], [test x$GCC_ATOMIC_BUILTINS_SUPPORTED = x1])
 AC_SUBST([LIBATOMIC_LIBS])
 
 dnl Check if host supports 64-bit atomics
@@ -865,7 +862,6 @@ fi
 AC_HEADER_MAJOR
 AC_CHECK_HEADER([xlocale.h], [DEFINES="$DEFINES -DHAVE_XLOCALE_H"])
 AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES -DHAVE_SYS_SYSCTL_H"])
-AC_CHECK_HEADERS([endian.h])
 AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
 AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])
 AC_CHECK_FUNC([timespec_get], [DEFINES="$DEFINES -DHAVE_TIMESPEC_GET"])
@@ -1315,19 +1311,14 @@ AC_ARG_ENABLE([vdpau],
    [enable_vdpau=auto])
 AC_ARG_ENABLE([omx],
    [AS_HELP_STRING([--enable-omx],
-         [DEPRECATED: Use --enable-omx-bellagio or --enable-omx-tizonia instead @<:@default=auto@:>@])],
-   [AC_MSG_ERROR([--enable-omx is deprecated. Use --enable-omx-bellagio or --enable-omx-tizonia instead.])],
+         [DEPRECATED: Use --enable-omx-bellagio instead @<:@default=auto@:>@])],
+   [AC_MSG_ERROR([--enable-omx is deprecated. Use --enable-omx-bellagio instead.])],
    [])
 AC_ARG_ENABLE([omx-bellagio],
    [AS_HELP_STRING([--enable-omx-bellagio],
          [enable OpenMAX Bellagio library @<:@default=disabled@:>@])],
    [enable_omx_bellagio="$enableval"],
    [enable_omx_bellagio=no])
-AC_ARG_ENABLE([omx-tizonia],
-   [AS_HELP_STRING([--enable-omx-tizonia],
-         [enable OpenMAX Tizonia library @<:@default=disabled@:>@])],
-   [enable_omx_tizonia="$enableval"],
-   [enable_omx_tizonia=no])
 AC_ARG_ENABLE([va],
    [AS_HELP_STRING([--enable-va],
          [enable va library @<:@default=auto@:>@])],
@@ -1359,7 +1350,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast"
 AC_ARG_WITH([gallium-drivers],
     [AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@],
         [comma delimited Gallium drivers list, e.g.
-        "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,vc4,vc5,virgl,etnaviv,imx"
+        "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,vc4,vc5,virgl,etnaviv,imx"
         @<:@default=r300,r600,svga,swrast@:>@])],
     [with_gallium_drivers="$withval"],
     [with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"])
@@ -1379,17 +1370,11 @@ if test "x$enable_opengl" = xno -a \
         "x$enable_xvmc" = xno -a \
         "x$enable_vdpau" = xno -a \
         "x$enable_omx_bellagio" = xno -a \
-        "x$enable_omx_tizonia" = xno -a \
         "x$enable_va" = xno -a \
         "x$enable_opencl" = xno; then
     AC_MSG_ERROR([at least one API should be enabled])
 fi
 
-if test "x$enable_omx_bellagio" = xyes -a \
-        "x$enable_omx_tizonia" = xyes; then
-   AC_MSG_ERROR([Can't enable both bellagio and tizonia at same time])
-fi
-
 # Building OpenGL ES1 and/or ES2 without OpenGL is not supported on mesa 9.0.x
 if test "x$enable_opengl" = xno -a \
         "x$enable_gles1" = xyes; then
@@ -1785,6 +1770,19 @@ if test "x$with_platforms" = xauto; then
     with_platforms=$with_egl_platforms
 fi
 
+PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
+        WAYLAND_SCANNER=`$PKG_CONFIG --variable=wayland_scanner wayland-scanner`,
+        WAYLAND_SCANNER='')
+if test "x$WAYLAND_SCANNER" = x; then
+    AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner], [:])
+fi
+
+PKG_CHECK_EXISTS([wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED], [have_wayland_protocols=yes], [have_wayland_protocols=no])
+if test "x$have_wayland_protocols" = xyes; then
+    ac_wayland_protocols_pkgdatadir=`$PKG_CONFIG --variable=pkgdatadir wayland-protocols`
+fi
+AC_SUBST(WAYLAND_PROTOCOLS_DATADIR, $ac_wayland_protocols_pkgdatadir)
+
 # Do per platform setups and checks
 platforms=`IFS=', '; echo $with_platforms`
 for plat in $platforms; do
@@ -1793,19 +1791,13 @@ for plat in $platforms; do
 
         PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >= $WAYLAND_REQUIRED])
         PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >= $WAYLAND_REQUIRED])
-        PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED])
-        WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir wayland-protocols`
-
-        PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
-                          WAYLAND_SCANNER=`$PKG_CONFIG --variable=wayland_scanner wayland-scanner`,
-                          WAYLAND_SCANNER='')
-        if test "x$WAYLAND_SCANNER" = x; then
-            AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner], [:])
-        fi
 
         if test "x$WAYLAND_SCANNER" = "x:"; then
                 AC_MSG_ERROR([wayland-scanner is needed to compile the wayland platform])
         fi
+        if test "x$have_wayland_protocols" = xno; then
+                AC_MSG_ERROR([wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED is needed to compile the wayland platform])
+        fi
         DEFINES="$DEFINES -DHAVE_WAYLAND_PLATFORM -DWL_HIDE_DEPRECATED"
         ;;
 
@@ -1840,7 +1832,6 @@ for plat in $platforms; do
         ;;
     esac
 done
-AC_SUBST([WAYLAND_PROTOCOLS_DATADIR])
 
 if test "x$enable_glx" != xno; then
     if ! echo "$platforms" | grep -q 'x11'; then
@@ -1853,12 +1844,6 @@ if test x"$enable_dri3" = xyes; then
 
     dri3_modules="x11-xcb xcb >= $XCB_REQUIRED xcb-dri3 xcb-xfixes xcb-present xcb-sync xshmfence >= $XSHMFENCE_REQUIRED"
     PKG_CHECK_MODULES([XCB_DRI3], [$dri3_modules])
-    dri3_modifier_modules="xcb-dri3 >= $XCBDRI3_MODIFIERS_REQUIRED xcb-present >= $XCBPRESENT_MODIFIERS_REQUIRED"
-    PKG_CHECK_MODULES([XCB_DRI3_MODIFIERS], [$dri3_modifier_modules], [have_dri3_modifiers=yes], [have_dri3_modifiers=no])
-
-    if test "x$have_dri3_modifiers" == xyes; then
-        DEFINES="$DEFINES -DHAVE_DRI3_MODIFIERS"
-    fi
 fi
 
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
@@ -2230,10 +2215,6 @@ if test -n "$with_gallium_drivers" -a "x$with_gallium_drivers" != xswrast; then
         PKG_CHECK_EXISTS([libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED], [enable_omx_bellagio=yes], [enable_omx_bellagio=no])
     fi
 
-    if test "x$enable_omx_tizonia" = xauto -a "x$have_omx_platform" = xyes; then
-       PKG_CHECK_EXISTS([libtizonia >= $LIBOMXIL_TIZONIA_REQUIRED], [enable_omx_tizonia=yes], [enable_omx_tizonia=no])
-    fi
-
     if test "x$enable_va" = xauto -a "x$have_va_platform" = xyes; then
         PKG_CHECK_EXISTS([libva >= $LIBVA_REQUIRED], [enable_va=yes], [enable_va=no])
     fi
@@ -2243,7 +2224,6 @@ if test "x$enable_dri" = xyes -o \
         "x$enable_xvmc" = xyes -o \
         "x$enable_vdpau" = xyes -o \
         "x$enable_omx_bellagio" = xyes -o \
-        "x$enable_omx_tizonia" = xyes -o \
         "x$enable_va" = xyes; then
     need_gallium_vl=yes
 fi
@@ -2252,7 +2232,6 @@ AM_CONDITIONAL(NEED_GALLIUM_VL, test "x$need_gallium_vl" = xyes)
 if test "x$enable_xvmc" = xyes -o \
         "x$enable_vdpau" = xyes -o \
         "x$enable_omx_bellagio" = xyes -o \
-        "x$enable_omx_tizonia" = xyes -o \
         "x$enable_va" = xyes; then
     if echo $platforms | grep -q "x11"; then
         PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED])
@@ -2286,27 +2265,9 @@ if test "x$enable_omx_bellagio" = xyes; then
     fi
     PKG_CHECK_MODULES([OMX_BELLAGIO], [libomxil-bellagio >= $LIBOMXIL_BELLAGIO_REQUIRED])
     gallium_st="$gallium_st omx_bellagio"
-    AC_DEFINE([ENABLE_ST_OMX_BELLAGIO], 1, [Use Bellagio for OMX IL])
-else
-    AC_DEFINE([ENABLE_ST_OMX_BELLAGIO], 0)
 fi
 AM_CONDITIONAL(HAVE_ST_OMX_BELLAGIO, test "x$enable_omx_bellagio" = xyes)
 
-if test "x$enable_omx_tizonia" = xyes; then
-    if test "x$have_omx_platform" != xyes; then
-        AC_MSG_ERROR([OMX requires at least one of the x11 or drm platforms])
-    fi
-    PKG_CHECK_MODULES([OMX_TIZONIA],
-                      [libtizonia >= $LIBOMXIL_TIZONIA_REQUIRED
-                       tizilheaders >= $LIBOMXIL_TIZONIA_REQUIRED
-                       libtizplatform >= $LIBOMXIL_TIZONIA_REQUIRED])
-    gallium_st="$gallium_st omx_tizonia"
-    AC_DEFINE([ENABLE_ST_OMX_TIZONIA], 1, [Use Tizoina for OMX IL])
-else
-    AC_DEFINE([ENABLE_ST_OMX_TIZONIA], 0)
-fi
-AM_CONDITIONAL(HAVE_ST_OMX_TIZONIA, test "x$enable_omx_tizonia" = xyes)
-
 if test "x$enable_va" = xyes; then
     if test "x$have_va_platform" != xyes; then
         AC_MSG_ERROR([VA requires at least one of the x11 drm or wayland platforms])
@@ -2480,15 +2441,6 @@ AC_ARG_WITH([omx-bellagio-libdir],
                                    $PKG_CONFIG --define-variable=libdir=\$libdir --variable=pluginsdir libomxil-bellagio`])
 AC_SUBST([OMX_BELLAGIO_LIB_INSTALL_DIR])
 
-dnl Directory for OMX_TIZONIA libs
-
-AC_ARG_WITH([omx-tizonia-libdir],
-    [AS_HELP_STRING([--with-omx-tizonia-libdir=DIR],
-        [directory for the OMX_TIZONIA libraries])],
-    [OMX_TIZONIA_LIB_INSTALL_DIR="$withval"],
-    [OMX_TIZONIA_LIB_INSTALL_DIR=`$PKG_CONFIG --define-variable=libdir=\$libdir --variable=pluginsdir libtizcore`])
-AC_SUBST([OMX_TIZONIA_LIB_INSTALL_DIR])
-
 dnl Directory for VA libs
 
 AC_ARG_WITH([va-libdir],
@@ -2619,6 +2571,14 @@ if test -n "$with_gallium_drivers"; then
             HAVE_GALLIUM_RADEONSI=yes
             PKG_CHECK_MODULES([RADEON], [libdrm >= $LIBDRM_RADEON_REQUIRED libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
             PKG_CHECK_MODULES([AMDGPU], [libdrm >= $LIBDRM_AMDGPU_REQUIRED libdrm_amdgpu >= $LIBDRM_AMDGPU_REQUIRED])
+
+            # Blacklist libdrm_amdgpu 2.4.90 because it causes a crash in older
+            # radeonsi with pretty much any app.
+            libdrm_version=`pkg-config libdrm_amdgpu --modversion`
+            if test "x$libdrm_version" = x2.4.90; then
+                AC_MSG_ERROR([radeonsi can't use libdrm 2.4.90 due to a compatibility issue. Use a newer or older version.])
+            fi
+
             require_libdrm "radeonsi"
             radeon_llvm_check $LLVM_REQUIRED_RADEONSI "radeonsi"
             if test "x$enable_egl" = xyes; then
@@ -2643,10 +2603,6 @@ if test -n "$with_gallium_drivers"; then
        ximx)
             HAVE_GALLIUM_IMX=yes
             ;;
-        xtegra)
-            HAVE_GALLIUM_TEGRA=yes
-            require_libdrm "tegra"
-            ;;
         xswrast)
             HAVE_GALLIUM_SOFTPIPE=yes
             if test "x$enable_llvm" = xyes; then
@@ -2747,8 +2703,8 @@ if test -n "$with_gallium_drivers"; then
 fi
 
 # XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
-                                              "x$LLVM_VERSION" != x4.0.1)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x3.9.0 -a \
+                                              "x$LLVM_VERSION" != x3.9.1)
 
 if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
     llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
@@ -2771,9 +2727,6 @@ if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_PL111" = xyes  ; then
     AC_MSG_ERROR([Building with pl111 requires vc4])
 fi
 
-if test "x$HAVE_GALLIUM_NOUVEAU" != xyes -a "x$HAVE_GALLIUM_TEGRA" = xyes; then
-    AC_MSG_ERROR([Building with tegra requires nouveau])
-fi
 
 detect_old_buggy_llvm() {
     dnl llvm-config may not give the right answer when llvm is a built as a
@@ -2868,11 +2821,11 @@ AM_CONDITIONAL(HAVE_GALLIUM_PL111, test "x$HAVE_GALLIUM_PL111" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_R300, test "x$HAVE_GALLIUM_R300" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_R600, test "x$HAVE_GALLIUM_R600" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_RADEONSI, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
+AM_CONDITIONAL(HAVE_GALLIUM_RADEON_COMMON, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_NOUVEAU, test "x$HAVE_GALLIUM_NOUVEAU" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_ETNAVIV, test "x$HAVE_GALLIUM_ETNAVIV" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_IMX, test "x$HAVE_GALLIUM_IMX" = xyes)
-AM_CONDITIONAL(HAVE_GALLIUM_TEGRA, test "x$HAVE_GALLIUM_TEGRA" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_SOFTPIPE, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_LLVMPIPE, test "x$HAVE_GALLIUM_LLVMPIPE" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_SWR, test "x$HAVE_GALLIUM_SWR" = xyes)
@@ -3011,17 +2964,21 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/auxiliary/Makefile
                  src/gallium/auxiliary/pipe-loader/Makefile
                  src/gallium/drivers/freedreno/Makefile
+                 src/gallium/drivers/ddebug/Makefile
                  src/gallium/drivers/i915/Makefile
                  src/gallium/drivers/llvmpipe/Makefile
+                 src/gallium/drivers/noop/Makefile
                  src/gallium/drivers/nouveau/Makefile
                  src/gallium/drivers/pl111/Makefile
                  src/gallium/drivers/r300/Makefile
                  src/gallium/drivers/r600/Makefile
+                 src/gallium/drivers/radeon/Makefile
                  src/gallium/drivers/radeonsi/Makefile
+                 src/gallium/drivers/rbug/Makefile
                  src/gallium/drivers/softpipe/Makefile
                  src/gallium/drivers/svga/Makefile
                  src/gallium/drivers/swr/Makefile
-                 src/gallium/drivers/tegra/Makefile
+                 src/gallium/drivers/trace/Makefile
                  src/gallium/drivers/etnaviv/Makefile
                  src/gallium/drivers/imx/Makefile
                  src/gallium/drivers/vc4/Makefile
@@ -3031,9 +2988,7 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/state_trackers/dri/Makefile
                  src/gallium/state_trackers/glx/xlib/Makefile
                  src/gallium/state_trackers/nine/Makefile
-                 src/gallium/state_trackers/omx/Makefile
-                 src/gallium/state_trackers/omx/bellagio/Makefile
-                 src/gallium/state_trackers/omx/tizonia/Makefile
+                 src/gallium/state_trackers/omx_bellagio/Makefile
                  src/gallium/state_trackers/osmesa/Makefile
                  src/gallium/state_trackers/va/Makefile
                  src/gallium/state_trackers/vdpau/Makefile
@@ -3044,7 +2999,7 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/targets/d3dadapter9/d3d.pc
                  src/gallium/targets/dri/Makefile
                  src/gallium/targets/libgl-xlib/Makefile
-                 src/gallium/targets/omx/Makefile
+                 src/gallium/targets/omx-bellagio/Makefile
                  src/gallium/targets/opencl/Makefile
                  src/gallium/targets/opencl/mesa.icd
                  src/gallium/targets/osmesa/Makefile
@@ -3071,7 +3026,6 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/winsys/sw/null/Makefile
                  src/gallium/winsys/sw/wrapper/Makefile
                  src/gallium/winsys/sw/xlib/Makefile
-                 src/gallium/winsys/tegra/drm/Makefile
                  src/gallium/winsys/vc4/drm/Makefile
                  src/gallium/winsys/vc5/drm/Makefile
                  src/gallium/winsys/virgl/drm/Makefile
@@ -3121,9 +3075,6 @@ $SED -i -e 's/brw_blorp.cpp/brw_blorp.c/' src/mesa/drivers/dri/i965/.deps/brw_bl
 rm -f src/compiler/spirv/spirv_info.lo
 echo "# dummy" > src/compiler/spirv/.deps/spirv_info.Plo
 
-rm -f src/compiler/nir/.deps/nir_intrinsics.Plo
-echo "# dummy" > src/compiler/nir/.deps/nir_intrinsics.Plo
-
 dnl
 dnl Output some configuration info for the user
 dnl

docs/envvars.html

@@ -88,40 +88,22 @@ This is a work-around for that.
 <li>MESA_GL_VERSION_OVERRIDE - changes the value returned by
 glGetString(GL_VERSION) and possibly the GL API type.
 <ul>
-  <li>The format should be MAJOR.MINOR[FC|COMPAT]
-  <li>FC is an optional suffix that indicates a forward compatible
-      context. This is only valid for versions &gt;= 3.0.
-  <li>COMPAT is an optional suffix that indicates a compatibility
-      context or GL_ARB_compatibility support. This is only valid for
-      versions &gt;= 3.1.
-  <li>GL versions &lt;= 3.0 are set to a compatibility (non-Core)
-      profile
-  <li>GL versions = 3.1, depending on the driver, it may or may not
-      have the ARB_compatibility extension enabled.
-  <li>GL versions &gt;= 3.2 are set to a Core profile
-  <li>Examples: 2.1, 3.0, 3.0FC, 3.1, 3.1FC, 3.1COMPAT, X.Y, X.YFC,
-      X.YCOMPAT.
-  <ul>
-    <li>2.1 - select a compatibility (non-Core) profile with GL
-        version 2.1.
-    <li>3.0 - select a compatibility (non-Core) profile with GL
-        version 3.0.
-    <li>3.0FC - select a Core+Forward Compatible profile with GL
-        version 3.0.
-    <li>3.1 - select GL version 3.1 with GL_ARB_compatibility enabled
-        per the driver default.
-    <li>3.1FC - select GL version 3.1 with forward compatibility and
-        GL_ARB_compatibility disabled.
-    <li>3.1COMPAT - select GL version 3.1 with GL_ARB_compatibility
-        enabled.
-    <li>X.Y - override GL version to X.Y without changing the profile.
-    <li>X.YFC - select a Core+Forward Compatible profile with GL
-        version X.Y.
-    <li>X.YCOMPAT - select a Compatibility profile with GL version
-        X.Y.
-  </ul>
-  <li>Mesa may not really implement all the features of the given
-      version. (for developers only)
+<li> The format should be MAJOR.MINOR[FC]
+<li> FC is an optional suffix that indicates a forward compatible context.
+This is only valid for versions &gt;= 3.0.
+<li> GL versions &lt; 3.0 are set to a compatibility (non-Core) profile
+<li> GL versions = 3.0, see below
+<li> GL versions &gt; 3.0 are set to a Core profile
+<li> Examples: 2.1, 3.0, 3.0FC, 3.1, 3.1FC
+<ul>
+<li> 2.1 - select a compatibility (non-Core) profile with GL version 2.1
+<li> 3.0 - select a compatibility (non-Core) profile with GL version 3.0
+<li> 3.0FC - select a Core+Forward Compatible profile with GL version 3.0
+<li> 3.1 - select a Core profile with GL version 3.1
+<li> 3.1FC - select a Core+Forward Compatible profile with GL version 3.1
+</ul>
+<li> Mesa may not really implement all the features of the given version.
+(for developers only)
 </ul>
 <li>MESA_GLES_VERSION_OVERRIDE - changes the value returned by
 glGetString(GL_VERSION) for OpenGL ES.
@@ -153,16 +135,6 @@ home directory.
 <li>MESA_NO_MINMAX_CACHE - when set, the minmax index cache is globally disabled.
 <li>MESA_SHADER_CAPTURE_PATH - see <a href="shading.html#capture">Capturing Shaders</a></li>
 <li>MESA_SHADER_DUMP_PATH and MESA_SHADER_READ_PATH - see <a href="shading.html#replacement">Experimenting with Shader Replacements</a></li>
-<li>MESA_VK_VERSION_OVERRIDE - changes the Vulkan physical device version
-    as returned in VkPhysicalDeviceProperties::apiVersion.
-  <ul>
-    <li>The format should be MAJOR.MINOR[.PATCH]</li>
-    <li>This will not let you force a version higher than the driver's
-        instance versionas advertised by vkEnumerateInstanceVersion</li>
-    <li>This can be very useful for debugging but some features may not be
-        implemented correctly. (For developers only)</li>
-  </ul>
-</li>
 </ul>
 
 
@@ -269,7 +241,7 @@ Mesa EGL supports different sets of environment variables.  See the
     Especially useful to toggle hud at specific points of application and
     disable for unencumbered viewing the rest of the time. For example, set
     GALLIUM_HUD_VISIBLE to false and GALLIUM_HUD_TOGGLE_SIGNAL to 10 (SIGUSR1).
-    Use kill -10 &lt;pid&gt; to toggle the hud as desired.
+    Use kill -10 <pid> to toggle the hud as desired.
 <li>GALLIUM_HUD_DUMP_DIR - specifies a directory for writing the displayed
     hud values into files.
 <li>GALLIUM_DRIVER - useful in combination with LIBGL_ALWAYS_SOFTWARE=true for
@@ -341,12 +313,6 @@ such as the OpenGL program's name and command line arguments.
 <li>See the driver code for other, lesser-used variables.
 </ul>
 
-<h3>WGL environment variables</h3>
-<ul>
-<li>WGL_SWAP_INTERVAL - to set a swap interval, equivalent to calling
-wglSwapIntervalEXT() in an application.  If this environment variable
-is set, application calls to wglSwapIntervalEXT() will have no effect.
-</ul>
 
 <h3>VA-API state tracker environment variables</h3>
 <ul>

docs/features.txt

@@ -24,13 +24,10 @@ not started
 
 # OpenGL Core and Compatibility context support
 
-Some drivers do not support the Compatibility profile or the
-ARB_compatibility extensions.  If an application does not request a
-specific version without the forward-compatiblity flag, such drivers
-will be limited to OpenGL 3.0.  If an application requests OpenGL 3.1,
-it will get a context that may or may not have the ARB_compatibility
-extension enabled.  Some of the later GL features are exposed in the 3.0
-context as extensions.
+OpenGL 3.1 and later versions are only supported with the Core profile.
+There are no plans to support GL_ARB_compatibility. The last supported OpenGL
+version with all deprecated features is 3.0. Some of the later GL features
+are exposed in the 3.0 context as extensions.
 
 
 Feature                                                 Status
@@ -191,12 +188,12 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
   GL_ARB_vertex_attrib_binding                          DONE (all drivers)
 
 
-GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
+GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi
 
   GL_MAX_VERTEX_ATTRIB_STRIDE                           DONE (all drivers)
-  GL_ARB_buffer_storage                                 DONE (freedreno, i965, nv50, llvmpipe, swr)
-  GL_ARB_clear_texture                                  DONE (i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_enhanced_layouts                               DONE (i965, nv50, llvmpipe, softpipe)
+  GL_ARB_buffer_storage                                 DONE (freedreno, i965, nv50, r600, llvmpipe, swr)
+  GL_ARB_clear_texture                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_enhanced_layouts                               DONE (i965, nv50, r600, llvmpipe, softpipe)
   - compile-time constant expressions                   DONE
   - explicit byte offsets for blocks                    DONE
   - forced alignment within blocks                      DONE
@@ -205,9 +202,9 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
   - input/output block locations                        DONE
   GL_ARB_multi_bind                                     DONE (all drivers)
   GL_ARB_query_buffer_object                            DONE (i965/hsw+)
-  GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_texture_stencil8                               DONE (freedreno, i965/hsw+, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_texture_stencil8                               DONE (freedreno, i965/hsw+, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
 
 GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
 
@@ -235,7 +232,7 @@ GL 4.6, GLSL 4.60
   GL_ARB_shader_group_vote                              DONE (i965, nvc0, radeonsi)
   GL_ARB_spirv_extensions                               in progress (Nicolai Hähnle, Ian Romanick)
   GL_ARB_texture_filter_anisotropic                     DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, softpipe (*), llvmpipe (*))
-  GL_ARB_transform_feedback_overflow_query              DONE (i965/gen6+, nvc0, radeonsi, llvmpipe, softpipe)
+  GL_ARB_transform_feedback_overflow_query              DONE (i965/gen6+, radeonsi, llvmpipe, softpipe)
   GL_KHR_no_error                                       DONE (all drivers)
 
 (*) softpipe and llvmpipe advertise 16x anisotropy but simply ignore the setting
@@ -272,7 +269,7 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi
 GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+
 
   GL_EXT_color_buffer_float                             DONE (all drivers)
-  GL_KHR_blend_equation_advanced                        DONE (i965, nvc0, radeonsi)
+  GL_KHR_blend_equation_advanced                        DONE (i965, nvc0)
   GL_KHR_debug                                          DONE (all drivers)
   GL_KHR_robustness                                     DONE (i965, nvc0, radeonsi)
   GL_KHR_texture_compression_astc_ldr                   DONE (freedreno, i965/gen9+)
@@ -319,8 +316,8 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_EXT_memory_object                                  DONE (radeonsi)
   GL_EXT_memory_object_fd                               DONE (radeonsi)
   GL_EXT_memory_object_win32                            not started
-  GL_EXT_semaphore                                      DONE (radeonsi)
-  GL_EXT_semaphore_fd                                   DONE (radeonsi)
+  GL_EXT_semaphore                                      not started
+  GL_EXT_semaphore_fd                                   not started
   GL_EXT_semaphore_win32                                not started
   GL_KHR_blend_equation_advanced_coherent               DONE (i965/gen9+)
   GL_KHR_texture_compression_astc_hdr                   DONE (i965/bxt)

docs/index.html

@@ -16,59 +16,6 @@
 
 <h1>News</h1>
 
-<h2>April 18, 2018</h2>
-<p>
-<a href="relnotes/18.0.1.html">Mesa 18.0.1</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>April 18, 2018</h2>
-<p>
-<a href="relnotes/17.3.9.html">Mesa 17.3.9</a> is released.
-This is a bug-fix release.
-<br>
-NOTE: It is anticipated that 17.3.9 will be the final release in the
-17.3 series. Users of 17.3 are encouraged to migrate to the 18.0
-series in order to obtain future fixes.
-</p>
-
-<h2>April 03, 2018</h2>
-<p>
-<a href="relnotes/17.3.8.html">Mesa 17.3.8</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>March 27, 2018</h2>
-<p>
-<a href="relnotes/18.0.0.html">Mesa 18.0.0</a> is released.  This is a
-new development release.  See the release notes for more information
-about the release.
-</p>
-
-<h2>March 21, 2018</h2>
-<p>
-<a href="relnotes/17.3.7.html">Mesa 17.3.7</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>February 26, 2018</h2>
-<p>
-<a href="relnotes/17.3.6.html">Mesa 17.3.6</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>February 19, 2018</h2>
-<p>
-<a href="relnotes/17.3.5.html">Mesa 17.3.5</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>February 15, 2018</h2>
-<p>
-<a href="relnotes/17.3.4.html">Mesa 17.3.4</a> is released.
-This is a bug-fix release.
-</p>
-
 <h2>January 18, 2018</h2>
 <p>
 <a href="relnotes/17.3.3.html">Mesa 17.3.3</a> is released.

docs/meson.html

@@ -18,20 +18,11 @@
 
 <h2 id="basic">1. Basic Usage</h2>
 
-<p><strong>The Meson build system is generally considered stable and ready
-for production</strong></p>
+<p><strong>The Meson build system for Mesa is still under active development,
+and should not be used in production environments.</strong></p>
 
-<p>The meson build is tested on on Linux, macOS, Cygwin and Haiku, it should
-work on FreeBSD, DragonflyBSD, NetBSD, and OpenBSD.</p>
-
-<p><strong>Mesa requires Meson >= 0.42.0 to build in general.</strong>
-
-Additionaly, to build the Clover OpenCL state tracker or the OpenSWR driver
-meson 0.44.0 or greater is required.
-
-Some older versions of meson do not check that they are too old and will error
-out in odd ways.
-</p>
+<p>The meson build is currently only tested on linux, and is known to not work
+on macOS, Windows, and haiku. This will be fixed.</p>
 
 <p>
 The meson program is used to configure the source directory and generates
@@ -120,7 +111,6 @@ change compiler in a configured build directory.
 </dd>
 
 
-<dl>
 <dt><code>LLVM</code></dt>
 <dd><p>Meson includes upstream logic to wrap llvm-config using it's standard
 dependncy interface. It will search $PATH (or %PATH% on windows) for
@@ -129,15 +119,15 @@ llvm-config, so using an LLVM from a non-standard path is as easy as
 </p></dd>
 </dl>
 
-<dl>
 <dt><code>PKG_CONFIG_PATH</code></dt>
 <dd><p>The
 <code>pkg-config</code> utility is a hard requirement for configuring and
-building Mesa on Unix-like systems. It is used to search for external libraries
-on the system. This environment variable is used to control the search path for
-<code>pkg-config</code>. For instance, setting
-<code>PKG_CONFIG_PATH=/usr/X11R6/lib/pkgconfig</code> will search for package
-metadata in <code>/usr/X11R6</code> before the standard directories.</p>
+building Mesa on Linux and *BSD. It is used to search for external libraries
+on the system. This environment variable is used to control the search
+path for <code>pkg-config</code>. For instance, setting
+<code>PKG_CONFIG_PATH=/usr/X11R6/lib/pkgconfig</code> will search for
+package metadata in <code>/usr/X11R6</code> before the standard
+directories.</p>
 </dd>
 </dl>
 
@@ -161,9 +151,9 @@ may interfer with debbugging as some code and validation will be optimized
 away.
 </p>
 
-<p> For those wishing to pass their own optimization flags, use the "plain"
-buildtype, which causes meson to inject no additional compiler arguments, only
-those in the C/CXXFLAGS and those that mesa itself defines.</p>
+<p> For those wishing to pass their own -O option, use the "plain" buildtype,
+which cuases meson to inject no additional compiler arguments, only those in
+the C/CXXFLAGS and those that mesa itself defines.</p>
 </dd>
 </dl>
 

docs/patents.txt

@@ -27,5 +27,5 @@ ARB_texture_float:
     enable this extension.
 
 
-[1] https://patents.google.com/patent/US6650327B1
+[1] https://www.google.com/patents/about?id=mIIOAAAAEBAJ&dq=6650327
 [2] https://www.opengl.org/registry/specs/ARB/texture_float.txt

docs/release-calendar.html

@@ -37,99 +37,69 @@ if you'd like to nominate a patch in the next stable release.
 <th>Release</th>
 <th>Release manager</th>
 <th>Notes</th>
+</tr>
 <tr>
-<td rowspan="3">18.0</td>
-<td>2018-04-20</td>
+<td rowspan="3">17.3</td>
+<td>2018-01-26</td>
+<td>17.3.4</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-02-09</td>
+<td>17.3.5</td>
+<td>Juan A. Suarez Romero</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-02-23</td>
+<td>17.3.6</td>
+<td>Juan A. Suarez Romero</td>
+<td>Final planned release for the 17.3 series</td>
+</tr>
+<tr>
+<td rowspan="7">18.0</td>
+<td>2018-01-19</td>
+<td>18.0.0-rc1</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-01-26</td>
+<td>18.0.0-rc2</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-02-02</td>
+<td>18.0.0-rc3</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-02-09</td>
+<td>18.0.0-rc4</td>
+<td>Emil Velikov</td>
+<td>May be promoted to 18.0.0 final</td>
+</tr>
+<tr>
+<td>2018-02-23</td>
+<td>18.0.1</td>
+<td>Andres Gomez</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-03-09</td>
 <td>18.0.2</td>
-<td>Juan A. Suarez Romero</td>
+<td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-05-04</td>
+<td>2018-03-23</td>
 <td>18.0.3</td>
-<td>Juan A. Suarez Romero</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-05-18</td>
-<td>18.0.4</td>
-<td>Juan A. Suarez Romero</td>
-<td>Last planned 18.0.x release</td>
-</tr>
-<tr>
-<td rowspan="8">18.1</td>
-<td>2018-04-20</td>
-<td>18.1.0rc1</td>
-<td>Dylan Baker</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-04-27</td>
-<td>18.1.0rc2</td>
-<td>Dylan Baker</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-05-04</td>
-<td>18.1.0rc3</td>
-<td>Dylan Baker</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-05-11</td>
-<td>18.1.0rc4</td>
-<td>Dylan Baker</td>
-<td>Last planned RC/Final release</td>
-</tr>
-<tr>
-<td>TBD</td>
-<td>18.1.1</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>TBD</td>
-<td>18.1.2</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>TBD</td>
-<td>18.1.3</td>
-<td>Emil Velikov</td>
-<td></td>
-</tr>
-<tr>
-<td>TBD</td>
-<td>18.1.4</td>
-<td>Emil Velikov</td>
-<td>Last planned RC/Final release</td>
-</tr>
-<tr>
-<td rowspan="4">18.2</td>
-<td>2018-07-20</td>
-<td>18.2.0rc1</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
-<tr>
-<td>2018-07-27</td>
-<td>18.2.0rc2</td>
-<td>Andres Gomez</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-08-03</td>
-<td>18.2.0rc3</td>
-<td>Andres Gomez</td>
-<td></td>
-</tr>
-<tr>
-<td>2018-08-10</td>
-<td>18.2.0rc4</td>
-<td>Andres Gomez</td>
-<td>Last planned RC/Final release</td>
-</tr>
 </table>
 
 </div>

docs/relnotes.html

@@ -21,15 +21,7 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>
 
 <ul>
-<li><a href="relnotes/18.0.1.html">18.0.1 release notes</a>
-<li><a href="relnotes/17.3.9.html">17.3.9 release notes</a>
-<li><a href="relnotes/17.3.8.html">17.3.8 release notes</a>
-<li><a href="relnotes/18.0.0.html">18.0.0 release notes</a>
-<li><a href="relnotes/17.3.7.html">17.3.7 release notes</a>
-<li><a href="relnotes/17.3.6.html">17.3.6 release notes</a>
-<li><a href="relnotes/17.3.5.html">17.3.5 release notes</a>
-<li><a href="relnotes/17.3.4.html">17.3.4 release notes</a>
-<li><a href="relnotes/17.3.3.html">17.3.3 release notes</a>
+<li><a href="relnotes/17.3.2.html">17.3.3 release notes</a>
 <li><a href="relnotes/17.3.2.html">17.3.2 release notes</a>
 <li><a href="relnotes/17.2.8.html">17.2.8 release notes</a>
 <li><a href="relnotes/17.3.1.html">17.3.1 release notes</a>

docs/relnotes/17.3.4.html

@@ -1,275 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.4 Release Notes / January 15, 2018</h1>
-
-<p>
-Mesa 17.3.4 is a bug fix release which fixes bugs found since the 17.3.3 release.
-</p>
-<p>
-Mesa 17.3.4 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-2d3a4c3cbc995b3e192361dce710d8c749e046e7575aa1b7d8fc9e6b4df28f84  mesa-17.3.4.tar.gz
-71f995e233bc5df1a0dd46c980d1720106e7f82f02d61c1ca50854b5e02590d0  mesa-17.3.4.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=90311">Bug 90311</a> - Fail to build libglx with clang at linking stage</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101442">Bug 101442</a> - Piglit shaders&#64;ssa&#64;fs-if-def-else-break fails with sb but passes with R600_DEBUG=nosb</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102435">Bug 102435</a> - [skl,kbl] [drm] GPU HANG: ecode 9:0:0x86df7cf9, in csgo_linux64 [4947], reason: Hang on rcs, action: reset</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103006">Bug 103006</a> - [OpenGL CTS] [HSW] KHR-GL45.vertex_attrib_binding.basic-inputL-case1</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103626">Bug 103626</a> - [SNB] ES3-CTS.functional.shaders.precision</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104163">Bug 104163</a> - [GEN9+] 2-3% perf drop in GfxBench Manhattan 3.1 from &quot;i965: Disable regular fast-clears (CCS_D) on gen9+&quot;</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104383">Bug 104383</a> - [KBL] Intel GPU hang with firefox</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104411">Bug 104411</a> - [CCS] lemonbar-xft GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104487">Bug 104487</a> - [KBL] portal2_linux GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104711">Bug 104711</a> - [skl CCS] Oxenfree (unity engine game) hangs GPU</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104741">Bug 104741</a> - Graphic corruption for Android apps Telegram and KineMaster</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104745">Bug 104745</a> - HEVC VDPAU decoding broken on RX 460 with UVD Firmware v1.130</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104818">Bug 104818</a> - mesa fails to build on ia64</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Gomez (1):</p>
-<ul>
-  <li>i965: perform 2 uploads with dual slot *64*PASSTHRU formats on gen&lt;8</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (10):</p>
-<ul>
-  <li>radv: Fix ordering issue in meta memory allocation failure path.</li>
-  <li>radv: Fix memory allocation failure path in compute resolve init.</li>
-  <li>radv: Fix freeing meta state if the device pipeline cache fails to allocate.</li>
-  <li>radv: Fix fragment resolve init memory allocation failure paths.</li>
-  <li>radv: Fix bufimage failure deallocation.</li>
-  <li>radv: Init variant entry with memset.</li>
-  <li>radv: Don't allow 3d or 1d depth/stencil textures.</li>
-  <li>ac/nir: Use instance_rate_inputs per attribute, not per variable.</li>
-  <li>ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.</li>
-  <li>ac/nir: Fix vector extraction if source vector has &gt;4 elements.</li>
-</ul>
-
-<p>Boyuan Zhang (2):</p>
-<ul>
-  <li>radeon/vcn: add and manage render picture list</li>
-  <li>radeon/uvd: add and manage render picture list</li>
-</ul>
-
-<p>Chuck Atkins (1):</p>
-<ul>
-  <li>configure.ac: add missing llvm dependencies to .pc files</li>
-</ul>
-
-<p>Dave Airlie (10):</p>
-<ul>
-  <li>r600/sb: fix a bug emitting ar load from a constant.</li>
-  <li>ac/nir: account for view index in the user sgpr allocation.</li>
-  <li>radv: add fs_key meta format support to resolve passes.</li>
-  <li>radv: don't use hw resolve for integer image formats</li>
-  <li>radv: don't use hw resolves for r16g16 norm formats.</li>
-  <li>radv: move spi_baryc_cntl to pipeline</li>
-  <li>r600/sb: insert the else clause when we might depart from a loop</li>
-  <li>radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)</li>
-  <li>radv/gfx9: fix block compression texture views. (v2)</li>
-  <li>virgl: also remove dimension on indirect.</li>
-</ul>
-
-<p>Eleni Maria Stea (1):</p>
-<ul>
-  <li>mesa: Fix function pointers initialization in status tracker</li>
-</ul>
-
-<p>Emil Velikov (18):</p>
-<ul>
-  <li>cherry-ignore: i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext</li>
-  <li>cherry-ignore: swr: refactor swr_create_screen to allow for proper cleanup on error</li>
-  <li>cherry-ignore: anv: add explicit 18.0 only nominations</li>
-  <li>cherry-ignore: radv: fix sample_mask_in loading. (v3.1)</li>
-  <li>cherry-ignore: meson: multiple fixes</li>
-  <li>cherry-ignore: swr/rast: support llvm 3.9 type declarations</li>
-  <li>Revert "cherry-ignore: intel/fs: Use the original destination region for int MUL lowering"</li>
-  <li>cherry-ignore: ac/nir: set amdgpu.uniform and invariant.load for UBOs</li>
-  <li>cherry-ignore: add gen10 fixes</li>
-  <li>cherry-ignore: add r600/amdgpu 18.0 nominations</li>
-  <li>cherry-ignore: add i965 shader cache fixes</li>
-  <li>cherry-ignore: nir: mark unused space in packed_tex_data</li>
-  <li>radv: Stop advertising VK_KHX_multiview</li>
-  <li>cherry-ignore: radv: Don't expose VK_KHX_multiview on android.</li>
-  <li>configure.ac: correct driglx-direct help text</li>
-  <li>cherry-ignore: add meson fix</li>
-  <li>cherry-ignore: add a few more meson fixes</li>
-  <li>Update version to 17.3.4</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>radeon: remove left over dead code</li>
-</ul>
-
-<p>Gert Wollny (1):</p>
-<ul>
-  <li>r600/shader: Initialize max_driver_temp_used correctly for the first time</li>
-</ul>
-
-<p>Grazvydas Ignotas (2):</p>
-<ul>
-  <li>st/va: release held locks in error paths</li>
-  <li>st/vdpau: release held lock in error path</li>
-</ul>
-
-<p>Igor Gnatenko (1):</p>
-<ul>
-  <li>link mesautil with pthreads</li>
-</ul>
-
-<p>Indrajit Das (4):</p>
-<ul>
-  <li>st/omx_bellagio: Update default intra matrix per MPEG2 spec</li>
-  <li>radeon/uvd: update quantiser matrices only when requested</li>
-  <li>radeon/vcn: update quantiser matrices only when requested</li>
-  <li>st/va: clear pointers for mpeg2 quantiser matrices</li>
-</ul>
-
-<p>Jason Ekstrand (19):</p>
-<ul>
-  <li>i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer</li>
-  <li>i965: Add more precise cache tracking helpers</li>
-  <li>i965/blorp: Add more destination flushing</li>
-  <li>i965: Track the depth and render caches separately</li>
-  <li>i965: Track format and aux usage in the render cache</li>
-  <li>Re-enable regular fast-clears (CCS_D) on gen9+</li>
-  <li>i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage</li>
-  <li>i965/miptree: Add an explicit tiling parameter to create_for_bo</li>
-  <li>i965/miptree: Use the tiling from the modifier instead of the BO</li>
-  <li>i965/bufmgr: Add a create_from_prime_tiled function</li>
-  <li>i965: Set tiling on BOs imported with modifiers</li>
-  <li>i965/miptree: Take an aux_usage in prepare/finish_render</li>
-  <li>i965/miptree: Add an aux_disabled parameter to render_aux_usage</li>
-  <li>i965/surface_state: Drop brw_aux_surface_disabled</li>
-  <li>intel/fs: Use the original destination region for int MUL lowering</li>
-  <li>anv/pipeline: Don't look at blend state unless we have an attachment</li>
-  <li>anv/cmd_buffer: Re-emit the pipeline at every subpass</li>
-  <li>anv: Stop advertising VK_KHX_multiview</li>
-  <li>i965: Call prepare_external after implicit window-system MSAA resolves</li>
-</ul>
-
-<p>Jon Turney (3):</p>
-<ul>
-  <li>configure: Default to gbm=no on osx</li>
-  <li>glx/apple: include util/debug.h for env_var_as_boolean prototype</li>
-  <li>glx/apple: locate dispatch table functions to wrap by name</li>
-</ul>
-
-<p>José Fonseca (1):</p>
-<ul>
-  <li>svga: Prevent use after free.</li>
-</ul>
-
-<p>Juan A. Suarez Romero (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.3</li>
-</ul>
-
-<p>Kenneth Graunke (2):</p>
-<ul>
-  <li>i965: Bind null render targets for shadow sampling + color.</li>
-  <li>i965: Bump official kernel requirement to Linux v3.9.</li>
-</ul>
-
-<p>Lucas Stach (2):</p>
-<ul>
-  <li>etnaviv: dirty TS state when framebuffer has changed</li>
-  <li>renderonly: fix dumb BO allocation for non 32bpp formats</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>radeonsi: don't ignore pitch for imported textures</li>
-</ul>
-
-<p>Matthew Nicholls (2):</p>
-<ul>
-  <li>radv: restore previous stencil reference after depth-stencil clear</li>
-  <li>radv: remove predication on cache flushes</li>
-</ul>
-
-<p>Maxin B. John (1):</p>
-<ul>
-  <li>anv_icd.py: improve reproducible builds</li>
-</ul>
-
-<p>Michel Dänzer (1):</p>
-<ul>
-  <li>winsys/radeon: Compute is_displayable in surf_drm_to_winsys</li>
-</ul>
-
-<p>Roland Scheidegger (1):</p>
-<ul>
-  <li>r600: don't do stack workarounds for hemlock</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: create pipeline layout objects for all meta operations</li>
-</ul>
-
-<p>Samuel Thibault (1):</p>
-<ul>
-  <li>glx: fix non-dri build</li>
-</ul>
-
-<p>Timothy Arceri (2):</p>
-<ul>
-  <li>ac: fix buffer overflow bug in 64bit SSBO loads</li>
-  <li>ac: fix visit_ssa_undef() for doubles</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.3.5.html

@@ -1,66 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.5 Release Notes / February 19, 2018</h1>
-
-<p>
-Mesa 17.3.5 is a bug fix release which fixes bugs found since the 17.3.4 release.
-</p>
-<p>
-Mesa 17.3.5 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-bc1ee20366aae2affc37c89228f871f438136f70252005e9f842169bde976788  mesa-17.3.5.tar.gz
-eb9228fc8aaa71e0205c1481c5b157752ebaec9b646b030d27478e25a6d7936a  mesa-17.3.5.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Emil Velikov (2):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.4</li>
-  <li>Update version to 17.3.5</li>
-</ul>
-
-<p>James Legg (1):</p>
-<ul>
-  <li>ac/nir: Fix conflict resolution typo in handle_vs_input_decl</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/17.3.6.html

@@ -1,85 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.6 Release Notes / February 27, 2018</h1>
-
-<p>
-Mesa 17.3.6 is a bug fix release which fixes bugs found since the 17.3.5 release.
-</p>
-<p>
-Mesa 17.3.6 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-d5e10ea3f0d11b06d2b0b235bba372a04278c39bc0e712090bda1f61842db188  mesa-17.3.6.tar.gz
-e5915680d44ac9d05defdec529db7459ac9edd441c9845266eff2e2d3e57fbf8  mesa-17.3.6.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104383">Bug 104383</a> - [KBL] Intel GPU hang with firefox</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104411">Bug 104411</a> - [CCS] lemonbar-xft GPU hang</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104546">Bug 104546</a> - Crash happens when running compute pipeline after calling glxMakeCurrent two times</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Emil Velikov (2):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.5</li>
-  <li>Update version to 17.3.6</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>i965/draw: Do resolves properly for textures used by TXF</li>
-  <li>i965: Replace draw_aux_buffer_disabled with draw_aux_usage</li>
-  <li>i965/draw: Set NEW_AUX_STATE when draw aux changes</li>
-  <li>i965: Stop disabling aux during texture preparation</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Don't disable CCS for RT dependencies when dispatching compute.</li>
-</ul>
-
-<p>Topi Pohjolainen (1):</p>
-<ul>
-  <li>i965: Don't try to disable render aux buffers for compute</li>
-</ul>
-
-</div>
-</body>
-</html>
-

docs/relnotes/17.3.7.html

@@ -1,312 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.7 Release Notes / March 21, 2018</h1>
-
-<p>
-Mesa 17.3.7 is a bug fix release which fixes bugs found since the 17.3.7 release.
-</p>
-<p>
-Mesa 17.3.7 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-f08de6d0ccb3dbca04b44790d85c3ff9e7b1cc4189d1b7c7167e5ba7d98736c0  mesa-17.3.7.tar.gz
-0595904a8fba65a8fe853a84ad3c940205503b94af41e8ceed245fada777ac1e  mesa-17.3.7.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103007">Bug 103007</a> - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103988">Bug 103988</a> - Intermittent piglit failures with shader cache enabled</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104302">Bug 104302</a> - Wolfenstein 2 (2017) under wine graphical artifacting on RADV</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104381">Bug 104381</a> - swr fails to build since llvm-svn r321257</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104625">Bug 104625</a> - semicolon after if</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104642">Bug 104642</a> - Android: NULL pointer dereference with i965 mesa-dev, seems build_id_length related</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104654">Bug 104654</a> - r600/sb: Alien Isolation GPU lock</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104905">Bug 104905</a> - SpvOpFOrdEqual doesn't return correct results for NaNs</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104915">Bug 104915</a> - Indexed SHADING_LANGUAGE_VERSION query not supported</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104923">Bug 104923</a> - anv: Dota2 rendering corruption</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105013">Bug 105013</a> - [regression] GLX+VA-API+clutter-gst video playback is corrupt with Mesa 17.3 (but is fine with 17.2)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105029">Bug 105029</a> - simdlib_512_avx512.inl:371:57: error: could not convert ‘_mm512_mask_blend_epi32((__mmask16)(ImmT), a, b)’ from ‘__m512i’ {aka ‘__vector(8) long long int’} to ‘SIMDImpl::SIMD512Impl::Float’</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105098">Bug 105098</a> - [RADV] GPU freeze with simple Vulkan App</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105103">Bug 105103</a> - Wayland master causes Mesa to fail to compile</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105224">Bug 105224</a> - Webgl Pointclouds flickers</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105255">Bug 105255</a> - Waiting for fences without waitAll is not implemented</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105271">Bug 105271</a> - WebGL2 shader crashes i965_dri.so 17.3.3</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105436">Bug 105436</a> - Blinking textures in UT2004 [bisected]</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Smith (1):</p>
-<ul>
-  <li>radv: Fix CmdCopyImage between uncompressed and compressed images</li>
-</ul>
-
-<p>Andriy Khulap (1):</p>
-<ul>
-  <li>i965: Fix RELOC_WRITE typo in brw_store_data_imm64()</li>
-</ul>
-
-<p>Anuj Phogat (1):</p>
-<ul>
-  <li>isl: Don't use surface format R32_FLOAT for typed atomic integer operations</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (6):</p>
-<ul>
-  <li>radv: Always lower indirect derefs after nir_lower_global_vars_to_local.</li>
-  <li>radeonsi: Export signalled sync file instead of -1.</li>
-  <li>radv: Implement WaitForFences with !waitAll.</li>
-  <li>radv: Implement waiting on non-submitted fences.</li>
-  <li>radv: Fix copying from 3D images starting at non-zero depth.</li>
-  <li>radv: Increase the number of dynamic uniform buffers.</li>
-</ul>
-
-<p>Brian Paul (1):</p>
-<ul>
-  <li>mesa: add missing switch case for EXTRA_VERSION_40 in check_extra()</li>
-</ul>
-
-<p>Chuck Atkins (1):</p>
-<ul>
-  <li>glx: Properly handle cases where screen creation fails</li>
-</ul>
-
-<p>Daniel Stone (3):</p>
-<ul>
-  <li>i965: Fix bugs in intel_from_planar</li>
-  <li>egl/wayland: Fix ARGB/XRGB transposition in config map</li>
-  <li>egl/wayland: Always use in-tree wayland-egl-backend.h</li>
-</ul>
-
-<p>Dave Airlie (9):</p>
-<ul>
-  <li>r600: fix cubemap arrays</li>
-  <li>r600/sb/cayman: fix indirect ubo access on cayman</li>
-  <li>r600: fix xfb stream check.</li>
-  <li>ac/nir: to integer the args to bcsel.</li>
-  <li>r600/cayman: fix fragcood loading recip generation.</li>
-  <li>radv: don't support tc-compat on multisample d32s8 at all.</li>
-  <li>virgl: remap query types to hw support.</li>
-  <li>ac/nir: don't apply slice rounding on txf_ms</li>
-  <li>r600: implement callstack workaround for evergreen.</li>
-</ul>
-
-<p>Dylan Baker (2):</p>
-<ul>
-  <li>glapi/check_table: Remove 'extern "C"' block</li>
-  <li>glapi: remove APPLE extensions from test</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.6</li>
-</ul>
-
-<p>Eric Anholt (4):</p>
-<ul>
-  <li>mesa: Drop incorrect A4B4G4R4 _mesa_format_matches_format_and_type() cases.</li>
-  <li>ac/nir: Fix compiler warning about uninitialized dw_addr.</li>
-  <li>glsl/tests: Fix strict aliasing warning about int64/double.</li>
-  <li>glsl/tests: Fix a compiler warning about signed/unsigned loop comparison.</li>
-</ul>
-
-<p>Francisco Jerez (1):</p>
-<ul>
-  <li>i965: Fix KHR_blend_equation_advanced with some render targets.</li>
-</ul>
-
-<p>Frank Binns (1):</p>
-<ul>
-  <li>egl/dri2: fix segfault when display initialisation fails</li>
-</ul>
-
-<p>George Kyriazis (1):</p>
-<ul>
-  <li>swr/rast: blend_epi32() should return Integer, not Float</li>
-</ul>
-
-<p>Gert Wollny (1):</p>
-<ul>
-  <li>r600: Take ALU_EXTENDED into account when evaluating jump offsets</li>
-</ul>
-
-<p>Gurchetan Singh (1):</p>
-<ul>
-  <li>mesa: don't clamp just based on ARB_viewport_array extension</li>
-</ul>
-
-<p>Iago Toral Quiroga (2):</p>
-<ul>
-  <li>i965/sbe: fix number of inputs for active components</li>
-  <li>i965/vec4: use a temp register to compute offsets for pull loads</li>
-</ul>
-
-<p>James Legg (1):</p>
-<ul>
-  <li>radv: Really use correct HTILE expanded words.</li>
-</ul>
-
-<p>Jason Ekstrand (3):</p>
-<ul>
-  <li>intel/isl: Add an isl_color_value_is_zero helper</li>
-  <li>vulkan/wsi/x11: Set OUT_OF_DATE if wait_for_special_event fails</li>
-  <li>intel/fs: Set up sampler message headers in the visitor on gen7+</li>
-</ul>
-
-<p>Jonathan Gray (1):</p>
-<ul>
-  <li>configure.ac: pthread-stubs not present on OpenBSD</li>
-</ul>
-
-<p>Jordan Justen (3):</p>
-<ul>
-  <li>i965: Create new program cache bo when clearing the program cache</li>
-  <li>program: Don't reset SamplersValidated when restoring from shader cache</li>
-  <li>intel/vulkan: Hard code CS scratch_ids_per_subslice for Cherryview</li>
-</ul>
-
-<p>Juan A. Suarez Romero (14):</p>
-<ul>
-  <li>cherry-ignore: Explicit 18.0 only nominations</li>
-  <li>cherry-ignore: r600/compute: only mark buffer/image state dirty for fragment shaders</li>
-  <li>cherry-ignore: anv: Move setting current_pipeline to cmd_state_init</li>
-  <li>cherry-ignore: anv: Be more careful about fast-clear colors</li>
-  <li>cherry-ignore: Add patches that has a specific version for 17.3</li>
-  <li>cherry-ignore: r600: Take ALU_EXTENDED into account when evaluating jump offsets</li>
-  <li>cherry-ignore: intel/compiler: Memory fence commit must always be enabled for gen10+</li>
-  <li>cherry-ignore: i965: Avoid problems from referencing orphaned BOs after growing.</li>
-  <li>cherry-ignore: include all Meson related fixes</li>
-  <li>cherry-ignore: ac/shader: fix vertex input with components.</li>
-  <li>cherry-ignore: i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.</li>
-  <li>cherry-ignore: anv/image: Separate modifiers from legacy scanout</li>
-  <li>cherry-ignore: glsl: Fix memory leak with known glsl_type instances</li>
-  <li>Update version to 17.3.7</li>
-</ul>
-
-<p>Karol Herbst (1):</p>
-<ul>
-  <li>nvir/nvc0: fix legalizing of ld unlock c0[0x10000]</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Emit CS stall before MEDIA_VFE_STATE.</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>i965: perf: ensure reading config IDs from sysfs isn't interrupted</li>
-</ul>
-
-<p>Marek Olšák (2):</p>
-<ul>
-  <li>radeonsi: align command buffer starting address to fix some Raven hangs</li>
-  <li>configure.ac: blacklist libdrm 2.4.90</li>
-</ul>
-
-<p>Michal Navratil (1):</p>
-<ul>
-  <li>winsys/amdgpu: allow non page-aligned size bo creation from pointer</li>
-</ul>
-
-<p>Samuel Iglesias Gonsálvez (1):</p>
-<ul>
-  <li>glsl/linker: fix bug when checking precision qualifier</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>ac/nir: use ordered float comparisons except for not equal</li>
-  <li>Revert "mesa: do not trigger _NEW_TEXTURE_STATE in glActiveTexture()"</li>
-</ul>
-
-<p>Stephan Gerhold (1):</p>
-<ul>
-  <li>util/build-id: Fix address comparison for binaries with LOAD vaddr &gt; 0</li>
-</ul>
-
-<p>Thomas Hellstrom (2):</p>
-<ul>
-  <li>svga: Fix a leftover debug hack</li>
-  <li>loader_dri3/glx/egl: Reinstate the loader_dri3_vtable get_dri_screen callback</li>
-</ul>
-
-<p>Tim Rowley (1):</p>
-<ul>
-  <li>swr/rast: fix MemoryBuffer build break for llvm-6</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>nir: fix interger divide by zero crash during constant folding</li>
-</ul>
-
-<p>Tobias Droste (1):</p>
-<ul>
-  <li>gallivm: Use new LLVM fast-math-flags API</li>
-</ul>
-
-<p>Vadym Shovkoplias (1):</p>
-<ul>
-  <li>mesa: add glsl version query (v4)</li>
-</ul>
-
-<p>Vinson Lee (1):</p>
-<ul>
-  <li>swr/rast: Fix macOS macro.</li>
-</ul>
-
-
-</div>
-</body>
-</html>
-

docs/relnotes/17.3.8.html

@@ -1,147 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.8 Release Notes / April 03, 2018</h1>
-
-<p>
-Mesa 17.3.8 is a bug fix release which fixes bugs found since the 17.3.7 release.
-</p>
-<p>
-Mesa 17.3.8 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-175d2ca9be2af3a8db6cd603986096d75da70f59699528d7b6675d542a305e23  mesa-17.3.8.tar.gz
-8f9d9bf281c48e4a8f5228816577263b4c655248dc7666e75034ab422951a6b1  mesa-17.3.8.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102542">Bug 102542</a> - mesa-17.2.0/src/gallium/state_trackers/nine/nine_ff.c:1938: bad assignment ?</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103746">Bug 103746</a> - [BDW BSW SKL KBL] dEQP-GLES31.functional.copy_image regressions</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104636">Bug 104636</a> - [BSW/HD400] Aztec Ruins GL version GPU hangs</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105290">Bug 105290</a> - [BSW/HD400] SynMark OglCSDof GPU hangs when shaders come from cache</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105464">Bug 105464</a> - Reading per-patch outputs in Tessellation Control Shader returns undefined values</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105670">Bug 105670</a> - [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105704">Bug 105704</a> - compiler assertion hit</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105717">Bug 105717</a> - [bisected] Mesa build tests fails: BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Axel Davy (3):</p>
-<ul>
-  <li>st/nine: Fix bad tracking of vs textures for NINESBT_ALL</li>
-  <li>st/nine: Fixes warning about implicit conversion</li>
-  <li>st/nine: Fix non inversible matrix check</li>
-</ul>
-
-<p>Caio Marcelo de Oliveira Filho (1):</p>
-<ul>
-  <li>anv/pipeline: fail if TCS/TES compile fail</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>radv: get correct offset into LDS for indexed vars.</li>
-</ul>
-
-<p>Derek Foreman (1):</p>
-<ul>
-  <li>egl/wayland: Make swrast display_sync the correct queue</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>meson/configure: detect endian.h instead of trying to guess when it's available</li>
-</ul>
-
-<p>Ian Romanick (2):</p>
-<ul>
-  <li>mesa: Don't write to user buffer in glGetTexParameterIuiv on error</li>
-  <li>i965/vec4: Fix null destination register in 3-source instructions</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965: Emit texture cache invalidates around blorp_copy</li>
-</ul>
-
-<p>Jordan Justen (2):</p>
-<ul>
-  <li>i965: Calculate thread_count in brw_alloc_stage_scratch</li>
-  <li>i965: Hard code CS scratch_ids_per_subslice for Cherryview</li>
-</ul>
-
-<p>Juan A. Suarez Romero (6):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.7</li>
-  <li>cherry-ignore: ac/nir: pass the nir variable through tcs loading.</li>
-  <li>cherry-ignore: radv: handle exporting view index to fragment shader. (v1.1)</li>
-  <li>cherry-ignore: omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}</li>
-  <li>cherry-ignore: docs: fix 18.0 release note version</li>
-  <li>Update version to 17.3.8</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/vce: move feedback command inside of destroy function</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>st/dri: fix OpenGL-OpenCL interop for GL_TEXTURE_BUFFER</li>
-</ul>
-
-<p>Rob Clark (1):</p>
-<ul>
-  <li>nir: fix per_vertex_output intrinsic</li>
-</ul>
-
-<p>Timothy Arceri (2):</p>
-<ul>
-  <li>glsl: fix infinite loop caused by bug in loop unrolling pass</li>
-  <li>nir: fix crash in loop unroll corner case</li>
-</ul>
-
-
-</div>
-</body>
-</html>
-

docs/relnotes/17.3.9.html

@@ -1,162 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 17.3.9 Release Notes / April 18, 2018</h1>
-
-<p>
-Mesa 17.3.9 is a bug fix release which fixes bugs found since the 17.3.8 release.
-</p>
-<p>
-Mesa 17.3.9 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-4d625f65a1ff4cd8cfeb39e38f047507c6dea047502a0d53113c96f54588f340  mesa-17.3.9.tar.gz
-c5beb5fc05f0e0c294fefe1a393ee118cb67e27a4dca417d77c297f7d4b6e479  mesa-17.3.9.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98281">Bug 98281</a> - 'message's in ctx-&gt;Debug.LogMessages[] seem to leak.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101408">Bug 101408</a> - [Gen8+] Xonotic fails to render one of the weapons</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102342">Bug 102342</a> - mesa-17.1.7/src/gallium/auxiliary/pipebuffer/pb_cache.c:169]: (style) Suspicious condition</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105317">Bug 105317</a> - The GPU Vega 56 was hang while try to pass #GraphicsFuzz shader15 test</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105440">Bug 105440</a> - GEN7: rendering issue on citra</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105442">Bug 105442</a> - Hang when running nine ff lighting shader with radeonsi</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105994">Bug 105994</a> - surface state leak when creating and destroying image views with aspectMask depth and stencil</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Gomez (2):</p>
-<ul>
-  <li>dri_util: when overriding, always reset the core version</li>
-  <li>mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage</li>
-</ul>
-
-<p>Axel Davy (2):</p>
-<ul>
-  <li>st/nine: Declare lighting consts for ff shaders</li>
-  <li>st/nine: Do not use scratch for face register</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (1):</p>
-<ul>
-  <li>ac/nir: Add workaround for GFX9 buffer views.</li>
-</ul>
-
-<p>Daniel Stone (1):</p>
-<ul>
-  <li>st/dri: Initialise modifier to INVALID for DRI2</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>glsl: remove unreachable assert()</li>
-</ul>
-
-<p>Eric Engestrom (1):</p>
-<ul>
-  <li>gbm: remove never-implemented function</li>
-</ul>
-
-<p>Henri Verbeet (1):</p>
-<ul>
-  <li>mesa: Inherit texture view multi-sample information from the original texture images.</li>
-</ul>
-
-<p>Iago Toral Quiroga (1):</p>
-<ul>
-  <li>compiler/spirv: set is_shadow for depth comparitor sampling opcodes</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>nir/vars_to_ssa: Remove copies from the correct set</li>
-  <li>nir/lower_indirect_derefs: Support interp_var_at intrinsics</li>
-  <li>intel/vec4: Set channel_sizes for MOV_INDIRECT sources</li>
-  <li>nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination</li>
-</ul>
-
-<p>Juan A. Suarez Romero (3):</p>
-<ul>
-  <li>docs: add sha256 checksums for 17.3.8</li>
-  <li>cherry-ignore: Explicit 18.0 only nominations</li>
-  <li>Update version to 17.3.9</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>anv: fix number of planes for depth &amp; stencil</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: fix picking the method for resolve subpass</li>
-</ul>
-
-<p>Sergii Romantsov (1):</p>
-<ul>
-  <li>i965: Extend the negative 32-bit deltas to 64-bits</li>
-</ul>
-
-<p>Timothy Arceri (6):</p>
-<ul>
-  <li>gallium/pipebuffer: fix parenthesis location</li>
-  <li>glsl: always call do_lower_jumps() after loop unrolling</li>
-  <li>ac: add if/loop build helpers</li>
-  <li>radeonsi: make use of if/loop build helpers in ac</li>
-  <li>ac: make use of if/loop build helpers</li>
-  <li>mesa: free debug messages when destroying the debug state</li>
-</ul>
-
-<p>Xiong, James (1):</p>
-<ul>
-  <li>i965: return the fourcc saved in __DRIimage when possible</li>
-</ul>
-
-
-</div>
-</body>
-</html>
-

docs/relnotes/18.0.0.html

@@ -14,15 +14,15 @@
 <iframe src="../contents.html"></iframe>
 <div class="content">
 
-<h1>Mesa 18.0.0 Release Notes / March 27 2018</h1>
+<h1>Mesa 17.4.0 Release Notes / March 27 2018</h1>
 
 <p>
-Mesa 18.0.0 is a new development release.
+Mesa 17.4.0 is a new development release.
 People who are concerned with stability and reliability should stick
-with a previous release or wait for Mesa 18.0.1.
+with a previous release or wait for Mesa 17.4.1.
 </p>
 <p>
-Mesa 18.0.0 implements the OpenGL 4.5 API, but the version reported by
+Mesa 17.4.0 implements the OpenGL 4.5 API, but the version reported by
 glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
 glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
 Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
@@ -33,8 +33,7 @@ because compatibility contexts are not supported.
 
 <h2>SHA256 checksums</h2>
 <pre>
-93c2d3504b2871ac2146603fb1270f341d36a39695e2950a469c5eac74f98457  mesa-18.0.0.tar.gz
-694e5c3d37717d23258c1f88bc134223c5d1aac70518d2f9134d6df3ee791eea  mesa-18.0.0.tar.xz
+TBD.
 </pre>
 
 

docs/relnotes/18.0.1.html

@@ -1,225 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.1 Release Notes / April 18, 2018</h1>
-
-<p>
-Mesa 18.0.1 is a bug fix release which fixes bugs found since the 18.0.0 release.
-</p>
-<p>
-Mesa 18.0.1 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-0c93ba892c0610f5dd87f2e2673b9445187995c395b3ddb33fd4260bfb291e89  mesa-18.0.1.tar.gz
-b2d2f5b5dbaab13e15cb0dcb5ec81887467f55ebc9625945b303a3647cd87954  mesa-18.0.1.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101408">Bug 101408</a> - [Gen8+] Xonotic fails to render one of the weapons</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102342">Bug 102342</a> - mesa-17.1.7/src/gallium/auxiliary/pipebuffer/pb_cache.c:169]: (style) Suspicious condition</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102542">Bug 102542</a> - mesa-17.2.0/src/gallium/state_trackers/nine/nine_ff.c:1938: bad assignment ?</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105317">Bug 105317</a> - The GPU Vega 56 was hang while try to pass #GraphicsFuzz shader15 test</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105440">Bug 105440</a> - GEN7: rendering issue on citra</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105442">Bug 105442</a> - Hang when running nine ff lighting shader with radeonsi</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105567">Bug 105567</a> - meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105670">Bug 105670</a> - [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105704">Bug 105704</a> - compiler assertion hit</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105717">Bug 105717</a> - [bisected] Mesa build tests fails: BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105942">Bug 105942</a> - Graphical artefacts after update to mesa 18.0.0-2</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Gomez (2):</p>
-<ul>
-  <li>dri_util: when overriding, always reset the core version</li>
-  <li>mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage</li>
-</ul>
-
-<p>Axel Davy (5):</p>
-<ul>
-  <li>st/nine: Fix bad tracking of vs textures for NINESBT_ALL</li>
-  <li>st/nine: Fixes warning about implicit conversion</li>
-  <li>st/nine: Fix non inversible matrix check</li>
-  <li>st/nine: Declare lighting consts for ff shaders</li>
-  <li>st/nine: Do not use scratch for face register</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>ac/nir: Add workaround for GFX9 buffer views.</li>
-  <li>radv: Don't set instance count using predication.</li>
-  <li>radv: Always reset draw user SGPRs after secondary command buffer.</li>
-</ul>
-
-<p>Caio Marcelo de Oliveira Filho (1):</p>
-<ul>
-  <li>anv/pipeline: fail if TCS/TES compile fail</li>
-</ul>
-
-<p>Daniel Stone (1):</p>
-<ul>
-  <li>st/dri: Initialise modifier to INVALID for DRI2</li>
-</ul>
-
-<p>Derek Foreman (1):</p>
-<ul>
-  <li>egl/wayland: Make swrast display_sync the correct queue</li>
-</ul>
-
-<p>Dylan Baker (4):</p>
-<ul>
-  <li>meson: don't use compiler.has_header</li>
-  <li>autotools: include meson_get_version</li>
-  <li>meson: Set .so version for xa like autotools does</li>
-  <li>meson: fix megadriver symlinking</li>
-</ul>
-
-<p>Emil Velikov (1):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.0</li>
-</ul>
-
-<p>Eric Engestrom (3):</p>
-<ul>
-  <li>meson/configure: detect endian.h instead of trying to guess when it's available</li>
-  <li>docs: fix 18.0 release note version</li>
-  <li>gbm: remove never-implemented function</li>
-</ul>
-
-<p>Henri Verbeet (1):</p>
-<ul>
-  <li>mesa: Inherit texture view multi-sample information from the original texture images.</li>
-</ul>
-
-<p>Iago Toral Quiroga (1):</p>
-<ul>
-  <li>compiler/spirv: set is_shadow for depth comparitor sampling opcodes</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>i965/vec4: Fix null destination register in 3-source instructions</li>
-</ul>
-
-<p>Jason Ekstrand (4):</p>
-<ul>
-  <li>nir/vars_to_ssa: Remove copies from the correct set</li>
-  <li>nir/lower_indirect_derefs: Support interp_var_at intrinsics</li>
-  <li>intel/vec4: Set channel_sizes for MOV_INDIRECT sources</li>
-  <li>nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination</li>
-</ul>
-
-<p>Juan A. Suarez Romero (5):</p>
-<ul>
-  <li>cherry-ignore anv: Be more careful about fast-clear colors</li>
-  <li>cherry-ignore: ac/shader: fix vertex input with components.</li>
-  <li>cherry-ignore: radv: handle exporting view index to fragment shader. (v1.1)</li>
-  <li>cherry-ignore: omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}</li>
-  <li>Update version to 18.0.1</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>radeon/vce: move feedback command inside of destroy function</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>i965/perf: fix config registration when uploading to kernel</li>
-</ul>
-
-<p>Marc Dietrich (1):</p>
-<ul>
-  <li>meson: fix HAVE_LLVM version define in meson build</li>
-</ul>
-
-<p>Marek Olšák (1):</p>
-<ul>
-  <li>mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override</li>
-</ul>
-
-<p>Mark Thompson (1):</p>
-<ul>
-  <li>st/va: Enable vaExportSurfaceHandle()</li>
-</ul>
-
-<p>Rob Clark (3):</p>
-<ul>
-  <li>nir: fix per_vertex_output intrinsic</li>
-  <li>freedreno/a5xx: fix page faults on last level</li>
-  <li>freedreno/a5xx: don't align height for PIPE_BUFFER</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv: fix picking the method for resolve subpass</li>
-  <li>radv: fix radv_layout_dcc_compressed() when image doesn't have DCC</li>
-</ul>
-
-<p>Sergii Romantsov (1):</p>
-<ul>
-  <li>i965: Extend the negative 32-bit deltas to 64-bits</li>
-</ul>
-
-<p>Timothy Arceri (7):</p>
-<ul>
-  <li>ac: add if/loop build helpers</li>
-  <li>radeonsi: make use of if/loop build helpers in ac</li>
-  <li>ac: make use of if/loop build helpers</li>
-  <li>glsl: fix infinite loop caused by bug in loop unrolling pass</li>
-  <li>nir: fix crash in loop unroll corner case</li>
-  <li>gallium/pipebuffer: fix parenthesis location</li>
-  <li>glsl: always call do_lower_jumps() after loop unrolling</li>
-</ul>
-
-<p>Xiong, James (1):</p>
-<ul>
-  <li>i965: return the fourcc saved in __DRIimage when possible</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.1.0.html

@@ -1,73 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.1.0 Release Notes / TBD</h1>
-
-<p>
-Mesa 18.1.0 is a new development release. People who are concerned
-with stability and reliability should stick with a previous release or
-wait for Mesa 18.1.1.
-</p>
-<p>
-Mesa 18.1.0 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-TBD.
-</pre>
-
-
-<h2>New features</h2>
-
-<p>
-Note: some of the new features are only available with certain drivers.
-</p>
-
-<ul>
-<li>OpenGL 3.1 with ARB_compatibility on nv50, nvc0, r600, radeonsi, softpipe, llvmpipe, svga</li>
-<li>GL_ARB_bindless_texture on nvc0/maxwell+</li>
-<li>GL_ARB_transform_feedback_overflow_query on nvc0</li>
-<li>GL_EXT_semaphore on radeonsi</li>
-<li>GL_EXT_semaphore_fd on radeonsi</li>
-<li>GL_EXT_shader_framebuffer_fetch on i965 on desktop GL (GLES was already supported)</li>
-<li>GL_EXT_shader_framebuffer_fetch_non_coherent on i965</li>
-<li>GL_KHR_blend_equation_advanced on radeonsi</li>
-<li>Disk shader cache support for i965 enabled by default</li>
-</ul>
-
-<h2>Bug fixes</h2>
-
-<ul>
-TBD
-</ul>
-
-<h2>Changes</h2>
-
-<ul>
-<li>Remove incomplete GLX_SGIX_swap_barrier stubs from the Xlib libGL</li>
-<li>Remove incomplete GLX_SGIX_swap_group stubs from the Xlib libGL</li>
-</ul>
-
-</div>
-</body>
-</html>

docs/submittingpatches.html

@@ -246,10 +246,6 @@ release.
 Note: resending patch identical to one on mesa-dev@ or one that differs only
 by the extra mesa-stable@ tag is <strong>not</strong> recommended.
 </p>
-<p>
-If you are not the author of the original patch, please Cc: them in your
-nomination request.
-</p>
 
 
 <h3 id="thetag">The stable tag</h3>

include/EGL/eglext.h

@@ -933,7 +933,6 @@ EGLAPI EGLSurface EGLAPIENTRY eglCreatePixmapSurfaceHI (EGLDisplay dpy, EGLConfi
 #define EGL_DRM_BUFFER_STRIDE_MESA        0x31D4
 #define EGL_DRM_BUFFER_USE_SCANOUT_MESA   0x00000001
 #define EGL_DRM_BUFFER_USE_SHARE_MESA     0x00000002
-#define EGL_DRM_BUFFER_USE_CURSOR_MESA    0x00000004
 typedef EGLImageKHR (EGLAPIENTRYP PFNEGLCREATEDRMIMAGEMESAPROC) (EGLDisplay dpy, const EGLint *attrib_list);
 typedef EGLBoolean (EGLAPIENTRYP PFNEGLEXPORTDRMIMAGEMESAPROC) (EGLDisplay dpy, EGLImageKHR image, EGLint *name, EGLint *handle, EGLint *stride);
 #ifdef EGL_EGLEXT_PROTOTYPES

include/EGL/eglmesaext.h

@@ -34,6 +34,13 @@ extern "C" {
 
 #include <EGL/eglplatform.h>
 
+#ifdef EGL_MESA_drm_image
+/* Mesa's extension to EGL_MESA_drm_image... */
+#ifndef EGL_DRM_BUFFER_USE_CURSOR_MESA
+#define EGL_DRM_BUFFER_USE_CURSOR_MESA		0x0004
+#endif
+#endif
+
 #ifndef EGL_WL_bind_wayland_display
 #define EGL_WL_bind_wayland_display 1
 

include/EGL/eglplatform.h

@@ -104,12 +104,6 @@ typedef struct ANativeWindow*           EGLNativeWindowType;
 typedef struct egl_native_pixmap_t*     EGLNativePixmapType;
 typedef void*                           EGLNativeDisplayType;
 
-#elif defined(USE_OZONE)
-
-typedef intptr_t EGLNativeDisplayType;
-typedef intptr_t EGLNativeWindowType;
-typedef intptr_t EGLNativePixmapType;
-
 #elif defined(__unix__) || defined(__APPLE__)
 
 #if defined(MESA_EGL_NO_X11_HEADERS)
@@ -130,13 +124,11 @@ typedef Window   EGLNativeWindowType;
 
 #endif /* MESA_EGL_NO_X11_HEADERS */
 
-#elif defined(__HAIKU__)
-
+#elif __HAIKU__
 #include <kernel/image.h>
-
-typedef void              *EGLNativeDisplayType;
-typedef khronos_uintptr_t  EGLNativePixmapType;
-typedef khronos_uintptr_t  EGLNativeWindowType;
+typedef void				*EGLNativeDisplayType;
+typedef khronos_uintptr_t	 EGLNativePixmapType;
+typedef khronos_uintptr_t	 EGLNativeWindowType;
 
 #else
 #error "Platform not recognized"

include/GL/gl.h

@@ -47,9 +47,9 @@
 #    define GLAPI __declspec(dllimport)
 #  else /* for use with static link lib build of Win32 edition only */
 #    define GLAPI extern
-#  endif
+#  endif /* _STATIC_MESA support */
 #  if defined(__MINGW32__) && defined(GL_NO_STDCALL) || defined(UNDER_CE)  /* The generated DLLs by MingW with STDCALL are not compatible with the ones done by Microsoft's compilers */
-#    define GLAPIENTRY
+#    define GLAPIENTRY 
 #  else
 #    define GLAPIENTRY __stdcall
 #  endif

include/GL/internal/dri_interface.h

@@ -82,7 +82,7 @@ typedef struct __DRI2flushExtensionRec	__DRI2flushExtension;
 typedef struct __DRI2throttleExtensionRec	__DRI2throttleExtension;
 typedef struct __DRI2fenceExtensionRec          __DRI2fenceExtension;
 typedef struct __DRI2interopExtensionRec	__DRI2interopExtension;
-typedef struct __DRI2blobExtensionRec           __DRI2blobExtension;
+
 
 typedef struct __DRIimageLoaderExtensionRec     __DRIimageLoaderExtension;
 typedef struct __DRIimageDriverExtensionRec     __DRIimageDriverExtension;
@@ -336,30 +336,6 @@ struct __DRI2throttleExtensionRec {
 		    enum __DRI2throttleReason reason);
 };
 
-/**
- * Extension for EGL_ANDROID_blob_cache
- */
-
-#define __DRI2_BLOB "DRI2_Blob"
-#define __DRI2_BLOB_VERSION 1
-
-typedef void
-(*__DRIblobCacheSet) (const void *key, signed long keySize,
-                      const void *value, signed long valueSize);
-
-typedef signed long
-(*__DRIblobCacheGet) (const void *key, signed long keySize,
-                      void *value, signed long valueSize);
-
-struct __DRI2blobExtensionRec {
-   __DRIextension base;
-
-   /**
-    * Set cache functions for setting and getting cache entries.
-    */
-   void (*set_cache_funcs) (__DRIscreen *screen,
-                            __DRIblobCacheSet set, __DRIblobCacheGet get);
-};
 
 /**
  * Extension for fences / synchronization objects.
@@ -1251,8 +1227,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_R16          0x100d
 #define __DRI_IMAGE_FORMAT_GR1616       0x100e
 #define __DRI_IMAGE_FORMAT_YUYV         0x100f
-#define __DRI_IMAGE_FORMAT_XBGR2101010  0x1010
-#define __DRI_IMAGE_FORMAT_ABGR2101010  0x1011
 
 #define __DRI_IMAGE_USE_SHARE		0x0001
 #define __DRI_IMAGE_USE_SCANOUT		0x0002

include/drm-uapi/README

@@ -13,9 +13,9 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
 
 The last update was done at the following kernel commit :
 
-commit 78230c46ec0a91dd4256c9e54934b3c7095a7ee3
-Merge: b65bd4031156 037f03155b7d
+commit ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
+Merge: 2c1c55cb75a9 010d118c2061
 Author: Dave Airlie <airlied@redhat.com>
-Date:   Wed Mar 21 14:07:03 2018 +1000
+Date:   Mon Dec 4 09:40:35 2017 +1000
 
-    Merge tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
+    Merge tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

include/drm-uapi/drm_fourcc.h

@@ -178,7 +178,7 @@ extern "C" {
 #define DRM_FORMAT_MOD_VENDOR_NONE    0
 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
-#define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
+#define DRM_FORMAT_MOD_VENDOR_NV      0x03
 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
@@ -188,7 +188,7 @@ extern "C" {
 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
 
 #define fourcc_mod_code(vendor, val) \
-	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
+	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
 
 /*
  * Format Modifier tokens:
@@ -338,17 +338,29 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
 
-/* NVIDIA frame buffer modifiers */
+/* NVIDIA Tegra frame buffer modifiers */
+
+/*
+ * Some modifiers take parameters, for example the number of vertical GOBs in
+ * a block. Reserve the lower 32 bits for parameters
+ */
+#define __fourcc_mod_tegra_mode_shift 32
+#define fourcc_mod_tegra_code(val, params) \
+	fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
+#define fourcc_mod_tegra_mod(m) \
+	(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
+#define fourcc_mod_tegra_param(m) \
+	(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
 
 /*
  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
  *
  * Pixels are arranged in simple tiles of 16 x 16 bytes.
  */
-#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
 
 /*
- * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
+ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
  *
  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
@@ -368,21 +380,7 @@ extern "C" {
  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
  * in full detail.
  */
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
-	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
-
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
-	fourcc_mod_code(NVIDIA, 0x10)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
-	fourcc_mod_code(NVIDIA, 0x11)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
-	fourcc_mod_code(NVIDIA, 0x12)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
-	fourcc_mod_code(NVIDIA, 0x13)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
-	fourcc_mod_code(NVIDIA, 0x14)
-#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
-	fourcc_mod_code(NVIDIA, 0x15)
+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
 
 /*
  * Broadcom VC4 "T" format

include/drm-uapi/drm_mode.h

@@ -38,18 +38,14 @@ extern "C" {
 #define DRM_DISPLAY_MODE_LEN	32
 #define DRM_PROP_NAME_LEN	32
 
-#define DRM_MODE_TYPE_BUILTIN	(1<<0) /* deprecated */
-#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */
-#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */
+#define DRM_MODE_TYPE_BUILTIN	(1<<0)
+#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
 #define DRM_MODE_TYPE_PREFERRED	(1<<3)
-#define DRM_MODE_TYPE_DEFAULT	(1<<4) /* deprecated */
+#define DRM_MODE_TYPE_DEFAULT	(1<<4)
 #define DRM_MODE_TYPE_USERDEF	(1<<5)
 #define DRM_MODE_TYPE_DRIVER	(1<<6)
 
-#define DRM_MODE_TYPE_ALL	(DRM_MODE_TYPE_PREFERRED |	\
-				 DRM_MODE_TYPE_USERDEF |	\
-				 DRM_MODE_TYPE_DRIVER)
-
 /* Video mode flags */
 /* bit compatible with the xrandr RR_ definitions (bits 0-13)
  *
@@ -70,8 +66,8 @@ extern "C" {
 #define DRM_MODE_FLAG_PCSYNC			(1<<7)
 #define DRM_MODE_FLAG_NCSYNC			(1<<8)
 #define DRM_MODE_FLAG_HSKEW			(1<<9) /* hskew provided */
-#define DRM_MODE_FLAG_BCAST			(1<<10) /* deprecated */
-#define DRM_MODE_FLAG_PIXMUX			(1<<11) /* deprecated */
+#define DRM_MODE_FLAG_BCAST			(1<<10)
+#define DRM_MODE_FLAG_PIXMUX			(1<<11)
 #define DRM_MODE_FLAG_DBLCLK			(1<<12)
 #define DRM_MODE_FLAG_CLKDIV2			(1<<13)
  /*
@@ -103,20 +99,6 @@ extern "C" {
 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
 			(DRM_MODE_PICTURE_ASPECT_16_9<<19)
 
-#define  DRM_MODE_FLAG_ALL	(DRM_MODE_FLAG_PHSYNC |		\
-				 DRM_MODE_FLAG_NHSYNC |		\
-				 DRM_MODE_FLAG_PVSYNC |		\
-				 DRM_MODE_FLAG_NVSYNC |		\
-				 DRM_MODE_FLAG_INTERLACE |	\
-				 DRM_MODE_FLAG_DBLSCAN |	\
-				 DRM_MODE_FLAG_CSYNC |		\
-				 DRM_MODE_FLAG_PCSYNC |		\
-				 DRM_MODE_FLAG_NCSYNC |		\
-				 DRM_MODE_FLAG_HSKEW |		\
-				 DRM_MODE_FLAG_DBLCLK |		\
-				 DRM_MODE_FLAG_CLKDIV2 |	\
-				 DRM_MODE_FLAG_3D_MASK)
-
 /* DPMS flags */
 /* bit compatible with the xorg definitions. */
 #define DRM_MODE_DPMS_ON	0
@@ -191,10 +173,6 @@ extern "C" {
 		DRM_MODE_REFLECT_X | \
 		DRM_MODE_REFLECT_Y)
 
-/* Content Protection Flags */
-#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED	0
-#define DRM_MODE_CONTENT_PROTECTION_DESIRED     1
-#define DRM_MODE_CONTENT_PROTECTION_ENABLED     2
 
 struct drm_mode_modeinfo {
 	__u32 clock;
@@ -363,7 +341,7 @@ struct drm_mode_get_connector {
 	__u32 pad;
 };
 
-#define DRM_MODE_PROP_PENDING	(1<<0) /* deprecated, do not use */
+#define DRM_MODE_PROP_PENDING	(1<<0)
 #define DRM_MODE_PROP_RANGE	(1<<1)
 #define DRM_MODE_PROP_IMMUTABLE	(1<<2)
 #define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
@@ -598,11 +576,8 @@ struct drm_mode_crtc_lut {
 };
 
 struct drm_color_ctm {
-	/*
-	 * Conversion matrix in S31.32 sign-magnitude
-	 * (not two's complement!) format.
-	 */
-	__u64 matrix[9];
+	/* Conversion matrix in S31.32 format. */
+	__s64 matrix[9];
 };
 
 struct drm_color_lut {

include/drm-uapi/i915_drm.h

@@ -102,46 +102,6 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
-/**
- * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
- *
- */
-
-enum drm_i915_pmu_engine_sample {
-	I915_SAMPLE_BUSY = 0,
-	I915_SAMPLE_WAIT = 1,
-	I915_SAMPLE_SEMA = 2
-};
-
-#define I915_PMU_SAMPLE_BITS (4)
-#define I915_PMU_SAMPLE_MASK (0xf)
-#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
-#define I915_PMU_CLASS_SHIFT \
-	(I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
-
-#define __I915_PMU_ENGINE(class, instance, sample) \
-	((class) << I915_PMU_CLASS_SHIFT | \
-	(instance) << I915_PMU_SAMPLE_BITS | \
-	(sample))
-
-#define I915_PMU_ENGINE_BUSY(class, instance) \
-	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
-
-#define I915_PMU_ENGINE_WAIT(class, instance) \
-	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
-
-#define I915_PMU_ENGINE_SEMA(class, instance) \
-	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
-
-#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
-
-#define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
-#define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
-#define I915_PMU_INTERRUPTS		__I915_PMU_OTHER(2)
-#define I915_PMU_RC6_RESIDENCY		__I915_PMU_OTHER(3)
-
-#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
-
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
@@ -318,7 +278,6 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_OPEN		0x36
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
-#define DRM_I915_QUERY			0x39
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -376,7 +335,6 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
-#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1360,9 +1318,7 @@ struct drm_intel_overlay_attrs {
  * active on a given plane.
  */
 
-#define I915_SET_COLORKEY_NONE		(1<<0) /* Deprecated. Instead set
-						* flags==0 to disable colorkeying.
-						*/
+#define I915_SET_COLORKEY_NONE		(1<<0) /* disable color key matching */
 #define I915_SET_COLORKEY_DESTINATION	(1<<1)
 #define I915_SET_COLORKEY_SOURCE	(1<<2)
 struct drm_intel_sprite_colorkey {
@@ -1608,115 +1564,15 @@ struct drm_i915_perf_oa_config {
 	__u32 n_flex_regs;
 
 	/*
-	 * These fields are pointers to tuples of u32 values (register address,
-	 * value). For example the expected length of the buffer pointed by
-	 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+	 * These fields are pointers to tuples of u32 values (register
+	 * address, value). For example the expected length of the buffer
+	 * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
 	 */
 	__u64 mux_regs_ptr;
 	__u64 boolean_regs_ptr;
 	__u64 flex_regs_ptr;
 };
 
-struct drm_i915_query_item {
-	__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO    1
-
-	/*
-	 * When set to zero by userspace, this is filled with the size of the
-	 * data to be written at the data_ptr pointer. The kernel sets this
-	 * value to a negative value to signal an error on a particular query
-	 * item.
-	 */
-	__s32 length;
-
-	/*
-	 * Unused for now. Must be cleared to zero.
-	 */
-	__u32 flags;
-
-	/*
-	 * Data will be written at the location pointed by data_ptr when the
-	 * value of length matches the length of the data to be written by the
-	 * kernel.
-	 */
-	__u64 data_ptr;
-};
-
-struct drm_i915_query {
-	__u32 num_items;
-
-	/*
-	 * Unused for now. Must be cleared to zero.
-	 */
-	__u32 flags;
-
-	/*
-	 * This points to an array of num_items drm_i915_query_item structures.
-	 */
-	__u64 items_ptr;
-};
-
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- *   available. The availability of slice X can be queried with the following
- *   formula :
- *
- *           (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- *   whether a subslice is available. The availability of subslice Y in slice
- *   X can be queried with the following formula :
- *
- *           (data[subslice_offset +
- *                 X * subslice_stride +
- *                 Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- *   whether an EU is available. The availability of EU Z in subslice Y in
- *   slice X can be queried with the following formula :
- *
- *           (data[eu_offset +
- *                 (X * max_subslices + Y) * eu_stride +
- *                 Z / 8] >> (Z % 8)) & 1
- */
-struct drm_i915_query_topology_info {
-	/*
-	 * Unused for now. Must be cleared to zero.
-	 */
-	__u16 flags;
-
-	__u16 max_slices;
-	__u16 max_subslices;
-	__u16 max_eus_per_subslice;
-
-	/*
-	 * Offset in data[] at which the subslice masks are stored.
-	 */
-	__u16 subslice_offset;
-
-	/*
-	 * Stride at which each of the subslice masks for each slice are
-	 * stored.
-	 */
-	__u16 subslice_stride;
-
-	/*
-	 * Offset in data[] at which the EU masks are stored.
-	 */
-	__u16 eu_offset;
-
-	/*
-	 * Stride at which each of the EU masks for each subslice are stored.
-	 */
-	__u16 eu_stride;
-
-	__u8 data[];
-};
-
 #if defined(__cplusplus)
 }
 #endif

include/drm-uapi/tegra_drm.h

@@ -1,209 +0,0 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
-
-#include "drm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
-#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
-
-struct drm_tegra_gem_create {
-	__u64 size;
-	__u32 flags;
-	__u32 handle;
-};
-
-struct drm_tegra_gem_mmap {
-	__u32 handle;
-	__u32 pad;
-	__u64 offset;
-};
-
-struct drm_tegra_syncpt_read {
-	__u32 id;
-	__u32 value;
-};
-
-struct drm_tegra_syncpt_incr {
-	__u32 id;
-	__u32 pad;
-};
-
-struct drm_tegra_syncpt_wait {
-	__u32 id;
-	__u32 thresh;
-	__u32 timeout;
-	__u32 value;
-};
-
-#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
-
-struct drm_tegra_open_channel {
-	__u32 client;
-	__u32 pad;
-	__u64 context;
-};
-
-struct drm_tegra_close_channel {
-	__u64 context;
-};
-
-struct drm_tegra_get_syncpt {
-	__u64 context;
-	__u32 index;
-	__u32 id;
-};
-
-struct drm_tegra_get_syncpt_base {
-	__u64 context;
-	__u32 syncpt;
-	__u32 id;
-};
-
-struct drm_tegra_syncpt {
-	__u32 id;
-	__u32 incrs;
-};
-
-struct drm_tegra_cmdbuf {
-	__u32 handle;
-	__u32 offset;
-	__u32 words;
-	__u32 pad;
-};
-
-struct drm_tegra_reloc {
-	struct {
-		__u32 handle;
-		__u32 offset;
-	} cmdbuf;
-	struct {
-		__u32 handle;
-		__u32 offset;
-	} target;
-	__u32 shift;
-	__u32 pad;
-};
-
-struct drm_tegra_waitchk {
-	__u32 handle;
-	__u32 offset;
-	__u32 syncpt;
-	__u32 thresh;
-};
-
-struct drm_tegra_submit {
-	__u64 context;
-	__u32 num_syncpts;
-	__u32 num_cmdbufs;
-	__u32 num_relocs;
-	__u32 num_waitchks;
-	__u32 waitchk_mask;
-	__u32 timeout;
-	__u64 syncpts;
-	__u64 cmdbufs;
-	__u64 relocs;
-	__u64 waitchks;
-	__u32 fence;		/* Return value */
-
-	__u32 reserved[5];	/* future expansion */
-};
-
-#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
-#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
-#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
-
-struct drm_tegra_gem_set_tiling {
-	/* input */
-	__u32 handle;
-	__u32 mode;
-	__u32 value;
-	__u32 pad;
-};
-
-struct drm_tegra_gem_get_tiling {
-	/* input */
-	__u32 handle;
-	/* output */
-	__u32 mode;
-	__u32 value;
-	__u32 pad;
-};
-
-#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
-#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
-
-struct drm_tegra_gem_set_flags {
-	/* input */
-	__u32 handle;
-	/* output */
-	__u32 flags;
-};
-
-struct drm_tegra_gem_get_flags {
-	/* input */
-	__u32 handle;
-	/* output */
-	__u32 flags;
-};
-
-#define DRM_TEGRA_GEM_CREATE		0x00
-#define DRM_TEGRA_GEM_MMAP		0x01
-#define DRM_TEGRA_SYNCPT_READ		0x02
-#define DRM_TEGRA_SYNCPT_INCR		0x03
-#define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
-#define DRM_TEGRA_GET_SYNCPT		0x07
-#define DRM_TEGRA_SUBMIT		0x08
-#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
-#define DRM_TEGRA_GEM_SET_TILING	0x0a
-#define DRM_TEGRA_GEM_GET_TILING	0x0b
-#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
-#define DRM_TEGRA_GEM_GET_FLAGS		0x0d
-
-#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
-#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
-#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
-#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
-#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
-#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
-#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
-#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
-#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
-#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
-#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
-#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
-#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
-#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif

include/drm-uapi/vc4_drm.h

@@ -42,9 +42,6 @@ extern "C" {
 #define DRM_VC4_GET_TILING                        0x09
 #define DRM_VC4_LABEL_BO                          0x0a
 #define DRM_VC4_GEM_MADVISE                       0x0b
-#define DRM_VC4_PERFMON_CREATE                    0x0c
-#define DRM_VC4_PERFMON_DESTROY                   0x0d
-#define DRM_VC4_PERFMON_GET_VALUES                0x0e
 
 #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
 #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -58,9 +55,6 @@ extern "C" {
 #define DRM_IOCTL_VC4_GET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
 #define DRM_IOCTL_VC4_LABEL_BO            DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
 #define DRM_IOCTL_VC4_GEM_MADVISE         DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
-#define DRM_IOCTL_VC4_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
-#define DRM_IOCTL_VC4_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
-#define DRM_IOCTL_VC4_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
 
 struct drm_vc4_submit_rcl_surface {
 	__u32 hindex; /* Handle index, or ~0 if not present. */
@@ -179,15 +173,6 @@ struct drm_vc4_submit_cl {
 	 * wait ioctl).
 	 */
 	__u64 seqno;
-
-	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
-	__u32 perfmonid;
-
-	/* Unused field to align this struct on 64 bits. Must be set to 0.
-	 * If one ever needs to add an u32 field to this struct, this field
-	 * can be used.
-	 */
-	__u32 pad2;
 };
 
 /**
@@ -323,7 +308,6 @@ struct drm_vc4_get_hang_state {
 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS	5
 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER	6
 #define DRM_VC4_PARAM_SUPPORTS_MADVISE		7
-#define DRM_VC4_PARAM_SUPPORTS_PERFMON		8
 
 struct drm_vc4_get_param {
 	__u32 param;
@@ -368,66 +352,6 @@ struct drm_vc4_gem_madvise {
 	__u32 pad;
 };
 
-enum {
-	VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
-	VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
-	VC4_PERFCNT_FEP_CLIPPED_QUADS,
-	VC4_PERFCNT_FEP_VALID_QUADS,
-	VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
-	VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
-	VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
-	VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
-	VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
-	VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
-	VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
-	VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
-	VC4_PERFCNT_PSE_PRIMS_REVERSED,
-	VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
-	VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
-	VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
-	VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
-	VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
-	VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
-	VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
-	VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
-	VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
-	VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
-	VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
-	VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
-	VC4_PERFCNT_NUM_EVENTS,
-};
-
-#define DRM_VC4_MAX_PERF_COUNTERS	16
-
-struct drm_vc4_perfmon_create {
-	__u32 id;
-	__u32 ncounters;
-	__u8 events[DRM_VC4_MAX_PERF_COUNTERS];
-};
-
-struct drm_vc4_perfmon_destroy {
-	__u32 id;
-};
-
-/*
- * Returns the values of the performance counters tracked by this
- * perfmon (as an array of ncounters u64 values).
- *
- * No implicit synchronization is performed, so the user has to
- * guarantee that any jobs using this perfmon have already been
- * completed  (probably by blocking on the seqno returned by the
- * last exec that used the perfmon).
- */
-struct drm_vc4_perfmon_get_values {
-	__u32 id;
-	__u64 values_ptr;
-};
-
 #if defined(__cplusplus)
 }
 #endif

include/meson.build

@@ -22,7 +22,6 @@ inc_drm_uapi = include_directories('drm-uapi')
 inc_vulkan = include_directories('vulkan')
 inc_d3d9 = include_directories('D3D9')
 inc_gl_internal = include_directories('GL/internal')
-inc_haikugl = include_directories('HaikuGL')
 
 if with_gles1
   install_headers(
@@ -81,13 +80,6 @@ if with_gallium_st_nine
   )
 endif
 
-if with_platform_haiku
-  install_headers(
-    'HaikuGL/GLRenderer.h', 'HaikuGL/GLView.h', 'HaikuGL/OpenGLKit.h',
-    subdir : 'opengl',
-  )
-endif
-
 # Only install the headers if we are building a stand alone implementation and
 # not an ICD enabled implementation
 if with_gallium_opencl and not with_opencl_icd

include/pci_ids/i965_pci_ids.h

@@ -165,16 +165,16 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk,     "Intel(R) UHD Graphics 605 (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
-CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
-CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
-CHIPSET(0x3E9B, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
 CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
@@ -196,11 +196,3 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
-CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
-CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
-CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
-CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
-CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
-CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
-CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
-CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")

include/pci_ids/radeonsi_pci_ids.h

@@ -216,9 +216,6 @@ CHIPSET(0x6995, POLARIS12)
 CHIPSET(0x6997, POLARIS12)
 CHIPSET(0x699F, POLARIS12)
 
-CHIPSET(0x694C, VEGAM)
-CHIPSET(0x694E, VEGAM)
-
 CHIPSET(0x6860, VEGA10)
 CHIPSET(0x6861, VEGA10)
 CHIPSET(0x6862, VEGA10)
@@ -229,10 +226,4 @@ CHIPSET(0x6868, VEGA10)
 CHIPSET(0x687F, VEGA10)
 CHIPSET(0x686C, VEGA10)
 
-CHIPSET(0x69A0, VEGA12)
-CHIPSET(0x69A1, VEGA12)
-CHIPSET(0x69A2, VEGA12)
-CHIPSET(0x69A3, VEGA12)
-CHIPSET(0x69AF, VEGA12)
-
 CHIPSET(0x15DD, RAVEN)

include/vulkan/vk_platform.h

@@ -89,4 +89,32 @@ extern "C"
 } // extern "C"
 #endif // __cplusplus
 
+// Platform-specific headers required by platform window system extensions.
+// These are enabled prior to #including "vulkan.h". The same enable then
+// controls inclusion of the extension interfaces in vulkan.h.
+
+#ifdef VK_USE_PLATFORM_ANDROID_KHR
+#include <android/native_window.h>
+#endif
+
+#ifdef VK_USE_PLATFORM_MIR_KHR
+#include <mir_toolkit/client_types.h>
+#endif
+
+#ifdef VK_USE_PLATFORM_WAYLAND_KHR
+#include <wayland-client.h>
+#endif
+
+#ifdef VK_USE_PLATFORM_WIN32_KHR
+#include <windows.h>
+#endif
+
+#ifdef VK_USE_PLATFORM_XLIB_KHR
+#include <X11/Xlib.h>
+#endif
+
+#ifdef VK_USE_PLATFORM_XCB_KHR
+#include <xcb/xcb.h>
+#endif
+
 #endif

include/vulkan/vulkan_android.h

@@ -1,126 +0,0 @@
-#ifndef VULKAN_ANDROID_H_
-#define VULKAN_ANDROID_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_android_surface 1
-struct ANativeWindow;
-
-#define VK_KHR_ANDROID_SURFACE_SPEC_VERSION 6
-#define VK_KHR_ANDROID_SURFACE_EXTENSION_NAME "VK_KHR_android_surface"
-
-typedef VkFlags VkAndroidSurfaceCreateFlagsKHR;
-
-typedef struct VkAndroidSurfaceCreateInfoKHR {
-    VkStructureType                   sType;
-    const void*                       pNext;
-    VkAndroidSurfaceCreateFlagsKHR    flags;
-    struct ANativeWindow*             window;
-} VkAndroidSurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateAndroidSurfaceKHR)(VkInstance instance, const VkAndroidSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateAndroidSurfaceKHR(
-    VkInstance                                  instance,
-    const VkAndroidSurfaceCreateInfoKHR*        pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-#endif
-
-#define VK_ANDROID_external_memory_android_hardware_buffer 1
-struct AHardwareBuffer;
-
-#define VK_ANDROID_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_SPEC_VERSION 3
-#define VK_ANDROID_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_EXTENSION_NAME "VK_ANDROID_external_memory_android_hardware_buffer"
-
-typedef struct VkAndroidHardwareBufferUsageANDROID {
-    VkStructureType    sType;
-    void*              pNext;
-    uint64_t           androidHardwareBufferUsage;
-} VkAndroidHardwareBufferUsageANDROID;
-
-typedef struct VkAndroidHardwareBufferPropertiesANDROID {
-    VkStructureType    sType;
-    void*              pNext;
-    VkDeviceSize       allocationSize;
-    uint32_t           memoryTypeBits;
-} VkAndroidHardwareBufferPropertiesANDROID;
-
-typedef struct VkAndroidHardwareBufferFormatPropertiesANDROID {
-    VkStructureType                  sType;
-    void*                            pNext;
-    VkFormat                         format;
-    uint64_t                         externalFormat;
-    VkFormatFeatureFlags             formatFeatures;
-    VkComponentMapping               samplerYcbcrConversionComponents;
-    VkSamplerYcbcrModelConversion    suggestedYcbcrModel;
-    VkSamplerYcbcrRange              suggestedYcbcrRange;
-    VkChromaLocation                 suggestedXChromaOffset;
-    VkChromaLocation                 suggestedYChromaOffset;
-} VkAndroidHardwareBufferFormatPropertiesANDROID;
-
-typedef struct VkImportAndroidHardwareBufferInfoANDROID {
-    VkStructureType            sType;
-    const void*                pNext;
-    struct AHardwareBuffer*    buffer;
-} VkImportAndroidHardwareBufferInfoANDROID;
-
-typedef struct VkMemoryGetAndroidHardwareBufferInfoANDROID {
-    VkStructureType    sType;
-    const void*        pNext;
-    VkDeviceMemory     memory;
-} VkMemoryGetAndroidHardwareBufferInfoANDROID;
-
-typedef struct VkExternalFormatANDROID {
-    VkStructureType    sType;
-    void*              pNext;
-    uint64_t           externalFormat;
-} VkExternalFormatANDROID;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetAndroidHardwareBufferPropertiesANDROID)(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties);
-typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryAndroidHardwareBufferANDROID)(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetAndroidHardwareBufferPropertiesANDROID(
-    VkDevice                                    device,
-    const struct AHardwareBuffer*               buffer,
-    VkAndroidHardwareBufferPropertiesANDROID*   pProperties);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetMemoryAndroidHardwareBufferANDROID(
-    VkDevice                                    device,
-    const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo,
-    struct AHardwareBuffer**                    pBuffer);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_ios.h

@@ -1,58 +0,0 @@
-#ifndef VULKAN_IOS_H_
-#define VULKAN_IOS_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_MVK_ios_surface 1
-#define VK_MVK_IOS_SURFACE_SPEC_VERSION   2
-#define VK_MVK_IOS_SURFACE_EXTENSION_NAME "VK_MVK_ios_surface"
-
-typedef VkFlags VkIOSSurfaceCreateFlagsMVK;
-
-typedef struct VkIOSSurfaceCreateInfoMVK {
-    VkStructureType               sType;
-    const void*                   pNext;
-    VkIOSSurfaceCreateFlagsMVK    flags;
-    const void*                   pView;
-} VkIOSSurfaceCreateInfoMVK;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateIOSSurfaceMVK)(VkInstance instance, const VkIOSSurfaceCreateInfoMVK* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateIOSSurfaceMVK(
-    VkInstance                                  instance,
-    const VkIOSSurfaceCreateInfoMVK*            pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_macos.h

@@ -1,58 +0,0 @@
-#ifndef VULKAN_MACOS_H_
-#define VULKAN_MACOS_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_MVK_macos_surface 1
-#define VK_MVK_MACOS_SURFACE_SPEC_VERSION 2
-#define VK_MVK_MACOS_SURFACE_EXTENSION_NAME "VK_MVK_macos_surface"
-
-typedef VkFlags VkMacOSSurfaceCreateFlagsMVK;
-
-typedef struct VkMacOSSurfaceCreateInfoMVK {
-    VkStructureType                 sType;
-    const void*                     pNext;
-    VkMacOSSurfaceCreateFlagsMVK    flags;
-    const void*                     pView;
-} VkMacOSSurfaceCreateInfoMVK;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateMacOSSurfaceMVK)(VkInstance instance, const VkMacOSSurfaceCreateInfoMVK* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateMacOSSurfaceMVK(
-    VkInstance                                  instance,
-    const VkMacOSSurfaceCreateInfoMVK*          pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_mir.h

@@ -1,65 +0,0 @@
-#ifndef VULKAN_MIR_H_
-#define VULKAN_MIR_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_mir_surface 1
-#define VK_KHR_MIR_SURFACE_SPEC_VERSION   4
-#define VK_KHR_MIR_SURFACE_EXTENSION_NAME "VK_KHR_mir_surface"
-
-typedef VkFlags VkMirSurfaceCreateFlagsKHR;
-
-typedef struct VkMirSurfaceCreateInfoKHR {
-    VkStructureType               sType;
-    const void*                   pNext;
-    VkMirSurfaceCreateFlagsKHR    flags;
-    MirConnection*                connection;
-    MirSurface*                   mirSurface;
-} VkMirSurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateMirSurfaceKHR)(VkInstance instance, const VkMirSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceMirPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, MirConnection* connection);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateMirSurfaceKHR(
-    VkInstance                                  instance,
-    const VkMirSurfaceCreateInfoKHR*            pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-
-VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceMirPresentationSupportKHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t                                    queueFamilyIndex,
-    MirConnection*                              connection);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_vi.h

@@ -1,58 +0,0 @@
-#ifndef VULKAN_VI_H_
-#define VULKAN_VI_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_NN_vi_surface 1
-#define VK_NN_VI_SURFACE_SPEC_VERSION     1
-#define VK_NN_VI_SURFACE_EXTENSION_NAME   "VK_NN_vi_surface"
-
-typedef VkFlags VkViSurfaceCreateFlagsNN;
-
-typedef struct VkViSurfaceCreateInfoNN {
-    VkStructureType             sType;
-    const void*                 pNext;
-    VkViSurfaceCreateFlagsNN    flags;
-    void*                       window;
-} VkViSurfaceCreateInfoNN;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateViSurfaceNN)(VkInstance instance, const VkViSurfaceCreateInfoNN* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateViSurfaceNN(
-    VkInstance                                  instance,
-    const VkViSurfaceCreateInfoNN*              pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_wayland.h

@@ -1,65 +0,0 @@
-#ifndef VULKAN_WAYLAND_H_
-#define VULKAN_WAYLAND_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_wayland_surface 1
-#define VK_KHR_WAYLAND_SURFACE_SPEC_VERSION 6
-#define VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME "VK_KHR_wayland_surface"
-
-typedef VkFlags VkWaylandSurfaceCreateFlagsKHR;
-
-typedef struct VkWaylandSurfaceCreateInfoKHR {
-    VkStructureType                   sType;
-    const void*                       pNext;
-    VkWaylandSurfaceCreateFlagsKHR    flags;
-    struct wl_display*                display;
-    struct wl_surface*                surface;
-} VkWaylandSurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateWaylandSurfaceKHR)(VkInstance instance, const VkWaylandSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceWaylandPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, struct wl_display* display);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateWaylandSurfaceKHR(
-    VkInstance                                  instance,
-    const VkWaylandSurfaceCreateInfoKHR*        pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-
-VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceWaylandPresentationSupportKHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t                                    queueFamilyIndex,
-    struct wl_display*                          display);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_win32.h

@@ -1,276 +0,0 @@
-#ifndef VULKAN_WIN32_H_
-#define VULKAN_WIN32_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_win32_surface 1
-#define VK_KHR_WIN32_SURFACE_SPEC_VERSION 6
-#define VK_KHR_WIN32_SURFACE_EXTENSION_NAME "VK_KHR_win32_surface"
-
-typedef VkFlags VkWin32SurfaceCreateFlagsKHR;
-
-typedef struct VkWin32SurfaceCreateInfoKHR {
-    VkStructureType                 sType;
-    const void*                     pNext;
-    VkWin32SurfaceCreateFlagsKHR    flags;
-    HINSTANCE                       hinstance;
-    HWND                            hwnd;
-} VkWin32SurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateWin32SurfaceKHR)(VkInstance instance, const VkWin32SurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceWin32PresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateWin32SurfaceKHR(
-    VkInstance                                  instance,
-    const VkWin32SurfaceCreateInfoKHR*          pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-
-VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceWin32PresentationSupportKHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t                                    queueFamilyIndex);
-#endif
-
-#define VK_KHR_external_memory_win32 1
-#define VK_KHR_EXTERNAL_MEMORY_WIN32_SPEC_VERSION 1
-#define VK_KHR_EXTERNAL_MEMORY_WIN32_EXTENSION_NAME "VK_KHR_external_memory_win32"
-
-typedef struct VkImportMemoryWin32HandleInfoKHR {
-    VkStructureType                       sType;
-    const void*                           pNext;
-    VkExternalMemoryHandleTypeFlagBits    handleType;
-    HANDLE                                handle;
-    LPCWSTR                               name;
-} VkImportMemoryWin32HandleInfoKHR;
-
-typedef struct VkExportMemoryWin32HandleInfoKHR {
-    VkStructureType               sType;
-    const void*                   pNext;
-    const SECURITY_ATTRIBUTES*    pAttributes;
-    DWORD                         dwAccess;
-    LPCWSTR                       name;
-} VkExportMemoryWin32HandleInfoKHR;
-
-typedef struct VkMemoryWin32HandlePropertiesKHR {
-    VkStructureType    sType;
-    void*              pNext;
-    uint32_t           memoryTypeBits;
-} VkMemoryWin32HandlePropertiesKHR;
-
-typedef struct VkMemoryGetWin32HandleInfoKHR {
-    VkStructureType                       sType;
-    const void*                           pNext;
-    VkDeviceMemory                        memory;
-    VkExternalMemoryHandleTypeFlagBits    handleType;
-} VkMemoryGetWin32HandleInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryWin32HandleKHR)(VkDevice device, const VkMemoryGetWin32HandleInfoKHR* pGetWin32HandleInfo, HANDLE* pHandle);
-typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryWin32HandlePropertiesKHR)(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, HANDLE handle, VkMemoryWin32HandlePropertiesKHR* pMemoryWin32HandleProperties);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetMemoryWin32HandleKHR(
-    VkDevice                                    device,
-    const VkMemoryGetWin32HandleInfoKHR*        pGetWin32HandleInfo,
-    HANDLE*                                     pHandle);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetMemoryWin32HandlePropertiesKHR(
-    VkDevice                                    device,
-    VkExternalMemoryHandleTypeFlagBits          handleType,
-    HANDLE                                      handle,
-    VkMemoryWin32HandlePropertiesKHR*           pMemoryWin32HandleProperties);
-#endif
-
-#define VK_KHR_win32_keyed_mutex 1
-#define VK_KHR_WIN32_KEYED_MUTEX_SPEC_VERSION 1
-#define VK_KHR_WIN32_KEYED_MUTEX_EXTENSION_NAME "VK_KHR_win32_keyed_mutex"
-
-typedef struct VkWin32KeyedMutexAcquireReleaseInfoKHR {
-    VkStructureType          sType;
-    const void*              pNext;
-    uint32_t                 acquireCount;
-    const VkDeviceMemory*    pAcquireSyncs;
-    const uint64_t*          pAcquireKeys;
-    const uint32_t*          pAcquireTimeouts;
-    uint32_t                 releaseCount;
-    const VkDeviceMemory*    pReleaseSyncs;
-    const uint64_t*          pReleaseKeys;
-} VkWin32KeyedMutexAcquireReleaseInfoKHR;
-
-
-
-#define VK_KHR_external_semaphore_win32 1
-#define VK_KHR_EXTERNAL_SEMAPHORE_WIN32_SPEC_VERSION 1
-#define VK_KHR_EXTERNAL_SEMAPHORE_WIN32_EXTENSION_NAME "VK_KHR_external_semaphore_win32"
-
-typedef struct VkImportSemaphoreWin32HandleInfoKHR {
-    VkStructureType                          sType;
-    const void*                              pNext;
-    VkSemaphore                              semaphore;
-    VkSemaphoreImportFlags                   flags;
-    VkExternalSemaphoreHandleTypeFlagBits    handleType;
-    HANDLE                                   handle;
-    LPCWSTR                                  name;
-} VkImportSemaphoreWin32HandleInfoKHR;
-
-typedef struct VkExportSemaphoreWin32HandleInfoKHR {
-    VkStructureType               sType;
-    const void*                   pNext;
-    const SECURITY_ATTRIBUTES*    pAttributes;
-    DWORD                         dwAccess;
-    LPCWSTR                       name;
-} VkExportSemaphoreWin32HandleInfoKHR;
-
-typedef struct VkD3D12FenceSubmitInfoKHR {
-    VkStructureType    sType;
-    const void*        pNext;
-    uint32_t           waitSemaphoreValuesCount;
-    const uint64_t*    pWaitSemaphoreValues;
-    uint32_t           signalSemaphoreValuesCount;
-    const uint64_t*    pSignalSemaphoreValues;
-} VkD3D12FenceSubmitInfoKHR;
-
-typedef struct VkSemaphoreGetWin32HandleInfoKHR {
-    VkStructureType                          sType;
-    const void*                              pNext;
-    VkSemaphore                              semaphore;
-    VkExternalSemaphoreHandleTypeFlagBits    handleType;
-} VkSemaphoreGetWin32HandleInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkImportSemaphoreWin32HandleKHR)(VkDevice device, const VkImportSemaphoreWin32HandleInfoKHR* pImportSemaphoreWin32HandleInfo);
-typedef VkResult (VKAPI_PTR *PFN_vkGetSemaphoreWin32HandleKHR)(VkDevice device, const VkSemaphoreGetWin32HandleInfoKHR* pGetWin32HandleInfo, HANDLE* pHandle);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkImportSemaphoreWin32HandleKHR(
-    VkDevice                                    device,
-    const VkImportSemaphoreWin32HandleInfoKHR*  pImportSemaphoreWin32HandleInfo);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetSemaphoreWin32HandleKHR(
-    VkDevice                                    device,
-    const VkSemaphoreGetWin32HandleInfoKHR*     pGetWin32HandleInfo,
-    HANDLE*                                     pHandle);
-#endif
-
-#define VK_KHR_external_fence_win32 1
-#define VK_KHR_EXTERNAL_FENCE_WIN32_SPEC_VERSION 1
-#define VK_KHR_EXTERNAL_FENCE_WIN32_EXTENSION_NAME "VK_KHR_external_fence_win32"
-
-typedef struct VkImportFenceWin32HandleInfoKHR {
-    VkStructureType                      sType;
-    const void*                          pNext;
-    VkFence                              fence;
-    VkFenceImportFlags                   flags;
-    VkExternalFenceHandleTypeFlagBits    handleType;
-    HANDLE                               handle;
-    LPCWSTR                              name;
-} VkImportFenceWin32HandleInfoKHR;
-
-typedef struct VkExportFenceWin32HandleInfoKHR {
-    VkStructureType               sType;
-    const void*                   pNext;
-    const SECURITY_ATTRIBUTES*    pAttributes;
-    DWORD                         dwAccess;
-    LPCWSTR                       name;
-} VkExportFenceWin32HandleInfoKHR;
-
-typedef struct VkFenceGetWin32HandleInfoKHR {
-    VkStructureType                      sType;
-    const void*                          pNext;
-    VkFence                              fence;
-    VkExternalFenceHandleTypeFlagBits    handleType;
-} VkFenceGetWin32HandleInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkImportFenceWin32HandleKHR)(VkDevice device, const VkImportFenceWin32HandleInfoKHR* pImportFenceWin32HandleInfo);
-typedef VkResult (VKAPI_PTR *PFN_vkGetFenceWin32HandleKHR)(VkDevice device, const VkFenceGetWin32HandleInfoKHR* pGetWin32HandleInfo, HANDLE* pHandle);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkImportFenceWin32HandleKHR(
-    VkDevice                                    device,
-    const VkImportFenceWin32HandleInfoKHR*      pImportFenceWin32HandleInfo);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetFenceWin32HandleKHR(
-    VkDevice                                    device,
-    const VkFenceGetWin32HandleInfoKHR*         pGetWin32HandleInfo,
-    HANDLE*                                     pHandle);
-#endif
-
-#define VK_NV_external_memory_win32 1
-#define VK_NV_EXTERNAL_MEMORY_WIN32_SPEC_VERSION 1
-#define VK_NV_EXTERNAL_MEMORY_WIN32_EXTENSION_NAME "VK_NV_external_memory_win32"
-
-typedef struct VkImportMemoryWin32HandleInfoNV {
-    VkStructureType                      sType;
-    const void*                          pNext;
-    VkExternalMemoryHandleTypeFlagsNV    handleType;
-    HANDLE                               handle;
-} VkImportMemoryWin32HandleInfoNV;
-
-typedef struct VkExportMemoryWin32HandleInfoNV {
-    VkStructureType               sType;
-    const void*                   pNext;
-    const SECURITY_ATTRIBUTES*    pAttributes;
-    DWORD                         dwAccess;
-} VkExportMemoryWin32HandleInfoNV;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryWin32HandleNV)(VkDevice device, VkDeviceMemory memory, VkExternalMemoryHandleTypeFlagsNV handleType, HANDLE* pHandle);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetMemoryWin32HandleNV(
-    VkDevice                                    device,
-    VkDeviceMemory                              memory,
-    VkExternalMemoryHandleTypeFlagsNV           handleType,
-    HANDLE*                                     pHandle);
-#endif
-
-#define VK_NV_win32_keyed_mutex 1
-#define VK_NV_WIN32_KEYED_MUTEX_SPEC_VERSION 1
-#define VK_NV_WIN32_KEYED_MUTEX_EXTENSION_NAME "VK_NV_win32_keyed_mutex"
-
-typedef struct VkWin32KeyedMutexAcquireReleaseInfoNV {
-    VkStructureType          sType;
-    const void*              pNext;
-    uint32_t                 acquireCount;
-    const VkDeviceMemory*    pAcquireSyncs;
-    const uint64_t*          pAcquireKeys;
-    const uint32_t*          pAcquireTimeoutMilliseconds;
-    uint32_t                 releaseCount;
-    const VkDeviceMemory*    pReleaseSyncs;
-    const uint64_t*          pReleaseKeys;
-} VkWin32KeyedMutexAcquireReleaseInfoNV;
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_xcb.h

@@ -1,66 +0,0 @@
-#ifndef VULKAN_XCB_H_
-#define VULKAN_XCB_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_xcb_surface 1
-#define VK_KHR_XCB_SURFACE_SPEC_VERSION   6
-#define VK_KHR_XCB_SURFACE_EXTENSION_NAME "VK_KHR_xcb_surface"
-
-typedef VkFlags VkXcbSurfaceCreateFlagsKHR;
-
-typedef struct VkXcbSurfaceCreateInfoKHR {
-    VkStructureType               sType;
-    const void*                   pNext;
-    VkXcbSurfaceCreateFlagsKHR    flags;
-    xcb_connection_t*             connection;
-    xcb_window_t                  window;
-} VkXcbSurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateXcbSurfaceKHR)(VkInstance instance, const VkXcbSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceXcbPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, xcb_connection_t* connection, xcb_visualid_t visual_id);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateXcbSurfaceKHR(
-    VkInstance                                  instance,
-    const VkXcbSurfaceCreateInfoKHR*            pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-
-VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceXcbPresentationSupportKHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t                                    queueFamilyIndex,
-    xcb_connection_t*                           connection,
-    xcb_visualid_t                              visual_id);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_xlib.h

@@ -1,66 +0,0 @@
-#ifndef VULKAN_XLIB_H_
-#define VULKAN_XLIB_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_KHR_xlib_surface 1
-#define VK_KHR_XLIB_SURFACE_SPEC_VERSION  6
-#define VK_KHR_XLIB_SURFACE_EXTENSION_NAME "VK_KHR_xlib_surface"
-
-typedef VkFlags VkXlibSurfaceCreateFlagsKHR;
-
-typedef struct VkXlibSurfaceCreateInfoKHR {
-    VkStructureType                sType;
-    const void*                    pNext;
-    VkXlibSurfaceCreateFlagsKHR    flags;
-    Display*                       dpy;
-    Window                         window;
-} VkXlibSurfaceCreateInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateXlibSurfaceKHR)(VkInstance instance, const VkXlibSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
-typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceXlibPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, Display* dpy, VisualID visualID);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateXlibSurfaceKHR(
-    VkInstance                                  instance,
-    const VkXlibSurfaceCreateInfoKHR*           pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkSurfaceKHR*                               pSurface);
-
-VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceXlibPresentationSupportKHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t                                    queueFamilyIndex,
-    Display*                                    dpy,
-    VisualID                                    visualID);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_xlib_randr.h

@@ -1,54 +0,0 @@
-#ifndef VULKAN_XLIB_RANDR_H_
-#define VULKAN_XLIB_RANDR_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2017 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_EXT_acquire_xlib_display 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_SPEC_VERSION 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_EXTENSION_NAME "VK_EXT_acquire_xlib_display"
-
-typedef VkResult (VKAPI_PTR *PFN_vkAcquireXlibDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, VkDisplayKHR display);
-typedef VkResult (VKAPI_PTR *PFN_vkGetRandROutputDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, RROutput rrOutput, VkDisplayKHR* pDisplay);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkAcquireXlibDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    VkDisplayKHR                                display);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetRandROutputDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    RROutput                                    rrOutput,
-    VkDisplayKHR*                               pDisplay);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

include/vulkan/vulkan_xlib_xrandr.h

@@ -1,54 +0,0 @@
-#ifndef VULKAN_XLIB_XRANDR_H_
-#define VULKAN_XLIB_XRANDR_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2018 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_EXT_acquire_xlib_display 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_SPEC_VERSION 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_EXTENSION_NAME "VK_EXT_acquire_xlib_display"
-
-typedef VkResult (VKAPI_PTR *PFN_vkAcquireXlibDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, VkDisplayKHR display);
-typedef VkResult (VKAPI_PTR *PFN_vkGetRandROutputDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, RROutput rrOutput, VkDisplayKHR* pDisplay);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkAcquireXlibDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    VkDisplayKHR                                display);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetRandROutputDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    RROutput                                    rrOutput,
-    VkDisplayKHR*                               pDisplay);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

meson.build

@@ -1,4 +1,4 @@
-# Copyright © 2017-2018 Intel Corporation
+# Copyright © 2017 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -29,10 +29,6 @@ project(
   default_options : ['buildtype=debugoptimized', 'c_std=c99', 'cpp_std=c++11']
 )
 
-null_dep = dependency('', required : false)
-
-system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
-
 # Arguments for the preprocessor, put these in a separate array from the C and
 # C++ (cpp in meson terminology) arguments since they need to be added to the
 # default arguments for both C and C++.
@@ -52,10 +48,6 @@ with_libunwind = get_option('libunwind')
 with_asm = get_option('asm')
 with_osmesa = get_option('osmesa')
 with_swr_arches = get_option('swr-arches').split(',')
-with_tools = get_option('tools').split(',')
-if with_tools.contains('all')
-  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau']
-endif
 if get_option('texture-float')
   pre_args += '-DTEXTURE_FLOAT_ENABLED'
   message('WARNING: Floating-point texture enabled. Please consult docs/patents.txt and your lawyer before building mesa.')
@@ -91,8 +83,6 @@ if (with_gles1 or with_gles2) and not with_opengl
   error('building OpenGL ES without OpenGL is not supported.')
 endif
 
-system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
-
 with_dri = false
 with_dri_i915 = false
 with_dri_i965 = false
@@ -102,18 +92,13 @@ with_dri_nouveau = false
 with_dri_swrast = false
 _drivers = get_option('dri-drivers')
 if _drivers == 'auto'
-  if system_has_kms_drm
-    # TODO: PPC, Sparc
+  # TODO: PPC, Sparc
+  if not ['darwin', 'windows'].contains(host_machine.system())
     if ['x86', 'x86_64'].contains(host_machine.cpu_family())
       _drivers = 'i915,i965,r100,r200,nouveau'
-    elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-      _drivers = ''
     else
       error('Unknown architecture. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
-  elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
-    # only swrast would make sense here, but gallium swrast is a much better default
-    _drivers = ''
   else
     error('Unknown OS. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
@@ -141,24 +126,21 @@ with_gallium_vc4 = false
 with_gallium_vc5 = false
 with_gallium_etnaviv = false
 with_gallium_imx = false
-with_gallium_tegra = false
 with_gallium_i915 = false
 with_gallium_svga = false
 with_gallium_virgl = false
 with_gallium_swr = false
 _drivers = get_option('gallium-drivers')
 if _drivers == 'auto'
-  if system_has_kms_drm
+  if not ['darwin', 'windows'].contains(host_machine.system())
     # TODO: PPC, Sparc
     if ['x86', 'x86_64'].contains(host_machine.cpu_family())
       _drivers = 'r300,r600,radeonsi,nouveau,virgl,svga,swrast'
     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-      _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,nouveau,tegra,virgl,swrast'
+      _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,virgl,svga,swrast'
     else
       error('Unknown architecture. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
-  elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
-    _drivers = 'swrast'
   else
     error('Unknown OS. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
@@ -176,19 +158,11 @@ if _drivers != ''
   with_gallium_vc5 = _split.contains('vc5')
   with_gallium_etnaviv = _split.contains('etnaviv')
   with_gallium_imx = _split.contains('imx')
-  with_gallium_tegra = _split.contains('tegra')
   with_gallium_i915 = _split.contains('i915')
   with_gallium_svga = _split.contains('svga')
   with_gallium_virgl = _split.contains('virgl')
   with_gallium_swr = _split.contains('swr')
   with_gallium = true
-  if system_has_kms_drm
-    _glx = get_option('glx')
-    _egl = get_option('egl')
-    if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 'false')
-      with_dri = true
-    endif
-  endif
 endif
 
 with_intel_vk = false
@@ -196,17 +170,15 @@ with_amd_vk = false
 with_any_vk = false
 _vulkan_drivers = get_option('vulkan-drivers')
 if _vulkan_drivers == 'auto'
-  if system_has_kms_drm
+  if not ['darwin', 'windows'].contains(host_machine.system())
     if host_machine.cpu_family().startswith('x86')
       _vulkan_drivers = 'amd,intel'
     else
       error('Unknown architecture. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
-  elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
+  else
     # No vulkan driver supports windows or macOS currently
     _vulkan_drivers = ''
-  else
-    error('Unknown OS. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
 endif
 if _vulkan_drivers != ''
@@ -228,10 +200,14 @@ endif
 if with_gallium_pl111 and not with_gallium_vc4
   error('pl111 driver requires vc4 driver')
 endif
-if with_gallium_tegra and not with_gallium_nouveau
-  error('tegra driver requires nouveau driver')
+
+dep_libdrm_intel = []
+if with_dri_i915 or with_gallium_i915
+  dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
 endif
 
+system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
+
 if host_machine.system() == 'darwin'
   with_dri_platform = 'apple'
 elif ['windows', 'cygwin'].contains(host_machine.system())
@@ -257,12 +233,8 @@ _platforms = get_option('platforms')
 if _platforms == 'auto'
   if system_has_kms_drm
     _platforms = 'x11,wayland,drm,surfaceless'
-  elif ['darwin', 'windows', 'cygwin'].contains(host_machine.system())
-    _platforms = 'x11,surfaceless'
-  elif ['haiku'].contains(host_machine.system())
-    _platforms = 'haiku'
   else
-    error('Unknown OS. Please pass -Dplatforms to set platforms. Patches gladly accepted to fix this.')
+    error('Unknown OS, no platforms enabled. Patches gladly accepted to fix this.')
   endif
 endif
 if _platforms != ''
@@ -271,7 +243,6 @@ if _platforms != ''
   with_platform_x11 = _split.contains('x11')
   with_platform_wayland = _split.contains('wayland')
   with_platform_drm = _split.contains('drm')
-  with_platform_haiku = _split.contains('haiku')
   with_platform_surfaceless = _split.contains('surfaceless')
   egl_native_platform = _split[0]
 endif
@@ -280,12 +251,9 @@ with_glx = get_option('glx')
 if with_glx == 'auto'
   if with_dri
     with_glx = 'dri'
-  elif with_platform_haiku
-    with_glx = 'disabled'
   elif with_gallium
     # Even when building just gallium drivers the user probably wants dri
     with_glx = 'dri'
-    with_dri = true
   elif with_platform_x11 and with_any_opengl and not with_any_vk
     # The automatic behavior should not be to turn on xlib based glx when
     # building only vulkan drivers
@@ -294,6 +262,11 @@ if with_glx == 'auto'
     with_glx = 'disabled'
   endif
 endif
+if with_glx == 'dri'
+   if with_gallium
+      with_dri = true
+   endif
+endif
 
 if not (with_dri or with_gallium or with_glx == 'xlib' or with_glx == 'gallium-xlib')
   with_gles1 = false
@@ -303,14 +276,16 @@ if not (with_dri or with_gallium or with_glx == 'xlib' or with_glx == 'gallium-x
   with_shared_glapi = false
 endif
 
-_gbm = get_option('gbm')
-if _gbm == 'auto'
-  with_gbm = system_has_kms_drm and with_dri
+with_gbm = get_option('gbm')
+if with_gbm == 'auto' and with_dri  # TODO: or gallium
+  with_gbm = system_has_kms_drm
+elif with_gbm == 'true'
+  if not system_has_kms_drm
+    error('GBM only supports DRM/KMS platforms')
+  endif
+  with_gbm = true
 else
-  with_gbm = _gbm == 'true'
-endif
-if with_gbm and not system_has_kms_drm
-  error('GBM only supports DRM/KMS platforms')
+  with_gbm = false
 endif
 
 _egl = get_option('egl')
@@ -323,8 +298,6 @@ elif _egl == 'true'
     error('EGL requires shared-glapi')
   elif egl_native_platform == ''
     error('No platforms specified, consider -Dplatforms=drm,x11 at least')
-  elif not ['disabled', 'dri'].contains(with_glx)
-    error('EGL requires dri, but a GLX is being built without dri')
   endif
   with_egl = true
 else
@@ -382,18 +355,24 @@ if with_vulkan_icd_dir == ''
 endif
 
 with_dri2 = (with_dri or with_any_vk) and with_dri_platform == 'drm'
-_dri3 = get_option('dri3')
-if _dri3 == 'auto'
-  with_dri3 = system_has_kms_drm and with_dri2
+with_dri3 = get_option('dri3')
+if with_dri3 == 'auto'
+  if system_has_kms_drm and with_dri2
+    with_dri3 = true
+  else
+    with_dri3 = false
+ endif
+elif with_dri3 == 'true'
+  with_dri3 = true
 else
-  with_dri3 = _dri3 == 'true'
+  with_dri3 = false
 endif
 
 if with_any_vk and (with_platform_x11 and not with_dri3)
   error('Vulkan drivers require dri3 for X11 support')
 endif
 if with_dri or with_gallium
-  if with_glx == 'disabled' and not with_egl and not with_platform_haiku
+  if with_glx == 'disabled' and not with_egl
     error('building dri or gallium drivers require at least one window system')
   endif
 endif
@@ -424,7 +403,7 @@ elif _vdpau == 'auto'
   _vdpau = 'true'
 endif
 with_gallium_vdpau = _vdpau == 'true'
-dep_vdpau = null_dep
+dep_vdpau = []
 if with_gallium_vdpau
   dep_vdpau = dependency('vdpau', version : '>= 1.1')
   dep_vdpau = declare_dependency(
@@ -463,7 +442,7 @@ elif _xvmc == 'auto'
   _xvmc = 'true'
 endif
 with_gallium_xvmc = _xvmc == 'true'
-dep_xvmc = null_dep
+dep_xvmc = []
 if with_gallium_xvmc
   dep_xvmc = dependency('xvmc', version : '>= 1.0.6')
 endif
@@ -475,67 +454,34 @@ endif
 
 _omx = get_option('gallium-omx')
 if not system_has_kms_drm
-  if ['auto', 'disabled'].contains(_omx)
-    _omx = 'disabled'
-  else
+  if _omx == 'true'
     error('OMX state tracker can only be built on unix-like OSes.')
+  else
+    _omx = 'false'
   endif
 elif not (with_platform_x11 or with_platform_drm)
-  if ['auto', 'disabled'].contains(_omx)
-    _omx = 'disabled'
-  else
+  if _omx == 'true'
     error('OMX state tracker requires X11 or drm platform support.')
+  else
+    _omx = 'false'
   endif
 elif not (with_gallium_r600 or with_gallium_radeonsi or with_gallium_nouveau)
-  if ['auto', 'disabled'].contains(_omx)
-    _omx = 'disabled'
-  else
+  if _omx == 'true'
     error('OMX state tracker requires at least one of the following gallium drivers: r600, radeonsi, nouveau.')
+  else
+    _omx = 'false'
   endif
+elif _omx == 'auto'
+  _omx = 'true'
 endif
-with_gallium_omx = _omx
-dep_omx = null_dep
-dep_omx_other = []
-if ['auto', 'bellagio'].contains(_omx)
-  dep_omx = dependency(
-    'libomxil-bellagio', required : _omx == 'bellagio'
-  )
-  if dep_omx.found()
-    with_gallium_omx = 'bellagio'
-  endif
+with_gallium_omx = _omx == 'true'
+dep_omx = []
+if with_gallium_omx
+  dep_omx = dependency('libomxil-bellagio')
 endif
-if ['auto', 'tizonia'].contains(_omx)
-  if with_dri and with_egl
-    dep_omx = dependency(
-      'libtizonia', version : '>= 0.10.0',
-      required : _omx == 'tizonia',
-    )
-    dep_omx_other = [
-      dependency('libtizplatform', required : _omx == 'tizonia'),
-      dependency('tizilheaders', required : _omx == 'tizonia'),
-    ]
-    if dep_omx.found() and dep_omx_other[0].found() and dep_omx_other[1].found()
-      with_gallium_omx = 'tizonia'
-    endif
-  elif _omx == 'tizonia'
-    error('OMX-Tizonia state tracker requires dri and egl')
-  endif
-endif
-if _omx == 'auto'
-  with_gallium_omx = 'disabled'
-else
-  with_gallium_omx = _omx
-endif
-
-pre_args += [
-  '-DENABLE_ST_OMX_BELLAGIO=' + (with_gallium_omx == 'bellagio' ? '1' : '0'),
-  '-DENABLE_ST_OMX_TIZONIA=' + (with_gallium_omx == 'tizonia' ? '1' : '0'),
-]
-
 
 omx_drivers_path = get_option('omx-libs-path')
-
-if with_gallium_omx != 'disabled'
+if with_gallium_omx
   # Figure out where to put the omx driver.
   # FIXME: this could all be vastly simplified by adding a 'defined_variable'
   # argument to meson's get_pkgconfig_variable method.
@@ -582,7 +528,7 @@ elif _va == 'auto'
   _va = 'true'
 endif
 with_gallium_va = _va == 'true'
-dep_va = null_dep
+dep_va = []
 if with_gallium_va
   dep_va = dependency('libva', version : '>= 0.38.0')
   dep_va_headers = declare_dependency(
@@ -641,14 +587,14 @@ if _opencl != 'disabled'
   with_gallium_opencl = true
   with_opencl_icd = _opencl == 'icd'
 else
-  dep_clc = null_dep
+  dep_clc = []
   with_gallium_opencl = false
   with_gallium_icd = false
 endif
 
 gl_pkgconfig_c_flags = []
 if with_platform_x11
-  if with_any_vk or with_egl or (with_glx == 'dri' and with_dri_platform == 'drm')
+  if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
     pre_args += '-DHAVE_X11_PLATFORM'
   endif
   if with_glx == 'xlib' or with_glx == 'gallium-xlib'
@@ -660,8 +606,6 @@ if with_platform_x11
     endif
     if with_dri_platform == 'drm'
       pre_args += '-DGLX_USE_DRM'
-    elif with_dri_platform == 'apple'
-      pre_args += '-DGLX_USE_APPLEGL'
     elif with_dri_platform == 'windows'
       pre_args += '-DGLX_USE_WINDOWSGL'
     endif
@@ -687,9 +631,6 @@ if with_platform_android
   ]
   pre_args += '-DHAVE_ANDROID_PLATFORM'
 endif
-if with_platform_haiku
-  pre_args += '-DHAVE_HAIKU_PLATFORM'
-endif
 
 prog_python2 = find_program('python2')
 has_mako = run_command(prog_python2, '-c', 'import mako')
@@ -834,26 +775,9 @@ else
 endif
 
 # Check for GCC style atomics
-dep_atomic = null_dep
-
 if cc.compiles('int main() { int n; return __atomic_load_n(&n, __ATOMIC_ACQUIRE); }',
                name : 'GCC atomic builtins')
   pre_args += '-DUSE_GCC_ATOMIC_BUILTINS'
-
-  # Not all atomic calls can be turned into lock-free instructions, in which
-  # GCC will make calls into the libatomic library. Check whether we need to
-  # link with -latomic.
-  #
-  # This can happen for 64-bit atomic operations on 32-bit architectures such
-  # as ARM.
-  if not cc.links('''#include <stdint.h>
-                     int main() {
-                       uint64_t n;
-                       return (int)__atomic_load_n(&n, __ATOMIC_ACQUIRE);
-                     }''',
-                  name : 'GCC atomic builtins required -latomic')
-    dep_atomic = cc.find_library('atomic')
-  endif
 endif
 if not cc.links('''#include <stdint.h>
                    uint64_t v;
@@ -914,8 +838,8 @@ elif cc.has_header_symbol('sys/mkdev.h', 'major')
   pre_args += '-DMAJOR_IN_MKDEV'
 endif
 
-foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h', 'endian.h']
-  if cc.compiles('#include <@0@>'.format(h), name : '@0@'.format(h))
+foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h']
+  if cc.has_header(h)
     pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
   endif
 endforeach
@@ -972,14 +896,10 @@ if cc.links('int main() { return 0; }',
             name : 'dynamic-list')
   with_ld_dynamic_list = true
 endif
-ld_args_build_id = []
-if build_machine.system() != 'darwin'
-   ld_args_build_id += '-Wl,--build-id=sha1'
-endif
 
 # check for dl support
 if cc.has_function('dlopen')
-  dep_dl = null_dep
+  dep_dl = []
 else
   dep_dl = cc.find_library('dl')
 endif
@@ -998,11 +918,21 @@ endif
 
 # Determine whether or not the rt library is needed for time functions
 if cc.has_function('clock_gettime')
-  dep_clock = null_dep
+  dep_clock = []
 else
   dep_clock = cc.find_library('rt')
 endif
 
+with_gallium_drisw_kms = false
+dep_libdrm = dependency('libdrm', version : '>= 2.4.75',
+                        required : with_dri2 or with_dri3)
+if dep_libdrm.found()
+  pre_args += '-DHAVE_LIBDRM'
+  if with_dri_platform == 'drm' and with_dri
+    with_gallium_drisw_kms = true
+  endif
+endif
+
 # TODO: some of these may be conditional
 dep_zlib = dependency('zlib', version : '>= 1.2.3')
 pre_args += '-DHAVE_ZLIB'
@@ -1016,71 +946,35 @@ if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or with_gallium_ope
     dep_elf = cc.find_library('elf')
   endif
 else
-  dep_elf = null_dep
+  dep_elf = []
 endif
 dep_expat = dependency('expat')
 # this only exists on linux so either this is linux and it will be found, or
 # its not linux and and wont
 dep_m = cc.find_library('m', required : false)
 
-# Check for libdrm. various drivers have different libdrm version requirements,
-# but we always want to use the same version for all libdrm modules. That means
-# even if driver foo requires 2.4.0 and driver bar requires 2.4.3, if foo and
-# bar are both on use 2.4.3 for both of them
-dep_libdrm_amdgpu = null_dep
-dep_libdrm_radeon = null_dep
-dep_libdrm_nouveau = null_dep
-dep_libdrm_etnaviv = null_dep
-dep_libdrm_freedreno = null_dep
-dep_libdrm_intel = null_dep
-
-_drm_amdgpu_ver = '2.4.91'
-_drm_radeon_ver = '2.4.71'
-_drm_nouveau_ver = '2.4.66'
-_drm_etnaviv_ver = '2.4.89'
-_drm_freedreno_ver = '2.4.91'
-_drm_intel_ver = '2.4.75'
-_drm_ver = '2.4.75'
-
-_libdrm_checks = [
-  ['intel', with_dri_i915 or with_gallium_i915],
-  ['amdgpu', with_amd_vk or with_gallium_radeonsi],
-  ['radeon', (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
-              with_gallium_r300 or with_gallium_r600)],
-  ['nouveau', (with_gallium_nouveau or with_dri_nouveau)],
-  ['etnaviv', with_gallium_etnaviv],
-  ['freedreno', with_gallium_freedreno],
-]
-
-# Loop over the enables versions and get the highest libdrm requirement for all
-# active drivers.
-foreach d : _libdrm_checks
-  ver = get_variable('_drm_@0@_ver'.format(d[0]))
-  if d[1] and ver.version_compare('>' + _drm_ver)
-    _drm_ver = ver
-  endif
-endforeach
-
-# Then get each libdrm module
-foreach d : _libdrm_checks
-  if d[1]
-    set_variable(
-      'dep_libdrm_' + d[0],
-      dependency('libdrm_' + d[0], version : '>=' + _drm_ver)
-    )
-  endif
-endforeach
-
-with_gallium_drisw_kms = false
-dep_libdrm = dependency(
-  'libdrm', version : '>=' + _drm_ver,
-  required : with_dri2 or with_dri3
-)
-if dep_libdrm.found()
-  pre_args += '-DHAVE_LIBDRM'
-  if with_dri_platform == 'drm' and with_dri
-    with_gallium_drisw_kms = true
-  endif
+dep_libdrm_amdgpu = []
+dep_libdrm_radeon = []
+dep_libdrm_nouveau = []
+dep_libdrm_etnaviv = []
+dep_libdrm_freedreno = []
+if with_amd_vk or with_gallium_radeonsi
+  dep_libdrm_amdgpu = dependency(
+    'libdrm_amdgpu', version : ['>= 2.4.89', '!= 2.4.90']
+  )
+endif
+if (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
+    with_gallium_r300 or with_gallium_r600)
+  dep_libdrm_radeon = dependency('libdrm_radeon', version : '>= 2.4.71')
+endif
+if with_gallium_nouveau or with_dri_nouveau
+  dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
+endif
+if with_gallium_etnaviv
+  dep_libdrm_etnaviv = dependency('libdrm_etnaviv', version : '>= 2.4.82')
+endif
+if with_gallium_freedreno
+  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.89')
 endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
@@ -1098,9 +992,9 @@ if with_gallium_opencl
   # TODO: optional modules
 endif
 
-if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
+if with_amd_vk
   _llvm_version = '>= 4.0.0'
-elif with_gallium_opencl or with_gallium_r600
+elif with_gallium_opencl or with_gallium_swr or with_gallium_r600 or with_gallium_radeonsi
   _llvm_version = '>= 3.9.0'
 else
   _llvm_version = '>= 3.3.0'
@@ -1117,7 +1011,7 @@ elif _llvm == 'true'
   dep_llvm = dependency('llvm', version : _llvm_version, modules : llvm_modules)
   with_llvm = true
 else
-  dep_llvm = null_dep
+  dep_llvm = []
   with_llvm = false
 endif
 if with_llvm
@@ -1126,28 +1020,21 @@ if with_llvm
   # that for our version checks.
   # svn suffixes are stripped by meson as of 0.43, and git suffixes are
   # strippped as of 0.44, but we support older meson versions.
-
-  # 3 digits versions in LLVM only started from 3.4.1 on
-  if dep_llvm.version().version_compare('>= 3.4.1')
-    _llvm_patch = _llvm_version[2]
-  else
-    _llvm_patch = '0'
-  endif
-
+  _llvm_patch = _llvm_version[2]
   if _llvm_patch.endswith('svn')
     _llvm_patch = _llvm_patch.split('s')[0]
   elif _llvm_patch.contains('git')
     _llvm_patch = _llvm_patch.split('g')[0]
   endif
   pre_args += [
-    '-DHAVE_LLVM=0x0@0@0@1@'.format(_llvm_version[0], _llvm_version[1]),
+    '-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], _llvm_patch),
     '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
   ]
 elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
-  error('The following drivers require LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
+  error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
 endif
 
-dep_glvnd = null_dep
+dep_glvnd = []
 if with_glvnd
   dep_glvnd = dependency('libglvnd', version : '>= 0.2.0')
   pre_args += '-DUSE_LIBGLVND=1'
@@ -1159,7 +1046,7 @@ if with_valgrind != 'false'
     pre_args += '-DHAVE_VALGRIND'
   endif
 else
-  dep_valgrind = null_dep
+  dep_valgrind = []
 endif
 
 # pthread stubs. Lets not and say we didn't
@@ -1167,7 +1054,7 @@ endif
 prog_bison = find_program('bison', required : with_any_opengl)
 prog_flex = find_program('flex', required : with_any_opengl)
 
-dep_selinux = null_dep
+dep_selinux = []
 if get_option('selinux')
   dep_selinux = dependency('libselinux')
   pre_args += '-DMESA_SELINUX'
@@ -1181,7 +1068,7 @@ if with_libunwind != 'false'
     pre_args += '-DHAVE_LIBUNWIND'
   endif
 else
-  dep_unwind = null_dep
+  dep_unwind = []
 endif
 
 # TODO: gallium-hud
@@ -1220,29 +1107,29 @@ if with_platform_wayland
   pre_args += ['-DHAVE_WAYLAND_PLATFORM', '-DWL_HIDE_DEPRECATED']
 else
   prog_wl_scanner = []
-  dep_wl_protocols = null_dep
-  dep_wayland_client = null_dep
-  dep_wayland_server = null_dep
+  dep_wl_protocols = []
+  dep_wayland_client = []
+  dep_wayland_server = []
   wayland_dmabuf_xml = ''
 endif
 
-dep_x11 = null_dep
-dep_xext = null_dep
-dep_xdamage = null_dep
-dep_xfixes = null_dep
-dep_x11_xcb = null_dep
-dep_xcb = null_dep
-dep_xcb_glx = null_dep
-dep_xcb_dri2 = null_dep
-dep_xcb_dri3 = null_dep
-dep_dri2proto = null_dep
-dep_glproto = null_dep
-dep_xxf86vm = null_dep
-dep_xcb_dri3 = null_dep
-dep_xcb_present = null_dep
-dep_xcb_sync = null_dep
-dep_xcb_xfixes = null_dep
-dep_xshmfence = null_dep
+dep_x11 = []
+dep_xext = []
+dep_xdamage = []
+dep_xfixes = []
+dep_x11_xcb = []
+dep_xcb = []
+dep_xcb_glx = []
+dep_xcb_dri2 = []
+dep_xcb_dri3 = []
+dep_dri2proto = []
+dep_glproto = []
+dep_xxf86vm = []
+dep_xcb_dri3 = []
+dep_xcb_present = []
+dep_xcb_sync = []
+dep_xcb_xfixes = []
+dep_xshmfence = []
 if with_platform_x11
   if with_glx == 'xlib' or with_glx == 'gallium-xlib'
     dep_x11 = dependency('x11')
@@ -1257,23 +1144,18 @@ if with_platform_x11
     dep_xxf86vm = dependency('xxf86vm', required : false)
   endif
   if (with_any_vk or with_glx == 'dri' or
-       (with_gallium_vdpau or with_gallium_xvmc or with_gallium_va or
-        with_gallium_omx != 'disabled'))
+       (with_gallium_vdpau or with_gallium_xvmc or with_gallium_omx or
+        with_gallium_xa))
     dep_xcb = dependency('xcb')
     dep_x11_xcb = dependency('x11-xcb')
   endif
-  if with_any_vk or with_egl or (with_glx == 'dri' and with_dri_platform == 'drm')
+  if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
     dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
 
     if with_dri3
       pre_args += '-DHAVE_DRI3'
       dep_xcb_dri3 = dependency('xcb-dri3')
       dep_xcb_present = dependency('xcb-present')
-      # until xcb-dri3 has been around long enough to make a hard-dependency:
-      if (dep_xcb_dri3.version().version_compare('>= 1.13') and
-          dep_xcb_present.version().version_compare('>= 1.13'))
-        pre_args += '-DHAVE_DRI3_MODIFIERS'
-      endif
       dep_xcb_sync = dependency('xcb-sync')
       dep_xshmfence = dependency('xshmfence', version : '>= 1.1')
     endif
@@ -1284,9 +1166,7 @@ if with_platform_x11
     endif
     dep_glproto = dependency('glproto', version : '>= 1.4.14')
   endif
-  if (with_egl or (
-      with_gallium_vdpau or with_gallium_xvmc or with_gallium_xa or
-      with_gallium_omx != 'disabled'))
+  if with_egl
     dep_xcb_xfixes = dependency('xcb-xfixes')
   endif
 endif
@@ -1302,9 +1182,11 @@ if _sensors != 'false'
     pre_args += '-DHAVE_LIBSENSORS=1'
   endif
 else
-  dep_lmsensors = null_dep
+  dep_lmsensors = []
 endif
 
+# TODO: gallium tests
+
 # TODO: various libdirs
 
 # TODO: gallium driver dirs
@@ -1335,7 +1217,7 @@ gl_priv_reqs = [
 if dep_libdrm.found()
   gl_priv_reqs += 'libdrm >= 2.4.75'
 endif
-if dep_xxf86vm.found()
+if dep_xxf86vm != [] and dep_xxf86vm.found()
   gl_priv_reqs += 'xxf86vm'
 endif
 if with_dri_platform == 'drm'
@@ -1349,15 +1231,12 @@ endif
 if dep_m.found()
   gl_priv_libs += '-lm'
 endif
-if dep_dl.found()
+if dep_dl != [] and dep_dl.found()
   gl_priv_libs += '-ldl'
 endif
 
 pkg = import('pkgconfig')
 
-env_test = environment()
-env_test.set('NM', find_program('nm').path())
-
 subdir('include')
 subdir('bin')
 subdir('src')

meson_options.txt

@@ -91,8 +91,8 @@ option(
   'gallium-omx',
   type : 'combo',
   value : 'auto',
-  choices : ['auto', 'disabled', 'bellagio', 'tizonia'],
-  description : 'enable gallium omx state tracker.',
+  choices : ['auto', 'true', 'false'],
+  description : 'enable gallium omx bellagio state tracker.',
 )
 option(
   'omx-libs-path',
@@ -280,9 +280,3 @@ option(
   value : 'avx,avx2',
   description : 'Comma delemited swr architectures. choices : avx,avx2,knl,skx'
 )
-option(
-  'tools',
-  type : 'string',
-  value : '',
-  description : 'Comma delimited list of tools to build. choices : freedreno,glsl,intel,nir,nouveau or all'
-)

scons/gallium.py

@@ -134,9 +134,7 @@ def check_cc(env, cc, expr, cpp_opt = '-E'):
     source.write('#if !(%s)\n#error\n#endif\n' % expr)
     source.close()
 
-    # sys.stderr.write('%r %s %s\n' % (env['CC'], cpp_opt, source.name));
-
-    pipe = SCons.Action._subproc(env, env.Split(env['CC']) + [cpp_opt, source.name],
+    pipe = SCons.Action._subproc(env, [env['CC'], cpp_opt, source.name],
                                  stdin = 'devnull',
                                  stderr = 'devnull',
                                  stdout = 'devnull')
@@ -354,9 +352,6 @@ def generate(env):
         if check_header(env, 'xlocale.h'):
             cppdefines += ['HAVE_XLOCALE_H']
 
-        if check_header(env, 'endian.h'):
-            cppdefines += ['HAVE_ENDIAN_H']
-
         if check_functions(env, ['strtod_l', 'strtof_l']):
             cppdefines += ['HAVE_STRTOD_L']
 

src/Makefile.am

@@ -67,6 +67,7 @@ SUBDIRS += vulkan
 endif
 
 EXTRA_DIST += vulkan/registry/vk.xml
+EXTRA_DIST += vulkan/registry/vk_android_native_buffer.xml
 
 if HAVE_AMD_DRIVERS
 SUBDIRS += amd

src/amd/Makefile.sources

@@ -45,6 +45,8 @@ AMD_COMPILER_FILES = \
 	common/ac_llvm_util.c \
 	common/ac_llvm_util.h \
 	common/ac_shader_abi.h \
+	common/ac_shader_info.c \
+	common/ac_shader_info.h \
 	common/ac_shader_util.c \
 	common/ac_shader_util.h
 

src/amd/addrlib/addrinterface.cpp

@@ -1054,7 +1054,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
 */
 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
     ADDR_HANDLE                     hLib, ///< address lib handle
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
 {
     Addr::Lib* pLib = Lib::GetLib(hLib);
 
@@ -1072,36 +1072,6 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
     return returnCode;
 }
 
-/**
-****************************************************************************************************
-*   AddrGetMaxMetaAlignments
-*
-*   @brief
-*       Convert maximum alignments for metadata
-*
-*   @return
-*       ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
-****************************************************************************************************
-*/
-ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
-    ADDR_HANDLE                     hLib, ///< address lib handle
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
-{
-    Addr::Lib* pLib = Lib::GetLib(hLib);
-
-    ADDR_E_RETURNCODE returnCode = ADDR_OK;
-
-    if (pLib != NULL)
-    {
-        returnCode = pLib->GetMaxMetaAlignments(pOut);
-    }
-    else
-    {
-        returnCode = ADDR_ERROR;
-    }
-
-    return returnCode;
-}
 
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////

src/amd/addrlib/addrinterface.h

@@ -528,8 +528,7 @@ typedef union _ADDR_SURFACE_FLAGS
         UINT_32 preferEquation       : 1; ///< Return equation index without adjusting tile mode
         UINT_32 matchStencilTileCfg  : 1; ///< Select tile index of stencil as well as depth surface
                                           ///  to make sure they share same tile config parameters
-        UINT_32 disallowLargeThickDegrade   : 1;    ///< Disallow large thick tile degrade
-        UINT_32 reserved             : 1; ///< Reserved bits
+        UINT_32 reserved             : 2; ///< Reserved bits
     };
 
     UINT_32 value;
@@ -2274,7 +2273,7 @@ typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
 {
     UINT_32 size;                 ///< Size of this structure in bytes
-    UINT_32 dccRamBaseAlign;      ///< Base alignment of dcc key
+    UINT_64 dccRamBaseAlign;      ///< Base alignment of dcc key
     UINT_64 dccRamSize;           ///< Size of dcc key
     UINT_64 dccFastClearSize;     ///< Size of dcc key portion that can be fast cleared
     BOOL_32 subLvlCompressible;   ///< Whether sub resource is compressiable
@@ -2299,17 +2298,17 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
 
 /**
 ****************************************************************************************************
-*   ADDR_GET_MAX_ALINGMENTS_OUTPUT
+*   ADDR_GET_MAX_ALIGNMENTS_OUTPUT
 *
 *   @brief
 *       Output structure of AddrGetMaxAlignments
 ****************************************************************************************************
 */
-typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
+typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
 {
     UINT_32 size;                   ///< Size of this structure in bytes
-    UINT_32 baseAlign;              ///< Maximum base alignment in bytes
-} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
+    UINT_64 baseAlign;              ///< Maximum base alignment in bytes
+} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
 
 /**
 ****************************************************************************************************
@@ -2321,19 +2320,9 @@ typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
 */
 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
     ADDR_HANDLE                     hLib,
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
+
 
-/**
-****************************************************************************************************
-*   AddrGetMaxMetaAlignments
-*
-*   @brief
-*       Gets maximnum alignments for metadata
-****************************************************************************************************
-*/
-ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
-    ADDR_HANDLE                     hLib,
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
 
 /**
 ****************************************************************************************************
@@ -2377,25 +2366,22 @@ typedef union _ADDR2_SURFACE_FLAGS
 {
     struct
     {
-        UINT_32 color             :  1; ///< This resource is a color buffer, can be used with RTV
-        UINT_32 depth             :  1; ///< Thie resource is a depth buffer, can be used with DSV
-        UINT_32 stencil           :  1; ///< Thie resource is a stencil buffer, can be used with DSV
-        UINT_32 fmask             :  1; ///< This is an fmask surface
-        UINT_32 overlay           :  1; ///< This is an overlay surface
-        UINT_32 display           :  1; ///< This resource is displable, can be used with DRV
-        UINT_32 prt               :  1; ///< This is a partially resident texture
-        UINT_32 qbStereo          :  1; ///< This is a quad buffer stereo surface
-        UINT_32 interleaved       :  1; ///< Special flag for interleaved YUV surface padding
-        UINT_32 texture           :  1; ///< This resource can be used with SRV
-        UINT_32 unordered         :  1; ///< This resource can be used with UAV
-        UINT_32 rotated           :  1; ///< This resource is rotated and displable
-        UINT_32 needEquation      :  1; ///< This resource needs equation to be generated if possible
-        UINT_32 opt4space         :  1; ///< This resource should be optimized for space
-        UINT_32 minimizeAlign     :  1; ///< This resource should use minimum alignment
-        UINT_32 noMetadata        :  1; ///< This resource has no metadata
-        UINT_32 metaRbUnaligned   :  1; ///< This resource has rb unaligned metadata
-        UINT_32 metaPipeUnaligned :  1; ///< This resource has pipe unaligned metadata
-        UINT_32 reserved          : 14; ///< Reserved bits
+        UINT_32 color         :  1; ///< This resource is a color buffer, can be used with RTV
+        UINT_32 depth         :  1; ///< Thie resource is a depth buffer, can be used with DSV
+        UINT_32 stencil       :  1; ///< Thie resource is a stencil buffer, can be used with DSV
+        UINT_32 fmask         :  1; ///< This is an fmask surface
+        UINT_32 overlay       :  1; ///< This is an overlay surface
+        UINT_32 display       :  1; ///< This resource is displable, can be used with DRV
+        UINT_32 prt           :  1; ///< This is a partially resident texture
+        UINT_32 qbStereo      :  1; ///< This is a quad buffer stereo surface
+        UINT_32 interleaved   :  1; ///< Special flag for interleaved YUV surface padding
+        UINT_32 texture       :  1; ///< This resource can be used with SRV
+        UINT_32 unordered     :  1; ///< This resource can be used with UAV
+        UINT_32 rotated       :  1; ///< This resource is rotated and displable
+        UINT_32 needEquation  :  1; ///< This resource needs equation to be generated if possible
+        UINT_32 opt4space     :  1; ///< This resource should be optimized for space
+        UINT_32 minimizeAlign :  1; ///< This resource should use minimum alignment
+        UINT_32 reserved      : 17; ///< Reserved bits
     };
 
     UINT_32 value;

src/amd/addrlib/addrtypes.h

@@ -76,7 +76,7 @@ typedef int            INT;
 
 #ifndef ADDR_STDCALL
     #if defined(__GNUC__)
-        #if defined(__amd64__) || defined(__x86_64__)
+        #if defined(__AMD64__)
             #define ADDR_STDCALL
         #else
             #define ADDR_STDCALL __attribute__((stdcall))
@@ -87,9 +87,7 @@ typedef int            INT;
 #endif
 
 #ifndef ADDR_FASTCALL
-    #if defined(BRAHMA_ARM)
-        #define ADDR_FASTCALL
-    #elif defined(__GNUC__)
+    #if defined(__GNUC__)
         #if defined(__i386__)
             #define ADDR_FASTCALL __attribute__((regparm(0)))
         #else

src/amd/addrlib/amdgpu_asic_addr.h

@@ -79,14 +79,12 @@
 #define AMDGPU_POLARIS10_RANGE  0x50, 0x5A
 #define AMDGPU_POLARIS11_RANGE  0x5A, 0x64
 #define AMDGPU_POLARIS12_RANGE  0x64, 0x6E
-#define AMDGPU_VEGAM_RANGE      0x6E, 0xFF
 
 #define AMDGPU_CARRIZO_RANGE    0x01, 0x21
 #define AMDGPU_BRISTOL_RANGE    0x10, 0x21
 #define AMDGPU_STONEY_RANGE     0x61, 0xFF
 
 #define AMDGPU_VEGA10_RANGE     0x01, 0x14
-#define AMDGPU_VEGA12_RANGE     0x14, 0x28
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
 
@@ -118,7 +116,6 @@
 #define ASICREV_IS_POLARIS10_P(r)      ASICREV_IS(r, POLARIS10)
 #define ASICREV_IS_POLARIS11_M(r)      ASICREV_IS(r, POLARIS11)
 #define ASICREV_IS_POLARIS12_V(r)      ASICREV_IS(r, POLARIS12)
-#define ASICREV_IS_VEGAM_P(r)          ASICREV_IS(r, VEGAM)
 
 #define ASICREV_IS_CARRIZO(r)          ASICREV_IS(r, CARRIZO)
 #define ASICREV_IS_CARRIZO_BRISTOL(r)  ASICREV_IS(r, BRISTOL)
@@ -126,8 +123,6 @@
 
 #define ASICREV_IS_VEGA10_M(r)         ASICREV_IS(r, VEGA10)
 #define ASICREV_IS_VEGA10_P(r)         ASICREV_IS(r, VEGA10)
-#define ASICREV_IS_VEGA12_P(r)         ASICREV_IS(r, VEGA12)
-#define ASICREV_IS_VEGA12_p(r)         ASICREV_IS(r, VEGA12)
 
 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
 

src/amd/addrlib/core/addrlib.cpp

@@ -285,12 +285,10 @@ ADDR_E_RETURNCODE Lib::Create(
     {
         pCreateOut->numEquations =
             pLib->HwlGetEquationTableInfo(&pCreateOut->pEquationTable);
-
-        pLib->SetMaxAlignments();
-
     }
-    else if ((pLib == NULL) &&
-             (returnCode == ADDR_OK))
+
+    if ((pLib == NULL) &&
+        (returnCode == ADDR_OK))
     {
         // Unknown failures, we return the general error code
         returnCode = ADDR_ERROR;
@@ -338,23 +336,6 @@ VOID Lib::SetMinPitchAlignPixels(
     m_minPitchAlignPixels = (minPitchAlignPixels == 0) ? 1 : minPitchAlignPixels;
 }
 
-/**
-****************************************************************************************************
-*   Lib::SetMaxAlignments
-*
-*   @brief
-*       Set max alignments
-*
-*   @return
-*      N/A
-****************************************************************************************************
-*/
-VOID Lib::SetMaxAlignments()
-{
-    m_maxBaseAlign     = HwlComputeMaxBaseAlignments();
-    m_maxMetaBaseAlign = HwlComputeMaxMetaBaseAlignments();
-}
-
 /**
 ****************************************************************************************************
 *   Lib::GetLib
@@ -377,21 +358,21 @@ Lib* Lib::GetLib(
 *   Lib::GetMaxAlignments
 *
 *   @brief
-*       Gets maximum alignments for data surface (include FMask)
+*       Gets maximum alignments
 *
 *   @return
 *       ADDR_E_RETURNCODE
 ****************************************************************************************************
 */
 ADDR_E_RETURNCODE Lib::GetMaxAlignments(
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut    ///< [out] output structure
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut    ///< [out] output structure
     ) const
 {
     ADDR_E_RETURNCODE returnCode = ADDR_OK;
 
     if (GetFillSizeFieldsFlags() == TRUE)
     {
-        if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
+        if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
         {
             returnCode = ADDR_PARAMSIZEMISMATCH;
         }
@@ -399,54 +380,7 @@ ADDR_E_RETURNCODE Lib::GetMaxAlignments(
 
     if (returnCode == ADDR_OK)
     {
-        if (m_maxBaseAlign != 0)
-        {
-            pOut->baseAlign = m_maxBaseAlign;
-        }
-        else
-        {
-            returnCode = ADDR_NOTIMPLEMENTED;
-        }
-    }
-
-    return returnCode;
-}
-
-/**
-****************************************************************************************************
-*   Lib::GetMaxMetaAlignments
-*
-*   @brief
-*       Gets maximum alignments for metadata (CMask, DCC and HTile)
-*
-*   @return
-*       ADDR_E_RETURNCODE
-****************************************************************************************************
-*/
-ADDR_E_RETURNCODE Lib::GetMaxMetaAlignments(
-    ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut    ///< [out] output structure
-    ) const
-{
-    ADDR_E_RETURNCODE returnCode = ADDR_OK;
-
-    if (GetFillSizeFieldsFlags() == TRUE)
-    {
-        if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
-        {
-            returnCode = ADDR_PARAMSIZEMISMATCH;
-        }
-    }
-
-    if (returnCode == ADDR_OK)
-    {
-        if (m_maxMetaBaseAlign != 0)
-        {
-            pOut->baseAlign = m_maxMetaBaseAlign;
-        }
-        else
-        {
-            returnCode = ADDR_NOTIMPLEMENTED;
-        }
+        returnCode = HwlGetMaxAlignments(pOut);
     }
 
     return returnCode;

src/amd/addrlib/core/addrlib.h

@@ -282,38 +282,14 @@ public:
 
     BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
 
-    ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
-
-    ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
+    ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
 
 protected:
     Lib();  // Constructor is protected
     Lib(const Client* pClient);
 
-    /// Pure virtual function to get max base alignments
-    virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0;
-
-    /// Gets maximum alignements for metadata
-    virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const
-    {
-        ADDR_NOT_IMPLEMENTED();
-
-        return 0;
-    }
-
-    VOID ValidBaseAlignments(UINT_32 alignment) const
-    {
-#if DEBUG
-        ADDR_ASSERT(alignment <= m_maxBaseAlign);
-#endif
-    }
-
-    VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const
-    {
-#if DEBUG
-        ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign);
-#endif
-    }
+    /// Pure virtual function to get max alignments
+    virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const = 0;
 
     //
     // Initialization
@@ -365,8 +341,6 @@ private:
 
     VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
 
-    VOID SetMaxAlignments();
-
 protected:
     LibClass    m_class;        ///< Store class type (HWL type)
 
@@ -396,10 +370,6 @@ protected:
 
     UINT_32     m_minPitchAlignPixels;  ///< Minimum pitch alignment in pixels
     UINT_32     m_maxSamples;           ///< Max numSamples
-
-    UINT_32     m_maxBaseAlign;         ///< Max base alignment for data surface
-    UINT_32     m_maxMetaBaseAlign;     ///< Max base alignment for metadata
-
 private:
     ElemLib*    m_pElemLib;             ///< Element Lib pointer
 };

src/amd/addrlib/core/addrlib1.cpp

@@ -428,8 +428,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
         }
     }
 
-    ValidBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -897,8 +895,6 @@ ADDR_E_RETURNCODE Lib::ComputeFmaskInfo(
         }
     }
 
-    ValidBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -1337,8 +1333,6 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
         }
     }
 
-    ValidMetaBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -1405,8 +1399,6 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
         }
     }
 
-    ValidMetaBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -1451,11 +1443,9 @@ ADDR_E_RETURNCODE Lib::ComputeDccInfo(
             pIn = &input;
         }
 
-        if (ret == ADDR_OK)
+        if (ADDR_OK == ret)
         {
             ret = HwlComputeDccInfo(pIn, pOut);
-
-            ValidMetaBaseAlignments(pOut->dccRamBaseAlign);
         }
     }
 
@@ -3662,7 +3652,7 @@ VOID Lib::OptimizeTileMode(
                         tileMode = (thickness == 1) ?
                                    ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
                     }
-                    else if ((thickness > 1) && (pInOut->flags.disallowLargeThickDegrade == 0))
+                    else if (thickness > 1)
                     {
                         // As in the following HwlComputeSurfaceInfo, thick modes may be degraded to
                         // thinner modes, we should re-evaluate whether the corresponding

src/amd/addrlib/core/addrlib2.cpp

@@ -295,8 +295,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
 
     ADDR_ASSERT(pOut->surfSize != 0);
 
-    ValidBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -449,8 +447,6 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
     else
     {
         returnCode = HwlComputeHtileInfo(pIn, pOut);
-
-        ValidMetaBaseAlignments(pOut->baseAlign);
     }
 
     return returnCode;
@@ -549,8 +545,6 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
     else
     {
         returnCode = HwlComputeCmaskInfo(pIn, pOut);
-
-        ValidMetaBaseAlignments(pOut->baseAlign);
     }
 
     return returnCode;
@@ -694,8 +688,6 @@ ADDR_E_RETURNCODE Lib::ComputeFmaskInfo(
         }
     }
 
-    ValidBaseAlignments(pOut->baseAlign);
-
     return returnCode;
 }
 
@@ -772,8 +764,6 @@ ADDR_E_RETURNCODE Lib::ComputeDccInfo(
     else
     {
         returnCode = HwlComputeDccInfo(pIn, pOut);
-
-        ValidMetaBaseAlignments(pOut->dccRamBaseAlign);
     }
 
     return returnCode;

src/amd/addrlib/core/addrlib2.h

@@ -480,6 +480,12 @@ protected:
         return HwlGetEquationIndex(pIn, pOut);
     }
 
+    virtual UINT_32 HwlComputeSurfaceBaseAlign(AddrSwizzleMode swizzleMode) const
+    {
+        ADDR_NOT_IMPLEMENTED();
+        return 0;
+    }
+
     virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
         const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
         ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT*      pOut) const

src/amd/addrlib/gfx9/gfx9addrlib.cpp

@@ -189,10 +189,10 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeHtileInfo(
 
     numCompressBlkPerMetaBlk = 1 << numCompressBlkPerMetaBlkLog2;
 
-    Dim3d   metaBlkDim   = {8, 8, 1};
+    Dim3d metaBlkDim = {8, 8, 1};
     UINT_32 totalAmpBits = numCompressBlkPerMetaBlkLog2;
-    UINT_32 widthAmp     = (pIn->numMipLevels > 1) ? (totalAmpBits >> 1) : RoundHalf(totalAmpBits);
-    UINT_32 heightAmp    = totalAmpBits - widthAmp;
+    UINT_32 widthAmp = (pIn->numMipLevels > 1) ? (totalAmpBits >> 1) : RoundHalf(totalAmpBits);
+    UINT_32 heightAmp = totalAmpBits - widthAmp;
     metaBlkDim.w <<= widthAmp;
     metaBlkDim.h <<= heightAmp;
 
@@ -221,42 +221,39 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeHtileInfo(
                    pIn->unalignedWidth, pIn->unalignedHeight, pIn->numSlices,
                    &numMetaBlkX, &numMetaBlkY, &numMetaBlkZ);
 
-    const UINT_32 metaBlkSize = numCompressBlkPerMetaBlk << 2;
-    UINT_32       align       = numPipeTotal * numRbTotal * m_pipeInterleaveBytes;
-
-    if ((IsXor(pIn->swizzleMode) == FALSE) && (numPipeTotal > 2))
-    {
-        align *= (numPipeTotal >> 1);
-    }
-
-    align = Max(align, metaBlkSize);
-
-    if (m_settings.metaBaseAlignFix)
-    {
-        align = Max(align, GetBlockSize(pIn->swizzleMode));
-    }
+    UINT_32 sizeAlign = numPipeTotal * numRbTotal * m_pipeInterleaveBytes;
 
     if (m_settings.htileAlignFix)
     {
-        const INT_32 metaBlkSizeLog2        = numCompressBlkPerMetaBlkLog2 + 2;
-        const INT_32 htileCachelineSizeLog2 = 11;
-        const INT_32 maxNumOfRbMaskBits     = 1 + Log2(numPipeTotal) + Log2(numRbTotal);
-
-        INT_32 rbMaskPadding = Max(0, htileCachelineSizeLog2 - (metaBlkSizeLog2 - maxNumOfRbMaskBits));
-
-        align <<= rbMaskPadding;
+        sizeAlign <<= 1;
     }
 
     pOut->pitch      = numMetaBlkX * metaBlkDim.w;
     pOut->height     = numMetaBlkY * metaBlkDim.h;
-    pOut->sliceSize  = numMetaBlkX * numMetaBlkY * metaBlkSize;
+    pOut->sliceSize  = numMetaBlkX * numMetaBlkY * numCompressBlkPerMetaBlk * 4;
 
-    pOut->metaBlkWidth       = metaBlkDim.w;
-    pOut->metaBlkHeight      = metaBlkDim.h;
+    pOut->metaBlkWidth = metaBlkDim.w;
+    pOut->metaBlkHeight = metaBlkDim.h;
     pOut->metaBlkNumPerSlice = numMetaBlkX * numMetaBlkY;
 
-    pOut->baseAlign  = align;
-    pOut->htileBytes = PowTwoAlign(pOut->sliceSize * numMetaBlkZ, align);
+    pOut->baseAlign = Max(numCompressBlkPerMetaBlk * 4, sizeAlign);
+
+    if (m_settings.metaBaseAlignFix)
+    {
+        pOut->baseAlign = Max(pOut->baseAlign, GetBlockSize(pIn->swizzleMode));
+    }
+
+    if ((IsXor(pIn->swizzleMode) == FALSE) && (numPipeTotal > 2))
+    {
+        UINT_32 additionalAlign = numPipeTotal * numCompressBlkPerMetaBlk * 2;
+
+        if (additionalAlign > sizeAlign)
+        {
+            sizeAlign = additionalAlign;
+        }
+    }
+
+    pOut->htileBytes = PowTwoAlign(pOut->sliceSize * numMetaBlkZ, sizeAlign);
 
     return ADDR_OK;
 }
@@ -336,17 +333,17 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeCmaskInfo(
 
     UINT_32 sizeAlign = numPipeTotal * numRbTotal * m_pipeInterleaveBytes;
 
-    if (m_settings.metaBaseAlignFix)
-    {
-        sizeAlign = Max(sizeAlign, GetBlockSize(pIn->swizzleMode));
-    }
-
     pOut->pitch      = numMetaBlkX * metaBlkDim.w;
     pOut->height     = numMetaBlkY * metaBlkDim.h;
     pOut->sliceSize  = (numMetaBlkX * numMetaBlkY * numCompressBlkPerMetaBlk) >> 1;
     pOut->cmaskBytes = PowTwoAlign(pOut->sliceSize * numMetaBlkZ, sizeAlign);
     pOut->baseAlign  = Max(numCompressBlkPerMetaBlk >> 1, sizeAlign);
 
+    if (m_settings.metaBaseAlignFix)
+    {
+        pOut->baseAlign = Max(pOut->baseAlign, GetBlockSize(pIn->swizzleMode));
+    }
+
     pOut->metaBlkWidth = metaBlkDim.w;
     pOut->metaBlkHeight = metaBlkDim.h;
 
@@ -641,16 +638,16 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeDccInfo(
             sizeAlign *= (numFrags / m_maxCompFrag);
         }
 
-        if (m_settings.metaBaseAlignFix)
-        {
-            sizeAlign = Max(sizeAlign, GetBlockSize(pIn->swizzleMode));
-        }
-
         pOut->dccRamSize = numMetaBlkX * numMetaBlkY * numMetaBlkZ *
                            numCompressBlkPerMetaBlk * numFrags;
         pOut->dccRamSize = PowTwoAlign(pOut->dccRamSize, sizeAlign);
         pOut->dccRamBaseAlign = Max(numCompressBlkPerMetaBlk, sizeAlign);
 
+        if (m_settings.metaBaseAlignFix)
+        {
+            pOut->dccRamBaseAlign = Max(pOut->dccRamBaseAlign, GetBlockSize(pIn->swizzleMode));
+        }
+
         pOut->pitch = numMetaBlkX * metaBlkDim.w;
         pOut->height = numMetaBlkY * metaBlkDim.h;
         pOut->depth = numMetaBlkZ * metaBlkDim.d;
@@ -673,78 +670,21 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeDccInfo(
 
 /**
 ************************************************************************************************************************
-*   Gfx9Lib::HwlComputeMaxBaseAlignments
+*   Gfx9Lib::HwlGetMaxAlignments
 *
 *   @brief
 *       Gets maximum alignments
 *   @return
-*       maximum alignments
+*       ADDR_E_RETURNCODE
 ************************************************************************************************************************
 */
-UINT_32 Gfx9Lib::HwlComputeMaxBaseAlignments() const
+ADDR_E_RETURNCODE Gfx9Lib::HwlGetMaxAlignments(
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut    ///< [out] output structure
+    ) const
 {
-    return ComputeSurfaceBaseAlignTiled(ADDR_SW_64KB);
-}
+    pOut->baseAlign = HwlComputeSurfaceBaseAlign(ADDR_SW_64KB);
 
-/**
-************************************************************************************************************************
-*   Gfx9Lib::HwlComputeMaxMetaBaseAlignments
-*
-*   @brief
-*       Gets maximum alignments for metadata
-*   @return
-*       maximum alignments for metadata
-************************************************************************************************************************
-*/
-UINT_32 Gfx9Lib::HwlComputeMaxMetaBaseAlignments() const
-{
-    // Max base alignment for Htile
-    const UINT_32 maxNumPipeTotal = GetPipeNumForMetaAddressing(TRUE, ADDR_SW_64KB_Z);
-    const UINT_32 maxNumRbTotal   = m_se * m_rbPerSe;
-
-    // If applyAliasFix was set, the extra bits should be MAX(10u, m_pipeInterleaveLog2),
-    // but we never saw any ASIC whose m_pipeInterleaveLog2 != 8, so just put an assertion and simply the logic.
-    ADDR_ASSERT((m_settings.applyAliasFix == FALSE) || (m_pipeInterleaveLog2 <= 10u));
-    const UINT_32 maxNumCompressBlkPerMetaBlk = 1u << (m_seLog2 + m_rbPerSeLog2 + 10u);
-
-    UINT_32 maxBaseAlignHtile = maxNumPipeTotal * maxNumRbTotal * m_pipeInterleaveBytes;
-
-    if (maxNumPipeTotal > 2)
-    {
-        maxBaseAlignHtile *= (maxNumPipeTotal >> 1);
-    }
-
-    maxBaseAlignHtile = Max(maxNumCompressBlkPerMetaBlk << 2, maxBaseAlignHtile);
-
-    if (m_settings.metaBaseAlignFix)
-    {
-        maxBaseAlignHtile = Max(maxBaseAlignHtile, GetBlockSize(ADDR_SW_64KB));
-    }
-
-    if (m_settings.htileAlignFix)
-    {
-        maxBaseAlignHtile *= maxNumPipeTotal;
-    }
-
-    // Max base alignment for Cmask will not be larger than that for Htile, no need to calculate
-
-    // Max base alignment for 2D Dcc will not be larger than that for 3D, no need to calculate
-    UINT_32 maxBaseAlignDcc3D = 65536;
-
-    if ((maxNumPipeTotal > 1) || (maxNumRbTotal > 1))
-    {
-        maxBaseAlignDcc3D = Min(m_se * m_rbPerSe * 262144, 65536 * 128u);
-    }
-
-    // Max base alignment for Msaa Dcc
-    UINT_32 maxBaseAlignDccMsaa = maxNumPipeTotal * maxNumRbTotal * m_pipeInterleaveBytes * (8 / m_maxCompFrag);
-
-    if (m_settings.metaBaseAlignFix)
-    {
-        maxBaseAlignDccMsaa = Max(maxBaseAlignDccMsaa, GetBlockSize(ADDR_SW_64KB));
-    }
-
-    return Max(maxBaseAlignHtile, Max(maxBaseAlignDccMsaa, maxBaseAlignDcc3D));
+    return ADDR_OK;
 }
 
 /**
@@ -784,11 +724,9 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeCmaskAddrFromCoord(
         UINT_32 metaBlkWidthLog2      = Log2(output.metaBlkWidth);
         UINT_32 metaBlkHeightLog2     = Log2(output.metaBlkHeight);
 
-        MetaEqParams metaEqParams = {0, fmaskElementBytesLog2, 0, pIn->cMaskFlags,
-                                     Gfx9DataFmask, pIn->swizzleMode, pIn->resourceType,
-                                     metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0};
-
-        const CoordEq* pMetaEq = GetMetaEquation(metaEqParams);
+        const CoordEq* pMetaEq = GetMetaEquation({0, fmaskElementBytesLog2, 0, pIn->cMaskFlags,
+                                                  Gfx9DataFmask, pIn->swizzleMode, pIn->resourceType,
+                                                  metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0});
 
         UINT_32 xb = pIn->x / output.metaBlkWidth;
         UINT_32 yb = pIn->y / output.metaBlkHeight;
@@ -860,11 +798,9 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeHtileAddrFromCoord(
             UINT_32 metaBlkHeightLog2 = Log2(output.metaBlkHeight);
             UINT_32 numSamplesLog2    = Log2(pIn->numSamples);
 
-            MetaEqParams metaEqParams = {0, elementBytesLog2, numSamplesLog2, pIn->hTileFlags,
-                                         Gfx9DataDepthStencil, pIn->swizzleMode, ADDR_RSRC_TEX_2D,
-                                         metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0};
-
-            const CoordEq* pMetaEq = GetMetaEquation(metaEqParams);
+            const CoordEq* pMetaEq = GetMetaEquation({0, elementBytesLog2, numSamplesLog2, pIn->hTileFlags,
+                                                      Gfx9DataDepthStencil, pIn->swizzleMode, ADDR_RSRC_TEX_2D,
+                                                      metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0});
 
             UINT_32 xb = pIn->x / output.metaBlkWidth;
             UINT_32 yb = pIn->y / output.metaBlkHeight;
@@ -934,11 +870,9 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeHtileCoordFromAddr(
             UINT_32 metaBlkHeightLog2 = Log2(output.metaBlkHeight);
             UINT_32 numSamplesLog2    = Log2(pIn->numSamples);
 
-            MetaEqParams metaEqParams = {0, elementBytesLog2, numSamplesLog2, pIn->hTileFlags,
-                                         Gfx9DataDepthStencil, pIn->swizzleMode, ADDR_RSRC_TEX_2D,
-                                         metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0};
-
-            const CoordEq* pMetaEq = GetMetaEquation(metaEqParams);
+            const CoordEq* pMetaEq = GetMetaEquation({0, elementBytesLog2, numSamplesLog2, pIn->hTileFlags,
+                                                      Gfx9DataDepthStencil, pIn->swizzleMode, ADDR_RSRC_TEX_2D,
+                                                      metaBlkWidthLog2, metaBlkHeightLog2, 0, 3, 3, 0});
 
             UINT_32 numPipeBits = GetPipeLog2ForMetaAddressing(pIn->hTileFlags.pipeAligned,
                                                                pIn->swizzleMode);
@@ -1014,12 +948,10 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeDccAddrFromCoord(
             UINT_32 compBlkHeightLog2 = Log2(output.compressBlkHeight);
             UINT_32 compBlkDepthLog2  = Log2(output.compressBlkDepth);
 
-            MetaEqParams metaEqParams = {pIn->mipId, elementBytesLog2, numSamplesLog2, pIn->dccKeyFlags,
-                                         Gfx9DataColor, pIn->swizzleMode, pIn->resourceType,
-                                         metaBlkWidthLog2, metaBlkHeightLog2, metaBlkDepthLog2,
-                                         compBlkWidthLog2, compBlkHeightLog2, compBlkDepthLog2};
-
-            const CoordEq* pMetaEq = GetMetaEquation(metaEqParams);
+            const CoordEq* pMetaEq = GetMetaEquation({pIn->mipId, elementBytesLog2, numSamplesLog2, pIn->dccKeyFlags,
+                                                      Gfx9DataColor, pIn->swizzleMode, pIn->resourceType,
+                                                      metaBlkWidthLog2, metaBlkHeightLog2, metaBlkDepthLog2,
+                                                      compBlkWidthLog2, compBlkHeightLog2, compBlkDepthLog2});
 
             UINT_32 xb = pIn->x / output.metaBlkWidth;
             UINT_32 yb = pIn->y / output.metaBlkHeight;
@@ -1123,10 +1055,6 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
                 break;
         }
 
-        // Addr::V2::Lib::ComputePipeBankXor()/ComputeSlicePipeBankXor() requires pipe interleave to be exactly 8 bits,
-        // and any larger value requires a post-process (left shift) on the output pipeBankXor bits.
-        ADDR_ASSERT(m_pipeInterleaveBytes == ADDR_PIPEINTERLEAVE_256B);
-
         switch (gbAddrConfig.bits.NUM_BANKS)
         {
             case ADDR_CONFIG_1_BANK:
@@ -1223,19 +1151,6 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
         ADDR_ASSERT((m_blockVarSizeLog2 == 0) ||
                     ((m_blockVarSizeLog2 >= 17u) && (m_blockVarSizeLog2 <= 20u)));
         m_blockVarSizeLog2 = Min(Max(17u, m_blockVarSizeLog2), 20u);
-
-        if ((m_rbPerSeLog2 == 1) &&
-            (((m_pipesLog2 == 1) && ((m_seLog2 == 2) || (m_seLog2 == 3))) ||
-             ((m_pipesLog2 == 2) && ((m_seLog2 == 1) || (m_seLog2 == 2)))))
-        {
-            ADDR_ASSERT(m_settings.isVega10 == FALSE);
-            ADDR_ASSERT(m_settings.isRaven == FALSE);
-
-            if (m_settings.isVega12)
-            {
-                m_settings.htileCacheRbConflict = 1;
-            }
-        }
     }
     else
     {
@@ -1272,7 +1187,6 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
         case FAMILY_AI:
             m_settings.isArcticIsland = 1;
             m_settings.isVega10    = ASICREV_IS_VEGA10_P(uChipRevision);
-            m_settings.isVega12    = ASICREV_IS_VEGA12_P(uChipRevision);
 
             m_settings.isDce12 = 1;
 
@@ -3365,11 +3279,10 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting(
             addrPreferredSwSet.value = AddrSwSetZ;
             addrValidSwSet.value     = AddrSwSetZ;
 
-            if (pIn->flags.noMetadata == FALSE)
+            if (pIn->flags.depth && pIn->flags.texture)
             {
-                if (pIn->flags.depth &&
-                    pIn->flags.texture &&
-                    (((bpp == 16) && (numFrags >= 4)) || ((bpp == 32) && (numFrags >= 2))))
+                if (((bpp == 16) && (numFrags >= 4)) ||
+                    ((bpp == 32) && (numFrags >= 2)))
                 {
                     // When _X/_T swizzle mode was used for MSAA depth texture, TC will get zplane
                     // equation from wrong address within memory range a tile covered and use the
@@ -3377,16 +3290,6 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting(
                     pOut->canXor = FALSE;
                     prtXor       = FALSE;
                 }
-
-                if (m_settings.htileCacheRbConflict &&
-                    (pIn->flags.depth || pIn->flags.stencil) &&
-                    (slice > 1) &&
-                    (pIn->flags.metaRbUnaligned == FALSE) &&
-                    (pIn->flags.metaPipeUnaligned == FALSE))
-                {
-                    // Z_X 2D array with Rb/Pipe aligned HTile won't have metadata cache coherency
-                    pOut->canXor = FALSE;
-                }
             }
         }
         else if (ElemLib::IsBlockCompressed(pIn->format))
@@ -3499,12 +3402,12 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting(
                         if (pIn->bpp == 64)
                         {
                             addrPreferredSwSet.value = AddrSwSetD;
-                            addrValidSwSet.value     = AddrSwSetS | AddrSwSetD;
+                            addrValidSwSet.value     = AddrSwSetD;
                         }
                         else
                         {
                             addrPreferredSwSet.value = AddrSwSetS;
-                            addrValidSwSet.value     = AddrSwSetS;
+                            addrValidSwSet.value     = AddrSwSetS | AddrSwSetD;
                         }
 
                         blockSet.micro = FALSE;
@@ -4134,7 +4037,7 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeSurfaceInfoTiled(
             pOut->sliceSize = static_cast<UINT_64>(pOut->mipChainPitch) * pOut->mipChainHeight *
                               (pIn->bpp >> 3) * pIn->numFrags;
             pOut->surfSize  = pOut->sliceSize * pOut->mipChainSlice;
-            pOut->baseAlign = ComputeSurfaceBaseAlignTiled(pIn->swizzleMode);
+            pOut->baseAlign = HwlComputeSurfaceBaseAlign(pIn->swizzleMode);
 
             if (pIn->flags.prt)
             {
@@ -4859,12 +4762,15 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeSurfaceAddrFromCoordTiled(
             UINT_32 pitchInMacroBlock = localOut.mipChainPitch / localOut.blockWidth;
             UINT_32 paddedHeightInMacroBlock = localOut.mipChainHeight / localOut.blockHeight;
             UINT_32 sliceSizeInMacroBlock = pitchInMacroBlock * paddedHeightInMacroBlock;
-            UINT_64 macroBlockIndex =
+            UINT_32 macroBlockIndex =
                 (pIn->slice + mipStartPos.d) * sliceSizeInMacroBlock +
                 ((pIn->y / localOut.blockHeight) + mipStartPos.h) * pitchInMacroBlock +
                 ((pIn->x / localOut.blockWidth) + mipStartPos.w);
 
-            pOut->addr = blockOffset | (macroBlockIndex << log2blkSize);
+            UINT_64 macroBlockOffset = (static_cast<UINT_64>(macroBlockIndex) <<
+                                       GetBlockSizeLog2(pIn->swizzleMode));
+
+            pOut->addr = blockOffset | macroBlockOffset;
         }
         else
         {
@@ -4929,7 +4835,7 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeSurfaceAddrFromCoordTiled(
             UINT_32 pitchInBlock = localOut.mipChainPitch / localOut.blockWidth;
             UINT_32 sliceSizeInBlock =
                 (localOut.mipChainHeight / localOut.blockHeight) * pitchInBlock;
-            UINT_64 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
+            UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
 
             pOut->addr = blockOffset | (blockIndex << log2blkSize);
         }

src/amd/addrlib/gfx9/gfx9addrlib.h

@@ -55,19 +55,19 @@ struct Gfx9ChipSettings
         UINT_32 isArcticIsland      : 1;
         UINT_32 isVega10            : 1;
         UINT_32 isRaven             : 1;
-        UINT_32 isVega12            : 1;
+        UINT_32 reserved0           : 29;
 
         // Display engine IP version name
         UINT_32 isDce12             : 1;
         UINT_32 isDcn1              : 1;
+        UINT_32 reserved1           : 29;
 
         // Misc configuration bits
         UINT_32 metaBaseAlignFix    : 1;
         UINT_32 depthPipeXorDisable : 1;
         UINT_32 htileAlignFix       : 1;
         UINT_32 applyAliasFix       : 1;
-        UINT_32 htileCacheRbConflict: 1;
-        UINT_32 reserved2           : 27;
+        UINT_32 reserved2           : 28;
     };
 };
 
@@ -121,6 +121,9 @@ public:
         return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
     }
 
+    virtual BOOL_32 IsValidDisplaySwizzleMode(
+        const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
+
 protected:
     Gfx9Lib(const Client* pClient);
     virtual ~Gfx9Lib();
@@ -221,7 +224,7 @@ protected:
         AddrSwizzleMode swMode,
         UINT_32 elementBytesLog2) const;
 
-    UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const
+    virtual UINT_32 HwlComputeSurfaceBaseAlign(AddrSwizzleMode swizzleMode) const
     {
         UINT_32 baseAlign;
 
@@ -397,11 +400,11 @@ protected:
     static const UINT_32    MaxCachedMetaEq = 2;
 
 private:
-    virtual UINT_32 HwlComputeMaxBaseAlignments() const;
+    virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(
+        ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
 
-    virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
-
-    virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
+    virtual BOOL_32 HwlInitGlobalParams(
+        const ADDR_CREATE_INPUT* pCreateIn);
 
     VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const;
 
@@ -431,8 +434,6 @@ private:
                         UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
                         UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
 
-    BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
-
     ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
         UINT_32*                                pMipmap0PaddedWidth,

src/amd/addrlib/r800/ciaddrlib.cpp

@@ -401,7 +401,6 @@ ChipFamily CiLib::HwlConvertChipFamily(
             m_settings.isPolaris10       = ASICREV_IS_POLARIS10_P(uChipRevision);
             m_settings.isPolaris11       = ASICREV_IS_POLARIS11_M(uChipRevision);
             m_settings.isPolaris12       = ASICREV_IS_POLARIS12_V(uChipRevision);
-            m_settings.isVegaM           = ASICREV_IS_VEGAM_P(uChipRevision);
             family = ADDR_CHIP_FAMILY_VI;
             break;
         case FAMILY_CZ:
@@ -471,10 +470,6 @@ BOOL_32 CiLib::HwlInitGlobalParams(
     {
         m_pipes = 4;
     }
-    else if (m_settings.isVegaM)
-    {
-        m_pipes = 16;
-    }
 
     if (valid)
     {
@@ -741,7 +736,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
 
                 SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
 
-                ADDR_ASSERT((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex));
+                ADDR_ASSERT(((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex)) || pOut->tileIndex == Depth1DThinIndex);
 
                 depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
             }
@@ -2162,27 +2157,29 @@ VOID CiLib::HwlPadDimensions(
 
 /**
 ****************************************************************************************************
-*   CiLib::HwlComputeMaxBaseAlignments
+*   CiLib::HwlGetMaxAlignments
 *
 *   @brief
 *       Gets maximum alignments
 *   @return
-*       maximum alignments
+*       ADDR_E_RETURNCODE
 ****************************************************************************************************
 */
-UINT_32 CiLib::HwlComputeMaxBaseAlignments() const
+ADDR_E_RETURNCODE CiLib::HwlGetMaxAlignments(
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut    ///< [out] output structure
+    ) const
 {
     const UINT_32 pipes = HwlGetPipes(&m_tileTable[0].info);
 
     // Initial size is 64 KiB for PRT.
-    UINT_32 maxBaseAlign = 64 * 1024;
+    UINT_64 maxBaseAlign = 64 * 1024;
 
     for (UINT_32 i = 0; i < m_noOfMacroEntries; i++)
     {
         // The maximum tile size is 16 byte-per-pixel and either 8-sample or 8-slice.
         UINT_32 tileSize = m_macroTileTable[i].tileSplitBytes;
 
-        UINT_32 baseAlign = tileSize * pipes * m_macroTileTable[i].banks *
+        UINT_64 baseAlign = tileSize * pipes * m_macroTileTable[i].banks *
                             m_macroTileTable[i].bankWidth * m_macroTileTable[i].bankHeight;
 
         if (baseAlign > maxBaseAlign)
@@ -2191,32 +2188,12 @@ UINT_32 CiLib::HwlComputeMaxBaseAlignments() const
         }
     }
 
-    return maxBaseAlign;
-}
-
-/**
-****************************************************************************************************
-*   CiLib::HwlComputeMaxMetaBaseAlignments
-*
-*   @brief
-*       Gets maximum alignments for metadata
-*   @return
-*       maximum alignments for metadata
-****************************************************************************************************
-*/
-UINT_32 CiLib::HwlComputeMaxMetaBaseAlignments() const
-{
-    UINT_32 maxBank = 1;
-
-    for (UINT_32 i = 0; i < m_noOfMacroEntries; i++)
+    if (pOut != NULL)
     {
-        if ((m_settings.isVolcanicIslands) && IsMacroTiled(m_tileTable[i].mode))
-        {
-            maxBank = Max(maxBank, m_macroTileTable[i].banks);
-        }
+        pOut->baseAlign = maxBaseAlign;
     }
 
-    return SiLib::HwlComputeMaxMetaBaseAlignments() * maxBank;
+    return ADDR_OK;
 }
 
 /**

src/amd/addrlib/r800/ciaddrlib.h

@@ -137,9 +137,7 @@ protected:
         const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*  pIn,
         ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*       pOut) const;
 
-    virtual UINT_32 HwlComputeMaxBaseAlignments() const;
-
-    virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
+    virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
 
     virtual VOID HwlPadDimensions(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,

src/amd/addrlib/r800/egbaddrlib.cpp

@@ -100,13 +100,11 @@ BOOL_32 EgBasedLib::DispatchComputeSurfaceInfo(
 
     ADDR_TILEINFO       tileInfoDef   = {0};
     ADDR_TILEINFO*      pTileInfo     = &tileInfoDef;
-    UINT_32             padDims       = 0;
+
+    UINT_32             padDims = 0;
     BOOL_32             valid;
 
-    if (pIn->flags.disallowLargeThickDegrade == 0)
-    {
-        tileMode = DegradeLargeThickTile(tileMode, bpp);
-    }
+    tileMode = DegradeLargeThickTile(tileMode, bpp);
 
     // Only override numSamples for NI above
     if (m_chipFamily >= ADDR_CHIP_FAMILY_NI)

src/amd/addrlib/r800/siaddrlib.cpp

@@ -611,29 +611,6 @@ ADDR_E_RETURNCODE SiLib::ComputePipeEquation(
             break;
     }
 
-    if (m_settings.isVegaM && (pEquation->numBits == 4))
-    {
-        ADDR_CHANNEL_SETTING addeMsb = pAddr[0];
-        ADDR_CHANNEL_SETTING xor1Msb = pXor1[0];
-        ADDR_CHANNEL_SETTING xor2Msb = pXor2[0];
-
-        pAddr[0] = pAddr[1];
-        pXor1[0] = pXor1[1];
-        pXor2[0] = pXor2[1];
-
-        pAddr[1] = pAddr[2];
-        pXor1[1] = pXor1[2];
-        pXor2[1] = pXor2[2];
-
-        pAddr[2] = pAddr[3];
-        pXor1[2] = pXor1[3];
-        pXor2[2] = pXor2[3];
-
-        pAddr[3] = addeMsb;
-        pXor1[3] = xor1Msb;
-        pXor2[3] = xor2Msb;
-    }
-
     for (UINT_32 i = 0; i < pEquation->numBits; i++)
     {
         if (pAddr[i].value == 0)
@@ -777,16 +754,6 @@ UINT_32 SiLib::ComputePipeFromCoord(
             ADDR_UNHANDLED_CASE();
             break;
     }
-
-    if (m_settings.isVegaM && (numPipes == 16))
-    {
-        UINT_32 pipeMsb = pipeBit0;
-        pipeBit0 = pipeBit1;
-        pipeBit1 = pipeBit2;
-        pipeBit2 = pipeBit3;
-        pipeBit3 = pipeMsb;
-    }
-
     pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
 
     UINT_32 microTileThickness = Thickness(tileMode);
@@ -3501,20 +3468,22 @@ VOID SiLib::HwlSelectTileMode(
 
 /**
 ****************************************************************************************************
-*   SiLib::HwlComputeMaxBaseAlignments
+*   SiLib::HwlGetMaxAlignments
 *
 *   @brief
 *       Gets maximum alignments
 *   @return
-*       maximum alignments
+*       ADDR_E_RETURNCODE
 ****************************************************************************************************
 */
-UINT_32 SiLib::HwlComputeMaxBaseAlignments() const
+ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments(
+    ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut    ///< [out] output structure
+    ) const
 {
     const UINT_32 pipes = HwlGetPipes(&m_tileTable[0].info);
 
     // Initial size is 64 KiB for PRT.
-    UINT_32 maxBaseAlign = 64 * 1024;
+    UINT_64 maxBaseAlign = 64 * 1024;
 
     for (UINT_32 i = 0; i < m_noOfEntries; i++)
     {
@@ -3525,7 +3494,7 @@ UINT_32 SiLib::HwlComputeMaxBaseAlignments() const
             UINT_32 tileSize = Min(m_tileTable[i].info.tileSplitBytes,
                                    MicroTilePixels * 8 * 16);
 
-            UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks *
+            UINT_64 baseAlign = tileSize * pipes * m_tileTable[i].info.banks *
                                 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight;
 
             if (baseAlign > maxBaseAlign)
@@ -3535,29 +3504,12 @@ UINT_32 SiLib::HwlComputeMaxBaseAlignments() const
         }
     }
 
-    return maxBaseAlign;
-}
-
-/**
-****************************************************************************************************
-*   SiLib::HwlComputeMaxMetaBaseAlignments
-*
-*   @brief
-*       Gets maximum alignments for metadata
-*   @return
-*       maximum alignments for metadata
-****************************************************************************************************
-*/
-UINT_32 SiLib::HwlComputeMaxMetaBaseAlignments() const
-{
-    UINT_32 maxPipe = 1;
-
-    for (UINT_32 i = 0; i < m_noOfEntries; i++)
+    if (pOut != NULL)
     {
-        maxPipe = Max(maxPipe, HwlGetPipes(&m_tileTable[i].info));
+        pOut->baseAlign = maxBaseAlign;
     }
 
-    return m_pipeInterleaveBytes * maxPipe;
+    return ADDR_OK;
 }
 
 /**

src/amd/addrlib/r800/siaddrlib.h

@@ -87,7 +87,6 @@ struct SiChipSettings
     UINT_32 isPolaris10       : 1;
     UINT_32 isPolaris11       : 1;
     UINT_32 isPolaris12       : 1;
-    UINT_32 isVegaM           : 1;
     // VI fusion
     UINT_32 isCarrizo         : 1;
 };
@@ -264,9 +263,7 @@ protected:
         return TRUE;
     }
 
-    virtual UINT_32 HwlComputeMaxBaseAlignments() const;
-
-    virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
+    virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
 
     virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
         AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,

src/amd/common/ac_debug.c

@@ -761,7 +761,7 @@ unsigned ac_get_wave_info(struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP])
 	char line[2000];
 	unsigned num_waves = 0;
 
-	FILE *p = popen("umr -O halt_waves -wa", "r");
+	FILE *p = popen("umr -wa", "r");
 	if (!p)
 		return 0;
 

src/amd/common/ac_gpu_info.c

@@ -99,9 +99,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	struct amdgpu_buffer_size_alignments alignment_info = {};
 	struct amdgpu_heap_info vram, vram_vis, gtt;
 	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+	struct drm_amdgpu_info_hw_ip vce = {}, vcn_dec = {};
 	struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
-	struct amdgpu_gds_resource_info gds = {};
 	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 	int r, i, j;
 	drmDevicePtr devinfo;
@@ -175,14 +174,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		return false;
 	}
 
-	if (info->drm_major == 3 && info->drm_minor >= 17) {
-		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
-		if (r) {
-			fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
-			return false;
-		}
-	}
-
 	if (info->drm_major == 3 && info->drm_minor >= 17) {
 		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 		if (r) {
@@ -243,18 +234,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		return false;
 	}
 
-	r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
-	if (r) {
-		fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
-		return false;
-	}
-
-	r = amdgpu_query_gds_info(dev, &gds);
-	if (r) {
-		fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
-		return false;
-	}
-
 	/* Set chip identification. */
 	info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 	info->vce_harvest_config = amdinfo->vce_harvest_config;
@@ -290,8 +269,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->gart_size = gtt.heap_size;
 	info->vram_size = vram.heap_size;
 	info->vram_vis_size = vram_vis.heap_size;
-	info->gds_size = gds.gds_total_size;
-	info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
 	/* The kernel can split large buffers in VRAM but not in GTT, so large
 	 * allocations can fail or cause buffer movement failures in the kernel.
 	 */
@@ -306,16 +283,11 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		uvd.available_rings ? uvd_version : 0;
 	info->vce_fw_version =
 		vce.available_rings ? vce_version : 0;
-	info->uvd_enc_supported =
-		uvd_enc.available_rings ? true : false;
 	info->has_userptr = true;
 	info->has_syncobj = has_syncobj(fd);
 	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 	info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 	info->has_ctx_priority = info->drm_minor >= 22;
-	/* TODO: Enable this once the kernel handles it efficiently. */
-	info->has_local_buffers = info->drm_minor >= 20 &&
-				  !info->has_dedicated_vram;
 	info->num_render_backends = amdinfo->rb_pipes;
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
@@ -323,7 +295,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		info->clock_crystal_freq = 1;
 	}
 	info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
-	info->gb_addr_config = amdinfo->gb_addr_cfg;
 	if (info->chip_class == GFX9) {
 		info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 		info->pipe_interleave_bytes =
@@ -333,10 +304,10 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		info->pipe_interleave_bytes =
 			256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 	}
-	info->r600_has_virtual_memory = true;
+	info->has_virtual_memory = true;
 
-	assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
-	assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
+	assert(util_is_power_of_two(dma.available_rings + 1));
+	assert(util_is_power_of_two(compute.available_rings + 1));
 
 	info->num_sdma_rings = util_bitcount(dma.available_rings);
 	info->num_compute_rings = util_bitcount(compute.available_rings);
@@ -366,11 +337,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	ib_align = MAX2(ib_align, compute.ib_start_alignment);
 	ib_align = MAX2(ib_align, dma.ib_start_alignment);
 	ib_align = MAX2(ib_align, uvd.ib_start_alignment);
-	ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
 	ib_align = MAX2(ib_align, vce.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
-       assert(ib_align);
 	info->ib_start_alignment = ib_align;
 
 	return true;
@@ -406,118 +375,55 @@ void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
 
 void ac_print_gpu_info(struct radeon_info *info)
 {
-	printf("Device info:\n");
-	printf("    pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
+	printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
 	       info->pci_domain, info->pci_bus,
 	       info->pci_dev, info->pci_func);
-	printf("    pci_id = 0x%x\n", info->pci_id);
-	printf("    family = %i\n", info->family);
-	printf("    chip_class = %i\n", info->chip_class);
-	printf("    num_compute_rings = %u\n", info->num_compute_rings);
-	printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
-	printf("    clock_crystal_freq = %i\n", info->clock_crystal_freq);
-	printf("    tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
-
-	printf("Memory info:\n");
-	printf("    pte_fragment_size = %u\n", info->pte_fragment_size);
-	printf("    gart_page_size = %u\n", info->gart_page_size);
-	printf("    gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
-	printf("    vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
-	printf("    vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
-	printf("    gds_size = %u kB\n", info->gds_size / 1024);
-	printf("    gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
-	printf("    max_alloc_size = %i MB\n",
+	printf("pci_id = 0x%x\n", info->pci_id);
+	printf("family = %i\n", info->family);
+	printf("chip_class = %i\n", info->chip_class);
+	printf("pte_fragment_size = %u\n", info->pte_fragment_size);
+	printf("gart_page_size = %u\n", info->gart_page_size);
+	printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
+	printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
+	printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
+	printf("max_alloc_size = %i MB\n",
 	       (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
-	printf("    min_alloc_size = %u\n", info->min_alloc_size);
-	printf("    address32_hi = %u\n", info->address32_hi);
-	printf("    has_dedicated_vram = %u\n", info->has_dedicated_vram);
-
-	printf("CP info:\n");
-	printf("    gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
-	printf("    ib_start_alignment = %u\n", info->ib_start_alignment);
-	printf("    me_fw_version = %i\n", info->me_fw_version);
-	printf("    me_fw_feature = %i\n", info->me_fw_feature);
-	printf("    pfp_fw_version = %i\n", info->pfp_fw_version);
-	printf("    pfp_fw_feature = %i\n", info->pfp_fw_feature);
-	printf("    ce_fw_version = %i\n", info->ce_fw_version);
-	printf("    ce_fw_feature = %i\n", info->ce_fw_feature);
-
-	printf("Multimedia info:\n");
-	printf("    has_hw_decode = %u\n", info->has_hw_decode);
-	printf("    uvd_enc_supported = %u\n", info->uvd_enc_supported);
-	printf("    uvd_fw_version = %u\n", info->uvd_fw_version);
-	printf("    vce_fw_version = %u\n", info->vce_fw_version);
-	printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
-
-	printf("Kernel info:\n");
-	printf("    drm = %i.%i.%i\n", info->drm_major,
+	printf("min_alloc_size = %u\n", info->min_alloc_size);
+	printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
+	printf("has_virtual_memory = %i\n", info->has_virtual_memory);
+	printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
+	printf("has_hw_decode = %u\n", info->has_hw_decode);
+	printf("num_sdma_rings = %i\n", info->num_sdma_rings);
+	printf("num_compute_rings = %u\n", info->num_compute_rings);
+	printf("uvd_fw_version = %u\n", info->uvd_fw_version);
+	printf("vce_fw_version = %u\n", info->vce_fw_version);
+	printf("me_fw_version = %i\n", info->me_fw_version);
+	printf("me_fw_feature = %i\n", info->me_fw_feature);
+	printf("pfp_fw_version = %i\n", info->pfp_fw_version);
+	printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
+	printf("ce_fw_version = %i\n", info->ce_fw_version);
+	printf("ce_fw_feature = %i\n", info->ce_fw_feature);
+	printf("vce_harvest_config = %i\n", info->vce_harvest_config);
+	printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
+	printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+	printf("drm = %i.%i.%i\n", info->drm_major,
 	       info->drm_minor, info->drm_patchlevel);
-	printf("    has_userptr = %i\n", info->has_userptr);
-	printf("    has_syncobj = %u\n", info->has_syncobj);
-	printf("    has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
-	printf("    has_fence_to_handle = %u\n", info->has_fence_to_handle);
-	printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
-	printf("    has_local_buffers = %u\n", info->has_local_buffers);
+	printf("has_userptr = %i\n", info->has_userptr);
+	printf("has_syncobj = %u\n", info->has_syncobj);
+	printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
 
-	printf("Shader core info:\n");
-	printf("    max_shader_clock = %i\n", info->max_shader_clock);
-	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
-	printf("    max_se = %i\n", info->max_se);
-	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
+	printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
+	printf("max_shader_clock = %i\n", info->max_shader_clock);
+	printf("num_good_compute_units = %i\n", info->num_good_compute_units);
+	printf("max_se = %i\n", info->max_se);
+	printf("max_sh_per_se = %i\n", info->max_sh_per_se);
 
-	printf("Render backend info:\n");
-	printf("    num_render_backends = %i\n", info->num_render_backends);
-	printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
-	printf("    pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
-	printf("    enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
-	printf("    max_alignment = %u\n", (unsigned)info->max_alignment);
-
-	printf("GB_ADDR_CONFIG:\n");
-	if (info->chip_class >= GFX9) {
-		printf("    num_pipes = %u\n",
-		       1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
-		printf("    pipe_interleave_size = %u\n",
-		       256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
-		printf("    max_compressed_frags = %u\n",
-		       1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
-		printf("    bank_interleave_size = %u\n",
-		       1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
-		printf("    num_banks = %u\n",
-		       1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
-		printf("    shader_engine_tile_size = %u\n",
-		       16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
-		printf("    num_shader_engines = %u\n",
-		       1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
-		printf("    num_gpus = %u (raw)\n",
-		       G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
-		printf("    multi_gpu_tile_size = %u (raw)\n",
-		       G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
-		printf("    num_rb_per_se = %u\n",
-		       1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
-		printf("    row_size = %u\n",
-		       1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
-		printf("    num_lower_pipes = %u (raw)\n",
-		       G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
-		printf("    se_enable = %u (raw)\n",
-		       G_0098F8_SE_ENABLE(info->gb_addr_config));
-	} else {
-		printf("    num_pipes = %u\n",
-		       1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
-		printf("    pipe_interleave_size = %u\n",
-		       256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
-		printf("    bank_interleave_size = %u\n",
-		       1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
-		printf("    num_shader_engines = %u\n",
-		       1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
-		printf("    shader_engine_tile_size = %u\n",
-		       16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
-		printf("    num_gpus = %u (raw)\n",
-		       G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
-		printf("    multi_gpu_tile_size = %u (raw)\n",
-		       G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
-		printf("    row_size = %u\n",
-		       1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
-		printf("    num_lower_pipes = %u (raw)\n",
-		       G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
-	}
+	printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
+	printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid);
+	printf("r600_num_banks = %i\n", info->r600_num_banks);
+	printf("num_render_backends = %i\n", info->num_render_backends);
+	printf("num_tile_pipes = %i\n", info->num_tile_pipes);
+	printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
+	printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
+	printf("max_alignment = %u\n", (unsigned)info->max_alignment);
 }

src/amd/common/ac_gpu_info.h

@@ -50,41 +50,31 @@ struct radeon_info {
 	uint32_t                    pci_id;
 	enum radeon_family          family;
 	enum chip_class             chip_class;
-	uint32_t                    num_compute_rings;
-	uint32_t                    num_sdma_rings;
-	uint32_t                    clock_crystal_freq;
-	uint32_t                    tcc_cache_line_size;
-
-	/* Memory info. */
 	uint32_t                    pte_fragment_size;
 	uint32_t                    gart_page_size;
 	uint64_t                    gart_size;
 	uint64_t                    vram_size;
 	uint64_t                    vram_vis_size;
-	unsigned                    gds_size;
-	unsigned                    gds_gfx_partition_size;
 	uint64_t                    max_alloc_size;
 	uint32_t                    min_alloc_size;
-	uint32_t                    address32_hi;
 	bool                        has_dedicated_vram;
-	bool                        r600_has_virtual_memory;
-
-	/* CP info. */
+	bool                        has_virtual_memory;
 	bool                        gfx_ib_pad_with_type2;
+	bool                        has_hw_decode;
 	unsigned                    ib_start_alignment;
+	uint32_t                    num_sdma_rings;
+	uint32_t                    num_compute_rings;
+	uint32_t                    uvd_fw_version;
+	uint32_t                    vce_fw_version;
 	uint32_t                    me_fw_version;
 	uint32_t                    me_fw_feature;
 	uint32_t                    pfp_fw_version;
 	uint32_t                    pfp_fw_feature;
 	uint32_t                    ce_fw_version;
 	uint32_t                    ce_fw_feature;
-
-	/* Multimedia info. */
-	bool                        has_hw_decode;
-	bool                        uvd_enc_supported;
-	uint32_t                    uvd_fw_version;
-	uint32_t                    vce_fw_version;
 	uint32_t                    vce_harvest_config;
+	uint32_t                    clock_crystal_freq;
+	uint32_t                    tcc_cache_line_size;
 
 	/* Kernel info. */
 	uint32_t                    drm_major; /* version */
@@ -95,7 +85,6 @@ struct radeon_info {
 	bool                        has_syncobj_wait_for_submit;
 	bool                        has_fence_to_handle;
 	bool                        has_ctx_priority;
-	bool                        has_local_buffers;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
@@ -110,13 +99,12 @@ struct radeon_info {
 	uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 	bool                        r600_gb_backend_map_valid;
 	uint32_t                    r600_num_banks;
-	uint32_t                    gb_addr_config;
 	uint32_t                    num_render_backends;
 	uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 	uint32_t                    pipe_interleave_bytes;
 	uint32_t                    enabled_rb_mask; /* GCN harvest config */
-	uint64_t                    max_alignment; /* from addrlib */
 
+	uint64_t                    max_alignment; /* from addrlib */
 	/* Tile modes. */
 	uint32_t                    si_tile_mode_array[32];
 	uint32_t                    cik_macrotile_mode_array[16];

src/amd/common/ac_llvm_build.h

@@ -27,24 +27,17 @@
 
 #include <stdbool.h>
 #include <llvm-c/TargetMachine.h>
-#include "compiler/nir/nir.h"
+
 #include "amd_family.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define HAVE_32BIT_POINTERS (HAVE_LLVM >= 0x0700)
-
 enum {
-	/* CONST is the only address space that selects SMEM loads */
-	AC_CONST_ADDR_SPACE = HAVE_LLVM >= 0x700 ? 4 : 2,
 	AC_LOCAL_ADDR_SPACE = 3,
-	AC_CONST_32BIT_ADDR_SPACE = 6, /* same as CONST, but the pointer type has 32 bits */
 };
 
-struct ac_llvm_flow;
-
 struct ac_llvm_context {
 	LLVMContextRef context;
 	LLVMModuleRef module;
@@ -56,11 +49,9 @@ struct ac_llvm_context {
 	LLVMTypeRef i16;
 	LLVMTypeRef i32;
 	LLVMTypeRef i64;
-	LLVMTypeRef intptr;
 	LLVMTypeRef f16;
 	LLVMTypeRef f32;
 	LLVMTypeRef f64;
-	LLVMTypeRef v2i16;
 	LLVMTypeRef v2i32;
 	LLVMTypeRef v3i32;
 	LLVMTypeRef v4i32;
@@ -79,10 +70,6 @@ struct ac_llvm_context {
 	LLVMValueRef i1true;
 	LLVMValueRef i1false;
 
-	struct ac_llvm_flow *flow;
-	unsigned flow_depth;
-	unsigned flow_depth_max;
-
 	unsigned range_md_kind;
 	unsigned invariant_load_md_kind;
 	unsigned uniform_md_kind;
@@ -100,15 +87,9 @@ void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 		     enum chip_class chip_class, enum radeon_family family);
 
-void
-ac_llvm_context_dispose(struct ac_llvm_context *ctx);
-
 int
 ac_get_llvm_num_components(LLVMValueRef value);
 
-int
-ac_get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type);
-
 LLVMValueRef
 ac_llvm_extract_elem(struct ac_llvm_context *ac,
 		     LLVMValueRef value,
@@ -136,8 +117,6 @@ ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
 void ac_build_optimization_barrier(struct ac_llvm_context *ctx,
 				   LLVMValueRef *pvgpr);
 
-LLVMValueRef ac_build_shader_clock(struct ac_llvm_context *ctx);
-
 LLVMValueRef ac_build_ballot(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_all(struct ac_llvm_context *ctx, LLVMValueRef value);
@@ -161,9 +140,6 @@ LLVMValueRef
 ac_build_gather_values(struct ac_llvm_context *ctx,
 		       LLVMValueRef *values,
 		       unsigned value_count);
-LLVMValueRef ac_build_expand_to_vec4(struct ac_llvm_context *ctx,
-				     LLVMValueRef value,
-				     unsigned num_channels);
 
 LLVMValueRef
 ac_build_fdiv(struct ac_llvm_context *ctx,
@@ -238,20 +214,8 @@ LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
 					 LLVMValueRef rsrc,
 					 LLVMValueRef vindex,
 					 LLVMValueRef voffset,
-					 unsigned num_channels,
-					 bool glc,
 					 bool can_speculate);
 
-/* load_format that handles the stride & element count better if idxen is
- * disabled by LLVM. */
-LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
-                                                  LLVMValueRef rsrc,
-                                                  LLVMValueRef vindex,
-                                                  LLVMValueRef voffset,
-                                                  unsigned num_channels,
-                                                  bool glc,
-                                                  bool can_speculate);
-
 LLVMValueRef
 ac_get_thread_id(struct ac_llvm_context *ctx);
 
@@ -288,10 +252,6 @@ LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, LLVMValueRef a,
 			   LLVMValueRef b);
 LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
 			   LLVMValueRef b);
-LLVMValueRef ac_build_imin(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b);
-LLVMValueRef ac_build_imax(struct ac_llvm_context *ctx, LLVMValueRef a,
-			   LLVMValueRef b);
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a, LLVMValueRef b);
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value);
 
@@ -306,84 +266,36 @@ struct ac_export_args {
 
 void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a);
 
-void ac_build_export_null(struct ac_llvm_context *ctx);
-
 enum ac_image_opcode {
 	ac_image_sample,
 	ac_image_gather4,
 	ac_image_load,
 	ac_image_load_mip,
-	ac_image_store,
-	ac_image_store_mip,
 	ac_image_get_lod,
 	ac_image_get_resinfo,
-	ac_image_atomic,
-	ac_image_atomic_cmpswap,
-};
-
-enum ac_atomic_op {
-	ac_atomic_swap,
-	ac_atomic_add,
-	ac_atomic_sub,
-	ac_atomic_smin,
-	ac_atomic_umin,
-	ac_atomic_smax,
-	ac_atomic_umax,
-	ac_atomic_and,
-	ac_atomic_or,
-	ac_atomic_xor,
-};
-
-enum ac_image_dim {
-	ac_image_1d,
-	ac_image_2d,
-	ac_image_3d,
-	ac_image_cube, // includes cube arrays
-	ac_image_1darray,
-	ac_image_2darray,
-	ac_image_2dmsaa,
-	ac_image_2darraymsaa,
-};
-
-/* These cache policy bits match the definitions used by the LLVM intrinsics. */
-enum ac_image_cache_policy {
-	ac_glc = 1 << 0,
-	ac_slc = 1 << 1,
 };
 
 struct ac_image_args {
-	enum ac_image_opcode opcode : 4;
-	enum ac_atomic_op atomic : 4; /* for the ac_image_atomic opcode */
-	enum ac_image_dim dim : 3;
-	unsigned dmask : 4;
-	unsigned cache_policy : 2;
-	bool unorm : 1;
-	bool level_zero : 1;
-	unsigned attributes; /* additional call-site specific AC_FUNC_ATTRs */
+	enum ac_image_opcode opcode;
+	bool level_zero;
+	bool bias;
+	bool lod;
+	bool deriv;
+	bool compare;
+	bool offset;
 
 	LLVMValueRef resource;
 	LLVMValueRef sampler;
-	LLVMValueRef data[2]; /* data[0] is source data (vector); data[1] is cmp for cmpswap */
-	LLVMValueRef offset;
-	LLVMValueRef bias;
-	LLVMValueRef compare;
-	LLVMValueRef derivs[6];
-	LLVMValueRef coords[4];
-	LLVMValueRef lod; // also used by ac_image_get_resinfo
+	LLVMValueRef addr;
+	unsigned dmask;
+	bool unorm;
+	bool da;
 };
 
 LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 				   struct ac_image_args *a);
 LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
 				    LLVMValueRef args[2]);
-LLVMValueRef ac_build_cvt_pknorm_i16(struct ac_llvm_context *ctx,
-				     LLVMValueRef args[2]);
-LLVMValueRef ac_build_cvt_pknorm_u16(struct ac_llvm_context *ctx,
-				     LLVMValueRef args[2]);
-LLVMValueRef ac_build_cvt_pk_i16(struct ac_llvm_context *ctx,
-				 LLVMValueRef args[2], unsigned bits, bool hi);
-LLVMValueRef ac_build_cvt_pk_u16(struct ac_llvm_context *ctx,
-				 LLVMValueRef args[2], unsigned bits, bool hi);
 LLVMValueRef ac_build_wqm_vote(struct ac_llvm_context *ctx, LLVMValueRef i1);
 void ac_build_kill_if_false(struct ac_llvm_context *ctx, LLVMValueRef i1);
 LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
@@ -392,14 +304,11 @@ LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
 
 void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16);
 
-LLVMValueRef ac_build_fract(struct ac_llvm_context *ctx, LLVMValueRef src0,
-			   unsigned bitsize);
-
-LLVMValueRef ac_build_isign(struct ac_llvm_context *ctx, LLVMValueRef src0,
-			    unsigned bitsize);
-
-LLVMValueRef ac_build_fsign(struct ac_llvm_context *ctx, LLVMValueRef src0,
-			    unsigned bitsize);
+void ac_get_image_intr_name(const char *base_name,
+			    LLVMTypeRef data_type,
+			    LLVMTypeRef coords_type,
+			    LLVMTypeRef rsrc_type,
+			    char *out_name, unsigned out_len);
 
 void ac_optimize_vs_outputs(struct ac_llvm_context *ac,
 			    LLVMValueRef main_fn,
@@ -417,66 +326,6 @@ void ac_lds_store(struct ac_llvm_context *ctx,
 LLVMValueRef ac_find_lsb(struct ac_llvm_context *ctx,
 			 LLVMTypeRef dst_type,
 			 LLVMValueRef src0);
-
-LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type);
-LLVMTypeRef ac_array_in_const32_addr_space(LLVMTypeRef elem_type);
-
-void ac_build_bgnloop(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_break(struct ac_llvm_context *ctx);
-void ac_build_continue(struct ac_llvm_context *ctx);
-void ac_build_else(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_endif(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_endloop(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
-		 int lable_id);
-void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
-		  int lable_id);
-
-LLVMValueRef ac_build_alloca(struct ac_llvm_context *ac, LLVMTypeRef type,
-			     const char *name);
-LLVMValueRef ac_build_alloca_undef(struct ac_llvm_context *ac, LLVMTypeRef type,
-				   const char *name);
-
-LLVMValueRef ac_cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
-			 LLVMTypeRef type);
-
-LLVMValueRef ac_trim_vector(struct ac_llvm_context *ctx, LLVMValueRef value,
-			    unsigned count);
-
-LLVMValueRef ac_unpack_param(struct ac_llvm_context *ctx, LLVMValueRef param,
-			     unsigned rshift, unsigned bitwidth);
-
-void ac_apply_fmask_to_sample(struct ac_llvm_context *ac, LLVMValueRef fmask,
-			      LLVMValueRef *addr, bool is_array_tex);
-
-LLVMValueRef
-ac_build_ds_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned mask);
-
-LLVMValueRef
-ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef lane);
-
-LLVMValueRef
-ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef value, LLVMValueRef lane);
-
-LLVMValueRef
-ac_build_mbcnt(struct ac_llvm_context *ctx, LLVMValueRef mask);
-
-LLVMValueRef
-ac_build_inclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op);
-
-LLVMValueRef
-ac_build_exclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op);
-
-LLVMValueRef
-ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op, unsigned cluster_size);
-
-LLVMValueRef
-ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src,
-		unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3);
-
-LLVMValueRef
-ac_build_shuffle(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef index);
-
 #ifdef __cplusplus
 }
 #endif

src/amd/common/ac_llvm_helper.cpp

@@ -60,17 +60,26 @@ bool ac_is_sgpr_param(LLVMValueRef arg)
 	llvm::Argument *A = llvm::unwrap<llvm::Argument>(arg);
 	llvm::AttributeList AS = A->getParent()->getAttributes();
 	unsigned ArgNo = A->getArgNo();
-	return AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg);
+	return AS.hasAttribute(ArgNo + 1, llvm::Attribute::ByVal) ||
+	       AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg);
 }
 
 LLVMValueRef ac_llvm_get_called_value(LLVMValueRef call)
 {
+#if HAVE_LLVM >= 0x0309
 	return LLVMGetCalledValue(call);
+#else
+	return llvm::wrap(llvm::CallSite(llvm::unwrap<llvm::Instruction>(call)).getCalledValue());
+#endif
 }
 
 bool ac_llvm_is_function(LLVMValueRef v)
 {
+#if HAVE_LLVM >= 0x0309
 	return LLVMGetValueKind(v) == LLVMFunctionValueKind;
+#else
+	return llvm::isa<llvm::Function>(llvm::unwrap(v));
+#endif
 }
 
 LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
@@ -78,6 +87,7 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 {
 	LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
 
+#if HAVE_LLVM >= 0x0308
 	llvm::FastMathFlags flags;
 
 	switch (float_mode) {
@@ -96,6 +106,7 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 		llvm::unwrap(builder)->setFastMathFlags(flags);
 		break;
 	}
+#endif
 
 	return builder;
 }

src/amd/common/ac_llvm_util.c

@@ -24,12 +24,10 @@
  */
 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
 #include "ac_llvm_util.h"
-#include "ac_llvm_build.h"
 #include "util/bitscan.h"
 #include <llvm-c/Core.h>
 #include <llvm-c/Support.h>
 #include "c11/threads.h"
-#include "util/u_math.h"
 
 #include <assert.h>
 #include <stdio.h>
@@ -48,11 +46,12 @@ static void ac_init_llvm_target()
 	/* Workaround for bug in llvm 4.0 that causes image intrinsics
 	 * to disappear.
 	 * https://reviews.llvm.org/D26348
-	 *
-	 * "mesa" is the prefix for error messages.
 	 */
-	const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
-	LLVMParseCommandLineOptions(2, argv, NULL);
+	if (HAVE_LLVM >= 0x0400) {
+		/* "mesa" is the prefix for error messages */
+		const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
+		LLVMParseCommandLineOptions(2, argv, NULL);
+	}
 }
 
 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
@@ -112,10 +111,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
 		return "polaris10";
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
 		return "polaris11";
 	case CHIP_VEGA10:
-	case CHIP_VEGA12:
 	case CHIP_RAVEN:
 		return "gfx900";
 	default:
@@ -149,10 +146,31 @@ LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac
 	return tm;
 }
 
+
+#if HAVE_LLVM < 0x0400
+static LLVMAttribute ac_attr_to_llvm_attr(enum ac_func_attr attr)
+{
+   switch (attr) {
+   case AC_FUNC_ATTR_ALWAYSINLINE: return LLVMAlwaysInlineAttribute;
+   case AC_FUNC_ATTR_BYVAL: return LLVMByValAttribute;
+   case AC_FUNC_ATTR_INREG: return LLVMInRegAttribute;
+   case AC_FUNC_ATTR_NOALIAS: return LLVMNoAliasAttribute;
+   case AC_FUNC_ATTR_NOUNWIND: return LLVMNoUnwindAttribute;
+   case AC_FUNC_ATTR_READNONE: return LLVMReadNoneAttribute;
+   case AC_FUNC_ATTR_READONLY: return LLVMReadOnlyAttribute;
+   default:
+	   fprintf(stderr, "Unhandled function attribute: %x\n", attr);
+	   return 0;
+   }
+}
+
+#else
+
 static const char *attr_to_str(enum ac_func_attr attr)
 {
    switch (attr) {
    case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
+   case AC_FUNC_ATTR_BYVAL: return "byval";
    case AC_FUNC_ATTR_INREG: return "inreg";
    case AC_FUNC_ATTR_NOALIAS: return "noalias";
    case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
@@ -167,10 +185,20 @@ static const char *attr_to_str(enum ac_func_attr attr)
    }
 }
 
+#endif
+
 void
 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
                      int attr_idx, enum ac_func_attr attr)
 {
+#if HAVE_LLVM < 0x0400
+   LLVMAttribute llvm_attr = ac_attr_to_llvm_attr(attr);
+   if (attr_idx == -1) {
+      LLVMAddFunctionAttr(function, llvm_attr);
+   } else {
+      LLVMAddAttribute(LLVMGetParam(function, attr_idx - 1), llvm_attr);
+   }
+#else
    const char *attr_name = attr_to_str(attr);
    unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
                                                       strlen(attr_name));
@@ -180,6 +208,7 @@ ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
       LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
    else
       LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
+#endif
 }
 
 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
@@ -204,39 +233,10 @@ ac_dump_module(LLVMModuleRef module)
 
 void
 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
-				     const char *name, unsigned value)
+				     const char *name, int value)
 {
 	char str[16];
 
-	snprintf(str, sizeof(str), "0x%x", value);
+	snprintf(str, sizeof(str), "%i", value);
 	LLVMAddTargetDependentFunctionAttr(F, name, str);
 }
-
-unsigned
-ac_count_scratch_private_memory(LLVMValueRef function)
-{
-	unsigned private_mem_vgprs = 0;
-
-	/* Process all LLVM instructions. */
-	LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
-	while (bb) {
-		LLVMValueRef next = LLVMGetFirstInstruction(bb);
-
-		while (next) {
-			LLVMValueRef inst = next;
-			next = LLVMGetNextInstruction(next);
-
-			if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
-				continue;
-
-			LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
-			/* No idea why LLVM aligns allocas to 4 elements. */
-			unsigned alignment = LLVMGetAlignment(inst);
-			unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
-			private_mem_vgprs += dw_size;
-		}
-		bb = LLVMGetNextBasicBlock(bb);
-	}
-
-	return private_mem_vgprs;
-}

src/amd/common/ac_llvm_util.h

@@ -37,14 +37,15 @@ extern "C" {
 
 enum ac_func_attr {
 	AC_FUNC_ATTR_ALWAYSINLINE = (1 << 0),
+	AC_FUNC_ATTR_BYVAL        = (1 << 1),
 	AC_FUNC_ATTR_INREG        = (1 << 2),
 	AC_FUNC_ATTR_NOALIAS      = (1 << 3),
 	AC_FUNC_ATTR_NOUNWIND     = (1 << 4),
 	AC_FUNC_ATTR_READNONE     = (1 << 5),
 	AC_FUNC_ATTR_READONLY     = (1 << 6),
-	AC_FUNC_ATTR_WRITEONLY    = (1 << 7),
-	AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = (1 << 8),
-	AC_FUNC_ATTR_CONVERGENT = (1 << 9),
+	AC_FUNC_ATTR_WRITEONLY    = HAVE_LLVM >= 0x0400 ? (1 << 7) : 0,
+	AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = HAVE_LLVM >= 0x0400 ? (1 << 8) : 0,
+	AC_FUNC_ATTR_CONVERGENT = HAVE_LLVM >= 0x0400 ? (1 << 9) : 0,
 
 	/* Legacy intrinsic that needs attributes on function declarations
 	 * and they must match the internal LLVM definition exactly, otherwise
@@ -87,27 +88,26 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 
 void
 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
-				     const char *name, unsigned value);
+				     const char *name, int value);
 
 static inline unsigned
 ac_get_load_intr_attribs(bool can_speculate)
 {
 	/* READNONE means writes can't affect it, while READONLY means that
 	 * writes can affect it. */
-	return can_speculate ? AC_FUNC_ATTR_READNONE :
-			       AC_FUNC_ATTR_READONLY;
+	return can_speculate && HAVE_LLVM >= 0x0400 ?
+				 AC_FUNC_ATTR_READNONE :
+				 AC_FUNC_ATTR_READONLY;
 }
 
 static inline unsigned
 ac_get_store_intr_attribs(bool writeonly_memory)
 {
-	return writeonly_memory ? AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
+	return writeonly_memory && HAVE_LLVM >= 0x0400 ?
+				  AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
 				  AC_FUNC_ATTR_WRITEONLY;
 }
 
-unsigned
-ac_count_scratch_private_memory(LLVMValueRef function);
-
 #ifdef __cplusplus
 }
 #endif

src/amd/common/ac_nir_to_llvm.h

@@ -28,35 +28,212 @@
 #include "llvm-c/Core.h"
 #include "llvm-c/TargetMachine.h"
 #include "amd_family.h"
+#include "../vulkan/radv_descriptor_set.h"
+#include "ac_shader_info.h"
 #include "compiler/shader_enums.h"
-
+struct ac_shader_binary;
+struct ac_shader_config;
 struct nir_shader;
-struct nir_variable;
+struct radv_pipeline_layout;
+
 struct ac_llvm_context;
 struct ac_shader_abi;
 
-/* Interpolation locations */
-#define INTERP_CENTER 0
-#define INTERP_CENTROID 1
-#define INTERP_SAMPLE 2
+struct ac_vs_variant_key {
+	uint32_t instance_rate_inputs;
+	uint32_t as_es:1;
+	uint32_t as_ls:1;
+	uint32_t export_prim_id:1;
+};
 
-static inline unsigned ac_llvm_reg_index_soa(unsigned index, unsigned chan)
-{
-	return (index * 4) + chan;
-}
+struct ac_tes_variant_key {
+	uint32_t as_es:1;
+	uint32_t export_prim_id:1;
+};
 
-void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
+struct ac_tcs_variant_key {
+	struct ac_vs_variant_key vs_key;
+	unsigned primitive_mode;
+	unsigned input_vertices;
+	uint32_t tes_reads_tess_factors:1;
+};
 
+struct ac_fs_variant_key {
+	uint32_t col_format;
+	uint8_t log2_ps_iter_samples;
+	uint8_t log2_num_samples;
+	uint32_t is_int8;
+	uint32_t is_int10;
+	uint32_t multisample : 1;
+};
+
+struct ac_shader_variant_key {
+	union {
+		struct ac_vs_variant_key vs;
+		struct ac_fs_variant_key fs;
+		struct ac_tes_variant_key tes;
+		struct ac_tcs_variant_key tcs;
+	};
+	bool has_multiview_view_index;
+};
+
+struct ac_nir_compiler_options {
+	struct radv_pipeline_layout *layout;
+	struct ac_shader_variant_key key;
+	bool unsafe_math;
+	bool supports_spill;
+	bool clamp_shadow_reference;
+	bool dump_preoptir;
+	enum radeon_family family;
+	enum chip_class chip_class;
+};
+
+struct ac_userdata_info {
+	int8_t sgpr_idx;
+	uint8_t num_sgprs;
+	bool indirect;
+	uint32_t indirect_offset;
+};
+
+enum ac_ud_index {
+	AC_UD_SCRATCH_RING_OFFSETS = 0,
+	AC_UD_PUSH_CONSTANTS = 1,
+	AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
+	AC_UD_VIEW_INDEX = 3,
+	AC_UD_SHADER_START = 4,
+	AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
+	AC_UD_VS_BASE_VERTEX_START_INSTANCE,
+	AC_UD_VS_LS_TCS_IN_LAYOUT,
+	AC_UD_VS_MAX_UD,
+	AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
+	AC_UD_PS_MAX_UD,
+	AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
+	AC_UD_CS_MAX_UD,
+	AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
+	AC_UD_GS_MAX_UD,
+	AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
+	AC_UD_TCS_MAX_UD,
+	AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
+	AC_UD_TES_MAX_UD,
+	AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
+};
+
+/* descriptor index into scratch ring offsets */
+#define RING_SCRATCH 0
+#define RING_ESGS_VS 1
+#define RING_ESGS_GS 2
+#define RING_GSVS_VS 3
+#define RING_GSVS_GS 4
+#define RING_HS_TESS_FACTOR 5
+#define RING_HS_TESS_OFFCHIP 6
+#define RING_PS_SAMPLE_POSITIONS 7
+
+// Match MAX_SETS from radv_descriptor_set.h
+#define AC_UD_MAX_SETS MAX_SETS
+
+struct ac_userdata_locations {
+	struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
+	struct ac_userdata_info shader_data[AC_UD_MAX_UD];
+};
+
+struct ac_vs_output_info {
+	uint8_t	vs_output_param_offset[VARYING_SLOT_MAX];
+	uint8_t clip_dist_mask;
+	uint8_t cull_dist_mask;
+	uint8_t param_exports;
+	bool writes_pointsize;
+	bool writes_layer;
+	bool writes_viewport_index;
+	bool export_prim_id;
+	uint32_t export_mask;
+	unsigned pos_exports;
+};
+
+struct ac_es_output_info {
+	uint32_t esgs_itemsize;
+};
+
+struct ac_shader_variant_info {
+	struct ac_userdata_locations user_sgprs_locs;
+	struct ac_shader_info info;
+	unsigned num_user_sgprs;
+	unsigned num_input_sgprs;
+	unsigned num_input_vgprs;
+	bool need_indirect_descriptor_sets;
+	struct {
+		struct {
+			struct ac_vs_output_info outinfo;
+			struct ac_es_output_info es_info;
+			unsigned vgpr_comp_cnt;
+			bool as_es;
+			bool as_ls;
+			uint64_t outputs_written;
+		} vs;
+		struct {
+			unsigned num_interp;
+			uint32_t input_mask;
+			uint32_t flat_shaded_mask;
+			bool has_pcoord;
+			bool can_discard;
+			bool writes_z;
+			bool writes_stencil;
+			bool writes_sample_mask;
+			bool early_fragment_test;
+			bool writes_memory;
+			bool prim_id_input;
+			bool layer_input;
+		} fs;
+		struct {
+			unsigned block_size[3];
+		} cs;
+		struct {
+			unsigned vertices_in;
+			unsigned vertices_out;
+			unsigned output_prim;
+			unsigned invocations;
+			unsigned gsvs_vertex_size;
+			unsigned max_gsvs_emit_size;
+			unsigned es_type; /* GFX9: VS or TES */
+		} gs;
+		struct {
+			unsigned tcs_vertices_out;
+			/* Which outputs are actually written */
+			uint64_t outputs_written;
+			/* Which patch outputs are actually written */
+			uint32_t patch_outputs_written;
+
+		} tcs;
+		struct {
+			struct ac_vs_output_info outinfo;
+			struct ac_es_output_info es_info;
+			bool as_es;
+			unsigned primitive_mode;
+			enum gl_tess_spacing spacing;
+			bool ccw;
+			bool point_mode;
+		} tes;
+	};
+};
+
+void ac_compile_nir_shader(LLVMTargetMachineRef tm,
+                           struct ac_shader_binary *binary,
+                           struct ac_shader_config *config,
+                           struct ac_shader_variant_info *shader_info,
+                           struct nir_shader *const *nir,
+                           int nir_count,
+                           const struct ac_nir_compiler_options *options,
+			   bool dump_shader);
+
+void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
+			      struct nir_shader *geom_shader,
+			      struct ac_shader_binary *binary,
+			      struct ac_shader_config *config,
+			      struct ac_shader_variant_info *shader_info,
+			      const struct ac_nir_compiler_options *options,
+			      bool dump_shader);
+
+struct nir_to_llvm_context;
 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
-		      struct nir_shader *nir);
-
-void
-ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
-			     struct ac_shader_abi *abi,
-			     struct nir_shader *nir,
-			     struct nir_variable *variable,
-			     gl_shader_stage stage);
-
-void ac_emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage);
+		      struct nir_shader *nir, struct nir_to_llvm_context *nctx);
 
 #endif /* AC_NIR_TO_LLVM_H */

src/amd/common/ac_shader_abi.h

@@ -26,12 +26,8 @@
 
 #include <llvm-c/Core.h>
 
-#include "compiler/shader_enums.h"
-
 struct nir_variable;
 
-#define AC_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
-
 enum ac_descriptor_type {
 	AC_DESC_IMAGE,
 	AC_DESC_FMASK,
@@ -57,18 +53,6 @@ struct ac_shader_abi {
 	LLVMValueRef front_face;
 	LLVMValueRef ancillary;
 	LLVMValueRef sample_coverage;
-	LLVMValueRef prim_mask;
-	/* CS */
-	LLVMValueRef local_invocation_ids;
-	LLVMValueRef num_work_groups;
-	LLVMValueRef workgroup_ids[3];
-	LLVMValueRef tg_size;
-
-	/* Vulkan only */
-	LLVMValueRef push_constants;
-	LLVMValueRef view_index;
-
-	LLVMValueRef outputs[AC_LLVM_MAX_OUTPUTS * 4];
 
 	/* For VS and PS: pre-loaded shader inputs.
 	 *
@@ -88,8 +72,6 @@ struct ac_shader_abi {
 	void (*emit_primitive)(struct ac_shader_abi *abi,
 			       unsigned stream);
 
-	void (*emit_kill)(struct ac_shader_abi *abi, LLVMValueRef visible);
-
 	LLVMValueRef (*load_inputs)(struct ac_shader_abi *abi,
 				    unsigned location,
 				    unsigned driver_location,
@@ -100,7 +82,6 @@ struct ac_shader_abi {
 				    LLVMTypeRef type);
 
 	LLVMValueRef (*load_tess_varyings)(struct ac_shader_abi *abi,
-					   LLVMTypeRef type,
 					   LLVMValueRef vertex_index,
 					   LLVMValueRef param_index,
 					   unsigned const_index,
@@ -120,7 +101,9 @@ struct ac_shader_abi {
 				  LLVMValueRef src,
 				  unsigned writemask);
 
-	LLVMValueRef (*load_tess_coord)(struct ac_shader_abi *abi);
+	LLVMValueRef (*load_tess_coord)(struct ac_shader_abi *abi,
+					LLVMTypeRef type,
+					unsigned num_components);
 
 	LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
 
@@ -157,41 +140,11 @@ struct ac_shader_abi {
 					  unsigned constant_index,
 					  LLVMValueRef index,
 					  enum ac_descriptor_type desc_type,
-					  bool image, bool write,
-					  bool bindless);
-
-	/**
-	 * Load a Vulkan-specific resource.
-	 *
-	 * \param index resource index
-	 * \param desc_set descriptor set
-	 * \param binding descriptor set binding
-	 */
-	LLVMValueRef (*load_resource)(struct ac_shader_abi *abi,
-				      LLVMValueRef index,
-				      unsigned desc_set,
-				      unsigned binding);
-
-	LLVMValueRef (*lookup_interp_param)(struct ac_shader_abi *abi,
-					    enum glsl_interp_mode interp,
-					    unsigned location);
-
-	LLVMValueRef (*load_sample_position)(struct ac_shader_abi *abi,
-					     LLVMValueRef sample_id);
-
-	LLVMValueRef (*load_local_group_size)(struct ac_shader_abi *abi);
-
-	LLVMValueRef (*load_sample_mask_in)(struct ac_shader_abi *abi);
-
-	LLVMValueRef (*load_base_vertex)(struct ac_shader_abi *abi);
+					  bool image, bool write);
 
 	/* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi currently
 	 * uses it due to promoting D16 to D32, but radv needs it off. */
 	bool clamp_shadow_reference;
-
-	/* Whether to workaround GFX9 ignoring the stride for the buffer size if IDXEN=0
-	* and LLVM optimizes an indexed load with constant index to IDXEN=0. */
-	bool gfx9_stride_size_workaround;
 };
 
 #endif /* AC_SHADER_ABI_H */

src/amd/common/ac_shader_info.c

@@ -0,0 +1,170 @@
+/*
+ * Copyright © 2017 Red Hat
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "nir/nir.h"
+#include "ac_shader_info.h"
+#include "ac_nir_to_llvm.h"
+
+static void mark_sampler_desc(const nir_variable *var,
+			      struct ac_shader_info *info)
+{
+	info->desc_set_used_mask = (1 << var->data.descriptor_set);
+}
+
+static void
+gather_intrinsic_info(const nir_intrinsic_instr *instr,
+		      struct ac_shader_info *info)
+{
+	switch (instr->intrinsic) {
+	case nir_intrinsic_interp_var_at_sample:
+		info->ps.needs_sample_positions = true;
+		break;
+	case nir_intrinsic_load_draw_id:
+		info->vs.needs_draw_id = true;
+		break;
+	case nir_intrinsic_load_instance_id:
+		info->vs.needs_instance_id = true;
+		break;
+	case nir_intrinsic_load_num_work_groups:
+		info->cs.uses_grid_size = true;
+		break;
+	case nir_intrinsic_load_local_invocation_id:
+	case nir_intrinsic_load_work_group_id: {
+		unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
+		while (mask) {
+			unsigned i = u_bit_scan(&mask);
+
+			if (instr->intrinsic == nir_intrinsic_load_work_group_id)
+				info->cs.uses_block_id[i] = true;
+			else
+				info->cs.uses_thread_id[i] = true;
+		}
+		break;
+	}
+	case nir_intrinsic_load_local_invocation_index:
+		info->cs.uses_local_invocation_idx = true;
+		break;
+	case nir_intrinsic_load_sample_id:
+		info->ps.force_persample = true;
+		break;
+	case nir_intrinsic_load_sample_pos:
+		info->ps.force_persample = true;
+		break;
+	case nir_intrinsic_load_view_index:
+		info->needs_multiview_view_index = true;
+		break;
+	case nir_intrinsic_load_invocation_id:
+		info->uses_invocation_id = true;
+		break;
+	case nir_intrinsic_load_primitive_id:
+		info->uses_prim_id = true;
+		break;
+	case nir_intrinsic_load_push_constant:
+		info->loads_push_constants = true;
+		break;
+	case nir_intrinsic_vulkan_resource_index:
+		info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
+		break;
+	case nir_intrinsic_image_load:
+	case nir_intrinsic_image_store:
+	case nir_intrinsic_image_atomic_add:
+	case nir_intrinsic_image_atomic_min:
+	case nir_intrinsic_image_atomic_max:
+	case nir_intrinsic_image_atomic_and:
+	case nir_intrinsic_image_atomic_or:
+	case nir_intrinsic_image_atomic_xor:
+	case nir_intrinsic_image_atomic_exchange:
+	case nir_intrinsic_image_atomic_comp_swap:
+	case nir_intrinsic_image_size: {
+		const struct glsl_type *type = instr->variables[0]->var->type;
+		if(instr->variables[0]->deref.child)
+			type = instr->variables[0]->deref.child->type;
+
+		enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
+		if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
+		    dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
+			info->ps.uses_input_attachments = true;
+		mark_sampler_desc(instr->variables[0]->var, info);
+		break;
+	}
+	default:
+		break;
+	}
+}
+
+static void
+gather_tex_info(const nir_tex_instr *instr, struct ac_shader_info *info)
+{
+	if (instr->sampler)
+		mark_sampler_desc(instr->sampler->var, info);
+	if (instr->texture)
+		mark_sampler_desc(instr->texture->var, info);
+}
+
+static void
+gather_info_block(const nir_block *block, struct ac_shader_info *info)
+{
+	nir_foreach_instr(instr, block) {
+		switch (instr->type) {
+		case nir_instr_type_intrinsic:
+			gather_intrinsic_info(nir_instr_as_intrinsic(instr), info);
+			break;
+		case nir_instr_type_tex:
+			gather_tex_info(nir_instr_as_tex(instr), info);
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+static void
+gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
+		       struct ac_shader_info *info)
+{
+	switch (nir->info.stage) {
+	case MESA_SHADER_VERTEX:
+		info->vs.has_vertex_buffers = true;
+		break;
+	default:
+		break;
+	}
+}
+
+void
+ac_nir_shader_info_pass(const struct nir_shader *nir,
+			const struct ac_nir_compiler_options *options,
+			struct ac_shader_info *info)
+{
+	struct nir_function *func =
+		(struct nir_function *)exec_list_get_head_const(&nir->functions);
+
+	if (options->layout->dynamic_offset_count)
+		info->loads_push_constants = true;
+
+	nir_foreach_variable(variable, &nir->inputs)
+		gather_info_input_decl(nir, variable, info);
+
+	nir_foreach_block(block, func->impl) {
+		gather_info_block(block, info);
+	}
+}

src/amd/common/ac_shader_info.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2014-2018 NVIDIA Corporation
+ * Copyright © 2017 Red Hat
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,29 +21,42 @@
  * IN THE SOFTWARE.
  */
 
-#include <fcntl.h>
+#ifndef AC_SHADER_INFO_H
+#define AC_SHADER_INFO_H
 
-#include "util/u_debug.h"
+struct nir_shader;
+struct ac_nir_compiler_options;
 
-#include "tegra/tegra_screen.h"
+struct ac_shader_info {
+	bool loads_push_constants;
+	uint32_t desc_set_used_mask;
+	bool needs_multiview_view_index;
+	bool uses_invocation_id;
+	bool uses_prim_id;
+	struct {
+		bool has_vertex_buffers; /* needs vertex buffers and base/start */
+		bool needs_draw_id;
+		bool needs_instance_id;
+	} vs;
+	struct {
+		bool force_persample;
+		bool needs_sample_positions;
+		bool uses_input_attachments;
+	} ps;
+	struct {
+		bool uses_grid_size;
+		bool uses_block_id[3];
+		bool uses_thread_id[3];
+		bool uses_local_invocation_idx;
+	} cs;
+};
 
-struct pipe_screen *tegra_drm_screen_create(int fd);
+/* A NIR pass to gather all the info needed to optimise the allocation patterns
+ * for the RADV user sgprs
+ */
+void
+ac_nir_shader_info_pass(const struct nir_shader *nir,
+			const struct ac_nir_compiler_options *options,
+			struct ac_shader_info *info);
 
-struct pipe_screen *tegra_drm_screen_create(int fd)
-{
-   struct pipe_screen *screen;
-
-   /*
-    * NOTE: There are reportedly issues with reusing the file descriptor
-    * as-is related to Xinerama. Duplicate it to side-step any issues.
-    */
-   fd = fcntl(fd, F_DUPFD_CLOEXEC, 0);
-   if (fd < 0)
-      return NULL;
-
-   screen = tegra_screen_create(fd);
-   if (!screen)
-      close(fd);
-
-   return screen;
-}
+#endif

src/amd/common/ac_surface.c

@@ -131,18 +131,10 @@ static void addrlib_family_rev_id(enum radeon_family family,
 		*addrlib_family = FAMILY_VI;
 		*addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
 		break;
-	case CHIP_VEGAM:
-		*addrlib_family = FAMILY_VI;
-		*addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
-		break;
 	case CHIP_VEGA10:
 		*addrlib_family = FAMILY_AI;
 		*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
 		break;
-	case CHIP_VEGA12:
-		*addrlib_family = FAMILY_AI;
-		*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
-		break;
 	case CHIP_RAVEN:
 		*addrlib_family = FAMILY_RV;
 		*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
@@ -171,7 +163,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 	ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 	ADDR_REGISTER_VALUE regValue = {0};
 	ADDR_CREATE_FLAGS createFlags = {{0}};
-	ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
+	ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
 	ADDR_E_RETURNCODE addrRet;
 
 	addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
@@ -279,7 +271,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 	    AddrSurfInfoIn->bpp) {
 		unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 
-		assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
+		assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
 		AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 	}
 
@@ -419,31 +411,6 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 	return index;
 }
 
-static bool get_display_flag(const struct ac_surf_config *config,
-			     const struct radeon_surf *surf)
-{
-	unsigned num_channels = config->info.num_channels;
-	unsigned bpe = surf->bpe;
-
-	if (surf->flags & RADEON_SURF_SCANOUT &&
-	    !(surf->flags & RADEON_SURF_FMASK) &&
-	    config->info.samples <= 1 &&
-	    surf->blk_w <= 2 && surf->blk_h == 1) {
-		/* subsampled */
-		if (surf->blk_w == 2 && surf->blk_h == 1)
-			return true;
-
-		if  (/* RGBA8 or RGBA16F */
-		     (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
-		     /* R5G6B5 or R5G5B5A1 */
-		     (bpe == 2 && num_channels >= 3) ||
-		     /* C8 palette */
-		     (bpe == 1 && num_channels == 1))
-			return true;
-	}
-	return false;
-}
-
 /**
  * This must be called after the first level is computed.
  *
@@ -478,7 +445,7 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 	    config->info.surf_index &&
 	    surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 	    !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
-	    !get_display_flag(config, surf)) {
+	    (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
 		ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 		ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 
@@ -597,7 +564,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 	AddrSurfInfoIn.flags.cube = config->is_cube;
 	AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
-	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
+	AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 	AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 	AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
@@ -843,8 +810,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 static int
 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 				ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
-				bool is_fmask, unsigned flags,
-				AddrSwizzleMode *swizzle_mode)
+				bool is_fmask, AddrSwizzleMode *swizzle_mode)
 {
 	ADDR_E_RETURNCODE ret;
 	ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
@@ -869,18 +835,7 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 	sin.numSamples = in->numSamples;
 	sin.numFrags = in->numFrags;
 
-	if (flags & RADEON_SURF_SCANOUT) {
-		sin.preferredSwSet.sw_D = 1;
-		/* Raven only allows S for displayable surfaces with < 64 bpp, so
-		 * allow it as fallback */
-		sin.preferredSwSet.sw_S = 1;
-	} else if (in->flags.depth || in->flags.stencil || is_fmask)
-		sin.preferredSwSet.sw_Z = 1;
-	else
-		sin.preferredSwSet.sw_S = 1;
-
 	if (is_fmask) {
-		sin.flags.display = 0;
 		sin.flags.color = 0;
 		sin.flags.fmask = 1;
 	}
@@ -894,7 +849,6 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 }
 
 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
-				const struct ac_surf_config *config,
 				struct radeon_surf *surf, bool compressed,
 				ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 {
@@ -950,8 +904,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 		hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 
-		hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-		hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
+		hin.hTileFlags.pipeAligned = 1;
+		hin.hTileFlags.rbAligned = 1;
 		hin.depthFlags = in->flags;
 		hin.swizzleMode = in->swizzleMode;
 		hin.unalignedWidth = in->width;
@@ -969,37 +923,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		surf->htile_slice_size = hout.sliceSize;
 		surf->htile_alignment = hout.baseAlign;
 	} else {
-		/* Compute tile swizzle for the color surface.
-		 * All *_X and *_T modes can use the swizzle.
-		 */
-		if (config->info.surf_index &&
-		    in->swizzleMode >= ADDR_SW_64KB_Z_T &&
-		    !out.mipChainInTail &&
-		    !(surf->flags & RADEON_SURF_SHAREABLE) &&
-		    !in->flags.display) {
-			ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
-			ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
-
-			xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
-			xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
-
-			xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
-			xin.flags = in->flags;
-			xin.swizzleMode = in->swizzleMode;
-			xin.resourceType = in->resourceType;
-			xin.format = in->format;
-			xin.numSamples = in->numSamples;
-			xin.numFrags = in->numFrags;
-
-			ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
-			if (ret != ADDR_OK)
-				return ret;
-
-			assert(xout.pipeBankXor <=
-			       u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
-			surf->tile_swizzle = xout.pipeBankXor;
-		}
-
 		/* DCC */
 		if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 		    !compressed &&
@@ -1012,8 +935,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 			dout.pMipInfo = meta_mip_info;
 
-			din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-			din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
+			din.dccKeyFlags.pipeAligned = 1;
+			din.dccKeyFlags.rbAligned = 1;
 			din.colorFlags = in->flags;
 			din.resourceType = in->resourceType;
 			din.swizzleMode = in->swizzleMode;
@@ -1077,9 +1000,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
 			fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 
-			ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
-							      true, surf->flags,
-							      &fin.swizzleMode);
+			ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
 			if (ret != ADDR_OK)
 				return ret;
 
@@ -1097,34 +1018,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			surf->u.gfx9.fmask.epitch = fout.pitch - 1;
 			surf->u.gfx9.fmask_size = fout.fmaskBytes;
 			surf->u.gfx9.fmask_alignment = fout.baseAlign;
-
-			/* Compute tile swizzle for the FMASK surface. */
-			if (config->info.fmask_surf_index &&
-			    fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
-			    !(surf->flags & RADEON_SURF_SHAREABLE)) {
-				ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
-				ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
-
-				xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
-				xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
-
-				/* This counter starts from 1 instead of 0. */
-				xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
-				xin.flags = in->flags;
-				xin.swizzleMode = in->swizzleMode;
-				xin.resourceType = in->resourceType;
-				xin.format = in->format;
-				xin.numSamples = in->numSamples;
-				xin.numFrags = in->numFrags;
-
-				ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
-				if (ret != ADDR_OK)
-					return ret;
-
-				assert(xout.pipeBankXor <=
-				       u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
-				surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
-			}
 		}
 
 		/* CMASK */
@@ -1135,14 +1028,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 			cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 
-			if (in->numSamples) {
-				/* FMASK is always aligned. */
-				cin.cMaskFlags.pipeAligned = 1;
-				cin.cMaskFlags.rbAligned = 1;
-			} else {
-				cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-				cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
-			}
+			cin.cMaskFlags.pipeAligned = 1;
+			cin.cMaskFlags.rbAligned = 1;
 			cin.colorFlags = in->flags;
 			cin.resourceType = in->resourceType;
 			cin.unalignedWidth = in->width;
@@ -1169,7 +1056,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 }
 
 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
-				const struct radeon_info *info,
 				const struct ac_surf_config *config,
 				enum radeon_surf_mode mode,
 				struct radeon_surf *surf)
@@ -1198,38 +1084,12 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 			assert(0);
 		}
 	} else {
-		switch (surf->bpe) {
-		case 1:
-			assert(!(surf->flags & RADEON_SURF_ZBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_8;
-			break;
-		case 2:
-			assert(surf->flags & RADEON_SURF_ZBUFFER ||
-			       !(surf->flags & RADEON_SURF_SBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_16;
-			break;
-		case 4:
-			assert(surf->flags & RADEON_SURF_ZBUFFER ||
-			       !(surf->flags & RADEON_SURF_SBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_32;
-			break;
-		case 8:
-			assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_32_32;
-			break;
-		case 16:
-			assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
-			break;
-		default:
-			assert(0);
-		}
 		AddrSurfInfoIn.bpp = surf->bpe * 8;
 	}
 
 	AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
-	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
+	AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 	/* flags.texture currently refers to TC-compatible HTILE */
 	AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
 				       surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
@@ -1257,10 +1117,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	else
 		AddrSurfInfoIn.numSlices = config->info.array_size;
 
-	/* This is propagated to HTILE/DCC/CMASK. */
-	AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
-	AddrSurfInfoIn.flags.metaRbUnaligned = 0;
-
 	switch (mode) {
 	case RADEON_SURF_MODE_LINEAR_ALIGNED:
 		assert(config->info.samples <= 1);
@@ -1275,8 +1131,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 			break;
 		}
 
-		r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
-						    false, surf->flags,
+		r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
 						    &AddrSurfInfoIn.swizzleMode);
 		if (r)
 			return r;
@@ -1300,8 +1155,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	surf->u.gfx9.cmask_size = 0;
 
 	/* Calculate texture layout information. */
-	r = gfx9_compute_miptree(addrlib, config, surf, compressed,
-				 &AddrSurfInfoIn);
+	r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
 	if (r)
 		return r;
 
@@ -1309,19 +1163,16 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	if (surf->flags & RADEON_SURF_SBUFFER) {
 		AddrSurfInfoIn.flags.stencil = 1;
 		AddrSurfInfoIn.bpp = 8;
-		AddrSurfInfoIn.format = ADDR_FMT_8;
 
 		if (!AddrSurfInfoIn.flags.depth) {
-			r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
-							    false, surf->flags,
+			r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
 							    &AddrSurfInfoIn.swizzleMode);
 			if (r)
 				return r;
 		} else
 			AddrSurfInfoIn.flags.depth = 0;
 
-		r = gfx9_compute_miptree(addrlib, config, surf, compressed,
-					 &AddrSurfInfoIn);
+		r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
 		if (r)
 			return r;
 	}
@@ -1389,10 +1240,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 			assert(0);
 	}
 
-	/* Temporary workaround to prevent VM faults and hangs. */
-	if (info->family == CHIP_VEGA12)
-		surf->u.gfx9.fmask_size *= 8;
-
 	return 0;
 }
 
@@ -1408,7 +1255,7 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 		return r;
 
 	if (info->chip_class >= GFX9)
-		return gfx9_compute_surface(addrlib, info, config, mode, surf);
+		return gfx9_compute_surface(addrlib, config, mode, surf);
 	else
 		return gfx6_compute_surface(addrlib, info, config, mode, surf);
 }

src/amd/common/ac_surface.h

@@ -147,8 +147,6 @@ struct gfx9_surf_layout {
 
     uint32_t                    fmask_alignment;
     uint32_t                    cmask_alignment;
-
-    uint8_t                     fmask_tile_swizzle;
 };
 
 struct radeon_surf {
@@ -177,8 +175,7 @@ struct radeon_surf {
     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
      * The value is the same for all mipmap levels. Supported tile modes:
      * - GFX6: Only macro tiling.
-     * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
-     *   tail.
+     * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
      *
      * Only these surfaces are allowed to set it:
      * - color (if it doesn't have to be displayable)
@@ -219,10 +216,8 @@ struct ac_surf_info {
 	uint32_t depth;
 	uint8_t samples;
 	uint8_t levels;
-	uint8_t num_channels; /* heuristic for displayability */
 	uint16_t array_size;
 	uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
-	uint32_t *fmask_surf_index; /* GFX9+ */
 };
 
 struct ac_surf_config {

src/amd/common/amd_family.h

@@ -92,9 +92,7 @@ enum radeon_family {
     CHIP_POLARIS10,
     CHIP_POLARIS11,
     CHIP_POLARIS12,
-    CHIP_VEGAM,
     CHIP_VEGA10,
-    CHIP_VEGA12,
     CHIP_RAVEN,
     CHIP_LAST,
 };

src/amd/common/meson.build

@@ -36,6 +36,8 @@ amd_common_files = files(
   'ac_llvm_util.c',
   'ac_llvm_util.h',
   'ac_shader_abi.h',
+  'ac_shader_info.c',
+  'ac_shader_info.h',
   'ac_shader_util.c',
   'ac_shader_util.h',
   'ac_nir_to_llvm.c',

src/amd/vulkan/Makefile.am

@@ -23,10 +23,6 @@ include Makefile.sources
 
 noinst_HEADERS = \
 	$(top_srcdir)/include/vulkan/vk_platform.h \
-	$(top_srcdir)/include/vulkan/vulkan_core.h \
-	$(top_srcdir)/include/vulkan/vulkan_wayland.h \
-	$(top_srcdir)/include/vulkan/vulkan_xcb.h \
-	$(top_srcdir)/include/vulkan/vulkan_xlib.h \
 	$(top_srcdir)/include/vulkan/vulkan.h
 
 lib_LTLIBRARIES = libvulkan_radeon.la
@@ -117,11 +113,13 @@ nodist_EXTRA_libvulkan_radeon_la_SOURCES = dummy.cpp
 libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES)
 
 vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
+vk_android_native_buffer_xml = $(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml
 
 radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py $(vulkan_api_xml)
 	$(MKDIR_GEN)
 	$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
 		--xml $(vulkan_api_xml) \
+		--xml $(vk_android_native_buffer_xml) \
 		--outdir $(builddir)
 radv_entrypoints.h: radv_entrypoints.c
 
@@ -130,9 +128,8 @@ radv_extensions.c: radv_extensions.py \
 	$(MKDIR_GEN)
 	$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_extensions.py \
 		--xml $(vulkan_api_xml) \
-		--out-c radv_extensions.c \
-		--out-h radv_extensions.h
-radv_extensions.h: radv_extensions.c
+		--xml $(vk_android_native_buffer_xml) \
+		--out $@
 
 vk_format_table.c: vk_format_table.py \
 		   vk_format_parse.py \
@@ -143,9 +140,10 @@ BUILT_SOURCES = $(VULKAN_GENERATED_FILES)
 CLEANFILES = $(BUILT_SOURCES) dev_icd.json radeon_icd.@host_cpu@.json
 EXTRA_DIST = \
 	$(top_srcdir)/include/vulkan/vk_icd.h \
+	dev_icd.json.in \
+	radeon_icd.json.in \
 	radv_entrypoints_gen.py \
 	radv_extensions.py \
-	radv_icd.py \
 	vk_format_layout.csv \
 	vk_format_parse.py \
 	vk_format_table.py \
@@ -169,12 +167,14 @@ icdconf_DATA = radeon_icd.@host_cpu@.json
 # The following is used for development purposes, by setting VK_ICD_FILENAMES.
 noinst_DATA = dev_icd.json
 
-dev_icd.json : radv_extensions.py radv_icd.py
-	$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_icd.py \
-		--lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
+dev_icd.json : dev_icd.json.in
+	$(AM_V_GEN) $(SED) \
+		-e "s#@libvulkan_radeon_path@#${abs_top_builddir}/${LIB_DIR}/libvulkan_radeon.so#" \
+		< $(srcdir)/dev_icd.json.in > $@
 
-radeon_icd.@host_cpu@.json : radv_extensions.py radv_icd.py
-	$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_icd.py \
-		--lib-path="${libdir}" --out $@
+radeon_icd.@host_cpu@.json : radeon_icd.json.in
+	$(AM_V_GEN) $(SED) \
+		-e "s#@install_libdir@#${libdir}#" \
+		< $(srcdir)/radeon_icd.json.in > $@
 
 include $(top_srcdir)/install-lib-links.mk

src/amd/vulkan/Makefile.sources

@@ -53,14 +53,12 @@ VULKAN_FILES := \
 	radv_meta_resolve.c \
 	radv_meta_resolve_cs.c \
 	radv_meta_resolve_fs.c \
-	radv_nir_to_llvm.c \
 	radv_pass.c \
 	radv_pipeline.c \
 	radv_pipeline_cache.c \
 	radv_private.h \
 	radv_radeon_winsys.h \
 	radv_shader.c \
-	radv_shader_info.c \
 	radv_shader.h \
 	radv_query.c \
 	radv_util.c \
@@ -83,6 +81,5 @@ VULKAN_WSI_X11_FILES := \
 VULKAN_GENERATED_FILES := \
 	radv_entrypoints.c \
 	radv_entrypoints.h \
-	radv_extensions.c \
-	radv_extensions.h
+	radv_extensions.c
 

src/amd/vulkan/dev_icd.json.in

@@ -0,0 +1,7 @@
+{
+    "file_format_version": "1.0.0",
+    "ICD": {
+        "library_path": "@libvulkan_radeon_path@",
+        "api_version": "1.0.3"
+    }
+}

src/amd/vulkan/meson.build

@@ -31,11 +31,10 @@ radv_entrypoints = custom_target(
 
 radv_extensions_c = custom_target(
   'radv_extensions.c',
-  input : ['radv_extensions.py', vk_api_xml],
-  output : ['radv_extensions.c', 'radv_extensions.h'],
+  input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml],
+  output : ['radv_extensions.c'],
   command : [
-    prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--out-c', '@OUTPUT0@',
-    '--out-h', '@OUTPUT1@'
+    prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', '--out', '@OUTPUT@',
   ],
 )
 
@@ -80,7 +79,6 @@ libradv_files = files(
   'radv_meta_resolve.c',
   'radv_meta_resolve_cs.c',
   'radv_meta_resolve_fs.c',
-  'radv_nir_to_llvm.c',
   'radv_pass.c',
   'radv_pipeline.c',
   'radv_pipeline_cache.c',
@@ -88,7 +86,6 @@ libradv_files = files(
   'radv_radeon_winsys.h',
   'radv_shader.c',
   'radv_shader.h',
-  'radv_shader_info.c',
   'radv_query.c',
   'radv_util.c',
   'radv_util.h',
@@ -136,30 +133,18 @@ libvulkan_radeon = shared_library(
   install : true,
 )
 
-radeon_icd = custom_target(
-  'radeon_icd',
-  input : 'radv_icd.py',
-  output : 'radeon_icd.@0@.json'.format(host_machine.cpu()),
-  command : [
-    prog_python2, '@INPUT@',
-    '--lib-path', join_paths(get_option('prefix'), get_option('libdir')),
-    '--out', '@OUTPUT@',
-  ],
-  depend_files : files('radv_extensions.py'),
-  build_by_default : true,
-  install_dir : with_vulkan_icd_dir,
-  install : true,
-)
+radv_data = configuration_data()
+radv_data.set('install_libdir', join_paths(get_option('prefix'), get_option('libdir')))
+radv_data.set('libvulkan_radeon_path', libvulkan_radeon.full_path())
 
-radv_dev_icd = custom_target(
-  'radv_dev_icd',
-  input : 'radv_icd.py',
-  output : 'dev_icd.json',
-  command : [
-    prog_python2, '@INPUT@', '--lib-path', meson.current_build_dir(),
-    '--out', '@OUTPUT@'
-  ],
-  depend_files : files('radv_extensions.py'),
-  build_by_default : true,
-  install : false,
+configure_file(
+  configuration : radv_data,
+  input : 'radeon_icd.json.in',
+  output : 'radeon_icd.@0@.json'.format(host_machine.cpu()),
+  install_dir : with_vulkan_icd_dir,
+)
+configure_file(
+  configuration : radv_data,
+  input : 'dev_icd.json.in',
+  output : 'dev_icd.json'
 )

src/amd/vulkan/radeon_icd.json.in

@@ -0,0 +1,7 @@
+{
+    "file_format_version": "1.0.0",
+    "ICD": {
+        "library_path": "@install_libdir@/libvulkan_radeon.so",
+        "api_version": "1.0.3"
+    }
+}

src/amd/vulkan/radv_android.c

@@ -230,11 +230,11 @@ VkResult radv_GetSwapchainGrallocUsageANDROID(
 	};
 
 	/* Check that requested format and usage are supported. */
-	result = radv_GetPhysicalDeviceImageFormatProperties2(phys_dev_h,
-	                                                      &image_format_info, &image_format_props);
+	result = radv_GetPhysicalDeviceImageFormatProperties2KHR(phys_dev_h,
+	                                                         &image_format_info, &image_format_props);
 	if (result != VK_SUCCESS) {
 		return vk_errorf(result,
-		                 "radv_GetPhysicalDeviceImageFormatProperties2 failed "
+		                 "radv_GetPhysicalDeviceImageFormatProperties2KHR failed "
 		                 "inside %s", __func__);
 	}
 

src/amd/vulkan/radv_debug.c

@@ -29,7 +29,6 @@
 #include <stdio.h>
 #include <sys/utsname.h>
 
-#include "util/mesa-sha1.h"
 #include "sid.h"
 #include "gfx9d.h"
 #include "ac_debug.h"
@@ -500,13 +499,7 @@ radv_dump_shader(struct radv_pipeline *pipeline,
 	fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
 
 	if (shader->spirv) {
-		unsigned char sha1[21];
-		char sha1buf[41];
-
-		_mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
-		_mesa_sha1_format(sha1buf, sha1);
-
-		fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
+		fprintf(f, "SPIRV:\n");
 		radv_print_spirv(shader->spirv, shader->spirv_size, f);
 	}
 
@@ -515,7 +508,6 @@ radv_dump_shader(struct radv_pipeline *pipeline,
 		nir_print_shader(shader->nir, f);
 	}
 
-	fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string);
 	fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 
 	radv_shader_dump_stats(pipeline->device, shader, stage, f);
@@ -601,32 +593,28 @@ radv_dump_dmesg(FILE *f)
 	pclose(p);
 }
 
-void
+static void
 radv_dump_enabled_options(struct radv_device *device, FILE *f)
 {
 	uint64_t mask;
 
-	if (device->instance->debug_flags) {
-		fprintf(f, "Enabled debug options: ");
+	fprintf(f, "Enabled debug options: ");
 
-		mask = device->instance->debug_flags;
-		while (mask) {
-			int i = u_bit_scan64(&mask);
-			fprintf(f, "%s, ", radv_get_debug_option_name(i));
-		}
-		fprintf(f, "\n");
+	mask = device->instance->debug_flags;
+	while (mask) {
+		int i = u_bit_scan64(&mask);
+		fprintf(f, "%s, ", radv_get_debug_option_name(i));
 	}
+	fprintf(f, "\n");
 
-	if (device->instance->perftest_flags) {
-		fprintf(f, "Enabled perftest options: ");
+	fprintf(f, "Enabled perftest options: ");
 
-		mask = device->instance->perftest_flags;
-		while (mask) {
-			int i = u_bit_scan64(&mask);
-			fprintf(f, "%s, ", radv_get_perftest_option_name(i));
-		}
-		fprintf(f, "\n");
+	mask = device->instance->perftest_flags;
+	while (mask) {
+		int i = u_bit_scan64(&mask);
+		fprintf(f, "%s, ", radv_get_perftest_option_name(i));
 	}
+	fprintf(f, "\n");
 }
 
 static void