docs: Add 18.1.9 release notes

Bump version to 18.1.9
radv: Fix driver UUID SHA1 init.
2018-09-24 08:43:25 -07:00 · 2018-09-21 09:02:55 -07:00 · 2018-09-20 14:53:59 -07:00 · 2018-09-20 13:30:54 -07:00 · 2018-09-20 13:29:41 -07:00 · 2018-09-20 13:29:40 -07:00
71 changed files with 1197 additions and 251 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-18.1.7
+18.1.9
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -66,8 +66,64 @@ f9e8456c39136aa41f85f82758a00e5aa2aab334
 a4a104fc81e93555899050efac23c3cd6ba762ab
 24ee53231da84a1be5ec08abebe8a2ff6aa019ca
 4c43ec461de4f122d5d6566361d064c816e4ef69
+743e11c10b180247488ae0cc24900560e0a74e2b
+4ffb575da59fd3aece02734ca4fd3212d5002d55
+8c048af5890d43578ca41eb9dcfa60cb9cc3fc9c
+c92a463d2341dd7893dd8b54775930ed9be72ac0
+ea1e50cc166ae855f9fa91ca6a4f944123298e4e
+f73f748323ef5a421ffd8fa0f02afd9627e31023
+d4e52281aa9c1acc92619736da8b67d8c02ce380
+a5f35aa742c3f1e2fae6a6c2fb53f92822f0cb70
+f6e09db2e613c215257b80f40957d580165b5ddf
+d4bf954fe61ec231be2bfa5e059f0fb7f6150bd1
+abdf396cbeaec2bfe9da2fd773d42fa3022ca8b5
+b9f6521157ab55073eec528cacc1f3b567e49503
+aa3020592964344c7032396d159e4ab2df743587
+063264db5be2941746fa58f164cdc803362753a9
+748f4cce183007587a6688ef25ad5f9dbea5c33c
+9de062ef207c6062d1fabb70209f4bbc9dc4732d
+7d1d1208c2b38890fe065b6431ef2e3b7166bae4
+0796c3934ebfe3448acf2d63f478f51c08e33046
+864c780566b8782c4fc69b4337db768223717bd8

 # These have more than one fixes tag and generate a warning
 #
 24839663a40257e0468406d72c48d431b5ae2bd4
 6ff1c479968819b93c46d24bd898e89ce14ac401
+ac0856ae4100a05dcd1fd932d9fd10200f8f7a7c
+c9f54486959716762e6818dabb0a73a8cd46df67
+
+# This patch requires patches that would require python 3, the thing they're
+# fixing isn't really even a bug, it's more of a style choice, so I'm not going
+# to pull them.
+#
+48820ed8da0ad50d51a58f26e156d82b685492e2
+
+# This patch doesn't apply and either needs to be backported or can just be
+# ignored
+#
+1e40f6948310be07abb2d0198e6602769892cdac
+
+# This patch isn't necessary, since the patch it fixes is not present in 18.1
+#
+a72dbc461bdb7714656e62cd8f4b00a404c2e6e0
+
+# This requires a much more significant patch not present in 18.1
+#
+4dc244eb447b1fa4e39d67a58328ed774395c901
+
+# This patches were dropped since they only fix developer tools, which aren't
+# built by default and should be of no use to end users or distros
+#
+97fcccb25ed5f55139c03ebc1c71742f0f25f683
+4aec44c0d9c4c0649c362199fac97efe0a3b38a4
+
+# This patch was reverted on master shortly after merging.
+#
+90819abb56f6b1a0cd4946b13b6caf24fb46e500
+
+# These were supreceeded by patches backported to 18.1
+#
+3341429d74099b436c3824164837eebd47029ded
+9158e0bd82ffdad4baf46221bccbbb3fe4764c11
+cc3b99bb48769ccd018b781338b548306af5046b
--- a/docs/install.html
+++ b/docs/install.html
@@ -75,7 +75,7 @@ you think you've spotted a bug let developers know by filing a
 Version 2.6.4 or later should work.
 </li>
 <li><a href="http://www.makotemplates.org/">Python Mako module</a> -
-Python Mako module is required. Version 0.3.4 or later should work.
+Python Mako module is required. Version 0.8.0 or later should work.
 </li>
 <li>lex / yacc - for building the Mesa IR and GLSL compiler.
 <div>
--- a/docs/relnotes/18.1.7.html
+++ b/docs/relnotes/18.1.7.html
@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+0c3c240bcd1352d179e65993214f9d55a399beac852c3ab4433e8df9b6c51c83  mesa-18.1.7.tar.gz
+655e3b32ce3bdddd5e6e8768596e5d4bdef82d0dd37067c324cc4b2daa207306  mesa-18.1.7.tar.xz
 </pre>


--- a/docs/relnotes/18.1.8.html
+++ b/docs/relnotes/18.1.8.html
@@ -0,0 +1,180 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.8 Release Notes / September 7 2018</h1>
+
+<p>
+Mesa 18.1.8 is a bug fix release which fixes bugs found since the 18.1.7 release.
+</p>
+<p>
+Mesa 18.1.8 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+8ec62f215dd1bb3910987f9941c6fc31632a0874e618815cf1e8e29445c86e0a  mesa-18.1.8.tar.gz
+bd1be67fe9c73b517765264ac28911c84144682d28dbff140e1c2deb2f44c21b  mesa-18.1.8.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93355">Bug 93355</a> - [BXT,SKLGT4e] intermittent ext_framebuffer_multisample.accuracy fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101247">Bug 101247</a> - Mesa fails to link GLSL programs with unused output blocks</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104809">Bug 104809</a> - anv: DOOM 2016 and Wolfenstein II:The New Colossus crash due to not having depthBoundsTest</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105904">Bug 105904</a> - Needed to delete mesa shader cache after driver upgrade for 32 bit wine vulkan programs to work.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106738">Bug 106738</a> - No test for miptrees with DRI modifiers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106865">Bug 106865</a> - [GLK] piglit.spec.ext_framebuffer_multisample.accuracy stencil tests fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107359">Bug 107359</a> - [Regression] [bisected] [OpenGL CTS] [SKL,BDW] KHR-GL46.texture_barrier*-texels, GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners, and GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners fail with some configuration</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107477">Bug 107477</a> - [DXVK] Setting high shader quality in GTA V results in LLVM error</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107579">Bug 107579</a> - [SNB] The graphic corruption when we reuse the GS compiled and used for TFB when statebuffer contain magic trash in the unused space</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107601">Bug 107601</a> - Rise of the Tomb Raider Segmentation Fault when the game starts</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107760">Bug 107760</a> - GPU Hang when Playing DiRT 3 Complete Edition using Steam Play with DXVK</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Andrii Simiklit (1):</p>
+<ul>
+  <li>i965/gen6/xfb: handle case where transform feedback is not active</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+  <li>radv: Add missing checks in radv_get_image_format_properties.</li>
+  <li>radv: Fix CMASK dimensions.</li>
+  <li>radv: Use a lower max offchip buffer count.</li>
+</ul>
+
+<p>Christian Gmeiner (1):</p>
+<ul>
+  <li>tegra: fix memory leak</li>
+</ul>
+
+<p>Daniel Stone (1):</p>
+<ul>
+  <li>st/dri: Don't expose sRGB formats to clients</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>ac/radeonsi: fix CIK copy max size</li>
+</ul>
+
+<p>Dylan Baker (10):</p>
+<ul>
+  <li>docs: Add mesa 18.1.7 notes</li>
+  <li>cherry-ignore: add a patch</li>
+  <li>cherry-ignore: Add more 18.2 only patches</li>
+  <li>meson: Actually load translation files</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: Add additional patch</li>
+  <li>cherry-ignore: Add patch that doesn't apply to 18.1</li>
+  <li>cherry-ignore: Add a couple of two fixes warning patches</li>
+  <li>cherry-ignore: Add patch that needs more significant patches to function</li>
+  <li>Bump version to 18.1.8</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>docs: update required mako version</li>
+</ul>
+
+<p>Grazvydas Ignotas (1):</p>
+<ul>
+  <li>radv: place pointer length into cache uuid</li>
+</ul>
+
+<p>Gurchetan Singh (2):</p>
+<ul>
+  <li>meson: fix egl build for surfaceless</li>
+  <li>meson: fix egl build for android</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>i965/vec4: Clamp indirect tes input array reads with 0x0fffffff</li>
+  <li>i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset</li>
+</ul>
+
+<p>Jason Ekstrand (5):</p>
+<ul>
+  <li>anv: Fill holes in the VF VUE to zero</li>
+  <li>nir/algebraic: Be more careful converting ushr to extract_u8/16</li>
+  <li>egl/dri2: Add a helper for the number of planes for a FOURCC format</li>
+  <li>egl/dri2: Guard against invalid fourcc formats</li>
+  <li>anv/blorp: Do more flushing around HiZ clears</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+  <li>egl/wayland: do not leak wl_buffer when it is locked</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>anv: blorp: support multiple aspect blits</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>glapi: actually implement GL_EXT_robustness for GLES</li>
+</ul>
+
+<p>Nanley Chery (7):</p>
+<ul>
+  <li>intel/isl: Avoid tiling some 16K-wide render targets</li>
+  <li>i965: Make blt_pitch public</li>
+  <li>i965/miptree: Drop an if case from retile_as_linear</li>
+  <li>i965/miptree: Use the correct BLT pitch</li>
+  <li>i965/miptree: Use miptree_map in map_blit functions</li>
+  <li>i965/miptree: Fix can_blit_slice()</li>
+  <li>i965/gen7_urb: Re-emit PUSH_CONSTANT_ALLOC on some gen9</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+  <li>radv: fix passing clip/cull distances from VS to PS</li>
+</ul>
+
+<p>vadym.shovkoplias (1):</p>
+<ul>
+  <li>glsl/linker: Allow unused in blocks which are not declated on previous stage</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/18.1.9.html
+++ b/docs/relnotes/18.1.9.html
@@ -0,0 +1,177 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.8 Release Notes / September 24 2018</h1>
+
+<p>
+Mesa 18.1.9 is a bug fix release which fixes bugs found since the 18.1.8 release.
+</p>
+<p>
+Mesa 18.1.9 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103241">Bug 103241</a> - Anv crashes when using 64-bit vertex inputs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104926">Bug 104926</a> - swrast: Mesa 17.3.3 produces:  HW cursor for format 875713089 not supported</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107280">Bug 107280</a> - [DXVK] Batman: Arkham City with tessellation enabled hangs on SKL GT4</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107772">Bug 107772</a> - Mesa preprocessor matches if(def)s &amp; endifs incorrectly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107779">Bug 107779</a> - Access violation with some games</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107810">Bug 107810</a> - The 'va_end' call is missed after 'va_copy' in 'util_vsnprintf' function under windows</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Andrii Simiklit (4):</p>
+<ul>
+  <li>apple/glx/log: added missing va_end() after va_copy()</li>
+  <li>mesa/util: don't use the same 'va_list' instance twice</li>
+  <li>mesa/util: don't ignore NULL returned from 'malloc'</li>
+  <li>mesa/util: add missing va_end() after va_copy()</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (4):</p>
+<ul>
+  <li>radv: Use build ID if available for cache UUID.</li>
+  <li>radv: Only allow 16 user SGPRs for compute on GFX9+.</li>
+  <li>radv: Set the user SGPR MSB for Vega.</li>
+  <li>radv: Fix driver UUID SHA1 init.</li>
+</ul>
+
+<p>Christopher Egert (1):</p>
+<ul>
+  <li>radeon: fix ColorMask</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>virgl: don't send a shader create with no data. (v2)</li>
+</ul>
+
+<p>Dylan Baker (10):</p>
+<ul>
+  <li>docs/relnotes: Add sha256 sums for mesa 18.1.8</li>
+  <li>cherry-ignore: Add additional 18.2 patch</li>
+  <li>meson: Print a message about why a libdrm version was selected</li>
+  <li>cherry-ignore: add another 18.2 patch</li>
+  <li>cherry-ignore: Add patches that don't apply cleanly and are for developer tools</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: add 18.2 patchs</li>
+  <li>cherry-ignore: add a patch that was reverted on master</li>
+  <li>cherry-ignore: one final update</li>
+  <li>Bump version to 18.1.9</li>
+</ul>
+
+<p>Erik Faye-Lund (2):</p>
+<ul>
+  <li>winsys/virgl: avoid unintended behavior</li>
+  <li>virgl: adjust strides when mapping temp-resources</li>
+</ul>
+
+<p>Gert Wollny (1):</p>
+<ul>
+  <li>winsys/virgl: correct resource and handle allocation (v2)</li>
+</ul>
+
+<p>Jason Ekstrand (6):</p>
+<ul>
+  <li>anv/pipeline: Only consider double elements which actually exist</li>
+  <li>i965: Workaround the gen9 hw astc5x5 sampler bug</li>
+  <li>anv: Re-emit vertex buffers when the pipeline changes</li>
+  <li>anv: Disable the vertex cache when tessellating on SKL GT4</li>
+  <li>anv: Clamp scissors to the framebuffer boundary</li>
+  <li>anv/query: Write both dwords in emit_zero_queries</li>
+</ul>
+
+<p>Josh Pieper (1):</p>
+<ul>
+  <li>st/mesa: Validate the result of pipe_transfer_map in make_texture (v2)</li>
+</ul>
+
+<p>Kenneth Feng (1):</p>
+<ul>
+  <li>amd: Add Picasso device id</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>st/mesa: help fix stencil border color for GL_DEPTH_STENCIL textures</li>
+  <li>radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI</li>
+  <li>r600: fix HTILE for NPOT textures with mipmapping</li>
+  <li>radeonsi: fix printing a BO list into ddebug reports</li>
+</ul>
+
+<p>Mathias Fröhlich (1):</p>
+<ul>
+  <li>tnl: Fix green gun regression in xonotic.</li>
+</ul>
+
+<p>Mauro Rossi (3):</p>
+<ul>
+  <li>android: broadcom/genxml: fix collision with intel/genxml header-gen macro</li>
+  <li>android: broadcom/cle: add gallium include path</li>
+  <li>android: broadcom/cle: export the broadcom top level path headers</li>
+</ul>
+
+<p>Michal Srb (1):</p>
+<ul>
+  <li>st/dri: don't set queryDmaBufFormats/queryDmaBufModifiers if the driver does not implement it</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>loader/dri3: Only wait for back buffer fences in dri3_get_buffer</li>
+</ul>
+
+<p>Pierre Moreau (1):</p>
+<ul>
+  <li>nvir: Always split 64-bit IMAD/IMUL operations</li>
+</ul>
+
+<p>Sergii Romantsov (1):</p>
+<ul>
+  <li>intel: compiler option msse2 and mstackrealign</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>glsl: fixer lexer for unreachable defines</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -236,3 +236,4 @@ CHIPSET(0x69A3, VEGA12)
 CHIPSET(0x69AF, VEGA12)

 CHIPSET(0x15DD, RAVEN)
+CHIPSET(0x15D8, RAVEN)
--- a/meson.build
+++ b/meson.build
@@ -1068,12 +1068,17 @@ _libdrm_checks = [

 # Loop over the enables versions and get the highest libdrm requirement for all
 # active drivers.
+_drm_blame = ''
 foreach d : _libdrm_checks
  ver = get_variable('_drm_@0@_ver'.format(d[0]))
  if d[1] and ver.version_compare('>' + _drm_ver)
    _drm_ver = ver
+    _drm_blame = d[0]
  endif
 endforeach
+if _drm_blame != ''
+  message('libdrm @0@ needed because @1@ has the highest requirement'.format(_drm_ver, _drm_blame))
+endif

 # Then get each libdrm module
 foreach d : _libdrm_checks
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -9123,7 +9123,9 @@
 #define    CIK_SDMA_PACKET_SEMAPHORE               0x7
 #define    CIK_SDMA_PACKET_CONSTANT_FILL           0xb
 #define    CIK_SDMA_PACKET_SRBM_WRITE              0xe
-#define    CIK_SDMA_COPY_MAX_SIZE                  0x3fffe0
+/* There is apparently an undocumented HW "feature" that
+   prevents the HW from copying past 256 bytes of (1 << 22) */
+#define    CIK_SDMA_COPY_MAX_SIZE                  0x3fff00

 enum amd_cmp_class_flags {
 	S_NAN = 1 << 0,        // Signaling NaN
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -45,22 +45,51 @@
 #include "sid.h"
 #include "gfx9d.h"
 #include "addrlib/gfx9/chip/gfx9_enum.h"
+#include "util/build_id.h"
 #include "util/debug.h"
+#include "util/mesa-sha1.h"
+
+static bool
+radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
+{
+	uint32_t timestamp;
+
+#ifdef HAVE_DL_ITERATE_PHDR
+	const struct build_id_note *note = NULL;
+	if ((note = build_id_find_nhdr_for_addr(ptr))) {
+		_mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
+	} else
+#endif
+	if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
+		if (!timestamp) {
+			fprintf(stderr, "radv: The provided filesystem timestamp for the cache is bogus!\n");
+		}
+
+		_mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
+	} else
+		return false;
+	return true;
+}

 static int
 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
 {
-	uint32_t mesa_timestamp, llvm_timestamp;
-	uint16_t f = family;
+	struct mesa_sha1 ctx;
+	unsigned char sha1[20];
+	unsigned ptr_size = sizeof(void*);
+
 	memset(uuid, 0, VK_UUID_SIZE);
-	if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
-	    !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
+	_mesa_sha1_init(&ctx);
+
+	if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
+	    !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
 		return -1;

-	memcpy(uuid, &mesa_timestamp, 4);
-	memcpy((char*)uuid + 4, &llvm_timestamp, 4);
-	memcpy((char*)uuid + 8, &f, 2);
-	snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
+	_mesa_sha1_update(&ctx, &family, sizeof(family));
+	_mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
+	_mesa_sha1_final(&ctx, sha1);
+
+	memcpy(uuid, sha1, VK_UUID_SIZE);
 	return 0;
 }

@@ -1860,10 +1889,30 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff
 		device->physical_device->rad_info.family != CHIP_CARRIZO &&
 		device->physical_device->rad_info.family != CHIP_STONEY;
 	unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
-	unsigned max_offchip_buffers = max_offchip_buffers_per_se *
-		device->physical_device->rad_info.max_se;
+	unsigned max_offchip_buffers;
 	unsigned offchip_granularity;
 	unsigned hs_offchip_param;
+
+	/*
+	 * Per RadeonSI:
+	 * This must be one less than the maximum number due to a hw limitation.
+         * Various hardware bugs in SI, CIK, and GFX9 need this.
+	 *
+	 * Per AMDVLK:
+	 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
+	 * Gfx7 should limit max_offchip_buffers to 508
+	 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
+	 *
+	 * Follow AMDVLK here.
+	 */
+	if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
+	    device->physical_device->rad_info.chip_class == CIK ||
+	    device->physical_device->rad_info.chip_class == SI)
+		--max_offchip_buffers_per_se;
+
+	max_offchip_buffers = max_offchip_buffers_per_se *
+		device->physical_device->rad_info.max_se;
+
 	switch (device->tess_offchip_block_dw_size) {
 	default:
 		assert(0);
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1180,6 +1180,25 @@ static VkResult radv_get_image_format_properties(struct radv_physical_device *ph
 		}
 	}

+	if (info->usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
+		if (!(format_feature_flags & VK_FORMAT_FEATURE_TRANSFER_SRC_BIT)) {
+			goto unsupported;
+		}
+	}
+
+	if (info->usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
+		if (!(format_feature_flags & VK_FORMAT_FEATURE_TRANSFER_DST_BIT)) {
+			goto unsupported;
+		}
+	}
+
+	if (info->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
+		if (!(format_feature_flags & (VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
+		                              VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT))) {
+			goto unsupported;
+		}
+	}
+
 	*pImageFormatProperties = (VkImageFormatProperties) {
 		.maxExtent = maxExtent,
 		.maxMipLevels = maxMipLevels,
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -830,8 +830,8 @@ radv_image_get_cmask_info(struct radv_device *device,

 	unsigned base_align = num_pipes * pipe_interleave_bytes;

-	unsigned width = align(image->info.width, cl_width*8);
-	unsigned height = align(image->info.height, cl_height*8);
+	unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
+	unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
 	unsigned slice_elements = (width * height) / (8*8);

 	/* Each element of CMASK is a nibble. */
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -583,7 +583,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
 	if (ctx->shader_info->info.loads_push_constants)
 		user_sgpr_info->sgpr_count += 2;

-	uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
+	uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
 	uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;

 	if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
@@ -1944,9 +1944,10 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
 	int idx = variable->data.location;
 	unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
 	LLVMValueRef interp;
+	uint64_t mask;

 	variable->data.driver_location = idx * 4;
-	ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
+	mask = ((1ull << attrib_count) - 1) << variable->data.location;

 	if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
 		unsigned interp_type;
@@ -1964,6 +1965,15 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
 	for (unsigned i = 0; i < attrib_count; ++i)
 		ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;

+	if (idx == VARYING_SLOT_CLIP_DIST0) {
+		/* Do not account for the number of components inside the array
+		 * of clip/cull distances because this might wrongly set other
+		 * bits like primitive ID or layer.
+		 */
+		mask = 1ull << VARYING_SLOT_CLIP_DIST0;
+	}
+
+	ctx->input_mask |= mask;
 }

 static void
@@ -2028,6 +2038,17 @@ handle_fs_inputs(struct radv_shader_context *ctx,
 			if (!interp_param)
 				ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
 			++index;
+		} else if (i == VARYING_SLOT_CLIP_DIST0) {
+			int length = ctx->shader_info->info.ps.num_input_clips_culls;
+
+			for (unsigned j = 0; j < length; j += 4) {
+				inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
+
+				interp_param = *inputs;
+				interp_fs_input(ctx, index, interp_param,
+						ctx->abi.prim_mask, inputs);
+				++index;
+			}
 		} else if (i == VARYING_SLOT_POS) {
 			for(int i = 0; i < 3; ++i)
 				inputs[i] = ctx->abi.frag_pos[i];
@@ -2295,6 +2316,13 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
 		memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
 		       &args, sizeof(args));

+		/* Export the clip/cull distances values to the next stage. */
+		radv_export_param(ctx, param_count, &slots[0], 0xf);
+		outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
+		if (ctx->num_output_clips + ctx->num_output_culls > 4) {
+			radv_export_param(ctx, param_count, &slots[4], 0xf);
+			outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
+		}
 	}

 	LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3050,6 +3050,23 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
 		ps_offset++;
 	}

+	if (ps->info.info.ps.num_input_clips_culls) {
+		unsigned vs_offset;
+
+		vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
+		if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
+			ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+			++ps_offset;
+		}
+
+		vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
+		if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
+		    ps->info.info.ps.num_input_clips_culls > 4) {
+			ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
+			++ps_offset;
+		}
+	}
+
 	for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
 		unsigned vs_offset;
 		bool flat_shade;
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -379,7 +379,8 @@ radv_fill_shader_variant(struct radv_device *device,

 	variant->code_size = binary->code_size;
 	variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
-			S_00B12C_SCRATCH_EN(scratch_enabled);
+			 S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
+			 S_00B12C_SCRATCH_EN(scratch_enabled);

 	variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 		S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -171,6 +171,7 @@ struct radv_shader_info {
 		bool has_pcoord;
 		bool prim_id_input;
 		bool layer_input;
+		uint8_t num_input_clips_culls;
 	} ps;
 	struct {
 		bool uses_grid_size;
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -293,6 +293,7 @@ static void
 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 			  struct radv_shader_info *info)
 {
+	unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 	const struct glsl_type *type = glsl_without_array(var->type);
 	int idx = var->data.location;

@@ -306,6 +307,9 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 	case VARYING_SLOT_LAYER:
 		info->ps.layer_input = true;
 		break;
+	case VARYING_SLOT_CLIP_DIST0:
+		info->ps.num_input_clips_culls = attrib_count;
+		break;
 	default:
 		break;
 	}
--- a/src/broadcom/Android.cle.mk
+++ b/src/broadcom/Android.cle.mk
@@ -29,6 +29,10 @@ LOCAL_SRC_FILES := $(BROADCOM_DECODER_FILES)

 LOCAL_STATIC_LIBRARIES := libmesa_broadcom_genxml

+LOCAL_C_INCLUDES += $(MESA_TOP)/src/gallium/include
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_PATH)
+
 LOCAL_SHARED_LIBRARIES := libexpat libz

 include $(MESA_COMMON_MK)
--- a/src/broadcom/Android.genxml.mk
+++ b/src/broadcom/Android.genxml.mk
@@ -39,7 +39,7 @@ $(intermediates)/dummy.c:
 # This is the list of auto-generated files headers
 LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/broadcom/, $(BROADCOM_GENXML_GENERATED_FILES))

-define header-gen
+define pack-header-gen
 	@mkdir -p $(dir $@)
 	@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
 	$(hide) $(PRIVATE_SCRIPT) $(PRIVATE_SCRIPT_FLAGS) $(PRIVATE_XML) > $@
@@ -48,22 +48,22 @@ endef
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v21.xml
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v21.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v33.xml
 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v33.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v41.xml
 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v41.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v42.xml
 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v42.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_xml.h: $(addprefix $(MESA_TOP)/src/broadcom/,$(BROADCOM_GENXML_XML_FILES)) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
 	@mkdir -p $(dir $@)
--- a/src/compiler/glsl/glcpp/glcpp-lex.l
+++ b/src/compiler/glsl/glcpp/glcpp-lex.l
@@ -289,6 +289,7 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
         * token. */
 	if (parser->first_non_space_token_this_line) {
 		BEGIN HASH;
+		yyextra->in_define = false;
 	}

 	RETURN_TOKEN_NEVER_SKIP (HASH_TOKEN);
@@ -336,43 +337,55 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
 	/* For the pre-processor directives, we return these tokens
 	 * even when we are otherwise skipping. */
 <HASH>ifdef {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IFDEF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IFDEF);
+	}
 }

 <HASH>ifndef {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IFNDEF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IFNDEF);
+	}
 }

 <HASH>if/[^_a-zA-Z0-9] {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IF);
+	}
 }

 <HASH>elif/[^_a-zA-Z0-9] {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ELIF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ELIF);
+	}
 }

 <HASH>else {
-	BEGIN INITIAL;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ELSE);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ELSE);
+	}
 }

 <HASH>endif {
-	BEGIN INITIAL;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ENDIF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ENDIF);
+	}
 }

 <HASH>error[^\r\n]* {
@@ -399,7 +412,8 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
 	 *	  and not whitespace). This will generate an error.
 	 */
 <HASH>define{HSPACE}* {
-	if (! parser->skipping) {
+	yyextra->in_define = true;
+	if (!parser->skipping) {
 		BEGIN DEFINE;
 		yyextra->space_tokens = 0;
 		RETURN_TOKEN (DEFINE_TOKEN);
--- a/src/compiler/glsl/glcpp/glcpp.h
+++ b/src/compiler/glsl/glcpp/glcpp.h
@@ -197,6 +197,7 @@ struct glcpp_parser {
 	int first_non_space_token_this_line;
 	int newline_as_space;
 	int in_control_line;
+	bool in_define;
 	int paren_count;
 	int commented_newlines;
 	skip_node_t *skip_stack;
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -667,8 +667,8 @@ public:
       * variable has been used.  For example, it is an error to redeclare a
       * variable as invariant after it has been used.
       *
-       * This is only maintained in the ast_to_hir.cpp path, not in
-       * Mesa's fixed function or ARB program paths.
+       * This is maintained in the ast_to_hir.cpp path and during linking,
+       * but not in Mesa's fixed function or ARB program paths.
       */
      unsigned used:1;

--- a/src/compiler/glsl/link_interface_blocks.cpp
+++ b/src/compiler/glsl/link_interface_blocks.cpp
@@ -417,9 +417,15 @@ validate_interstage_inout_blocks(struct gl_shader_program *prog,
       * write to any of the pre-defined outputs (e.g. if the vertex shader
       * does not write to gl_Position, etc), which is allowed and results in
       * undefined behavior.
+       *
+       * From Section 4.3.4 (Inputs) of the GLSL 1.50 spec:
+       *
+       *    "Only the input variables that are actually read need to be written
+       *     by the previous stage; it is allowed to have superfluous
+       *     declarations of input variables."
       */
      if (producer_def == NULL &&
-          !is_builtin_gl_in_block(var, consumer->Stage)) {
+          !is_builtin_gl_in_block(var, consumer->Stage) && var->data.used) {
         linker_error(prog, "Input block `%s' is not an output of "
                      "the previous stage\n", var->get_interface_type()->name);
         return;
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -427,13 +427,13 @@ optimizations = [
                           ('unpack_64_2x32_split_y', a)), a),

   # Byte extraction
-   (('ushr', a, 24), ('extract_u8', a, 3), '!options->lower_extract_byte'),
+   (('ushr', 'a@32', 24), ('extract_u8', a, 3), '!options->lower_extract_byte'),
   (('iand', 0xff, ('ushr', a, 16)), ('extract_u8', a, 2), '!options->lower_extract_byte'),
   (('iand', 0xff, ('ushr', a,  8)), ('extract_u8', a, 1), '!options->lower_extract_byte'),
   (('iand', 0xff, a), ('extract_u8', a, 0), '!options->lower_extract_byte'),

    # Word extraction
-   (('ushr', a, 16), ('extract_u16', a, 1), '!options->lower_extract_word'),
+   (('ushr', 'a@32', 16), ('extract_u16', a, 1), '!options->lower_extract_word'),
   (('iand', 0xffff, a), ('extract_u16', a, 0), '!options->lower_extract_word'),

   # Subtracts
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -2223,13 +2223,13 @@ dri2_check_dma_buf_attribs(const _EGLImageAttribs *attrs)
   return EGL_TRUE;
 }

-/* Returns the total number of file descriptors. Zero indicates an error. */
+/* Returns the total number of planes for the format or zero if it isn't a
+ * valid fourcc format.
+ */
 static unsigned
-dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
+dri2_num_fourcc_format_planes(EGLint format)
 {
-   unsigned plane_n;
-
-   switch (attrs->DMABufFourCC.Value) {
+   switch (format) {
   case DRM_FORMAT_R8:
   case DRM_FORMAT_RG88:
   case DRM_FORMAT_GR88:
@@ -2277,14 +2277,14 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
   case DRM_FORMAT_YVYU:
   case DRM_FORMAT_UYVY:
   case DRM_FORMAT_VYUY:
-      plane_n = 1;
-      break;
+      return 1;
+
   case DRM_FORMAT_NV12:
   case DRM_FORMAT_NV21:
   case DRM_FORMAT_NV16:
   case DRM_FORMAT_NV61:
-      plane_n = 2;
-      break;
+      return 2;
+
   case DRM_FORMAT_YUV410:
   case DRM_FORMAT_YVU410:
   case DRM_FORMAT_YUV411:
@@ -2295,9 +2295,19 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
   case DRM_FORMAT_YVU422:
   case DRM_FORMAT_YUV444:
   case DRM_FORMAT_YVU444:
-      plane_n = 3;
-      break;
+      return 3;
+
   default:
+      return 0;
+   }
+}
+
+/* Returns the total number of file descriptors. Zero indicates an error. */
+static unsigned
+dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
+{
+   unsigned plane_n = dri2_num_fourcc_format_planes(attrs->DMABufFourCC.Value);
+   if (plane_n == 0) {
      _eglError(EGL_BAD_ATTRIBUTE, "invalid format");
      return 0;
   }
@@ -2371,6 +2381,18 @@ dri2_query_dma_buf_formats(_EGLDriver *drv, _EGLDisplay *disp,
                                            formats, count))
      return EGL_FALSE;

+   if (max > 0) {
+      /* Assert that all of the formats returned are actually fourcc formats.
+       * Some day, if we want the internal interface function to be able to
+       * return the fake fourcc formats defined in dri_interface.h, we'll have
+       * to do something more clever here to pair the list down to just real
+       * fourcc formats so that we don't leak the fake internal ones.
+       */
+      for (int i = 0; i < *count; i++) {
+         assert(dri2_num_fourcc_format_planes(formats[i]) > 0);
+      }
+   }
+
   return EGL_TRUE;
 }

@@ -2381,6 +2403,9 @@ dri2_query_dma_buf_modifiers(_EGLDriver *drv, _EGLDisplay *disp, EGLint format,
 {
   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);

+   if (dri2_num_fourcc_format_planes(format) == 0)
+      return _eglError(EGL_BAD_PARAMETER, "invalid fourcc format");
+
   if (max < 0)
      return _eglError(EGL_BAD_PARAMETER, "invalid value for max count of formats");

--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -292,6 +292,7 @@ struct dri2_egl_surface
   struct {
 #ifdef HAVE_WAYLAND_PLATFORM
      struct wl_buffer   *wl_buffer;
+      bool                wl_release;
      __DRIimage         *dri_image;
      /* for is_different_gpu case. NULL else */
      __DRIimage         *linear_copy;
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -179,9 +179,12 @@ wl_buffer_release(void *data, struct wl_buffer *buffer)
      if (dri2_surf->color_buffers[i].wl_buffer == buffer)
         break;

-   if (i == ARRAY_SIZE(dri2_surf->color_buffers)) {
+   assert (i < ARRAY_SIZE(dri2_surf->color_buffers));
+
+   if (dri2_surf->color_buffers[i].wl_release) {
      wl_buffer_destroy(buffer);
-      return;
+      dri2_surf->color_buffers[i].wl_release = false;
+      dri2_surf->color_buffers[i].wl_buffer = NULL;
   }

   dri2_surf->color_buffers[i].locked = false;
@@ -417,9 +420,14 @@ dri2_wl_release_buffers(struct dri2_egl_surface *dri2_surf)
      dri2_egl_display(dri2_surf->base.Resource.Display);

   for (int i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
-      if (dri2_surf->color_buffers[i].wl_buffer &&
-          !dri2_surf->color_buffers[i].locked)
-         wl_buffer_destroy(dri2_surf->color_buffers[i].wl_buffer);
+      if (dri2_surf->color_buffers[i].wl_buffer) {
+         if (dri2_surf->color_buffers[i].locked) {
+            dri2_surf->color_buffers[i].wl_release = true;
+         } else {
+            wl_buffer_destroy(dri2_surf->color_buffers[i].wl_buffer);
+            dri2_surf->color_buffers[i].wl_buffer = NULL;
+         }
+      }
      if (dri2_surf->color_buffers[i].dri_image)
         dri2_dpy->image->destroyImage(dri2_surf->color_buffers[i].dri_image);
      if (dri2_surf->color_buffers[i].linear_copy)
@@ -428,11 +436,9 @@ dri2_wl_release_buffers(struct dri2_egl_surface *dri2_surf)
         munmap(dri2_surf->color_buffers[i].data,
                dri2_surf->color_buffers[i].data_size);

-      dri2_surf->color_buffers[i].wl_buffer = NULL;
      dri2_surf->color_buffers[i].dri_image = NULL;
      dri2_surf->color_buffers[i].linear_copy = NULL;
      dri2_surf->color_buffers[i].data = NULL;
-      dri2_surf->color_buffers[i].locked = false;
   }

   if (dri2_dpy->dri2)
@@ -961,6 +967,8 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
      dri2_surf->current->wl_buffer =
         create_wl_buffer(dri2_dpy, dri2_surf, image);

+      dri2_surf->current->wl_release = false;
+
      wl_buffer_add_listener(dri2_surf->current->wl_buffer,
                             &wl_buffer_listener, dri2_surf);
   }
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -114,6 +114,7 @@ if with_platform_drm
 endif
 if with_platform_surfaceless
  files_egl += files('drivers/dri2/platform_surfaceless.c')
+  incs_for_egl += [inc_loader]
 endif
 if with_platform_wayland
  deps_for_egl += [dep_wayland_client, dep_wayland_server]
@@ -131,6 +132,7 @@ endif
 if with_platform_android
  deps_for_egl += dep_android
  files_egl += files('drivers/dri2/platform_android.c')
+  incs_for_egl += [inc_loader]
 endif
 if with_platform_haiku
  incs_for_egl += inc_haikugl
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3797,7 +3797,7 @@ Program::optimizeSSA(int level)
   RUN_PASS(2, AlgebraicOpt, run);
   RUN_PASS(2, ModifierFolding, run); // before load propagation -> less checks
   RUN_PASS(1, ConstantFolding, foldAll);
-   RUN_PASS(1, Split64BitOpPreRA, run);
+   RUN_PASS(0, Split64BitOpPreRA, run);
   RUN_PASS(1, LoadPropagation, run);
   RUN_PASS(1, IndirectPropagation, run);
   RUN_PASS(2, MemoryOpt, run);
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -774,8 +774,8 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 		return;
 	}

-	width = align(rtex->resource.b.b.width0, cl_width * 8);
-	height = align(rtex->resource.b.b.height0, cl_height * 8);
+	width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+	height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);

 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -134,12 +134,13 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,

 	if (ctx->current_saved_cs) {
 		si_trace_emit(ctx);
-		si_log_hw_flush(ctx);

 		/* Save the IB for debug contexts. */
 		si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 		ctx->current_saved_cs->flushed = true;
 		ctx->current_saved_cs->time_flush = os_time_get_nano();
+
+		si_log_hw_flush(ctx);
 	}

 	/* Flush the CS. */
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1019,8 +1019,8 @@ static void si_texture_get_htile_size(struct si_screen *sscreen,
 		return;
 	}

-	width = align(rtex->resource.b.b.width0, cl_width * 8);
-	height = align(rtex->resource.b.b.height0, cl_height * 8);
+	width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+	height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);

 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
--- a/src/gallium/drivers/tegra/tegra_screen.c
+++ b/src/gallium/drivers/tegra/tegra_screen.c
@@ -201,6 +201,7 @@ static int tegra_open_render_node(void)
         }

         if (strcmp(version->name, "nouveau") != 0) {
+            drmFreeVersion(version);
            close(fd);
            continue;
         }
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -283,7 +283,7 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
   while (left_bytes) {
      uint32_t length, offlen;
      int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
-      if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
+      if (ctx->cbuf->cdw + hdr_len + 1 >= VIRGL_MAX_CMDBUF_DWORDS)
         ctx->base.flush(&ctx->base, NULL, 0);

      thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
--- a/src/gallium/drivers/virgl/virgl_texture.c
+++ b/src/gallium/drivers/virgl/virgl_texture.c
@@ -177,6 +177,8 @@ static void *virgl_texture_transfer_map(struct pipe_context *ctx,
      /* we want to do a resolve blit into the temporary */
      hw_res = trans->resolve_tmp->hw_res;
      offset = 0;
+      trans->base.stride = ((struct virgl_texture*)trans->resolve_tmp)->stride[level];
+      trans->base.layer_stride = trans->base.stride * nblocksy;
   } else {
      offset = vrend_get_tex_image_offset(vtex, level, box->z);

--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1482,6 +1482,12 @@ dri2_query_dma_buf_formats(__DRIscreen *_screen, int max, int *formats,

   for (i = 0, j = 0; (i < ARRAY_SIZE(fourcc_formats)) &&
         (j < max || max == 0); i++) {
+      /* The sRGB format is not a real FourCC as defined by drm_fourcc.h, so we
+       * must not leak it out to clients.
+       */
+      if (fourcc_formats[i] == __DRI_IMAGE_FOURCC_SARGB8888)
+         continue;
+
      if (pscreen->is_format_supported(pscreen,
                                       fourcc_to_pipe_format(
                                          fourcc_formats[i]),
@@ -2209,8 +2215,10 @@ dri_kms_init_screen(__DRIscreen * sPriv)
      dri2ImageExtension.createImageFromFds = dri2_from_fds;
      dri2ImageExtension.createImageFromDmaBufs = dri2_from_dma_bufs;
      dri2ImageExtension.createImageFromDmaBufs2 = dri2_from_dma_bufs2;
-      dri2ImageExtension.queryDmaBufFormats = dri2_query_dma_buf_formats;
-      dri2ImageExtension.queryDmaBufModifiers = dri2_query_dma_buf_modifiers;
+      if (pscreen->query_dmabuf_modifiers) {
+         dri2ImageExtension.queryDmaBufFormats = dri2_query_dma_buf_formats;
+         dri2ImageExtension.queryDmaBufModifiers = dri2_query_dma_buf_modifiers;
+      }
   }

   sPriv->extensions = dri_screen_extensions;
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -313,7 +313,7 @@ virgl_drm_winsys_resource_cache_create(struct virgl_winsys *qws,
   struct virgl_hw_res *res, *curr_res;
   struct list_head *curr, *next;
   int64_t now;
-   int ret;
+   int ret = 0;

   /* only store binds for vertex/index/const buffers */
   if (bind != VIRGL_BIND_CONSTANT_BUFFER && bind != VIRGL_BIND_INDEX_BUFFER &&
@@ -617,13 +617,26 @@ static void virgl_drm_add_res(struct virgl_drm_winsys *qdws,
 {
   unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);

-   if (cbuf->cres > cbuf->nres) {
-      cbuf->nres += 256;
-      cbuf->res_bo = realloc(cbuf->res_bo, cbuf->nres * sizeof(struct virgl_hw_buf*));
-      if (!cbuf->res_bo) {
-          fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, cbuf->nres);
+   if (cbuf->cres >= cbuf->nres) {
+      unsigned new_nres = cbuf->nres + 256;
+      void *new_ptr = REALLOC(cbuf->res_bo,
+                              cbuf->nres * sizeof(struct virgl_hw_buf*),
+                              new_nres * sizeof(struct virgl_hw_buf*));
+      if (!new_ptr) {
+          fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, new_nres);
          return;
      }
+      cbuf->res_bo = new_ptr;
+
+      new_ptr = REALLOC(cbuf->res_hlist,
+                        cbuf->nres * sizeof(uint32_t),
+                        new_nres * sizeof(uint32_t));
+      if (!new_ptr) {
+          fprintf(stderr,"failure to add hlist relocation %d, %d\n", cbuf->cres, cbuf->nres);
+          return;
+      }
+      cbuf->res_hlist = new_ptr;
+      cbuf->nres = new_nres;
   }

   cbuf->res_bo[cbuf->cres] = NULL;
--- a/src/glx/apple/apple_glx_log.c
+++ b/src/glx/apple/apple_glx_log.c
@@ -97,6 +97,7 @@ void _apple_glx_vlog(int level, const char *file, const char *function,
        fprintf(stderr, "%-9s %24s:%-4d %s(%"PRIu64"): ",
                _asl_level_string(level), file, line, function, thread);
        vfprintf(stderr, fmt, args2);
+        va_end(args2);
    }

    msg = asl_new(ASL_TYPE_MSG);
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -104,7 +104,7 @@ noinst_LTLIBRARIES += $(VULKAN_PER_GEN_LIBS)

 VULKAN_CFLAGS = \
 	$(AM_CFLAGS) \
-	-msse2
+	-msse2 -mstackrealign

 VULKAN_CPPFLAGS = \
 	-I$(top_srcdir)/src/compiler \
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -932,8 +932,21 @@ generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);

   brw_MOV(p, dst, header);
+
+   /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
+    * Other values get <4;1,0>.
+    */
+   struct brw_reg restrided_offset;
+   if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
+       offset.width == BRW_WIDTH_4 &&
+       offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
+      restrided_offset = stride(offset, 0, 1, 0);
+   } else {
+      restrided_offset = stride(offset, 4, 1, 0);
+   }
+
   /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
-   brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
+   brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);

   brw_pop_insn_state(p);
 }
--- a/src/intel/compiler/brw_vec4_tes.cpp
+++ b/src/intel/compiler/brw_vec4_tes.cpp
@@ -185,9 +185,19 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
         first_component /= 2;

      if (indirect_offset.file != BAD_FILE) {
+         src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type);
+
+         /* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the
+          * valid range of the offset is [0, 0FFFFFFFh].
+          */
+         emit_minmax(BRW_CONDITIONAL_L,
+                     dst_reg(clamped_indirect_offset),
+                     retype(indirect_offset, BRW_REGISTER_TYPE_UD),
+                     brw_imm_ud(0x0fffffffu));
+
         header = src_reg(this, glsl_type::uvec4_type);
         emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
-              input_read_header, indirect_offset);
+              input_read_header, clamped_indirect_offset);
      } else {
         /* Arbitrarily only push up to 24 vec4 slots worth of data,
          * which is 12 registers (since each holds 2 vec4 slots).
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -294,6 +294,29 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
    */
   if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
      *flags &= ~ISL_TILING_Y0_BIT;
+
+   /* From the BDW and SKL PRMs, Volume 2d,
+    * RENDER_SURFACE_STATE::Width - Programming Notes:
+    *
+    *   A known issue exists if a primitive is rendered to the first 2 rows and
+    *   last 2 columns of a 16K width surface. If any geometry is drawn inside
+    *   this square it will be copied to column X=2 and X=3 (arrangement on Y
+    *   position will stay the same). If any geometry exceeds the boundaries of
+    *   this 2x2 region it will be drawn normally. The issue also only occurs
+    *   if the surface has TileMode != Linear.
+    *
+    * [Internal documentation notes that this issue isn't present on SKL GT4.]
+    * To prevent this rendering corruption, only allow linear tiling for
+    * surfaces with widths greater than 16K-2 pixels.
+    *
+    * TODO: Is this an issue for multisampled surfaces as well?
+    */
+   if (info->width > 16382 && info->samples == 1 &&
+       info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
+       (ISL_DEV_GEN(dev) == 8 ||
+        (dev->info->is_skylake && dev->info->gt != 4))) {
+          *flags &= ISL_TILING_LINEAR_BIT;
+   }
 }

 void
--- a/src/intel/meson.build
+++ b/src/intel/meson.build
@@ -18,6 +18,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.

+c_sse2_args = ['-msse2', '-mstackrealign']
 inc_intel = include_directories('.')

 subdir('blorp')
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -533,82 +533,86 @@ void anv_CmdBlitImage(
      const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
      const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;

-      get_blorp_surf_for_anv_image(cmd_buffer->device,
-                                   src_image, src_res->aspectMask,
-                                   srcImageLayout, ISL_AUX_USAGE_NONE, &src);
-      get_blorp_surf_for_anv_image(cmd_buffer->device,
-                                   dst_image, dst_res->aspectMask,
-                                   dstImageLayout, ISL_AUX_USAGE_NONE, &dst);
+      assert(anv_image_aspects_compatible(src_res->aspectMask,
+                                          dst_res->aspectMask));

-      struct anv_format_plane src_format =
-         anv_get_format_plane(&cmd_buffer->device->info, src_image->vk_format,
-                              src_res->aspectMask, src_image->tiling);
-      struct anv_format_plane dst_format =
-         anv_get_format_plane(&cmd_buffer->device->info, dst_image->vk_format,
-                              dst_res->aspectMask, dst_image->tiling);
+      uint32_t aspect_bit;
+      anv_foreach_image_aspect_bit(aspect_bit, src_image, src_res->aspectMask) {
+         get_blorp_surf_for_anv_image(cmd_buffer->device,
+                                      src_image, 1U << aspect_bit,
+                                      srcImageLayout, ISL_AUX_USAGE_NONE, &src);
+         get_blorp_surf_for_anv_image(cmd_buffer->device,
+                                      dst_image, 1U << aspect_bit,
+                                      dstImageLayout, ISL_AUX_USAGE_NONE, &dst);

-      unsigned dst_start, dst_end;
-      if (dst_image->type == VK_IMAGE_TYPE_3D) {
-         assert(dst_res->baseArrayLayer == 0);
-         dst_start = pRegions[r].dstOffsets[0].z;
-         dst_end = pRegions[r].dstOffsets[1].z;
-      } else {
-         dst_start = dst_res->baseArrayLayer;
-         dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
+         struct anv_format_plane src_format =
+            anv_get_format_plane(&cmd_buffer->device->info, src_image->vk_format,
+                                 1U << aspect_bit, src_image->tiling);
+         struct anv_format_plane dst_format =
+            anv_get_format_plane(&cmd_buffer->device->info, dst_image->vk_format,
+                                 1U << aspect_bit, dst_image->tiling);
+
+         unsigned dst_start, dst_end;
+         if (dst_image->type == VK_IMAGE_TYPE_3D) {
+            assert(dst_res->baseArrayLayer == 0);
+            dst_start = pRegions[r].dstOffsets[0].z;
+            dst_end = pRegions[r].dstOffsets[1].z;
+         } else {
+            dst_start = dst_res->baseArrayLayer;
+            dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
+         }
+
+         unsigned src_start, src_end;
+         if (src_image->type == VK_IMAGE_TYPE_3D) {
+            assert(src_res->baseArrayLayer == 0);
+            src_start = pRegions[r].srcOffsets[0].z;
+            src_end = pRegions[r].srcOffsets[1].z;
+         } else {
+            src_start = src_res->baseArrayLayer;
+            src_end = src_start + anv_get_layerCount(src_image, src_res);
+         }
+
+         bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
+         float src_z_step = (float)(src_end + 1 - src_start) /
+            (float)(dst_end + 1 - dst_start);
+
+         if (flip_z) {
+            src_start = src_end;
+            src_z_step *= -1;
+         }
+
+         unsigned src_x0 = pRegions[r].srcOffsets[0].x;
+         unsigned src_x1 = pRegions[r].srcOffsets[1].x;
+         unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
+         unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
+         bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
+
+         unsigned src_y0 = pRegions[r].srcOffsets[0].y;
+         unsigned src_y1 = pRegions[r].srcOffsets[1].y;
+         unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
+         unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
+         bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
+
+         const unsigned num_layers = dst_end - dst_start;
+         anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
+                                           1U << aspect_bit,
+                                           dst.aux_usage,
+                                           dst_res->mipLevel,
+                                           dst_start, num_layers);
+
+         for (unsigned i = 0; i < num_layers; i++) {
+            unsigned dst_z = dst_start + i;
+            unsigned src_z = src_start + i * src_z_step;
+
+            blorp_blit(&batch, &src, src_res->mipLevel, src_z,
+                       src_format.isl_format, src_format.swizzle,
+                       &dst, dst_res->mipLevel, dst_z,
+                       dst_format.isl_format, dst_format.swizzle,
+                       src_x0, src_y0, src_x1, src_y1,
+                       dst_x0, dst_y0, dst_x1, dst_y1,
+                       gl_filter, flip_x, flip_y);
+         }
      }
-
-      unsigned src_start, src_end;
-      if (src_image->type == VK_IMAGE_TYPE_3D) {
-         assert(src_res->baseArrayLayer == 0);
-         src_start = pRegions[r].srcOffsets[0].z;
-         src_end = pRegions[r].srcOffsets[1].z;
-      } else {
-         src_start = src_res->baseArrayLayer;
-         src_end = src_start + anv_get_layerCount(src_image, src_res);
-      }
-
-      bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
-      float src_z_step = (float)(src_end + 1 - src_start) /
-                         (float)(dst_end + 1 - dst_start);
-
-      if (flip_z) {
-         src_start = src_end;
-         src_z_step *= -1;
-      }
-
-      unsigned src_x0 = pRegions[r].srcOffsets[0].x;
-      unsigned src_x1 = pRegions[r].srcOffsets[1].x;
-      unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
-      unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
-      bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
-
-      unsigned src_y0 = pRegions[r].srcOffsets[0].y;
-      unsigned src_y1 = pRegions[r].srcOffsets[1].y;
-      unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
-      unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
-      bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
-
-      const unsigned num_layers = dst_end - dst_start;
-      anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
-                                        dst_res->aspectMask,
-                                        dst.aux_usage,
-                                        dst_res->mipLevel,
-                                        dst_start, num_layers);
-
-      for (unsigned i = 0; i < num_layers; i++) {
-         unsigned dst_z = dst_start + i;
-         unsigned src_z = src_start + i * src_z_step;
-
-         blorp_blit(&batch, &src, src_res->mipLevel, src_z,
-                    src_format.isl_format, src_format.swizzle,
-                    &dst, dst_res->mipLevel, dst_z,
-                    dst_format.isl_format,
-                    anv_swizzle_for_render(dst_format.swizzle),
-                    src_x0, src_y0, src_x1, src_y1,
-                    dst_x0, dst_y0, dst_x1, dst_y1,
-                    gl_filter, flip_x, flip_y);
-      }
-
   }

   blorp_batch_finish(&batch);
@@ -1583,6 +1587,24 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
                                   ISL_AUX_USAGE_NONE, &stencil);
   }

+   /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
+    *
+    *    "The following is required when performing a depth buffer clear with
+    *    using the WM_STATE or 3DSTATE_WM:
+    *
+    *       * If other rendering operations have preceded this clear, a
+    *         PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
+    *         enabled must be issued before the rectangle primitive used for
+    *         the depth buffer clear operation.
+    *       * [...]"
+    *
+    * Even though the PRM only says that this is required if using 3DSTATE_WM
+    * and a 3DPRIMITIVE, it appears to also sometimes hang when doing a clear
+    * with WM_HZ_OP.
+    */
+   cmd_buffer->state.pending_pipe_bits |=
+      ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+
   blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil,
                                 level, base_layer, layer_count,
                                 area.offset.x, area.offset.y,
@@ -1597,18 +1619,22 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,

   /* From the SKL PRM, Depth Buffer Clear:
    *
-    * Depth Buffer Clear Workaround
-    * Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
-    * or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
-    * DEPTH_STALL bit and Depth FLUSH bits “set” before starting to render.
-    * DepthStall and DepthFlush are not needed between consecutive depth clear
-    * passes nor is it required if the depth-clear pass was done with
-    * “full_surf_clear” bit set in the 3DSTATE_WM_HZ_OP.
+    *    "Depth Buffer Clear Workaround
+    *
+    *    Depth buffer clear pass using any of the methods (WM_STATE,
+    *    3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
+    *    command with DEPTH_STALL bit and Depth FLUSH bits “set” before
+    *    starting to render.  DepthStall and DepthFlush are not needed between
+    *    consecutive depth clear passes nor is it required if the depth-clear
+    *    pass was done with “full_surf_clear” bit set in the
+    *    3DSTATE_WM_HZ_OP."
+    *
+    * Even though the PRM provides a bunch of conditions under which this is
+    * supposedly unnecessary, we choose to perform the flush unconditionally
+    * just to be safe.
    */
-   if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
-      cmd_buffer->state.pending_pipe_bits |=
-         ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
-   }
+   cmd_buffer->state.pending_pipe_bits |=
+      ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
 }

 void
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -48,6 +48,7 @@ clamp_int64(int64_t x, int64_t min, int64_t max)
 void
 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 {
+   struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
   uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
   const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
   struct anv_state scissor_state =
@@ -73,8 +74,8 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
         /* Do this math using int64_t so overflow gets clamped correctly. */
         .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
         .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
-         .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
-         .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
+         .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, fb->height - 1),
+         .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, fb->width - 1)
      };

      if (s->extent.width <= 0 || s->extent.height <= 0) {
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2475,6 +2475,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
   uint32_t *p;

   uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
+   if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
+      vb_emit |= pipeline->vb_used;

   assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);

@@ -2599,7 +2601,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
                                          pipeline->depth_clamp_enable);
   }

-   if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
+   if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
+                                      ANV_CMD_DIRTY_RENDER_TARGETS))
      gen7_cmd_buffer_emit_scissor(cmd_buffer);

   genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -91,7 +91,8 @@ emit_vertex_input(struct anv_pipeline *pipeline,

   /* Pull inputs_read out of the VS prog data */
   const uint64_t inputs_read = vs_prog_data->inputs_read;
-   const uint64_t double_inputs_read = vs_prog_data->double_inputs_read;
+   const uint64_t double_inputs_read =
+      vs_prog_data->double_inputs_read & inputs_read;
   assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
   const uint32_t elements = inputs_read >> VERT_ATTRIB_GENERIC0;
   const uint32_t elements_double = double_inputs_read >> VERT_ATTRIB_GENERIC0;
@@ -115,7 +116,34 @@ emit_vertex_input(struct anv_pipeline *pipeline,
                       GENX(3DSTATE_VERTEX_ELEMENTS));
   if (!p)
      return;
-   memset(p + 1, 0, (num_dwords - 1) * 4);
+
+   for (uint32_t i = 0; i < total_elems; i++) {
+      /* The SKL docs for VERTEX_ELEMENT_STATE say:
+       *
+       *    "All elements must be valid from Element[0] to the last valid
+       *    element. (I.e. if Element[2] is valid then Element[1] and
+       *    Element[0] must also be valid)."
+       *
+       * The SKL docs for 3D_Vertex_Component_Control say:
+       *
+       *    "Don't store this component. (Not valid for Component 0, but can
+       *    be used for Component 1-3)."
+       *
+       * So we can't just leave a vertex element blank and hope for the best.
+       * We have to tell the VF hardware to put something in it; so we just
+       * store a bunch of zero.
+       *
+       * TODO: Compact vertex elements so we never end up with holes.
+       */
+      struct GENX(VERTEX_ELEMENT_STATE) element = {
+         .Valid = true,
+         .Component0Control = VFCOMP_STORE_0,
+         .Component1Control = VFCOMP_STORE_0,
+         .Component2Control = VFCOMP_STORE_0,
+         .Component3Control = VFCOMP_STORE_0,
+      };
+      GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
+   }

   for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
      const VkVertexInputAttributeDescription *desc =
@@ -1145,7 +1173,28 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
      vs.IllegalOpcodeExceptionEnable = false;
      vs.SoftwareExceptionEnable    = false;
      vs.MaximumNumberofThreads     = devinfo->max_vs_threads - 1;
-      vs.VertexCacheDisable         = false;
+
+      if (GEN_GEN == 9 && devinfo->gt == 4 &&
+          anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
+         /* On Sky Lake GT4, we have experienced some hangs related to the VS
+          * cache and tessellation.  It is unknown exactly what is happening
+          * but the Haswell docs for the "VS Reference Count Full Force Miss
+          * Enable" field of the "Thread Mode" register refer to a HSW bug in
+          * which the VUE handle reference count would overflow resulting in
+          * internal reference counting bugs.  My (Jason's) best guess is that
+          * this bug cropped back up on SKL GT4 when we suddenly had more
+          * threads in play than any previous gen9 hardware.
+          *
+          * What we do know for sure is that setting this bit when
+          * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
+          * City when playing with DXVK (https://bugs.freedesktop.org/107280).
+          * Disabling the vertex cache with tessellation shaders should only
+          * have a minor performance impact as the tessellation shaders are
+          * likely generating and processing far more geometry than the vertex
+          * stage.
+          */
+         vs.VertexCacheDisable = true;
+      }

      vs.VertexURBEntryReadLength      = vs_prog_data->base.urb_read_length;
      vs.VertexURBEntryReadOffset      = 0;
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -341,6 +341,11 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
            sdi.Address.offset = slot_offset + j * sizeof(uint64_t);
            sdi.ImmediateData = 0ull;
         }
+         anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+            sdi.Address.bo = &pool->bo;
+            sdi.Address.offset = slot_offset + j * sizeof(uint64_t) + 4;
+            sdi.ImmediateData = 0ull;
+         }
      }
      emit_query_availability(cmd_buffer, &pool->bo, slot_offset);
   }
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -111,7 +111,7 @@ foreach g : [['70', ['gen7_cmd_buffer.c']], ['75', ['gen7_cmd_buffer.c']],
      inc_vulkan_wsi,
    ],
    c_args : [
-      c_vis_args, no_override_init_args, '-msse2',
+      c_vis_args, no_override_init_args, c_sse2_args,
      '-DGEN_VERSIONx10=@0@'.format(_gen),
    ],
    dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers],
@@ -155,7 +155,7 @@ anv_deps = [
 anv_flags = [
  c_vis_args,
  no_override_init_args,
-  '-msse2',
+  c_sse2_args,
 ]

 if with_platform_x11
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1736,7 +1736,9 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
      buffer = new_buffer;
      draw->buffers[buf_id] = buffer;
   }
-   dri3_fence_await(draw->conn, draw, buffer);
+
+   if (buffer_type == loader_dri3_buffer_back)
+      dri3_fence_await(draw->conn, draw, buffer);

   /*
    * Do we need to preserve the content of a previous buffer?
--- a/src/mapi/glapi/gen/KHR_robustness_es.xml
+++ b/src/mapi/glapi/gen/KHR_robustness_es.xml
@@ -60,4 +60,36 @@

 </category>

+<category name="GL_EXT_robustness" number="107">
+    <function name="GetGraphicsResetStatusEXT"
+              alias="GetGraphicsResetStatusARB" es2="2.0">
+        <return type="GLenum"/>
+    </function>
+
+    <function name="ReadnPixelsEXT" alias="ReadnPixelsARB" es2="2.0">
+        <param name="x" type="GLint"/>
+        <param name="y" type="GLint"/>
+        <param name="width" type="GLsizei"/>
+        <param name="height" type="GLsizei"/>
+        <param name="format" type="GLenum"/>
+        <param name="type" type="GLenum"/>
+        <param name="bufSize" type="GLsizei"/>
+        <param name="data" type="GLvoid *" output="true"/>
+    </function>
+
+    <function name="GetnUniformfvEXT" alias="GetnUniformfvARB" es2="2.0">
+        <param name="program" type="GLuint"/>
+        <param name="location" type="GLint"/>
+        <param name="bufSize" type="GLsizei"/>
+        <param name="params" type="GLfloat *" output="true"/>
+    </function>
+
+    <function name="GetnUniformivEXT" alias="GetnUniformivARB" es2="2.0">
+        <param name="program" type="GLuint"/>
+        <param name="location" type="GLint"/>
+        <param name="bufSize" type="GLsizei"/>
+        <param name="params" type="GLint *" output="true"/>
+    </function>
+</category>
+
 </OpenGLAPI>
--- a/src/mesa/Android.libmesa_dricore.mk
+++ b/src/mesa/Android.libmesa_dricore.mk
@@ -49,7 +49,7 @@ ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
 LOCAL_WHOLE_STATIC_LIBRARIES := \
 	libmesa_sse41
 LOCAL_CFLAGS := \
-	-msse4.1 \
+	-msse4.1 -mstackrealign \
       -DUSE_SSE41
 endif

--- a/src/mesa/Android.libmesa_sse41.mk
+++ b/src/mesa/Android.libmesa_sse41.mk
@@ -34,7 +34,7 @@ LOCAL_SRC_FILES += \
 	$(X86_SSE41_FILES)

 LOCAL_CFLAGS := \
-	-msse4.1
+	-msse4.1 -mstackrealign

 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -44,7 +44,7 @@ AM_CFLAGS = \
 	$(WNO_OVERRIDE_INIT) \
 	$(LIBDRM_CFLAGS) \
 	$(VALGRIND_CFLAGS) \
-	-msse2
+	-msse2 -mstackrealign

 AM_CXXFLAGS = $(AM_CFLAGS)

--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -194,6 +194,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
   assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
          (surf->aux_addr.buffer == NULL));

+   if (!is_render_target && brw->screen->devinfo.gen == 9)
+      gen9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage);
+
   /* ISL wants real levels, not offset ones. */
   *level -= mt->first_level;
 }
@@ -305,7 +308,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   enum isl_format src_isl_format =
      brw_blorp_to_isl_format(brw, src_format, false);
   enum isl_aux_usage src_aux_usage =
-      intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format);
+      intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
+                                      0 /* The astc5x5 WA isn't needed */);
   /* We do format workarounds for some depth formats so we can't reliably
    * sample with HiZ.  One of these days, we should fix that.
    */
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -168,6 +168,11 @@ enum brw_cache_id {
   BRW_MAX_CACHE
 };

+enum gen9_astc5x5_wa_tex_type {
+   GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
+   GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
+};
+
 enum brw_state_id {
   /* brw_cache_ids must come first - see brw_program_cache.c */
   BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
@@ -1312,6 +1317,8 @@ struct brw_context
    */
   enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS];

+   enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask;
+
   __DRIcontext *driContext;
   struct intel_screen *screen;
 };
@@ -1336,6 +1343,10 @@ void intel_update_renderbuffers(__DRIcontext *context,
                                __DRIdrawable *drawable);
 void intel_prepare_render(struct brw_context *brw);

+void gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
+                                      mesa_format format,
+                                      enum isl_aux_usage aux_usage);
+
 void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
                                bool *draw_aux_buffer_disabled);

--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -376,6 +376,68 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
   return found;
 }

+/** Implement the ASTC 5x5 sampler workaround
+ *
+ * Gen9 sampling hardware has a bug where an ASTC 5x5 compressed surface
+ * cannot live in the sampler cache at the same time as an aux compressed
+ * surface.  In order to work around the bug we have to stall rendering with a
+ * CS and pixel scoreboard stall (implicit in the CS stall) and invalidate the
+ * texture cache whenever one of ASTC 5x5 or aux compressed may be in the
+ * sampler cache and we're about to render with something which samples from
+ * the other.
+ *
+ * In the case of a single shader which textures from both ASTC 5x5 and
+ * a texture which is CCS or HiZ compressed, we have to resolve the aux
+ * compressed texture prior to rendering.  This second part is handled in
+ * brw_predraw_resolve_inputs() below.
+ *
+ * We have observed this issue to affect CCS and HiZ sampling but whether or
+ * not it also affects MCS is unknown.  Because MCS has no concept of a
+ * resolve (and doing one would be stupid expensive), we choose to simply
+ * ignore the possibility and hope for the best.
+ */
+static void
+gen9_apply_astc5x5_wa_flush(struct brw_context *brw,
+                            enum gen9_astc5x5_wa_tex_type curr_mask)
+{
+   assert(brw->screen->devinfo.gen == 9);
+
+   if (((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+        (curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX)) ||
+       ((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX) &&
+        (curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5))) {
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
+   }
+
+   brw->gen9_astc5x5_wa_tex_mask = curr_mask;
+}
+
+static enum gen9_astc5x5_wa_tex_type
+gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage)
+{
+   if (aux_usage != ISL_AUX_USAGE_NONE &&
+       aux_usage != ISL_AUX_USAGE_MCS)
+      return GEN9_ASTC5X5_WA_TEX_TYPE_AUX;
+
+   if (format == MESA_FORMAT_RGBA_ASTC_5x5 ||
+       format == MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5)
+      return GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5;
+
+   return 0;
+}
+
+/* Helper for the gen9 ASTC 5x5 workaround.  This version exists for BLORP's
+ * use-cases where only a single texture is bound.
+ */
+void
+gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
+                                 mesa_format format,
+                                 enum isl_aux_usage aux_usage)
+{
+   gen9_apply_astc5x5_wa_flush(brw, gen9_astc5x5_wa_bits(format, aux_usage));
+}
+
 static void
 mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
                           const struct gl_program *prog)
@@ -415,8 +477,30 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
      mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
   }

-   /* Resolve depth buffer and render cache of each enabled texture. */
   int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
+
+   enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits = 0;
+   if (brw->screen->devinfo.gen == 9) {
+      /* In order to properly implement the ASTC 5x5 workaround for an
+       * arbitrary draw or dispatch call, we have to walk the entire list of
+       * textures looking for ASTC 5x5.  If there is any ASTC 5x5 in this draw
+       * call, all aux compressed textures must be resolved and have aux
+       * compression disabled while sampling.
+       */
+      for (int i = 0; i <= maxEnabledUnit; i++) {
+         if (!ctx->Texture.Unit[i]._Current)
+            continue;
+         tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
+         if (!tex_obj || !tex_obj->mt)
+            continue;
+
+         astc5x5_wa_bits |= gen9_astc5x5_wa_bits(tex_obj->_Format,
+                                                 tex_obj->mt->aux_usage);
+      }
+      gen9_apply_astc5x5_wa_flush(brw, astc5x5_wa_bits);
+   }
+
+   /* Resolve depth buffer and render cache of each enabled texture. */
   for (int i = 0; i <= maxEnabledUnit; i++) {
      if (!ctx->Texture.Unit[i]._Current)
 	 continue;
@@ -450,7 +534,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,

      intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
                                    min_level, num_levels,
-                                    min_layer, num_layers);
+                                    min_layer, num_layers,
+                                    astc5x5_wa_bits);

      /* If any programs are using it with texelFetch, we may need to also do
       * a prepare with an sRGB format to ensure texelFetch works "properly".
@@ -461,7 +546,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
         if (txf_format != view_format) {
            intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
                                          min_level, num_levels,
-                                          min_layer, num_layers);
+                                          min_layer, num_layers,
+                                          astc5x5_wa_bits);
         }
      }

@@ -533,7 +619,8 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
         if (irb) {
            intel_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
                                          irb->mt_level, 1,
-                                          irb->mt_layer, irb->layer_count);
+                                          irb->mt_layer, irb->layer_count,
+                                          brw->gen9_astc5x5_wa_tex_mask);
         }
      }
   }
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -601,7 +601,8 @@ static void brw_update_texture_surface(struct gl_context *ctx,
         view.usage |= ISL_SURF_USAGE_CUBE_BIT;

      enum isl_aux_usage aux_usage =
-         intel_miptree_texture_aux_usage(brw, mt, format);
+         intel_miptree_texture_aux_usage(brw, mt, format,
+                                         brw->gen9_astc5x5_wa_tex_mask);

      brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
                             surf_offset, surf_index,
@@ -1105,7 +1106,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
            };

            enum isl_aux_usage aux_usage =
-               intel_miptree_texture_aux_usage(brw, irb->mt, format);
+               intel_miptree_texture_aux_usage(brw, irb->mt, format,
+                                               brw->gen9_astc5x5_wa_tex_mask);
            if (brw->draw_aux_usage[i] == ISL_AUX_USAGE_NONE)
               aux_usage = ISL_AUX_USAGE_NONE;

--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -118,6 +118,33 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
   const struct gen_device_info *devinfo = &brw->screen->devinfo;
   unsigned offset = 0;

+   /* From the SKL PRM, Workarounds section (#878):
+    *
+    *    Push constant buffer corruption possible. WA: Insert 2 zero-length
+    *    PushConst_PS before every intended PushConst_PS update, issue a
+    *    NULLPRIM after each of the zero len PC update to make sure CS commits
+    *    them.
+    *
+    * This workaround is attempting to solve a pixel shader push constant
+    * synchronization issue.
+    *
+    * There's an unpublished WA that involves re-emitting
+    * 3DSTATE_PUSH_CONSTANT_ALLOC_PS for every 500-ish 3DSTATE_CONSTANT_PS
+    * packets. Since our counting methods may not be reliable due to
+    * context-switching and pre-emption, we instead choose to approximate this
+    * behavior by re-emitting the packet at the top of the batch.
+    */
+   if (brw->ctx.NewDriverState == BRW_NEW_BATCH) {
+       /* SKL GT2 and GLK 2x6 have reliably demonstrated this issue thus far.
+        * We've also seen some intermittent failures from SKL GT4 and BXT in
+        * the past.
+        */
+      if (!devinfo->is_skylake &&
+          !devinfo->is_broxton &&
+          !devinfo->is_geminilake)
+         return;
+   }
+
   BEGIN_BATCH(10);
   OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
   OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
@@ -154,6 +181,7 @@ const struct brw_tracked_state gen7_push_constant_space = {
   .dirty = {
      .mesa = 0,
      .brw = BRW_NEW_CONTEXT |
+             BRW_NEW_BATCH | /* Push constant workaround */
             BRW_NEW_GEOMETRY_PROGRAM |
             BRW_NEW_TESS_PROGRAMS,
   },
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2696,7 +2696,7 @@ genX(upload_gs_state)(struct brw_context *brw)
 #if GEN_GEN < 7
         gs.SOStatisticsEnable = true;
         if (gs_prog->info.has_transform_feedback_varyings)
-            gs.SVBIPayloadEnable = true;
+            gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx);

         /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
          * was previously done for gen6.
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -121,15 +121,6 @@ set_blitter_tiling(struct brw_context *brw,
         SET_BLITTER_TILING(brw, false, false);                         \
      ADVANCE_BATCH()

-static int
-blt_pitch(struct intel_mipmap_tree *mt)
-{
-   int pitch = mt->surf.row_pitch;
-   if (mt->surf.tiling != ISL_TILING_LINEAR)
-      pitch /= 4;
-   return pitch;
-}
-
 bool
 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 {
@@ -403,7 +394,8 @@ emit_miptree_blit(struct brw_context *brw,
    * for linear surfaces and DWords for tiled surfaces.  So the maximum
    * pitch is 32k linear and 128k tiled.
    */
-   if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
+   if (intel_miptree_blt_pitch(src_mt) >= 32768 ||
+       intel_miptree_blt_pitch(dst_mt) >= 32768) {
      perf_debug("Falling back due to >= 32k/128k pitch\n");
      return false;
   }
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -509,7 +509,7 @@ free_aux_state_map(enum isl_aux_state **state)
 }

 static bool
-need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
+need_to_retile_as_linear(struct brw_context *brw, unsigned blt_pitch,
                         enum isl_tiling tiling, unsigned samples)
 {
   if (samples > 1)
@@ -518,13 +518,9 @@ need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
   if (tiling == ISL_TILING_LINEAR)
      return false;

-    /* If the width is much smaller than a tile, don't bother tiling. */
-   if (row_pitch < 64)
-      return true;
-
-   if (ALIGN(row_pitch, 512) >= 32768) {
-      perf_debug("row pitch %u too large to blit, falling back to untiled",
-                 row_pitch);
+   if (blt_pitch >= 32768) {
+      perf_debug("blt pitch %u too large to blit, falling back to untiled",
+                 blt_pitch);
      return true;
   }

@@ -604,7 +600,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
   bool is_depth_stencil =
      mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
   if (!is_depth_stencil) {
-      if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
+      if (need_to_retile_as_linear(brw, intel_miptree_blt_pitch(mt),
                                   mt->surf.tiling, mt->surf.samples)) {
         init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
         if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
@@ -2623,8 +2619,19 @@ can_texture_with_ccs(struct brw_context *brw,
 enum isl_aux_usage
 intel_miptree_texture_aux_usage(struct brw_context *brw,
                                struct intel_mipmap_tree *mt,
-                                enum isl_format view_format)
+                                enum isl_format view_format,
+                                enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
 {
+   assert(brw->screen->devinfo.gen == 9 || astc5x5_wa_bits == 0);
+
+   /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
+    * CCS or HiZ compressed textures.  See gen9_apply_astc5x5_wa_flush() for
+    * details.
+    */
+   if ((astc5x5_wa_bits & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+       mt->aux_usage != ISL_AUX_USAGE_MCS)
+      return ISL_AUX_USAGE_NONE;
+
   switch (mt->aux_usage) {
   case ISL_AUX_USAGE_HIZ:
      if (intel_miptree_sample_with_hiz(brw, mt))
@@ -2682,10 +2689,12 @@ intel_miptree_prepare_texture(struct brw_context *brw,
                              struct intel_mipmap_tree *mt,
                              enum isl_format view_format,
                              uint32_t start_level, uint32_t num_levels,
-                              uint32_t start_layer, uint32_t num_layers)
+                              uint32_t start_layer, uint32_t num_layers,
+                              enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
 {
   enum isl_aux_usage aux_usage =
-      intel_miptree_texture_aux_usage(brw, mt, view_format);
+      intel_miptree_texture_aux_usage(brw, mt, view_format, astc5x5_wa_bits);
+
   bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;

   /* Clear color is specified as ints or floats and the conversion is done by
@@ -3578,21 +3587,18 @@ intel_miptree_release_map(struct intel_mipmap_tree *mt,

 static bool
 can_blit_slice(struct intel_mipmap_tree *mt,
-               unsigned int level, unsigned int slice)
+               const struct intel_miptree_map *map)
 {
   /* See intel_miptree_blit() for details on the 32k pitch limit. */
-   if (mt->surf.row_pitch >= 32768)
-      return false;
-
-   return true;
+   const unsigned src_blt_pitch = intel_miptree_blt_pitch(mt);
+   const unsigned dst_blt_pitch = ALIGN(map->w * mt->cpp, 64);
+   return src_blt_pitch < 32768 && dst_blt_pitch < 32768;
 }

 static bool
 use_intel_mipree_map_blit(struct brw_context *brw,
                          struct intel_mipmap_tree *mt,
-                          GLbitfield mode,
-                          unsigned int level,
-                          unsigned int slice)
+                          const struct intel_miptree_map *map)
 {
   const struct gen_device_info *devinfo = &brw->screen->devinfo;

@@ -3600,19 +3606,19 @@ use_intel_mipree_map_blit(struct brw_context *brw,
      /* It's probably not worth swapping to the blit ring because of
       * all the overhead involved.
       */
-       !(mode & GL_MAP_WRITE_BIT) &&
+       !(map->mode & GL_MAP_WRITE_BIT) &&
       !mt->compressed &&
       (mt->surf.tiling == ISL_TILING_X ||
        /* Prior to Sandybridge, the blitter can't handle Y tiling */
        (devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) ||
        /* Fast copy blit on skl+ supports all tiling formats. */
        devinfo->gen >= 9) &&
-       can_blit_slice(mt, level, slice))
+       can_blit_slice(mt, map))
      return true;

   if (mt->surf.tiling != ISL_TILING_LINEAR &&
       mt->bo->size >= brw->max_gtt_map_object_size) {
-      assert(can_blit_slice(mt, level, slice));
+      assert(can_blit_slice(mt, map));
      return true;
   }

@@ -3664,7 +3670,7 @@ intel_miptree_map(struct brw_context *brw,
      intel_miptree_map_etc(brw, mt, map, level, slice);
   } else if (mt->stencil_mt && !(mode & BRW_MAP_DIRECT_BIT)) {
      intel_miptree_map_depthstencil(brw, mt, map, level, slice);
-   } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
+   } else if (use_intel_mipree_map_blit(brw, mt, map)) {
      intel_miptree_map_blit(brw, mt, map, level, slice);
 #if defined(USE_SSE41)
   } else if (!(mode & GL_MAP_WRITE_BIT) &&
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -652,13 +652,15 @@ intel_miptree_access_raw(struct brw_context *brw,
 enum isl_aux_usage
 intel_miptree_texture_aux_usage(struct brw_context *brw,
                                struct intel_mipmap_tree *mt,
-                                enum isl_format view_format);
+                                enum isl_format view_format,
+                                enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
                              struct intel_mipmap_tree *mt,
                              enum isl_format view_format,
                              uint32_t start_level, uint32_t num_levels,
-                              uint32_t start_layer, uint32_t num_layers);
+                              uint32_t start_layer, uint32_t num_layers,
+                              enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 void
 intel_miptree_prepare_image(struct brw_context *brw,
                            struct intel_mipmap_tree *mt);
@@ -741,6 +743,16 @@ intel_miptree_set_depth_clear_value(struct brw_context *brw,
                                    struct intel_mipmap_tree *mt,
                                    float clear_value);

+
+static inline int
+intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
+{
+   int pitch = mt->surf.row_pitch;
+   if (mt->surf.tiling != ISL_TILING_LINEAR)
+      pitch /= 4;
+   return pitch;
+}
+
 #ifdef __cplusplus
 }
 #endif
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -142,7 +142,7 @@ foreach v : ['40', '45', '50', '60', '70', '75', '80', '90', '100', '110']
    ['genX_blorp_exec.c', 'genX_state_upload.c', gen_xml_pack],
    include_directories : [inc_common, inc_intel, inc_dri_common],
    c_args : [
-      c_vis_args, no_override_init_args, '-msse2',
+      c_vis_args, no_override_init_args, c_sse2_args,
      '-DGEN_VERSIONx10=@0@'.format(v),
    ],
    dependencies : [dep_libdrm, idep_nir_headers],
@@ -183,8 +183,8 @@ libi965 = static_library(
  include_directories : [
    inc_common, inc_intel, inc_dri_common, inc_util, inc_drm_uapi,
  ],
-  c_args : [c_vis_args, no_override_init_args, '-msse2'],
-  cpp_args : [cpp_vis_args, '-msse2'],
+  c_args : [c_vis_args, no_override_init_args, c_sse2_args],
+  cpp_args : [cpp_vis_args, c_sse2_args],
  link_with : [
    i965_gen_libs, libintel_common, libintel_dev, libisl, libintel_compiler,
    libblorp,
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -688,10 +688,10 @@ static void r200ColorMask( struct gl_context *ctx,
   if (!rrb)
     return;
   mask = radeonPackColor( rrb->cpp,
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3) );
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3)*0xFF );


   if (!(r && g && b && a))
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -503,10 +503,10 @@ static void radeonColorMask( struct gl_context *ctx,
     return;

   mask = radeonPackColor( rrb->cpp,
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3) );
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3)*0xFF );

   if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
      RADEON_STATECHANGE( rmesa, msk );
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -163,6 +163,9 @@ st_convert_sampler(const struct st_context *st,
      const GLboolean is_integer = texobj->_IsIntegerFormat;
      GLenum texBaseFormat = _mesa_base_tex_image(texobj)->_BaseFormat;

+      if (texobj->StencilSampling)
+         texBaseFormat = GL_STENCIL_INDEX;
+
      if (st->apply_texture_swizzle_to_border_color) {
         const struct st_texture_object *stobj = st_texture_object_const(texobj);
         /* XXX: clean that up to not use the sampler view at all */
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -566,7 +566,11 @@ make_texture(struct st_context *st,
      dest = pipe_transfer_map(pipe, pt, 0, 0,
                               PIPE_TRANSFER_WRITE, 0, 0,
                               width, height, &transfer);
-
+      if (!dest) {
+         pipe_resource_reference(&pt, NULL);
+         _mesa_unmap_pbo_source(ctx, unpack);
+         return NULL;
+      }

      /* Put image into texture transfer.
       * Note that the image is actually going to be upside down in
@@ -1173,6 +1177,13 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
      return;
   }

+   /* Put glDrawPixels image into a texture */
+   pt = make_texture(st, width, height, format, type, unpack, pixels);
+   if (!pt) {
+      _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDrawPixels");
+      return;
+   }
+
   /*
    * Get vertex/fragment shaders
    */
@@ -1199,13 +1210,6 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
      st_upload_constants(st, &st->fp->Base);
   }

-   /* Put glDrawPixels image into a texture */
-   pt = make_texture(st, width, height, format, type, unpack, pixels);
-   if (!pt) {
-      _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDrawPixels");
-      return;
-   }
-
   /* create sampler view for the image */
   sv[0] = st_create_texture_sampler_view(st->pipe, pt);
   if (!sv[0]) {
--- a/src/mesa/tnl/t_split_copy.c
+++ b/src/mesa/tnl/t_split_copy.c
@@ -519,7 +519,7 @@ replay_init(struct copy_context *copy)
   for (offset = 0, i = 0; i < copy->nr_varying; i++) {
      const struct gl_vertex_array *src = copy->varying[i].array;
      const struct gl_array_attributes *srcattr = src->VertexAttrib;
-      struct gl_vertex_array *dst = &copy->dstarray[i];
+      struct gl_vertex_array *dst = &copy->dstarray[copy->varying[i].attr];
      struct gl_vertex_buffer_binding *dstbind = &copy->varying[i].dstbinding;
      struct gl_array_attributes *dstattr = &copy->varying[i].dstattribs;

--- a/src/util/u_string.h
+++ b/src/util/u_string.h
@@ -81,6 +81,7 @@ util_vsnprintf(char *str, size_t size, const char *format, va_list ap)
   if (ret < 0) {
      ret = _vscprintf(format, ap_copy);
   }
+   va_end(ap_copy);
   return ret;
 }

@@ -119,14 +120,14 @@ util_vasprintf(char **ret, const char *format, va_list ap)

   /* Compute length of output string first */
   va_copy(ap_copy, ap);
-   int r = util_vsnprintf(NULL, 0, format, ap);
+   int r = util_vsnprintf(NULL, 0, format, ap_copy);
   va_end(ap_copy);

   if (r < 0)
      return -1;

   *ret = (char *) malloc(r + 1);
-   if (!ret)
+   if (!*ret)
      return -1;

   /* Print to buffer */
--- a/src/util/xmlpool/meson.build
+++ b/src/util/xmlpool/meson.build
@@ -22,7 +22,10 @@ xmlpool_options_h = custom_target(
  'xmlpool_options.h',
  input : ['gen_xmlpool.py', 't_options.h'],
  output : 'options.h',
-  command : [prog_python2, '@INPUT@', meson.current_source_dir()],
+  command : [
+    prog_python2, '@INPUT@', meson.current_source_dir(),
+    'ca', 'es', 'de', 'nl', 'sv', 'fr',
+  ],
  capture : true,
  depend_files : files('ca.po', 'es.po', 'de.po', 'nl.po', 'sv.po', 'fr.po'),
 )
@@ -1 +1 @@
 .1.7
 .1.9