docs: Add release notes for 19.0.2

VERSION: bump version for 19.0.2
st/va: reverse qt matrix back to its original order
2019-04-10 20:34:09 -07:00 · 2019-04-10 20:30:30 -07:00 · 2019-04-09 08:36:40 -07:00 · 2019-04-09 08:35:49 -07:00 · 2019-04-08 09:30:03 -07:00 · 2019-04-05 09:08:03 -07:00
63 changed files with 881 additions and 87 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-19.0.0
+19.0.2
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -11,4 +11,7 @@ b031c643491a92a5574c7a4bd659df33f2d89bb6

 # These were manually rebased by Jason, thanks!
 8ab95b849e66f3221d80a67eef2ec6e3730901a8
-5c30fffeec1732c21d600c036f95f8cdb1bb5487
+5c30fffeec1732c21d600c036f95f8cdb1bb5487
+
+# This doesn't actually appliy to 19.0
+29179f58c6ba8099859ea25900214dbbd3814a92
--- a/bin/install_megadrivers.py
+++ b/bin/install_megadrivers.py
@@ -35,7 +35,11 @@ def main():
    args = parser.parse_args()

    if os.path.isabs(args.libdir):
-        to = os.path.join(os.environ.get('DESTDIR', '/'), args.libdir[1:])
+        destdir = os.environ.get('DESTDIR')
+        if destdir:
+            to = os.path.join(destdir, args.libdir[1:])
+        else:
+            to = args.libdir
    else:
        to = os.path.join(os.environ['MESON_INSTALL_DESTDIR_PREFIX'], args.libdir)

@@ -45,7 +49,6 @@ def main():
        if os.path.lexists(to):
            os.unlink(to)
        os.makedirs(to)
-    shutil.copy(args.megadriver, master)

    for driver in args.drivers:
        abs_driver = os.path.join(to, driver)
--- a/docs/relnotes/19.0.0.html
+++ b/docs/relnotes/19.0.0.html
@@ -32,7 +32,8 @@ Compatibility contexts may report a lower version depending on each driver.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD.
+  4c5b9c5227d37c1f6bdc786a6fa7ee7fbce40b2e8a87340c7d3234534ece3304  mesa-19.0.0.tar.gz
+  5a549dfb40ec31e5c36c47aadac04554cb2e2a8d144a046a378fc16da57e38f8  mesa-19.0.0.tar.xz
 </pre>


--- a/docs/relnotes/19.0.1.html
+++ b/docs/relnotes/19.0.1.html
@@ -0,0 +1,159 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.1 Release Notes / March 27, 2019</h1>
+
+<p>
+Mesa 19.0.1 is a bug fix release which fixes bugs found since the 19.0.0 release.
+</p>
+<p>
+Mesa 19.0.1 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd  mesa-19.0.1.tar.gz
+6884163c0ea9e4c98378ab8fecd72fe7b5f437713a14471beda378df247999d4  mesa-19.0.1.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100316">Bug 100316</a> - Linking GLSL 1.30 shaders with invariant and deprecated variables triggers an 'mismatching invariant qualifiers' error</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107563">Bug 107563</a> - [RADV] Broken rendering in Unity demos</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109698">Bug 109698</a> - dri.pc contents invalid when built with meson</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109980">Bug 109980</a> - [i915 CI][HSW] spec&#64;arb_fragment_shader_interlock&#64;arb_fragment_shader_interlock-image-load-store - fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110211">Bug 110211</a> - If DESTDIR is set to an empty string, the dri drivers are not installed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110221">Bug 110221</a> - build error with meson</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Andres Gomez (4):</p>
+<ul>
+  <li>glsl: correctly validate component layout qualifier for dvec{3,4}</li>
+  <li>glsl/linker: don't fail non static used inputs without matching outputs</li>
+  <li>glsl/linker: simplify xfb_offset vs xfb_stride overflow check</li>
+  <li>Revert "glsl: relax input-&gt;output validation for SSO programs"</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (2):</p>
+<ul>
+  <li>radv: Use correct image view comparison for fast clears.</li>
+  <li>ac/nir: Return frag_coord as integer.</li>
+</ul>
+
+<p>Danylo Piliaiev (2):</p>
+<ul>
+  <li>anv: Treat zero size XFB buffer as disabled</li>
+  <li>glsl: Cross validate variable's invariance by explicit invariance only</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>softpipe: fix texture view crashes</li>
+</ul>
+
+<p>Dylan Baker (5):</p>
+<ul>
+  <li>docs: Add SHA256 sums for 19.0.0</li>
+  <li>cherry-ignore: Add commit that doesn't apply</li>
+  <li>bin/install_megadrivers.py: Correctly handle DESTDIR=''</li>
+  <li>bin/install_megadrivers.py: Fix regression for set DESTDIR</li>
+  <li>bump version for 19.0.1</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>v3d: Fix leak of the renderonly struct on screen destruction.</li>
+</ul>
+
+<p>Jason Ekstrand (6):</p>
+<ul>
+  <li>glsl/lower_vector_derefs: Don't use a temporary for TCS outputs</li>
+  <li>glsl/list: Add a list variant of insert_after</li>
+  <li>anv/pass: Flag the need for a RT flush for resolve attachments</li>
+  <li>nir/builder: Add a vector extract helper</li>
+  <li>nir: Add a new pass to lower array dereferences on vectors</li>
+  <li>intel/nir: Lower array-deref-of-vector UBO and SSBO loads</li>
+</ul>
+
+<p>Józef Kucia (2):</p>
+<ul>
+  <li>radv: Fix driverUUID</li>
+  <li>mesa: Fix GL_NUM_DEVICE_UUIDS_EXT</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>intel/fs: Fix opt_peephole_csel to not throw away saturates.</li>
+</ul>
+
+<p>Kevin Strasser (1):</p>
+<ul>
+  <li>egl/dri: Avoid out of bounds array access</li>
+</ul>
+
+<p>Mark Janes (1):</p>
+<ul>
+  <li>mesa: properly report the length of truncated log messages</li>
+</ul>
+
+<p>Plamena Manolova (1):</p>
+<ul>
+  <li>i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9</li>
+</ul>
+
+<p>Samuel Pitoiset (3):</p>
+<ul>
+  <li>radv: set the maximum number of IBs per submit to 192</li>
+  <li>radv: always initialize HTILE when the src layout is UNDEFINED</li>
+  <li>radv: fix binding transform feedback buffers</li>
+</ul>
+
+<p>Sergii Romantsov (1):</p>
+<ul>
+  <li>d3d: meson: do not prefix user provided d3d-drivers-path</li>
+</ul>
+
+<p>Tapani Pälli (2):</p>
+<ul>
+  <li>isl: fix automake build when sse41 is not supported</li>
+  <li>anv/radv: release memory allocated by glsl types during spirv_to_nir</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.0.2.html
+++ b/docs/relnotes/19.0.2.html
@@ -0,0 +1,121 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.2 Release Notes / April 10, 2019</h1>
+
+<p>
+Mesa 19.0.2 is a bug fix release which fixes bugs found since the 19.0.1 release.
+</p>
+<p>
+Mesa 19.0.2 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+
+
+<h2>Bug fixes</h2>
+
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108766">Bug 108766</a> - Mesa built with meson has RPATH entries</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109648">Bug 109648</a> - AMD Raven hang during va-api decoding</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110257">Bug 110257</a> - Major artifacts in mpeg2 vaapi hw decoding</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110259">Bug 110259</a> - radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero (regression, bisected)</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+
+<p>Boyuan Zhang (1):</p>
+<ul>
+  <li>st/va: reverse qt matrix back to its original order</li>
+</ul>
+
+<p>Caio Marcelo de Oliveira Filho (1):</p>
+<ul>
+  <li>nir: Take if_uses into account when repairing SSA</li>
+</ul>
+
+<p>Dylan Baker (2):</p>
+<ul>
+  <li>docs: Add SHA256 sums for mesa 19.0.1</li>
+  <li>VERSION: bump version for 19.0.2</li>
+</ul>
+
+<p>Eric Anholt (3):</p>
+<ul>
+  <li>dri3: Return the current swap interval from glXGetSwapIntervalMESA().</li>
+  <li>v3d: Bump the maximum texture size to 4k for V3D 4.x.</li>
+  <li>v3d: Don't try to use the TFU blit path if a scissor is enabled.</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+  <li>meson: strip rpath from megadrivers</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"</li>
+</ul>
+
+<p>Karol Herbst (1):</p>
+<ul>
+  <li>nir/print: fix printing the image_array intrinsic index</li>
+</ul>
+
+<p>Leo Liu (2):</p>
+<ul>
+  <li>radeon/vcn: add H.264 constrained baseline support</li>
+  <li>radeon/vcn/vp9: search the render target from the whole list</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>intel: add dependency on genxml generated files</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>radeonsi: fix assertion failure by using the correct type</li>
+</ul>
+
+<p>Samuel Pitoiset (2):</p>
+<ul>
+  <li>radv: skip updating depth/color metadata for conditional rendering</li>
+  <li>radv: do not always initialize HTILE in compressed state</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/meson.build
+++ b/meson.build
@@ -608,7 +608,7 @@ with_gallium_xa = _xa != 'false'

 d3d_drivers_path = get_option('d3d-drivers-path')
 if d3d_drivers_path == ''
-  d3d_drivers_path = join_paths(get_option('libdir'), 'd3d')
+  d3d_drivers_path = join_paths(get_option('prefix'), get_option('libdir'), 'd3d')
 endif

 with_gallium_st_nine =  get_option('gallium-nine')
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3093,7 +3093,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 			ctx->abi->frag_pos[2],
 			ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
 		};
-		result = ac_build_gather_values(&ctx->ac, values, 4);
+		result = ac_to_integer(&ctx->ac,
+		                       ac_build_gather_values(&ctx->ac, values, 4));
 		break;
 	}
 	case nir_intrinsic_load_front_face:
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1258,7 +1258,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 	if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 		++reg_count;

-	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
+	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
 	radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
 			S_370_WR_CONFIRM(1) |
 			S_370_ENGINE_SEL(V_370_PFP));
@@ -1282,7 +1282,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
 	uint64_t va = radv_buffer_get_va(image->bo);
 	va += image->offset + image->tc_compat_zrange_offset;

-	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
+	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
 	radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
 			S_370_WR_CONFIRM(1) |
 			S_370_ENGINE_SEL(V_370_PFP));
@@ -1476,7 +1476,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,

 	assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));

-	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
+	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
 	radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
 			S_370_WR_CONFIRM(1) |
 			S_370_ENGINE_SEL(V_370_PFP));
@@ -4406,10 +4406,15 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
 	if (!radv_image_has_htile(image))
 		return;

-	if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
-	           radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
-		/* TODO: merge with the clear if applicable */
-		radv_initialize_htile(cmd_buffer, image, range, 0);
+	if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+		uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
+
+		if (radv_layout_is_htile_compressed(image, dst_layout,
+						    dst_queue_mask)) {
+			clear_value = 0;
+		}
+
+		radv_initialize_htile(cmd_buffer, image, range, clear_value);
 	} else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
 	           radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
 		uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
@@ -4906,7 +4911,7 @@ void radv_CmdBindTransformFeedbackBuffersEXT(
 		enabled_mask |= 1 << idx;
 	}

-	cmd_buffer->state.streamout.enabled_mask = enabled_mask;
+	cmd_buffer->state.streamout.enabled_mask |= enabled_mask;

 	cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
 }
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -337,7 +337,7 @@ radv_physical_device_init(struct radv_physical_device *device,
 	    device->rad_info.chip_class > GFX9)
 		fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");

-	radv_get_driver_uuid(&device->device_uuid);
+	radv_get_driver_uuid(&device->driver_uuid);
 	radv_get_device_uuid(&device->rad_info, &device->device_uuid);

 	if (device->rad_info.family == CHIP_STONEY ||
@@ -2794,7 +2794,7 @@ VkResult radv_QueueSubmit(
 	struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
 	struct radeon_winsys_ctx *ctx = queue->hw_ctx;
 	int ret;
-	uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
+	uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
 	uint32_t scratch_size = 0;
 	uint32_t compute_scratch_size = 0;
 	uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -651,7 +651,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 	    iview->base_mip == 0 &&
 	    iview->base_layer == 0 &&
 	    radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
-	    !radv_image_extent_compare(iview->image, &iview->extent))
+	    radv_image_extent_compare(iview->image, &iview->extent))
 		return true;
 	return false;
 }
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
@@ -29,6 +29,13 @@
 #ifndef RADV_AMDGPU_WINSYS_PUBLIC_H
 #define RADV_AMDGPU_WINSYS_PUBLIC_H

+/* The number of IBs per submit isn't infinite, it depends on the ring type
+ * (ie. some initial setup needed for a submit) and the number of IBs (4 DW).
+ * This limit is arbitrary but should be safe for now.  Ideally, we should get
+ * this limit from the KMD.
+*/
+#define RADV_MAX_IBS_PER_SUBMIT 192
+
 struct radeon_winsys *radv_amdgpu_winsys_create(int fd, uint64_t debug_flags,
 						uint64_t perftest_flags);

--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -820,8 +820,8 @@

  <packet code="120" name="Tile Binning Mode Cfg" min_ver="41">

-    <field name="Height (in pixels)" size="12" start="48" type="uint" minus_one="true"/>
-    <field name="Width (in pixels)" size="12" start="32" type="uint" minus_one="true"/>
+    <field name="Height (in pixels)" size="16" start="48" type="uint" minus_one="true"/>
+    <field name="Width (in pixels)" size="16" start="32" type="uint" minus_one="true"/>

    <field name="Double-buffer in non-ms mode" size="1" start="15" type="bool"/>
    <field name="Multisample Mode (4x)" size="1" start="14" type="bool"/>
--- a/src/broadcom/common/v3d_limits.h
+++ b/src/broadcom/common/v3d_limits.h
@@ -32,7 +32,8 @@
 */
 #define V3D_MAX_TEXTURE_SAMPLERS 16

-#define V3D_MAX_MIP_LEVELS 12
+/* The HW can do 16384 (15), but we run into hangs when we expose that. */
+#define V3D_MAX_MIP_LEVELS 13

 #define V3D_MAX_SAMPLES 4

--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -229,6 +229,7 @@ NIR_FILES = \
 	nir/nir_lower_alpha_test.c \
 	nir/nir_lower_alu.c \
 	nir/nir_lower_alu_to_scalar.c \
+	nir/nir_lower_array_deref_of_vec.c \
 	nir/nir_lower_atomics_to_ssbo.c \
 	nir/nir_lower_bitmap.c \
 	nir/nir_lower_bit_size.c \
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -3698,6 +3698,10 @@ apply_layout_qualifier_to_variable(const struct ast_type_qualifier *qual,
                                "cannot be applied to a matrix, a structure, "
                                "a block, or an array containing any of "
                                "these.");
+            } else if (components > 4 && type->is_64bit()) {
+               _mesa_glsl_error(loc, state, "component layout qualifier "
+                                "cannot be applied to dvec%u.",
+                                components / 2);
            } else if (qual_component != 0 &&
                (qual_component + components - 1) > 3) {
               _mesa_glsl_error(loc, state, "component overflow (%u > 3)",
@@ -3940,7 +3944,8 @@ apply_type_qualifier_to_variable(const struct ast_type_qualifier *qual,
                          "`invariant' after being used",
                          var->name);
      } else {
-         var->data.invariant = 1;
+         var->data.explicit_invariant = true;
+         var->data.invariant = true;
      }
   }

@@ -4148,8 +4153,10 @@ apply_type_qualifier_to_variable(const struct ast_type_qualifier *qual,
      }
   }

-   if (state->all_invariant && var->data.mode == ir_var_shader_out)
+   if (state->all_invariant && var->data.mode == ir_var_shader_out) {
+      var->data.explicit_invariant = true;
      var->data.invariant = true;
+   }

   var->data.interpolation =
      interpret_interpolation_qualifier(qual, var->type,
@@ -4857,6 +4864,7 @@ ast_declarator_list::hir(exec_list *instructions,
                            "`invariant' after being used",
                            earlier->name);
         } else {
+            earlier->data.explicit_invariant = true;
            earlier->data.invariant = true;
         }
      }
--- a/src/compiler/glsl/ir.cpp
+++ b/src/compiler/glsl/ir.cpp
@@ -1734,6 +1734,7 @@ ir_variable::ir_variable(const struct glsl_type *type, const char *name,
   this->data.centroid = false;
   this->data.sample = false;
   this->data.patch = false;
+   this->data.explicit_invariant = false;
   this->data.invariant = false;
   this->data.how_declared = ir_var_declared_normally;
   this->data.mode = mode;
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -657,6 +657,19 @@ public:
      unsigned centroid:1;
      unsigned sample:1;
      unsigned patch:1;
+      /**
+       * Was an 'invariant' qualifier explicitly set in the shader?
+       *
+       * This is used to cross validate qualifiers.
+       */
+      unsigned explicit_invariant:1;
+      /**
+       * Is the variable invariant?
+       *
+       * It can happen either by having the 'invariant' qualifier
+       * explicitly set in the shader or by being used in calculations
+       * of other invariant variables.
+       */
      unsigned invariant:1;
      unsigned precise:1;

--- a/src/compiler/glsl/ir_print_visitor.cpp
+++ b/src/compiler/glsl/ir_print_visitor.cpp
@@ -199,6 +199,7 @@ void ir_print_visitor::visit(ir_variable *ir)
   const char *const samp = (ir->data.sample) ? "sample " : "";
   const char *const patc = (ir->data.patch) ? "patch " : "";
   const char *const inv = (ir->data.invariant) ? "invariant " : "";
+   const char *const explicit_inv = (ir->data.explicit_invariant) ? "explicit_invariant " : "";
   const char *const prec = (ir->data.precise) ? "precise " : "";
   const char *const bindless = (ir->data.bindless) ? "bindless " : "";
   const char *const bound = (ir->data.bound) ? "bound " : "";
@@ -215,11 +216,11 @@ void ir_print_visitor::visit(ir_variable *ir)
   const char *const interp[] = { "", "smooth", "flat", "noperspective" };
   STATIC_ASSERT(ARRAY_SIZE(interp) == INTERP_MODE_COUNT);

-   fprintf(f, "(%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s) ",
+   fprintf(f, "(%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s) ",
           binding, loc, component, cent, bindless, bound,
           image_format, memory_read_only, memory_write_only,
           memory_coherent, memory_volatile, memory_restrict,
-           samp, patc, inv, prec, mode[ir->data.mode],
+           samp, patc, inv, explicit_inv, prec, mode[ir->data.mode],
           stream,
           interp[ir->data.interpolation]);

--- a/src/compiler/glsl/ir_reader.cpp
+++ b/src/compiler/glsl/ir_reader.cpp
@@ -419,8 +419,10 @@ ir_reader::read_declaration(s_expression *expr)
         var->data.sample = 1;
      } else if (strcmp(qualifier->value(), "patch") == 0) {
         var->data.patch = 1;
+      } else if (strcmp(qualifier->value(), "explicit_invariant") == 0) {
+         var->data.explicit_invariant = true;
      } else if (strcmp(qualifier->value(), "invariant") == 0) {
-	 var->data.invariant = 1;
+         var->data.invariant = true;
      } else if (strcmp(qualifier->value(), "uniform") == 0) {
 	 var->data.mode = ir_var_uniform;
      } else if (strcmp(qualifier->value(), "shader_storage") == 0) {
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -309,16 +309,16 @@ cross_validate_types_and_qualifiers(struct gl_context *ctx,
    *    "The invariance of varyings that are declared in both the vertex
    *     and fragment shaders must match."
    */
-   if (input->data.invariant != output->data.invariant &&
+   if (input->data.explicit_invariant != output->data.explicit_invariant &&
       prog->data->Version < (prog->IsES ? 300 : 430)) {
      linker_error(prog,
                   "%s shader output `%s' %s invariant qualifier, "
                   "but %s shader input %s invariant qualifier\n",
                   _mesa_shader_stage_to_string(producer_stage),
                   output->name,
-                   (output->data.invariant) ? "has" : "lacks",
+                   (output->data.explicit_invariant) ? "has" : "lacks",
                   _mesa_shader_stage_to_string(consumer_stage),
-                   (input->data.invariant) ? "has" : "lacks");
+                   (input->data.explicit_invariant) ? "has" : "lacks");
      return;
   }

@@ -773,8 +773,20 @@ cross_validate_outputs_to_inputs(struct gl_context *ctx,

               output = explicit_locations[idx][input->data.location_frac].var;

-               if (output == NULL ||
-                   input->data.location != output->data.location) {
+               if (output == NULL) {
+                  /* A linker failure should only happen when there is no
+                   * output declaration and there is Static Use of the
+                   * declared input.
+                   */
+                  if (input->data.used) {
+                     linker_error(prog,
+                                  "%s shader input `%s' with explicit location "
+                                  "has no matching output\n",
+                                  _mesa_shader_stage_to_string(consumer->Stage),
+                                  input->name);
+                     break;
+                  }
+               } else if (input->data.location != output->data.location) {
                  linker_error(prog,
                               "%s shader input `%s' with explicit location "
                               "has no matching output\n",
@@ -804,7 +816,7 @@ cross_validate_outputs_to_inputs(struct gl_context *ctx,
             */
            assert(!input->data.assigned);
            if (input->data.used && !input->get_interface_type() &&
-                !input->data.explicit_location && !prog->SeparateShader)
+                !input->data.explicit_location)
               linker_error(prog,
                            "%s shader input `%s' "
                            "has no matching output in the previous stage\n",
@@ -1166,8 +1178,7 @@ tfeedback_decl::store(struct gl_context *ctx, struct gl_shader_program *prog,
         return false;
      }

-      if ((this->offset / 4) / info->Buffers[buffer].Stride !=
-          (xfb_offset - 1) / info->Buffers[buffer].Stride) {
+      if (xfb_offset > info->Buffers[buffer].Stride) {
         linker_error(prog, "xfb_offset (%d) overflows xfb_stride (%d) for "
                      "buffer (%d)", xfb_offset * 4,
                      info->Buffers[buffer].Stride * 4, buffer);
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1090,7 +1090,7 @@ cross_validate_globals(struct gl_context *ctx, struct gl_shader_program *prog,
            }
         }

-         if (existing->data.invariant != var->data.invariant) {
+         if (existing->data.explicit_invariant != var->data.explicit_invariant) {
            linker_error(prog, "declarations for %s `%s' have "
                         "mismatching invariant qualifiers\n",
                         mode_string(var), var->name);
--- a/src/compiler/glsl/list.h
+++ b/src/compiler/glsl/list.h
@@ -81,6 +81,12 @@ struct exec_node {
    * Insert a node in the list after the current node
    */
   void insert_after(exec_node *after);
+
+   /**
+    * Insert another list in the list after the current node
+    */
+   void insert_after(struct exec_list *after);
+
   /**
    * Insert a node in the list before the current node
    */
@@ -507,6 +513,21 @@ exec_list_append(struct exec_list *list, struct exec_list *source)
   exec_list_make_empty(source);
 }

+static inline void
+exec_node_insert_list_after(struct exec_node *n, struct exec_list *after)
+{
+   if (exec_list_is_empty(after))
+      return;
+
+   after->tail_sentinel.prev->next = n->next;
+   after->head_sentinel.next->prev = n;
+
+   n->next->prev = after->tail_sentinel.prev;
+   n->next = after->head_sentinel.next;
+
+   exec_list_make_empty(after);
+}
+
 static inline void
 exec_list_prepend(struct exec_list *list, struct exec_list *source)
 {
@@ -635,6 +656,11 @@ inline void exec_list::append_list(exec_list *source)
   exec_list_append(this, source);
 }

+inline void exec_node::insert_after(exec_list *after)
+{
+   exec_node_insert_list_after(this, after);
+}
+
 inline void exec_list::prepend_list(exec_list *source)
 {
   exec_list_prepend(this, source);
--- a/src/compiler/glsl/lower_vector_derefs.cpp
+++ b/src/compiler/glsl/lower_vector_derefs.cpp
@@ -32,8 +32,9 @@ namespace {

 class vector_deref_visitor : public ir_rvalue_enter_visitor {
 public:
-   vector_deref_visitor()
-      : progress(false)
+   vector_deref_visitor(void *mem_ctx, gl_shader_stage shader_stage)
+      : progress(false), shader_stage(shader_stage),
+        factory(&factory_instructions, mem_ctx)
   {
   }

@@ -45,6 +46,9 @@ public:
   virtual ir_visitor_status visit_enter(ir_assignment *ir);

   bool progress;
+   gl_shader_stage shader_stage;
+   exec_list factory_instructions;
+   ir_factory factory;
 };

 } /* anonymous namespace */
@@ -65,13 +69,63 @@ vector_deref_visitor::visit_enter(ir_assignment *ir)
   ir_constant *old_index_constant =
      deref->array_index->constant_expression_value(mem_ctx);
   if (!old_index_constant) {
-      ir->rhs = new(mem_ctx) ir_expression(ir_triop_vector_insert,
-                                           new_lhs->type,
-                                           new_lhs->clone(mem_ctx, NULL),
-                                           ir->rhs,
-                                           deref->array_index);
-      ir->write_mask = (1 << new_lhs->type->vector_elements) - 1;
-      ir->set_lhs(new_lhs);
+      if (shader_stage == MESA_SHADER_TESS_CTRL &&
+          deref->variable_referenced()->data.mode == ir_var_shader_out) {
+         /* Tessellation control shader outputs act as if they have memory
+          * backing them and if we have writes from multiple threads
+          * targeting the same vec4 (this can happen for patch outputs), the
+          * load-vec-store pattern of ir_triop_vector_insert doesn't work.
+          * Instead, we have to lower to a series of conditional write-masked
+          * assignments.
+          */
+         ir_variable *const src_temp =
+            factory.make_temp(ir->rhs->type, "scalar_tmp");
+
+         /* The newly created variable declaration goes before the assignment
+          * because we're going to set it as the new LHS.
+          */
+         ir->insert_before(factory.instructions);
+         ir->set_lhs(new(mem_ctx) ir_dereference_variable(src_temp));
+
+         ir_variable *const arr_index =
+            factory.make_temp(deref->array_index->type, "index_tmp");
+         factory.emit(assign(arr_index, deref->array_index));
+
+         for (unsigned i = 0; i < new_lhs->type->vector_elements; i++) {
+            ir_constant *const cmp_index =
+               ir_constant::zero(factory.mem_ctx, deref->array_index->type);
+            cmp_index->value.u[0] = i;
+
+            ir_rvalue *const lhs_clone = new_lhs->clone(factory.mem_ctx, NULL);
+            ir_dereference_variable *const src_temp_deref =
+               new(mem_ctx) ir_dereference_variable(src_temp);
+
+            if (new_lhs->ir_type != ir_type_swizzle) {
+               assert(lhs_clone->as_dereference());
+               ir_assignment *cond_assign =
+                  new(mem_ctx) ir_assignment(lhs_clone->as_dereference(),
+                                             src_temp_deref,
+                                             equal(arr_index, cmp_index),
+                                             WRITEMASK_X << i);
+               factory.emit(cond_assign);
+            } else {
+               ir_assignment *cond_assign =
+                  new(mem_ctx) ir_assignment(swizzle(lhs_clone, i, 1),
+                                             src_temp_deref,
+                                             equal(arr_index, cmp_index));
+               factory.emit(cond_assign);
+            }
+         }
+         ir->insert_after(factory.instructions);
+      } else {
+         ir->rhs = new(mem_ctx) ir_expression(ir_triop_vector_insert,
+                                              new_lhs->type,
+                                              new_lhs->clone(mem_ctx, NULL),
+                                              ir->rhs,
+                                              deref->array_index);
+         ir->write_mask = (1 << new_lhs->type->vector_elements) - 1;
+         ir->set_lhs(new_lhs);
+      }
   } else if (new_lhs->ir_type != ir_type_swizzle) {
      ir->set_lhs(new_lhs);
      ir->write_mask = 1 << old_index_constant->get_uint_component(0);
@@ -105,7 +159,7 @@ vector_deref_visitor::handle_rvalue(ir_rvalue **rv)
 bool
 lower_vector_derefs(gl_linked_shader *shader)
 {
-   vector_deref_visitor v;
+   vector_deref_visitor v(shader->ir, shader->Stage);

   visit_list_elements(&v, shader->ir);

--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -112,6 +112,7 @@ files_libnir = files(
  'nir_lower_alu.c',
  'nir_lower_alu_to_scalar.c',
  'nir_lower_alpha_test.c',
+  'nir_lower_array_deref_of_vec.c',
  'nir_lower_atomics_to_ssbo.c',
  'nir_lower_bitmap.c',
  'nir_lower_bool_to_float.c',
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2910,6 +2910,16 @@ void nir_fixup_deref_modes(nir_shader *shader);

 bool nir_lower_global_vars_to_local(nir_shader *shader);

+typedef enum {
+   nir_lower_direct_array_deref_of_vec_load     = (1 << 0),
+   nir_lower_indirect_array_deref_of_vec_load   = (1 << 1),
+   nir_lower_direct_array_deref_of_vec_store    = (1 << 2),
+   nir_lower_indirect_array_deref_of_vec_store  = (1 << 3),
+} nir_lower_array_deref_of_vec_options;
+
+bool nir_lower_array_deref_of_vec(nir_shader *shader, nir_variable_mode modes,
+                                  nir_lower_array_deref_of_vec_options options);
+
 bool nir_lower_indirect_derefs(nir_shader *shader, nir_variable_mode modes);

 bool nir_lower_locals_to_regs(nir_shader *shader);
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -560,6 +560,35 @@ nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask)
   return nir_swizzle(b, def, swizzle, num_channels, false);
 }

+static inline nir_ssa_def *
+_nir_vector_extract_helper(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c,
+                           unsigned start, unsigned end)
+{
+   if (start == end - 1) {
+      return nir_channel(b, vec, start);
+   } else {
+      unsigned mid = start + (end - start) / 2;
+      return nir_bcsel(b, nir_ilt(b, c, nir_imm_int(b, mid)),
+                       _nir_vector_extract_helper(b, vec, c, start, mid),
+                       _nir_vector_extract_helper(b, vec, c, mid, end));
+   }
+}
+
+static inline nir_ssa_def *
+nir_vector_extract(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c)
+{
+   nir_src c_src = nir_src_for_ssa(c);
+   if (nir_src_is_const(c_src)) {
+      unsigned c_const = nir_src_as_uint(c_src);
+      if (c_const < vec->num_components)
+         return nir_channel(b, vec, c_const);
+      else
+         return nir_ssa_undef(b, 1, vec->bit_size);
+   } else {
+      return _nir_vector_extract_helper(b, vec, c, 0, vec->num_components);
+   }
+}
+
 static inline nir_ssa_def *
 nir_i2i(nir_builder *build, nir_ssa_def *x, unsigned dest_bit_size)
 {
--- a/src/compiler/nir/nir_lower_array_deref_of_vec.c
+++ b/src/compiler/nir/nir_lower_array_deref_of_vec.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+
+static void
+build_write_masked_store(nir_builder *b, nir_deref_instr *vec_deref,
+                         nir_ssa_def *value, unsigned component)
+{
+   assert(value->num_components == 1);
+   unsigned num_components = glsl_get_components(vec_deref->type);
+   assert(num_components > 1 && num_components <= NIR_MAX_VEC_COMPONENTS);
+
+   nir_ssa_def *u = nir_ssa_undef(b, 1, value->bit_size);
+   nir_ssa_def *comps[NIR_MAX_VEC_COMPONENTS];
+   for (unsigned i = 0; i < num_components; i++)
+      comps[i] = (i == component) ? value : u;
+
+   nir_ssa_def *vec = nir_vec(b, comps, num_components);
+   nir_store_deref(b, vec_deref, vec, (1u << component));
+}
+
+static void
+build_write_masked_stores(nir_builder *b, nir_deref_instr *vec_deref,
+                          nir_ssa_def *value, nir_ssa_def *index,
+                          unsigned start, unsigned end)
+{
+   if (start == end - 1) {
+      build_write_masked_store(b, vec_deref, value, start);
+   } else {
+      unsigned mid = start + (end - start) / 2;
+      nir_push_if(b, nir_ilt(b, index, nir_imm_int(b, mid)));
+      build_write_masked_stores(b, vec_deref, value, index, start, mid);
+      nir_push_else(b, NULL);
+      build_write_masked_stores(b, vec_deref, value, index, mid, end);
+      nir_pop_if(b, NULL);
+   }
+}
+
+static bool
+nir_lower_array_deref_of_vec_impl(nir_function_impl *impl,
+                                  nir_variable_mode modes,
+                                  nir_lower_array_deref_of_vec_options options)
+{
+   bool progress = false;
+
+   nir_builder b;
+   nir_builder_init(&b, impl);
+
+   nir_foreach_block(block, impl) {
+      nir_foreach_instr_safe(instr, block) {
+         if (instr->type != nir_instr_type_intrinsic)
+            continue;
+
+         nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+         assert(intrin->intrinsic != nir_intrinsic_copy_deref);
+
+         if (intrin->intrinsic != nir_intrinsic_load_deref &&
+             intrin->intrinsic != nir_intrinsic_interp_deref_at_centroid &&
+             intrin->intrinsic != nir_intrinsic_interp_deref_at_sample &&
+             intrin->intrinsic != nir_intrinsic_interp_deref_at_offset &&
+             intrin->intrinsic != nir_intrinsic_store_deref)
+            continue;
+
+         nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
+         if (!(deref->mode & modes))
+            continue;
+
+         /* We only care about array derefs that act on vectors */
+         if (deref->deref_type != nir_deref_type_array)
+            continue;
+
+         nir_deref_instr *vec_deref = nir_deref_instr_parent(deref);
+         if (!glsl_type_is_vector(vec_deref->type))
+            continue;
+
+         assert(intrin->num_components == 1);
+         unsigned num_components = glsl_get_components(vec_deref->type);
+         assert(num_components > 1 && num_components <= NIR_MAX_VEC_COMPONENTS);
+
+         b.cursor = nir_after_instr(&intrin->instr);
+
+         if (intrin->intrinsic == nir_intrinsic_store_deref) {
+            assert(intrin->src[1].is_ssa);
+            nir_ssa_def *value = intrin->src[1].ssa;
+
+            if (nir_src_is_const(deref->arr.index)) {
+               if (!(options & nir_lower_direct_array_deref_of_vec_store))
+                  continue;
+
+               unsigned index = nir_src_as_uint(deref->arr.index);
+               /* If index is OOB, we throw the old store away and don't
+                * replace it with anything.
+                */
+               if (index < num_components)
+                  build_write_masked_store(&b, vec_deref, value, index);
+            } else {
+               if (!(options & nir_lower_indirect_array_deref_of_vec_store))
+                  continue;
+
+               nir_ssa_def *index = nir_ssa_for_src(&b, deref->arr.index, 1);
+               build_write_masked_stores(&b, vec_deref, value, index,
+                                         0, num_components);
+            }
+            nir_instr_remove(&intrin->instr);
+
+            progress = true;
+         } else {
+            if (nir_src_is_const(deref->arr.index)) {
+               if (!(options & nir_lower_direct_array_deref_of_vec_load))
+                  continue;
+            } else {
+               if (!(options & nir_lower_indirect_array_deref_of_vec_load))
+                  continue;
+            }
+
+            /* Turn the load into a vector load */
+            nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
+                                  nir_src_for_ssa(&vec_deref->dest.ssa));
+            intrin->dest.ssa.num_components = num_components;
+            intrin->num_components = num_components;
+
+            nir_ssa_def *index = nir_ssa_for_src(&b, deref->arr.index, 1);
+            nir_ssa_def *scalar =
+               nir_vector_extract(&b, &intrin->dest.ssa, index);
+            if (scalar->parent_instr->type == nir_instr_type_ssa_undef) {
+               nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
+                                        nir_src_for_ssa(scalar));
+               nir_instr_remove(&intrin->instr);
+            } else {
+               nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa,
+                                              nir_src_for_ssa(scalar),
+                                              scalar->parent_instr);
+            }
+            progress = true;
+         }
+      }
+   }
+
+   if (progress) {
+      nir_metadata_preserve(impl, nir_metadata_block_index |
+                                  nir_metadata_dominance);
+   }
+
+   return progress;
+}
+
+/* Lowers away array dereferences on vectors
+ *
+ * These are allowed on certain variable types such as SSBOs and TCS outputs.
+ * However, not everyone can actually handle them everywhere.  There are also
+ * cases where we want to lower them for performance reasons.
+ *
+ * This patch assumes that copy_deref instructions have already been lowered.
+ */
+bool
+nir_lower_array_deref_of_vec(nir_shader *shader, nir_variable_mode modes,
+                             nir_lower_array_deref_of_vec_options options)
+{
+   bool progress = false;
+
+   nir_foreach_function(function, shader) {
+      if (function->impl &&
+          nir_lower_array_deref_of_vec_impl(function->impl, modes, options))
+         progress = true;
+   }
+
+   return progress;
+}
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -812,8 +812,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state)
         assert(dim < ARRAY_SIZE(dim_name) && dim_name[dim]);
         fprintf(fp, " image_dim=%s", dim_name[dim]);
      } else if (idx == NIR_INTRINSIC_IMAGE_ARRAY) {
-         bool array = nir_intrinsic_image_dim(instr);
-         fprintf(fp, " image_dim=%s", array ? "true" : "false");
+         bool array = nir_intrinsic_image_array(instr);
+         fprintf(fp, " image_array=%s", array ? "true" : "false");
      } else if (idx == NIR_INTRINSIC_DESC_TYPE) {
         VkDescriptorType desc_type = nir_intrinsic_desc_type(instr);
         fprintf(fp, " desc_type=%s", vulkan_descriptor_type_name(desc_type));
--- a/src/compiler/nir/nir_repair_ssa.c
+++ b/src/compiler/nir/nir_repair_ssa.c
@@ -77,6 +77,15 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
      }
   }

+   nir_foreach_if_use(src, def) {
+      nir_block *block_before_if =
+         nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
+      if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
+         is_valid = false;
+         break;
+      }
+   }
+
   if (is_valid)
      return true;

@@ -98,6 +107,15 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
      }
   }

+   nir_foreach_if_use_safe(src, def) {
+      nir_block *block_before_if =
+         nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
+      if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
+         nir_if_rewrite_condition(src->parent_if, nir_src_for_ssa(
+            nir_phi_builder_value_get_block_def(val, block_before_if)));
+      }
+   }
+
   return true;
 }

--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3045,12 +3045,7 @@ nir_ssa_def *
 vtn_vector_extract_dynamic(struct vtn_builder *b, nir_ssa_def *src,
                           nir_ssa_def *index)
 {
-   nir_ssa_def *dest = vtn_vector_extract(b, src, 0);
-   for (unsigned i = 1; i < src->num_components; i++)
-      dest = nir_bcsel(&b->nb, nir_ieq_imm(&b->nb, index, i),
-                       vtn_vector_extract(b, src, i), dest);
-
-   return dest;
+   return nir_vector_extract(&b->nb, src, nir_i2i(&b->nb, index, 32));
 }

 nir_ssa_def *
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -199,8 +199,10 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
   bind_to_texture_rgb = 0;
   bind_to_texture_rgba = 0;

-   for (int i = 0; dri2_dpy->core->indexConfigAttrib(dri_config, i, &attrib,
-                                                     &value); ++i) {
+   for (int i = 0; i < __DRI_ATTRIB_MAX; ++i) {
+      if (!dri2_dpy->core->indexConfigAttrib(dri_config, i, &attrib, &value))
+         break;
+
      switch (attrib) {
      case __DRI_ATTRIB_RENDER_TYPE:
         if (value & __DRI_ATTRIB_RGBA_BIT)
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -64,6 +64,7 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
 	memset(&result, 0, sizeof(result));
 	switch (pic->base.profile) {
 	case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
+	case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
 		result.profile = RDECODE_H264_PROFILE_BASELINE;
 		break;

@@ -490,7 +491,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,

 	assert(dec->base.max_references + 1 <= 16);

-	for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
+	for (i = 0 ; i < 16 ; ++i) {
 		if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
 			result.curr_pic_idx =
 				(uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -186,7 +186,7 @@ static void si_emit_guardband(struct si_context *ctx)
 		ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);

 	/* Indexed by quantization modes */
-	static unsigned max_viewport_size[] = {65535, 16383, 4095};
+	static int max_viewport_size[] = {65535, 16383, 4095};

 	/* Ensure that the whole viewport stays representable in
 	 * absolute coordinates.
--- a/src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tile_cache.c
@@ -373,17 +373,18 @@ sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc, int layer)
               if (util_format_is_pure_uint(tc->surface->format)) {
                  pipe_put_tile_ui_format(pt, tc->transfer_map[layer],
                                          x, y, TILE_SIZE, TILE_SIZE,
-                                          pt->resource->format,
+                                          tc->surface->format,
                                          (unsigned *) tc->tile->data.colorui128);
               } else if (util_format_is_pure_sint(tc->surface->format)) {
                  pipe_put_tile_i_format(pt, tc->transfer_map[layer],
                                         x, y, TILE_SIZE, TILE_SIZE,
-                                         pt->resource->format,
+                                         tc->surface->format,
                                         (int *) tc->tile->data.colori128);
               } else {
-                  pipe_put_tile_rgba(pt, tc->transfer_map[layer],
-                                     x, y, TILE_SIZE, TILE_SIZE,
-                                     (float *) tc->tile->data.color);
+                  pipe_put_tile_rgba_format(pt, tc->transfer_map[layer],
+                                            x, y, TILE_SIZE, TILE_SIZE,
+                                            tc->surface->format,
+                                            (float *) tc->tile->data.color);
               }
            }
            numCleared++;
--- a/src/gallium/drivers/v3d/v3d_blit.c
+++ b/src/gallium/drivers/v3d/v3d_blit.c
@@ -491,7 +491,8 @@ v3d_tfu_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
        if ((info->mask & PIPE_MASK_RGBA) == 0)
                return false;

-        if (info->dst.box.x != 0 ||
+        if (info->scissor_enable ||
+            info->dst.box.x != 0 ||
            info->dst.box.y != 0 ||
            info->dst.box.width != dst_width ||
            info->dst.box.height != dst_height ||
--- a/src/gallium/drivers/v3d/v3d_screen.c
+++ b/src/gallium/drivers/v3d/v3d_screen.c
@@ -70,6 +70,7 @@ v3d_screen_destroy(struct pipe_screen *pscreen)
        util_hash_table_destroy(screen->bo_handles);
        v3d_bufmgr_destroy(pscreen);
        slab_destroy_parent(&screen->transfer_pool);
+        free(screen->ro);

        if (using_v3d_simulator)
                v3d_simulator_destroy(screen);
@@ -184,7 +185,10 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
-                return V3D_MAX_MIP_LEVELS;
+                if (screen->devinfo.ver < 40)
+                        return 12;
+                else
+                        return V3D_MAX_MIP_LEVELS;
        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
                return 2048;

--- a/src/gallium/drivers/v3d/v3dx_draw.c
+++ b/src/gallium/drivers/v3d/v3dx_draw.c
@@ -55,7 +55,28 @@ v3d_start_draw(struct v3d_context *v3d)
        job->submit.bcl_start = job->bcl.bo->offset;
        v3d_job_add_bo(job, job->bcl.bo);

-        job->tile_alloc = v3d_bo_alloc(v3d->screen, 1024 * 1024, "tile_alloc");
+        /* The PTB will request the tile alloc initial size per tile at start
+         * of tile binning.
+         */
+        uint32_t tile_alloc_size = (job->draw_tiles_x *
+                                    job->draw_tiles_y) * 64;
+        /* The PTB allocates in aligned 4k chunks after the initial setup. */
+        tile_alloc_size = align(tile_alloc_size, 4096);
+
+        /* Include the first two chunk allocations that the PTB does so that
+         * we definitely clear the OOM condition before triggering one (the HW
+         * won't trigger OOM during the first allocations).
+         */
+        tile_alloc_size += 8192;
+
+        /* For performance, allocate some extra initial memory after the PTB's
+         * minimal allocations, so that we hopefully don't have to block the
+         * GPU on the kernel handling an OOM signal.
+         */
+        tile_alloc_size += 512 * 1024;
+
+        job->tile_alloc = v3d_bo_alloc(v3d->screen, tile_alloc_size,
+                                       "tile_alloc");
        uint32_t tsda_per_tile_size = v3d->screen->devinfo.ver >= 40 ? 256 : 64;
        job->tile_state = v3d_bo_alloc(v3d->screen,
                                       job->draw_tiles_y *
--- a/src/gallium/drivers/v3d/v3dx_state.c
+++ b/src/gallium/drivers/v3d/v3dx_state.c
@@ -846,6 +846,9 @@ v3d_setup_texture_shader_state(struct V3DX(TEXTURE_SHADER_STATE) *tex,
            prsc->target == PIPE_TEXTURE_1D_ARRAY) {
                tex->image_height = tex->image_width >> 14;
        }
+
+        tex->image_width &= (1 << 14) - 1;
+        tex->image_height &= (1 << 14) - 1;
 #endif

        if (prsc->target == PIPE_TEXTURE_3D) {
--- a/src/gallium/state_trackers/va/picture_mpeg12.c
+++ b/src/gallium/state_trackers/va/picture_mpeg12.c
@@ -27,6 +27,19 @@

 #include "va_private.h"

+const int reverse_inverse_zscan[] =
+{
+   /* Reverse inverse z scan pattern */
+    0,  2,  3,  9, 10, 20, 21, 35,
+    1,  4,  8, 11, 19, 22, 34, 36,
+    5,  7, 12, 18, 23, 33, 37, 48,
+    6, 13, 17, 24, 32, 38, 47, 49,
+   14, 16, 25, 31, 39, 46, 50, 57,
+   15, 26, 30, 40, 45, 51, 56, 58,
+   27, 29, 41, 44, 52, 55, 59, 62,
+   28, 42, 43, 53, 54, 60, 61, 63,
+};
+
 void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *buf)
 {
   VAPictureParameterBufferMPEG2 *mpeg2 = buf->data;
@@ -66,16 +79,29 @@ void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *contex
 void vlVaHandleIQMatrixBufferMPEG12(vlVaContext *context, vlVaBuffer *buf)
 {
   VAIQMatrixBufferMPEG2 *mpeg2 = buf->data;
+   static uint8_t temp_intra_matrix[64];
+   static uint8_t temp_nonintra_matrix[64];

   assert(buf->size >= sizeof(VAIQMatrixBufferMPEG2) && buf->num_elements == 1);
-   if (mpeg2->load_intra_quantiser_matrix)
-      context->desc.mpeg12.intra_matrix = mpeg2->intra_quantiser_matrix;
-   else
+   if (mpeg2->load_intra_quantiser_matrix) {
+      /* The quantiser matrix that VAAPI provides has been applied
+         with inverse z-scan. However, what we expect in MPEG2
+         picture description is the original order. Therefore,
+         we need to reverse it back to its original order.
+      */
+      for (int i = 0; i < 64; i++)
+         temp_intra_matrix[i] =
+            mpeg2->intra_quantiser_matrix[reverse_inverse_zscan[i]];
+      context->desc.mpeg12.intra_matrix = temp_intra_matrix;
+   } else
      context->desc.mpeg12.intra_matrix = NULL;

-   if (mpeg2->load_non_intra_quantiser_matrix)
-      context->desc.mpeg12.non_intra_matrix = mpeg2->non_intra_quantiser_matrix;
-   else
+   if (mpeg2->load_non_intra_quantiser_matrix) {
+      for (int i = 0; i < 64; i++)
+         temp_nonintra_matrix[i] =
+            mpeg2->non_intra_quantiser_matrix[reverse_inverse_zscan[i]];
+      context->desc.mpeg12.non_intra_matrix = temp_nonintra_matrix;
+   } else
      context->desc.mpeg12.non_intra_matrix = NULL;
 }

--- a/src/gallium/targets/d3dadapter9/meson.build
+++ b/src/gallium/targets/d3dadapter9/meson.build
@@ -68,5 +68,5 @@ pkg.generate(
  description : 'Native D3D driver modules',
  version : '.'.join(nine_version),
  requires_private : 'libdrm >= ' + dep_libdrm.version(),
-  variables : ['moduledir=${prefix}/@0@'.format(d3d_drivers_path)],
+  variables : ['moduledir=@0@'.format(d3d_drivers_path)],
 )
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -60,6 +60,9 @@ libgallium_dri = shared_library(
    driver_tegra, driver_i915, driver_svga, driver_virgl,
    driver_swr,
  ],
+  # Will be deleted during installation, see install_megadrivers.py
+  install : true,
+  install_dir : dri_drivers_path,
 )

 foreach d : [[with_gallium_kmsro, 'pl111_dri.so'],
--- a/src/gallium/targets/va/meson.build
+++ b/src/gallium/targets/va/meson.build
@@ -49,6 +49,7 @@ libva_gallium = shared_library(
    dep_libdrm, dep_thread, driver_r600, driver_radeonsi, driver_nouveau,
  ],
  link_depends : va_link_depends,
+  # Will be deleted during installation, see install_megadrivers.py
  install : true,
  install_dir : va_drivers_path,
 )
--- a/src/gallium/targets/vdpau/meson.build
+++ b/src/gallium/targets/vdpau/meson.build
@@ -55,6 +55,9 @@ libvdpau_gallium = shared_library(
  ],
  link_depends : vdpau_link_depends,
  soversion : '@0@.@1@.0'.format(VDPAU_MAJOR, VDPAU_MINOR),
+  # Will be deleted during installation, see install_megadrivers.py
+  install : true,
+  install_dir : vdpau_drivers_path,
 )
 foreach d : [[with_gallium_r300, 'r300'],
             [with_gallium_r600, 'r600'],
--- a/src/gallium/targets/xvmc/meson.build
+++ b/src/gallium/targets/xvmc/meson.build
@@ -47,6 +47,9 @@ libxvmc_gallium = shared_library(
  ],
  dependencies : [dep_thread, driver_r600, driver_nouveau],
  link_depends : xvmc_link_depends,
+  # Will be deleted during installation, see install_megadrivers.py
+  install : true,
+  install_dir : xvmc_drivers_path,
 )

 foreach d : [[with_gallium_r600, 'r600'], [with_gallium_nouveau, 'nouveau']]
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -642,7 +642,6 @@ dri3_set_swap_interval(__GLXDRIdrawable *pdraw, int interval)
      break;
   }

-   priv->swap_interval = interval;
   loader_dri3_set_swap_interval(&priv->loader_drawable, interval);

   return 0;
@@ -659,7 +658,7 @@ dri3_get_swap_interval(__GLXDRIdrawable *pdraw)

   struct dri3_drawable *priv =  (struct dri3_drawable *) pdraw;

-  return priv->swap_interval;
+  return priv->loader_drawable.swap_interval;
 }

 static void
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -117,7 +117,6 @@ struct dri3_context
 struct dri3_drawable {
   __GLXDRIdrawable base;
   struct loader_dri3_drawable loader_drawable;
-   int swap_interval;

   /* LIBGL_SHOW_FPS support */
   uint64_t previous_ust;
--- a/src/intel/Makefile.isl.am
+++ b/src/intel/Makefile.isl.am
@@ -33,12 +33,15 @@ ISL_GEN_LIBS =                                           \

 noinst_LTLIBRARIES += $(ISL_GEN_LIBS) \
                      isl/libisl.la \
-                      libisl_tiled_memcpy.la \
-                      libisl_tiled_memcpy_sse41.la
+                      libisl_tiled_memcpy.la

 isl_libisl_la_LIBADD = $(ISL_GEN_LIBS) \
-                       libisl_tiled_memcpy.la \
-                       libisl_tiled_memcpy_sse41.la
+                       libisl_tiled_memcpy.la
+
+if SSE41_SUPPORTED
+isl_libisl_la_LIBADD += libisl_tiled_memcpy_sse41.la
+noinst_LTLIBRARIES += libisl_tiled_memcpy_sse41.la
+endif

 isl_libisl_la_SOURCES = $(ISL_FILES) $(ISL_GENERATED_FILES)

--- a/src/intel/blorp/meson.build
+++ b/src/intel/blorp/meson.build
@@ -33,5 +33,5 @@ libblorp = static_library(
  files_libblorp,
  include_directories : [inc_common, inc_intel],
  c_args : [c_vis_args, no_override_init_args],
-  dependencies : idep_nir_headers,
+  dependencies : [idep_nir_headers, idep_genxml],
 )
--- a/src/intel/common/meson.build
+++ b/src/intel/common/meson.build
@@ -43,5 +43,5 @@ libintel_common = static_library(
  include_directories : [inc_common, inc_intel],
  c_args : [c_vis_args, no_override_init_args],
  link_with : [libisl],
-  dependencies : [dep_expat, dep_libdrm, dep_thread],
+  dependencies : [dep_expat, dep_libdrm, dep_thread, idep_genxml],
 )
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3117,6 +3117,7 @@ fs_visitor::opt_peephole_csel()

            if (csel_inst != NULL) {
               progress = true;
+               csel_inst->saturate = inst->saturate;
               inst->remove(block);
            }

--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2100,6 +2100,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
         break;

      case SHADER_OPCODE_INTERLOCK:
+         assert(devinfo->gen >= 9);
         /* The interlock is basically a memory fence issued via sendc */
         brw_memory_fence(p, dst, BRW_OPCODE_SENDC);
         break;
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -781,6 +781,17 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)

   OPT(brw_nir_lower_mem_access_bit_sizes);

+   /* Lower array derefs of vectors for SSBO and UBO loads.  For both UBOs and
+    * SSBOs, our back-end is capable of loading an entire vec4 at a time and
+    * we would like to take advantage of that whenever possible regardless of
+    * whether or not the app gives us full loads.  This should allow the
+    * optimizer to combine UBO and SSBO load operations and save us some send
+    * messages.
+    */
+   OPT(nir_lower_array_deref_of_vec,
+       nir_var_mem_ubo | nir_var_mem_ssbo,
+       nir_lower_direct_array_deref_of_vec_load);
+
   /* Get rid of split copies */
   nir = brw_nir_optimize(nir, compiler, is_scalar, false);

--- a/src/intel/genxml/meson.build
+++ b/src/intel/genxml/meson.build
@@ -57,3 +57,5 @@ foreach f : gen_xml_files
    capture : true,
  )
 endforeach
+
+idep_genxml = declare_dependency(sources : [gen_xml_pack, genX_bits_h, genX_xml_h])
--- a/src/intel/meson.build
+++ b/src/intel/meson.build
@@ -21,9 +21,9 @@
 c_sse2_args = ['-msse2', '-mstackrealign']
 inc_intel = include_directories('.')

+subdir('genxml')
 subdir('blorp')
 subdir('dev')
-subdir('genxml')
 subdir('isl')
 subdir('common')
 subdir('compiler')
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -178,12 +178,28 @@ anv_render_pass_compile(struct anv_render_pass *pass)
    * subpasses and checking to see if any of them don't have an external
    * dependency.  Or, we could just be lazy and add a couple extra flushes.
    * We choose to be lazy.
+    *
+    * From the documentation for vkCmdNextSubpass:
+    *
+    *    "Moving to the next subpass automatically performs any multisample
+    *    resolve operations in the subpass being ended. End-of-subpass
+    *    multisample resolves are treated as color attachment writes for the
+    *    purposes of synchronization. This applies to resolve operations for
+    *    both color and depth/stencil attachments. That is, they are
+    *    considered to execute in the
+    *    VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
+    *    their writes are synchronized with
+    *    VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT."
+    *
+    * Therefore, the above flags concerning color attachments also apply to
+    * color and depth/stencil resolve attachments.
    */
   if (all_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
      pass->subpass_flushes[0] |=
         ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
   }
-   if (all_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
+   if (all_usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
+                    VK_IMAGE_USAGE_TRANSFER_DST_BIT)) {
      pass->subpass_flushes[pass->subpass_count] |=
         ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
   }
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2653,7 +2653,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
         anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {
            sob.SOBufferIndex = idx;

-            if (cmd_buffer->state.xfb_enabled && xfb->buffer) {
+            if (cmd_buffer->state.xfb_enabled && xfb->buffer && xfb->size != 0) {
               sob.SOBufferEnable = true;
               sob.MOCS = cmd_buffer->device->default_mocs,
               sob.StreamOffsetWriteEnable = false;
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -203,7 +203,7 @@ libvulkan_intel = shared_library(
    libvulkan_util, libvulkan_wsi, libmesa_util,
  ],
  dependencies : [
-    dep_thread, dep_dl, dep_m, anv_deps, idep_nir,
+    dep_thread, dep_dl, dep_m, anv_deps, idep_nir, idep_genxml,
  ],
  c_args : anv_flags,
  link_args : ['-Wl,--build-id=sha1', ld_args_bsymbolic, ld_args_gc_sections],
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -253,7 +253,6 @@ intelInitExtensions(struct gl_context *ctx)
      ctx->Extensions.EXT_shader_samples_identical = true;
      ctx->Extensions.OES_primitive_bounding_box = true;
      ctx->Extensions.OES_texture_buffer = true;
-      ctx->Extensions.ARB_fragment_shader_interlock = true;

      if (can_do_pipelined_register_writes(brw->screen)) {
         ctx->Extensions.ARB_draw_indirect = true;
@@ -318,6 +317,30 @@ intelInitExtensions(struct gl_context *ctx)
      ctx->Extensions.KHR_blend_equation_advanced_coherent = true;
      ctx->Extensions.KHR_texture_compression_astc_ldr = true;
      ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
+
+      /*
+       * From the Skylake PRM Vol. 7 (Memory Fence Message, page 221):
+       *  "A memory fence message issued by a thread causes further messages
+       *   issued by the thread to be blocked until all previous data port
+       *   messages have completed, or the results can be globally observed from
+       *   the point of view of other threads in the system."
+       *
+       * From the Haswell PRM Vol. 7 (Memory Fence, page 256):
+       *  "A memory fence message issued by a thread causes further messages
+       *   issued by the thread to be blocked until all previous messages issued
+       *   by the thread to that data port (data cache or render cache) have
+       *   been globally observed from the point of view of other threads in the
+       *   system."
+       *
+       * Summarized: For ARB_fragment_shader_interlock to work, we need to
+       * ensure memory access ordering for all messages to the dataport from
+       * all threads. Memory fence messages prior to SKL only provide memory
+       * access ordering for messages from the same thread, so we can only
+       * support the feature from Gen9 onwards.
+       *
+       */
+
+      ctx->Extensions.ARB_fragment_shader_interlock = true;
   }

   if (gen_device_info_is_9lp(devinfo))
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -187,7 +187,7 @@ libi965 = static_library(
    i965_gen_libs, libintel_common, libintel_dev, libisl, libintel_compiler,
    libblorp
  ],
-  dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers],
+  dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers, idep_genxml],
 )

 dri_drivers += libi965
--- a/src/mesa/drivers/dri/meson.build
+++ b/src/mesa/drivers/dri/meson.build
@@ -54,6 +54,9 @@ if dri_drivers != []
      dep_selinux, dep_libdrm, dep_expat, dep_m, dep_thread, dep_dl, idep_nir,
    ],
    link_args : [ld_args_build_id, ld_args_bsymbolic, ld_args_gc_sections],
+    # Will be deleted during installation, see install_megadrivers.py
+    install : true,
+    install_dir : dri_drivers_path,
  )

  meson.add_install_script(
--- a/src/mesa/main/errors.c
+++ b/src/mesa/main/errors.c
@@ -231,6 +231,9 @@ _mesa_gl_vdebug(struct gl_context *ctx,
   _mesa_debug_get_id(id);

   len = _mesa_vsnprintf(s, MAX_DEBUG_MESSAGE_LENGTH, fmtString, args);
+   if (len >= MAX_DEBUG_MESSAGE_LENGTH)
+      /* message was truncated */
+      len = MAX_DEBUG_MESSAGE_LENGTH - 1;

   _mesa_log_msg(ctx, source, type, *id, severity, len, s);
 }
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -906,6 +906,9 @@ find_custom_value(struct gl_context *ctx, const struct value_desc *d, union valu
      break;

   /* GL_EXT_external_objects */
+   case GL_NUM_DEVICE_UUIDS_EXT:
+      v->value_int = 1;
+      break;
   case GL_DRIVER_UUID_EXT:
      _mesa_get_driver_uuid(ctx, v->value_int_4);
      break;
@@ -1 +1 @@
 .0.0
 .0.2