docs: add release notes for 18.3.5

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

.editorconfig

@@ -11,7 +11,6 @@ tab_width = 8
 [*.{c,h,cpp,hpp,cc,hh}]
 indent_style = space
 indent_size = 3
-max_line_length = 78
 
 [{Makefile*,*.mk}]
 indent_style = tab

.travis.yml

@@ -1,6 +1,7 @@
 language: c
 
-dist: xenial
+sudo: false
+dist: trusty
 
 cache:
   apt: true
@@ -15,7 +16,7 @@ env:
     - GLPROTO_VERSION=glproto-1.4.17
     - DRI2PROTO_VERSION=dri2proto-2.8
     - LIBPCIACCESS_VERSION=libpciaccess-0.13.4
-    - LIBDRM_VERSION=libdrm-2.4.97
+    - LIBDRM_VERSION=libdrm-2.4.74
     - XCBPROTO_VERSION=xcb-proto-1.13
     - RANDRPROTO_VERSION=randrproto-1.3.0
     - LIBXRANDR_VERSION=libXrandr-1.3.0
@@ -34,19 +35,20 @@ matrix:
     - env:
         - LABEL="meson Vulkan"
         - BUILD=meson
-        - UNWIND="false"
-        - DRI_LOADERS="-Dglx=disabled -Dgbm=false -Degl=false -Dplatforms=x11,wayland,drm -Dosmesa=none"
-        - GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
+        - DRI_DRIVERS=""
+        - GALLIUM_DRIVERS=""
         - VULKAN_DRIVERS="intel,amd"
-        - LLVM_VERSION=7
+        - LLVM_VERSION=6.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
       addons:
         apt:
           sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
-              key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
-            - llvm-7-dev
+            # From sources above
+            - llvm-6.0-dev
             # Common
             - xz-utils
             - libexpat1-dev
@@ -54,27 +56,23 @@ matrix:
             - libelf-dev
             - python3.5
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="meson loaders/classic DRI"
         - BUILD=meson
-        - UNWIND="false"
-        - DRI_LOADERS="-Dglx=dri -Dgbm=true -Degl=true -Dplatforms=x11,wayland,drm,surfaceless -Dosmesa=classic"
         - DRI_DRIVERS="i915,i965,r100,r200,swrast,nouveau"
-        - GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
+        - GALLIUM_DRIVERS=""
+        - VULKAN_DRIVERS=""
       addons:
         apt:
           packages:
             - xz-utils
             - x11proto-xf86vidmode-dev
-            - libxxf86vm-dev
             - libexpat1-dev
             - libx11-xcb-dev
             - libxdamage-dev
             - libxfixes-dev
             - python3.5
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make loaders/classic DRI"
         - BUILD=make
@@ -91,200 +89,11 @@ matrix:
           packages:
             - xz-utils
             - x11proto-xf86vidmode-dev
-            - libxxf86vm-dev
             - libexpat1-dev
             - libx11-xcb-dev
             - libxdamage-dev
             - libxfixes-dev
             - python3-pip
-            - python3-setuptools
-    - env:
-        # NOTE: Building SWR is 2x (yes two) times slower than all the other
-        # gallium drivers combined.
-        # Start this early so that it doesn't hunder the run time.
-        - LABEL="meson Gallium Drivers SWR"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
-        - GALLIUM_DRIVERS="swr"
-        - LLVM_VERSION=6.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          packages:
-            - llvm-6.0-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium Drivers RadeonSI"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
-        - GALLIUM_DRIVERS="radeonsi"
-        - LLVM_VERSION=7
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
-              key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
-          packages:
-            # From sources above
-            - llvm-7-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium Drivers Other"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
-        - GALLIUM_DRIVERS="i915,nouveau,kmsro,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv"
-        - LLVM_VERSION=5.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          packages:
-            # LLVM packaging is broken and misses these dependencies
-            - libedit-dev
-            - llvm-5.0-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium ST Clover LLVM-5.0"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
-        - GALLIUM_DRIVERS="r600"
-        - LLVM_VERSION=5.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          packages:
-            - libclc-dev
-            # LLVM packaging is broken and misses these dependencies
-            - libedit-dev
-            - llvm-5.0-dev
-            - clang-5.0
-            - libclang-5.0-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium ST Clover LLVM-6.0"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
-        - GALLIUM_DRIVERS="r600"
-        - LLVM_VERSION=6.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          packages:
-            - libclc-dev
-            - llvm-6.0-dev
-            - clang-6.0
-            - libclang-6.0-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium ST Clover LLVM-7"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
-        - GALLIUM_DRIVERS="r600,radeonsi"
-        - LLVM_VERSION=7
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
-              key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
-          packages:
-            - libclc-dev
-            # From sources above
-            - llvm-7-dev
-            - clang-7
-            - libclang-7-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
-    - env:
-        - LABEL="meson Gallium ST Other"
-        - BUILD=meson
-        - UNWIND="true"
-        - DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
-        - GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=true -Dgallium-xvmc=true -Dgallium-omx=bellagio -Dgallium-va=true -Dgallium-xa=true -Dgallium-nine=true -Dgallium-opencl=disabled -Dosmesa=gallium"
-        # We need swrast for osmesa and nine.
-        # Nouveau supports, or builds at least against all ST.
-        - GALLIUM_DRIVERS="nouveau,swrast"
-        - LLVM_VERSION=5.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-      addons:
-        apt:
-          packages:
-            - llvm-5.0-dev
-            # LLVM packaging is broken and misses these dependencies
-            - libedit-dev
-            # Nine requires gcc 4.6... which is the one we have right ?
-            - libxvmc-dev
-            # Build locally, for now.
-            #- libvdpau-dev
-            #- libva-dev
-            - libomxil-bellagio-dev
-            # Common
-            - xz-utils
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
-            - python3.5
-            - python3-pip
-            - python3-setuptools
     - env:
         # NOTE: Building SWR is 2x (yes two) times slower than all the other
         # gallium drivers combined.
@@ -303,7 +112,12 @@ matrix:
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
+            # From sources above
             - llvm-6.0-dev
             # Common
             - xz-utils
@@ -312,13 +126,12 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium Drivers RadeonSI"
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=7
+        - LLVM_VERSION=6.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
@@ -329,11 +142,12 @@ matrix:
       addons:
         apt:
           sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
-              key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
             # From sources above
-            - llvm-7-dev
+            - llvm-6.0-dev
             # Common
             - xz-utils
             - libexpat1-dev
@@ -341,7 +155,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium Drivers Other"
         - BUILD=make
@@ -349,17 +162,23 @@ matrix:
         - MAKE_CHECK_COMMAND="true"
         - LLVM_VERSION=3.9
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+        # New binutils linker is required for llvm-3.9
+        - OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="i915,nouveau,kmsro,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv"
+        - GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv,imx"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-3.9
           packages:
+            - binutils-2.26
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
+            # From sources above
             - llvm-3.9-dev
             # Common
             - xz-utils
@@ -368,7 +187,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium ST Clover LLVM-3.9"
         - BUILD=make
@@ -376,6 +194,10 @@ matrix:
         - MAKE_CHECK_COMMAND="true"
         - LLVM_VERSION=3.9
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+        - OVERRIDE_CC=gcc-4.7
+        - OVERRIDE_CXX=g++-4.7
+        # New binutils linker is required for llvm-3.9
+        - OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -384,10 +206,15 @@ matrix:
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-3.9
           packages:
+            - binutils-2.26
             - libclc-dev
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
+            - g++-4.7
+            # From sources above
             - llvm-3.9-dev
             - clang-3.9
             - libclang-3.9-dev
@@ -398,7 +225,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium ST Clover LLVM-4.0"
         - BUILD=make
@@ -406,6 +232,8 @@ matrix:
         - MAKE_CHECK_COMMAND="true"
         - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+        - OVERRIDE_CC=gcc-4.8
+        - OVERRIDE_CXX=g++-4.8
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -414,10 +242,14 @@ matrix:
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-4.0
           packages:
             - libclc-dev
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
+            - g++-4.8
+            # From sources above
             - llvm-4.0-dev
             - clang-4.0
             - libclang-4.0-dev
@@ -428,7 +260,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium ST Clover LLVM-5.0"
         - BUILD=make
@@ -436,6 +267,8 @@ matrix:
         - MAKE_CHECK_COMMAND="true"
         - LLVM_VERSION=5.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+        - OVERRIDE_CC=gcc-4.8
+        - OVERRIDE_CXX=g++-4.8
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -444,10 +277,14 @@ matrix:
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-5.0
           packages:
             - libclc-dev
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
+            - g++-4.8
+            # From sources above
             - llvm-5.0-dev
             - clang-5.0
             - libclang-5.0-dev
@@ -458,7 +295,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium ST Clover LLVM-6.0"
         - BUILD=make
@@ -469,13 +305,18 @@ matrix:
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="r600"
+        - GALLIUM_DRIVERS="r600,radeonsi"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
             - libclc-dev
+            # From sources above
             - llvm-6.0-dev
             - clang-6.0
             - libclang-6.0-dev
@@ -486,7 +327,6 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Gallium ST Clover LLVM-7"
         - BUILD=make
@@ -503,8 +343,10 @@ matrix:
       addons:
         apt:
           sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
+            - sourceline: 'deb http://apt.llvm.org/trusty/ llvm-toolchain-trusty-7 main'
               key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
+            # llvm-7 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
             - libclc-dev
             # From sources above
@@ -522,7 +364,7 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=3.5
+        - LLVM_VERSION=3.3
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
@@ -536,8 +378,8 @@ matrix:
       addons:
         apt:
           packages:
-            # We actually want to test against llvm-3.3, yet 3.5 is available
-            - llvm-3.5-dev
+            # We actually want to test against llvm-3.3
+            - llvm-3.3-dev
             # Nine requires gcc 4.6... which is the one we have right ?
             - libxvmc-dev
             # Build locally, for now.
@@ -553,13 +395,12 @@ matrix:
             - libelf-dev
             - libunwind8-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="make Vulkan"
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel check"
-        - LLVM_VERSION=7
+        - LLVM_VERSION=6.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl --with-platforms=x11,wayland"
         - DRI_DRIVERS=""
@@ -570,18 +411,18 @@ matrix:
       addons:
         apt:
           sources:
-            - sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
-              key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
             # From sources above
-            - llvm-7-dev
+            - llvm-6.0-dev
             # Common
             - xz-utils
             - libexpat1-dev
             - libx11-xcb-dev
             - libelf-dev
             - python3-pip
-            - python3-setuptools
     - env:
         - LABEL="scons"
         - BUILD=scons
@@ -606,15 +447,14 @@ matrix:
         - SCONS_TARGET="llvm=1"
         # Keep it symmetrical to the make build.
         - SCONS_CHECK_COMMAND="scons llvm=1 check"
-        - LLVM_VERSION=3.5
+        - LLVM_VERSION=3.3
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
       addons:
         apt:
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
-            # We actually want to test against llvm-3.3, yet 3.5 is available
-            - llvm-3.5-dev
+            - llvm-3.3-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -632,7 +472,12 @@ matrix:
         - SCONS_CHECK_COMMAND="true"
       addons:
         apt:
+          sources:
+            - llvm-toolchain-trusty-6.0
+            # llvm-6 requires libstdc++4.9 which is not in main repo
+            - ubuntu-toolchain-r-test
           packages:
+            # From sources above
             - llvm-6.0-dev
             # Common
             - xz-utils
@@ -650,9 +495,6 @@ matrix:
     - env:
         - LABEL="macOS meson"
         - BUILD=meson
-        - UNWIND="false"
-        - DRI_LOADERS="-Dglx=dri -Dgbm=false -Degl=false -Dplatforms=x11 -Dosmesa=none"
-        - GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
       os: osx
 
 before_install:
@@ -680,8 +522,10 @@ before_install:
 
 install:
   # Install a more modern meson from pip, since the version in the
-  # ubuntu repos is often quite old.
+  # ubuntu repos is often quite old. This requires python>=3.5, so
+  # let's make it default
   - if test "x$BUILD" = xmeson; then
+      sudo update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.5 10;
       pip3 install --user meson;
       pip3 install --user mako;
     fi
@@ -697,6 +541,16 @@ install:
       pip2 install --user mako;
     fi
 
+  # Since libdrm gets updated in configure.ac regularly, try to pick up the
+  # latest version from there.
+  - for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
+      old_ver=`echo $LIBDRM_VERSION | sed 's/libdrm-//'`;
+      new_ver=`echo $line | sed 's/.*REQUIRED=//'`;
+      if `echo "$old_ver,$new_ver" | tr ',' '\n' | sort -Vc 2> /dev/null`; then
+        export LIBDRM_VERSION="libdrm-$new_ver";
+      fi;
+    done
+
   # Install dependencies where we require specific versions (or where
   # disallowed by Travis CI's package whitelisting).
 
@@ -758,7 +612,7 @@ install:
       tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
       (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && make install)
 
-      # Meson requires ninja >= 1.6, but xenial has 1.3.x
+      # Meson requires ninja >= 1.6, but trusty has 1.3.x
       wget https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip
       unzip ninja-linux.zip
       mv ninja $HOME/prefix/bin/
@@ -801,13 +655,15 @@ install:
 
 script:
   - if test "x$BUILD" = xmake; then
+      test -n "$OVERRIDE_CC" && export CC="$OVERRIDE_CC";
+      test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
+      test -n "$OVERRIDE_PATH" && export PATH="$OVERRIDE_PATH:$PATH";
+
       export CFLAGS="$CFLAGS -isystem`pwd`";
 
       mkdir build &&
       cd build &&
-      ../autogen.sh
-        --enable-autotools
-        --enable-debug
+      ../autogen.sh --enable-debug
         $LIBUNWIND_FLAGS
         $DRI_LOADERS
         --with-dri-drivers=$DRI_DRIVERS
@@ -820,33 +676,41 @@ script:
     fi
 
   - if test "x$BUILD" = xscons; then
+      test -n "$OVERRIDE_CC" && export CC="$OVERRIDE_CC";
+      test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
       scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
     fi
 
   - |
     if test "x$BUILD" = xmeson; then
-      if test -n "$LLVM_CONFIG"; then
-        # We need to control the version of llvm-config we're using, so we'll
-        # generate a native file to do so. This requires meson >=0.49
-        #
-        echo -e "[binaries]\nllvm-config = '`which $LLVM_CONFIG`'" > native.file
 
-        $LLVM_CONFIG --version
-      else
-        : > native.file
+      if test "x$TRAVIS_OS_NAME" == xosx; then
+        MESON_OPTIONS="-Degl=false"
       fi
 
+      if test "x$TRAVIS_OS_NAME" == xlinux; then
+        MESON_OPTIONS="-Ddri-drivers=${DRI_DRIVERS:-[]} -Dgallium-drivers=${GALLIUM_DRIVERS:-[]} -Dvulkan-drivers=${VULKAN_DRIVERS:-[]}"
+      fi
+
+      # Travis CI has moved to LLVM 5.0, and meson is detecting
+      # automatically the available version in /usr/local/bin based on
+      # the PATH env variable order preference.
+      #
+      # As for 0.44.x, Meson cannot receive the path to the
+      # llvm-config binary as a configuration parameter. See
+      # https://github.com/mesonbuild/meson/issues/2887 and
+      # https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef
+      #
+      # We want to use the custom (APT) installed version. Therefore,
+      # let's make Meson find our wanted version sooner than the one
+      # at /usr/local/bin
+      #
+      # Once this is corrected, we would still need a patch similar
+      # to:
+      # https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html
+      test -f /usr/bin/$LLVM_CONFIG && ln -s /usr/bin/$LLVM_CONFIG $HOME/prefix/bin/llvm-config
+
       export CFLAGS="$CFLAGS -isystem`pwd`"
-      meson _build \
-                   --native-file=native.file \
-                   -Dbuild-tests=true \
-                   -Dlibunwind=${UNWIND} \
-                   ${DRI_LOADERS} \
-                   -Ddri-drivers=${DRI_DRIVERS:-[]} \
-                   ${GALLIUM_ST} \
-                   -Dgallium-drivers=${GALLIUM_DRIVERS:-[]} \
-                   -Dvulkan-drivers=${VULKAN_DRIVERS:-[]}
-      meson configure _build
+      meson _build $MESON_OPTIONS
       ninja -C _build
-      ninja -C _build test
     fi

Android.common.mk

@@ -37,6 +37,7 @@ LOCAL_CFLAGS += \
 	-Wno-missing-field-initializers \
 	-Wno-initializer-overrides \
 	-Wno-mismatched-tags \
+	-DVERSION=\"$(MESA_VERSION)\" \
 	-DPACKAGE_VERSION=\"$(MESA_VERSION)\" \
 	-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"
 

Android.mk

@@ -24,7 +24,7 @@
 # BOARD_GPU_DRIVERS should be defined.  The valid values are
 #
 #   classic drivers: i915 i965
-#   gallium drivers: swrast freedreno i915g nouveau kmsro r300g r600g radeonsi vc4 virgl vmwgfx etnaviv
+#   gallium drivers: swrast freedreno i915g nouveau pl111 r300g r600g radeonsi vc4 virgl vmwgfx etnaviv imx
 #
 # The main target is libGLES_mesa.  For each classic driver enabled, a DRI
 # module will also be built.  DRI modules will be loaded by libGLES_mesa.
@@ -52,14 +52,15 @@ gallium_drivers := \
 	freedreno.HAVE_GALLIUM_FREEDRENO \
 	i915g.HAVE_GALLIUM_I915 \
 	nouveau.HAVE_GALLIUM_NOUVEAU \
-	kmsro.HAVE_GALLIUM_KMSRO \
+	pl111.HAVE_GALLIUM_PL111 \
 	r300g.HAVE_GALLIUM_R300 \
 	r600g.HAVE_GALLIUM_R600 \
 	radeonsi.HAVE_GALLIUM_RADEONSI \
 	vmwgfx.HAVE_GALLIUM_VMWGFX \
 	vc4.HAVE_GALLIUM_VC4 \
 	virgl.HAVE_GALLIUM_VIRGL \
-	etnaviv.HAVE_GALLIUM_ETNAVIV
+	etnaviv.HAVE_GALLIUM_ETNAVIV \
+	imx.HAVE_GALLIUM_IMX
 
 ifeq ($(BOARD_GPU_DRIVERS),all)
 MESA_BUILD_CLASSIC := $(filter HAVE_%, $(subst ., , $(classic_drivers)))

Makefile.am

@@ -22,7 +22,6 @@
 SUBDIRS = src
 
 AM_DISTCHECK_CONFIGURE_FLAGS = \
-	--enable-autotools \
 	--enable-dri \
 	--enable-dri3 \
 	--enable-egl \
@@ -46,7 +45,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
 	--enable-libunwind \
 	--with-platforms=x11,wayland,drm,surfaceless \
 	--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
-	--with-gallium-drivers=i915,nouveau,r300,kmsro,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv \
+	--with-gallium-drivers=i915,nouveau,r300,pl111,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv,imx \
 	--with-vulkan-drivers=intel,radeon
 
 ACLOCAL_AMFLAGS = -I m4

REVIEWERS

@@ -72,9 +72,7 @@ F: src/loader/
 
 EGL
 R: Eric Engestrom <eric@engestrom.ch>
-R: Emil Velikov <emil.l.velikov@gmail.com>
 F: src/egl/
-F: include/EGL/
 
 HAIKU
 R: Alexander von Gluck IV <kallisti5@unixzen.com>
@@ -138,8 +136,3 @@ F:	src/gallium/drivers/freedreno/
 GLX
 R: Adam Jackson <ajax@redhat.com>
 F: src/glx/
-
-VULKAN
-R: Eric Engestrom <eric@engestrom.ch>
-F: src/vulkan/
-F: include/vulkan/

VERSION

@@ -1 +1 @@
-19.0.0
+18.3.5

bin/.cherry-ignore

@@ -1,14 +1,54 @@
-# Both of these were already merged with different shas
-da48cba61ef6fefb799bf96e6364b70dbf4ec712
-c812c740e60c14060eb89db66039111881a0f42f
+# fixes: Commit was squashed into the respective offenders
+c02390f8fcd367c7350db568feabb2f062efca14 egl/wayland: rather obvious build fix
+# fixes: The commit addresses b4476138d5ad3f8d30c14ee61f2f375edfdbab2a
+ff6f1dd0d3c6b4c15ca51b478b2884d14f6a1e06 meson: libfreedreno depends upon libdrm (for fence support)
 
-# The commit these fix was reverted from 19.0, but fixed for 19.1 due
-# to the number of fixes required to make that commit work
-8d8f80af3a17354508f2ec9d6559c915d5be351d
-0c0c69729b6d72a5297122856c8fe48510e90764
-0881e90c09965818b02e359474a6f7446b41d647
-b031c643491a92a5574c7a4bd659df33f2d89bb6
+# fixes: This commit requires commits aeaf8dbd097 and 7484bc894b9 which did not
+#        land in branch.
+f67dea5e19ef14187be0e8d0f61b1f764c7ccb4f radv: Fix multiview depth clears
 
-# These were manually rebased by Jason, thanks!
-8ab95b849e66f3221d80a67eef2ec6e3730901a8
-5c30fffeec1732c21d600c036f95f8cdb1bb5487
+# stable The commits aren't suitable in their present form.
+bfe31c5e461a1330d6f606bf5310685eff1198dd nir/builder: Add nir_i2i and nir_u2u helpers which take a bit size
+abfe674c54bee6f8fdcae411b07db89c10b9d530 spirv: Handle arbitrary bit sizes for deref array indices
+
+# warn   The commits refer stale sha, yet don't fix anything in particular.
+98984b7cdd79c15cc7331c791f8be61e873b8bbd Revert "mapi/new: sort by slot number"
+9f86f1da7c68b5b900cd6f60925610ff1225a72d egl: add glvnd entrypoints for EGL_MESA_query_driver
+
+# stable Explicit 19.0 only nomination.
+38f542783faa360020b77fdd76b97f207a9e0068 v50,nvc0: add explicit settings for recent caps
+
+# stable Explicit 19.0 only nominations.
+399215eb7a0517463e5757c598d6cff6ae2301d0 nvc0: add support for handling indirect draws with attrib conversion
+4443b6ddf2e08d06f3d0457cf20a2e04244cde37 nvc0/ir: always use CG mode for loads from atomic-only buffers
+5de5beedf21306b01730085f8e03d8f424729016 nvc0/ir: fix second tex argument after levelZero optimization
+162352e6711b3ceab114686f7a3248074339e7f7 nvc0: fix 3d images on kepler
+e00799d3dc0595dc3998dbf199ceec8b1eece966 nv50,nvc0: use condition for occlusion queries when already complete
+6adb9b38bfb1f6ee4c94596bf0744225aa8e967a nvc0: stick zero values for the compute invocation counts
+04593d9a73ea257a36cc3b9fb5cd41427beaaea5 gk110/ir: Add rcp f64 implementation
+7937408052a1896f0b08b0110bb8a1790eeee351 gk110/ir: Add rsq f64 implementation
+656ad060518d067a3b311db8c2de2a396fb41898 gk110/ir: Use the new rcp/rsq in library
+12669d29705a26478aa691cb454149628be65f17 gk104/ir: Use the new rcp/rsq in library
+815a8e59c6d462a7008653ea9e3010d40b6ba589 gm107/ir: add fp64 rcp
+cce495572136a606dd2a35e79f45080c3796e2cc gm107/ir: add fp64 rsq
+6010d7b8e8bee1bcea2b329cf6d3b44c5fc3ca66 gallium: add PIPE_CAP_MAX_VARYINGS
+cbd1ad6165f0aea7fb7c6fd1b36ad5317dd65cb7 st/mesa: require RGBA2, RGB4, and RGBA4 to be renderable
+
+# stable The commit addresses functionality not present in branch
+1b8983c25be19073c02fe9630e949be55f8280fa radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
+
+# stable Explicit 19.0 only nominations, require work which did not land in branch
+8ab95b849e66f3221d80a67eef2ec6e3730901a8 anv: Refactor descriptor pushing a bit
+5c30fffeec1732c21d600c036f95f8cdb1bb5487 anv: Take references to push descriptor set layouts
+
+# sha    Commit references invalid sha - a offender did not land in branch.
+85ee157283c667372baf7c03259cba08853f0067 gitlab-ci: autotools needs to be told which llvm version to use
+
+# revert The commit was reverted shortly after it was applied on master
+47fc359822494935852de1e70e4d840b2fe6a25c anv: release memory allocated by glsl types during spirv_to_nir
+
+# stable Explicitly 19.0 nomination, seemingly a performance patch
+5ef2b8f1f2ebcdb4ffe5c98b3f4f48e584cb4b22 nir: Add a pass for lowering IO back to vector when possible
+
+# fixes Temporary block perf. fix depending on previous opt. pass
+6d5d89d25a0a4299dbfcbfeca71b6c7e65ef3d45 intel/nir: Vectorize all IO

bin/meson-cmd-extract.py

@@ -1,88 +0,0 @@
-#!/usr/bin/env python3
-# Copyright © 2019 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-"""This script reads a meson build directory and gives back the command line it
-was configured with.
-
-This only works for meson 0.49.0 and newer.
-"""
-
-import argparse
-import ast
-import configparser
-import pathlib
-import sys
-
-
-def parse_args() -> argparse.Namespace:
-    """Parse arguments."""
-    parser = argparse.ArgumentParser()
-    parser.add_argument(
-        'build_dir',
-        help='Path the meson build directory')
-    args = parser.parse_args()
-    return args
-
-
-def load_config(path: pathlib.Path) -> configparser.ConfigParser:
-    """Load config file."""
-    conf = configparser.ConfigParser()
-    with path.open() as f:
-        conf.read_file(f)
-    return conf
-
-
-def build_cmd(conf: configparser.ConfigParser) -> str:
-    """Rebuild the command line."""
-    args = []
-    for k, v in conf['options'].items():
-        if ' ' in v:
-            args.append(f'-D{k}="{v}"')
-        else:
-            args.append(f'-D{k}={v}')
-
-    cf = conf['properties'].get('cross_file')
-    if cf:
-        args.append('--cross-file={}'.format(cf))
-    nf = conf['properties'].get('native_file')
-    if nf:
-        # this will be in the form "['str', 'str']", so use ast.literal_eval to
-        # convert it to a list of strings.
-        nf = ast.literal_eval(nf)
-        args.extend(['--native-file={}'.format(f) for f in nf])
-    return ' '.join(args)
-
-
-def main():
-    args = parse_args()
-    path = pathlib.Path(args.build_dir, 'meson-private', 'cmd_line.txt')
-    if not path.exists():
-        print('Cannot find the necessary file to rebuild command line. '
-              'Is your meson version >= 0.49.0?', file=sys.stderr)
-        sys.exit(1)
-
-    conf = load_config(path)
-    cmd = build_cmd(conf)
-    print(cmd)
-
-
-if __name__ == '__main__':
-    main()

configure.ac

@@ -52,19 +52,6 @@ mingw*)
     ;;
 esac
 
-AC_ARG_ENABLE(autotools,
-   [AS_HELP_STRING([--enable-autotools],
-                   [Enable the use of this autotools based build configuration])],
-   [enable_autotools=$enableval], [enable_autotools=no])
-
-if test "x$enable_autotools" != "xyes" ; then
-    AC_MSG_ERROR([the autotools build system has been deprecated in favour of
-    meson and will be removed eventually. For instructions on how to use meson
-    see https://www.mesa3d.org/meson.html.
-    If you still want to use the autotools build, then add --enable-autotools
-    to the configure command line.])
-fi
-
 # Support silent build rules, requires at least automake-1.11. Disable
 # by either passing --disable-silent-rules to configure or passing V=1
 # to make
@@ -87,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.97
+LIBDRM_AMDGPU_REQUIRED=2.4.95
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
@@ -120,9 +107,9 @@ dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
 LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
-LLVM_REQUIRED_RADEONSI=7.0.0
-LLVM_REQUIRED_RADV=7.0.0
-LLVM_REQUIRED_SWR=7.0.0
+LLVM_REQUIRED_RADEONSI=6.0.0
+LLVM_REQUIRED_RADV=6.0.0
+LLVM_REQUIRED_SWR=6.0.0
 
 dnl Check for progs
 AC_PROG_CPP
@@ -1408,7 +1395,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast"
 AC_ARG_WITH([gallium-drivers],
     [AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@],
         [comma delimited Gallium drivers list, e.g.
-        "i915,nouveau,r300,r600,radeonsi,freedreno,kmsro,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv"
+        "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv,imx"
         @<:@default=r300,r600,svga,swrast@:>@])],
     [with_gallium_drivers="$withval"],
     [with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"])
@@ -1922,7 +1909,7 @@ if test x"$enable_dri3" = xyes; then
     dri3_modifier_modules="xcb-dri3 >= $XCBDRI3_MODIFIERS_REQUIRED xcb-present >= $XCBPRESENT_MODIFIERS_REQUIRED"
     PKG_CHECK_MODULES([XCB_DRI3_MODIFIERS], [$dri3_modifier_modules], [have_dri3_modifiers=yes], [have_dri3_modifiers=no])
 
-    if test "x$have_dri3_modifiers" = xyes; then
+    if test "x$have_dri3_modifiers" == xyes; then
         DEFINES="$DEFINES -DHAVE_DRI3_MODIFIERS"
     fi
 fi
@@ -2741,6 +2728,9 @@ if test -n "$with_gallium_drivers"; then
             PKG_CHECK_MODULES([ETNAVIV], [libdrm >= $LIBDRM_ETNAVIV_REQUIRED libdrm_etnaviv >= $LIBDRM_ETNAVIV_REQUIRED])
             require_libdrm "etnaviv"
             ;;
+       ximx)
+            HAVE_GALLIUM_IMX=yes
+            ;;
         xtegra)
             HAVE_GALLIUM_TEGRA=yes
             require_libdrm "tegra"
@@ -2827,8 +2817,8 @@ if test -n "$with_gallium_drivers"; then
                                DEFINES="$DEFINES -DUSE_V3D_SIMULATOR"],
                               [USE_V3D_SIMULATOR=no])
             ;;
-        xkmsro)
-            HAVE_GALLIUM_KMSRO=yes
+        xpl111)
+            HAVE_GALLIUM_PL111=yes
             ;;
         xvirgl)
             HAVE_GALLIUM_VIRGL=yes
@@ -2845,8 +2835,8 @@ if test -n "$with_gallium_drivers"; then
 fi
 
 # XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x7.0.0 -a \
-                                              "x$LLVM_VERSION" != x7.0.1)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x6.0.0 -a \
+                                              "x$LLVM_VERSION" != x6.0.1)
 
 if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
     llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
@@ -2861,8 +2851,12 @@ AM_CONDITIONAL(HAVE_SWR_BUILTIN, test "x$HAVE_SWR_BUILTIN" = xyes)
 
 dnl We need to validate some needed dependencies for renderonly drivers.
 
-if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_KMSRO" = xyes  ; then
-    AC_MSG_ERROR([Building with kmsro requires vc4])
+if test "x$HAVE_GALLIUM_ETNAVIV" != xyes -a "x$HAVE_GALLIUM_IMX" = xyes  ; then
+    AC_MSG_ERROR([Building with imx requires etnaviv])
+fi
+
+if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_PL111" = xyes  ; then
+    AC_MSG_ERROR([Building with pl111 requires vc4])
 fi
 
 if test "x$HAVE_GALLIUM_NOUVEAU" != xyes -a "x$HAVE_GALLIUM_TEGRA" = xyes; then
@@ -2910,7 +2904,6 @@ if test "x$enable_llvm" = xyes; then
     LLVM_LDFLAGS=`$LLVM_CONFIG --ldflags`
     LLVM_CFLAGS=$LLVM_CPPFLAGS   # CPPFLAGS seem to be sufficient
     LLVM_CXXFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cxxflags"`
-    LLVM_CXXFLAGS="$CXX11_CXXFLAGS $LLVM_CXXFLAGS"
 
     dnl Set LLVM_LIBS - This is done after the driver configuration so
     dnl that drivers can add additional components to LLVM_COMPONENTS.
@@ -2945,11 +2938,11 @@ if test "x$enable_llvm" = xyes; then
     fi
 
     dnl The gallium-xlib GLX and gallium OSMesa targets directly embed the
-    dnl swr/llvmpipe driver into the final binary.  Adding LLVM_LIBS results in
+    dnl swr/llvmpipe driver into the final binary.  Adding LLVM_LIBS results in 
     dnl the LLVM library propagated in the Libs.private of the respective .pc
     dnl file which ensures complete dependency information when statically
     dnl linking.
-    if test "x$enable_glx" = xgallium-xlib; then
+    if test "x$enable_glx" == xgallium-xlib; then
         GL_PC_LIB_PRIV="$GL_PC_LIB_PRIV $LLVM_LIBS"
     fi
     if test "x$enable_gallium_osmesa" = xyes; then
@@ -2959,13 +2952,14 @@ fi
 
 AM_CONDITIONAL(HAVE_GALLIUM_SVGA, test "x$HAVE_GALLIUM_SVGA" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_I915, test "x$HAVE_GALLIUM_I915" = xyes)
-AM_CONDITIONAL(HAVE_GALLIUM_KMSRO, test "x$HAVE_GALLIUM_KMSRO" = xyes)
+AM_CONDITIONAL(HAVE_GALLIUM_PL111, test "x$HAVE_GALLIUM_PL111" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_R300, test "x$HAVE_GALLIUM_R300" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_R600, test "x$HAVE_GALLIUM_R600" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_RADEONSI, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_NOUVEAU, test "x$HAVE_GALLIUM_NOUVEAU" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_ETNAVIV, test "x$HAVE_GALLIUM_ETNAVIV" = xyes)
+AM_CONDITIONAL(HAVE_GALLIUM_IMX, test "x$HAVE_GALLIUM_IMX" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_TEGRA, test "x$HAVE_GALLIUM_TEGRA" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_SOFTPIPE, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_LLVMPIPE, test "x$HAVE_GALLIUM_LLVMPIPE" = xyes)
@@ -3004,7 +2998,6 @@ AM_CONDITIONAL(HAVE_AMD_DRIVERS, test "x$HAVE_GALLIUM_RADEONSI" = xyes -o \
 AM_CONDITIONAL(HAVE_BROADCOM_DRIVERS, test "x$HAVE_GALLIUM_VC4" = xyes -o \
                                       "x$HAVE_GALLIUM_V3D" = xyes)
 
-AM_CONDITIONAL(HAVE_FREEDRENO_DRIVERS, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
 AM_CONDITIONAL(HAVE_INTEL_DRIVERS, test "x$HAVE_INTEL_VULKAN" = xyes -o \
                                         "x$HAVE_I965_DRI" = xyes)
 
@@ -3051,7 +3044,7 @@ AC_SUBST([XVMC_MAJOR], 1)
 AC_SUBST([XVMC_MINOR], 0)
 
 AC_SUBST([XA_MAJOR], 2)
-AC_SUBST([XA_MINOR], 5)
+AC_SUBST([XA_MINOR], 4)
 AC_SUBST([XA_PATCH], 0)
 AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
 
@@ -3097,7 +3090,6 @@ AC_CONFIG_FILES([Makefile
                  src/amd/vulkan/Makefile
                  src/broadcom/Makefile
                  src/compiler/Makefile
-                 src/freedreno/Makefile
                  src/egl/Makefile
                  src/egl/main/egl.pc
                  src/egl/wayland/wayland-drm/Makefile
@@ -3108,7 +3100,7 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/drivers/i915/Makefile
                  src/gallium/drivers/llvmpipe/Makefile
                  src/gallium/drivers/nouveau/Makefile
-                 src/gallium/drivers/kmsro/Makefile
+                 src/gallium/drivers/pl111/Makefile
                  src/gallium/drivers/r300/Makefile
                  src/gallium/drivers/r600/Makefile
                  src/gallium/drivers/radeonsi/Makefile
@@ -3117,6 +3109,7 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/drivers/swr/Makefile
                  src/gallium/drivers/tegra/Makefile
                  src/gallium/drivers/etnaviv/Makefile
+                 src/gallium/drivers/imx/Makefile
                  src/gallium/drivers/v3d/Makefile
                  src/gallium/drivers/vc4/Makefile
                  src/gallium/drivers/virgl/Makefile
@@ -3151,10 +3144,11 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/tests/trivial/Makefile
                  src/gallium/tests/unit/Makefile
                  src/gallium/winsys/etnaviv/drm/Makefile
+                 src/gallium/winsys/imx/drm/Makefile
                  src/gallium/winsys/freedreno/drm/Makefile
                  src/gallium/winsys/i915/drm/Makefile
                  src/gallium/winsys/nouveau/drm/Makefile
-                 src/gallium/winsys/kmsro/drm/Makefile
+                 src/gallium/winsys/pl111/drm/Makefile
                  src/gallium/winsys/radeon/drm/Makefile
                  src/gallium/winsys/amdgpu/drm/Makefile
                  src/gallium/winsys/svga/drm/Makefile

docs/autoconf.html

@@ -26,12 +26,6 @@
   </ul>
 </ol>
 
-<h2>ATTENTION:</h2>
-<p>
-    The autotools build is being replaced by the <a href="meson.html">meson</a>
-    build system. If you haven't yet now is a good time to try using meson and
-    report any issues you run into.
-</p>
 
 <h2 id="basic">1. Basic Usage</h2>
 

docs/features.txt

@@ -319,7 +319,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_EXT_memory_object                                  DONE (radeonsi)
   GL_EXT_memory_object_fd                               DONE (radeonsi)
   GL_EXT_memory_object_win32                            not started
-  GL_EXT_render_snorm                                   DONE (i965, radeonsi)
+  GL_EXT_render_snorm                                   DONE (i965)
   GL_EXT_semaphore                                      DONE (radeonsi)
   GL_EXT_semaphore_fd                                   DONE (radeonsi)
   GL_EXT_semaphore_win32                                not started
@@ -338,7 +338,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_OES_texture_float_linear                           DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
   GL_OES_texture_half_float                             DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
   GL_OES_texture_half_float_linear                      DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
-  GL_OES_texture_view                                   DONE (freedreno, i965/gen8+, r600, radeonsi, nv50, nvc0, softpipe, llvmpipe, swr)
+  GL_OES_texture_view                                   DONE (i965/gen8+)
   GL_OES_viewport_array                                 DONE (i965, nvc0, radeonsi)
   GLX_ARB_context_flush_control                         not started
   GLX_ARB_robustness_application_isolation              not started

docs/index.html

@@ -15,53 +15,6 @@
 <div class="content">
 
 <h1>News</h1>
-<h2>January 17, 2019</h2>
-<p>
-<a href="relnotes/18.3.2.html">Mesa 18.3.2</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 27, 2018</h2>
-<p>
-<a href="relnotes/18.2.8.html">Mesa 18.2.8</a> is released.
-This is a bug-fix release.
-<br>
-NOTE: It is anticipated that 18.2.8 will be the final release in the
-18.2 series. Users of 18.2 are encouraged to migrate to the 18.3
-series in order to obtain future fixes.
-</p>
-
-<h2>December 13, 2018</h2>
-<p>
-<a href="relnotes/18.2.7.html">Mesa 18.2.7</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 11, 2018</h2>
-<p>
-<a href="relnotes/18.3.1.html">Mesa 18.3.1</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>December 7, 2018</h2>
-<p>
-<a href="relnotes/18.3.0.html">Mesa 18.3.0</a> is released.  This is a
-new development release.  See the release notes for more information
-about the release.
-</p>
-
-<h2>November 28, 2018</h2>
-<p>
-<a href="relnotes/18.2.6.html">Mesa 18.2.6</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>November 15, 2018</h2>
-<p>
-<a href="relnotes/18.2.5.html">Mesa 18.2.5</a> is released.
-This is a bug-fix release.
-</p>
-
 <h2>October 31, 2018</h2>
 <p>
 <a href="relnotes/18.2.4.html">Mesa 18.2.4</a> is released.

docs/install.html

@@ -22,7 +22,6 @@
   <li><a href="#prereq-general">General prerequisites</a>
   <li><a href="#prereq-dri">For DRI and hardware acceleration</a>
   </ul>
-<li><a href="#meson">Building with meson</a>
 <li><a href="#autoconf">Building with autoconf (Linux/Unix/X11)</a>
 <li><a href="#scons">Building with SCons (Windows/Linux)</a>
 <li><a href="#android">Building with AOSP (Android)</a>
@@ -40,10 +39,9 @@ Build system.
 </p>
 
 <ul>
-<li><a href="https://mesonbuild.com">meson</a> is recommended when building on *nix platforms.
-<li>Autoconf is another option when building on *nix platforms.
+<li>Autoconf is required when building on *nix platforms.
 <li><a href="http://www.scons.org/">SCons</a> is required for building on
-Windows and optional for Linux (it's an alternative to autoconf/automake or meson.)
+Windows and optional for Linux (it's an alternative to autoconf/automake.)
 </li>
 <li>Android Build system when building as native Android component. Autoconf
 is used when when building ARC.
@@ -74,9 +72,7 @@ you think you've spotted a bug let developers know by filing a
 
 <ul>
 <li><a href="https://www.python.org/">Python</a> - Python is required.
-When building with scons 2.7 is required.
-When building with meson 3.5 or newer is required.
-When building with autotools 2.7, or 3.5 or later are required.
+Version 2.7 or later should work.
 </li>
 <li><a href="http://www.makotemplates.org/">Python Mako module</a> -
 Python Mako module is required. Version 0.8.0 or later should work.
@@ -115,31 +111,11 @@ the packaging tool used by your distro.
   ... # others
 </pre>
 
-<h1 id="meson">2. Building with meson</h1>
+
+<h1 id="autoconf">2. Building with autoconf (Linux/Unix/X11)</h1>
 
 <p>
-Meson is the latest build system in mesa, it is currently able to build for
-*nix systems like Linux and BSD, and will be able to build for windows as well.
-</p>
-
-<p>
-The general approach is:
-</p>
-<pre>
-  meson builddir/
-  ninja -C builddir/
-  sudo ninja -C builddir/ install
-</pre>
-<p>
-Please read the <a href="meson.html">detailed meson instructions</a>
-for more information
-</p>
-
-<h1 id="autoconf">3. Building with autoconf (Linux/Unix/X11)</h1>
-
-<p>
-Although meson is recommended, another supported way to build on *nix systems
-is with autoconf.
+The primary method to build Mesa on Unix systems is with autoconf.
 </p>
 
 <p>
@@ -157,7 +133,7 @@ for more details.
 
 
 
-<h1 id="scons">4. Building with SCons (Windows/Linux)</h1>
+<h1 id="scons">3. Building with SCons (Windows/Linux)</h1>
 
 <p>
 To build Mesa with SCons on Linux or Windows do
@@ -193,7 +169,7 @@ Additional information is available in <a href="README.WIN32">README.WIN32</a>.
 
 
 
-<h1 id="android">5. Building with AOSP (Android)</h1>
+<h1 id="android">4. Building with AOSP (Android)</h1>
 
 <p>
 Currently one can build Mesa for Android as part of the AOSP project, yet
@@ -212,7 +188,7 @@ Android-x86 and/or other resources.
 </p>
 
 
-<h1 id="libs">6. Library Information</h1>
+<h1 id="libs">5. Library Information</h1>
 
 <p>
 When compilation has finished, look in the top-level <code>lib/</code>
@@ -250,7 +226,7 @@ versions of libGL and device drivers.
 </p>
 
 
-<h1 id="pkg-config">7. Building OpenGL programs with pkg-config</h1>
+<h1 id="pkg-config">6. Building OpenGL programs with pkg-config</h1>
 
 <p>
 Running <code>make install</code> will install package configuration files

docs/mesa.css

@@ -29,9 +29,6 @@ pre {
 	/*font-family: monospace;*/
 	font-size: 10pt;
 	/*color: black;*/
-	background-color: #eee;
-	margin-left: 2em;
-	padding: .5em;
 }
 
 iframe {

docs/meson.html

@@ -16,11 +16,6 @@
 
 <h1>Compilation and Installation using Meson</h1>
 
-<ul>
-  <li><a href="#basic">Basic Usage</a></li>
-  <li><a href="#cross-compilation">Cross-compilation and 32-bit builds</a></li>
-</ul>
-
 <h2 id="basic">1. Basic Usage</h2>
 
 <p><strong>The Meson build system is generally considered stable and ready
@@ -53,13 +48,9 @@ To see a description of your options you can run <code>meson configure</code>
 along with a build directory to view the selected options for. This will show
 your meson global arguments and project arguments, along with their defaults
 and your local settings.
-</p>
 
-<p>
 Meson does not currently support listing options before configure a build
 directory, but this feature is being discussed upstream.
-For now, the only way to see what options exist is to look at the
-<code>meson_options.txt</code> file at the root of the project.
 </p>
 
 <pre>
@@ -114,14 +105,14 @@ to invoke non-default targets for ninja to update them:
 <dl>
 <dt><code>Environment Variables</code></dt>
 <dd><p>Meson supports the standard CC and CXX environment variables for
-changing the default compiler. Meson does support CFLAGS, CXXFLAGS, etc. But
-their use is discouraged because of the many caveats in using them. Instead it
-is recomended to use <code>-D${lang}_args</code> and
-<code>-D${lang}_link_args</code> instead. Among the benefits of these options
-is that they are guaranteed to persist across rebuilds and reconfigurations.
+changing the default compiler, and CFLAGS, CXXFLAGS, and LDFLAGS for setting
+options to the compiler and linker during the initial configuration.
 
-Meson does not allow changing compiler in a configured builddir, you will need
-to create a new build dir for a different compiler.
+These arguments are consumed and stored by meson when it is initialized. To
+change these flags after the build is initialized (or when doing a first
+initialization), consider using <code>-D${lang}_args</code> and
+<code>-D${lang}_link_args</code> instead. Meson will never change compiler in a
+configured build directory.
 </p>
 
 <pre>
@@ -144,56 +135,11 @@ the popular compilers, a complete list is available
 
 <dt><code>LLVM</code></dt>
 <dd><p>Meson includes upstream logic to wrap llvm-config using its standard
-dependency interface.
+dependency interface. It will search <code>$PATH</code> (or <code>%PATH%</code> on windows) for
+llvm-config (and llvm-config$version and llvm-config-$version), so using an
+LLVM from a non-standard path is as easy as
+<code>PATH=/path/with/llvm-config:$PATH meson build</code>.
 </p></dd>
-
-<dd><p>
-As of meson 0.49.0 meson also has the concept of a
-<a href="https://mesonbuild.com/Native-environments.html">"native file"</a>,
-these files provide information about the native build environment (as opposed
-to a cross build environment). They are ini formatted and can override where to
-find llvm-config:
-
-custom-llvm.ini
-<pre>
-    [binaries]
-    llvm-config = '/usr/local/bin/llvm/llvm-config'
-</pre>
-
-Then configure meson:
-
-<pre>
-    meson builddir/ --native-file custom-llvm.ini
-</pre>
-</p></dd>
-
-<dd><p>
-For selecting llvm-config for cross compiling a
-<a href="https://mesonbuild.com/Cross-compilation.html#defining-the-environment">"cross file"</a>
-should be used. It uses the same format as the native file above:
-
-cross-llvm.ini
-<pre>
-    [binaries]
-    ...
-    llvm-config = '/usr/lib/llvm-config-32'
-</pre>
-
-Then configure meson:
-
-<pre>
-    meson builddir/ --cross-file cross-llvm.ini
-</pre>
-
-See the <a href="#cross-compilation">Cross Compilation</a> section for more information.
-</dd></p>
-
-<dd><p>
-For older versions of meson <code>$PATH</code> (or <code>%PATH%</code> on
-windows) will be searched for llvm-config (and llvm-config$version and
-llvm-config-$version), you can override this environment variable to control
-the search: <code>PATH=/path/with/llvm-config:$PATH meson build</code>.
-</dd></p>
 </dl>
 
 <dl>
@@ -244,93 +190,6 @@ is unrelated to the <code>buildtype</code>; setting the latter to
 </dd>
 </dl>
 
-<h2 id="cross-compilation">2. Cross-compilation and 32-bit builds</h2>
-
-<p><a href="https://mesonbuild.com/Cross-compilation.html">Meson supports
-cross-compilation</a> by specifying a number of binary paths and
-settings in a file and passing this file to <code>meson</code> or
-<code>meson configure</code> with the <code>--cross-file</code>
-parameter.</p>
-
-<p>This file can live at any location, but you can use the bare filename
-(without the folder path) if you put it in $XDG_DATA_HOME/meson/cross or
-~/.local/share/meson/cross</p>
-
-<p>Below are a few example of cross files, but keep in mind that you
-will likely have to alter them for your system.</p>
-
-<p>
-Those running on ArchLinux can use the AUR-maintained packages for some
-of those, as they'll have the right values for your system:
-<ul>
-  <li><a href="https://aur.archlinux.org/packages/meson-cross-x86-linux-gnu">meson-cross-x86-linux-gnu</a></li>
-  <li><a href="https://aur.archlinux.org/packages/meson-cross-aarch64-linux-gnu">meson-cross-aarch64-linux-gnu</a></li>
-</ul>
-</p>
-
-<p>
-32-bit build on x86 linux:
-<pre>
-[binaries]
-c = '/usr/bin/gcc'
-cpp = '/usr/bin/g++'
-ar = '/usr/bin/gcc-ar'
-strip = '/usr/bin/strip'
-pkgconfig = '/usr/bin/pkg-config-32'
-llvm-config = '/usr/bin/llvm-config32'
-
-[properties]
-c_args = ['-m32']
-c_link_args = ['-m32']
-cpp_args = ['-m32']
-cpp_link_args = ['-m32']
-
-[host_machine]
-system = 'linux'
-cpu_family = 'x86'
-cpu = 'i686'
-endian = 'little'
-</pre>
-</p>
-
-<p>
-64-bit build on ARM linux:
-<pre>
-[binaries]
-c = '/usr/bin/aarch64-linux-gnu-gcc'
-cpp = '/usr/bin/aarch64-linux-gnu-g++'
-ar = '/usr/bin/aarch64-linux-gnu-gcc-ar'
-strip = '/usr/bin/aarch64-linux-gnu-strip'
-pkgconfig = '/usr/bin/aarch64-linux-gnu-pkg-config'
-exe_wrapper = '/usr/bin/qemu-aarch64-static'
-
-[host_machine]
-system = 'linux'
-cpu_family = 'aarch64'
-cpu = 'aarch64'
-endian = 'little'
-</pre>
-</p>
-
-<p>
-64-bit build on x86 windows:
-<pre>
-[binaries]
-c = '/usr/bin/x86_64-w64-mingw32-gcc'
-cpp = '/usr/bin/x86_64-w64-mingw32-g++'
-ar = '/usr/bin/x86_64-w64-mingw32-ar'
-strip = '/usr/bin/x86_64-w64-mingw32-strip'
-pkgconfig = '/usr/bin/x86_64-w64-mingw32-pkg-config'
-exe_wrapper = 'wine'
-
-[host_machine]
-system = 'windows'
-cpu_family = 'x86_64'
-cpu = 'i686'
-endian = 'little'
-</pre>
-</p>
-
 </div>
 </body>
 </html>

docs/release-calendar.html

@@ -23,16 +23,6 @@ Mesa provides feature/development and stable releases.
 The table below lists the date and release manager that is expected to do the
 specific release.
 <br>
-Regular updates will ensure that the schedule for the current and the
-next two feature releases are shown in the table.
-<br>
-In order to keep the whole releasing team up to date with the tools
-used, best practices and other details, the member in charge of the
-next feature release will be in constant rotation.
-<br>
-The way the release schedule works is
-explained <a href="releasing.html#schedule" target="_parent">here</a>.
-<br>
 Take a look <a href="submittingpatches.html#criteria" target="_parent">here</a>
 if you'd like to nominate a patch in the next stable release.
 </p>
@@ -49,129 +39,47 @@ if you'd like to nominate a patch in the next stable release.
 <th>Notes</th>
 </tr>
 <tr>
+<td rowspan="3">18.2</td>
+<td>2018-11-14</td>
+<td>18.2.5</td>
+<td>Juan A. Suarez</td>
+<td/>
+</tr>
+<tr>
+<td>2018-11-28</td>
+<td>18.2.6</td>
+<td>Juan A. Suarez</td>
+<td/>
+</tr>
+<tr>
+<td>2018-12-12</td>
+<td>18.2.7</td>
+<td>Juan A. Suarez</td>
+<td>Last planned 18.2.x release</td>
+</tr>
 <td rowspan="4">18.3</td>
-<td>2019-01-30</td>
-<td>18.3.3</td>
+<td>2018-10-31</td>
+<td>18.3.0-rc1</td>
 <td>Emil Velikov</td>
-<td>
+<td></td>
 </tr>
 <tr>
-<td>2019-02-13</td>
-<td>18.3.4</td>
+<td>2018-11-07</td>
+<td>18.3.0-rc2</td>
 <td>Emil Velikov</td>
-<td>
+<td/>
 </tr>
 <tr>
-<td>2019-02-27</td>
-<td>18.3.5</td>
+<td>2018-11-14</td>
+<td>18.3.0-rc3</td>
 <td>Emil Velikov</td>
-<td>
+<td/>
 </tr>
 <tr>
-<td>2019-03-13</td>
-<td>18.3.6</td>
+<td>2018-11-21</td>
+<td>18.3.0-rc4</td>
 <td>Emil Velikov</td>
-<td>Last planned 18.3.x release</td>
-</tr>
-<tr>
-<td rowspan="4">19.0</td>
-<td>2019-01-29</td>
-<td>19.0.0-rc1</td>
-<td>Dylan Baker</td>
-<td>
-</tr>
-<tr>
-<td>2019-02-05</td>
-<td>19.0.0-rc2</td>
-<td>Dylan Baker</td>
-<td>
-</tr>
-<tr>
-<td>2019-02-12</td>
-<td>19.0.0-rc3</td>
-<td>Dylan Baker</td>
-<td>
-</tr>
-<tr>
-<td>2019-02-19</td>
-<td>19.0.0-rc4</td>
-<td>Dylan Baker</td>
-<td>Last planned RC/Final release</td>
-</tr>
-<tr>
-<td rowspan="4">19.1</td>
-<td>2019-04-30</td>
-<td>19.1.0-rc1</td>
-<td>Andres Gomez</td>
-<td>
-</tr>
-<tr>
-<td>2019-05-07</td>
-<td>19.1.0-rc2</td>
-<td>Andres Gomez</td>
-<td>
-</tr>
-<tr>
-<td>2019-05-14</td>
-<td>19.1.0-rc3</td>
-<td>Andres Gomez</td>
-<td>
-</tr>
-<tr>
-<td>2019-05-21</td>
-<td>19.1.0-rc4</td>
-<td>Andres Gomez</td>
-<td>Last planned RC/Final release</td>
-</tr>
-<tr>
-<td rowspan="4">19.2</td>
-<td>2019-08-06</td>
-<td>19.2.0-rc1</td>
-<td>Emil Velikov</td>
-<td>
-</tr>
-<tr>
-<td>2019-08-13</td>
-<td>19.2.0-rc2</td>
-<td>Emil Velikov</td>
-<td>
-</tr>
-<tr>
-<td>2019-08-20</td>
-<td>19.2.0-rc3</td>
-<td>Emil Velikov</td>
-<td>
-</tr>
-<tr>
-<td>2019-08-27</td>
-<td>19.2.0-rc4</td>
-<td>Emil Velikov</td>
-<td>Last planned RC/Final release</td>
-</tr>
-<tr>
-<td rowspan="4">19.3</td>
-<td>2019-10-15</td>
-<td>19.3.0-rc1</td>
-<td>Juan A. Suarez</td>
-<td>
-</tr>
-<tr>
-<td>2019-10-22</td>
-<td>19.3.0-rc2</td>
-<td>Juan A. Suarez</td>
-<td>
-</tr>
-<tr>
-<td>2019-10-29</td>
-<td>19.3.0-rc3</td>
-<td>Juan A. Suarez</td>
-<td>
-</tr>
-<tr>
-<td>2019-11-05</td>
-<td>19.3.0-rc4</td>
-<td>Juan A. Suarez</td>
-<td>Last planned RC/Final release</td>
+<td>Last planned RC/final release</td>
 </tr>
 </table>
 

docs/releasing.html

@@ -56,10 +56,9 @@ For example:
 
 <p>
 Releases should happen on Wednesdays. Delays can occur although those
-should be kept to a minimum.
+should be keep to a minimum.
 <br>
-See our <a href="release-calendar.html" target="_parent">calendar</a>
-for information about how the release schedule is planned, and the
+See our <a href="release-calendar.html" target="_parent">calendar</a> for the
 date and other details for individual releases.
 </p>
 
@@ -68,9 +67,6 @@ date and other details for individual releases.
 <li>Available approximately every three months.
 <li>Initial timeplan available 2-4 weeks before the planned branchpoint (rc1)
 on the mesa-announce@ mailing list.
-<li>Typically, the final release will happen after 4
-candidates. Additional ones may be needed in order to resolve blocking
-regressions, though.
 <li>A <a href="#prerelease">pre-release</a> announcement should be available
 approximately 24 hours before the final (non-rc) release.
 </ul>
@@ -88,12 +84,6 @@ Note: There is one or two releases overlap when changing branches. For example:
 <br>
 The final release from the 12.0 series Mesa 12.0.5 will be out around the same
 time (or shortly after) 13.0.1 is out.
-<br>
-This also involves that, as a final release may be delayed due to the
-need of additional candidates to solve some blocking regression(s),
-the release manager might have to update
-the <a href="release-calendar.html" target="_parent">calendar</a> with
-additional bug fix releases of the current stable branch.
 </p>
 
 
@@ -122,21 +112,18 @@ the autoconf and scons build.
 <p>Done continuously up-to the <a href="#prerelease">pre-release</a> announcement.</p>
 
 <p>
-Developers can request, <em>as an exception</em>, patches to be applied up-to
-the last one hour before the actual release. This is made <strong>only</strong>
-with explicit permission/request, and the patch <strong>must</strong> be very
-well contained. Thus it cannot affect more than one driver/subsystem.
+As an exception, patches can be applied up-to the last ~1h before the actual
+release. This is made <strong>only</strong> with explicit permission/request,
+and the patch <strong>must</strong> be very well contained. Thus it cannot
+affect more than one driver/subsystem.
 </p>
 
-<p>Following developers have requested permanent exception</p>
-<ul>
-<li><em>Ilia Mirkin</em>
-<li><em>AMD team</em>
-</ul>
+<p>
+Currently Ilia Mirkin and AMD devs have requested "permanent" exception.
+</p>
 
-<p>The following must pass:</p>
 <ul>
-<li>make distcheck, scons and scons check
+<li>make distcheck, scons and scons check must pass
 <li>Testing with different version of system components - LLVM and others is also
 performed where possible.
 <li>As a general rule, testing with various combinations of configure
@@ -144,9 +131,9 @@ switches, depending on the specific patchset.
 </ul>
 
 <p>
-These are achieved by combination of <a href="basictesting">local testing</a>,
-which includes mingw-w64 cross compilation and AppVeyor plus Travis-CI, the
-latter two as part of their Github integration.
+Achieved by combination of local ad-hoc scripts, mingw-w64 cross
+compilation and AppVeyor plus Travis-CI, the latter as part of their
+Github integration.
 </p>
 
 <p>
@@ -238,7 +225,7 @@ in the main repository under <code>staging/X.Y</code>. For example:
 Notes:
 </p>
 <ul>
-<li>People are encouraged to test the staging branch and report regressions.</li>
+<li>People are encouraged to test the branch and report regressions.</li>
 <li>The branch history is not stable and it <strong>will</strong> be rebased,</li>
 </ul>
 
@@ -458,7 +445,7 @@ Ensure the latest code is available - both in your local master and the
 relevant branch.
 </p>
 
-<h3 id="basictesting">Perform basic testing</h3>
+<h3>Perform basic testing</h3>
 
 <p>
 Most of the testing should already be done during the

docs/relnotes.html

@@ -21,13 +21,6 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>
 
 <ul>
-<li><a href="relnotes/18.3.2.html">18.3.2 release notes</a>
-<li><a href="relnotes/18.2.8.html">18.2.8 release notes</a>
-<li><a href="relnotes/18.2.7.html">18.2.7 release notes</a>
-<li><a href="relnotes/18.3.1.html">18.3.1 release notes</a>
-<li><a href="relnotes/18.3.0.html">18.3.0 release notes</a>
-<li><a href="relnotes/18.2.6.html">18.2.6 release notes</a>
-<li><a href="relnotes/18.2.5.html">18.2.5 release notes</a>
 <li><a href="relnotes/18.2.4.html">18.2.4 release notes</a>
 <li><a href="relnotes/18.2.3.html">18.2.3 release notes</a>
 <li><a href="relnotes/18.2.2.html">18.2.2 release notes</a>

docs/relnotes/18.2.5.html

@@ -1,172 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.2.5 Release Notes / November 15, 2018</h1>
-
-<p>
-Mesa 18.2.5 is a bug fix release which fixes bugs found since the 18.2.4 release.
-</p>
-<p>
-Mesa 18.2.5 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-dddc28928b6f4083a0d5120b58c1c8e2dc189ab5c14299c08a386607fdbbdce7  mesa-18.2.5.tar.gz
-b12c32872832e5353155e1e8026e1f1ab75bba9dc5b178d712045684d26c2b73  mesa-18.2.5.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105731">Bug 105731</a> - linker error &quot;fragment shader input ... has no matching output in the previous stage&quot; when previous stage's output declaration in a separate shader object</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107511">Bug 107511</a> - KHR/khrplatform.h not always installed when needed</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107626">Bug 107626</a> - [SNB] The graphical corruption and GPU hang occur sometimes on the piglit test &quot;arb_texture_multisample-large-float-texture&quot; with parameter --fp16</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108082">Bug 108082</a> - warning: unknown warning option '-Wno-format-truncation' [-Wunknown-warning-option]</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108560">Bug 108560</a> - Mesa 32 is built without sse</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andre Heider (1):</p>
-<ul>
-  <li>st/nine: fix stack corruption due to ABI mismatch</li>
-</ul>
-
-<p>Andrii Simiklit (1):</p>
-<ul>
-  <li>i965/batch: don't ignore the 'brw_new_batch' call for a 'new batch'</li>
-</ul>
-
-<p>Dylan Baker (2):</p>
-<ul>
-  <li>meson: link gallium nine with pthreads</li>
-  <li>meson: fix libatomic tests</li>
-</ul>
-
-<p>Emil Velikov (2):</p>
-<ul>
-  <li>egl/glvnd: correctly report errors when vendor cannot be found</li>
-  <li>m4: add Werror when checking for compiler flags</li>
-</ul>
-
-<p>Eric Engestrom (6):</p>
-<ul>
-  <li>svga: add missing meson build dependency</li>
-  <li>clover: add missing meson build dependency</li>
-  <li>wsi/wayland: use proper VkResult type</li>
-  <li>wsi/wayland: only finish() a successfully init()ed display</li>
-  <li>configure: install KHR/khrplatform.h when needed</li>
-  <li>meson: install KHR/khrplatform.h when needed</li>
-</ul>
-
-<p>Gert Wollny (1):</p>
-<ul>
-  <li>virgl/vtest-winsys: Use virgl version of bind flags</li>
-</ul>
-
-<p>Jonathan Gray (1):</p>
-<ul>
-  <li>intel/tools: include stdarg.h in error2aub</li>
-</ul>
-
-<p>Juan A. Suarez Romero (4):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.2.4</li>
-  <li>cherry-ignore: add explicit 18.3 only nominations</li>
-  <li>cherry-ignore: i965/batch: avoid reverting batch buffer if saved state is an empty</li>
-  <li>Update version to 18.2.5</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>anv/android: mark gralloc allocated BOs as external</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>ac: fix ac_build_fdiv for f64</li>
-  <li>st/va: fix incorrect use of resource_destroy</li>
-  <li>include: update GL &amp; GLES headers (v2)</li>
-</ul>
-
-<p>Matt Turner (2):</p>
-<ul>
-  <li>util/ralloc: Switch from DEBUG to NDEBUG</li>
-  <li>util/ralloc: Make sizeof(linear_header) a multiple of 8</li>
-</ul>
-
-<p>Olivier Fourdan (1):</p>
-<ul>
-  <li>wayland/egl: Resize EGL surface on update buffer for swrast</li>
-</ul>
-
-<p>Rhys Perry (1):</p>
-<ul>
-  <li>glsl_to_tgsi: don't create 64-bit integer MAD/FMA</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv: disable conditional rendering for vkCmdCopyQueryPoolResults()</li>
-  <li>radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+</li>
-</ul>
-
-<p>Sergii Romantsov (1):</p>
-<ul>
-  <li>autotools: library-dependency when no sse and 32-bit</li>
-</ul>
-
-<p>Timothy Arceri (4):</p>
-<ul>
-  <li>st/mesa: calculate buffer size correctly for packed uniforms</li>
-  <li>st/glsl_to_nir: fix next_stage gathering</li>
-  <li>nir: add glsl_type_is_integer() helper</li>
-  <li>nir: don't pack varyings ints with floats unless flat</li>
-</ul>
-
-<p>Vadym Shovkoplias (1):</p>
-<ul>
-  <li>glsl/linker: Fix out variables linking during single stage</li>
-</ul>
-
-<p>Vinson Lee (1):</p>
-<ul>
-  <li>r600/sb: Fix constant logical operand in assert.</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.2.6.html

@@ -1,179 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.2.6 Release Notes / November 28, 2018</h1>
-
-<p>
-Mesa 18.2.6 is a bug fix release which fixes bugs found since the 18.2.5 release.
-</p>
-<p>
-Mesa 18.2.6 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-e0ea1236dbc6c412b02e1b5d7f838072525971a6630246fa82ae4466a6d8a587  mesa-18.2.6.tar.gz
-9ebafa4f8249df0c718e93b9ca155e3593a1239af303aa2a8b0f2056a7efdc12  mesa-18.2.6.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107626">Bug 107626</a> - [SNB] The graphical corruption and GPU hang occur sometimes on the piglit test &quot;arb_texture_multisample-large-float-texture&quot; with parameter --fp16</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107856">Bug 107856</a> - i965 incorrectly calculates the number of layers for texture views (assert)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108630">Bug 108630</a> - [G965] piglit.spec.!opengl 1_2.tex3d-maxsize spins forever</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108713">Bug 108713</a> - Gallium: use after free with transform feedback</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108829">Bug 108829</a> - [meson] libglapi exports internal API</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andrii Simiklit (1):</p>
-<ul>
-  <li>i965/batch: avoid reverting batch buffer if saved state is an empty</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (1):</p>
-<ul>
-  <li>radv: Fix opaque metadata descriptor last layer.</li>
-</ul>
-
-<p>Brian Paul (1):</p>
-<ul>
-  <li>scons/svga: remove opt from the list of valid build types</li>
-</ul>
-
-<p>Danylo Piliaiev (1):</p>
-<ul>
-  <li>i965: Fix calculation of layers array length for isl_view</li>
-</ul>
-
-<p>Dylan Baker (2):</p>
-<ul>
-  <li>meson: Don't set -Wall</li>
-  <li>meson: Don't force libva to required from auto</li>
-</ul>
-
-<p>Emil Velikov (13):</p>
-<ul>
-  <li>bin/get-pick-list.sh: simplify git oneline printing</li>
-  <li>bin/get-pick-list.sh: prefix output with "[stable] "</li>
-  <li>bin/get-pick-list.sh: handle "typod" usecase.</li>
-  <li>bin/get-pick-list.sh: handle the fixes tag</li>
-  <li>bin/get-pick-list.sh: tweak the commit sha matching pattern</li>
-  <li>bin/get-pick-list.sh: flesh out is_sha_nomination</li>
-  <li>bin/get-pick-list.sh: handle fixes tag with missing colon</li>
-  <li>bin/get-pick-list.sh: handle unofficial "broken by" tag</li>
-  <li>bin/get-pick-list.sh: use test instead of [ ]</li>
-  <li>bin/get-pick-list.sh: handle reverts prior to the branchpoint</li>
-  <li>travis: drop unneeded x11proto-xf86vidmode-dev</li>
-  <li>glx: make xf86vidmode mandatory for direct rendering</li>
-  <li>travis: adding missing x11-xcb for meson+vulkan</li>
-</ul>
-
-<p>Eric Anholt (1):</p>
-<ul>
-  <li>vc4: Make sure we make ro scanout resources for create_with_modifiers.</li>
-</ul>
-
-<p>Eric Engestrom (5):</p>
-<ul>
-  <li>meson: only run vulkan's meson.build when building vulkan</li>
-  <li>gbm: remove unnecessary meson include</li>
-  <li>meson: fix wayland-less builds</li>
-  <li>egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache</li>
-  <li>glapi: add missing visibility args</li>
-</ul>
-
-<p>Erik Faye-Lund (1):</p>
-<ul>
-  <li>mesa/main: remove bogus error for zero-sized images</li>
-</ul>
-
-<p>Gert Wollny (3):</p>
-<ul>
-  <li>mesa: Reference count shaders that are used by transform feedback objects</li>
-  <li>r600: clean up the GS ring buffers when the context is destroyed</li>
-  <li>glsl: free or reuse memory allocated for TF varying</li>
-</ul>
-
-<p>Jason Ekstrand (2):</p>
-<ul>
-  <li>nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16</li>
-  <li>anv: Put robust buffer access in the pipeline hash</li>
-</ul>
-
-<p>Juan A. Suarez Romero (6):</p>
-<ul>
-  <li>cherry-ignore: add explicit 18.3 only nominations</li>
-  <li>cherry-ignore: intel/aub_viewer: fix dynamic state printing</li>
-  <li>cherry-ignore: intel/aub_viewer: Print blend states properly</li>
-  <li>cherry-ignore: mesa/main: fix incorrect depth-error</li>
-  <li>docs: add sha256 checksums for 18.2.5</li>
-  <li>Update version to 18.2.6</li>
-</ul>
-
-<p>Karol Herbst (1):</p>
-<ul>
-  <li>nir/spirv: cast shift operand to u32</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Add PCI IDs for new Amberlake parts that are Coffeelake based</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>egl/dri: fix error value with unknown drm format</li>
-</ul>
-
-<p>Marek Olšák (2):</p>
-<ul>
-  <li>winsys/amdgpu: fix a buffer leak in amdgpu_bo_from_handle</li>
-  <li>winsys/amdgpu: fix a device handle leak in amdgpu_winsys_create</li>
-</ul>
-
-<p>Rodrigo Vivi (4):</p>
-<ul>
-  <li>i965: Add a new CFL PCI ID.</li>
-  <li>intel: aubinator: Adding missed platforms to the error message.</li>
-  <li>intel: Introducing Amber Lake platform</li>
-  <li>intel: Introducing Whiskey Lake platform</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.2.7.html

@@ -1,167 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.2.7 Release Notes / December 13, 2018</h1>
-
-<p>
-Mesa 18.2.7 is a bug fix release which fixes bugs found since the 18.2.6 release.
-</p>
-<p>
-Mesa 18.2.7 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-092351cfbcd430ec595fbd3a3d8d253fd62c29074e1740d7198b00289ab400f8  mesa-18.2.7.tar.gz
-9c7b02560d89d77ca279cd21f36ea9a49e9ffc5611f6fe35099357d744d07ae6  mesa-18.2.7.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106577">Bug 106577</a> - broken rendering with nine and nouveau (GM107)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108245">Bug 108245</a> - RADV/Vega: Low mip levels of large BCn textures get corrupted by vkCmdCopyBufferToImage</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108311">Bug 108311</a> - Query buffer object support is broken on r600.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108894">Bug 108894</a> - [anv] vkCmdCopyBuffer() and vkCmdCopyQueryPoolResults() write-after-write hazard</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108909">Bug 108909</a> - Vkd3d test failure test_resolve_non_issued_query_data()</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108914">Bug 108914</a> - blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108925">Bug 108925</a> - vkCmdCopyQueryPoolResults(VK_QUERY_RESULT_WAIT_BIT) for timestamps with large query count hangs</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Smith (1):</p>
-<ul>
-  <li>radv: Flush before vkCmdWriteTimestamp() if needed</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (4):</p>
-<ul>
-  <li>radv: Align large buffers to the fragment size.</li>
-  <li>radv: Clamp gfx9 image view extents to the allocated image extents.</li>
-  <li>radv/android: Mark android WSI image as shareable.</li>
-  <li>radv/android: Use buffer metadata to determine scanout compat.</li>
-</ul>
-
-<p>Dave Airlie (2):</p>
-<ul>
-  <li>r600: make suballocator 256-bytes align</li>
-  <li>radv: use 3d shader for gfx9 copies if dst is 3d</li>
-</ul>
-
-<p>Emil Velikov (2):</p>
-<ul>
-  <li>egl/wayland: bail out when drmGetMagic fails</li>
-  <li>egl/wayland: plug memory leak in drm_handle_device()</li>
-</ul>
-
-<p>Eric Anholt (3):</p>
-<ul>
-  <li>v3d: Fix a leak of the transfer helper on screen destroy.</li>
-  <li>vc4: Fix a leak of the transfer helper on screen destroy.</li>
-  <li>v3d: Fix a leak of the disassembled instruction string during debug dumps.</li>
-</ul>
-
-<p>Eric Engestrom (3):</p>
-<ul>
-  <li>anv: correctly use vulkan 1.0 by default</li>
-  <li>wsi/display: fix mem leak when freeing swapchains</li>
-  <li>vulkan/wsi: fix s/,/;/ typo</li>
-</ul>
-
-<p>Gurchetan Singh (3):</p>
-<ul>
-  <li>virgl: quadruple command buffer size</li>
-  <li>virgl: avoid large inline transfers</li>
-  <li>virgl: don't mark buffers as unclean after a write</li>
-</ul>
-
-<p>Juan A. Suarez Romero (4):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.2.6</li>
-  <li>cherry-ignore: freedreno: Fix autotools build.</li>
-  <li>cherry-ignore: mesa: Revert INTEL_fragment_shader_ordering support</li>
-  <li>Update version to 18.2.7</li>
-</ul>
-
-<p>Karol Herbst (1):</p>
-<ul>
-  <li>nv50,nvc0: Fix gallium nine regression regarding sampler bindings</li>
-</ul>
-
-<p>Lionel Landwerlin (2):</p>
-<ul>
-  <li>anv: flush pipeline before query result copies</li>
-  <li>anv/query: flush render target before copying results</li>
-</ul>
-
-<p>Michal Srb (2):</p>
-<ul>
-  <li>gallium: Constify drisw_loader_funcs struct</li>
-  <li>drisw: Use separate drisw_loader_funcs for shm</li>
-</ul>
-
-<p>Nicolai Hähnle (2):</p>
-<ul>
-  <li>egl/wayland: rather obvious build fix</li>
-  <li>meson: link LLVM 'native' component when LLVM is available</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: rework the TC-compat HTILE hardware bug with COND_EXEC</li>
-</ul>
-
-<p>Thomas Hellstrom (2):</p>
-<ul>
-  <li>st/xa: Fix a memory leak</li>
-  <li>winsys/svga: Fix a memory leak</li>
-</ul>
-
-<p>Tobias Klausmann (1):</p>
-<ul>
-  <li>amd/vulkan: meson build - use radv_deps for libvulkan_radeon</li>
-</ul>
-
-<p>Vinson Lee (1):</p>
-<ul>
-  <li>st/xvmc: Add X11 include path.</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.2.8.html

@@ -1,183 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.2.8 Release Notes / December 27, 2018</h1>
-
-<p>
-Mesa 18.2.8 is a bug fix release which fixes bugs found since the 18.2.7 release.
-</p>
-<p>
-Mesa 18.2.8 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-77512edc0a84e19c7131a0e2e5ebf1beaf1494dc4b71508fcc92d06d65f9f4f5  mesa-18.2.8.tar.gz
-1d2ed9fd435d86d95b7215b287258d3e6b1180293a36f688e5a2efc18298d863  mesa-18.2.8.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108114">Bug 108114</a> - [vulkancts] new VK_KHR_16bit_storage tests fail.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108116">Bug 108116</a> - [vulkancts] stencil partial clear tests fail.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108910">Bug 108910</a> - Vkd3d test failure test_multisample_array_texture()</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108911">Bug 108911</a> - Vkd3d test failure test_clear_render_target_view()</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109081">Bug 109081</a> - [bisected] [HSW] Regression in clipping.user_defined.clip_* vulkancts tests</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Alex Deucher (3):</p>
-<ul>
-  <li>pci_ids: add new vega10 pci ids</li>
-  <li>pci_ids: add new vega20 pci id</li>
-  <li>pci_ids: add new VegaM pci id</li>
-</ul>
-
-<p>Axel Davy (3):</p>
-<ul>
-  <li>st/nine: Fix volumetexture dtor on ctor failure</li>
-  <li>st/nine: Bind src not dst in nine_context_box_upload</li>
-  <li>st/nine: Add src reference to nine_context_range_upload</li>
-</ul>
-
-<p>Caio Marcelo de Oliveira Filho (1):</p>
-<ul>
-  <li>nir: properly clear the entry sources in copy_prop_vars</li>
-</ul>
-
-<p>Dylan Baker (1):</p>
-<ul>
-  <li>meson: Fix ppc64 little endian detection</li>
-</ul>
-
-<p>Emil Velikov (9):</p>
-<ul>
-  <li>glx: mandate xf86vidmode only for "drm" dri platforms</li>
-  <li>bin/get-pick-list.sh: rework handing of sha nominations</li>
-  <li>bin/get-pick-list.sh: warn when commit lists invalid sha</li>
-  <li>meson: don't require glx/egl/gbm with gallium drivers</li>
-  <li>pipe-loader: meson: reference correct library</li>
-  <li>TODO: glx: meson: build dri based glx tests, only with -Dglx=dri</li>
-  <li>glx: meson: drop includes from a link-only library</li>
-  <li>glx: meson: wire up the dispatch-index-check test</li>
-  <li>glx/test: meson: assorted include fixes</li>
-</ul>
-
-<p>Eric Anholt (2):</p>
-<ul>
-  <li>v3d: Make sure that a thrsw doesn't split a multop from its umul24.</li>
-  <li>v3d: Add missing flagging of SYNCB as a TSY op.</li>
-</ul>
-
-<p>Erik Faye-Lund (2):</p>
-<ul>
-  <li>virgl: wrap vertex element state in a struct</li>
-  <li>virgl: work around bad assumptions in virglrenderer</li>
-</ul>
-
-<p>Iago Toral Quiroga (1):</p>
-<ul>
-  <li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
-</ul>
-
-<p>Ian Romanick (2):</p>
-<ul>
-  <li>i965/vec4/dce: Don't narrow the write mask if the flags are used</li>
-  <li>Revert "nir/lower_indirect: Bail early if modes == 0"</li>
-</ul>
-
-<p>Jan Vesely (1):</p>
-<ul>
-  <li>clover: Fix build after clang r348827</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>nir/constant_folding: Fix source bit size logic</li>
-</ul>
-
-<p>Jon Turney (1):</p>
-<ul>
-  <li>glx: Fix compilation with GLX_USE_WINDOWSGL</li>
-</ul>
-
-<p>Juan A. Suarez Romero (7):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.2.7</li>
-  <li>cherry-ignore: add explicit 18.3 only nominations</li>
-  <li>cherry-ignore: meson: libfreedreno depends upon libdrm (for fence support)</li>
-  <li>cherry-ignore: radv: Fix multiview depth clears</li>
-  <li>cherry-ignore: nir: properly find the entry to keep in copy_prop_vars</li>
-  <li>cherry-ignore: intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs</li>
-  <li>Update version to 18.2.8</li>
-</ul>
-
-<p>Kirill Burtsev (1):</p>
-<ul>
-  <li>loader: free error state, when checking the drawable type</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>anv: don't do partial resolve on layer &gt; 0</li>
-</ul>
-
-<p>Rhys Perry (2):</p>
-<ul>
-  <li>radv: don't set surf_index for stencil-only images</li>
-  <li>ac: split 16-bit ssbo loads that may not be dword aligned</li>
-</ul>
-
-<p>Rob Clark (1):</p>
-<ul>
-  <li>mesa/st/nir: fix missing nir_compact_varyings</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: switch on EOP when primitive restart is enabled with triangle strips</li>
-</ul>
-
-<p>Vinson Lee (2):</p>
-<ul>
-  <li>meson: Fix typo.</li>
-  <li>meson: Fix libsensors detection.</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.3.3.html

@@ -0,0 +1,208 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.3.3 Release Notes / January 31, 2019</h1>
+
+<p>
+Mesa 18.3.3 is a bug fix release which fixes bugs found since the 18.3.2 release.
+</p>
+<p>
+Mesa 18.3.3 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+6b9893942fe8011c7736d51448deb6ef80ece2257e0fac27b02e997a6605d5e4  mesa-18.3.3.tar.gz
+2ab6886a6966c532ccbcc3b240925e681464b658244f0cbed752615af3936299  mesa-18.3.3.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108877">Bug 108877</a> - OpenGL CTS gl43 test cases were interrupted due to segment fault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109023">Bug 109023</a> - error: inlining failed in call to always_inline ‘__m512 _mm512_and_ps(__m512, __m512)’: target specific option mismatch</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109129">Bug 109129</a> - format_types.h:1220: undefined reference to `_mm256_cvtps_ph'</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109229">Bug 109229</a> - glLinkProgram locks up for ~30 seconds</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109242">Bug 109242</a> - [RADV] The Witcher 3 system freeze</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109488">Bug 109488</a> - Mesa 18.3.2 crash on a specific fragment shader (assert triggered) / already fixed on the master branch.</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Andres Gomez (2):</p>
+<ul>
+  <li>bin/get-pick-list.sh: fix the oneline printing</li>
+  <li>bin/get-pick-list.sh: fix redirection in sh</li>
+</ul>
+
+<p>Axel Davy (1):</p>
+<ul>
+  <li>st/nine: Immediately upload user provided textures</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+  <li>radv: Only use 32 KiB per threadgroup on Stoney.</li>
+  <li>radv: Set partial_vs_wave for pipelines with just GS, not tess.</li>
+  <li>nir: Account for atomics in copy propagation.</li>
+</ul>
+
+<p>Bruce Cherniak (1):</p>
+<ul>
+  <li>gallium/swr: Fix multi-context sync fence deadlock.</li>
+</ul>
+
+<p>Carsten Haitzler (Rasterman) (2):</p>
+<ul>
+  <li>vc4: Use named parameters for the NEON inline asm.</li>
+  <li>vc4: Declare the cpu pointers as being modified in NEON asm.</li>
+</ul>
+
+<p>Danylo Piliaiev (1):</p>
+<ul>
+  <li>glsl: Fix copying function's out to temp if dereferenced by array</li>
+</ul>
+
+<p>Dave Airlie (3):</p>
+<ul>
+  <li>dri_interface: add put shm image2 (v2)</li>
+  <li>glx: add support for putimageshm2 path (v2)</li>
+  <li>gallium: use put image shm2 path (v2)</li>
+</ul>
+
+<p>Dylan Baker (4):</p>
+<ul>
+  <li>meson: allow building dri driver without window system if osmesa is classic</li>
+  <li>meson: fix swr KNL build</li>
+  <li>meson: Fix compiler checks for SWR with ICC</li>
+  <li>meson: Add warnings and errors when using ICC</li>
+</ul>
+
+<p>Emil Velikov (4):</p>
+<ul>
+  <li>docs: add sha256 checksums for 18.3.2</li>
+  <li>cherry-ignore: radv: Fix multiview depth clears</li>
+  <li>cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices</li>
+  <li>cherry-ignore: WARNING: Commit XXX lists invalid sha</li>
+</ul>
+
+<p>Eric Anholt (2):</p>
+<ul>
+  <li>vc4: Don't leak the GPU fd for renderonly usage.</li>
+  <li>vc4: Enable NEON asm on meson cross-builds.</li>
+</ul>
+
+<p>Eric Engestrom (2):</p>
+<ul>
+  <li>configure: EGL requirements only apply if EGL is built</li>
+  <li>meson/vdpau: add missing soversion</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>anv/device: fix maximum number of images supported</li>
+</ul>
+
+<p>Jason Ekstrand (3):</p>
+<ul>
+  <li>anv/nir: Rework arguments to apply_pipeline_layout</li>
+  <li>anv: Only parse pImmutableSamplers if the descriptor has samplers</li>
+  <li>nir/xfb: Fix offset accounting for dvec3/4</li>
+</ul>
+
+<p>Karol Herbst (2):</p>
+<ul>
+  <li>nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions</li>
+  <li>glsl/lower_output_reads: set invariant and precise flags on temporaries</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>anv: fix invalid binding table index computation</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>radeonsi: also apply the GS hang workaround to draws without tessellation</li>
+  <li>radeonsi: fix a u_blitter crash after a shader with FBFETCH</li>
+  <li>radeonsi: fix rendering to tiny viewports where the viewport center is &gt; 8K</li>
+  <li>st/mesa: purge framebuffers when unbinding a context</li>
+</ul>
+
+<p>Niklas Haas (1):</p>
+<ul>
+  <li>radv: correctly use vulkan 1.0 by default</li>
+</ul>
+
+<p>Pierre Moreau (1):</p>
+<ul>
+  <li>meson: Fix with_gallium_icd to with_opencl_icd</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+  <li>loader: fix the no-modifiers case</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+  <li>radv: clean up setting partial_es_wave for distributed tess on VI</li>
+</ul>
+
+<p>Timothy Arceri (5):</p>
+<ul>
+  <li>ac/nir_to_llvm: fix interpolateAt* for arrays</li>
+  <li>ac/nir_to_llvm: fix clamp shadow reference for more hardware</li>
+  <li>radv/ac: fix some fp16 handling</li>
+  <li>glsl: use remap location when serialising uniform program resource data</li>
+  <li>glsl: Copy function out to temp if we don't directly ref a variable</li>
+</ul>
+
+<p>Tomeu Vizoso (1):</p>
+<ul>
+  <li>etnaviv: Consolidate buffer references from framebuffers</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+  <li>meson: Fix typo.</li>
+</ul>
+
+
+
+</div>
+</body>
+</html>
+

docs/relnotes/18.3.4.html

@@ -0,0 +1,180 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.3.4 Release Notes / February 18, 2019</h1>
+
+<p>
+Mesa 18.3.4 is a bug fix release which fixes bugs found since the 18.3.3 release.
+</p>
+<p>
+Mesa 18.3.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+e22e6fe4c3aca80fe872a0a7285b6c5523e0cfc0bfb57ffcc3b3d66d292593e4  mesa-18.3.4.tar.gz
+32314da4365d37f80d84f599bd9625b00161c273c39600ba63b45002d500bb07  mesa-18.3.4.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109107">Bug 109107</a> - gallium/st/va: change va max_profiles when using Radeon VCN Hardware</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109401">Bug 109401</a> - [DXVK] Project Cars rendering problems</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109543">Bug 109543</a> - After upgrade mesa to 19.0.0~rc1 all vulkan based application stop working [&quot;vulkan-cube&quot; received SIGSEGV in radv_pipeline_init_blend_state at ../src/amd/vulkan/radv_pipeline.c:699]</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109603">Bug 109603</a> - nir_instr_as_deref: Assertion `parent &amp;&amp; parent-&gt;type == nir_instr_type_deref' failed.</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Bart Oldeman (1):</p>
+<ul>
+  <li>gallium-xlib: query MIT-SHM before using it.</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (2):</p>
+<ul>
+  <li>radv: Only look at pImmutableSamples if the descriptor has a sampler.</li>
+  <li>amd/common: Use correct writemask for shared memory stores.</li>
+</ul>
+
+<p>Dylan Baker (2):</p>
+<ul>
+  <li>get-pick-list: Add --pretty=medium to the arguments for Cc patches</li>
+  <li>meson: Add dependency on genxml to anvil</li>
+</ul>
+
+<p>Emil Velikov (5):</p>
+<ul>
+  <li>docs: add sha256 checksums for 18.3.3</li>
+  <li>cherry-ignore: nv50,nvc0: add explicit settings for recent caps</li>
+  <li>cherry-ignore: add more 19.0 only nominations from Ilia</li>
+  <li>cherry-ignore: radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8</li>
+  <li>Update version to 18.3.4</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>vc4: Fix copy-and-paste fail in backport of NEON asm fixes.</li>
+</ul>
+
+<p>Eric Engestrom (2):</p>
+<ul>
+  <li>xvmc: fix string comparison</li>
+  <li>xvmc: fix string comparison</li>
+</ul>
+
+<p>Ernestas Kulik (2):</p>
+<ul>
+  <li>vc4: Fix leak in HW queries error path</li>
+  <li>v3d: Fix leak in resource setup error path</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+  <li>nvc0: we have 16k-sized framebuffers, fix default scissors</li>
+</ul>
+
+<p>Jason Ekstrand (3):</p>
+<ul>
+  <li>intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()</li>
+  <li>intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode</li>
+  <li>nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+  <li>anv/cmd_buffer: check for NULL framebuffer</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048</li>
+</ul>
+
+<p>Kristian H. Kristensen (1):</p>
+<ul>
+  <li>freedreno/a6xx: Emit blitter dst with OUT_RELOCW</li>
+</ul>
+
+<p>Leo Liu (2):</p>
+<ul>
+  <li>st/va: fix the incorrect max profiles report</li>
+  <li>st/va/vp9: set max reference as default of VP9 reference number</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>meson: drop the xcb-xrandr version requirement</li>
+  <li>gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
+  <li>radeonsi: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
+  <li>winsys/amdgpu: don't drop manually added fence dependencies</li>
+</ul>
+
+<p>Mario Kleiner (2):</p>
+<ul>
+  <li>egl/wayland: Allow client-&gt;server format conversion for PRIME offload. (v2)</li>
+  <li>egl/wayland-drm: Only announce formats via wl_drm which the driver supports.</li>
+</ul>
+
+<p>Oscar Blumberg (1):</p>
+<ul>
+  <li>radeonsi: Fix guardband computation for large render targets</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+  <li>freedreno: stop frob'ing pipe_resource::nr_samples</li>
+</ul>
+
+<p>Rodrigo Vivi (1):</p>
+<ul>
+  <li>intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.</li>
+</ul>
+
+<p>Samuel Pitoiset (2):</p>
+<ul>
+  <li>radv: fix compiler issues with GCC 9</li>
+  <li>radv: always export gl_SampleMask when the fragment shader uses it</li>
+</ul>
+
+
+
+</div>
+</body>
+</html>

docs/relnotes/18.3.5.html

@@ -0,0 +1,270 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.3.5 Release Notes / March 18, 2019</h1>
+
+<p>
+Mesa 18.3.5 is a bug fix release which fixes bugs found since the 18.3.4 release.
+</p>
+<p>
+Mesa 18.3.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104297">Bug 104297</a> - [i965] Downward causes GPU hangs and misrendering on Haswell</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104602">Bug 104602</a> - [apitrace] Graphical artifacts in Civilization VI on RX Vega</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107052">Bug 107052</a> - [Regression][bisected]. Crookz - The Big Heist Demo can't be launched despite the &quot;true&quot; flag in &quot;drirc&quot;</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107563">Bug 107563</a> - [RADV] Broken rendering in Unity demos</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108457">Bug 108457</a> - [OpenGL CTS] KHR-GL46.tessellation_shader.single.xfb_captures_data_from_correct_stage fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108999">Bug 108999</a> - Calculating the scissors fields when the y is flipped (0 on top) can generate negative numbers that will cause assertion failure later on.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109328">Bug 109328</a> - [BSW BXT GLK] dEQP-VK.subgroups.arithmetic.subgroup regressions</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109443">Bug 109443</a> - Build failure with MSVC when using Scons &gt;= 3.0.2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109451">Bug 109451</a> - [IVB,SNB] LINE_STRIPs following a TRIANGLE_FAN fail to use primitive restart</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109594">Bug 109594</a> - totem assert failure: totem: src/intel/genxml/gen9_pack.h:72: __gen_uint: La declaración `v &lt;= max' no se cumple.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109597">Bug 109597</a> - wreckfest issues with transparent objects &amp; skybox</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109601">Bug 109601</a> - [Regression] RuneLite GPU rendering broken on 18.3.x</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109698">Bug 109698</a> - dri.pc contents invalid when built with meson</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109735">Bug 109735</a> - [Regression] broken font with mesa_vulkan_overlay</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alok Hota (1):</p>
+<ul>
+  <li>swr/rast: bypass size limit for non-sampled textures</li>
+</ul>
+
+<p>Andrii Simiklit (1):</p>
+<ul>
+  <li>i965: re-emit index buffer state on a reset option change.</li>
+</ul>
+
+<p>Axel Davy (2):</p>
+<ul>
+  <li>st/nine: Ignore window size if error</li>
+  <li>st/nine: Ignore multisample quality level if no ms</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (4):</p>
+<ul>
+  <li>radv: Sync ETC2 whitelisted devices.</li>
+  <li>radv: Fix float16 interpolation set up.</li>
+  <li>radv: Allow interpolation on non-float types.</li>
+  <li>radv: Interpolate less aggressively.</li>
+</ul>
+
+<p>Carlos Garnacho (1):</p>
+<ul>
+  <li>wayland/egl: Ensure EGL surface is resized on DRI update_buffers()</li>
+</ul>
+
+<p>Danylo Piliaiev (1):</p>
+<ul>
+  <li>glsl/linker: Fix unmatched TCS outputs being reduced to local variable</li>
+</ul>
+
+<p>David Shao (1):</p>
+<ul>
+  <li>meson: ensure that xmlpool_options.h is generated for gallium targets that need it</li>
+</ul>
+
+<p>Eleni Maria Stea (1):</p>
+<ul>
+  <li>i965: fixed clamping in set_scissor_bits when the y is flipped</li>
+</ul>
+
+<p>Emil Velikov (7):</p>
+<ul>
+  <li>docs: add sha256 checksums for 18.3.4</li>
+  <li>meson: egl: correctly manage loader/xmlconfig</li>
+  <li>cherry-ignore: add 19.0 only anv/push buffer nominations</li>
+  <li>cherry-ignore: add gitlab-ci fixup commit</li>
+  <li>cherry-ignore: ignore glsl_types memory cleanup patch</li>
+  <li>cherry-ignore: add explicit 19.0 performance optimisations</li>
+  <li>Update version to 18.3.5</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+  <li>egl: fix libdrm-less builds</li>
+</ul>
+
+<p>Francisco Jerez (1):</p>
+<ul>
+  <li>intel/fs: Implement extended strides greater than 4 for IR source regions.</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>intel/fs: nir_op_extract_i8 extracts a byte, not a word</li>
+  <li>intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+  <li>glsl: fix recording of variables for XFB in TCS shaders</li>
+</ul>
+
+<p>Jason Ekstrand (10):</p>
+<ul>
+  <li>intel/fs: Bail in optimize_extract_to_float if we have modifiers</li>
+  <li>compiler/types: Add a contains_64bit helper</li>
+  <li>nir/xfb: Properly align 64-bit values</li>
+  <li>nir/xfb: Work in terms of components rather than slots</li>
+  <li>nir/xfb: Handle compact arrays in gather_xfb_info</li>
+  <li>anv: Count surfaces for non-YCbCr images in GetDescriptorSetLayoutSupport</li>
+  <li>spirv: OpImageQueryLod requires a sampler</li>
+  <li>spirv: Pull offset/stride from the pointer for OpArrayLength</li>
+  <li>glsl/list: Add a list variant of insert_after</li>
+  <li>glsl/lower_vector_derefs: Don't use a temporary for TCS outputs</li>
+</ul>
+
+<p>Jose Maria Casanova Crespo (1):</p>
+<ul>
+  <li>glsl: TCS outputs can not be transform feedback candidates on GLES</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>scons: Workaround failures with MSVC when using SCons 3.0.[2-4].</li>
+</ul>
+
+<p>Juan A. Suarez Romero (3):</p>
+<ul>
+  <li>genxml: add missing field values for 3DSTATE_SF</li>
+  <li>anv: advertise 8 subpixel precision bits</li>
+  <li>anv: destroy descriptor sets when pool gets reset</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>intel/fs: Fix opt_peephole_csel to not throw away saturates.</li>
+</ul>
+
+<p>Kevin Strasser (1):</p>
+<ul>
+  <li>egl/dri: Avoid out of bounds array access</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>intel: fix urb size for CFL GT1</li>
+</ul>
+
+<p>Marek Olšák (5):</p>
+<ul>
+  <li>radeonsi: add driconf option radeonsi_enable_nir</li>
+  <li>radeonsi: always enable NIR for Civilization 6 to fix corruption</li>
+  <li>driconf: add Civ6Sub executable for Civilization 6</li>
+  <li>tgsi: don't set tgsi_info::uses_bindless_images for constbufs and hw atomics</li>
+  <li>radeonsi: compile clear and copy buffer compute shaders on demand</li>
+</ul>
+
+<p>Mauro Rossi (2):</p>
+<ul>
+  <li>android: anv: fix generated files depedencies (v2)</li>
+  <li>android: anv: fix libexpat shared dependency</li>
+</ul>
+
+<p>Ray Zhang (1):</p>
+<ul>
+  <li>glx: fix shared memory leak in X11</li>
+</ul>
+
+<p>Rhys Perry (2):</p>
+<ul>
+  <li>radv: bitcast 16-bit outputs to integers</li>
+  <li>radv: ensure export arguments are always float</li>
+</ul>
+
+<p>Samuel Pitoiset (8):</p>
+<ul>
+  <li>radv: write the alpha channel of MRT0 when alpha coverage is enabled</li>
+  <li>radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled</li>
+  <li>radv: fix clearing attachments in secondary command buffers</li>
+  <li>radv: fix out-of-bounds access when copying descriptors BO list</li>
+  <li>radv: don't copy buffer descriptors list for samplers</li>
+  <li>radv: properly align the fence and EOP bug VA on GFX9</li>
+  <li>radv: fix pointSizeRange limits</li>
+  <li>radv: always initialize HTILE when the src layout is UNDEFINED</li>
+</ul>
+
+<p>Sergii Romantsov (2):</p>
+<ul>
+  <li>dri: meson: do not prefix user provided dri-drivers-path</li>
+  <li>d3d: meson: do not prefix user provided d3d-drivers-path</li>
+</ul>
+
+<p>Tapani Pälli (3):</p>
+<ul>
+  <li>nir: initialize value in copy_prop_vars_block</li>
+  <li>anv: retain the is_array state in create_plane_tex_instr_implicit</li>
+  <li>anv: destroy descriptor sets when pool gets destroyed</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>glsl: fix shader cache for packed param list</li>
+</ul>
+
+<p>Yevhenii Kolesnikov (1):</p>
+<ul>
+  <li>i965: Fix allow_higher_compat_version workaround limited by OpenGL 3.0</li>
+</ul>
+
+<p>pal1000 (1):</p>
+<ul>
+  <li>scons: Compatibility with Scons development version string</li>
+</ul>
+
+
+</div>
+</body>
+</html>

docs/specs/EGL_MESA_query_driver.txt

@@ -1,95 +0,0 @@
-Name
-
-    MESA_query_driver
-
-Name Strings
-
-    EGL_MESA_query_driver
-
-Contact
-
-    Rob Clark      <robdclark 'at' gmail.com>
-    Nicolai Hähnle <Nicolai.Haehnle 'at' amd.com>
-
-Contibutors
-
-    Veluri Mithun <velurimithun38 'at' gmail.com>
-
-Status
-
-    Complete
-
-Version
-
-    Version 3, 2019-01-24
-
-Number
-
-    EGL Extension 131
-
-Dependencies
-
-    EGL 1.0 is required.
-
-Overview
-
-    When an application has to query the name of a driver and for
-    obtaining driver's option list (UTF-8 encoded XML) of a driver
-    the below functions are useful.
-
-    XML file formally describes all available options and also
-    includes verbal descriptions in multiple languages. Its main purpose
-    is to be automatically processed by configuration GUIs.
-    The XML shall respect the following DTD:
-
-    <!ELEMENT driinfo      (section*)>
-    <!ELEMENT section      (description+, option+)>
-    <!ELEMENT description  (enum*)>
-    <!ATTLIST description  lang CDATA #REQUIRED
-                           text CDATA #REQUIRED>
-    <!ELEMENT option       (description+)>
-    <!ATTLIST option       name CDATA #REQUIRED
-                           type (bool|enum|int|float) #REQUIRED
-                           default CDATA #REQUIRED
-                           valid CDATA #IMPLIED>
-    <!ELEMENT enum         EMPTY>
-    <!ATTLIST enum         value CDATA #REQUIRED
-                           text CDATA #REQUIRED>
-
-New Procedures and Functions
-
-    char* eglGetDisplayDriverConfig(EGLDisplay dpy);
-    const char* eglGetDisplayDriverName(EGLDisplay dpy);
-
-Description
-
-    By passing EGLDisplay as parameter to `eglGetDisplayDriverName` one can retrieve
-    driverName. Similarly passing EGLDisplay to `eglGetDisplayDriverConfig` we can retrieve
-    driverConfig options of the driver in XML format.
-
-    The string returned by `eglGetDisplayDriverConfig` is heap-allocated and caller
-    is responsible for freeing it.
-
-    EGL_BAD_DISPLAY is generated if `disp` is not an EGL display connection.
-
-    EGL_NOT_INITIALIZED is generated if `disp` has not been initialized.
-
-    If the implementation does not have enough resources to allocate the XML then an
-    EGL_BAD_ALLOC error is generated.
-
-New Tokens
-
-    No new tokens
-
-Issues
-
-    None
-
-
-Revision History
-
-    Version 1, 2018-11-05 - First draft (Veluri Mithun)
-    Version 2, 2019-01-23 - Final version (Veluri Mithun)
-    Version 3, 2019-01-24 - Mark as complete, add Khronos extension
-                            number, fix parameter name in prototypes,
-                            write revision history (Eric Engestrom)

docs/specs/MESA_query_renderer.spec

@@ -20,11 +20,11 @@ Status
 
 Version
 
-    Version 9, 09 November 2018
+    Version 8, 14-February-2014
 
 Number
 
-    OpenGL Extension #446
+    TBD.
 
 Dependencies
 
@@ -32,6 +32,9 @@ Dependencies
 
     GLX_ARB_create_context and GLX_ARB_create_context_profile are required.
 
+    This extension interacts with GLX_EXT_create_context_es2_profile and
+    GLX_EXT_create_context_es_profile.
+
 Overview
 
     In many situations, applications want to detect characteristics of a
@@ -92,13 +95,18 @@ New Tokens
         GLX_RENDERER_VENDOR_ID_MESA
         GLX_RENDERER_DEVICE_ID_MESA
 
+    Accepted as an attribute name in <*attrib_list> in
+    glXCreateContextAttribsARB:
+
+        GLX_RENDERER_ID_MESA                             0x818E
+
 Additions to the OpenGL / WGL Specifications
 
     None. This specification is written for GLX.
 
 Additions to the GLX 1.4 Specification
 
-    [Add to Section 3.3.2 "GLX Versioning" of the GLX Specification]
+    [Add the following to Section X.Y.Z of the GLX Specification]
 
     To obtain information about the available renderers for a particular
     display and screen,
@@ -198,6 +206,29 @@ Additions to the GLX 1.4 Specification
     format as the string that would be returned by glGetString of GL_RENDERER.
     It may, however, have a different value.
 
+
+    [Add to section section 3.3.7 "Rendering Contexts"]
+
+    The attribute name GLX_RENDERER_ID_MESA specified the index of the render
+    against which the context should be created.  The default value of
+    GLX_RENDERER_ID_MESA is 0.
+
+
+    [Add to list of errors for glXCreateContextAttribsARB in section section
+    3.3.7 "Rendering Contexts"]
+
+      * If the value of GLX_RENDERER_ID_MESA specifies a non-existent
+        renderer, BadMatch is generated.
+
+Dependencies on GLX_EXT_create_context_es_profile and
+GLX_EXT_create_context_es2_profile
+
+    If neither extension is supported, remove all mention of
+    GLX_RENDERER_OPENGL_ES2_PROFILE_VERSION_MESA from the spec.
+
+    If GLX_EXT_create_context_es_profile is not supported, remove all mention of
+    GLX_RENDERER_OPENGL_ES_PROFILE_VERSION_MESA from the spec.
+
 Issues
 
     1) How should the difference between on-card and GART memory be exposed?
@@ -377,9 +408,3 @@ Revision History
                             read GLX_RENDERER_ID_MESA. The VENDOR/DEVICE_ID
                             example given in issue #17 should be 0x5143 and
                             0xFFFFFFFF respectively.
-
-    Version 9, 2018/11/09 - Remove GLX_RENDERER_ID_MESA, which has never been
-                            implemented. Remove the unnecessary interactions
-                            with the GLX GLES profile extensions. Note the
-                            official GL extension number. Specify the section
-                            of the GLX spec to modify.

docs/submittingpatches.html

@@ -21,7 +21,7 @@
 <li><a href="#guidelines">Basic guidelines</a>
 <li><a href="#formatting">Patch formatting</a>
 <li><a href="#testing">Testing Patches</a>
-<li><a href="#submit">Submitting Patches</a>
+<li><a href="#mailing">Mailing Patches</a>
 <li><a href="#reviewing">Reviewing Patches</a>
 <li><a href="#nominations">Nominating a commit for a stable branch</a>
 <li><a href="#criteria">Criteria for accepting patches to the stable branch</a>
@@ -42,10 +42,8 @@ components.
 <code>git bisect</code>.)
 <li>Patches should be properly <a href="#formatting">formatted</a>.
 <li>Patches should be sufficiently <a href="#testing">tested</a> before submitting.
-<li>Patches should be <a href="#submit">submitted</a>
-to <a href="#mailing">mesa-dev</a> or with
-a <a href="#merge-request">merge request</a>
-for <a href="#reviewing">review</a>.
+<li>Patches should be submitted to <a href="#mailing">mesa-dev</a>
+for <a href="#reviewing">review</a> using <code>git send-email</code>.
 
 </ul>
 
@@ -158,29 +156,18 @@ As mentioned at the begining, patches should be bisectable.
 A good way to test this is to make use of the `git rebase` command,
 to run your tests on each commit. Assuming your branch is based off
 <code>origin/master</code>, you can run:
-</p>
 <pre>
 $ git rebase --interactive --exec "make check" origin/master
 </pre>
-<p>
 replacing <code>"make check"</code> with whatever other test you want to
 run.
 </p>
 
 
-<h2 id="submit">Submitting Patches</h2>
+<h2 id="mailing">Mailing Patches</h2>
 
 <p>
-Patches may be submitted to the Mesa project by
-<a href="#mailing">email</a> or with a
-GitLab <a href="#merge-request">merge request</a>. To prevent
-duplicate code review, only use one method to submit your changes.
-</p>
-
-<h3 id="mailing">Mailing Patches</h3>
-
-<p>
-Patches may be sent to the mesa-dev mailing list for review:
+Patches should be sent to the mesa-dev mailing list for review:
 <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev">
 mesa-dev@lists.freedesktop.org</a>.
 When submitting a patch make sure to use
@@ -214,65 +201,8 @@ disabled before sending your patches. (Note that you may need to contact
 your email administrator for this.)
 </p>
 
-<h3 id="merge-request">GitLab Merge Requests</h3>
-
-<p>
-  <a href="https://gitlab.freedesktop.org/mesa/mesa">GitLab</a> Merge
-  Requests (MR) can also be used to submit patches for Mesa.
-</p>
-
-<p>
-  If the MR may have interest for most of the Mesa community, you can
-  send an email to the mesa-dev email list including a link to the MR.
-  Don't send the patch to mesa-dev, just the MR link.
-</p>
-<p>
-  Add labels to your MR to help reviewers find it. For example:
-  <ul>
-    <li>Mesa changes affecting all drivers: mesa
-    <li>Hardware vendor specific code: amd, intel, nvidia, ...
-    <li>Driver specific code: anvil, freedreno, i965, iris, radeonsi,
-      radv, vc4, ...
-    <li>Other tag examples: gallium, util
-  </ul>
-</p>
-<p>
-  If you revise your patches based on code review and push an update
-  to your branch, you should maintain a <strong>clean</strong> history
-  in your patches. There should not be "fixup" patches in the history.
-  The series should be buildable and functional after every commit
-  whenever you push the branch.
-</p>
-<p>
-  It is your responsibility to keep the MR alive and making progress,
-  as there are no guarantees that a Mesa dev will independently take
-  interest in it.
-</p>
-<p>
-  Some other notes:
-  <ul>
-    <li>Make changes and update your branch based on feedback
-    <li>Old, stale MR may be closed, but you can reopen it if you
-      still want to pursue the changes
-    <li>You should periodically check to see if your MR needs to be
-      rebased
-    <li>Make sure your MR is closed if your patches get pushed outside
-      of GitLab
-    <li>Please send MRs from a personal fork rather than from the main
-      Mesa repository, as it clutters it unnecessarily.
-  </ul>
-</p>
-
 <h2 id="reviewing">Reviewing Patches</h2>
 
-<p>
-  To participate in code review, you should monitor the
-  <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev">
-  mesa-dev</a> email list and the GitLab
-  Mesa <a href="https://gitlab.freedesktop.org/mesa/mesa/merge_requests">Merge
-  Requests</a> page.
-</p>
-
 <p>
 When you've reviewed a patch on the mailing list, please be unambiguous
 about your review.  That is, state either
@@ -299,29 +229,6 @@ which tells the patch author that the patch can be committed, as long
 as the issues are resolved first.
 </p>
 
-<p>
-These Reviewed-by, Acked-by, and Tested-by tags should also be amended
-into commits in a MR before it is merged.
-</p>
-
-<p>
-When providing a Reviewed-by, Acked-by, or Tested-by tag in a gitlab MR,
-enclose the tag in backticks:
-</p>
-<pre>
-  `Reviewed-by: Joe Hacker &lt;jhacker@example.com&gt;`</pre>
-<p>
-This is the markdown format for literal, and will prevent gitlab from hiding
-the &lt; and &gt; symbols.
-</p>
-
-<p>
-Review by non-experts is encouraged.  Understanding how someone else
-goes about solving a problem is a great way to learn your way around
-the project.  The submitter is expected to evaluate whether they have
-an appropriate amount of review feedback from people who also
-understand the code before merging their patches.
-</p>
 
 <h2 id="nominations">Nominating a commit for a stable branch</h2>
 

include/EGL/egl.h

@@ -28,17 +28,17 @@ extern "C" {
 ** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
 */
 /*
-** This header is generated from the Khronos EGL XML API Registry.
-** The current version of the Registry, generator scripts
+** This header is generated from the Khronos OpenGL / OpenGL ES XML
+** API Registry. The current version of the Registry, generator scripts
 ** used to make the header, and the header can be found at
 **   http://www.khronos.org/registry/egl
 **
-** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
+** Khronos $Git commit SHA1: a732b061e7 $ on $Git commit date: 2017-06-17 23:27:53 +0100 $
 */
 
 #include <EGL/eglplatform.h>
 
-/* Generated on date 20190124 */
+/* Generated on date 20170627 */
 
 /* Generated C header for:
  * API: egl

include/EGL/eglext.h

@@ -28,17 +28,17 @@ extern "C" {
 ** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
 */
 /*
-** This header is generated from the Khronos EGL XML API Registry.
-** The current version of the Registry, generator scripts
+** This header is generated from the Khronos OpenGL / OpenGL ES XML
+** API Registry. The current version of the Registry, generator scripts
 ** used to make the header, and the header can be found at
 **   http://www.khronos.org/registry/egl
 **
-** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
+** Khronos $Git commit SHA1: bae3518c48 $ on $Git commit date: 2018-05-17 10:56:57 -0700 $
 */
 
 #include <EGL/eglplatform.h>
 
-#define EGL_EGLEXT_VERSION 20190124
+#define EGL_EGLEXT_VERSION 20180517
 
 /* Generated C header for:
  * API: egl
@@ -681,7 +681,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
 #ifndef EGL_EXT_device_drm
 #define EGL_EXT_device_drm 1
 #define EGL_DRM_DEVICE_FILE_EXT           0x3233
-#define EGL_DRM_MASTER_FD_EXT             0x333C
 #endif /* EGL_EXT_device_drm */
 
 #ifndef EGL_EXT_device_enumeration
@@ -717,11 +716,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
 #define EGL_GL_COLORSPACE_DISPLAY_P3_LINEAR_EXT 0x3362
 #endif /* EGL_EXT_gl_colorspace_display_p3_linear */
 
-#ifndef EGL_EXT_gl_colorspace_display_p3_passthrough
-#define EGL_EXT_gl_colorspace_display_p3_passthrough 1
-#define EGL_GL_COLORSPACE_DISPLAY_P3_PASSTHROUGH_EXT 0x3490
-#endif /* EGL_EXT_gl_colorspace_display_p3_passthrough */
-
 #ifndef EGL_EXT_gl_colorspace_scrgb
 #define EGL_EXT_gl_colorspace_scrgb 1
 #define EGL_GL_COLORSPACE_SCRGB_EXT       0x3351
@@ -1031,16 +1025,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglExportDMABUFImageMESA (EGLDisplay dpy, EGLImage
 #define EGL_PLATFORM_SURFACELESS_MESA     0x31DD
 #endif /* EGL_MESA_platform_surfaceless */
 
-#ifndef EGL_MESA_query_driver
-#define EGL_MESA_query_driver 1
-typedef char *(EGLAPIENTRYP PFNEGLGETDISPLAYDRIVERCONFIGPROC) (EGLDisplay dpy);
-typedef const char *(EGLAPIENTRYP PFNEGLGETDISPLAYDRIVERNAMEPROC) (EGLDisplay dpy);
-#ifdef EGL_EGLEXT_PROTOTYPES
-EGLAPI char *EGLAPIENTRY eglGetDisplayDriverConfig (EGLDisplay dpy);
-EGLAPI const char *EGLAPIENTRY eglGetDisplayDriverName (EGLDisplay dpy);
-#endif
-#endif /* EGL_MESA_query_driver */
-
 #ifndef EGL_NOK_swap_region
 #define EGL_NOK_swap_region 1
 typedef EGLBoolean (EGLAPIENTRYP PFNEGLSWAPBUFFERSREGIONNOKPROC) (EGLDisplay dpy, EGLSurface surface, EGLint numRects, const EGLint *rects);

include/GL/internal/dri_interface.h

@@ -1344,7 +1344,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_NV16		0x3631564e
 #define __DRI_IMAGE_FOURCC_YUYV		0x56595559
 #define __DRI_IMAGE_FOURCC_UYVY		0x59565955
-#define __DRI_IMAGE_FOURCC_AYUV		0x56555941
 
 #define __DRI_IMAGE_FOURCC_YVU410	0x39555659
 #define __DRI_IMAGE_FOURCC_YVU411	0x31315659
@@ -1371,7 +1370,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_COMPONENTS_Y_UV	0x3004
 #define __DRI_IMAGE_COMPONENTS_Y_XUXV	0x3005
 #define __DRI_IMAGE_COMPONENTS_Y_UXVX	0x3008
-#define __DRI_IMAGE_COMPONENTS_AYUV	0x3009
 #define __DRI_IMAGE_COMPONENTS_R	0x3006
 #define __DRI_IMAGE_COMPONENTS_RG	0x3007
 

include/drm-uapi/drm_fourcc.h

@@ -298,19 +298,6 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
 
-/*
- * Qualcomm Compressed Format
- *
- * Refers to a compressed variant of the base format that is compressed.
- * Implementation may be platform and base-format specific.
- *
- * Each macrotile consists of m x n (mostly 4 x 4) tiles.
- * Pixel data pitch/stride is aligned with macrotile width.
- * Pixel data height is aligned with macrotile height.
- * Entire pixel data buffer is aligned with 4k(bytes).
- */
-#define DRM_FORMAT_MOD_QCOM_COMPRESSED  fourcc_mod_code(QCOM, 1)
-
 /* Vivante framebuffer modifiers */
 
 /*

include/drm-uapi/v3d_drm.h

@@ -36,7 +36,6 @@ extern "C" {
 #define DRM_V3D_MMAP_BO                           0x03
 #define DRM_V3D_GET_PARAM                         0x04
 #define DRM_V3D_GET_BO_OFFSET                     0x05
-#define DRM_V3D_SUBMIT_TFU                        0x06
 
 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -44,7 +43,6 @@ extern "C" {
 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
-#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
 
 /**
  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -60,15 +58,10 @@ struct drm_v3d_submit_cl {
 	 * coordinate shader to determine where primitives land on the screen,
 	 * then writes out the state updates and draw calls necessary per tile
 	 * to the tile allocation BO.
-	 *
-	 * This BCL will block on any previous BCL submitted on the
-	 * same FD, but not on any RCL or BCLs submitted by other
-	 * clients -- that is left up to the submitter to control
-	 * using in_sync_bcl if necessary.
 	 */
 	__u32 bcl_start;
 
-	/** End address of the BCL (first byte after the BCL) */
+	 /** End address of the BCL (first byte after the BCL) */
 	__u32 bcl_end;
 
 	/* Offset of the render command list.
@@ -76,15 +69,10 @@ struct drm_v3d_submit_cl {
 	 * This is the second set of commands executed, which will either
 	 * execute the tiles that have been set up by the BCL, or a fixed set
 	 * of tiles (in the case of RCL-only blits).
-	 *
-	 * This RCL will block on this submit's BCL, and any previous
-	 * RCL submitted on the same FD, but not on any RCL or BCLs
-	 * submitted by other clients -- that is left up to the
-	 * submitter to control using in_sync_rcl if necessary.
 	 */
 	__u32 rcl_start;
 
-	/** End address of the RCL (first byte after the RCL) */
+	 /** End address of the RCL (first byte after the RCL) */
 	__u32 rcl_end;
 
 	/** An optional sync object to wait on before starting the BCL. */
@@ -181,7 +169,6 @@ enum drm_v3d_param {
 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
-	DRM_V3D_PARAM_SUPPORTS_TFU,
 };
 
 struct drm_v3d_get_param {
@@ -200,28 +187,6 @@ struct drm_v3d_get_bo_offset {
 	__u32 offset;
 };
 
-struct drm_v3d_submit_tfu {
-	__u32 icfg;
-	__u32 iia;
-	__u32 iis;
-	__u32 ica;
-	__u32 iua;
-	__u32 ioa;
-	__u32 ios;
-	__u32 coef[4];
-	/* First handle is the output BO, following are other inputs.
-	 * 0 for unused.
-	 */
-	__u32 bo_handles[4];
-	/* sync object to block on before running the TFU job.  Each TFU
-	 * job will execute in the order submitted to its FD.  Synchronization
-	 * against rendering jobs requires using sync objects.
-	 */
-	__u32 in_sync;
-	/* Sync object to signal when the TFU job is done. */
-	__u32 out_sync;
-};
-
 #if defined(__cplusplus)
 }
 #endif

include/vulkan/vulkan.h

@@ -2,7 +2,7 @@
 #define VULKAN_H_ 1
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.
@@ -39,6 +39,12 @@
 #endif
 
 
+#ifdef VK_USE_PLATFORM_MIR_KHR
+#include <mir_toolkit/client_types.h>
+#include "vulkan_mir.h"
+#endif
+
+
 #ifdef VK_USE_PLATFORM_VI_NN
 #include "vulkan_vi.h"
 #endif

include/vulkan/vulkan_android.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_fuchsia.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_ios.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_macos.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_mir.h

@@ -0,0 +1,65 @@
+#ifndef VULKAN_MIR_H_
+#define VULKAN_MIR_H_ 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** Copyright (c) 2015-2018 The Khronos Group Inc.
+**
+** Licensed under the Apache License, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+**
+**     http://www.apache.org/licenses/LICENSE-2.0
+**
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+*/
+
+/*
+** This header is generated from the Khronos Vulkan XML API Registry.
+**
+*/
+
+
+#define VK_KHR_mir_surface 1
+#define VK_KHR_MIR_SURFACE_SPEC_VERSION   4
+#define VK_KHR_MIR_SURFACE_EXTENSION_NAME "VK_KHR_mir_surface"
+
+typedef VkFlags VkMirSurfaceCreateFlagsKHR;
+
+typedef struct VkMirSurfaceCreateInfoKHR {
+    VkStructureType               sType;
+    const void*                   pNext;
+    VkMirSurfaceCreateFlagsKHR    flags;
+    MirConnection*                connection;
+    MirSurface*                   mirSurface;
+} VkMirSurfaceCreateInfoKHR;
+
+
+typedef VkResult (VKAPI_PTR *PFN_vkCreateMirSurfaceKHR)(VkInstance instance, const VkMirSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
+typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceMirPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, MirConnection* connection);
+
+#ifndef VK_NO_PROTOTYPES
+VKAPI_ATTR VkResult VKAPI_CALL vkCreateMirSurfaceKHR(
+    VkInstance                                  instance,
+    const VkMirSurfaceCreateInfoKHR*            pCreateInfo,
+    const VkAllocationCallbacks*                pAllocator,
+    VkSurfaceKHR*                               pSurface);
+
+VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceMirPresentationSupportKHR(
+    VkPhysicalDevice                            physicalDevice,
+    uint32_t                                    queueFamilyIndex,
+    MirConnection*                              connection);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

include/vulkan/vulkan_vi.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_wayland.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_win32.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_xcb.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_xlib.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

include/vulkan/vulkan_xlib_xrandr.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2019 The Khronos Group Inc.
+** Copyright (c) 2015-2018 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.

meson.build

@@ -34,6 +34,8 @@ cpp = meson.get_compiler('cpp')
 
 null_dep = dependency('', required : false)
 
+system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
+
 # Arguments for the preprocessor, put these in a separate array from the C and
 # C++ (cpp in meson terminology) arguments since they need to be added to the
 # default arguments for both C and C++.
@@ -41,7 +43,8 @@ pre_args = [
   '-D__STDC_CONSTANT_MACROS',
   '-D__STDC_FORMAT_MACROS',
   '-D__STDC_LIMIT_MACROS',
-  '-DPACKAGE_VERSION="@0@"'.format(meson.project_version()),
+  '-DVERSION="@0@"'.format(meson.project_version()),
+  '-DPACKAGE_VERSION=VERSION',
   '-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa"',
 ]
 
@@ -56,7 +59,7 @@ with_osmesa = get_option('osmesa')
 with_swr_arches = get_option('swr-arches')
 with_tools = get_option('tools')
 if with_tools.contains('all')
-  with_tools = ['etnaviv', 'freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
+  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
 endif
 
 dri_drivers_path = get_option('dri-drivers-path')
@@ -131,7 +134,7 @@ if _drivers.contains('auto')
       ]
     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
       _drivers = [
-        'kmsro', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau',
+        'pl111', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'imx', 'nouveau',
         'tegra', 'virgl', 'swrast',
       ]
     else
@@ -145,7 +148,7 @@ if _drivers.contains('auto')
           host_machine.system()))
   endif
 endif
-with_gallium_kmsro = _drivers.contains('kmsro')
+with_gallium_pl111 = _drivers.contains('pl111')
 with_gallium_radeonsi = _drivers.contains('radeonsi')
 with_gallium_r300 = _drivers.contains('r300')
 with_gallium_r600 = _drivers.contains('r600')
@@ -155,6 +158,7 @@ with_gallium_softpipe = _drivers.contains('swrast')
 with_gallium_vc4 = _drivers.contains('vc4')
 with_gallium_v3d = _drivers.contains('v3d')
 with_gallium_etnaviv = _drivers.contains('etnaviv')
+with_gallium_imx = _drivers.contains('imx')
 with_gallium_tegra = _drivers.contains('tegra')
 with_gallium_i915 = _drivers.contains('i915')
 with_gallium_svga = _drivers.contains('svga')
@@ -209,8 +213,11 @@ endif
 if with_dri_i915 and with_gallium_i915
   error('Only one i915 provider can be built')
 endif
-if with_gallium_kmsro and not (with_gallium_vc4 or with_gallium_etnaviv or with_gallium_freedreno)
-  error('kmsro driver requires one or more renderonly drivers (vc4, etnaviv, freedreno)')
+if with_gallium_imx and not with_gallium_etnaviv
+  error('IMX driver requires etnaviv driver')
+endif
+if with_gallium_pl111 and not with_gallium_vc4
+  error('pl111 driver requires vc4 driver')
 endif
 if with_gallium_tegra and not with_gallium_nouveau
   error('tegra driver requires nouveau driver')
@@ -608,7 +615,7 @@ with_gallium_xa = _xa != 'false'
 
 d3d_drivers_path = get_option('d3d-drivers-path')
 if d3d_drivers_path == ''
-  d3d_drivers_path = join_paths(get_option('libdir'), 'd3d')
+  d3d_drivers_path = join_paths(get_option('prefix'), get_option('libdir'), 'd3d')
 endif
 
 with_gallium_st_nine =  get_option('gallium-nine')
@@ -929,7 +936,7 @@ endif
 # case of cross compiling where we can use asm, and that's x86_64 -> x86 when
 # host OS == build OS, since in that case the build machine can run the host's
 # binaries.
-if with_asm and meson.is_cross_build()
+if meson.is_cross_build() 
   if build_machine.system() != host_machine.system()
     # TODO: It may be possible to do this with an exe_wrapper (like wine).
     message('Cross compiling from one OS to another, disabling assembly.')
@@ -1113,7 +1120,7 @@ dep_libdrm_nouveau = null_dep
 dep_libdrm_etnaviv = null_dep
 dep_libdrm_intel = null_dep
 
-_drm_amdgpu_ver = '2.4.97'
+_drm_amdgpu_ver = '2.4.95'
 _drm_radeon_ver = '2.4.71'
 _drm_nouveau_ver = '2.4.66'
 _drm_etnaviv_ver = '2.4.89'
@@ -1188,7 +1195,7 @@ if with_gallium_opencl
 endif
 
 if with_amd_vk or with_gallium_radeonsi
-  _llvm_version = '>= 7.0.0'
+  _llvm_version = '>= 6.0.0'
 elif with_gallium_swr
   _llvm_version = '>= 6.0.0'
 elif with_gallium_opencl or with_gallium_r600
@@ -1365,7 +1372,7 @@ if with_platform_x11
     dep_xfixes = dependency('xfixes')
     dep_xcb_glx = dependency('xcb-glx', version : '>= 1.8.1')
   endif
-  if (with_any_vk or with_glx == 'dri' or with_egl or
+  if (with_any_vk or with_glx == 'dri' or
        (with_gallium_vdpau or with_gallium_xvmc or with_gallium_va or
         with_gallium_omx != 'disabled'))
     dep_xcb = dependency('xcb')

meson_options.txt

@@ -58,8 +58,8 @@ option(
   type : 'array',
   value : ['auto'],
   choices : [
-    '', 'auto', 'kmsro', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
-    'swrast', 'v3d', 'vc4', 'etnaviv', 'tegra', 'i915', 'svga', 'virgl',
+    '', 'auto', 'pl111', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
+    'swrast', 'v3d', 'vc4', 'etnaviv', 'imx', 'tegra', 'i915', 'svga', 'virgl',
     'swr',
   ],
   description : 'List of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
@@ -301,7 +301,7 @@ option(
   'tools',
   type : 'array',
   value : [],
-  choices : ['etnaviv', 'freedreno', 'glsl', 'intel', 'intel-ui', 'nir', 'nouveau', 'xvmc', 'all'],
+  choices : ['freedreno', 'glsl', 'intel', 'intel-ui', 'nir', 'nouveau', 'xvmc', 'all'],
   description : 'List of tools to build. (Note: `intel-ui` selects `intel`)',
 )
 option(

src/Makefile.am

@@ -81,10 +81,6 @@ if HAVE_BROADCOM_DRIVERS
 SUBDIRS += broadcom
 endif
 
-if HAVE_FREEDRENO_DRIVERS
-SUBDIRS += freedreno
-endif
-
 if NEED_OPENGL_COMMON
 SUBDIRS += mesa
 endif

src/amd/Android.addrlib.mk

@@ -33,11 +33,12 @@ LOCAL_SRC_FILES := $(ADDRLIB_FILES)
 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src \
 	$(MESA_TOP)/src/amd/common \
-	$(MESA_TOP)/src/amd/addrlib/inc \
-	$(MESA_TOP)/src/amd/addrlib/src \
-	$(MESA_TOP)/src/amd/addrlib/src/core \
-	$(MESA_TOP)/src/amd/addrlib/src/chip/gfx9 \
-	$(MESA_TOP)/src/amd/addrlib/src/chip/r800
+	$(MESA_TOP)/src/amd/addrlib \
+	$(MESA_TOP)/src/amd/addrlib/core \
+	$(MESA_TOP)/src/amd/addrlib/inc/chip/gfx9 \
+	$(MESA_TOP)/src/amd/addrlib/inc/chip/r800 \
+	$(MESA_TOP)/src/amd/addrlib/gfx9/chip \
+	$(MESA_TOP)/src/amd/addrlib/r800/chip
 
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
 	$(LOCAL_PATH) \

src/amd/Makefile.addrlib.am

@@ -26,11 +26,12 @@ addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
 	-I$(top_srcdir)/src/ \
 	-I$(top_srcdir)/include \
 	-I$(srcdir)/common \
-	-I$(srcdir)/addrlib/inc \
-	-I$(srcdir)/addrlib/src \
-	-I$(srcdir)/addrlib/src/core \
-	-I$(srcdir)/addrlib/src/chip/gfx9 \
-	-I$(srcdir)/addrlib/src/chip/r800
+	-I$(srcdir)/addrlib \
+	-I$(srcdir)/addrlib/core \
+	-I$(srcdir)/addrlib/inc/chip/gfx9 \
+	-I$(srcdir)/addrlib/inc/chip/r800 \
+	-I$(srcdir)/addrlib/gfx9/chip \
+	-I$(srcdir)/addrlib/r800/chip
 
 addrlib_libamdgpu_addrlib_la_CXXFLAGS = \
 	$(VISIBILITY_CXXFLAGS) $(CXX11_CXXFLAGS)

src/amd/Makefile.sources

@@ -5,33 +5,35 @@ COMMON_HEADER_FILES = \
 	common/amd_kernel_code_t.h
 
 ADDRLIB_FILES = \
-	addrlib/inc/addrinterface.h \
-	addrlib/inc/addrtypes.h \
-	addrlib/src/addrinterface.cpp \
-	addrlib/src/amdgpu_asic_addr.h \
-	addrlib/src/core/addrcommon.h \
-	addrlib/src/core/addrelemlib.cpp \
-	addrlib/src/core/addrelemlib.h \
-	addrlib/src/core/addrlib.cpp \
-	addrlib/src/core/addrlib.h \
-	addrlib/src/core/addrlib1.cpp \
-	addrlib/src/core/addrlib1.h \
-	addrlib/src/core/addrlib2.cpp \
-	addrlib/src/core/addrlib2.h \
-	addrlib/src/core/addrobject.cpp \
-	addrlib/src/core/addrobject.h \
-	addrlib/src/core/coord.cpp \
-	addrlib/src/core/coord.h \
-	addrlib/src/gfx9/gfx9addrlib.cpp \
-	addrlib/src/gfx9/gfx9addrlib.h \
-	addrlib/src/chip/gfx9/gfx9_gb_reg.h \
-	addrlib/src/chip/r800/si_gb_reg.h \
-	addrlib/src/r800/ciaddrlib.cpp \
-	addrlib/src/r800/ciaddrlib.h \
-	addrlib/src/r800/egbaddrlib.cpp \
-	addrlib/src/r800/egbaddrlib.h \
-	addrlib/src/r800/siaddrlib.cpp \
-	addrlib/src/r800/siaddrlib.h
+	addrlib/addrinterface.cpp \
+	addrlib/addrinterface.h \
+	addrlib/addrtypes.h \
+	addrlib/amdgpu_asic_addr.h \
+	addrlib/core/addrcommon.h \
+	addrlib/core/addrelemlib.cpp \
+	addrlib/core/addrelemlib.h \
+	addrlib/core/addrlib.cpp \
+	addrlib/core/addrlib.h \
+	addrlib/core/addrlib1.cpp \
+	addrlib/core/addrlib1.h \
+	addrlib/core/addrlib2.cpp \
+	addrlib/core/addrlib2.h \
+	addrlib/core/addrobject.cpp \
+	addrlib/core/addrobject.h \
+	addrlib/gfx9/chip/gfx9_enum.h \
+	addrlib/gfx9/coord.cpp \
+	addrlib/gfx9/coord.h \
+	addrlib/gfx9/gfx9addrlib.cpp \
+	addrlib/gfx9/gfx9addrlib.h \
+	addrlib/inc/chip/gfx9/gfx9_gb_reg.h \
+	addrlib/inc/chip/r800/si_gb_reg.h \
+	addrlib/r800/chip/si_ci_vi_merged_enum.h \
+	addrlib/r800/ciaddrlib.cpp \
+	addrlib/r800/ciaddrlib.h \
+	addrlib/r800/egbaddrlib.cpp \
+	addrlib/r800/egbaddrlib.h \
+	addrlib/r800/siaddrlib.cpp \
+	addrlib/r800/siaddrlib.h
 
 AMD_COMPILER_FILES = \
 	common/ac_binary.c \

src/amd/addrlib/addrinterface.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -61,13 +61,13 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
 {
     ADDR_E_RETURNCODE returnCode = ADDR_OK;
 
-    {
-        returnCode = Lib::Create(pAddrCreateIn, pAddrCreateOut);
-    }
+    returnCode = Lib::Create(pAddrCreateIn, pAddrCreateOut);
 
     return returnCode;
 }
 
+
+
 /**
 ****************************************************************************************************
 *   AddrDestroy
@@ -97,6 +97,8 @@ ADDR_E_RETURNCODE ADDR_API AddrDestroy(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                    Surface functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -133,6 +135,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
     return returnCode;
 }
 
+
+
 /**
 ****************************************************************************************************
 *   AddrComputeSurfaceAddrFromCoord
@@ -197,6 +201,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                   HTile functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -298,6 +304,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     C-mask functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -400,6 +408,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     F-mask functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -500,6 +510,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     DCC key functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -534,6 +546,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
     return returnCode;
 }
 
+
+
 ///////////////////////////////////////////////////////////////////////////////
 // Below functions are element related or helper functions
 ///////////////////////////////////////////////////////////////////////////////
@@ -836,34 +850,6 @@ BOOL_32 ADDR_API ElemGetExportNorm(
     return enabled;
 }
 
-/**
-****************************************************************************************************
-*   ElemSize
-*
-*   @brief
-*       Get bits-per-element for specified format
-*
-*   @return
-*       Bits-per-element of specified format
-*
-****************************************************************************************************
-*/
-UINT_32 ADDR_API ElemSize(
-    ADDR_HANDLE hLib,
-    AddrFormat  format)
-{
-    UINT_32 bpe = 0;
-
-    Addr::Lib* pLib = Lib::GetLib(hLib);
-
-    if (pLib != NULL)
-    {
-        bpe = pLib->GetBpe(format);
-    }
-
-    return bpe;
-}
-
 /**
 ****************************************************************************************************
 *   AddrConvertTileInfoToHW
@@ -1119,6 +1105,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
     return returnCode;
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                    Surface functions for Addr2
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1155,6 +1142,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeSurfaceAddrFromCoord
@@ -1187,6 +1175,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeSurfaceCoordFromAddr
@@ -1219,6 +1208,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                   HTile functions for Addr2
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1255,6 +1246,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeHtileAddrFromCoord
@@ -1287,6 +1279,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeHtileCoordFromAddr
@@ -1320,6 +1313,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     C-mask functions for Addr2
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1357,6 +1352,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeCmaskAddrFromCoord
@@ -1389,6 +1385,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeCmaskCoordFromAddr
@@ -1422,6 +1419,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     F-mask functions for Addr2
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1458,6 +1457,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeFmaskAddrFromCoord
@@ -1490,6 +1490,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Addr2ComputeFmaskCoordFromAddr
@@ -1522,6 +1523,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
     return returnCode;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     DCC key functions for Addr2
 ////////////////////////////////////////////////////////////////////////////////////////////////////

src/amd/addrlib/addrinterface.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -177,6 +177,7 @@ typedef struct _ADDR_EQUATION
                                                        ///< stacked vertically prior to swizzling
 } ADDR_EQUATION;
 
+
 /**
 ****************************************************************************************************
 * @brief Alloc system memory flags.
@@ -408,6 +409,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
     const ADDR_CREATE_INPUT*    pAddrCreateIn,
     ADDR_CREATE_OUTPUT*         pAddrCreateOut);
 
+
+
 /**
 ****************************************************************************************************
 *   AddrDestroy
@@ -422,6 +425,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
 ADDR_E_RETURNCODE ADDR_API AddrDestroy(
     ADDR_HANDLE hLib);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                    Surface functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -653,6 +658,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
     const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,
     ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
@@ -741,6 +748,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
     const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
     ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
@@ -922,6 +931,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
     const ADDR_COMPUTE_HTILE_INFO_INPUT*    pIn,
     ADDR_COMPUTE_HTILE_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
@@ -984,6 +995,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
     const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*   pIn,
     ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*        pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
@@ -1044,6 +1057,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
     const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT*   pIn,
     ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*        pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     C-mask functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1131,6 +1146,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
     const ADDR_COMPUTE_CMASK_INFO_INPUT*    pIn,
     ADDR_COMPUTE_CMASK_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
@@ -1191,6 +1208,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
     const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,
     ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
@@ -1249,6 +1268,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
     const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT*   pIn,
     ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*        pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     F-mask functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1329,6 +1350,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
     const ADDR_COMPUTE_FMASK_INFO_INPUT*    pIn,
     ADDR_COMPUTE_FMASK_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
@@ -1405,6 +1428,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
     const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*   pIn,
     ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*        pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
@@ -1478,6 +1503,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
     const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT*   pIn,
     ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*        pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                          Element/utility functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1566,6 +1593,7 @@ ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
     const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT*  pIn,
     ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
 
+
 /**
 ****************************************************************************************************
 *   ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
@@ -1623,6 +1651,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
     const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT*  pIn,
     ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*       pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_SLICESWIZZLE_INPUT
@@ -1649,6 +1679,8 @@ typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
                                         ///< README: When tileIndex is not -1, this must be valid
 } ADDR_COMPUTE_SLICESWIZZLE_INPUT;
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
@@ -1679,6 +1711,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
     const ADDR_COMPUTE_SLICESWIZZLE_INPUT*  pIn,
     ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*       pOut);
 
+
 /**
 ****************************************************************************************************
 *   AddrSwizzleGenOption
@@ -1769,6 +1802,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
     const ADDR_COMPUTE_BASE_SWIZZLE_INPUT*  pIn,
     ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*       pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ELEM_GETEXPORTNORM_INPUT
@@ -1809,6 +1844,8 @@ BOOL_32 ADDR_API ElemGetExportNorm(
     ADDR_HANDLE                     hLib,
     const ELEM_GETEXPORTNORM_INPUT* pIn);
 
+
+
 /**
 ****************************************************************************************************
 *   ELEM_FLT32TODEPTHPIXEL_INPUT
@@ -1864,6 +1901,8 @@ ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
     const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
     ELEM_FLT32TODEPTHPIXEL_OUTPUT*      pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ELEM_FLT32TOCOLORPIXEL_INPUT
@@ -1917,21 +1956,6 @@ ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
     const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
     ELEM_FLT32TOCOLORPIXEL_OUTPUT*      pOut);
 
-/**
-****************************************************************************************************
-*   ElemSize
-*
-*   @brief
-*       Get bits-per-element for specified format
-*
-*   @return
-*       Bits-per-element of specified format
-*
-****************************************************************************************************
-*/
-UINT_32 ADDR_API ElemSize(
-    ADDR_HANDLE hLib,
-    AddrFormat  format);
 
 /**
 ****************************************************************************************************
@@ -1990,6 +2014,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
     const ADDR_CONVERT_TILEINFOTOHW_INPUT*  pIn,
     ADDR_CONVERT_TILEINFOTOHW_OUTPUT*       pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_CONVERT_TILEINDEX_INPUT
@@ -2114,6 +2140,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
     const ADDR_CONVERT_TILEINDEX1_INPUT*    pIn,
     ADDR_CONVERT_TILEINDEX_OUTPUT*          pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_GET_TILEINDEX_INPUT
@@ -2159,6 +2187,8 @@ ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
     const ADDR_GET_TILEINDEX_INPUT* pIn,
     ADDR_GET_TILEINDEX_OUTPUT*      pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_PRT_INFO_INPUT
@@ -2203,6 +2233,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
     const ADDR_PRT_INFO_INPUT*  pIn,
     ADDR_PRT_INFO_OUTPUT*       pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     DCC key functions
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2263,6 +2295,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
     const ADDR_COMPUTE_DCCINFO_INPUT*       pIn,
     ADDR_COMPUTE_DCCINFO_OUTPUT*            pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR_GET_MAX_ALINGMENTS_OUTPUT
@@ -2326,6 +2360,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
 *
 **/
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                    Surface functions for Gfx9
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2360,8 +2395,7 @@ typedef union _ADDR2_SURFACE_FLAGS
         UINT_32 noMetadata        :  1; ///< This resource has no metadata
         UINT_32 metaRbUnaligned   :  1; ///< This resource has rb unaligned metadata
         UINT_32 metaPipeUnaligned :  1; ///< This resource has pipe unaligned metadata
-        UINT_32 view3dAs2dArray   :  1; ///< This resource is a 3D resource viewed as 2D array
-        UINT_32 reserved          : 13; ///< Reserved bits
+        UINT_32 reserved          : 14; ///< Reserved bits
     };
 
     UINT_32 value;
@@ -2489,6 +2523,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
     const ADDR2_COMPUTE_SURFACE_INFO_INPUT*    pIn,
     ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
@@ -2555,6 +2591,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
     const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT*    pIn,
     ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
@@ -2620,6 +2658,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
     const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT*    pIn,
     ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*         pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                   HTile functions for Gfx9
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2670,10 +2710,8 @@ typedef struct _ADDR2_META_MIP_INFO
 
         struct
         {
-            UINT_32    offset;      ///< Metadata offset within one slice,
-                                    ///  the thickness of a slice is meta block depth.
-            UINT_32    sliceSize;   ///< Metadata size within one slice,
-                                    ///  the thickness of a slice is meta block depth.
+            UINT_32    offset;
+            UINT_32    sliceSize;
         };
     };
 } ADDR2_META_MIP_INFO;
@@ -2697,9 +2735,7 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
     UINT_32             unalignedHeight;    ///< Depth surface original height (of mip0)
     UINT_32             numSlices;          ///< Number of slices of depth surface (of mip0)
     UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
-    UINT_32             firstMipIdInTail;   ///  Id of the first mip in tail,
-                                            ///  if no mip is in tail, it should be set to
-                                            ///  number of mip levels
+    UINT_32             firstMipIdInTail;
 } ADDR2_COMPUTE_HTILE_INFO_INPUT;
 
 /**
@@ -2741,6 +2777,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
     const ADDR2_COMPUTE_HTILE_INFO_INPUT*    pIn,
     ADDR2_COMPUTE_HTILE_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
@@ -2798,6 +2836,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
     const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT*    pIn,
     ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
@@ -2856,6 +2896,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
     const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT*    pIn,
     ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*         pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     C-mask functions for Gfx9
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2921,6 +2963,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
     const ADDR2_COMPUTE_CMASK_INFO_INPUT*    pIn,
     ADDR2_COMPUTE_CMASK_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
@@ -2982,6 +3026,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
     const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT*   pIn,
     ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*        pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
@@ -3040,6 +3086,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
     const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT*    pIn,
     ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*         pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     F-mask functions for Gfx9
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -3122,6 +3170,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
     const ADDR2_COMPUTE_FMASK_INFO_INPUT*    pIn,
     ADDR2_COMPUTE_FMASK_INFO_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
@@ -3181,6 +3231,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
     const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT*    pIn,
     ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*         pOut);
 
+
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
@@ -3239,6 +3291,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
     const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT*    pIn,
     ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*         pOut);
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                                     DCC key functions for Gfx9
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -3267,8 +3321,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
     UINT_32             numMipLevels;       ///< Total mipmap levels of color surface
     UINT_32             dataSurfaceSize;    ///< The padded size of all slices and mip levels
                                             ///< useful in meta linear case
-    UINT_32             firstMipIdInTail;   ///< The id of first mip in tail, if no mip is in tail,
-                                            ///  it should be number of mip levels
+    UINT_32             firstMipIdInTail;
 } ADDR2_COMPUTE_DCCINFO_INPUT;
 
 /**
@@ -3303,9 +3356,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
     union
     {
         UINT_32 fastClearSizePerSlice;  ///< Size of DCC within a slice should be fast cleared
-        UINT_32 dccRamSliceSize;        ///< DCC ram size per slice. For mipmap, it's
-                                        ///  the slize size of a mip chain, the thickness of a
-                                        ///  a slice is meta block depth
+        UINT_32 dccRamSliceSize;
     };
 
     ADDR2_META_MIP_INFO* pMipInfo;      ///< DCC mip information
@@ -3325,6 +3376,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
     const ADDR2_COMPUTE_DCCINFO_INPUT*    pIn,
     ADDR2_COMPUTE_DCCINFO_OUTPUT*         pOut);
 
+
 /**
 ****************************************************************************************************
 *   ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
@@ -3576,55 +3628,6 @@ typedef union _ADDR2_SWTYPE_SET
     UINT_32 value;
 } ADDR2_SWTYPE_SET;
 
-/**
-****************************************************************************************************
-*   ADDR2_SWMODE_SET
-*
-*   @brief
-*       Bit field that defines swizzle type
-****************************************************************************************************
-*/
-typedef union _ADDR2_SWMODE_SET
-{
-    struct
-    {
-        UINT_32 swLinear   : 1;
-        UINT_32 sw256B_S   : 1;
-        UINT_32 sw256B_D   : 1;
-        UINT_32 sw256B_R   : 1;
-        UINT_32 sw4KB_Z    : 1;
-        UINT_32 sw4KB_S    : 1;
-        UINT_32 sw4KB_D    : 1;
-        UINT_32 sw4KB_R    : 1;
-        UINT_32 sw64KB_Z   : 1;
-        UINT_32 sw64KB_S   : 1;
-        UINT_32 sw64KB_D   : 1;
-        UINT_32 sw64KB_R   : 1;
-        UINT_32 swVar_Z    : 1;
-        UINT_32 swVar_S    : 1;
-        UINT_32 swVar_D    : 1;
-        UINT_32 swVar_R    : 1;
-        UINT_32 sw64KB_Z_T : 1;
-        UINT_32 sw64KB_S_T : 1;
-        UINT_32 sw64KB_D_T : 1;
-        UINT_32 sw64KB_R_T : 1;
-        UINT_32 sw4KB_Z_X  : 1;
-        UINT_32 sw4KB_S_X  : 1;
-        UINT_32 sw4KB_D_X  : 1;
-        UINT_32 sw4KB_R_X  : 1;
-        UINT_32 sw64KB_Z_X : 1;
-        UINT_32 sw64KB_S_X : 1;
-        UINT_32 sw64KB_D_X : 1;
-        UINT_32 sw64KB_R_X : 1;
-        UINT_32 swVar_Z_X  : 1;
-        UINT_32 swVar_S_X  : 1;
-        UINT_32 swVar_D_X  : 1;
-        UINT_32 swVar_R_X  : 1;
-    };
-
-    UINT_32 value;
-} ADDR2_SWMODE_SET;
-
 /**
 ****************************************************************************************************
 *   ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
@@ -3678,7 +3681,6 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
                                                 ///  type
     ADDR2_SWTYPE_SET      validSwTypeSet;       ///< Valid swizzle type bit combination
     ADDR2_SWTYPE_SET      clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
-    ADDR2_SWMODE_SET      validSwModeSet;       ///< Valid swizzle mode bit combination
 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
 
 /**

src/amd/addrlib/addrtypes.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -112,6 +112,7 @@ typedef int            INT;
     #define GC_FASTCALL  ADDR_FASTCALL
 #endif
 
+
 #if defined(__GNUC__)
     #define ADDR_INLINE static inline   // inline needs to be static to link
 #else
@@ -352,7 +353,7 @@ typedef enum _AddrFormat {
     ADDR_FMT_3_3_2                                = 0x00000003,
     ADDR_FMT_RESERVED_4                           = 0x00000004,
     ADDR_FMT_16                                   = 0x00000005,
-    ADDR_FMT_16_FLOAT                             = ADDR_FMT_16,
+    ADDR_FMT_16_FLOAT                             = 0x00000006,
     ADDR_FMT_8_8                                  = 0x00000007,
     ADDR_FMT_5_6_5                                = 0x00000008,
     ADDR_FMT_6_5_5                                = 0x00000009,
@@ -360,28 +361,28 @@ typedef enum _AddrFormat {
     ADDR_FMT_4_4_4_4                              = 0x0000000b,
     ADDR_FMT_5_5_5_1                              = 0x0000000c,
     ADDR_FMT_32                                   = 0x0000000d,
-    ADDR_FMT_32_FLOAT                             = ADDR_FMT_32,
+    ADDR_FMT_32_FLOAT                             = 0x0000000e,
     ADDR_FMT_16_16                                = 0x0000000f,
-    ADDR_FMT_16_16_FLOAT                          = ADDR_FMT_16_16,
+    ADDR_FMT_16_16_FLOAT                          = 0x00000010,
     ADDR_FMT_8_24                                 = 0x00000011,
-    ADDR_FMT_8_24_FLOAT                           = ADDR_FMT_8_24,
+    ADDR_FMT_8_24_FLOAT                           = 0x00000012,
     ADDR_FMT_24_8                                 = 0x00000013,
-    ADDR_FMT_24_8_FLOAT                           = ADDR_FMT_24_8,
+    ADDR_FMT_24_8_FLOAT                           = 0x00000014,
     ADDR_FMT_10_11_11                             = 0x00000015,
-    ADDR_FMT_10_11_11_FLOAT                       = ADDR_FMT_10_11_11,
+    ADDR_FMT_10_11_11_FLOAT                       = 0x00000016,
     ADDR_FMT_11_11_10                             = 0x00000017,
-    ADDR_FMT_11_11_10_FLOAT                       = ADDR_FMT_11_11_10,
+    ADDR_FMT_11_11_10_FLOAT                       = 0x00000018,
     ADDR_FMT_2_10_10_10                           = 0x00000019,
     ADDR_FMT_8_8_8_8                              = 0x0000001a,
     ADDR_FMT_10_10_10_2                           = 0x0000001b,
     ADDR_FMT_X24_8_32_FLOAT                       = 0x0000001c,
     ADDR_FMT_32_32                                = 0x0000001d,
-    ADDR_FMT_32_32_FLOAT                          = ADDR_FMT_32_32,
+    ADDR_FMT_32_32_FLOAT                          = 0x0000001e,
     ADDR_FMT_16_16_16_16                          = 0x0000001f,
-    ADDR_FMT_16_16_16_16_FLOAT                    = ADDR_FMT_16_16_16_16,
+    ADDR_FMT_16_16_16_16_FLOAT                    = 0x00000020,
     ADDR_FMT_RESERVED_33                          = 0x00000021,
     ADDR_FMT_32_32_32_32                          = 0x00000022,
-    ADDR_FMT_32_32_32_32_FLOAT                    = ADDR_FMT_32_32_32_32,
+    ADDR_FMT_32_32_32_32_FLOAT                    = 0x00000023,
     ADDR_FMT_RESERVED_36                          = 0x00000024,
     ADDR_FMT_1                                    = 0x00000025,
     ADDR_FMT_1_REVERSED                           = 0x00000026,
@@ -392,9 +393,9 @@ typedef enum _AddrFormat {
     ADDR_FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
     ADDR_FMT_8_8_8                                = 0x0000002c,
     ADDR_FMT_16_16_16                             = 0x0000002d,
-    ADDR_FMT_16_16_16_FLOAT                       = ADDR_FMT_16_16_16,
+    ADDR_FMT_16_16_16_FLOAT                       = 0x0000002e,
     ADDR_FMT_32_32_32                             = 0x0000002f,
-    ADDR_FMT_32_32_32_FLOAT                       = ADDR_FMT_32_32_32,
+    ADDR_FMT_32_32_32_FLOAT                       = 0x00000030,
     ADDR_FMT_BC1                                  = 0x00000031,
     ADDR_FMT_BC2                                  = 0x00000032,
     ADDR_FMT_BC3                                  = 0x00000033,
@@ -549,6 +550,7 @@ typedef enum _AddrHtileBlockSize
     ADDR_HTILE_BLOCKSIZE_8 = 8,
 } AddrHtileBlockSize;
 
+
 /**
 ****************************************************************************************************
 *   AddrPipeCfg
@@ -582,8 +584,7 @@ typedef enum _AddrPipeCfg
     ADDR_PIPECFG_P8_32x64_32x32  = 15,
     ADDR_PIPECFG_P16_32x32_8x16  = 17, /// 16 pipes
     ADDR_PIPECFG_P16_32x32_16x16 = 18,
-    ADDR_PIPECFG_RESERVED        = 19, /// reserved for internal use
-    ADDR_PIPECFG_MAX             = 20,
+    ADDR_PIPECFG_MAX             = 19,
 } AddrPipeCfg;
 
 /**
@@ -711,6 +712,7 @@ typedef enum _AddrTileType
 #define ADDR64D "lld" OR "I64d"
 #endif
 
+
 /// @brief Union for storing a 32-bit float or 32-bit integer
 /// @ingroup type
 ///
@@ -726,6 +728,7 @@ typedef union {
     float    f;
 } ADDR_FLT_32;
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //
 //  Macros for controlling linking and building on multiple systems

src/amd/addrlib/amdgpu_asic_addr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2017-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -96,6 +96,7 @@
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
 #define AMDGPU_IN_RANGE(val, ...)   AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
 
+
 // ASICREV_IS(eRevisionId, revisionName)
 #define ASICREV_IS(r, rn)              AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
 #define ASICREV_IS_TAHITI_P(r)         ASICREV_IS(r, TAHITI)

src/amd/addrlib/core/addrcommon.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -99,6 +99,7 @@
 #define ADDR_INFO(cond, a)         \
 { if (!(cond)) { ADDR_PRNT(a); } }
 
+
 /// @brief Macro for reporting error warning messages
 /// @ingroup util
 ///
@@ -117,6 +118,7 @@
     ADDR_PRNT(("  WARNING in file %s, line %d\n", __FILE__, __LINE__)); \
 } }
 
+
 /// @brief Macro for reporting fatal error conditions
 /// @ingroup util
 ///
@@ -259,8 +261,7 @@ union ConfigFlags
         UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
         UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
         UINT_32 disableLinearOpt       : 1;    ///< Disallow tile modes to be optimized to linear
-        UINT_32 use32bppFor422Fmt      : 1;    ///< View 422 formats as 32 bits per pixel element
-        UINT_32 reserved               : 21;   ///< Reserved bits for future use
+        UINT_32 reserved               : 22;   ///< Reserved bits for future use
     };
 
     UINT_32 value;
@@ -844,6 +845,7 @@ static inline VOID InitChannel(
     pChanSet->index = index;
 }
 
+
 /**
 ****************************************************************************************************
 *   InitChannel

src/amd/addrlib/core/addrelemlib.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -72,7 +72,6 @@ ElemLib::ElemLib(
         default:
             m_fp16ExportNorm = 1;
             m_depthPlanarType = ADDR_DEPTH_PLANAR_R800;
-            break;
     }
 
     m_configFlags.value = 0;
@@ -347,6 +346,7 @@ VOID ElemLib::Int32sToPixel(
     UINT_32 elemMask=0;
     UINT_32 elementXor = 0;  // address xor when reading bytes from elements
 
+
     // @@ NOTE: assert if called on a compressed format!
 
     if (properties.byteAligned)    // Components are all byte-sized
@@ -1387,33 +1387,38 @@ UINT_32 ElemLib::GetBitsPerPixel(
         case ADDR_FMT_8_8:
         case ADDR_FMT_4_4_4_4:
         case ADDR_FMT_16:
+        case ADDR_FMT_16_FLOAT:
             bpp = 16;
             break;
-        case ADDR_FMT_GB_GR:
+        case ADDR_FMT_GB_GR: // treat as FMT_8_8
             elemMode = ADDR_PACKED_GBGR;
-            bpp      = m_configFlags.use32bppFor422Fmt ? 32 : 16;
-            expandX  = m_configFlags.use32bppFor422Fmt ? 2 : 1;
+            bpp     = 16;
             break;
-        case ADDR_FMT_BG_RG:
+        case ADDR_FMT_BG_RG: // treat as FMT_8_8
             elemMode = ADDR_PACKED_BGRG;
-            bpp      = m_configFlags.use32bppFor422Fmt ? 32 : 16;
-            expandX  = m_configFlags.use32bppFor422Fmt ? 2 : 1;
+            bpp     = 16;
             break;
         case ADDR_FMT_8_8_8_8:
         case ADDR_FMT_2_10_10_10:
         case ADDR_FMT_10_11_11:
         case ADDR_FMT_11_11_10:
         case ADDR_FMT_16_16:
+        case ADDR_FMT_16_16_FLOAT:
         case ADDR_FMT_32:
+        case ADDR_FMT_32_FLOAT:
         case ADDR_FMT_24_8:
+        case ADDR_FMT_24_8_FLOAT:
             bpp = 32;
             break;
         case ADDR_FMT_16_16_16_16:
+        case ADDR_FMT_16_16_16_16_FLOAT:
         case ADDR_FMT_32_32:
+        case ADDR_FMT_32_32_FLOAT:
         case ADDR_FMT_CTX1:
             bpp = 64;
             break;
         case ADDR_FMT_32_32_32_32:
+        case ADDR_FMT_32_32_32_32_FLOAT:
             bpp = 128;
             break;
         case ADDR_FMT_INVALID:
@@ -1439,7 +1444,10 @@ UINT_32 ElemLib::GetBitsPerPixel(
         case ADDR_FMT_32_AS_8:
         case ADDR_FMT_32_AS_8_8:
         case ADDR_FMT_8_24:
+        case ADDR_FMT_8_24_FLOAT:
         case ADDR_FMT_10_10_10_2:
+        case ADDR_FMT_10_11_11_FLOAT:
+        case ADDR_FMT_11_11_10_FLOAT:
         case ADDR_FMT_5_9_9_9_SHAREDEXP:
             bpp = 32;
             break;
@@ -1453,10 +1461,12 @@ UINT_32 ElemLib::GetBitsPerPixel(
             expandX = 3;
             break;
         case ADDR_FMT_16_16_16:
+        case ADDR_FMT_16_16_16_FLOAT:
             elemMode = ADDR_EXPANDED;
             bpp = 48;//@@ 16;      // read 3 elements per pixel
             expandX = 3;
             break;
+        case ADDR_FMT_32_32_32_FLOAT:
         case ADDR_FMT_32_32_32:
             elemMode = ADDR_EXPANDED;
             expandX = 3;
@@ -1745,6 +1755,7 @@ BOOL_32 ElemLib::IsBlockCompressed(
             ((format >= ADDR_FMT_ASTC_4x4) && (format <= ADDR_FMT_ETC2_128BPP)));
 }
 
+
 /**
 ****************************************************************************************************
 *   ElemLib::IsCompressed
@@ -1786,7 +1797,9 @@ BOOL_32 ElemLib::IsExpand3x(
     {
         case ADDR_FMT_8_8_8:
         case ADDR_FMT_16_16_16:
+        case ADDR_FMT_16_16_16_FLOAT:
         case ADDR_FMT_32_32_32:
+        case ADDR_FMT_32_32_32_FLOAT:
             is3x = TRUE;
             break;
         default:

src/amd/addrlib/core/addrelemlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/core/addrlib.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -157,6 +157,7 @@ Lib::~Lib()
     }
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               Initialization/Helper
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -206,7 +207,7 @@ ADDR_E_RETURNCODE Lib::Create(
                         pLib = SiHwlInit(&client);
                         break;
                     case FAMILY_VI:
-                    case FAMILY_CZ:
+                    case FAMILY_CZ: // VI based fusion(carrizo)
                     case FAMILY_CI:
                     case FAMILY_KV: // CI based fusion
                         pLib = CiHwlInit(&client);
@@ -485,10 +486,12 @@ UINT_32 Lib::Bits2Number(
     return number;
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               Element lib
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
+
 /**
 ****************************************************************************************************
 *   Lib::Flt32ToColorPixel
@@ -604,6 +607,7 @@ ADDR_E_RETURNCODE Lib::Flt32ToColorPixel(
     return returnCode;
 }
 
+
 /**
 ****************************************************************************************************
 *   Lib::GetExportNorm
@@ -637,19 +641,4 @@ BOOL_32 Lib::GetExportNorm(
     return enabled;
 }
 
-/**
-****************************************************************************************************
-*   Lib::GetBpe
-*
-*   @brief
-*       Get bits-per-element for specified format
-*   @return
-*       bits-per-element of specified format
-****************************************************************************************************
-*/
-UINT_32 Lib::GetBpe(AddrFormat format) const
-{
-    return GetElemLib()->GetBitsPerPixel(format);
-}
-
 } // Addr

src/amd/addrlib/core/addrlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -286,8 +286,6 @@ public:
 
     ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
 
-    UINT_32 GetBpe(AddrFormat format) const;
-
 protected:
     Lib();  // Constructor is protected
     Lib(const Client* pClient);

src/amd/addrlib/core/addrlib1.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2016 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -140,17 +140,19 @@ Lib* Lib::GetLib(
         ((pAddrLib->GetChipFamily() == ADDR_CHIP_FAMILY_IVLD) ||
          (pAddrLib->GetChipFamily() > ADDR_CHIP_FAMILY_VI)))
     {
-        // only valid and pre-VI ASIC can use AddrLib1 function.
+        // only valid and pre-VI AISC can use AddrLib1 function.
         ADDR_ASSERT_ALWAYS();
         hLib = NULL;
     }
     return static_cast<Lib*>(hLib);
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               Surface Methods
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
+
 /**
 ****************************************************************************************************
 *   Lib::ComputeSurfaceInfo
@@ -1228,6 +1230,8 @@ UINT_32 Lib::Thickness(
     return ModeFlags[tileMode].thickness;
 }
 
+
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               CMASK/HTILE
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2008,6 +2012,7 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
     *pPitchOut = (pitchIn + macroWidth - 1) & ~(macroWidth - 1);
     *pHeightOut = (heightIn + macroHeight - 1) & ~(macroHeight - 1);
 
+
     sliceBytes = ComputeCmaskBytes(*pPitchOut,
                                    *pHeightOut,
                                    1);
@@ -2235,6 +2240,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
     UINT_32 groupBits = 8 * m_pipeInterleaveBytes;
     UINT_32 pipes = numPipes;
 
+
     //
     // Compute the micro tile size, in bits. And macro tile pitch and height.
     //
@@ -2287,17 +2293,20 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
     pitch = pitchAligned;
     height = heightAligned;
 
+
     //
     // Convert byte address to bit address.
     //
     bitAddr = BYTES_TO_BITS(addr) + bitPosition;
 
+
     //
     // Remove pipe bits from address.
     //
 
     bitAddr = (bitAddr % groupBits) + ((bitAddr/groupBits/pipes)*groupBits);
 
+
     elemOffset = bitAddr / elemBits;
 
     tilesPerMacro = (macroTilePitch/factor) * macroTileHeight / MicroTilePixels >> numPipeBits;
@@ -2315,6 +2324,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
     macroY = static_cast<UINT_32>((macroNumber % macrosPerSlice) / macrosPerPitch);
     macroZ = static_cast<UINT_32>((macroNumber / macrosPerSlice));
 
+
     microX = microNumber % (macroTilePitch / factor / MicroTileWidth);
     microY = (microNumber / (macroTilePitch / factor / MicroTileHeight));
 
@@ -2325,6 +2335,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
     microTileCoordY = ComputeXmaskCoordYFromPipe(pipe,
                                                  *pX/MicroTileWidth);
 
+
     //
     // Assemble final coordinates.
     //
@@ -2384,6 +2395,7 @@ UINT_64 Lib::HwlComputeXmaskAddrFromCoord(
     UINT_64 offsetHi;
     UINT_64 groupMask;
 
+
     UINT_32 elemBits = 0;
 
     UINT_32 numPipes = m_pipes; // This function is accessed prior to si only
@@ -3346,6 +3358,7 @@ VOID Lib::PadDimensions(
                      heightAlign);
 }
 
+
 /**
 ****************************************************************************************************
 *   Lib::HwlPreHandleBaseLvl3xPitch
@@ -3407,6 +3420,7 @@ UINT_32 Lib::HwlPostHandleBaseLvl3xPitch(
     return expPitch;
 }
 
+
 /**
 ****************************************************************************************************
 *   Lib::IsMacroTiled
@@ -3927,6 +3941,7 @@ VOID Lib::ComputeQbStereoInfo(
     // 1D surface on SI may break this rule, but we can force it to meet by checking .qbStereo.
 }
 
+
 /**
 ****************************************************************************************************
 *   Lib::ComputePrtInfo

src/amd/addrlib/core/addrlib1.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2016 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -354,6 +354,7 @@ protected:
         const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
         UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const = 0;
 
+
     virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
     {
         // not supported in hwl layer

src/amd/addrlib/core/addrlib2.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -113,17 +113,19 @@ Lib* Lib::GetLib(
     if ((pAddrLib != NULL) &&
         (pAddrLib->GetChipFamily() <= ADDR_CHIP_FAMILY_VI))
     {
-        // only valid and GFX9+ ASIC can use AddrLib2 function.
+        // only valid and GFX9+ AISC can use AddrLib2 function.
         ADDR_ASSERT_ALWAYS();
         hLib = NULL;
     }
     return static_cast<Lib*>(hLib);
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               Surface Methods
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
+
 /**
 ************************************************************************************************************************
 *   Lib::ComputeSurfaceInfo
@@ -415,6 +417,7 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceCoordFromAddr(
     return returnCode;
 }
 
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 //                               CMASK/HTILE
 ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -830,6 +833,10 @@ ADDR_E_RETURNCODE Lib::ComputePipeBankXor(
     {
         returnCode = ADDR_INVALIDPARAMS;
     }
+    else if (IsXor(pIn->swizzleMode) == FALSE)
+    {
+        returnCode = ADDR_NOTSUPPORTED;
+    }
     else
     {
         returnCode = HwlComputePipeBankXor(pIn, pOut);
@@ -1878,6 +1885,7 @@ VOID Lib::ComputeQbStereoInfo(
     pOut->surfSize <<= 1;
 }
 
+
 } // V2
 } // Addr
 

src/amd/addrlib/core/addrlib2.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -83,39 +83,6 @@ struct Dim3d
     UINT_32 d;
 };
 
-// Macro define resource block type
-enum AddrBlockType
-{
-    AddrBlockMicro     = 0, // Resource uses 256B block
-    AddrBlock4KB       = 1, // Resource uses 4KB block
-    AddrBlock64KB      = 2, // Resource uses 64KB block
-    AddrBlockVar       = 3, // Resource uses var block, only valid for GFX9
-    AddrBlockLinear    = 4, // Resource uses linear swizzle mode
-
-    AddrBlockMaxTiledType = AddrBlock64KB + 1,
-};
-
-enum AddrBlockSet
-{
-    AddrBlockSetMicro     = 1 << AddrBlockMicro,
-    AddrBlockSetMacro4KB  = 1 << AddrBlock4KB,
-    AddrBlockSetMacro64KB = 1 << AddrBlock64KB,
-    AddrBlockSetVar       = 1 << AddrBlockVar,
-    AddrBlockSetLinear    = 1 << AddrBlockLinear,
-
-    AddrBlockSetMacro   = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
-};
-
-enum AddrSwSet
-{
-    AddrSwSetZ = 1 << ADDR_SW_Z,
-    AddrSwSetS = 1 << ADDR_SW_S,
-    AddrSwSetD = 1 << ADDR_SW_D,
-    AddrSwSetR = 1 << ADDR_SW_R,
-
-    AddrSwSetAll         = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
-};
-
 /**
 ************************************************************************************************************************
 * @brief This class contains asic independent address lib functionalities
@@ -223,7 +190,6 @@ protected:
     Lib(const Client* pClient);
 
     static const UINT_32 MaxNumOfBpp = 5;
-    static const UINT_32 MaxNumOfAA  = 4;
 
     static const Dim2d Block256_2d[MaxNumOfBpp];
     static const Dim3d Block1K_3d[MaxNumOfBpp];
@@ -270,21 +236,6 @@ protected:
         return m_swizzleModeTable[swizzleMode].isZ;
     }
 
-    BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const
-    {
-        return m_swizzleModeTable[swizzleMode].isStd;
-    }
-
-    BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const
-    {
-        return m_swizzleModeTable[swizzleMode].isDisp;
-    }
-
-    BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
-    {
-        return m_swizzleModeTable[swizzleMode].isRot;
-    }
-
     BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
     {
         return HwlIsStandardSwizzle(resourceType, swizzleMode);
@@ -295,6 +246,11 @@ protected:
         return HwlIsDisplaySwizzle(resourceType, swizzleMode);
     }
 
+    BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
+    {
+        return m_swizzleModeTable[swizzleMode].isRot;
+    }
+
     BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
     {
         return m_swizzleModeTable[swizzleMode].isXor;
@@ -540,6 +496,7 @@ protected:
         return ADDR_NOTSUPPORTED;
     }
 
+
     virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
         const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
         ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT*      pOut) const

src/amd/addrlib/core/addrobject.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/core/addrobject.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/gfx9/coord.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -28,11 +28,6 @@
 #include "addrcommon.h"
 #include "coord.h"
 
-namespace Addr
-{
-namespace V2
-{
-
 Coordinate::Coordinate()
 {
     dim = 'x';
@@ -710,5 +705,3 @@ BOOL_32 CoordEq::operator!=(const CoordEq& b)
     return !(*this == b);
 }
 
-} // V2
-} // Addr

src/amd/addrlib/gfx9/coord.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -29,11 +29,6 @@
 #ifndef __COORD_H
 #define __COORD_H
 
-namespace Addr
-{
-namespace V2
-{
-
 class Coordinate
 {
 public:
@@ -115,8 +110,5 @@ private:
     CoordTerm m_eq[MaxEqBits];
 };
 
-} // V2
-} // Addr
-
 #endif
 

src/amd/addrlib/gfx9/gfx9addrlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -57,7 +57,6 @@ struct Gfx9ChipSettings
         UINT_32 isRaven             : 1;
         UINT_32 isVega12            : 1;
         UINT_32 isVega20            : 1;
-        UINT_32 reserved0           : 27;
 
         // Display engine IP version name
         UINT_32 isDce12             : 1;
@@ -85,155 +84,6 @@ enum Gfx9DataType
     Gfx9DataFmask
 };
 
-const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR);
-
-const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
-                                      (1u << ADDR_SW_256B_D) |
-                                      (1u << ADDR_SW_256B_R);
-
-const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z)   |
-                                     (1u << ADDR_SW_4KB_S)   |
-                                     (1u << ADDR_SW_4KB_D)   |
-                                     (1u << ADDR_SW_4KB_R)   |
-                                     (1u << ADDR_SW_4KB_Z_X) |
-                                     (1u << ADDR_SW_4KB_S_X) |
-                                     (1u << ADDR_SW_4KB_D_X) |
-                                     (1u << ADDR_SW_4KB_R_X);
-
-const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z)   |
-                                      (1u << ADDR_SW_64KB_S)   |
-                                      (1u << ADDR_SW_64KB_D)   |
-                                      (1u << ADDR_SW_64KB_R)   |
-                                      (1u << ADDR_SW_64KB_Z_T) |
-                                      (1u << ADDR_SW_64KB_S_T) |
-                                      (1u << ADDR_SW_64KB_D_T) |
-                                      (1u << ADDR_SW_64KB_R_T) |
-                                      (1u << ADDR_SW_64KB_Z_X) |
-                                      (1u << ADDR_SW_64KB_S_X) |
-                                      (1u << ADDR_SW_64KB_D_X) |
-                                      (1u << ADDR_SW_64KB_R_X);
-
-const UINT_32 Gfx9BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z)   |
-                                     (1u << ADDR_SW_VAR_S)   |
-                                     (1u << ADDR_SW_VAR_D)   |
-                                     (1u << ADDR_SW_VAR_R)   |
-                                     (1u << ADDR_SW_VAR_Z_X) |
-                                     (1u << ADDR_SW_VAR_S_X) |
-                                     (1u << ADDR_SW_VAR_D_X) |
-                                     (1u << ADDR_SW_VAR_R_X);
-
-const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z)    |
-                                (1u << ADDR_SW_64KB_Z)   |
-                                (1u << ADDR_SW_VAR_Z)    |
-                                (1u << ADDR_SW_64KB_Z_T) |
-                                (1u << ADDR_SW_4KB_Z_X)  |
-                                (1u << ADDR_SW_64KB_Z_X) |
-                                (1u << ADDR_SW_VAR_Z_X);
-
-const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S)   |
-                                       (1u << ADDR_SW_4KB_S)    |
-                                       (1u << ADDR_SW_64KB_S)   |
-                                       (1u << ADDR_SW_VAR_S)    |
-                                       (1u << ADDR_SW_64KB_S_T) |
-                                       (1u << ADDR_SW_4KB_S_X)  |
-                                       (1u << ADDR_SW_64KB_S_X) |
-                                       (1u << ADDR_SW_VAR_S_X);
-
-const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D)   |
-                                      (1u << ADDR_SW_4KB_D)    |
-                                      (1u << ADDR_SW_64KB_D)   |
-                                      (1u << ADDR_SW_VAR_D)    |
-                                      (1u << ADDR_SW_64KB_D_T) |
-                                      (1u << ADDR_SW_4KB_D_X)  |
-                                      (1u << ADDR_SW_64KB_D_X) |
-                                      (1u << ADDR_SW_VAR_D_X);
-
-const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R)   |
-                                     (1u << ADDR_SW_4KB_R)    |
-                                     (1u << ADDR_SW_64KB_R)   |
-                                     (1u << ADDR_SW_VAR_R)    |
-                                     (1u << ADDR_SW_64KB_R_T) |
-                                     (1u << ADDR_SW_4KB_R_X)  |
-                                     (1u << ADDR_SW_64KB_R_X) |
-                                     (1u << ADDR_SW_VAR_R_X);
-
-const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X)  |
-                                (1u << ADDR_SW_4KB_S_X)  |
-                                (1u << ADDR_SW_4KB_D_X)  |
-                                (1u << ADDR_SW_4KB_R_X)  |
-                                (1u << ADDR_SW_64KB_Z_X) |
-                                (1u << ADDR_SW_64KB_S_X) |
-                                (1u << ADDR_SW_64KB_D_X) |
-                                (1u << ADDR_SW_64KB_R_X) |
-                                (1u << ADDR_SW_VAR_Z_X)  |
-                                (1u << ADDR_SW_VAR_S_X)  |
-                                (1u << ADDR_SW_VAR_D_X)  |
-                                (1u << ADDR_SW_VAR_R_X);
-
-const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) |
-                                (1u << ADDR_SW_64KB_S_T) |
-                                (1u << ADDR_SW_64KB_D_T) |
-                                (1u << ADDR_SW_64KB_R_T);
-
-const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask |
-                                  Gfx9TSwModeMask;
-
-const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask   |
-                                  Gfx9ZSwModeMask        |
-                                  Gfx9StandardSwModeMask |
-                                  Gfx9DisplaySwModeMask  |
-                                  Gfx9RotateSwModeMask;
-
-const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask;
-
-const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask;
-
-const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask;
-
-const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask;
-
-const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask;
-
-const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask;
-
-const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask;
-
-const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR)   |
-                                        (1u << ADDR_SW_4KB_D)    |
-                                        (1u << ADDR_SW_4KB_R)    |
-                                        (1u << ADDR_SW_64KB_D)   |
-                                        (1u << ADDR_SW_64KB_R)   |
-                                        (1u << ADDR_SW_VAR_D)    |
-                                        (1u << ADDR_SW_VAR_R)    |
-                                        (1u << ADDR_SW_4KB_D_X)  |
-                                        (1u << ADDR_SW_4KB_R_X)  |
-                                        (1u << ADDR_SW_64KB_D_X) |
-                                        (1u << ADDR_SW_64KB_R_X) |
-                                        (1u << ADDR_SW_VAR_D_X)  |
-                                        (1u << ADDR_SW_VAR_R_X);
-
-const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) |
-                                     (1u << ADDR_SW_256B_R) |
-                                     Dce12NonBpp32SwModeMask;
-
-const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR)   |
-                                       (1u << ADDR_SW_4KB_S)    |
-                                       (1u << ADDR_SW_64KB_S)   |
-                                       (1u << ADDR_SW_VAR_S)    |
-                                       (1u << ADDR_SW_64KB_S_T) |
-                                       (1u << ADDR_SW_4KB_S_X)  |
-                                       (1u << ADDR_SW_64KB_S_X) |
-                                       (1u << ADDR_SW_VAR_S_X);
-
-const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D)    |
-                                    (1u << ADDR_SW_64KB_D)   |
-                                    (1u << ADDR_SW_VAR_D)    |
-                                    (1u << ADDR_SW_64KB_D_T) |
-                                    (1u << ADDR_SW_4KB_D_X)  |
-                                    (1u << ADDR_SW_64KB_D_X) |
-                                    (1u << ADDR_SW_VAR_D_X)  |
-                                    Dcn1NonBpp64SwModeMask;
-
 /**
 ************************************************************************************************************************
 * @brief GFX9 meta equation parameters
@@ -272,9 +122,6 @@ public:
         return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
     }
 
-    virtual BOOL_32 IsValidDisplaySwizzleMode(
-        const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
-
 protected:
     Gfx9Lib(const Client* pClient);
     virtual ~Gfx9Lib();
@@ -521,6 +368,7 @@ protected:
         return compressBlkDim;
     }
 
+
     static const UINT_32          MaxSeLog2      = 3;
     static const UINT_32          MaxRbPerSeLog2 = 2;
 
@@ -584,37 +432,14 @@ private:
                         UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
                         UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
 
+    BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
+
     ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
         UINT_32*                                pMipmap0PaddedWidth,
         UINT_32*                                pSlice0PaddedHeight,
         ADDR2_MIP_INFO*                         pMipInfo = NULL) const;
 
-    static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet)
-    {
-        ADDR2_BLOCK_SET allowedBlockSet = {};
-
-        allowedBlockSet.micro     = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE;
-        allowedBlockSet.macro4KB  = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask)  ? TRUE : FALSE;
-        allowedBlockSet.macro64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE;
-        allowedBlockSet.var       = (allowedSwModeSet.value & Gfx9BlkVarSwModeMask)  ? TRUE : FALSE;
-        allowedBlockSet.linear    = (allowedSwModeSet.value & Gfx9LinearSwModeMask)  ? TRUE : FALSE;
-
-        return allowedBlockSet;
-    }
-
-    static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
-    {
-        ADDR2_SWTYPE_SET allowedSwSet = {};
-
-        allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask)        ? TRUE : FALSE;
-        allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE;
-        allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask)  ? TRUE : FALSE;
-        allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask)   ? TRUE : FALSE;
-
-        return allowedSwSet;
-    }
-
     Gfx9ChipSettings m_settings;
 
     CoordEq      m_cachedMetaEq[MaxCachedMetaEq];

src/amd/addrlib/inc/chip/gfx9/gfx9_gb_reg.h

@@ -2,7 +2,7 @@
 #define __GFX9_GB_REG_H__
 
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2017 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/inc/chip/r800/si_gb_reg.h

@@ -2,7 +2,7 @@
 #define __SI_GB_REG_H__
 
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/meson.build

@@ -19,33 +19,35 @@
 # SOFTWARE.
 
 files_addrlib = files(
-  'inc/addrinterface.h',
-  'inc/addrtypes.h',
-  'src/addrinterface.cpp',
-  'src/core/addrcommon.h',
-  'src/core/addrelemlib.cpp',
-  'src/core/addrelemlib.h',
-  'src/core/addrlib.cpp',
-  'src/core/addrlib.h',
-  'src/core/addrlib1.cpp',
-  'src/core/addrlib1.h',
-  'src/core/addrlib2.cpp',
-  'src/core/addrlib2.h',
-  'src/core/addrobject.cpp',
-  'src/core/addrobject.h',
-  'src/core/coord.cpp',
-  'src/core/coord.h',
-  'src/gfx9/gfx9addrlib.cpp',
-  'src/gfx9/gfx9addrlib.h',
-  'src/amdgpu_asic_addr.h',
-  'src/chip/gfx9/gfx9_gb_reg.h',
-  'src/chip/r800/si_gb_reg.h',
-  'src/r800/ciaddrlib.cpp',
-  'src/r800/ciaddrlib.h',
-  'src/r800/egbaddrlib.cpp',
-  'src/r800/egbaddrlib.h',
-  'src/r800/siaddrlib.cpp',
-  'src/r800/siaddrlib.h',
+  'addrinterface.cpp',
+  'addrinterface.h',
+  'addrtypes.h',
+  'core/addrcommon.h',
+  'core/addrelemlib.cpp',
+  'core/addrelemlib.h',
+  'core/addrlib.cpp',
+  'core/addrlib.h',
+  'core/addrlib1.cpp',
+  'core/addrlib1.h',
+  'core/addrlib2.cpp',
+  'core/addrlib2.h',
+  'core/addrobject.cpp',
+  'core/addrobject.h',
+  'gfx9/chip/gfx9_enum.h',
+  'gfx9/coord.cpp',
+  'gfx9/coord.h',
+  'gfx9/gfx9addrlib.cpp',
+  'gfx9/gfx9addrlib.h',
+  'amdgpu_asic_addr.h',
+  'inc/chip/gfx9/gfx9_gb_reg.h',
+  'inc/chip/r800/si_gb_reg.h',
+  'r800/chip/si_ci_vi_merged_enum.h',
+  'r800/ciaddrlib.cpp',
+  'r800/ciaddrlib.h',
+  'r800/egbaddrlib.cpp',
+  'r800/egbaddrlib.h',
+  'r800/siaddrlib.cpp',
+  'r800/siaddrlib.h',
 )
 
 libamdgpu_addrlib = static_library(
@@ -53,7 +55,7 @@ libamdgpu_addrlib = static_library(
   files_addrlib,
   include_directories : [
     include_directories(
-      'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
+      'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
     ),
     inc_amd_common, inc_common, inc_src,
   ],

src/amd/addrlib/r800/chip/si_ci_vi_merged_enum.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright © 2014 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+#if !defined (SI_CI_VI_MERGED_ENUM_HEADER)
+#define SI_CI_VI_MERGED_ENUM_HEADER
+
+typedef enum PipeInterleaveSize {
+ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
+ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
+} PipeInterleaveSize;
+
+typedef enum RowSize {
+ADDR_CONFIG_1KB_ROW                      = 0x00000000,
+ADDR_CONFIG_2KB_ROW                      = 0x00000001,
+ADDR_CONFIG_4KB_ROW                      = 0x00000002,
+} RowSize;
+
+#endif

src/amd/addrlib/r800/ciaddrlib.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -1038,6 +1038,7 @@ VOID CiLib::HwlOverrideTileMode(
         {
             switch (pInOut->format)
             {
+                // see //gfxip/gcB/devel/cds/src/verif/tc/models/csim/tcp.cpp
                 // tcpError("Thick micro tiling is not supported for format...
                 case ADDR_FMT_X24_8_32_FLOAT:
                 case ADDR_FMT_32_AS_8:
@@ -2032,6 +2033,7 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
     /// NOTE *2 because we are converting to Nibble address in this step
     UINT_64 metaAddressInPipe = blockInBankpipeWithBankBits * 2 * metadataBitSize / 8;
 
+
     ///--------------------------------------------------------------------------------------------
     /// Reinsert pipe bits back into the final address
     ///--------------------------------------------------------------------------------------------

src/amd/addrlib/r800/ciaddrlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -151,14 +151,12 @@ protected:
         UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
 
 private:
-
     VOID ReadGbTileMode(
         UINT_32 regValue, TileConfig* pCfg) const;
 
     VOID ReadGbMacroTileCfg(
         UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
 
-private:
     BOOL_32 InitTileSettingTable(
         const UINT_32 *pSetting, UINT_32 noOfEntries);
 
@@ -199,3 +197,5 @@ private:
 } // Addr
 
 #endif
+
+

src/amd/addrlib/r800/egbaddrlib.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -436,6 +436,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
                                                               &expPitch,
                                                               &expHeight);
 
+
     pOut->pitch = expPitch;
     pOut->height = expHeight;
     pOut->depth = expNumSlices;
@@ -447,6 +448,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
     return valid;
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::ComputeSurfaceInfoMacroTiled
@@ -753,6 +755,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
     return valid;
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::HwlReduceBankWidthHeight
@@ -1814,6 +1817,7 @@ UINT_64 EgBasedLib::ComputeSurfaceAddrFromCoordMacroTiled(
                                 tileSplitSlice,
                                 pTileInfo);
 
+
     //
     // Split the offset to put some bits below the pipe+bank bits and some above.
     //
@@ -2157,6 +2161,7 @@ VOID EgBasedLib::HwlComputePixelCoordFromOffset(
     *pSlice += z;
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::DispatchComputeSurfaceCoordFromAddrDispatch
@@ -2301,6 +2306,7 @@ VOID EgBasedLib::DispatchComputeSurfaceCoordFromAddr(
     }
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::ComputeSurfaceCoordFromAddrMacroTiled
@@ -2345,6 +2351,7 @@ VOID EgBasedLib::ComputeSurfaceCoordFromAddrMacroTiled(
     UINT_32 tileIndex;
     UINT_64 totalOffset;
 
+
     UINT_32 bank;
     UINT_32 pipe;
     UINT_32 groupBits = m_pipeInterleaveBytes << 3;
@@ -2666,6 +2673,7 @@ ADDR_E_RETURNCODE EgBasedLib::HwlExtractBankPipeSwizzle(
     return ADDR_OK;
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::HwlCombineBankPipeSwizzle
@@ -3035,6 +3043,7 @@ UINT_32 EgBasedLib::ComputeBankFromCoord(
             break;
     }
 
+
     //
     // Compute bank rotation for the tile split slice.
     //
@@ -3132,6 +3141,8 @@ UINT_32 EgBasedLib::ComputePipeRotation(
     return rotation;
 }
 
+
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::ComputeBankRotation
@@ -3174,6 +3185,7 @@ UINT_32 EgBasedLib::ComputeBankRotation(
     return rotation;
 }
 
+
 /**
 ****************************************************************************************************
 *   EgBasedLib::ComputeHtileBytes

src/amd/addrlib/r800/egbaddrlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/r800/siaddrlib.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining

src/amd/addrlib/r800/siaddrlib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2007-2018 Advanced Micro Devices, Inc.
+ * Copyright © 2014 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining
@@ -88,6 +88,7 @@ struct SiChipSettings
     UINT_32 isPolaris11       : 1;
     UINT_32 isPolaris12       : 1;
     UINT_32 isVegaM           : 1;
+    // VI fusion
     UINT_32 isCarrizo         : 1;
 };
 

src/amd/common/ac_debug.c

@@ -233,7 +233,6 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 		if (op == PKT3_SET_CONTEXT_REG ||
 		    op == PKT3_SET_CONFIG_REG ||
 		    op == PKT3_SET_UCONFIG_REG ||
-		    op == PKT3_SET_UCONFIG_REG_INDEX ||
 		    op == PKT3_SET_SH_REG)
 			fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
 				name, predicate);
@@ -253,7 +252,6 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 		ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib);
 		break;
 	case PKT3_SET_UCONFIG_REG:
-	case PKT3_SET_UCONFIG_REG_INDEX:
 		ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
 		break;
 	case PKT3_SET_SH_REG:

src/amd/common/ac_gpu_info.c

@@ -455,7 +455,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
-	assert(ib_align);
+       assert(ib_align);
 	info->ib_start_alignment = ib_align;
 
 	return true;

src/amd/common/ac_llvm_build.c

@@ -75,7 +75,7 @@ ac_llvm_context_init(struct ac_llvm_context *ctx,
 	ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
 	ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
 	ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
-	ctx->intptr = ctx->i32;
+	ctx->intptr = HAVE_32BIT_POINTERS ? ctx->i32 : ctx->i64;
 	ctx->f16 = LLVMHalfTypeInContext(ctx->context);
 	ctx->f32 = LLVMFloatTypeInContext(ctx->context);
 	ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
@@ -229,15 +229,6 @@ ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
 	return LLVMBuildBitCast(ctx->builder, v, ac_to_integer_type(ctx, type), "");
 }
 
-LLVMValueRef
-ac_to_integer_or_pointer(struct ac_llvm_context *ctx, LLVMValueRef v)
-{
-	LLVMTypeRef type = LLVMTypeOf(v);
-	if (LLVMGetTypeKind(type) == LLVMPointerTypeKind)
-		return v;
-	return ac_to_integer(ctx, v);
-}
-
 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
 {
 	if (t == ctx->i16 || t == ctx->f16)
@@ -954,14 +945,6 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
 				  ctx->f32, args, 4, AC_FUNC_ATTR_READNONE);
 }
 
-LLVMValueRef
-ac_build_gep_ptr(struct ac_llvm_context *ctx,
-	         LLVMValueRef base_ptr,
-	         LLVMValueRef index)
-{
-	return LLVMBuildGEP(ctx->builder, base_ptr, &index, 1, "");
-}
-
 LLVMValueRef
 ac_build_gep0(struct ac_llvm_context *ctx,
 	      LLVMValueRef base_ptr,
@@ -1209,47 +1192,6 @@ ac_build_buffer_load_common(struct ac_llvm_context *ctx,
 				  ac_get_load_intr_attribs(can_speculate));
 }
 
-static LLVMValueRef
-ac_build_llvm8_buffer_load_common(struct ac_llvm_context *ctx,
-				  LLVMValueRef rsrc,
-				  LLVMValueRef vindex,
-				  LLVMValueRef voffset,
-				  LLVMValueRef soffset,
-				  unsigned num_channels,
-				  bool glc,
-				  bool slc,
-				  bool can_speculate,
-				  bool use_format,
-				  bool structurized)
-{
-	LLVMValueRef args[5];
-	int idx = 0;
-	args[idx++] = LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, "");
-	if (structurized)
-		args[idx++] = vindex ? vindex : ctx->i32_0;
-	args[idx++] = voffset ? voffset : ctx->i32_0;
-	args[idx++] = soffset ? soffset : ctx->i32_0;
-	args[idx++] = LLVMConstInt(ctx->i32, (glc ? 1 : 0) + (slc ? 2 : 0), 0);
-	unsigned func = CLAMP(num_channels, 1, 3) - 1;
-
-	LLVMTypeRef types[] = {ctx->f32, ctx->v2f32, ctx->v4f32};
-	const char *type_names[] = {"f32", "v2f32", "v4f32"};
-	const char *indexing_kind = structurized ? "struct" : "raw";
-	char name[256];
-
-	if (use_format) {
-		snprintf(name, sizeof(name), "llvm.amdgcn.%s.buffer.load.format.%s",
-			 indexing_kind, type_names[func]);
-	} else {
-		snprintf(name, sizeof(name), "llvm.amdgcn.%s.buffer.load.%s",
-			 indexing_kind, type_names[func]);
-	}
-
-	return ac_build_intrinsic(ctx, name, types[func], args,
-				  idx,
-				  ac_get_load_intr_attribs(can_speculate));
-}
-
 LLVMValueRef
 ac_build_buffer_load(struct ac_llvm_context *ctx,
 		     LLVMValueRef rsrc,
@@ -1269,8 +1211,8 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 	if (soffset)
 		offset = LLVMBuildAdd(ctx->builder, offset, soffset, "");
 
-	if (allow_smem && !slc &&
-	    (!glc || (HAVE_LLVM >= 0x0800 && ctx->chip_class >= VI))) {
+	/* TODO: VI and later generations can use SMEM with GLC=1.*/
+	if (allow_smem && !glc && !slc) {
 		assert(vindex == NULL);
 
 		LLVMValueRef result[8];
@@ -1280,19 +1222,11 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 				offset = LLVMBuildAdd(ctx->builder, offset,
 						      LLVMConstInt(ctx->i32, 4, 0), "");
 			}
-			const char *intrname =
-				HAVE_LLVM >= 0x0800 ? "llvm.amdgcn.s.buffer.load.f32"
-						    : "llvm.SI.load.const.v4i32";
-			unsigned num_args = HAVE_LLVM >= 0x0800 ? 3 : 2;
-			LLVMValueRef args[3] = {
-				rsrc,
-				offset,
-				glc ? ctx->i32_1 : ctx->i32_0,
-			};
-			result[i] = ac_build_intrinsic(ctx, intrname,
-						       ctx->f32, args, num_args,
+			LLVMValueRef args[2] = {rsrc, offset};
+			result[i] = ac_build_intrinsic(ctx, "llvm.SI.load.const.v4i32",
+						       ctx->f32, args, 2,
 						       AC_FUNC_ATTR_READNONE |
-						       (HAVE_LLVM < 0x0800 ? AC_FUNC_ATTR_LEGACY : 0));
+						       AC_FUNC_ATTR_LEGACY);
 		}
 		if (num_channels == 1)
 			return result[0];
@@ -1315,11 +1249,6 @@ LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
 					 bool glc,
 					 bool can_speculate)
 {
-	if (HAVE_LLVM >= 0x800) {
-		return ac_build_llvm8_buffer_load_common(ctx, rsrc, vindex, voffset, ctx->i32_0,
-							 num_channels, glc, false,
-							 can_speculate, true, true);
-	}
 	return ac_build_buffer_load_common(ctx, rsrc, vindex, voffset,
 					   num_channels, glc, false,
 					   can_speculate, true);
@@ -1333,12 +1262,6 @@ LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
                                                   bool glc,
                                                   bool can_speculate)
 {
-	if (HAVE_LLVM >= 0x800) {
-		return ac_build_llvm8_buffer_load_common(ctx, rsrc, vindex, voffset, ctx->i32_0,
-							 num_channels, glc, false,
-							 can_speculate, true, true);
-	}
-
 	LLVMValueRef elem_count = LLVMBuildExtractElement(ctx->builder, rsrc, LLVMConstInt(ctx->i32, 2, 0), "");
 	LLVMValueRef stride = LLVMBuildExtractElement(ctx->builder, rsrc, ctx->i32_1, "");
 	stride = LLVMBuildLShr(ctx->builder, stride, LLVMConstInt(ctx->i32, 16, 0), "");
@@ -1450,28 +1373,99 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
 	      int idx,
 	      LLVMValueRef val)
 {
-	unsigned tl_lanes[4], trbl_lanes[4];
-	LLVMValueRef tl, trbl;
+	LLVMValueRef tl, trbl, args[2];
 	LLVMValueRef result;
 
-	for (unsigned i = 0; i < 4; ++i) {
-		tl_lanes[i] = i & mask;
-		trbl_lanes[i] = (i & mask) + idx;
-	}
+	if (HAVE_LLVM >= 0x0700) {
+		unsigned tl_lanes[4], trbl_lanes[4];
 
-	tl = ac_build_quad_swizzle(ctx, val,
-				   tl_lanes[0], tl_lanes[1],
-				   tl_lanes[2], tl_lanes[3]);
-	trbl = ac_build_quad_swizzle(ctx, val,
-				     trbl_lanes[0], trbl_lanes[1],
-				     trbl_lanes[2], trbl_lanes[3]);
+		for (unsigned i = 0; i < 4; ++i) {
+			tl_lanes[i] = i & mask;
+			trbl_lanes[i] = (i & mask) + idx;
+		}
+
+		tl = ac_build_quad_swizzle(ctx, val,
+		                           tl_lanes[0], tl_lanes[1],
+		                           tl_lanes[2], tl_lanes[3]);
+		trbl = ac_build_quad_swizzle(ctx, val,
+		                             trbl_lanes[0], trbl_lanes[1],
+		                             trbl_lanes[2], trbl_lanes[3]);
+	} else if (ctx->chip_class >= VI) {
+		LLVMValueRef thread_id, tl_tid, trbl_tid;
+		thread_id = ac_get_thread_id(ctx);
+
+		tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
+				      LLVMConstInt(ctx->i32, mask, false), "");
+
+		trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
+					LLVMConstInt(ctx->i32, idx, false), "");
+
+		args[0] = LLVMBuildMul(ctx->builder, tl_tid,
+				       LLVMConstInt(ctx->i32, 4, false), "");
+		args[1] = val;
+		tl = ac_build_intrinsic(ctx,
+					"llvm.amdgcn.ds.bpermute", ctx->i32,
+					args, 2,
+					AC_FUNC_ATTR_READNONE |
+					AC_FUNC_ATTR_CONVERGENT);
+
+		args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
+				       LLVMConstInt(ctx->i32, 4, false), "");
+		trbl = ac_build_intrinsic(ctx,
+					  "llvm.amdgcn.ds.bpermute", ctx->i32,
+					  args, 2,
+					  AC_FUNC_ATTR_READNONE |
+					  AC_FUNC_ATTR_CONVERGENT);
+	} else {
+		uint32_t masks[2] = {};
+
+		switch (mask) {
+		case AC_TID_MASK_TOP_LEFT:
+			masks[0] = 0x8000;
+			if (idx == 1)
+				masks[1] = 0x8055;
+			else
+				masks[1] = 0x80aa;
+
+			break;
+		case AC_TID_MASK_TOP:
+			masks[0] = 0x8044;
+			masks[1] = 0x80ee;
+			break;
+		case AC_TID_MASK_LEFT:
+			masks[0] = 0x80a0;
+			masks[1] = 0x80f5;
+			break;
+		default:
+			assert(0);
+		}
+
+		args[0] = val;
+		args[1] = LLVMConstInt(ctx->i32, masks[0], false);
+
+		tl = ac_build_intrinsic(ctx,
+					"llvm.amdgcn.ds.swizzle", ctx->i32,
+					args, 2,
+					AC_FUNC_ATTR_READNONE |
+					AC_FUNC_ATTR_CONVERGENT);
+
+		args[1] = LLVMConstInt(ctx->i32, masks[1], false);
+		trbl = ac_build_intrinsic(ctx,
+					"llvm.amdgcn.ds.swizzle", ctx->i32,
+					args, 2,
+					AC_FUNC_ATTR_READNONE |
+					AC_FUNC_ATTR_CONVERGENT);
+	}
 
 	tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
 	trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
 	result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
 
-	result = ac_build_intrinsic(ctx, "llvm.amdgcn.wqm.f32", ctx->f32,
-				    &result, 1, 0);
+	if (HAVE_LLVM >= 0x0700) {
+		result = ac_build_intrinsic(ctx,
+			"llvm.amdgcn.wqm.f32", ctx->f32,
+			&result, 1, 0);
+	}
 
 	return result;
 }
@@ -1716,6 +1710,171 @@ static const char *get_atomic_name(enum ac_atomic_op op)
 	unreachable("bad atomic op");
 }
 
+/* LLVM 6 and older */
+static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
+						struct ac_image_args *a)
+{
+	LLVMValueRef args[16];
+	LLVMTypeRef retty = ctx->v4f32;
+	const char *name = NULL;
+	const char *atomic_subop = "";
+	char intr_name[128], coords_type[64];
+
+	bool sample = a->opcode == ac_image_sample ||
+		      a->opcode == ac_image_gather4 ||
+		      a->opcode == ac_image_get_lod;
+	bool atomic = a->opcode == ac_image_atomic ||
+		      a->opcode == ac_image_atomic_cmpswap;
+	bool da = a->dim == ac_image_cube ||
+		  a->dim == ac_image_1darray ||
+		  a->dim == ac_image_2darray ||
+		  a->dim == ac_image_2darraymsaa;
+	if (a->opcode == ac_image_get_lod)
+		da = false;
+
+	unsigned num_coords =
+		a->opcode != ac_image_get_resinfo ? ac_num_coords(a->dim) : 0;
+	LLVMValueRef addr;
+	unsigned num_addr = 0;
+
+	if (a->opcode == ac_image_get_lod) {
+		switch (a->dim) {
+		case ac_image_1darray:
+			num_coords = 1;
+			break;
+		case ac_image_2darray:
+		case ac_image_cube:
+			num_coords = 2;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (a->offset)
+		args[num_addr++] = ac_to_integer(ctx, a->offset);
+	if (a->bias)
+		args[num_addr++] = ac_to_integer(ctx, a->bias);
+	if (a->compare)
+		args[num_addr++] = ac_to_integer(ctx, a->compare);
+	if (a->derivs[0]) {
+		unsigned num_derivs = ac_num_derivs(a->dim);
+		for (unsigned i = 0; i < num_derivs; ++i)
+			args[num_addr++] = ac_to_integer(ctx, a->derivs[i]);
+	}
+	for (unsigned i = 0; i < num_coords; ++i)
+		args[num_addr++] = ac_to_integer(ctx, a->coords[i]);
+	if (a->lod)
+		args[num_addr++] = ac_to_integer(ctx, a->lod);
+
+	unsigned pad_goal = util_next_power_of_two(num_addr);
+	while (num_addr < pad_goal)
+		args[num_addr++] = LLVMGetUndef(ctx->i32);
+
+	addr = ac_build_gather_values(ctx, args, num_addr);
+
+	unsigned num_args = 0;
+	if (atomic || a->opcode == ac_image_store || a->opcode == ac_image_store_mip) {
+		args[num_args++] = a->data[0];
+		if (a->opcode == ac_image_atomic_cmpswap)
+			args[num_args++] = a->data[1];
+	}
+
+	unsigned coords_arg = num_args;
+	if (sample)
+		args[num_args++] = ac_to_float(ctx, addr);
+	else
+		args[num_args++] = ac_to_integer(ctx, addr);
+
+	args[num_args++] = a->resource;
+	if (sample)
+		args[num_args++] = a->sampler;
+	if (!atomic) {
+		args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
+		if (sample)
+			args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
+		args[num_args++] = a->cache_policy & ac_glc ? ctx->i1true : ctx->i1false;
+		args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
+		args[num_args++] = ctx->i1false; /* lwe */
+		args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
+	} else {
+		args[num_args++] = ctx->i1false; /* r128 */
+		args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
+		args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
+	}
+
+	switch (a->opcode) {
+	case ac_image_sample:
+		name = "llvm.amdgcn.image.sample";
+		break;
+	case ac_image_gather4:
+		name = "llvm.amdgcn.image.gather4";
+		break;
+	case ac_image_load:
+		name = "llvm.amdgcn.image.load";
+		break;
+	case ac_image_load_mip:
+		name = "llvm.amdgcn.image.load.mip";
+		break;
+	case ac_image_store:
+		name = "llvm.amdgcn.image.store";
+		retty = ctx->voidt;
+		break;
+	case ac_image_store_mip:
+		name = "llvm.amdgcn.image.store.mip";
+		retty = ctx->voidt;
+		break;
+	case ac_image_atomic:
+	case ac_image_atomic_cmpswap:
+		name = "llvm.amdgcn.image.atomic.";
+		retty = ctx->i32;
+		if (a->opcode == ac_image_atomic_cmpswap) {
+			atomic_subop = "cmpswap";
+		} else {
+			atomic_subop = get_atomic_name(a->atomic);
+		}
+		break;
+	case ac_image_get_lod:
+		name = "llvm.amdgcn.image.getlod";
+		break;
+	case ac_image_get_resinfo:
+		name = "llvm.amdgcn.image.getresinfo";
+		break;
+	default:
+		unreachable("invalid image opcode");
+	}
+
+	ac_build_type_name_for_intr(LLVMTypeOf(args[coords_arg]), coords_type,
+				    sizeof(coords_type));
+
+	if (atomic) {
+		snprintf(intr_name, sizeof(intr_name), "llvm.amdgcn.image.atomic.%s.%s",
+			 atomic_subop, coords_type);
+	} else {
+		bool lod_suffix =
+			a->lod && (a->opcode == ac_image_sample || a->opcode == ac_image_gather4);
+
+		snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.v4f32.%s.v8i32",
+			name,
+			a->compare ? ".c" : "",
+			a->bias ? ".b" :
+			lod_suffix ? ".l" :
+			a->derivs[0] ? ".d" :
+			a->level_zero ? ".lz" : "",
+			a->offset ? ".o" : "",
+			coords_type);
+	}
+
+	LLVMValueRef result =
+		ac_build_intrinsic(ctx, intr_name, retty, args, num_args,
+				   a->attributes);
+	if (!sample && retty == ctx->v4f32) {
+		result = LLVMBuildBitCast(ctx->builder, result,
+					  ctx->v4i32, "");
+	}
+	return result;
+}
+
 LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 				   struct ac_image_args *a)
 {
@@ -1740,6 +1899,9 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
 	       (a->level_zero ? 1 : 0) +
 	       (a->derivs[0] ? 1 : 0) <= 1);
 
+	if (HAVE_LLVM < 0x0700)
+		return ac_build_image_opcode_llvm6(ctx, a);
+
 	if (a->opcode == ac_image_get_lod) {
 		switch (dim) {
 		case ac_image_1darray:
@@ -2528,6 +2690,9 @@ LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type)
 
 LLVMTypeRef ac_array_in_const32_addr_space(LLVMTypeRef elem_type)
 {
+	if (!HAVE_32BIT_POINTERS)
+		return ac_array_in_const_addr_space(elem_type);
+
 	return LLVMPointerType(LLVMArrayType(elem_type, 0),
 			       AC_ADDR_SPACE_CONST_32BIT);
 }
@@ -2673,7 +2838,8 @@ void ac_build_endloop(struct ac_llvm_context *ctx, int label_id)
 	ctx->flow_depth--;
 }
 
-void ac_build_ifcc(struct ac_llvm_context *ctx, LLVMValueRef cond, int label_id)
+static void if_cond_emit(struct ac_llvm_context *ctx, LLVMValueRef cond,
+			 int label_id)
 {
 	struct ac_llvm_flow *flow = push_flow(ctx);
 	LLVMBasicBlockRef if_block;
@@ -2690,7 +2856,7 @@ void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
 {
 	LLVMValueRef cond = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
 					  value, ctx->f32_0, "");
-	ac_build_ifcc(ctx, cond, label_id);
+	if_cond_emit(ctx, cond, label_id);
 }
 
 void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
@@ -2699,7 +2865,7 @@ void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
 	LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
 					  ac_to_integer(ctx, value),
 					  ctx->i32_0, "");
-	ac_build_ifcc(ctx, cond, label_id);
+	if_cond_emit(ctx, cond, label_id);
 }
 
 LLVMValueRef ac_build_alloca_undef(struct ac_llvm_context *ac, LLVMTypeRef type,
@@ -3159,44 +3325,24 @@ ac_build_alu_op(struct ac_llvm_context *ctx, LLVMValueRef lhs, LLVMValueRef rhs,
 	}
 }
 
-/**
- * \param maxprefix specifies that the result only needs to be correct for a
- *     prefix of this many threads
- *
- * TODO: add inclusive and excluse scan functions for SI chip class.
- */
+/* TODO: add inclusive and excluse scan functions for SI chip class.  */
 static LLVMValueRef
-ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValueRef identity,
-	      unsigned maxprefix)
+ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValueRef identity)
 {
 	LLVMValueRef result, tmp;
 	result = src;
-	if (maxprefix <= 1)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(1), 0xf, 0xf, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 2)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(2), 0xf, 0xf, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 3)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(3), 0xf, 0xf, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 4)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, result, dpp_row_sr(4), 0xf, 0xe, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 8)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, result, dpp_row_sr(8), 0xf, 0xc, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 16)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, result, dpp_row_bcast15, 0xa, 0xf, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
-	if (maxprefix <= 32)
-		return result;
 	tmp = ac_build_dpp(ctx, identity, result, dpp_row_bcast31, 0xc, 0xf, false);
 	result = ac_build_alu_op(ctx, result, tmp, op);
 	return result;
@@ -3205,24 +3351,14 @@ ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValu
 LLVMValueRef
 ac_build_inclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op)
 {
-	LLVMValueRef result;
-
-	if (LLVMTypeOf(src) == ctx->i1 && op == nir_op_iadd) {
-		LLVMBuilderRef builder = ctx->builder;
-		src = LLVMBuildZExt(builder, src, ctx->i32, "");
-		result = ac_build_ballot(ctx, src);
-		result = ac_build_mbcnt(ctx, result);
-		result = LLVMBuildAdd(builder, result, src, "");
-		return result;
-	}
-
 	ac_build_optimization_barrier(ctx, &src);
-
-	LLVMValueRef identity =
-		get_reduction_identity(ctx, op, ac_get_type_size(LLVMTypeOf(src)));
-	result = LLVMBuildBitCast(ctx->builder, ac_build_set_inactive(ctx, src, identity),
-				  LLVMTypeOf(identity), "");
-	result = ac_build_scan(ctx, op, result, identity, 64);
+	LLVMValueRef result;
+	LLVMValueRef identity = get_reduction_identity(ctx, op,
+								ac_get_type_size(LLVMTypeOf(src)));
+	result = LLVMBuildBitCast(ctx->builder,
+								ac_build_set_inactive(ctx, src, identity),
+								LLVMTypeOf(identity), "");
+	result = ac_build_scan(ctx, op, result, identity);
 
 	return ac_build_wwm(ctx, result);
 }
@@ -3230,24 +3366,15 @@ ac_build_inclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op
 LLVMValueRef
 ac_build_exclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op)
 {
-	LLVMValueRef result;
-
-	if (LLVMTypeOf(src) == ctx->i1 && op == nir_op_iadd) {
-		LLVMBuilderRef builder = ctx->builder;
-		src = LLVMBuildZExt(builder, src, ctx->i32, "");
-		result = ac_build_ballot(ctx, src);
-		result = ac_build_mbcnt(ctx, result);
-		return result;
-	}
-
 	ac_build_optimization_barrier(ctx, &src);
-
-	LLVMValueRef identity =
-		get_reduction_identity(ctx, op, ac_get_type_size(LLVMTypeOf(src)));
-	result = LLVMBuildBitCast(ctx->builder, ac_build_set_inactive(ctx, src, identity),
-				  LLVMTypeOf(identity), "");
+	LLVMValueRef result;
+	LLVMValueRef identity = get_reduction_identity(ctx, op,
+								ac_get_type_size(LLVMTypeOf(src)));
+	result = LLVMBuildBitCast(ctx->builder,
+								ac_build_set_inactive(ctx, src, identity),
+								LLVMTypeOf(identity), "");
 	result = ac_build_dpp(ctx, identity, result, dpp_wf_sr1, 0xf, 0xf, false);
-	result = ac_build_scan(ctx, op, result, identity, 64);
+	result = ac_build_scan(ctx, op, result, identity);
 
 	return ac_build_wwm(ctx, result);
 }
@@ -3305,175 +3432,6 @@ ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op, unsign
 	}
 }
 
-/**
- * "Top half" of a scan that reduces per-wave values across an entire
- * workgroup.
- *
- * The source value must be present in the highest lane of the wave, and the
- * highest lane must be live.
- */
-void
-ac_build_wg_wavescan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	if (ws->maxwaves <= 1)
-		return;
-
-	const LLVMValueRef i32_63 = LLVMConstInt(ctx->i32, 63, false);
-	LLVMBuilderRef builder = ctx->builder;
-	LLVMValueRef tid = ac_get_thread_id(ctx);
-	LLVMValueRef tmp;
-
-	tmp = LLVMBuildICmp(builder, LLVMIntEQ, tid, i32_63, "");
-	ac_build_ifcc(ctx, tmp, 1000);
-	LLVMBuildStore(builder, ws->src, LLVMBuildGEP(builder, ws->scratch, &ws->waveidx, 1, ""));
-	ac_build_endif(ctx, 1000);
-}
-
-/**
- * "Bottom half" of a scan that reduces per-wave values across an entire
- * workgroup.
- *
- * The caller must place a barrier between the top and bottom halves.
- */
-void
-ac_build_wg_wavescan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	const LLVMTypeRef type = LLVMTypeOf(ws->src);
-	const LLVMValueRef identity =
-		get_reduction_identity(ctx, ws->op, ac_get_type_size(type));
-
-	if (ws->maxwaves <= 1) {
-		ws->result_reduce = ws->src;
-		ws->result_inclusive = ws->src;
-		ws->result_exclusive = identity;
-		return;
-	}
-	assert(ws->maxwaves <= 32);
-
-	LLVMBuilderRef builder = ctx->builder;
-	LLVMValueRef tid = ac_get_thread_id(ctx);
-	LLVMBasicBlockRef bbs[2];
-	LLVMValueRef phivalues_scan[2];
-	LLVMValueRef tmp, tmp2;
-
-	bbs[0] = LLVMGetInsertBlock(builder);
-	phivalues_scan[0] = LLVMGetUndef(type);
-
-	if (ws->enable_reduce)
-		tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, ws->numwaves, "");
-	else if (ws->enable_inclusive)
-		tmp = LLVMBuildICmp(builder, LLVMIntULE, tid, ws->waveidx, "");
-	else
-		tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, ws->waveidx, "");
-	ac_build_ifcc(ctx, tmp, 1001);
-	{
-		tmp = LLVMBuildLoad(builder, LLVMBuildGEP(builder, ws->scratch, &tid, 1, ""), "");
-
-		ac_build_optimization_barrier(ctx, &tmp);
-
-		bbs[1] = LLVMGetInsertBlock(builder);
-		phivalues_scan[1] = ac_build_scan(ctx, ws->op, tmp, identity, ws->maxwaves);
-	}
-	ac_build_endif(ctx, 1001);
-
-	const LLVMValueRef scan = ac_build_phi(ctx, type, 2, phivalues_scan, bbs);
-
-	if (ws->enable_reduce) {
-		tmp = LLVMBuildSub(builder, ws->numwaves, ctx->i32_1, "");
-		ws->result_reduce = ac_build_readlane(ctx, scan, tmp);
-	}
-	if (ws->enable_inclusive)
-		ws->result_inclusive = ac_build_readlane(ctx, scan, ws->waveidx);
-	if (ws->enable_exclusive) {
-		tmp = LLVMBuildSub(builder, ws->waveidx, ctx->i32_1, "");
-		tmp = ac_build_readlane(ctx, scan, tmp);
-		tmp2 = LLVMBuildICmp(builder, LLVMIntEQ, ws->waveidx, ctx->i32_0, "");
-		ws->result_exclusive = LLVMBuildSelect(builder, tmp2, identity, tmp, "");
-	}
-}
-
-/**
- * Inclusive scan of a per-wave value across an entire workgroup.
- *
- * This implies an s_barrier instruction.
- *
- * Unlike ac_build_inclusive_scan, the caller \em must ensure that all threads
- * of the workgroup are live. (This requirement cannot easily be relaxed in a
- * useful manner because of the barrier in the algorithm.)
- */
-void
-ac_build_wg_wavescan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	ac_build_wg_wavescan_top(ctx, ws);
-	ac_build_s_barrier(ctx);
-	ac_build_wg_wavescan_bottom(ctx, ws);
-}
-
-/**
- * "Top half" of a scan that reduces per-thread values across an entire
- * workgroup.
- *
- * All lanes must be active when this code runs.
- */
-void
-ac_build_wg_scan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	if (ws->enable_exclusive) {
-		ws->extra = ac_build_exclusive_scan(ctx, ws->src, ws->op);
-		if (LLVMTypeOf(ws->src) == ctx->i1 && ws->op == nir_op_iadd)
-			ws->src = LLVMBuildZExt(ctx->builder, ws->src, ctx->i32, "");
-		ws->src = ac_build_alu_op(ctx, ws->extra, ws->src, ws->op);
-	} else {
-		ws->src = ac_build_inclusive_scan(ctx, ws->src, ws->op);
-	}
-
-	bool enable_inclusive = ws->enable_inclusive;
-	bool enable_exclusive = ws->enable_exclusive;
-	ws->enable_inclusive = false;
-	ws->enable_exclusive = ws->enable_exclusive || enable_inclusive;
-	ac_build_wg_wavescan_top(ctx, ws);
-	ws->enable_inclusive = enable_inclusive;
-	ws->enable_exclusive = enable_exclusive;
-}
-
-/**
- * "Bottom half" of a scan that reduces per-thread values across an entire
- * workgroup.
- *
- * The caller must place a barrier between the top and bottom halves.
- */
-void
-ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	bool enable_inclusive = ws->enable_inclusive;
-	bool enable_exclusive = ws->enable_exclusive;
-	ws->enable_inclusive = false;
-	ws->enable_exclusive = ws->enable_exclusive || enable_inclusive;
-	ac_build_wg_wavescan_bottom(ctx, ws);
-	ws->enable_inclusive = enable_inclusive;
-	ws->enable_exclusive = enable_exclusive;
-
-	/* ws->result_reduce is already the correct value */
-	if (ws->enable_inclusive)
-		ws->result_inclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->src, ws->op);
-	if (ws->enable_exclusive)
-		ws->result_exclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->extra, ws->op);
-}
-
-/**
- * A scan that reduces per-thread values across an entire workgroup.
- *
- * The caller must ensure that all lanes are active when this code runs
- * (WWM is insufficient!), because there is an implied barrier.
- */
-void
-ac_build_wg_scan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
-{
-	ac_build_wg_scan_top(ctx, ws);
-	ac_build_s_barrier(ctx);
-	ac_build_wg_scan_bottom(ctx, ws);
-}
-
 LLVMValueRef
 ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src,
 		unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)

src/amd/common/ac_llvm_build.h

@@ -34,12 +34,14 @@
 extern "C" {
 #endif
 
+#define HAVE_32BIT_POINTERS (HAVE_LLVM >= 0x0700)
+
 enum {
-	AC_ADDR_SPACE_FLAT = 0, /* Slower than global. */
+	AC_ADDR_SPACE_FLAT = HAVE_LLVM >= 0x0700 ? 0 : 4, /* Slower than global. */
 	AC_ADDR_SPACE_GLOBAL = 1,
-	AC_ADDR_SPACE_GDS = 2,
+	AC_ADDR_SPACE_GDS = HAVE_LLVM >= 0x0700 ? 2 : 5,
 	AC_ADDR_SPACE_LDS = 3,
-	AC_ADDR_SPACE_CONST = 4, /* Global allowing SMEM. */
+	AC_ADDR_SPACE_CONST = HAVE_LLVM >= 0x0700 ? 4 : 2, /* Global allowing SMEM. */
 	AC_ADDR_SPACE_CONST_32BIT = 6, /* same as CONST, but the pointer type has 32 bits */
 };
 
@@ -126,7 +128,6 @@ unsigned ac_get_type_size(LLVMTypeRef type);
 
 LLVMTypeRef ac_to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
 LLVMValueRef ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v);
-LLVMValueRef ac_to_integer_or_pointer(struct ac_llvm_context *ctx, LLVMValueRef v);
 LLVMTypeRef ac_to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
 LLVMValueRef ac_to_float(struct ac_llvm_context *ctx, LLVMValueRef v);
 
@@ -231,11 +232,6 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
 		       LLVMValueRef attr_number,
 		       LLVMValueRef params);
 
-LLVMValueRef
-ac_build_gep_ptr(struct ac_llvm_context *ctx,
-	         LLVMValueRef base_ptr,
-	         LLVMValueRef index);
-
 LLVMValueRef
 ac_build_gep0(struct ac_llvm_context *ctx,
 	      LLVMValueRef base_ptr,
@@ -493,7 +489,6 @@ void ac_build_continue(struct ac_llvm_context *ctx);
 void ac_build_else(struct ac_llvm_context *ctx, int lable_id);
 void ac_build_endif(struct ac_llvm_context *ctx, int lable_id);
 void ac_build_endloop(struct ac_llvm_context *ctx, int lable_id);
-void ac_build_ifcc(struct ac_llvm_context *ctx, LLVMValueRef cond, int label_id);
 void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
 		 int lable_id);
 void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
@@ -537,42 +532,6 @@ ac_build_exclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op
 LLVMValueRef
 ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op, unsigned cluster_size);
 
-/**
- * Common arguments for a scan/reduce operation that accumulates per-wave
- * values across an entire workgroup, while respecting the order of waves.
- */
-struct ac_wg_scan {
-	bool enable_reduce;
-	bool enable_exclusive;
-	bool enable_inclusive;
-	nir_op op;
-	LLVMValueRef src; /* clobbered! */
-	LLVMValueRef result_reduce;
-	LLVMValueRef result_exclusive;
-	LLVMValueRef result_inclusive;
-	LLVMValueRef extra;
-	LLVMValueRef waveidx;
-	LLVMValueRef numwaves; /* only needed for "reduce" operations */
-
-	/* T addrspace(LDS) pointer to the same type as value, at least maxwaves entries */
-	LLVMValueRef scratch;
-	unsigned maxwaves;
-};
-
-void
-ac_build_wg_wavescan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-void
-ac_build_wg_wavescan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-void
-ac_build_wg_wavescan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-
-void
-ac_build_wg_scan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-void
-ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-void
-ac_build_wg_scan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
-
 LLVMValueRef
 ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src,
 		unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3);

src/amd/common/ac_llvm_helper.cpp

@@ -39,6 +39,9 @@
 #include <llvm/Transforms/IPO.h>
 
 #include <llvm/IR/LegacyPassManager.h>
+#if HAVE_LLVM < 0x0700
+#include "llvm/Support/raw_ostream.h"
+#endif
 
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)
 {
@@ -129,7 +132,9 @@ struct ac_compiler_passes *ac_create_llvm_passes(LLVMTargetMachineRef tm)
 	llvm::TargetMachine *TM = reinterpret_cast<llvm::TargetMachine*>(tm);
 
 	if (TM->addPassesToEmitFile(p->passmgr, p->ostream,
+#if HAVE_LLVM >= 0x0700
 				    nullptr,
+#endif
 				    llvm::TargetMachine::CGFT_ObjectFile)) {
 		fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n");
 		delete p;
@@ -165,5 +170,7 @@ void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr)
 
 void ac_enable_global_isel(LLVMTargetMachineRef tm)
 {
+#if HAVE_LLVM >= 0x0700
   reinterpret_cast<llvm::TargetMachine*>(tm)->setGlobalISel(true);
+#endif
 }

src/amd/common/ac_llvm_util.c

@@ -30,7 +30,9 @@
 #include <llvm-c/Support.h>
 #include <llvm-c/Transforms/IPO.h>
 #include <llvm-c/Transforms/Scalar.h>
+#if HAVE_LLVM >= 0x0700
 #include <llvm-c/Transforms/Utils.h>
+#endif
 #include "c11/threads.h"
 #include "gallivm/lp_bld_misc.h"
 #include "util/u_math.h"
@@ -130,11 +132,11 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
 	case CHIP_RAVEN:
 		return "gfx902";
 	case CHIP_VEGA12:
-		return "gfx904";
+		return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
 	case CHIP_VEGA20:
-		return "gfx906";
+		return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
 	case CHIP_RAVEN2:
-		return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
+		return "gfx902"; /* TODO: use gfx909 when it's available */
 	default:
 		return "";
 	}
@@ -151,8 +153,7 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
 	LLVMTargetRef target = ac_get_llvm_target(triple);
 
 	snprintf(features, sizeof(features),
-		 "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
-		 HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
+		 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
 		 tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
 		 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 		 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
@@ -301,6 +302,7 @@ ac_count_scratch_private_memory(LLVMValueRef function)
 
 bool
 ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
+		      bool okay_to_leak_target_library_info,
 		      enum radeon_family family,
 		      enum ac_target_machine_options tm_options)
 {
@@ -321,10 +323,12 @@ ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
 			goto fail;
 	}
 
-	compiler->target_library_info =
-		ac_create_target_library_info(triple);
-	if (!compiler->target_library_info)
-		goto fail;
+	if (okay_to_leak_target_library_info || (HAVE_LLVM >= 0x0700)) {
+		compiler->target_library_info =
+			ac_create_target_library_info(triple);
+		if (!compiler->target_library_info)
+			goto fail;
+	}
 
 	compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
 					      tm_options & AC_TM_CHECK_IR);
@@ -342,8 +346,11 @@ ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
 {
 	if (compiler->passmgr)
 		LLVMDisposePassManager(compiler->passmgr);
+#if HAVE_LLVM >= 0x0700
+	/* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
 	if (compiler->target_library_info)
 		ac_dispose_target_library_info(compiler->target_library_info);
+#endif
 	if (compiler->low_opt_tm)
 		LLVMDisposeTargetMachine(compiler->low_opt_tm);
 	if (compiler->tm)

src/amd/common/ac_llvm_util.h

@@ -134,6 +134,7 @@ void ac_init_llvm_once(void);
 
 
 bool ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
+			   bool okay_to_leak_target_library_info,
 			   enum radeon_family family,
 			   enum ac_target_machine_options tm_options);
 void ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler);

src/amd/common/ac_nir_to_llvm.c

@@ -270,9 +270,8 @@ static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
 {
 	LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
 				       ctx->i32_0, "");
-	return LLVMBuildSelect(ctx->builder, v,
-			       ac_to_integer_or_pointer(ctx, src1),
-			       ac_to_integer_or_pointer(ctx, src2), "");
+	return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
+			       ac_to_integer(ctx, src2), "");
 }
 
 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
@@ -429,12 +428,12 @@ static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
 {
 	LLVMValueRef result;
 
-	if (HAVE_LLVM >= 0x0800) {
+	if (HAVE_LLVM < 0x0700) {
 		LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
 		result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
 		result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
 	} else {
-		/* FIXME: LLVM 7+ returns incorrect result when count is 0.
+		/* FIXME: LLVM 7 returns incorrect result when count is 0.
 		 * https://bugs.freedesktop.org/show_bug.cgi?id=107276
 		 */
 		LLVMValueRef zero = ctx->i32_0;
@@ -687,34 +686,34 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
 						     LLVMTypeOf(src[0]), ""),
 				       "");
 		break;
-	case nir_op_ilt32:
+	case nir_op_ilt:
 		result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
 		break;
-	case nir_op_ine32:
+	case nir_op_ine:
 		result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
 		break;
-	case nir_op_ieq32:
+	case nir_op_ieq:
 		result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
 		break;
-	case nir_op_ige32:
+	case nir_op_ige:
 		result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
 		break;
-	case nir_op_ult32:
+	case nir_op_ult:
 		result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
 		break;
-	case nir_op_uge32:
+	case nir_op_uge:
 		result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
 		break;
-	case nir_op_feq32:
+	case nir_op_feq:
 		result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
 		break;
-	case nir_op_fne32:
+	case nir_op_fne:
 		result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
 		break;
-	case nir_op_flt32:
+	case nir_op_flt:
 		result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
 		break;
-	case nir_op_fge32:
+	case nir_op_fge:
 		result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
 		break;
 	case nir_op_fabs:
@@ -916,7 +915,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
 		else
 			result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
 		break;
-	case nir_op_b32csel:
+	case nir_op_bcsel:
 		result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
 		break;
 	case nir_op_find_lsb:
@@ -941,20 +940,16 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
 		src[1] = ac_to_integer(&ctx->ac, src[1]);
 		result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
 		break;
-	case nir_op_b2f16:
-	case nir_op_b2f32:
-	case nir_op_b2f64:
+	case nir_op_b2f:
 		result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
 		break;
-	case nir_op_f2b32:
+	case nir_op_f2b:
 		result = emit_f2b(&ctx->ac, src[0]);
 		break;
-	case nir_op_b2i16:
-	case nir_op_b2i32:
-	case nir_op_b2i64:
+	case nir_op_b2i:
 		result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
 		break;
-	case nir_op_i2b32:
+	case nir_op_i2b:
 		src[0] = ac_to_integer(&ctx->ac, src[0]);
 		result = emit_i2b(&ctx->ac, src[0]);
 		break;
@@ -1100,7 +1095,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
 
 	if (result) {
 		assert(instr->dest.dest.is_ssa);
-		result = ac_to_integer_or_pointer(&ctx->ac, result);
+		result = ac_to_integer(&ctx->ac, result);
 		ctx->ssa_defs[instr->dest.dest.ssa.index] = result;
 	}
 }
@@ -1463,30 +1458,6 @@ static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueR
 	}
 }
 
-static unsigned get_cache_policy(struct ac_nir_context *ctx,
-				 enum gl_access_qualifier access,
-				 bool may_store_unaligned,
-				 bool writeonly_memory)
-{
-	unsigned cache_policy = 0;
-
-	/* SI has a TC L1 bug causing corruption of 8bit/16bit stores.  All
-	 * store opcodes not aligned to a dword are affected. The only way to
-	 * get unaligned stores is through shader images.
-	 */
-	if (((may_store_unaligned && ctx->ac.chip_class == SI) ||
-	     /* If this is write-only, don't keep data in L1 to prevent
-	      * evicting L1 cache lines that may be needed by other
-	      * instructions.
-	      */
-	     writeonly_memory ||
-	     access & (ACCESS_COHERENT | ACCESS_VOLATILE))) {
-		cache_policy |= ac_glc;
-	}
-
-	return cache_policy;
-}
-
 static void visit_store_ssbo(struct ac_nir_context *ctx,
                              nir_intrinsic_instr *instr)
 {
@@ -1495,9 +1466,10 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
 	int elem_size_bytes = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 8;
 	unsigned writemask = nir_intrinsic_write_mask(instr);
 	enum gl_access_qualifier access = nir_intrinsic_access(instr);
-	bool writeonly_memory = access & ACCESS_NON_READABLE;
-	unsigned cache_policy = get_cache_policy(ctx, access, false, writeonly_memory);
-	LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
+	LLVMValueRef glc = ctx->ac.i1false;
+
+	if (access & (ACCESS_VOLATILE | ACCESS_COHERENT))
+		glc = ctx->ac.i1true;
 
 	LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
 				        get_src(ctx, instr->src[1]), true);
@@ -1653,8 +1625,10 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
 	int elem_size_bytes = instr->dest.ssa.bit_size / 8;
 	int num_components = instr->num_components;
 	enum gl_access_qualifier access = nir_intrinsic_access(instr);
-	unsigned cache_policy = get_cache_policy(ctx, access, false, false);
-	LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
+	LLVMValueRef glc = ctx->ac.i1false;
+
+	if (access & (ACCESS_VOLATILE | ACCESS_COHERENT))
+		glc = ctx->ac.i1true;
 
 	LLVMValueRef offset = get_src(ctx, instr->src[1]);
 	LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
@@ -1667,7 +1641,7 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
 	LLVMValueRef results[4];
 	for (int i = 0; i < num_components;) {
 		int num_elems = num_components - i;
-		if (elem_size_bytes < 4 && nir_intrinsic_align(instr) % 4 != 0)
+		if (elem_size_bytes < 4)
 			num_elems = 1;
 		if (num_elems * elem_size_bytes > 16)
 			num_elems = 16 / elem_size_bytes;
@@ -1884,36 +1858,23 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
 	nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 
 	LLVMValueRef values[8];
-	int idx = 0;
+	int idx = var->data.driver_location;
 	int ve = instr->dest.ssa.num_components;
-	unsigned comp = 0;
+	unsigned comp = var->data.location_frac;
 	LLVMValueRef indir_index;
 	LLVMValueRef ret;
 	unsigned const_index;
-	unsigned stride = 4;
-	int mode = nir_var_mem_shared;
-	
-	if (var) {
-		bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
-			var->data.mode == nir_var_shader_in;
-		idx = var->data.driver_location;
-		comp = var->data.location_frac;
-		mode = var->data.mode;
+	unsigned stride = var->data.compact ? 1 : 4;
+	bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
+	             var->data.mode == nir_var_shader_in;
 
-		get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), vs_in, NULL, NULL,
-				 &const_index, &indir_index);
-
-		if (var->data.compact) {
-			stride = 1;
-			const_index += comp;
-			comp = 0;
-		}
-	}
+	get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), vs_in, NULL, NULL,
+	                 &const_index, &indir_index);
 
 	if (instr->dest.ssa.bit_size == 64)
 		ve *= 2;
 
-	switch (mode) {
+	switch (var->data.mode) {
 	case nir_var_shader_in:
 		if (ctx->stage == MESA_SHADER_TESS_CTRL ||
 		    ctx->stage == MESA_SHADER_TESS_EVAL) {
@@ -1950,7 +1911,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
 				values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
 		}
 		break;
-	case nir_var_function_temp:
+	case nir_var_local:
 		for (unsigned chan = 0; chan < ve; chan++) {
 			if (indir_index) {
 				unsigned count = glsl_count_attribute_slots(
@@ -1968,7 +1929,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
 			}
 		}
 		break;
-	case nir_var_mem_shared: {
+	case nir_var_shared: {
 		LLVMValueRef address = get_src(ctx, instr->src[0]);
 		LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
 		return LLVMBuildBitCast(ctx->ac.builder, val,
@@ -2010,28 +1971,18 @@ static void
 visit_store_var(struct ac_nir_context *ctx,
 		nir_intrinsic_instr *instr)
 {
-	nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
-	nir_variable *var = nir_deref_instr_get_variable(deref);
+        nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 
 	LLVMValueRef temp_ptr, value;
-	int idx = 0;
-	unsigned comp = 0;
+	int idx = var->data.driver_location;
+	unsigned comp = var->data.location_frac;
 	LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[1]));
 	int writemask = instr->const_index[0];
 	LLVMValueRef indir_index;
 	unsigned const_index;
 
-	if (var) {
-		get_deref_offset(ctx, deref, false,
-		                 NULL, NULL, &const_index, &indir_index);
-		idx = var->data.driver_location;
-		comp = var->data.location_frac;
-
-		if (var->data.compact) {
-			const_index += comp;
-			comp = 0;
-		}
-	}
+	get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), false,
+	                 NULL, NULL, &const_index, &indir_index);
 
 	if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
 
@@ -2044,7 +1995,7 @@ visit_store_var(struct ac_nir_context *ctx,
 
 	writemask = writemask << comp;
 
-	switch (deref->mode) {
+	switch (var->data.mode) {
 	case nir_var_shader_out:
 
 		if (ctx->stage == MESA_SHADER_TESS_CTRL) {
@@ -2053,8 +2004,8 @@ visit_store_var(struct ac_nir_context *ctx,
 			unsigned const_index = 0;
 			const bool is_patch = var->data.patch;
 
-			get_deref_offset(ctx, deref, false, NULL,
-			                 is_patch ? NULL : &vertex_index,
+			get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr),
+			                 false, NULL, is_patch ? NULL : &vertex_index,
 			                 &const_index, &indir_index);
 
 			ctx->abi->store_tcs_outputs(ctx->abi, var,
@@ -2092,7 +2043,7 @@ visit_store_var(struct ac_nir_context *ctx,
 			}
 		}
 		break;
-	case nir_var_function_temp:
+	case nir_var_local:
 		for (unsigned chan = 0; chan < 8; chan++) {
 			if (!(writemask & (1 << chan)))
 				continue;
@@ -2117,7 +2068,7 @@ visit_store_var(struct ac_nir_context *ctx,
 			}
 		}
 		break;
-	case nir_var_mem_shared: {
+	case nir_var_shared: {
 		int writemask = instr->const_index[0];
 		LLVMValueRef address = get_src(ctx, instr->src[0]);
 		LLVMValueRef val = get_src(ctx, instr->src[1]);
@@ -2247,10 +2198,10 @@ static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
 	return sample_index;
 }
 
-static nir_deref_instr *get_image_deref(const nir_intrinsic_instr *instr)
+static nir_variable *get_image_variable(const nir_intrinsic_instr *instr)
 {
 	assert(instr->src[0].is_ssa);
-	return nir_instr_as_deref(instr->src[0].ssa->parent_instr);
+	return nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 }
 
 static LLVMValueRef get_image_descriptor(struct ac_nir_context *ctx,
@@ -2265,7 +2216,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
 			     const nir_intrinsic_instr *instr,
 			     struct ac_image_args *args)
 {
-	const struct glsl_type *type = get_image_deref(instr)->type;
+	const struct glsl_type *type = glsl_without_array(get_image_variable(instr)->type);
 
 	LLVMValueRef src0 = get_src(ctx, instr->src[1]);
 	LLVMValueRef masks[] = {
@@ -2284,7 +2235,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
 	bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
 	count = image_type_to_components_count(dim, is_array);
 
-	if (is_ms && instr->intrinsic == nir_intrinsic_image_deref_load) {
+	if (is_ms) {
 		LLVMValueRef fmask_load_address[3];
 		int chan;
 
@@ -2374,13 +2325,10 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
 				     const nir_intrinsic_instr *instr)
 {
 	LLVMValueRef res;
-	const nir_deref_instr *image_deref = get_image_deref(instr);
-	const struct glsl_type *type = image_deref->type;
-	const nir_variable *var = nir_deref_instr_get_variable(image_deref);
-	struct ac_image_args args = {};
+	const nir_variable *var = get_image_variable(instr);
+	const struct glsl_type *type = var->type;
 
-	args.cache_policy =
-		get_cache_policy(ctx, var->data.image.access, false, false);
+	type = glsl_without_array(type);
 
 	const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 	if (dim == GLSL_SAMPLER_DIM_BUF) {
@@ -2392,16 +2340,16 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
 		vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
 						 ctx->ac.i32_0, "");
 
-		/* TODO: set "can_speculate" when OpenGL needs it. */
+		/* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
 		res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
 						  ctx->ac.i32_0, num_channels,
-						  !!(args.cache_policy & ac_glc),
-						  false);
+						  false, false);
 		res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
 
 		res = ac_trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
 		res = ac_to_integer(&ctx->ac, res);
 	} else {
+		struct ac_image_args args = {};
 		args.opcode = ac_image_load;
 		get_image_coords(ctx, instr, &args);
 		args.resource = get_image_descriptor(ctx, instr, AC_DESC_IMAGE, false);
@@ -2409,6 +2357,8 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
 					    glsl_sampler_type_is_array(type));
 		args.dmask = 15;
 		args.attributes = AC_FUNC_ATTR_READONLY;
+		if (var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT))
+			args.cache_policy |= ac_glc;
 
 		res = ac_build_image_opcode(&ctx->ac, &args);
 	}
@@ -2419,15 +2369,13 @@ static void visit_image_store(struct ac_nir_context *ctx,
 			      nir_intrinsic_instr *instr)
 {
 	LLVMValueRef params[8];
-	const nir_deref_instr *image_deref = get_image_deref(instr);
-	const struct glsl_type *type = image_deref->type;
-	const nir_variable *var = nir_deref_instr_get_variable(image_deref);
+	const nir_variable *var = get_image_variable(instr);
+	const struct glsl_type *type = glsl_without_array(var->type);
 	const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
-	bool writeonly_memory = var->data.image.access & ACCESS_NON_READABLE;
-	struct ac_image_args args = {};
-
-	args.cache_policy = get_cache_policy(ctx, var->data.image.access, true,
-					     writeonly_memory);
+	LLVMValueRef glc = ctx->ac.i1false;
+	bool force_glc = ctx->ac.chip_class == SI;
+	if (force_glc)
+		glc = ctx->ac.i1true;
 
 	if (dim == GLSL_SAMPLER_DIM_BUF) {
 		char name[48];
@@ -2445,19 +2393,14 @@ static void visit_image_store(struct ac_nir_context *ctx,
 						    ctx->ac.i32_0, ""); /* vindex */
 		params[3] = ctx->ac.i32_0; /* voffset */
 		snprintf(name, sizeof(name), "%s.%s",
-		         HAVE_LLVM >= 0x800 ? "llvm.amdgcn.struct.buffer.store.format"
-		                            : "llvm.amdgcn.buffer.store.format",
+		                            "llvm.amdgcn.buffer.store.format",
 		         types[CLAMP(src_channels, 1, 3) - 1]);
 
-		if (HAVE_LLVM >= 0x800) {
-			params[4] = ctx->ac.i32_0; /* soffset */
-			params[5] = (args.cache_policy & ac_glc) ? ctx->ac.i32_1 : ctx->ac.i32_0;
-		} else {
-			params[4] = LLVMConstInt(ctx->ac.i1, !!(args.cache_policy & ac_glc), 0);
-			params[5] = ctx->ac.i1false;  /* slc */
-		}
+		params[4] = glc;  /* glc */
+		params[5] = ctx->ac.i1false;  /* slc */
 		ac_build_intrinsic(&ctx->ac, name, ctx->ac.voidt, params, 6, 0);
 	} else {
+		struct ac_image_args args = {};
 		args.opcode = ac_image_store;
 		args.data[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[3]));
 		get_image_coords(ctx, instr, &args);
@@ -2465,6 +2408,8 @@ static void visit_image_store(struct ac_nir_context *ctx,
 		args.dim = get_ac_image_dim(&ctx->ac, glsl_get_sampler_dim(type),
 					    glsl_sampler_type_is_array(type));
 		args.dmask = 15;
+		if (force_glc || (var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT)))
+			args.cache_policy |= ac_glc;
 
 		ac_build_image_opcode(&ctx->ac, &args);
 	}
@@ -2476,12 +2421,13 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
 {
 	LLVMValueRef params[7];
 	int param_count = 0;
-	const struct glsl_type *type = get_image_deref(instr)->type;
+	const nir_variable *var = get_image_variable(instr);
 
 	bool cmpswap = instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap;
 	const char *atomic_name;
-	char intrinsic_name[64];
+	char intrinsic_name[41];
 	enum ac_atomic_op atomic_subop;
+	const struct glsl_type *type = glsl_without_array(var->type);
 	MAYBE_UNUSED int length;
 
 	bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
@@ -2532,18 +2478,10 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
 		params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
 								ctx->ac.i32_0, ""); /* vindex */
 		params[param_count++] = ctx->ac.i32_0; /* voffset */
-		if (HAVE_LLVM >= 0x800) {
-			params[param_count++] = ctx->ac.i32_0; /* soffset */
-			params[param_count++] = ctx->ac.i32_0;  /* slc */
+		params[param_count++] = ctx->ac.i1false;  /* slc */
 
-			length = snprintf(intrinsic_name, sizeof(intrinsic_name),
-			                  "llvm.amdgcn.struct.buffer.atomic.%s.i32", atomic_name);
-		} else {
-			params[param_count++] = ctx->ac.i1false;  /* slc */
-
-			length = snprintf(intrinsic_name, sizeof(intrinsic_name),
-			                  "llvm.amdgcn.buffer.atomic.%s", atomic_name);
-		}
+		length = snprintf(intrinsic_name, sizeof(intrinsic_name),
+				  "llvm.amdgcn.buffer.atomic.%s", atomic_name);
 
 		assert(length < sizeof(intrinsic_name));
 		return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32,
@@ -2567,7 +2505,8 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
 					const nir_intrinsic_instr *instr)
 {
-	const struct glsl_type *type = get_image_deref(instr)->type;
+	const nir_variable *var = get_image_variable(instr);
+	const struct glsl_type *type = glsl_without_array(var->type);
 
 	struct ac_image_args args = { 0 };
 	args.dim = get_ac_sampler_dim(&ctx->ac, glsl_get_sampler_dim(type),
@@ -2585,7 +2524,8 @@ static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
 				     const nir_intrinsic_instr *instr)
 {
 	LLVMValueRef res;
-	const struct glsl_type *type = get_image_deref(instr)->type;
+	const nir_variable *var = get_image_variable(instr);
+	const struct glsl_type *type = glsl_without_array(var->type);
 
 	if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
 		return get_buffer_size(ctx, get_image_descriptor(ctx, instr, AC_DESC_BUFFER, false), true);
@@ -2938,10 +2878,12 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
 
 	}
 
-	LLVMValueRef attrib_idx = ctx->ac.i32_0;
+	LLVMValueRef array_idx = ctx->ac.i32_0;
 	while(deref_instr->deref_type != nir_deref_type_var) {
 		if (deref_instr->deref_type == nir_deref_type_array) {
-			unsigned array_size = glsl_count_attribute_slots(deref_instr->type, false);
+			unsigned array_size = glsl_get_aoa_size(deref_instr->type);
+			if (!array_size)
+				array_size = 1;
 
 			LLVMValueRef offset;
 			nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
@@ -2954,26 +2896,23 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
 						      LLVMConstInt(ctx->ac.i32, array_size, false), "");
 			}
 
-			attrib_idx = LLVMBuildAdd(ctx->ac.builder, attrib_idx, offset, "");
+			array_idx = LLVMBuildAdd(ctx->ac.builder, array_idx, offset, "");
 			deref_instr = nir_src_as_deref(deref_instr->parent);
-		} else if (deref_instr->deref_type == nir_deref_type_struct) {
-			LLVMValueRef offset;
-			unsigned sidx = deref_instr->strct.index;
-			deref_instr = nir_src_as_deref(deref_instr->parent);
-			offset = LLVMConstInt(ctx->ac.i32, glsl_get_record_location_offset(deref_instr->type, sidx), false);
-			attrib_idx = LLVMBuildAdd(ctx->ac.builder, attrib_idx, offset, "");
 		} else {
 			unreachable("Unsupported deref type");
 		}
 
 	}
 
-	unsigned attrib_size = glsl_count_attribute_slots(var->type, false);
+	unsigned input_array_size = glsl_get_aoa_size(var->type);
+	if (!input_array_size)
+		input_array_size = 1;
+
 	for (chan = 0; chan < 4; chan++) {
-		LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->ac.f32, attrib_size));
+		LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->ac.f32, input_array_size));
 		LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
 
-		for (unsigned idx = 0; idx < attrib_size; ++idx) {
+		for (unsigned idx = 0; idx < input_array_size; ++idx) {
 			LLVMValueRef v, attr_number;
 
 			attr_number = LLVMConstInt(ctx->ac.i32, input_base + idx, false);
@@ -2996,7 +2935,7 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
 							LLVMConstInt(ctx->ac.i32, idx, false), "");
 		}
 
-		result[chan] = LLVMBuildExtractElement(ctx->ac.builder, gather, attrib_idx, "");
+		result[chan] = LLVMBuildExtractElement(ctx->ac.builder, gather, array_idx, "");
 
 	}
 	return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
@@ -3318,27 +3257,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 	}
 }
 
-static LLVMValueRef get_bindless_index_from_uniform(struct ac_nir_context *ctx,
-						    unsigned base_index,
-						    unsigned constant_index,
-						    LLVMValueRef dynamic_index)
-{
-	LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, base_index * 4, 0);
-	LLVMValueRef index = LLVMBuildAdd(ctx->ac.builder, dynamic_index,
-					  LLVMConstInt(ctx->ac.i32, constant_index, 0), "");
-
-	/* Bindless uniforms are 64bit so multiple index by 8 */
-	index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->ac.i32, 8, 0), "");
-	offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
-
-	LLVMValueRef ubo_index = ctx->abi->load_ubo(ctx->abi, ctx->ac.i32_0);
-
-	LLVMValueRef ret = ac_build_buffer_load(&ctx->ac, ubo_index, 1, NULL, offset,
-						NULL, 0, false, false, true, true);
-
-	return LLVMBuildBitCast(ctx->ac.builder, ret, ctx->ac.i32, "");
-}
-
 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
 				     nir_deref_instr *deref_instr,
 				     enum ac_descriptor_type desc_type,
@@ -3357,49 +3275,30 @@ static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
 		base_index = tex_instr->sampler_index;
 	} else {
 		while(deref_instr->deref_type != nir_deref_type_var) {
-			if (deref_instr->deref_type == nir_deref_type_array) {
-				unsigned array_size = glsl_get_aoa_size(deref_instr->type);
-				if (!array_size)
-					array_size = 1;
+			unsigned array_size = glsl_get_aoa_size(deref_instr->type);
+			if (!array_size)
+				array_size = 1;
 
-				nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
-				if (const_value) {
-					constant_index += array_size * const_value->u32[0];
-				} else {
-					LLVMValueRef indirect = get_src(ctx, deref_instr->arr.index);
-
-					indirect = LLVMBuildMul(ctx->ac.builder, indirect,
-						LLVMConstInt(ctx->ac.i32, array_size, false), "");
-
-					if (!index)
-						index = indirect;
-					else
-						index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
-				}
-
-				deref_instr = nir_src_as_deref(deref_instr->parent);
-			} else if (deref_instr->deref_type == nir_deref_type_struct) {
-				unsigned sidx = deref_instr->strct.index;
-				deref_instr = nir_src_as_deref(deref_instr->parent);
-				constant_index += glsl_get_record_location_offset(deref_instr->type, sidx);
+			assert(deref_instr->deref_type == nir_deref_type_array);
+			nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
+			if (const_value) {
+				constant_index += array_size * const_value->u32[0];
 			} else {
-				unreachable("Unsupported deref type");
+				LLVMValueRef indirect = get_src(ctx, deref_instr->arr.index);
+
+				indirect = LLVMBuildMul(ctx->ac.builder, indirect,
+					LLVMConstInt(ctx->ac.i32, array_size, false), "");
+
+                                if (!index)
+					index = indirect;
+				else
+					index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
 			}
+
+			deref_instr = nir_src_as_deref(deref_instr->parent);
 		}
 		descriptor_set = deref_instr->var->data.descriptor_set;
-
-		if (deref_instr->var->data.bindless) {
-			/* For now just assert on unhandled variable types */
-			assert(deref_instr->var->data.mode == nir_var_uniform);
-
-			base_index = deref_instr->var->data.driver_location;
-			bindless = true;
-
-			index = index ? index : ctx->ac.i32_0;
-			index = get_bindless_index_from_uniform(ctx, base_index,
-								constant_index, index);
-		} else
-			base_index = deref_instr->var->data.binding;
+		base_index = deref_instr->var->data.binding;
 	}
 
 	return ctx->abi->load_sampler_desc(ctx->abi,
@@ -3832,77 +3731,10 @@ static void visit_jump(struct ac_llvm_context *ctx,
 	}
 }
 
-static LLVMTypeRef
-glsl_base_to_llvm_type(struct ac_llvm_context *ac,
-		       enum glsl_base_type type)
-{
-	switch (type) {
-	case GLSL_TYPE_INT:
-	case GLSL_TYPE_UINT:
-	case GLSL_TYPE_BOOL:
-	case GLSL_TYPE_SUBROUTINE:
-		return ac->i32;
-	case GLSL_TYPE_INT16:
-	case GLSL_TYPE_UINT16:
-		return ac->i16;
-	case GLSL_TYPE_FLOAT:
-		return ac->f32;
-	case GLSL_TYPE_FLOAT16:
-		return ac->f16;
-	case GLSL_TYPE_INT64:
-	case GLSL_TYPE_UINT64:
-		return ac->i64;
-	case GLSL_TYPE_DOUBLE:
-		return ac->f64;
-	default:
-		unreachable("unknown GLSL type");
-	}
-}
-
-static LLVMTypeRef
-glsl_to_llvm_type(struct ac_llvm_context *ac,
-		  const struct glsl_type *type)
-{
-	if (glsl_type_is_scalar(type)) {
-		return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
-	}
-
-	if (glsl_type_is_vector(type)) {
-		return LLVMVectorType(
-		   glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
-		   glsl_get_vector_elements(type));
-	}
-
-	if (glsl_type_is_matrix(type)) {
-		return LLVMArrayType(
-		   glsl_to_llvm_type(ac, glsl_get_column_type(type)),
-		   glsl_get_matrix_columns(type));
-	}
-
-	if (glsl_type_is_array(type)) {
-		return LLVMArrayType(
-		   glsl_to_llvm_type(ac, glsl_get_array_element(type)),
-		   glsl_get_length(type));
-	}
-
-	assert(glsl_type_is_struct(type));
-
-	LLVMTypeRef member_types[glsl_get_length(type)];
-
-	for (unsigned i = 0; i < glsl_get_length(type); i++) {
-		member_types[i] =
-			glsl_to_llvm_type(ac,
-					  glsl_get_struct_field(type, i));
-	}
-
-	return LLVMStructTypeInContext(ac->context, member_types,
-				       glsl_get_length(type), false);
-}
-
 static void visit_deref(struct ac_nir_context *ctx,
                         nir_deref_instr *instr)
 {
-	if (instr->mode != nir_var_mem_shared)
+	if (instr->mode != nir_var_shared)
 		return;
 
 	LLVMValueRef result = NULL;
@@ -3920,27 +3752,6 @@ static void visit_deref(struct ac_nir_context *ctx,
 		result = ac_build_gep0(&ctx->ac, get_src(ctx, instr->parent),
 		                       get_src(ctx, instr->arr.index));
 		break;
-	case nir_deref_type_ptr_as_array:
-		result = ac_build_gep_ptr(&ctx->ac, get_src(ctx, instr->parent),
-		                          get_src(ctx, instr->arr.index));
-		break;
-	case nir_deref_type_cast: {
-		result = get_src(ctx, instr->parent);
-
-		LLVMTypeRef pointee_type = glsl_to_llvm_type(&ctx->ac, instr->type);
-		LLVMTypeRef type = LLVMPointerType(pointee_type, AC_ADDR_SPACE_LDS);
-
-		if (LLVMTypeOf(result) != type) {
-			if (LLVMGetTypeKind(LLVMTypeOf(result)) == LLVMVectorTypeKind) {
-				result = LLVMBuildBitCast(ctx->ac.builder, result,
-				                          type, "");
-			} else {
-				result = LLVMBuildIntToPtr(ctx->ac.builder, result,
-				                           type, "");
-			}
-		}
-		break;
-	}
 	default:
 		unreachable("Unhandled deref_instr deref type");
 	}
@@ -4089,6 +3900,68 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
 	}
 }
 
+static LLVMTypeRef
+glsl_base_to_llvm_type(struct ac_llvm_context *ac,
+		       enum glsl_base_type type)
+{
+	switch (type) {
+	case GLSL_TYPE_INT:
+	case GLSL_TYPE_UINT:
+	case GLSL_TYPE_BOOL:
+	case GLSL_TYPE_SUBROUTINE:
+		return ac->i32;
+	case GLSL_TYPE_FLOAT: /* TODO handle mediump */
+		return ac->f32;
+	case GLSL_TYPE_INT64:
+	case GLSL_TYPE_UINT64:
+		return ac->i64;
+	case GLSL_TYPE_DOUBLE:
+		return ac->f64;
+	default:
+		unreachable("unknown GLSL type");
+	}
+}
+
+static LLVMTypeRef
+glsl_to_llvm_type(struct ac_llvm_context *ac,
+		  const struct glsl_type *type)
+{
+	if (glsl_type_is_scalar(type)) {
+		return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
+	}
+
+	if (glsl_type_is_vector(type)) {
+		return LLVMVectorType(
+		   glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
+		   glsl_get_vector_elements(type));
+	}
+
+	if (glsl_type_is_matrix(type)) {
+		return LLVMArrayType(
+		   glsl_to_llvm_type(ac, glsl_get_column_type(type)),
+		   glsl_get_matrix_columns(type));
+	}
+
+	if (glsl_type_is_array(type)) {
+		return LLVMArrayType(
+		   glsl_to_llvm_type(ac, glsl_get_array_element(type)),
+		   glsl_get_length(type));
+	}
+
+	assert(glsl_type_is_struct(type));
+
+	LLVMTypeRef member_types[glsl_get_length(type)];
+
+	for (unsigned i = 0; i < glsl_get_length(type); i++) {
+		member_types[i] =
+			glsl_to_llvm_type(ac,
+					  glsl_get_struct_field(type, i));
+	}
+
+	return LLVMStructTypeInContext(ac->context, member_types,
+				       glsl_get_length(type), false);
+}
+
 static void
 setup_locals(struct ac_nir_context *ctx,
 	     struct nir_function *func)
@@ -4158,13 +4031,13 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 
 	setup_locals(&ctx, func);
 
-	if (gl_shader_stage_is_compute(nir->info.stage))
+	if (nir->info.stage == MESA_SHADER_COMPUTE)
 		setup_shared(&ctx, nir);
 
 	visit_cf_list(&ctx, &func->impl->body);
 	phi_post_pass(&ctx);
 
-	if (!gl_shader_stage_is_compute(nir->info.stage))
+	if (nir->info.stage != MESA_SHADER_COMPUTE)
 		ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
 				      ctx.abi->outputs);
 
@@ -4207,168 +4080,7 @@ ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
 	 * See the following thread for more details of the problem:
 	 * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
 	 */
-	indirect_mask |= nir_var_function_temp;
+	indirect_mask |= nir_var_local;
 
 	nir_lower_indirect_derefs(nir, indirect_mask);
 }
-
-static unsigned
-get_inst_tessfactor_writemask(nir_intrinsic_instr *intrin)
-{
-	if (intrin->intrinsic != nir_intrinsic_store_deref)
-		return 0;
-
-	nir_variable *var =
-		nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[0]));
-
-	if (var->data.mode != nir_var_shader_out)
-		return 0;
-
-	unsigned writemask = 0;
-	const int location = var->data.location;
-	unsigned first_component = var->data.location_frac;
-	unsigned num_comps = intrin->dest.ssa.num_components;
-
-	if (location == VARYING_SLOT_TESS_LEVEL_INNER)
-		writemask = ((1 << (num_comps + 1)) - 1) << first_component;
-	else if (location == VARYING_SLOT_TESS_LEVEL_OUTER)
-		writemask = (((1 << (num_comps + 1)) - 1) << first_component) << 4;
-
-	return writemask;
-}
-
-static void
-scan_tess_ctrl(nir_cf_node *cf_node, unsigned *upper_block_tf_writemask,
-	       unsigned *cond_block_tf_writemask,
-	       bool *tessfactors_are_def_in_all_invocs, bool is_nested_cf)
-{
-	switch (cf_node->type) {
-	case nir_cf_node_block: {
-		nir_block *block = nir_cf_node_as_block(cf_node);
-		nir_foreach_instr(instr, block) {
-			if (instr->type != nir_instr_type_intrinsic)
-				continue;
-
-			nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-			if (intrin->intrinsic == nir_intrinsic_barrier) {
-
-				/* If we find a barrier in nested control flow put this in the
-				 * too hard basket. In GLSL this is not possible but it is in
-				 * SPIR-V.
-				 */
-				if (is_nested_cf) {
-					*tessfactors_are_def_in_all_invocs = false;
-					return;
-				}
-
-				/* The following case must be prevented:
-				 *    gl_TessLevelInner = ...;
-				 *    barrier();
-				 *    if (gl_InvocationID == 1)
-				 *       gl_TessLevelInner = ...;
-				 *
-				 * If you consider disjoint code segments separated by barriers, each
-				 * such segment that writes tess factor channels should write the same
-				 * channels in all codepaths within that segment.
-				 */
-				if (upper_block_tf_writemask || cond_block_tf_writemask) {
-					/* Accumulate the result: */
-					*tessfactors_are_def_in_all_invocs &=
-						!(*cond_block_tf_writemask & ~(*upper_block_tf_writemask));
-
-					/* Analyze the next code segment from scratch. */
-					*upper_block_tf_writemask = 0;
-					*cond_block_tf_writemask = 0;
-				}
-			} else
-				*upper_block_tf_writemask |= get_inst_tessfactor_writemask(intrin);
-		}
-
-		break;
-	}
-	case nir_cf_node_if: {
-		unsigned then_tessfactor_writemask = 0;
-		unsigned else_tessfactor_writemask = 0;
-
-		nir_if *if_stmt = nir_cf_node_as_if(cf_node);
-		foreach_list_typed(nir_cf_node, nested_node, node, &if_stmt->then_list) {
-			scan_tess_ctrl(nested_node, &then_tessfactor_writemask,
-				       cond_block_tf_writemask,
-				       tessfactors_are_def_in_all_invocs, true);
-		}
-
-		foreach_list_typed(nir_cf_node, nested_node, node, &if_stmt->else_list) {
-			scan_tess_ctrl(nested_node, &else_tessfactor_writemask,
-				       cond_block_tf_writemask,
-				       tessfactors_are_def_in_all_invocs, true);
-		}
-
-		if (then_tessfactor_writemask || else_tessfactor_writemask) {
-			/* If both statements write the same tess factor channels,
-			 * we can say that the upper block writes them too.
-			 */
-			*upper_block_tf_writemask |= then_tessfactor_writemask &
-				else_tessfactor_writemask;
-			*cond_block_tf_writemask |= then_tessfactor_writemask |
-				else_tessfactor_writemask;
-		}
-
-		break;
-	}
-	case nir_cf_node_loop: {
-		nir_loop *loop = nir_cf_node_as_loop(cf_node);
-		foreach_list_typed(nir_cf_node, nested_node, node, &loop->body) {
-			scan_tess_ctrl(nested_node, cond_block_tf_writemask,
-				       cond_block_tf_writemask,
-				       tessfactors_are_def_in_all_invocs, true);
-		}
-
-		break;
-	}
-	default:
-		unreachable("unknown cf node type");
-	}
-}
-
-bool
-ac_are_tessfactors_def_in_all_invocs(const struct nir_shader *nir)
-{
-	assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
-
-	/* The pass works as follows:
-	 * If all codepaths write tess factors, we can say that all
-	 * invocations define tess factors.
-	 *
-	 * Each tess factor channel is tracked separately.
-	 */
-	unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
-	unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
-
-	/* Initial value = true. Here the pass will accumulate results from
-	 * multiple segments surrounded by barriers. If tess factors aren't
-	 * written at all, it's a shader bug and we don't care if this will be
-	 * true.
-	 */
-	bool tessfactors_are_def_in_all_invocs = true;
-
-	nir_foreach_function(function, nir) {
-		if (function->impl) {
-			foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
-				scan_tess_ctrl(node, &main_block_tf_writemask,
-					       &cond_block_tf_writemask,
-					       &tessfactors_are_def_in_all_invocs,
-					       false);
-			}
-		}
-	}
-
-	/* Accumulate the result for the last code segment separated by a
-	 * barrier.
-	 */
-	if (main_block_tf_writemask || cond_block_tf_writemask) {
-		tessfactors_are_def_in_all_invocs &=
-			!(cond_block_tf_writemask & ~main_block_tf_writemask);
-	}
-
-	return tessfactors_are_def_in_all_invocs;
-}

src/amd/common/ac_nir_to_llvm.h

@@ -47,8 +47,6 @@ static inline unsigned ac_llvm_reg_index_soa(unsigned index, unsigned chan)
 
 void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
 
-bool ac_are_tessfactors_def_in_all_invocs(const struct nir_shader *nir);
-
 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 		      struct nir_shader *nir);
 

src/amd/common/ac_surface.c

@@ -27,7 +27,7 @@
 
 #include "ac_surface.h"
 #include "amd_family.h"
-#include "addrlib/src/amdgpu_asic_addr.h"
+#include "addrlib/amdgpu_asic_addr.h"
 #include "ac_gpu_info.h"
 #include "util/macros.h"
 #include "util/u_atomic.h"
@@ -39,7 +39,7 @@
 #include <amdgpu.h>
 #include <amdgpu_drm.h>
 
-#include "addrlib/inc/addrinterface.h"
+#include "addrlib/addrinterface.h"
 
 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
@@ -1038,7 +1038,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 static int
 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 				ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
-				bool is_fmask, AddrSwizzleMode *swizzle_mode)
+				bool is_fmask, unsigned flags,
+				AddrSwizzleMode *swizzle_mode)
 {
 	ADDR_E_RETURNCODE ret;
 	ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
@@ -1063,6 +1064,16 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 	sin.numSamples = in->numSamples;
 	sin.numFrags = in->numFrags;
 
+	if (flags & RADEON_SURF_SCANOUT) {
+		sin.preferredSwSet.sw_D = 1;
+		/* Raven only allows S for displayable surfaces with < 64 bpp, so
+		 * allow it as fallback */
+		sin.preferredSwSet.sw_S = 1;
+	} else if (in->flags.depth || in->flags.stencil || is_fmask)
+		sin.preferredSwSet.sw_Z = 1;
+	else
+		sin.preferredSwSet.sw_S = 1;
+
 	if (is_fmask) {
 		sin.flags.display = 0;
 		sin.flags.color = 0;
@@ -1262,7 +1273,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 
 			ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
-							      true, &fin.swizzleMode);
+							      true, surf->flags,
+							      &fin.swizzleMode);
 			if (ret != ADDR_OK)
 				return ret;
 
@@ -1412,13 +1424,11 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 		AddrSurfInfoIn.bpp = surf->bpe * 8;
 	}
 
-	bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
-	AddrSurfInfoIn.flags.color = is_color_surface &&
-	                             !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
+	AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	/* flags.texture currently refers to TC-compatible HTILE */
-	AddrSurfInfoIn.flags.texture = is_color_surface ||
+	AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
 				       surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
 	AddrSurfInfoIn.flags.opt4space = 1;
 
@@ -1466,7 +1476,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 		}
 
 		r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
-						    false, &AddrSurfInfoIn.swizzleMode);
+						    false, surf->flags,
+						    &AddrSurfInfoIn.swizzleMode);
 		if (r)
 			return r;
 		break;
@@ -1502,7 +1513,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 		if (!AddrSurfInfoIn.flags.depth) {
 			r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
-							    false, &AddrSurfInfoIn.swizzleMode);
+							    false, surf->flags,
+							    &AddrSurfInfoIn.swizzleMode);
 			if (r)
 				return r;
 		} else
@@ -1518,12 +1530,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	/* Query whether the surface is displayable. */
 	bool displayable = false;
-	if (!config->is_3d && !config->is_cube) {
-		r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
+	r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
 					   surf->bpe * 8, &displayable);
-		if (r)
-			return r;
-	}
+	if (r)
+		return r;
 	surf->is_displayable = displayable;
 
 	switch (surf->u.gfx9.surf.swizzle_mode) {
@@ -1584,6 +1594,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 			assert(0);
 	}
 
+	/* Temporary workaround to prevent VM faults and hangs. */
+	if (info->family == CHIP_VEGA12)
+		surf->fmask_size *= 8;
+
 	return 0;
 }
 

src/amd/common/ac_surface.h

@@ -68,7 +68,6 @@ enum radeon_micro_mode {
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
-#define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
 
 struct legacy_surf_level {
     uint64_t                    offset;

src/amd/common/sid.h

@@ -133,11 +133,11 @@
 #define     S_370_WR_ONE_ADDR(x)		(((unsigned)(x) & 0x1) << 16)
 #define     S_370_DST_SEL(x)			(((unsigned)(x) & 0xf) << 8)
 #define       V_370_MEM_MAPPED_REGISTER		0
-#define       V_370_MEM_GRBM			1 /* sync across GRBM */
+#define       V_370_MEMORY_SYNC			1
 #define       V_370_TC_L2			2
 #define       V_370_GDS				3
 #define       V_370_RESERVED			4
-#define       V_370_MEM				5 /* not on SI */
+#define       V_370_MEM_ASYNC			5
 #define   R_371_DST_ADDR_LO			0x371
 #define   R_372_DST_ADDR_HI			0x372
 #define PKT3_DRAW_INDEX_INDIRECT_MULTI         0x38
@@ -211,14 +211,12 @@
 #define PKT3_SET_SH_REG                        0x76
 #define PKT3_SET_SH_REG_OFFSET                 0x77
 #define PKT3_SET_UCONFIG_REG                   0x79 /* new for CIK */
-#define PKT3_SET_UCONFIG_REG_INDEX             0x7A /* new for GFX9, CP ucode version >= 26 */
 #define PKT3_LOAD_CONST_RAM                    0x80
 #define PKT3_WRITE_CONST_RAM                   0x81
 #define PKT3_DUMP_CONST_RAM                    0x83
 #define PKT3_INCREMENT_CE_COUNTER              0x84
 #define PKT3_INCREMENT_DE_COUNTER              0x85
 #define PKT3_WAIT_ON_CE_COUNTER                0x86
-#define PKT3_LOAD_CONTEXT_REG                  0x9F /* new for VI */
 
 #define PKT_TYPE_S(x)                   (((unsigned)(x) & 0x3) << 30)
 #define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
@@ -2437,9 +2435,6 @@
 #define   S_008F30_FILTER_MODE(x)                                     (((unsigned)(x) & 0x03) << 29)
 #define   G_008F30_FILTER_MODE(x)                                     (((x) >> 29) & 0x03)
 #define   C_008F30_FILTER_MODE                                        0x9FFFFFFF
-#define     V_008F30_SQ_IMG_FILTER_MODE_BLEND                       0x00
-#define     V_008F30_SQ_IMG_FILTER_MODE_MIN                         0x01
-#define     V_008F30_SQ_IMG_FILTER_MODE_MAX                         0x02
 /* VI */
 #define   S_008F30_COMPAT_MODE(x)                                     (((unsigned)(x) & 0x1) << 31)
 #define   G_008F30_COMPAT_MODE(x)                                     (((x) >> 31) & 0x1)

src/amd/common/sid_tables.py

@@ -1,4 +1,4 @@
-from __future__ import print_function, division, unicode_literals
+from __future__ import print_function
 
 CopyRight = '''
 /*

src/amd/vulkan/Makefile.sources

@@ -50,7 +50,6 @@ VULKAN_FILES := \
 	radv_meta_copy.c \
 	radv_meta_decompress.c \
 	radv_meta_fast_clear.c \
-	radv_meta_fmask_expand.c \
 	radv_meta_resolve.c \
 	radv_meta_resolve_cs.c \
 	radv_meta_resolve_fs.c \

src/amd/vulkan/meson.build

@@ -78,7 +78,6 @@ libradv_files = files(
   'radv_meta_copy.c',
   'radv_meta_decompress.c',
   'radv_meta_fast_clear.c',
-  'radv_meta_fmask_expand.c',
   'radv_meta_resolve.c',
   'radv_meta_resolve_cs.c',
   'radv_meta_resolve_fs.c',

src/amd/vulkan/radv_android.c

@@ -111,7 +111,7 @@ radv_image_from_gralloc(VkDevice device_h,
 	VkResult result;
 
 	if (gralloc_info->handle->numFds != 1) {
-		return vk_errorf(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE,
+		return vk_errorf(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR,
 		                 "VkNativeBufferANDROID::handle::numFds is %d, "
 		                 "expected 1", gralloc_info->handle->numFds);
 	}
@@ -126,7 +126,7 @@ radv_image_from_gralloc(VkDevice device_h,
 
 	const VkImportMemoryFdInfoKHR import_info = {
 		.sType = VK_STRUCTURE_TYPE_IMPORT_MEMORY_FD_INFO_KHR,
-		.handleType = VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT,
+		.handleType = VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR,
 		.fd = dup(dma_buf),
 	};
 
@@ -230,16 +230,16 @@ VkResult radv_GetSwapchainGrallocUsageANDROID(
 	 * dEQP-VK.wsi.android.swapchain.*.image_usage to fail.
 	 */
 
-	const VkPhysicalDeviceImageFormatInfo2 image_format_info = {
-		.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_FORMAT_INFO_2,
+	const VkPhysicalDeviceImageFormatInfo2KHR image_format_info = {
+		.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_FORMAT_INFO_2_KHR,
 		.format = format,
 		.type = VK_IMAGE_TYPE_2D,
 		.tiling = VK_IMAGE_TILING_OPTIMAL,
 		.usage = imageUsage,
 	};
 
-	VkImageFormatProperties2 image_format_props = {
-		.sType = VK_STRUCTURE_TYPE_IMAGE_FORMAT_PROPERTIES_2,
+	VkImageFormatProperties2KHR image_format_props = {
+		.sType = VK_STRUCTURE_TYPE_IMAGE_FORMAT_PROPERTIES_2_KHR,
 	};
 
 	/* Check that requested format and usage are supported. */
@@ -303,7 +303,7 @@ radv_AcquireImageANDROID(
 		semaphore_result = radv_ImportSemaphoreFdKHR(device,
 		                                             &(VkImportSemaphoreFdInfoKHR) {
 		                                                 .sType = VK_STRUCTURE_TYPE_IMPORT_SEMAPHORE_FD_INFO_KHR,
-		                                                 .flags = VK_SEMAPHORE_IMPORT_TEMPORARY_BIT,
+		                                                 .flags = VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR,
 		                                                 .fd = semaphore_fd,
 		                                                 .semaphore = semaphore,
 		                                            });
@@ -314,7 +314,7 @@ radv_AcquireImageANDROID(
 		fence_result = radv_ImportFenceFdKHR(device,
 		                                     &(VkImportFenceFdInfoKHR) {
 		                                         .sType = VK_STRUCTURE_TYPE_IMPORT_FENCE_FD_INFO_KHR,
-		                                         .flags = VK_FENCE_IMPORT_TEMPORARY_BIT,
+		                                         .flags = VK_FENCE_IMPORT_TEMPORARY_BIT_KHR,
 		                                         .fd = fence_fd,
 		                                         .fence = fence,
 		                                     });
@@ -351,7 +351,7 @@ radv_QueueSignalReleaseImageANDROID(
 		result = radv_GetSemaphoreFdKHR(radv_device_to_handle(queue->device),
 		                                &(VkSemaphoreGetFdInfoKHR) {
 		                                    .sType = VK_STRUCTURE_TYPE_SEMAPHORE_GET_FD_INFO_KHR,
-		                                    .handleType = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT,
+		                                    .handleType = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR,
 		                                    .semaphore = pWaitSemaphores[i],
 		                            }, &tmp_fd);
 		if (result != VK_SUCCESS) {