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Author SHA1 Message Date
Emil Velikov
eb9da68cbf docs: add sha256 checksums for 18.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-05 12:00:12 +01:00
Emil Velikov
b03f51c4b4 docs: add release notes for 18.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-05 11:59:15 +01:00
Emil Velikov
11049bcff8 Update version to 18.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-05 11:31:05 +01:00
Eric Anholt
2b50357c0f dri3: Return the current swap interval from glXGetSwapIntervalMESA().
We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit edc7deec42)
2019-04-05 11:31:05 +01:00
Marek Olšák
12ab2d0003 radeonsi: fix assertion failure by using the correct type
src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband:
Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode]
&& vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed.

The comparison was unsigned, so negative maxx or maxy would fail.

Fixes: 3c540e0a74 "radeonsi: Fix guardband computation for large render targets"
(cherry picked from commit 3ad2a9b3fa)
2019-04-05 11:31:05 +01:00
Leo Liu
319e0c1799 radeon/vcn/vp9: search the render target from the whole list
The number of render targets could be more than max of references,
so we search the full list of the render pictures for the current
render target index

https://bugs.freedesktop.org/show_bug.cgi?id=109648

Signed-off-by: Leo Liu <leo.liu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: James Zhu<James.Zhu@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d4e0fbc92f)
2019-04-05 11:31:05 +01:00
Eric Engestrom
14c82872f5 meson: strip rpath from megadrivers
More specifically, use the library file that has been post-processed by Meson
when creating the hardlinks.

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108766
Fixes: 3218056e0e "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit aa7afe324c)
2019-04-05 11:31:05 +01:00
Samuel Pitoiset
9434f6b5da radv: do not always initialize HTILE in compressed state
Especially when performing a transtion from UNDEFINED->GENERAL,
the driver shouldn't initialize HTILE metadata in compressed
state because it doesn't decompress when the src layout is
GENERAL.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110259
Fixes: 3a2e93147f ("radv: always initialize HTILE when the src layout is UNDEFINED")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 62a9d757e6)
2019-04-05 11:31:05 +01:00
Leo Liu
a5fc53b7f8 radeon/vcn: add H.264 constrained baseline support
VCN supports this profile as well as UVD, so add it

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f8ef8b56a6)
2019-04-05 11:31:05 +01:00
Jason Ekstrand
600f314d63 Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"
This reverts commit 4e1bbb000c.  It turns
out that some DXVK apps due to some implementation detail of DXVK or
other create and destroy instances in an interleaved way.  Freeing the
glsl_type memory without being a bit more careful causes use-after-free
issues.  Looks like we need to try again.

(cherry picked from commit ce47999cee)
2019-04-05 11:31:05 +01:00
Bas Nieuwenhuizen
cdd3eac623 ac/nir: Return frag_coord as integer.
To preserve the invariant that nir ssa defs are integers or pointers
in LLVM.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 82075e3c42)
2019-03-26 18:33:59 +00:00
Tapani Pälli
7c271fd482 anv/radv: release memory allocated by glsl types during spirv_to_nir
Fixes leaks for each glsl_type generated:

   ==32470== 384 bytes in 3 blocks are possibly lost in loss record 18 of 18
   ==32470==    at 0x483880B: malloc (vg_replace_malloc.c:309)
   ==32470==    by 0x4C43F4A: ralloc_size (ralloc.c:119)
   ==32470==    by 0x4C44014: rzalloc_size (ralloc.c:151)
   ==32470==    by 0x4C44258: rzalloc_array_size (ralloc.c:215)
   ==32470==    by 0x4D38957: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:114)
   ==32470==    by 0x4D3BEED: glsl_type::get_struct_instance(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:1146)
   ==32470==    by 0x4D42ECC: glsl_struct_type (nir_types.cpp:501)
   ==32470==    by 0x4CDB5A1: vtn_handle_type (spirv_to_nir.c:1269)
   ==32470==    by 0x4CE53DD: vtn_handle_variable_or_type_instruction (spirv_to_nir.c:4018)
   ==32470==    by 0x4CD8CFF: vtn_foreach_instruction (spirv_to_nir.c:365)
   ==32470==    by 0x4CE5E6B: spirv_to_nir (spirv_to_nir.c:4490)
   ==32470==    by 0x497AF10: anv_shader_compile_to_nir (anv_pipeline.c:173)

v2: move release call to vkDestroyInstance
v3: apply fix also to radv driver

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 4e1bbb000c)
2019-03-26 18:33:55 +00:00
Timothy Arceri
d29dca6d15 st/glsl_to_nir: fix incorrect arrary access
This fixes a segfault when we try to access the array using a
-1 when the array wasn't allocated in the first place.

Before 7536af670b we would just access a pre-allocated array
that was also load/stored to/from the shader cache. But now the
cache will no longer allocate these arrays if they are empty.
The change resulted in tests such as the following segfaulting
when run with a warm shader cache.

tests/spec/arb_arrays_of_arrays/execution/sampler/fs-struct-const-index.shader_test

(cherry picked from commit cb2898f478)
2019-03-25 16:48:24 +00:00
Józef Kucia
643754ce67 radv: Fix driverUUID
Fixes: 14cad8786a ("radv: generate the same driver UUID as radeonsi")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit c077d5d7de)
2019-03-25 16:31:40 +00:00
Danylo Piliaiev
eac9b871c9 glsl: Cross validate variable's invariance by explicit invariance only
'invariant' qualifier is propagated on variables which are used
to calculate other invariant variables, however when we are matching
variable's declarations we should take into account only explicitly
declared invariance because invariance propagation is an implementation
specific detail.

Thus new flag is added to ir_variable_data which indicates 'invariant'
qualifier being explicitly set in the shader.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100316
Fixes: 89b60492 ('glsl: Add a pass to propagate the "invariant" and
  "precise" qualifiers')

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit ea9bde151f)
2019-03-25 16:31:28 +00:00
Józef Kucia
f3617aa99c mesa: Fix GL_NUM_DEVICE_UUIDS_EXT
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 1d996ef714)
2019-03-25 16:30:25 +00:00
Dylan Baker
e9ff2b5276 bin/install_megadrivers.py: Correctly handle DESTDIR=''
Currently if destdir is set to '' then the resulting libdir will have
it's first character replaced by / instead of / being prepended to the
string. This was the result of ensuring that that DESTDIR wouldn't be
ignored if libdir was absolute, since the only cases that meson allows
the libdir to be absolute is if the prefix is /, this won't be a
problem.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110211
Fixes: ae3f45c11e
       ("bin/install_megadrivers: fix DESTDIR and -D*-path")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 4188dd7879)

Squashed with:

bin/install_megadrivers.py: Fix regression for set DESTDIR

The previous patch tried to address a bug when DESTDIR is '', however,
it introduces a bug when DESTDIR is not '', and fakeroot is used. This
patch does fix that, and has been tested with the arch pkg-build to
ensure it isn't regressed.

Fixes: 093a1ade4e24b7dd701a093d30a71efd669fe9c8
       ("bin/install_megadrivers.py: Correctly handle DESTDIR=''")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110221
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
(cherry picked from commit ed96038e55)
2019-03-25 16:28:17 +00:00
Dave Airlie
76719ecbb3 softpipe: fix texture view crashes
I noticed we crashed piglit arb_texture_view-rendering-formats
when run on softpipe.

This fixes the clear tiles to use the surface format not the
underlying storage format.

This fixes a bunch of srgb piglits as well.

Fixes: 396ac41fc2 (softpipe: add integer support)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 04189565a0)
2019-03-25 16:21:36 +00:00
Samuel Pitoiset
96a01a5eed radv: fix binding transform feedback buffers
The mask should be accumulated if two calls are used for
binding two buffers at different indexes. Otherwise, the
driver only accounts for the last one.

Noticed while glancing at this code.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 4fa61273a8)
2019-03-25 16:18:43 +00:00
Andres Gomez
0f976b92f8 Revert "glsl: relax input->output validation for SSO programs"
This reverts commit 1aa5738e66.

This patch incorrectly asumed that for SSOs no inner interface
matching check was needed.

From the ARB_separate_shader_objects spec v.25:

  " With separable program objects, interfaces between shader stages
    may involve the outputs from one program object and the inputs
    from a second program object.  For such interfaces, it is not
    possible to detect mismatches at link time, because the programs
    are linked separately.  When each such program is linked, all
    inputs or outputs interfacing with another program stage are
    treated as active.  The linker will generate an executable that
    assumes the presence of a compatible program on the other side of
    the interface.  If a mismatch between programs occurs, no GL error
    will be generated, but some or all of the inputs on the interface
    will be undefined."

This completes the fix from commit:
3be05dd267 ("glsl/linker: don't fail non static used inputs without matching outputs")

Fixes: 1aa5738e66 ("glsl: relax input->output validation for SSO programs")
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit ab28dca033)
2019-03-25 16:18:25 +00:00
Andres Gomez
208fd66d80 glsl/linker: simplify xfb_offset vs xfb_stride overflow check
Current implementation uses a complicated calculation which relies in
an implicit conversion to check the integral part of 2 division
results.

However, the calculation actually checks that the xfb_offset is
smaller or a multiplier of the xfb_stride. For example, while this is
expected to fail, it actually succeeds:

  "

    ...

    layout(xfb_buffer = 2, xfb_stride = 12) out block3 {
      layout(xfb_offset = 0) vec3 c;
      layout(xfb_offset = 12) vec3 d; // ERROR, requires stride of 24
    };

    ...

  "

Fixes: 2fab85aaea ("glsl: add xfb_stride link time validation")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 422882e78f)
2019-03-25 16:17:50 +00:00
Andres Gomez
479b11040f glsl/linker: don't fail non static used inputs without matching outputs
If there is no Static Use of an input variable, the linker shouldn't
fail whenever there is no defined matching output variable in the
previous stage.

From page 47 (page 51 of the PDF) of the GLSL 4.60 v.5 spec:

  " Only the input variables that are statically read need to be
    written by the previous stage; it is allowed to have superfluous
    declarations of input variables."

Now, we complete this exception whenever the input variable has an
explicit location. Previously, 18004c338f ("glsl: fail when a
shader's input var has not an equivalent out var in previous") took
care of the cases in which the input variable didn't have an explicit
location.

v2: do the location based interface matching check regardless on
    whether it is a separable program or not (Ilia).

Fixes: 1aa5738e66 ("glsl: relax input->output validation for SSO programs")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Iago Toral Quiroga <itoral@igalia.com>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 3be05dd267)
2019-03-25 16:17:03 +00:00
Andres Gomez
db517e336c glsl: correctly validate component layout qualifier for dvec{3,4}
From page 62 (page 68 of the PDF) of the GLSL 4.50 v.7 spec:

  " A dvec3 or dvec4 can only be declared without specifying a
    component."

Therefore, using the "component" qualifier with a dvec3 or dvec4
should result in a compiling error.

v2: enhance the error message (Timothy).

Fixes: 94438578d2 ("glsl: validate and store component layout qualifier in GLSL IR")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit a96093136b)
2019-03-25 16:15:02 +00:00
Bas Nieuwenhuizen
f9160aa98b radv: Use correct image view comparison for fast clears.
The if is actually returning true on success, enabling fast clears, so we
need to have the test succeed when the iview dimensions are right.

Fixes: d5400a5ec2 "radv: provide a helper for comparing an image extents."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a777c3d7cb)
2019-03-25 16:14:35 +00:00
Tobias Klausmann
8e90903463 vulkan/util: meson build - add wayland client include
Without this the build breaks with:

In file included from ../src/vulkan/util/vk_util.h:32,
                 from ../src/vulkan/util/vk_util.c:28:
../include/vulkan/vulkan.h:51:10: fatal error: wayland-client.h: No such file or
directory
 #include <wayland-client.h>
          ^~~~~~~~~~~~~~~~~~
compilation terminated.

The above misses the include directory for wayland:
   -I/usr/include/wayland

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 29179f58c6)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/vulkan/util/meson.build
2019-03-25 16:13:37 +00:00
Mark Janes
f29b229664 mesa: properly report the length of truncated log messages
_mesa_log_msg must provide the length of the string passed into the
KHR_debug api.  When the string formatted by _mesa_gl_vdebugf exceeds
MAX_DEBUG_MESSAGE_LENGTH, the length is incorrectly set to the number
of characters that would have been written if enough space had been
available.

Fixes: 3025680578
       ("mesa: Add support for GL_ARB_debug_output with dynamic ID allocation.")

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit eb1a869a5d)
2019-03-25 15:55:56 +00:00
Plamena Manolova
2c163bfe68 i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9
ARB_fragment_shader_interlock depends on memory fences to
ensure fragment ordering and this ordering guarantee is
only supported from GEN9 onwards.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980
Fixes: 939312702e "i965: Add ARB_fragment_shader_interlock support."
Signed-off-by: Plamena Manolova <plamena.n.manolova@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 19ab082001)
2019-03-25 15:55:35 +00:00
Jason Ekstrand
6f76ecffbc anv/pass: Flag the need for a RT flush for resolve attachments
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 489bf2de23)
2019-03-25 15:54:59 +00:00
Emil Velikov
ec770b43b9 docs: add sha256 checksums for 18.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-18 15:57:14 +00:00
Emil Velikov
022708cb40 docs: add release notes for 18.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-18 15:45:53 +00:00
Emil Velikov
2a1e743ed9 Update version to 18.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-18 15:37:03 +00:00
Samuel Pitoiset
60fb5f4b86 radv: always initialize HTILE when the src layout is UNDEFINED
HTILE should always be initialized when transitioning from
VK_IMAGE_LAYOUT_UNDEFINED to other image layouts. Otherwise,
if an app does a transition from UNDEFINED to GENERAL, the
driver doesn't initialize HTILE and it tries to decompress
the depth surface. For some reasons, this results in VM faults.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 3a2e93147f)
2019-03-15 14:31:32 +00:00
Kevin Strasser
bdd5f24c1b egl/dri: Avoid out of bounds array access
indexConfigAttrib iterates over every index in the dri driver, possibly
exceeding __DRI_ATTRIB_MAX. In other words, if the dri driver has newer
attributes libEGL will end up reading from uninitialized memory through
dri2_to_egl_attribute_map[].

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 70b36c0ef9)
2019-03-15 14:31:25 +00:00
Danylo Piliaiev
4f30487a80 glsl/linker: Fix unmatched TCS outputs being reduced to local variable
Always match TCS outputs since they are shared by all invocations
within the patch and should not be converted to local variables.

This is one of the issues found in Downward.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104297
(cherry picked from commit 9f29d90327)
2019-03-14 19:07:30 +00:00
Kenneth Graunke
a1c6be2ab6 intel/fs: Fix opt_peephole_csel to not throw away saturates.
We were not copying the saturate bit from the original instruction
to the new replacement instruction.  This caused major misrendering
in DiRT Rally on iris, where comparisons leading to discards failed
due to the missing saturate, causing lots of extra garbage pixels to
be drawn in text rendering, trees, and so on.

This did not show up on i965 because st/nir performs a more aggressive
version of nir_opt_peephole_select, yielding more b32csel operations.

Fixes: 52c7df1643 i965/fs: Merge CMP and SEL into CSEL on Gen8+

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 3570d15b6d)
2019-03-14 19:07:30 +00:00
Jason Ekstrand
92ad8814ac glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
Tessellation control shader outputs act as if they have memory backing
them and you can have multiple writes to different components of the
same vector in-flight at the same time.  When this happens, the load vec
store pattern that gets used by ir_triop_vector_insert doesn't yield the
correct results.  Instead, just emit a sequence of conditional
assignments.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit bd17bdc56b)
2019-03-14 19:07:30 +00:00
Jason Ekstrand
612ddf210f glsl/list: Add a list variant of insert_after
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

(cherry picked from commit 20c4578c55)
2019-03-14 19:07:30 +00:00
Emil Velikov
b6cf9b7348 cherry-ignore: add explicit 19.0 performance optimisations
nir: lower IO to vector
  intel: make use of the optimisation

They address a 10% regression in a synthetic benchmark. No real world
use-cases seems to be affected.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-14 19:04:43 +00:00
pal1000
13b23099a3 scons: Compatibility with Scons development version string
This ensures Mesa3D build doesn't fail in this case as encountered when
bisecting Scons source code while regression testing
https://bugs.freedesktop.org/show_bug.cgi?id=109443
and when testing 3.0.5.a.2

Technical details:
Scons version string has consistently been in this format:
MajorVersion.MinorVersion.Patch[.alpha/beta.yyyymmdd]
so these formulas should strip alpha/beta flags and return Scons version:

- as string - `'.'.join(SCons.__version__.split('.')[:3])`
- as tuple of integers - `tuple(map(int, SCons.__version__.split('.')[:3]))`

- v2: Fixed Scons version retrieval formulas as string and tuple of integers.
- v3: Fixed Scons version string format description.

Cc: "19.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 7f89fd17ed)
2019-03-14 19:03:56 +00:00
Jose Fonseca
dea94622fb scons: Workaround failures with MSVC when using SCons 3.0.[2-4].
This change applies the workaround suggested by Bill Deegan on the
affected SCons versions.

It also adds a comment with the URL explaining why we were using
customizing the decider and max_drift in the first place, as I had
forgotten all about it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109443
Tested-by: liviuprodea@yahoo.com
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 838c0485e0)
2019-03-14 19:03:56 +00:00
Samuel Pitoiset
ce57ea90d3 radv: fix pointSizeRange limits
The values should match the ones that are emitted.

This fixes new CTS dEQP-VK.rasterization.primitive_size.points.*.

Fixes: f4e499ec79 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 6403171843)
2019-03-14 19:03:56 +00:00
Juan A. Suarez Romero
d88857823f anv: destroy descriptor sets when pool gets reset
As stated in Vulkan spec:
   "Resetting a descriptor pool recycles all of the resources from all
    of the descriptor sets allocated from the descriptor pool back to
    the descriptor pool, and the descriptor sets are implicitly freed."

This fixes dEQP-VK.api.descriptor_pool.*

Fixes: 14f6275c92 "anv/descriptor_set: add reference counting for..."
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
(cherry picked from commit 775aabdd01)

Squashed with:

anv: Fix destroying descriptor sets when pool gets reset

pool->next and pool->free_list were reset before their usage in
anv_descriptor_pool_free_set

Fixes: 775aabdd "anv: destroy descriptor sets when pool gets reset"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 9c80be956f)
2019-03-14 19:03:56 +00:00
Emil Velikov
dfcae38dcc cherry-ignore: ignore glsl_types memory cleanup patch
The commit was reverted shortly after it was applied on master

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-14 19:03:56 +00:00
Tapani Pälli
81107c96e6 anv: destroy descriptor sets when pool gets destroyed
Patch maintains a list of sets in the pool and destroys possible
remaining sets when pool is destroyed.

As stated in Vulkan spec:
   "When a pool is destroyed, all descriptor sets allocated from
    the pool are implicitly freed and become invalid."

This fixes memory leaks spotted with valgrind:

   ==19622== 96 bytes in 1 blocks are definitely lost in loss record 2 of 3
   ==19622==    at 0x483880B: malloc (vg_replace_malloc.c:309)
   ==19622==    by 0x495B67E: default_alloc_func (anv_device.c:547)
   ==19622==    by 0x4955E05: vk_alloc (vk_alloc.h:36)
   ==19622==    by 0x4956A8F: anv_multialloc_alloc (anv_private.h:538)
   ==19622==    by 0x4956A8F: anv_CreateDescriptorSetLayout (anv_descriptor_set.c:217)

Fixes: 14f6275c92 ("anv/descriptor_set: add reference counting for descriptor set layouts")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 105002bd2d)
[Emil: move list_del() anv_descriptor_{pool_free_set,set_destroy} ]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/intel/vulkan/anv_descriptor_set.c

---
Mostly a gut feeling - Tapani do we need a list_addtail/list_del in
anv_descriptor_set_create()?
2019-03-14 19:03:56 +00:00
Emil Velikov
5429dd0098 cherry-ignore: add gitlab-ci fixup commit
gitlab-ci: autotools needs to be told which llvm version to use

Commit references invalid sha - the offender did not land in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-14 19:03:56 +00:00
Ian Romanick
b638eb5db4 intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer
In the old code, we would generate the exact same instruction for
extract_u8(some_u64, 0) and extract_u8(some_u64, 1).  The mask-a-word
trick only works for even numbered bytes.

This fixes the (new) piglit test
tests/spec/arb_gpu_shader_int64/execution/fs-ushr-and-mask.shader_test.

v2: Use a SHR instead of an AND.  This saves an instruction compared to
using two moves.  Suggested by Jason.

Fixes: 6ac2d16901 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 55e6454d5e)
[Emil: byte -> byte->u32[0] ]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-14 19:03:56 +00:00
Ian Romanick
8448ece460 intel/fs: nir_op_extract_i8 extracts a byte, not a word
Fixes: 6ac2d16901 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 4aaf139ea4)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/intel/compiler/brw_fs_nir.cpp
2019-03-14 19:03:56 +00:00
Marek Olšák
4f7c54ecce radeonsi: compile clear and copy buffer compute shaders on demand
same as all other shaders

(cherry picked from commit c605738113)
Bug: https://github.com/ValveSoftware/halflife/issues/2100
2019-03-14 19:03:56 +00:00
Emil Velikov
89f3547656 cherry-ignore: add 19.0 only anv/push buffer nominations
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-14 19:03:40 +00:00
Jason Ekstrand
4b372644f3 spirv: Pull offset/stride from the pointer for OpArrayLength
We can't pull it from the variable type because it might be an array of
blocks and not just the one block.  While we're here, throw in some
error checking.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit f1dbc7e97d)
2019-03-14 19:02:42 +00:00
Samuel Pitoiset
079c124bcb radv: properly align the fence and EOP bug VA on GFX9
If alignement is 0, offets returned by
radv_cmd_buffer_upload_alloc() are always 0. These two
virtual addresses were pointing at the same location.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit c2a148692b)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_cmd_buffer.c
2019-03-14 19:02:42 +00:00
Eric Engestrom
238c8c042b egl: fix libdrm-less builds
This function was never used, and isn't properly guarded by HAVE_LIBDRM,
breaking the build on systems that don't have libdrm.

Let's just remove it.

Fixes: 7552fcb7b9 "egl: add base EGL_EXT_device_base implementation"
Reported-by: Timo Aaltonen <tjaalton@debian.org>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit bcc4bfc8e8)
2019-03-14 19:02:42 +00:00
Tapani Pälli
c590c06776 anv: retain the is_array state in create_plane_tex_instr_implicit
This does not seem to fix anything ATM but is the right thing todo.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: f3e91e78a3 ("anv: add nir lowering pass for ycbcr textures")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 33bf3d510c)
2019-03-14 19:02:42 +00:00
Jason Ekstrand
8d21a1f814 spirv: OpImageQueryLod requires a sampler
No idea how this fell through the cracks besides the fact that the
sampler bound at 0 almost always works and the CTS isn't amazing.  In
any case, this appears to have been broken for almost forever.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ca295ddbfb)
2019-03-14 19:02:42 +00:00
Jason Ekstrand
85b165e99c anv: Count surfaces for non-YCbCr images in GetDescriptorSetLayoutSupport
We were accidentally not counting those surfaces

Fixes: ddc4069122 "anv: Implement VK_KHR_maintenance3"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 5049fbddb4)
2019-03-14 19:02:42 +00:00
Axel Davy
dd2554c85b st/nine: Ignore multisample quality level if no ms
Apparently instead of returning error when passing
a quality level different than 0 for
D3DMULTISAMPLE_NONE, we should pass.

Fixes: https://github.com/iXit/Mesa-3D/issues/340

Cc: mesa-stable@lists.freedesktop.org

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
(cherry picked from commit 1d363d440f)
2019-03-14 19:02:42 +00:00
Axel Davy
b1ef1c7a8e st/nine: Ignore window size if error
Check GetWindowInfo and ignore the computed sizes
if there is an error.

Fixes a regression caused by earlier commit when
using old wine gallium nine patches.

Should also address a crash at window destruction.

Related issues:
 https://github.com/iXit/Mesa-3D/issues/331
 https://github.com/iXit/Mesa-3D/issues/332

Cc: mesa-stable@lists.freedesktop.org
Fixes: 2318ca68bb ("st/nine: Handle window resize when a presentation buffer is used")
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
(cherry picked from commit 86666f051e)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/state_trackers/nine/swapchain9.c
2019-03-14 19:02:42 +00:00
Mauro Rossi
a61b634576 android: anv: fix libexpat shared dependency
Fixes undefined reference building errors for XML_* functions

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "19.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit ec0f465bc5)
2019-03-14 19:02:42 +00:00
Mauro Rossi
9814e18700 android: anv: fix generated files depedencies (v2)
Fix anv_extrypoints.{c,h} and anv_extensions.{c,h} missing dependencies
Rename the variable labels according to targets and python scripts
Align the building rules as per Automake for simplification

Fixes building errors during rebuils due to missing dependencies

(v2) Fixed a missing $(VULKAN_API_XML) reference

Fixes: 9a508b7 ("android: anv/extensions: fix generated sources build")
Fixes: dd088d4bec ("anv/extensions: Generate a header file with extension tables")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: "19.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 14e7e26a09)
2019-03-14 19:02:42 +00:00
Ilia Mirkin
7ea6309652 glsl: fix recording of variables for XFB in TCS shaders
This is purely for conformance, since it's not actually possible to do
XFB on TCS output varyings. However we do have to make sure we record
the names correctly, and this removes an extra level of array-ness from
the names in question.

Fixes KHR-GL45.tessellation_shader.single.xfb_captures_data_from_correct_stage

v2: Add comment to the new program_resource_visitor::process function.
    (Ilia Mirkin)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108457
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 4eec3a2a36)
2019-03-14 19:02:23 +00:00
Jose Maria Casanova Crespo
0d0d6f4369 glsl: TCS outputs can not be transform feedback candidates on GLES
Avoids regression on:

KHR-GLES*.core.tessellation_shader.single.xfb_captures_data_from_correct_stage

that is uncovered by the following patch.

"glsl: fix recording of variables for XFB in TCS shaders"

v2: Rebased over glsl: fix recording of variables for XFB in TCS shaders
v3: Move this patch before "glsl: fix recording of variables for XFB in TCS
    shaders" to avoid temporal regressions. (Illia Mirkin)

Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit bf1f49482d)
2019-03-14 19:02:18 +00:00
Ray Zhang
7c3c0823ba glx: fix shared memory leak in X11
call XShmDetach to allow X server to free shared memory

Fixes: bcd80be49a "drisw/glx: use XShm if possible"
Signed-off-by: Ray Zhang <zhanglei002@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b344e32cdf)
2019-03-06 21:35:53 +00:00
Timothy Arceri
8919ea0672 glsl: fix shader cache for packed param list
Some types of params such as some builtins are always padded. We
need to keep track of this so we can restore the list correctly.

Here we also remove a couple of cache entries that are not actually
required as they get rebuilt by the _mesa_add_parameter() calls.

This patch fixes a bunch of arb_texture_multisample and
arb_sample_shading piglit tests for the radeonsi NIR backend.

Fixes: edded12376 ("mesa: rework ParameterList to allow packing")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 7536af670b)
2019-03-06 21:35:53 +00:00
Yevhenii Kolesnikov
24db6eeca1 i965: Fix allow_higher_compat_version workaround limited by OpenGL 3.0
Added check for higher compat profile being allowed
before assigning certain extensions.

Fixes: 272fe94942 (mesa: enable ARB_texture_buffer_* extensions in the Compatibility profile)

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107052
(cherry picked from commit 07f4b4e403)
2019-03-06 21:35:53 +00:00
Bas Nieuwenhuizen
5a7cad3d52 radv: Interpolate less aggressively.
Seems like dxvk used integer builtins without setting the flat
interpolation decoration.

I believe in the current spec the app is required to set these,
but in the meantime to avoid breaking things in stable releases
(and so close to release for 19.0), only expand the interpolation
to float16 and struct (which cannot be builtins as our spirv parser
lowers the builtin block).

Fixes: f324784104 "radv: Allow interpolation on non-float types."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit c0110477b5)
2019-03-06 21:35:53 +00:00
Eleni Maria Stea
6765cee986 i965: fixed clamping in set_scissor_bits when the y is flipped
Calculating the scissor rectangle fields with the y flipped (0 on top)
can generate negative values that will cause assertion failure later on
as the scissor fields are all unsigned. We must clamp the bbox values
again to make sure they don't exceed the fb_height. Also fixed a
calculation error.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108999
          https://bugs.freedesktop.org/show_bug.cgi?id=109594

v2:
   - I initially clamped the values inside the if (Y is flipped) case
   and I made a mistake in the calculation: the clamp of the bbox[2] should
   be a check if (bbox[2] >= fbheight) bbox[2] = fbheight - 1 instead and I
   shouldn't have changed the ScissorRectangleYMax calculation. As the
   fixed code is equivalent with using CLAMP instead of MAX2 at the top of
   the function when bbox[2] and bbox[3] are calculated, and the 2nd is more
   clear, I replaced it. (Nanley Chery)

v3:
   - Reversed the CLAMP change in bbox[3] as the API guarantees that the
   viewport height is positive. (Nanley Chery)

v4:
  - Added nomination for the mesa-stable branch and the link to the second
  bugzilla bug (Nanley Chery)

CC: <mesa-stable@lists.freedesktop.org>
Tested-by: Paul Chelombitko <qamonstergl@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit fd37a19ac4)
2019-03-06 21:35:53 +00:00
Emil Velikov
eb9912b5c7 meson: egl: correctly manage loader/xmlconfig
Earlier commit introduced support for haiku yet did not properly
annotate the loader/xmlconfig dependencies.

Thus we ended up adding inc_loader for each !haiku platform - see
659910eda0 9a96bf0ecd c731508b98 ec6cb01e21.

One piece remained though - the wayland platform. Hence the following
would fail:

 meson -Dgallium-drivers=etnaviv -Ddri-drivers=''\
       -Dtools=etnaviv -Dplatforms=wayland -Dglx=disabled \
       build/

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Reported-by: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 834d221512 ("meson: Add Haiku platform support v4")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit f0a7b463b5)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/egl/meson.build
2019-03-06 21:35:53 +00:00
Samuel Pitoiset
b79bac03c4 radv: don't copy buffer descriptors list for samplers
Sampler descriptors don't have a buffer list.

This fixes some crashes with new CTS
dEQP-VK.binding_model.descriptor_copy.*.sampler_*.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 4924dfc851)
2019-03-06 21:35:53 +00:00
Samuel Pitoiset
0a261496f8 radv: fix out-of-bounds access when copying descriptors BO list
We shouldn't increment the buffer list pointers twice.

This fixes some crashes with new CTS
dEQP-VK.binding_model.descriptor_copy.*.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 9256e0a09d)
2019-03-06 21:35:53 +00:00
Tapani Pälli
b72e2f8600 nir: initialize value in copy_prop_vars_block
Fixes following valgrind warning:

   ==27561== Conditional jump or move depends on uninitialised value(s)
   ==27561==    at 0x667856B: value_set_ssa_components (nir_opt_copy_prop_vars.c:78)
   ==27561==    by 0x667A1C4: copy_prop_vars_block (nir_opt_copy_prop_vars.c:797)

Fixes: 62332d139c "nir: Add a local variable-based copy propagation pass"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit 22267feff1)
2019-03-06 21:35:53 +00:00
Samuel Pitoiset
3c4cc070c1 radv: fix clearing attachments in secondary command buffers
If no framebuffer is bound, get the number of samples and the
image format from the render pass.

This fixes new CTS dEQP-VK.geometry.layered.*.secondary_cmd_buffer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 5671f38085)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_meta_clear.c
2019-03-06 21:35:53 +00:00
Sergii Romantsov
1f09d08a4f d3d: meson: do not prefix user provided d3d-drivers-path
The user can select the location where there d3d drivers
are installed by the d3d-drivers-path meson option.

By default path will be $prefix/$libdir/d3d.

Currently we add $prefix to the user provided path.
Resulting in an incorrect or even missing path.

Based on logic of
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109698
CC: Kenneth Graunke <kenneth@whitecape.org>
CC: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit dcc4866419)
Fixes: b7c6870f87 ("meson: Add moduledir to d3d.pc")
2019-03-06 21:35:53 +00:00
Sergii Romantsov
5ed1b33205 dri: meson: do not prefix user provided dri-drivers-path
The user can select the location where there dri drivers
are installed by the dri-drivers-path meson option.

By default path will be $prefix/$libdir/dri.

Currently we add $prefix to the user provided path.
Resulting in an incorrect or even missing path.

v2: fixed dri_search_path by default, rebased to master

v3: new commit-message (Emil Velikov), cc mesa-stable

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109698
CC: Rafael Antognolli <rafael.antognolli@intel.com>
CC: Dylan Baker <dylan@pnwbakers.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Fixes: 306914db92 (meson: Add dridriverdir variable to dri.pc.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f6556ec7d1)
2019-03-06 21:35:53 +00:00
David Shao
2f67fa564f meson: ensure that xmlpool_options.h is generated for gallium targets that need it
Fixes: 68076b8747 "meson: build gallium vdpau state tracker"
Fixes: 22a817af8a "meson: build gallium xvmc state tracker"
Fixes: 5a785d51a6 "meson: build gallium va state tracker"
Fixes: 0ba909f0f1 "meson: build gallium xa state tracker"
Fixes: 1d36dc674d "meson: build gallium omx state tracker"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 6fa923a65d)
2019-03-06 21:35:53 +00:00
Alok Hota
09542cd070 swr/rast: bypass size limit for non-sampled textures
This fixes a bug where SWR will fail to render in cases with large
buffer allocations, e.g. very large meshes whose vertex buffers exceed
2GB

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit 6053499f2e)
2019-03-06 21:35:53 +00:00
Marek Olšák
483f947a58 tgsi: don't set tgsi_info::uses_bindless_images for constbufs and hw atomics
This might have decreased performance for radeonsi/tgsi, because most
most shaders claimed they used bindless.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit b326a15eda)
2019-03-06 21:35:53 +00:00
Juan A. Suarez Romero
e5bc47ca7d anv: advertise 8 subpixel precision bits
On one side, when emitting 3DSTATE_SF, VertexSubPixelPrecisionSelect is
used to select between 8 bit subpixel precision (value 0) or 4 bit
subpixel precision (value 1). As this value is not set, means it is
taking the value 0, so 8 bit are used.

On the other side, in the Vulkan CTS tests, if the reference rasterizer,
which uses 8 bit precision, as it is used to check what should be the
expected value for the tests, is changed to use 4 bit as ANV was
advertising so far, some of the tests will fail.

So it seems ANV is actually using 8 bits.

v2: explicitly set 3DSTATE_SF::VertexSubPixelPrecisionSelect (Jason)

v3: use _8Bit definition as value (Jason)

v4: (by Jason)
anv: Explicitly set 3DSTATE_CLIP::VertexSubPixelPrecisionSelect

This field was added on gen8 even though there's an identically defined
one in 3DSTATE_SF.

CC: Jason Ekstrand <jason@jlekstrand.net>
CC: Kenneth Graunke <kenneth@whitecape.org>
CC: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 4f917e6a61)
2019-03-06 21:35:53 +00:00
Juan A. Suarez Romero
da4db48c19 genxml: add missing field values for 3DSTATE_SF
Fill out "Vertex Sub Pixel Precision Select" possible values.

CC: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 3b423eeb2d)
2019-03-06 21:35:53 +00:00
Bas Nieuwenhuizen
d9d90ac663 radv: Allow interpolation on non-float types.
In particular structs containing floats and 16-bit floating point
types.

Fixes: 62024fa775 "radv: enable VK_KHR_16bit_storage extension / 16bit storage features"
Fixes: da29594636 "spirv: Only split blocks"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109735
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit f324784104)
2019-03-06 21:35:53 +00:00
Bas Nieuwenhuizen
e8d3c84582 radv: Fix float16 interpolation set up.
float16 types can have non-flat interpolation so set up the HW
correctly for that.

Fixes: 62024fa775 "radv: enable VK_KHR_16bit_storage extension / 16bit storage features"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit a1fdd4a4a7)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_nir_to_llvm.c
2019-03-06 21:35:53 +00:00
Lionel Landwerlin
bd00bd7c59 intel: fix urb size for CFL GT1
Same 192Kb amount as SKL/KBL GT1 applies.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Fixes: de7ed0ba55 ("i965/CFL: Add PCI Ids for Coffee Lake.")
(cherry picked from commit 1d626fc028)
2019-03-06 20:39:34 +00:00
Francisco Jerez
d6a8802aa7 intel/fs: Implement extended strides greater than 4 for IR source regions.
Strides up to 32B can be implemented for the source regions of most
instructions by leveraging either the vertical or the horizontal
stride of the hardware Align1 region.  The main motivation for this is
that currently the lower_integer_multiplication() pass will happily
double the stride of one of the 32-bit sources, which can blow up if
the stride of the original source was already the maximum value
allowed by the hardware.

An alternative would be to use the regioning legalization pass in
order to lower such strides into the composition of multiple legal
strides, but that would be somewhat less efficient.

This showed up as a regression from my commit cbea91eb57
in Vulkan 1.1 CTS tests on CHV/BXT platforms, however it was really a
pre-existing problem that had affected conformance on other platforms
without native support for integer multiplication.  CHV/BXT were
getting around it because the code I removed in that commit had the
"fortunate" side effect of emitting narrower regions that didn't hit
the hardware stride limit after lowering.  Beyond fixing the
regression this fixes ~90 additional Vulkan 1.1 subgroup CTS tests on
ICL (that's why this patch is marked for inclusion in mesa-stable even
though the original regressing patch was not).

According to Jason, a nearly equivalent change had been committed
previously as e8c9e65185 and then (mistakenly?) reverted as
a31d038208.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109328
Reported-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit e03be78252)
2019-03-06 20:39:34 +00:00
Jason Ekstrand
3481eafb8a nir/xfb: Handle compact arrays in gather_xfb_info
This makes us properly handle gl_ClipDistance and gl_CullDistance.

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 1a93fc382b)
2019-03-06 20:39:34 +00:00
Jason Ekstrand
6fb3cec8bc nir/xfb: Work in terms of components rather than slots
We needed to better handle cases where a chunk of a variable starts at
some non-zero location_frac and rolls over into the next slot but may
not be more than 4 dwords.  For example, if gl_CullDistance is an array
of 3 things and has location_frac = 2, it will span across two vec4s but
is not, itself, bigger than a vec4.  If you ignore the clip/cull special
case, it's not allowed to happen for anything else because the only
things that can span more than one slot is dvec3 and dvec4 and they're
both bigger than a vec4.  The current code uses this attrib_slot thing
where we count attribute slots and iterate over them.  However, that
doesn't work in the case above because gl_CullDistance will have an
attrib_slot count of 1 even though it does span two slots.  We could fix
this by adjusting attrib_slot but we already have comp_mask and it's
easier to just handle it that way.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 558c314504)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/nir/nir_gather_xfb_info.c
2019-03-06 20:39:03 +00:00
Jason Ekstrand
8bc0c75e64 nir/xfb: Properly align 64-bit values
Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 8f0fe71cc5)
2019-03-06 20:31:08 +00:00
Jason Ekstrand
910d7fe36c compiler/types: Add a contains_64bit helper
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 30b548fc62)
2019-03-06 20:30:01 +00:00
Andrii Simiklit
20e369fabf i965: re-emit index buffer state on a reset option change.
Seems like we forget to update the index buffer (ib) status and
IndexedDrawCutIndexEnable or CutIndexEnable flag is left unchanged it
leads to ignoring of glEnable/glDisable functions for GL_PRIMITIVE_RESTART
in some cases. The index buffer (ib) status should be re-emmited after the
reset option change to avoid some unexpected behavior.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109451
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
(cherry picked from commit f4f4ec941e)
2019-03-06 11:48:08 +00:00
Carlos Garnacho
036b326e02 wayland/egl: Ensure EGL surface is resized on DRI update_buffers()
Fullscreening and unfullscreening a totem window while playing a video
sometimes results in the video subsurface not changing size along. This
is also reproducible with epiphany.

If a surface gets resized while we have an active back buffer for it, the
resized dimensions won't get neither immediately applied on the resize
callback, nor correctly synchronized on update_buffers(), as the
(now stale) surface size and currently attached buffer size still do match.

There's actually 2 things to synchronize here, first the surface query
size might not be updated yet to the wl_egl_window's (i.e. resize_callback
happened while there is a back buffer), and second the wayland buffers
would need dropping if new surface size differs with the currently attached
buffer. These are done in separate steps now.

https://bugzilla.redhat.com/show_bug.cgi?id=1650929
https://bugs.freedesktop.org/show_bug.cgi?id=109594

Fixes: a9fb331ea7 ("wayland/egl: update surface size on window resize")
Signed-off-by: Carlos Garnacho <carlosg@gnome.org>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Bastien Nocera <hadess@hadess.net>
Tested-by: Denys Kostin <denys.kostin@globallogic.com>
(cherry picked from commit 30a01cd923)
2019-03-06 11:48:01 +00:00
Bas Nieuwenhuizen
9b483d945b radv: Sync ETC2 whitelisted devices.
Fixes: 4bb6c49375 "radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 7631feaa00)
2019-03-06 11:47:50 +00:00
Marek Olšák
c7aeed2925 driconf: add Civ6Sub executable for Civilization 6
I'm getting Civ6Sub instead of Civ6.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit bff8da6c59)
2019-03-06 11:47:28 +00:00
Marek Olšák
d46291c003 radeonsi: always enable NIR for Civilization 6 to fix corruption
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit ae21bdf47c)
2019-03-06 11:47:14 +00:00
Marek Olšák
444d1ccc28 radeonsi: add driconf option radeonsi_enable_nir
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit ccbfe44e5f)
2019-03-06 11:47:03 +00:00
Rhys Perry
c1fa0ec0e5 radv: ensure export arguments are always float
So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.

This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
tests

Fixes: b722b29f10 ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 0ca550e01a)
2019-03-06 11:46:45 +00:00
Rhys Perry
0633c4ef9d radv: bitcast 16-bit outputs to integers
16-bit outputs are stored as 16-bit floats in the outputs array, so they
have to be bitcast.

Fixes: b722b29f10 ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 64065aa504)
2019-03-06 11:46:36 +00:00
Samuel Pitoiset
d0f7e6f218 radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled
This version is better and safer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 47616810ed)
2019-03-06 11:46:30 +00:00
Samuel Pitoiset
242ef8d20b radv: write the alpha channel of MRT0 when alpha coverage is enabled
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 0d8f096293)
2019-03-06 11:46:22 +00:00
Jason Ekstrand
41d78f9ed7 intel/fs: Bail in optimize_extract_to_float if we have modifiers
This fixes a bug in runscape where we were optimizing x >> 16 to an
extract and then negating and converting to float.  The NIR to fs pass
was dropping the negate on the floor breaking a geometry shader and
causing it to render nothing.

Fixes: 1f862e923c "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 367b0ede4d)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/intel/compiler/brw_fs_nir.cpp
2019-03-06 11:45:25 +00:00
Emil Velikov
bfb5bdaa97 docs: add sha256 checksums for 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-18 18:33:16 +00:00
Emil Velikov
b26488dead docs: add release notes for 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-18 18:23:55 +00:00
Emil Velikov
a41881fcaa Update version to 18.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-18 18:19:54 +00:00
Eric Anholt
55f3a4fac3 vc4: Fix copy-and-paste fail in backport of NEON asm fixes.
One of the cpu pointers wasn't marked as read-write, causing gcc to complain:

../src/gallium/drivers/vc4/vc4_tiling_lt.c:181:17: error: output operand constraint lacks ‘=’
                 __asm__ volatile (

Cc: Emil Velikov <emil.l.velikov@gmail.com>
Fixes: 813f0a8296 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
2019-02-16 13:46:37 +00:00
Dylan Baker
d000488c2e meson: Add dependency on genxml to anvil
Currently the Intel "anvil" driver races with the generation of genxml
files, while i965 has an explicit dependency. This patch adds the same
dependency to anvil.

Fixes: d1992255bb
       ("meson: Add build Intel "anv" vulkan driver")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 279060cd32)
2019-02-15 11:40:11 +00:00
Samuel Pitoiset
4aa92b54e5 radv: always export gl_SampleMask when the fragment shader uses it
For some reasons, this breaks trees rendering in Project Cars.

Fixes: 85010585cd ("radv: only enable gl_SampleMask if MSAA is enabled too")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 334da034d8)
2019-02-15 11:40:11 +00:00
Dylan Baker
08ab660bf5 get-pick-list: Add --pretty=medium to the arguments for Cc patches
Because none of them have been picked up for 19.0 due to this bug
being reintroduced.

v2: - Fix fixes tags

Fixes: e6b3a3b201
       ("bin/get-pick-list.sh: handle "typod" usecase.")
Fixes: fac10169bb
       ("bin/get-pick-list.sh: prefix output with "[stable] "")
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit aff52dd2c6)
2019-02-15 11:40:11 +00:00
Oscar Blumberg
4bb51927aa radeonsi: Fix guardband computation for large render targets
Stop using 12.12 quantization for viewports that are not contained in
the lower 4k corner of the render target as the hardware needs to keep
both absolute and relative coordinates representable.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3c540e0a74)
2019-02-15 11:40:11 +00:00
Juan A. Suarez Romero
7662965ce9 anv/cmd_buffer: check for NULL framebuffer
This can happen when we record a VkCmdDraw in a secondary buffer that
was created inheriting from the primary buffer, but with the framebuffer
set to NULL in the VkCommandBufferInheritanceInfo.

Vulkan 1.1.81 spec says that "the application must ensure (using scissor
if neccesary) that all rendering is contained in the render area [...]
[which] must be contained within the framebuffer dimesions".

While this should be done by the application, commit 465e5a86 added the
clamp to the framebuffer size, in case of application does not do it.
But this requires to know the framebuffer dimensions.

If we do not have a framebuffer at that moment, the best compromise we
can do is to just apply the scissor as it is, and let the application to
ensure the rendering is contained in the render area.

v2: do not clamp to framebuffer if there isn't a framebuffer

v3 (Jason):
- clamp earlier in the conditional
- clamp to render area if command buffer is primary

v4: clamp also x and y to render area (Jason)

v5: rename used variables (Jason)

Fixes: 465e5a86 ("anv: Clamp scissors to the framebuffer boundary")
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 1ad26f9417)
2019-02-15 11:40:11 +00:00
Emil Velikov
6cea56e2c2 cherry-ignore: radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
stable The commit addresses functionality not present in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-15 11:40:09 +00:00
Rodrigo Vivi
5b48a26072 intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.
Align with kernel commits:

5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 56c3b4971d)
2019-02-15 11:39:41 +00:00
Mario Kleiner
d3f49ece4e egl/wayland-drm: Only announce formats via wl_drm which the driver supports.
Check if a pixel format is supported by the Wayland servers gpu driver
before exposing it to the client via wl_drm, so we avoid reporting formats
to the client which the server gpu can't handle.

Restrict this reporting to the new color depth 30 formats for now, as the
ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under
the sun.

Atm. this is mostly useful to allow proper PRIME renderoffload for depth
30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop
combo.

Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia
Optimus setup.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 820dfcea43)
2019-02-15 11:39:41 +00:00
Mario Kleiner
ecad528a11 egl/wayland: Allow client->server format conversion for PRIME offload. (v2)
Support PRIME render offload between a Wayland server gpu and a Wayland
client gpu with different channel ordering for their color formats,
e.g., between Intel drivers which currently only support ARGB2101010
and XRGB2101010 import/display and nouveau which only supports ABGR2101010
rendering and display on nv-50 and later.

In the wl_visuals table, we also store for each format an alternate
sibling format which stores colors at the same precision, but with
different channel ordering, e.g., ARGB2101010 <-> ABGR2101010.

If a given client-gpu renderable format is not supported by the server
for import, but the alternate format is supported by the server, expose
the client-gpu renderable format as a valid EGLConfig to the client. At
eglSwapBuffers time, during the blitImage() detiling blit from the client
backbuffer to the linear buffer, the client format is converted to the
server supported format. As we have to do a copy for PRIME anyway,
this channel swizzling conversion comes essentially for free.

Note that even if a server gpu in principle does support sampling
from the clients native format, this conversion will be a performance
advantage if it allows to convert to the servers preferred format
for direct scanout, as the Wayland compositor may then be able to
directly page-flip a fullscreen client wl_buffer onto the primary
plane, or onto a hardware overlay plane, avoiding an extra data copy
for desktop composition.

Tested so far under Weston with: nouveau single-gpu, Intel single-gpu,
AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia
client dGPU for rendering.

v2: Implement minor review comments by Eric Engestrom: Add some
    comment and assert, and some style fixes for clarity.
    No functional change.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit a34b0d68bb)
2019-02-15 11:39:41 +00:00
Iago Toral Quiroga
f036a040bb intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments
The implementation of these opcodes in the generator assumes that their
arguments are packed, and it generates register regions based on that
assumption.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 3918943211)
2019-02-15 11:39:41 +00:00
Samuel Pitoiset
5694279c14 radv: fix compiler issues with GCC 9
"The C standard says that compound literals which occur inside of
the body of a function have automatic storage duration associated
with the enclosing block. Older GCC releases were putting such
compound literals into the scope of the whole function, so their
lifetime actually ended at the end of containing function. This
has been fixed in GCC 9. Code that relied on this extended lifetime
needs to be fixed, move the compound literals to whatever scope
they need to accessible in."

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109543
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 129a9f4937)
2019-02-15 11:39:41 +00:00
Kenneth Graunke
75340edb27 st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048
Piglit's vp-max-array test creates a vertex program containing a uniform
array sized to the value of GL_MAX_NATIVE_PROGRAM_PARAMETERS_ARB.  Mesa
will then add additional state-var parameters for things like the MVP
matrix.

radeonsi currently exposes a value of 4096, derived from constant buffer
upload size.  This means the array will have 4096 elements, and the
extra MVP state-vars would get a prog_src_register::Index of over 4096.

Unfortunately, prog_src_register::Index is a signed 13-bit integer, so
values beyond 4096 end up turning into negative numbers.  Negative
source indexes are only valid for relative addressing, so this ends up
generating illegal IR.

In prog_to_nir, this would cause an out of bounds array access.
st_mesa_to_tgsi checks for a negative value, assumes it's bogus,
and remaps it to parameter 0 in order to get something in-range.
This isn't right - instead of reading the MVP matrix, it would read
the first element of the vertex program's large array.  But the test
only checks that the program compiles, so we never noticed that it
was broken.

This patch limits the size of the program limits, with the understanding
that we may need to generate additional state-vars internally.  i965 has
exposed 1024 for this limit for years, so I don't expect lowering it to
2048 will cause any practical problems for radeonsi or other drivers.

Fixes vp-max-array with prog_to_nir.c.

Cc: "19.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit f45dd6d31b)
2019-02-15 11:39:41 +00:00
Leo Liu
dafa02c980 st/va/vp9: set max reference as default of VP9 reference number
If there is no information about number of render targets

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a0a52a0367)
2019-02-15 11:39:21 +00:00
Leo Liu
36258308a7 st/va: fix the incorrect max profiles report
Add "PIPE_VIDEO_PROFILE_MAX" to enum, so it will make sure here will
be correct when adding more profiles in the future.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109107

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 21cdb828a3)
2019-02-15 11:38:47 +00:00
Marek Olšák
f1eccd091d winsys/amdgpu: don't drop manually added fence dependencies
wow, it's hard to believe that fence and syncobjs dependencies were ignored.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit ddfe209a0d)
2019-02-15 11:38:47 +00:00
Marek Olšák
945aa87408 radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 61c678d4bc)
2019-02-15 11:38:47 +00:00
Marek Olšák
b3b0a97f69 gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 4522f01d4e)
2019-02-15 11:38:47 +00:00
Jason Ekstrand
3545986962 nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks
When nir_rematerialize_derefs_in_use_blocks_impl was first written, I
attempted to optimize things a bit by not bothering to re-materialize
the sources of deref instructions figuring that the final caller would
take care of that.  However, in the case of more complex deref chains
where the first link or two lives in block A and then another link and
the load/store_deref intrinsic live in block B it doesn't work.  The
code in rematerialize_deref_in_block looks at the tail of the chain,
sees that it's already in block B and skips it, not realizing that part
of the chain also lives in block A.

The easy solution here is to just rematerialize deref sources of deref
instructions as well.  This may potentially lead to a few more deref
instructions being created by the conditions required for that to
actually happen are fairly unlikely and, thanks to the caching, it's all
linear time regardless.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109603
Fixes: 7d1d1208c2 "nir: Add a small pass to rematerialize derefs per-block"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 9e6a6ef0d4)
2019-02-15 11:38:47 +00:00
Ilia Mirkin
a9c0e146ef nvc0: we have 16k-sized framebuffers, fix default scissors
For some reason we don't use view volume clipping by default, and use
scissors instead. These scissors were set to an 8k max fb size, while
the driver advertises 16k-sized framebuffers.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit cc79a1483f)
2019-02-15 11:38:47 +00:00
Emil Velikov
541eb984ea cherry-ignore: add more 19.0 only nominations from Ilia
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-15 11:38:13 +00:00
Kristian H. Kristensen
fb63b1b3bf freedreno/a6xx: Emit blitter dst with OUT_RELOCW
We're writing to the bo and the kernel needs to know for
fd_bo_cpu_prep() to work.

Fixes: f93e431272 ("freedreno/a6xx: Enable blitter")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
(cherry picked from commit 357ea7da51)
2019-02-14 12:28:47 +00:00
Bas Nieuwenhuizen
08834a3721 amd/common: Use correct writemask for shared memory stores.
The check was for 1 bit being set, which is clearly not what we want.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 3c24fc64c7)
2019-02-14 12:28:47 +00:00
Bas Nieuwenhuizen
f04d57ff1f radv: Only look at pImmutableSamples if the descriptor has a sampler.
Equivalent of ANV patch c7f4a2867c

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 39ab4e12f7)
2019-02-14 12:28:47 +00:00
Eric Engestrom
45c3bf14ca xvmc: fix string comparison
Fixes: 6fca18696d "g3dvl: Update XvMC unit tests."
Cc: Younes Manton <younes.m@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 40b53a7203)
2019-02-14 12:28:47 +00:00
Eric Engestrom
2180aa1bb2 xvmc: fix string comparison
Fixes: c7b65dcaff "xvmc: Define some Xv attribs to allow users
                             to specify color standard and procamp"
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 110a6e1839)
2019-02-14 12:28:47 +00:00
Bart Oldeman
fdb66dd155 gallium-xlib: query MIT-SHM before using it.
When Mesa is compiled for gallium-xlib using e.g.
./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm
-disable-egl
and is used by an X server (usually remotely via SSH X11 forwarding)
that does not support MIT-SHM such as XMing or MobaXterm, OpenGL
clients report error messages such as
Xlib:  extension "MIT-SHM" missing on display "localhost:11.0".
ad infinitum.

The reason is that the code in src/gallium/winsys/sw/xlib uses
MIT-SHM without checking for its existence, unlike the code
in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c.
I copied the same check using XQueryExtension, and tested with
glxgears on MobaXterm.

This issue was reported before here:
https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a203eaa4f4)
2019-02-14 12:28:47 +00:00
Emil Velikov
e868c77615 cherry-ignore: nv50,nvc0: add explicit settings for recent caps
stable Explicit 19.0 only nomination.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-14 12:28:28 +00:00
Marek Olšák
a19ddce953 meson: drop the xcb-xrandr version requirement
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 1e85cfb91a)
2019-02-12 12:53:18 +00:00
Jason Ekstrand
7bf9cf29dc intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions.  If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.

Fixes: 232ed89802 "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b4f0d062cd)
2019-02-12 12:53:14 +00:00
Ernestas Kulik
e0eba40ae4 v3d: Fix leak in resource setup error path
Reported by Coverity: in the case of unsupported modifier request, the
code does not jump to the “fail” label to destroy the acquired resource.

CID: 1435704
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes: 45bb8f2957 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
(cherry picked from commit 90458bef54)
2019-02-12 12:53:12 +00:00
Ernestas Kulik
1a2b227fce vc4: Fix leak in HW queries error path
Reported by Coverity: in the case where there exist hardware and
non-hardware queries, the code does not jump to err_free_query and leaks
the query.

CID: 1430194
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes: 9ea90ffb98 ("broadcom/vc4: Add support for HW perfmon")
(cherry picked from commit f6e49d5ad0)
2019-02-12 12:53:09 +00:00
Jason Ekstrand
6beaa2d7fb intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
Like all the other sends, it's just mlen * REG_SIZE.

Fixes: 3cbc02e469 "intel: Use TXS for image_size when we have..."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit cf42b0f9e2)
2019-02-12 12:53:06 +00:00
Rob Clark
434f19a8dc freedreno: stop frob'ing pipe_resource::nr_samples
Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to
avoid having to deal with 0 vs 1 everywhere.  But this causes problems
in mesa/st, for example st_finalize_texture() will think there is a
nr_samples mismatch and recreate the texture.  Somehow this manifests
as corrupt x11 font rendering on generations that do not support MSAA
(but apparently works fine on a5xx and a6xx which do support MSAA.)

Fixes: cf0c7258ee freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit c3baa077bf)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/freedreno/freedreno_batch_cache.c
2019-02-12 12:52:32 +00:00
Emil Velikov
7475d7727f docs: add sha256 checksums for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-31 21:08:36 +00:00
Emil Velikov
190a79f462 docs: add release notes for 18.3.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-31 20:58:09 +00:00
Danylo Piliaiev
871aea89fd glsl: Fix copying function's out to temp if dereferenced by array
Function's out variable could be an array dereferenced by an array:
 func(v[w[i]]);
or something more complicated.

Copy index in any case.

Fixes: 76c27e47b9 ("glsl: Copy function out to temp if we don't directly ref a variable")

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 0862929bf6)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109488
Nominated-by: Matt Turner <mattst88@gmail.com>
2019-01-31 12:06:17 +00:00
Timothy Arceri
f2c1d7acd0 glsl: Copy function out to temp if we don't directly ref a variable
Otherwise we can end up with IR that looks like this:

    (
      (declare (temporary ) vec4 f@8)
      (assign  (xyzw) (var_ref f@8)  (var_ref f) )
      (call f16  ((swiz y (var_ref f@8) )))

      (assign  (xyzw) (var_ref f)  (var_ref f@8) )
    ))

When we really need:

      (declare (temporary ) float inout_tmp)
      (assign  (x) (var_ref inout_tmp)  (swiz y (var_ref f) ))
      (call f16  ((var_ref inout_tmp) ))

      (assign  (y) (var_ref f)  (swiz y (swiz xxxx (var_ref inout_tmp) )))
      (declare (temporary ) void void_var)

The GLSL IR function inlining code seemed to produce correct code
even without this but we need the correct IR for GLSL IR -> NIR to
be able to understand whats going on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 76c27e47b9)
Nominated-by: Matt Turner <mattst88@gmail.com>
2019-01-31 12:05:54 +00:00
Tomeu Vizoso
5e8af9e609 etnaviv: Consolidate buffer references from framebuffers
We were leaking surfaces because the references taken in
etna_set_framebuffer_state weren't being released on context destroy.

Instead of just directly releasing those references in
etna_context_destroy, use the util_copy_framebuffer_state helper.

Take the chance to remove the duplicated buffer references in
compiled_framebuffer_state to avoid confusion.

The leak can be reproduced with a client that continuously creates and
destroys contexts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reported-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit bf1dfcc3e8)
[Emil: resolve trivial conflict - dummy_rt does not exist in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/etnaviv/etnaviv_context.c
2019-01-30 17:33:50 +00:00
Eric Anholt
f072585522 vc4: Enable NEON asm on meson cross-builds.
The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson
cross-builds because of the need to run host binaries on the build system.
vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my
cross-builds.

Fixes: ebcb4c2156 ("meson: Enable VC4's NEON assembly support.")
(cherry picked from commit 932ed9c00b)
2019-01-30 17:33:50 +00:00
Vinson Lee
f275e16c9e meson: Fix typo.
meson.build:166:21: ERROR:  Unknown method "verson_compare" for a string.

Fixes: c1efa240c9 ("meson: Add warnings and errors when using ICC")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit be5b271ea7)
2019-01-30 17:33:50 +00:00
Carsten Haitzler (Rasterman)
813f0a8296 vc4: Declare the cpu pointers as being modified in NEON asm.
Otherwise, the compiler is free to reuse the register containing the input
for another call and assume that the value hasn't been modified.  Fixes
crashes on texture upload/download with current gcc.

We now have to have a temporary for the cpu2 value, since outputs must be
lvalues.

(commit message by anholt)

Fixes: 4d30024238 ("vc4: Use NEON to speed up utile loads on Pi2.")
(cherry picked from commit 300d3ae8b1)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/broadcom/common/v3d_cpu_tiling.h

Squashed with commit:

vc4: Declare the last cpu pointer as being modified in NEON asm.

Earlier commit addressed 7 of the 8 instances available.

v2: Rebase patch back to master (by anholt)

Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com>
Cc: Eric Anholt <eric@anholt.net>
Fixes: 300d3ae8b1 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 385843ac3c)

Conflicts:
	src/broadcom/common/v3d_cpu_tiling.h
2019-01-30 17:33:23 +00:00
Carsten Haitzler (Rasterman)
b280cdb59e vc4: Use named parameters for the NEON inline asm.
This makes the asm code more intelligible and clarifies the functional
change in the next commit.

(commit message and commit squashing by anholt)
(cherry picked from commiti 522f688471)
[Emil: apply the patch to vc4_tiling_lt.c instead of v3d_cpu_tiling.h]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
        src/broadcom/common/v3d_cpu_tiling.h
2019-01-29 19:30:12 +00:00
Timothy Arceri
3b9e9e4723 glsl: use remap location when serialising uniform program resource data
This allows us to avoid expensive string compares since we already have
a map to the pointers.

These compares were taking ~30 seconds for a single shader compile
in Godot due to it using 64,000+ uniforms.

Fixes: c4cff5f402 ("glsl: add basic support for resource list to shader cache")

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109229
(cherry picked from commit fb78a6cb72)
2019-01-29 17:44:27 +00:00
Timothy Arceri
12586d5846 radv/ac: fix some fp16 handling
Fixes: b722b29f10 ("radv: add support for 16bit input/output")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 0907ae35ad)
2019-01-29 17:44:27 +00:00
Niklas Haas
e362fe26ea radv: correctly use vulkan 1.0 by default
From the vulkan spec 3.2 "Instances":

"Providing a NULL VkInstanceCreateInfo::pApplicationInfo or providing an
apiVersion of 0 is equivalent to providing an apiVersion of
VK_MAKE_VERSION(1,0,0)."

Fixes: ffa15861ef "radv: UseEnumerateInstanceVersion for the default version."
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit d12dc39396)
2019-01-29 17:44:27 +00:00
Axel Davy
220490cf5f st/nine: Immediately upload user provided textures
Fixes regression caused by
42d672fa6a
st/nine: Bind src not dst in nine_context_box_upload

Before that patch, for user provided textures,
when the texture was destroyed, the safety
check for pending uploads, which according to
the code "Following condition cannot happen currently",
was flushing the queue and thus triggering the upload.

After the patch, the texture destruction was delayed after
the upload. However the user frees the texture buffer,
as it thinks the texture released.

Instead of reverting the faulty patch,
this patch instead flushes the csmt queue right away
after queuing the upload for this type of textures.
This is more future-proof, as we may want to bind the
surface for other reasons in the future.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d7433c22e6)
2019-01-29 17:44:27 +00:00
Dylan Baker
991f9ea553 meson: Add warnings and errors when using ICC
ICC tries to be helpful by not erroring when it sees something that it
doesn't understand, which is completely the opposite of helpful. Meson
0.49.0 does much better at handling this by really trying to make ICC
error, but there are some things in mesa that still get ignored until
0.49.1

v2: - Fix id check, which is 'intel' not 'icc'

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
(cherry picked from commit c1efa240c9)
2019-01-29 17:44:27 +00:00
Lionel Landwerlin
84f59f6bbc anv: fix invalid binding table index computation
The ++ operator strikes again.

Fixes: f92c5bc8f3 ("anv/device: fix maximum number of images supported")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 4149d41f2e)
2019-01-29 17:44:27 +00:00
Emil Velikov
e1374ce107 cherry-ignore: WARNING: Commit XXX lists invalid sha
warn The commits refer stale sha, yet don't fix anything in particular.

98984b7cdd
9f86f1da7c

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-29 17:44:27 +00:00
Timothy Arceri
0b4d381ee0 ac/nir_to_llvm: fix clamp shadow reference for more hardware
Fixes the following piglit test on my VEGA and matches the behaviour in the
tgsi backend.

tests/spec/glsl-1.10/execution/samplers/glsl-fs-shadow2D-clamp-z.shader_test

Fixes: 625dcbbc45 ("amd/common: pass address components individually to ac_build_image_intrinsic")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 5d66f7103f)
2019-01-29 17:44:27 +00:00
Eric Engestrom
6050d6f1cf meson/vdpau: add missing soversion
This mirrors what autotools does in src/gallium/state_trackers/vdpau/Makefile.am
and src/gallium/targets/vdpau/Makefile.am:

  VDPAU_MAJOR = 1
  VDPAU_MINOR = 0
  libvdpau_gallium_la_LDFLAGS = -version-number $(VDPAU_MAJOR):$(VDPAU_MINOR)

Reported-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Fixes: 68076b8747 "meson: build gallium vdpau state tracker"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 69e9440367)
2019-01-29 17:44:27 +00:00
Dylan Baker
cadab68f95 meson: Fix compiler checks for SWR with ICC
This is a bit fragile, as the way this "fixes" the check is to move the
one that we know is correct before the one that is incorrectly reported
as working. In meson 0.49.1 (which isn't out yet) this is fixed that the
incorrect check is reported as a failure.

Fixes: e0b037d697
       ("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109129
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 7cb7f35bc7)
2019-01-29 17:44:27 +00:00
Dylan Baker
8f45b22c11 meson: fix swr KNL build
There's a typo in one of the #defines that breaks compilation.

Fixes: e0b037d697
       ("meson: Build SWR driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109023
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 3ba7ab8d2c)
2019-01-29 17:44:27 +00:00
Dave Airlie
fea0bca1be gallium: use put image shm2 path (v2)
This fixes the drisw paths to use the new shm2 interface, so that
we don't trigger the X server overflow checks when the x offset is non-zero.

This just hides the versioning in drisw, and either passes the src_x
or adds the offset fixup for the fallback path.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit 1f6b92b476)
2019-01-29 17:44:27 +00:00
Dave Airlie
32c0f59c48 glx: add support for putimageshm2 path (v2)
v2: pass x,0 in as the offset coords at glx level not earlier

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit 00af91ca46)
2019-01-29 17:44:27 +00:00
Dave Airlie
2733d26011 dri_interface: add put shm image2 (v2)
This adds a new interface to the swrast interface to fix an shm put image bug.

The current code adds the x,y src offsets into the offset parameters,
however if the x offset is > 0, and the put image copies up to the height
of the image, this can trigger an X server validation check to fail and
the renderering to get BadMatch.

This patch fixes it to pass the x offset coord in as a src x.

We cannot pass the Y coordinate due to the horrible code mangling the
image w/h vs stride in swrastXPutImage.

v2: drop srcx,y from api

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit db83a2b40f)
2019-01-29 17:44:27 +00:00
Marek Olšák
8a6c154496 st/mesa: purge framebuffers when unbinding a context
This fixes pipe_surface "leaks".

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit c89e8470e5)
2019-01-29 17:44:27 +00:00
Rob Clark
9d45651005 loader: fix the no-modifiers case
Normally modifiers take precendence over use flags, as they are more
explicit.  But if the driver supports modifiers, but the xserver does
not, then we should fallback to the old mechanism of allocating a buffer
using 'use' flags.

Fixes: 069fdd5f9f
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
(cherry picked from commit c56fe4118a)
2019-01-29 17:44:27 +00:00
Marek Olšák
77ac39c359 radeonsi: fix rendering to tiny viewports where the viewport center is > 8K
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 4c4c8bb1f0)
2019-01-29 17:44:27 +00:00
Marek Olšák
ae91c29a25 radeonsi: fix a u_blitter crash after a shader with FBFETCH
This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit caa2dcd730)
2019-01-29 17:44:27 +00:00
Jason Ekstrand
b6cd30de3a nir/xfb: Fix offset accounting for dvec3/4
Before, we were double-counting the component slots when we had a dvec3
or dvec4.  Instead, just add them in once and manually offset the
recorded output offset.

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit 4f99ac9144)
2019-01-29 17:44:27 +00:00
Eric Engestrom
a1605e77d2 configure: EGL requirements only apply if EGL is built
Issue was hit with this configuration:
  --disable-{egl,gbm} --with-platform=drm

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 3208fd2e46 ("configure: move platform handling further up")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 610f956fde)
2019-01-29 17:44:27 +00:00
Jason Ekstrand
f5b6f5ad64 anv: Only parse pImmutableSamplers if the descriptor has samplers
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit c7f4a2867c)
2019-01-29 17:44:27 +00:00
Karol Herbst
93db1e7153 glsl/lower_output_reads: set invariant and precise flags on temporaries
fixes a couple of deqp tests (on nvc0 and potential other drivers):
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 987744be98)
2019-01-29 17:44:27 +00:00
Timothy Arceri
313c1487b7 ac/nir_to_llvm: fix interpolateAt* for arrays
This builds on the recent interpolate fix by Rhys ee8488ea3b.

This fixes the arb_gpu_shader5 interpolateAt* tests that contain
arrays.

Fixes: ee8488ea3b ("ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 9e669ed22b)
2019-01-29 17:44:27 +00:00
Karol Herbst
98a661f2b1 nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions
fixes dEQP-GLES2.functional.shaders.invariance.mediump.loop_3

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 30b5c9eda2)
2019-01-29 17:44:27 +00:00
Bas Nieuwenhuizen
ea2bf29ed9 nir: Account for atomics in copy propagation.
Otherwise writes get propagated across atomics if no barrier is
used. Without barrier writes should still be visible in the same
invocation, so an atomic has to be considered a write.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes: b3c6146925 "nir: Copy propagation between blocks"
Fixes: 62332d139c "nir: Add a local variable-based copy propagation pass"
(cherry picked from commit 8424cd8fbd)
2019-01-29 17:44:27 +00:00
Iago Toral Quiroga
252beed945 anv/device: fix maximum number of images supported
We had defined MAX_IMAGES as 8, which we used to size the array for
image push constant data. The comment there stated that this was for
gen8, but anv_nir_apply_pipeline_layout runs for all gens and writes
that array, asserting that we don't exceed that number of images,
which imposes a limit of MAX_IMAGES on all gens.

Furthermore, despite this, we are exposing up to 64 images per shader
stage on all gens, gen8 included.

This patch lowers the number of images we expose in gen8 to 8 and
keeps 64 images for gen9+ while making sure that only pre-SKL gens
use push constant space to handle images.

v2:
 - <= instead of < in the assert (Eric, Lionel)
 - Change the way the assertion is written (Eric)

v3:
 - Revert the way the assertion is written to the form it had in v1,
   the version in v2 was not equivalent and was incorrect. (Lionel)

v4:
 - gen9+ doesn't need push constants for images at all (Jason)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v3)
(cherry picked from commit f92c5bc8f3)
2019-01-29 17:44:27 +00:00
Jason Ekstrand
5f25cfdaf6 anv/nir: Rework arguments to apply_pipeline_layout
Instead of taking a whole pipeline (which could be anything!), just take
a physical device and robust_buffer_access boolean.  This makes it
easier to verify that only the things in the hash actually affect
pipeline compilation.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit a24654b49d)
2019-01-29 17:43:42 +00:00
Eric Anholt
92273935a5 vc4: Don't leak the GPU fd for renderonly usage.
Noticed while debugging V3D -- the ro->gpu_fd was freshly opened in ro
setup, and it needs to stay open until screen close (since it may be used
by renderonly) and should be the same one used by the vc4 screen.

Fixes: 7029ec05e2 ("gallium: Add renderonly-based support for pl111+vc4.")
(cherry picked from commit 99ef66c325)
2019-01-29 15:20:43 +00:00
Dylan Baker
8f1c75e9a0 meson: allow building dri driver without window system if osmesa is classic
This was already enabled for gallium based osmesa with gallium drivers
in 9d10581897, so do the same for classic
driver with classic osmesa.

Fixes: cbbd5bb889
       ("meson: build classic osmesa")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 431e9abaab)
2019-01-29 15:19:49 +00:00
Bruce Cherniak
e38d275a86 gallium/swr: Fix multi-context sync fence deadlock.
Various recreation scenarios lead to API thread getting stuck in
swr_fence_finish().  This is a multi-context issue, whereby one context
overwrites the fence read-value with a previous sync's lesser value.
The fence sync value is supposed to be always increasing.

In swr_fence_cb(), only update the "read" value if the new value is
greater.

(This may seem like we're not waiting on the other context to finish, but
had we needed for it to finish there would have been a wait prior to
submitting a new sync.)

cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ed7673afd2)
2019-01-29 15:19:40 +00:00
Pierre Moreau
f0eee7df43 meson: Fix with_gallium_icd to with_opencl_icd
`with_gallium_icd` is never used throughout the different Meson build
files, whereas `with_opencl_icd` tracks whether or not `gallium-opencl`
was set to "icd".

Fixes: 42ea0631f1
         ("meson: build clover")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 0b736f7fd4)
2019-01-29 15:19:25 +00:00
Bas Nieuwenhuizen
bd9edb5f2e radv: Set partial_vs_wave for pipelines with just GS, not tess.
Looking at -pro we need to enable it for pipelines with just a
GS too.

This seems to reduce the hangs from
https://bugs.freedesktop.org/show_bug.cgi?id=109242 on a RX 550 to
the point where I can't reproduce, after the false start with the
wd_switch_on_eop patch due to flakiness.

(but people are reporting it does not fix the issue completely for
 them on polaris 11)

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 568e7a2998)
2019-01-29 15:19:03 +00:00
Samuel Pitoiset
cad3d0735d radv: clean up setting partial_es_wave for distributed tess on VI
Only needed when the pipeline actually uses tessellation. I don't
think that changes anything, except improving readability.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit d9d14346c2)
2019-01-29 15:18:57 +00:00
Marek Olšák
4b91802bef radeonsi: also apply the GS hang workaround to draws without tessellation
ported from AMDVLK.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 5183e794af)
2019-01-29 15:12:43 +00:00
Bas Nieuwenhuizen
5d2cfa64c1 radv: Only use 32 KiB per threadgroup on Stoney.
Causes hangs on some machines.

What works for dEQP-VK.tessellation.shader_input_output.barrier:

- running num_patches = 6 (which limits LDS to 32 KiB)
- running num_patches = 8, and artificially cutting LDS size at 32 KiB.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 76b12fa564)
2019-01-29 15:12:39 +00:00
Andres Gomez
220705036c bin/get-pick-list.sh: fix redirection in sh
"&>" is bash specific.

Fixes: e0dbfc9953 ("bin/get-pick-list.sh: warn when commit lists invalid sha")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 3ec9ab80b8)
2019-01-29 15:12:36 +00:00
Andres Gomez
fa11468db4 bin/get-pick-list.sh: fix the oneline printing
"--summary" will also print extended header information such as
creations, renames and mode changes.

Let's just use "--no-patch", which suppresses the diff output.

v2: Use "--no-patch" instead of the "-s" abbreviation (Eric).

Fixes: 559c32d241 ("bin/get-pick-list.sh: simplify git oneline printing")
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 716ed41a36)
2019-01-29 15:12:32 +00:00
Emil Velikov
029dced476 cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices
stable The commits aren't suitable in their present form.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-29 15:10:34 +00:00
Emil Velikov
ec40bc62a5 cherry-ignore: radv: Fix multiview depth clears
fixes: This commit requires commits aeaf8dbd09 and 7484bc894b which
did not land in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-29 14:58:58 +00:00
Emil Velikov
8320a07221 docs: add sha256 checksums for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-17 11:30:49 +00:00
Emil Velikov
95a3b709c0 docs: add release notes for 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-17 11:24:36 +00:00
Emil Velikov
0fabb09696 Update version to 18.3.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-17 11:15:36 +00:00
Rhys Perry
f5e752c415 ac: split 16-bit ssbo loads that may not be dword aligned
This ends up refactoring visit_load_buffer() a little.

Fixes: 7e7ee82698 ('ac: add support for 16bit buffer loads')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit bde9f482de)
Note: this is a backport of the above commit provided by Rhys.
2019-01-11 20:35:36 +00:00
Nicolai Hähnle
2a9073301f meson: link LLVM 'native' component when LLVM is available
Linking against LLVM built with BUILD_SHARED_LIBS fails otherwise,
as the component is required for the draw module.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 4275cae95c)
2019-01-11 20:35:36 +00:00
Karol Herbst
0d5511f350 nv50/ir: fix use-after-free in ConstantFolding::visit
opnd() might delete the passed in instruction, but it's used through
i->srcExists() later in visit

v2: use continue instead return
v3: use brackets for the outer if/else chain

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 77944fb2b7)
2019-01-11 20:35:36 +00:00
Jason Ekstrand
79c865f231 intel/peephole_ffma: Fix swizzle propagation
The num_components value passed into get_mul_for_src is used to only
compose the parts of the swizzle that we know will be used so we don't
compose invalid swizzle components.  However, we had a bug where we
passed the number of components of the add all the way through.  For the
given source, we need the number of components read from that source.
In the case where we have a narrow add, say 2 components, that is
sourced from a chain of wider instructions, we may not compose all the
swizzles.  All we really need to do is pass through the right number of
components at each level.

Fixes: 2231cf0ba3 "nir: Fix output swizzle in get_mul_for_src"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 1ede463b6e)
2019-01-11 20:35:35 +00:00
Andres Gomez
37a8e85fa4 glsl/linker: specify proper direction in location aliasing error
The check for location aliasing was always asuming output variables
but this validation is also called for input variables.

Fixes: e2abb75b0e ("glsl/linker: validate explicit locations for SSO programs")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 428164d87f)
2019-01-11 19:19:09 +00:00
Francisco Jerez
78d28da209 intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.
Currently the visitor attempts to enforce the regioning restrictions
that apply to double-precision instructions on CHV/BXT at NIR-to-i965
translation time.  It is possible though for the copy propagation pass
to violate this restriction if a strided move is propagated into one
of the affected instructions.  I've only reproduced this issue on a
future platform but it could affect CHV/BXT too under the right
conditions.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit c301f447ea)
2019-01-11 19:19:09 +00:00
Francisco Jerez
c44c83ddd2 intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.
I triggered this bug while prototyping code for a future platform on
IVB.  Could be a problem today though if a strided move is
copy-propagated into a type-converting move with DF destination.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 464e79144f)
2019-01-11 19:19:09 +00:00
Francisco Jerez
7d5057bfe4 intel/fs: Fix bug in lower_simd_width while splitting an instruction which was already split.
This seems to be a problem in combination with the lower_regioning
pass introduced by a future commit, which can modify a SIMD-split
instruction causing its execution size to become illegal again.  A
subsequent call to lower_simd_width() would hit this bug on a future
platform.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit bc781a0323)
2019-01-11 19:19:09 +00:00
Francisco Jerez
9d8479d632 intel/fs: Implement quad swizzles on ICL+.
Align16 is no longer a thing, so a new implementation is provided
using Align1 instead.  Not all possible swizzles can be represented as
a single Align1 region, but some fast paths are provided for
frequently used swizzles that can be represented efficiently in Align1
mode.

Fixes ~90 subgroup quad swap Vulkan CTS tests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 812ede088f)
2019-01-11 19:19:09 +00:00
Francisco Jerez
10b99dd59d intel/fs: Handle source modifiers in lower_integer_multiplication().
lower_integer_multiplication() implements 32x32-bit multiplication on
some platforms by bit-casting one of the 32-bit sources into two
16-bit unsigned integer portions.  This can give incorrect results if
the original instruction specified a source modifier.  Fix it by
emitting an additional MOV instruction implementing the source
modifiers where necessary.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit c5f9c0009d)
2019-01-11 19:19:09 +00:00
Marek Olšák
fe9ff38d51 st/mesa: don't leak pipe_surface if pipe_context is not current
We have found some pipe_surface leaks internally.

This is the same code as surface_destroy in radeonsi.
Ideally, surface_destroy would be in pipe_screen.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit e986c1ca1d)
2019-01-11 19:19:09 +00:00
Mario Kleiner
78dd4d6536 radeonsi: Fix use of 1- or 2- component GL_DOUBLE vbo's.
With Mesa 18.1, commit be973ed21f, si_llvm_load_input_vs()
changed the number of source 32-bit wide dword components
used for fetching vertex attributes into the vertex shader
from a constant 4 to a variable num_channels number, depending
on input data format, with some special case handling for
input data formats like 64-Bit doubles.

In the case of a GL_DOUBLE input data format with one
or two components though, e.g, submitted via ...

a) glTexCoordPointer(1, GL_DOUBLE, 0, buffer);
b) glTexCoordPointer(2, GL_DOUBLE, 0, buffer);

... the input format would be SI_FIX_FETCH_RG_64_FLOAT,
but no special case handling was implemented for that
case, so in the default path the number of 32-bit
dwords would be set to the number of float input components
derived from info->input_usage_mask. This ends with corrupted
input to the vertex shader, because fetching a 64-bit double
from the vbo requires fetching two 32-bit dwords instead of 1,
and fetching a two double input requires 4 dword fetches
instead of 2, so in these cases the vertex shader receives
incomplete/truncated input data:

a) float v = gl_MultiTexCoord0.x;  -> v.x is corrupted.
b) vec2  v = gl_MultiTexCoord0.xy; -> v.x is assigned
   correctly, but v.y is corrupted.

This happens with the standard TGSI IR compiled shaders.
Under NIR with R600_DEBUG=nir, we got correct behavior
because the current radeonsi nir code always assigns
info->input_usage_mask = TGSI_WRITEMASK_XYZW, thereby
always fetches 4 dwords regardless of what the shader
actually needs.

Fix this by properly assigning 2 or 4 dword fetches for
one or two component GL_DOUBLE input.

Fixes: be973ed21f ("radeonsi: load the right number of
       components for VS inputs and TBOs")

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 5e30e54e05)
2019-01-11 19:19:09 +00:00
Rhys Perry
74c80a0117 ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics
Fixes artifacts in World of Warcraft when Multi-sample Alpha-Test is
enabled with DXVK.
It also fixes artifacts with Fallout 4's god rays with DXVK.
Various piglit interpolateAt*() tests under NIR are also fixed.

v2: formatting fix
    update commit message to include Fallout 4 and the Fixes tag

Fixes: f4e499ec79 ('radv: add initial non-conformant radv vulkan driver')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106595
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit ee8488ea3b)
2019-01-11 19:19:09 +00:00
Dylan Baker
4305b7abc3 autotools: Remove tegra vdpau driver
This has never functioned and probably wont ever function, due to the
way gallium media state trackers are architected and the tegra video
decoder is architected.

Cc: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes: 1755f608f5
       ("tegra: Initial support")
(cherry picked from commit 401dca1c73)
2019-01-11 19:19:09 +00:00
Lionel Landwerlin
57e5fe7074 anv: flush fast clear colors into compressed surfaces
In the following scenario :

   1. Create image format R8G8B8A8_UNORM
   2. Create image view format R8G8B8A8_SRGB
   3. Clear the view through a sub pass to a particular color
   4. Barrier on the image to from color attachment to source transfer
   5. Copy the image into a linear buffer to check the content

The step 4 resolving the clear color is unaware of the SRGB format of
the view, because the blorp resolve operations operate on images the
color associated with the resolve will not operate on SRGB format but
UNORM. Leading to the wrong color being written into surfaces.

This change forces a clear color resolve at the end of the render pass
so following resolves won't have to deal with the clear color with a
format that doesn't match the image's format.

On gfxbench vulkan_5_normal 1280x720, this appear to cost us ~0.5fps,
from 49.316 down to 48.949.

v2: Only fast clear resolve when image & view have different formats
    (Lionel)

v3: Update warning (Jason)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit add5a2ec92)
2019-01-11 19:19:09 +00:00
Lionel Landwerlin
39375bef88 anv: explictly specify format for blorp ccs/mcs op
Resolve operations can happen when dealing with view (begin/end
subpasses) in which case the view's format needs to apply, not the
image's format.

v2: Relayout arguments of a ccs_op() call (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 366eb656ac)
2019-01-11 19:19:09 +00:00
Jason Ekstrand
39b2d2fe08 spirv: Sign-extend array indices
The SPIR-V spec was recently updated to clarify that array indices are
treated as signed integers.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit c59f07684c)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/spirv/vtn_variables.c
2019-01-11 19:19:09 +00:00
Jason Ekstrand
ca8ef8234e anv/apply_pipeline_layout: Set the cursor in lower_res_reindex_intrinsic
The loop through instructions doesn't set the cursor for us so unless we
set it somewhere, we may end up emitting instructions in the wrong
place.  The only reason why we haven't been bitten by this in the past
is that it only happens in a few variable pointers cases and the CTS
tests for those don't use much control flow so things were getting
emitted in the correct order by accident.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit f8992eb5ba)
2019-01-11 19:19:09 +00:00
Jason Ekstrand
484efe75e4 spirv: Handle any bit size in vector_insert/extract
This crops up both in the actual SPIR-V VectorInsert/Extract opcodes as
well as various places where we deal with vector derefs.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit 42b2f3e91f)
2019-01-11 19:19:09 +00:00
Bas Nieuwenhuizen
8d09bd10d2 spirv: Fix matrix parameters in function calls.
They can be handled exactly the same as arrays, we just need to handle
the base type correctly in the switches.

Fixes: a45b6fb452 "spirv: Pass SSA values through functions"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109204
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 70ed049cc6)
2019-01-11 19:19:09 +00:00
Bas Nieuwenhuizen
7f29d45f91 radv: Fix rasterization precision bits.
Note that these limits are exact, not a "precision is at least x",
as texel coords also get snapped to a multiple of this step size
before filtering.

This fixes CTS tests

dEQP-VK.texture.explicit_lod.2d.sizes.31x55_nearest_linear_mipmap_nearest_repeat
dEQP-VK.texture.explicit_lod.2d.sizes.57x35_nearest_linear_mipmap_nearest_repeat

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109151
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 3cc940277a)
2019-01-11 19:19:09 +00:00
Andres Gomez
eac2b2161e glsl: correct typo in GLSL compilation error message
v2: Add the "fix" tag (Erik).

Fixes: 037f68d81e ("glsl: apply align layout qualifier rules to block offsets")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 0cc01f45e7)
2019-01-11 19:19:09 +00:00
Bas Nieuwenhuizen
2f2e8cc2c5 anv/android: Do not reject storage images.
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.

Intel does support storage for some of the support WSI formats, such
as R8G8B8A8_UNORM, and looking at the ISL_SURF_USAGE_DISABLE_AUX_BIT,
the imported images do not have any form of compression that would
prevent this fix.

v2: Also consider STORAGE bit for Gralloc usage bits.
     (From Kevin Strasser <kevin.strasser@intel.com>)

Fixes: 053d4c328f "anv: Implement VK_ANDROID_native_buffer (v9)"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 110564fdec)
2019-01-11 19:19:09 +00:00
Bas Nieuwenhuizen
e5b1fde8c2 radv: Implement buffer stores with less than 4 components.
We started using it in the btoi paths for r32g32b32, and the LLVM IR
checker will complain about it because we end up with intrinsics with
the wrong type extension in the name.

Fixes: 593996bc02 ("radv: implement buffer to image operations for R32G32B32")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 9a45a190ad)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/common/ac_nir_to_llvm.c
2019-01-11 19:19:09 +00:00
Jason Ekstrand
666ffbbae5 intel/blorp: Be more conservative about copying clear colors
In 92eb5bbc68 we attempted to avoid copying clear colors whenever
we weren't doing a resolve.  However, this broke MSAA resolves because
we need the clear color in the source.  This patch makes blorp much more
conservative such that it only avoids the clear color copy if either
aux_usage == NONE or it's explicitly doing a fast-clear.

Fixes: 92eb5bbc68 "intel/blorp: Only copy clear color when doing..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit 19c608fe43)
2019-01-11 19:19:09 +00:00
Caio Marcelo de Oliveira Filho
9ccb447e72 nir: remove dead code from copy_prop_vars
When copy_prop_vars also took care of dead write handling, intrin was
used as part of store_to_entry.  Now it isn't, so this assignment
isn't used really used.  Add a comment clarifying what happens to
intrin.

Fixes: 4dfa7adc10 "nir: Remove handling of dead writes from copy_prop_vars"
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit bbf9ee9b18)
2019-01-11 19:19:09 +00:00
Lionel Landwerlin
6499126ea9 i965: add CS stall on VF invalidation workaround
Even with the previous commit, hangs are still happening. The problem
there is that the VF cache invalidate do happen immediately without
waiting for previous rendering to complete. What happens is that we
invalidate the cache the moment the PIPE_CONTROL is parsed but we
still have old rendering in the pipe which continues to pull data into
the cache with the old high address bits. The later rendering with the
new high address bits then doesn't have the clean cache that it
expects/needs.

v2: Update commit message/explanation with Jason's

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: a363bb2cd0 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit 31e4c9ce40)
2019-01-11 19:19:09 +00:00
Lionel Landwerlin
2a54a90e51 i965: include draw_params/derived_draw_params for VF cache workaround
These buffers are using VB slots and should be included in the
workaround decision.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: a363bb2cd0 ("i965: Allocate VMA in userspace for full-PPGTT systems.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
(cherry picked from commit 92b7407090)
2019-01-11 19:19:09 +00:00
Dylan Baker
cec0f17216 meson: Error out if building nouveau and using LLVM without rtti
Nouveau requires rtti. Often LLVM is configured without rtti, and code
with and without cannot be linked safely. Lets just error out if nouveau
is requested and llvm is built without rtti.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109202
Fixes: c5a97d658e
       ("meson: fix builds against LLVM built without rtti")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit a2596450ac)
2019-01-11 19:19:09 +00:00
Alexander von Gluck IV
65f7c84835 egl/haiku: Fix reference to disp vs dpy
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 00992700c9 "egl: set the EGLDevice when creating a display"
(cherry picked from commit 1b97a72328)
2019-01-11 19:19:09 +00:00
Timothy Arceri
a7a8f906d4 tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()
The previous code used a do while loop and continues after walking
a nested loop/if-statement. This means we end up evaluating the
last instruction from the nested block against the while condition
and potentially exit early if it matches the exit condition of the
outer block.

Fixes: 386d165d8d ("tgsi/scan: add a new pass that analyzes tess factor writes")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 4dda445750)
2019-01-11 19:19:09 +00:00
Timothy Arceri
418fec283c tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()
This just happened not to crash/assert because all loops have at
least 1 if-statement and due to a second bug we end up matching
the same ENDIF to exit both the iteration over the if-statment
and the loop.

The second bug is fixed in the following patch.

Fixes: 386d165d8d ("tgsi/scan: add a new pass that analyzes tess factor writes")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit dd061eb044)
2019-01-11 19:19:09 +00:00
Bas Nieuwenhuizen
efa0c384dc radv: Do a cache flush if needed before reading predicates.
This caused random failures for two conditional rendering tests:

dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_discard
dEQP-VK.conditional_rendering.draw_clear.draw.update_with_rendering_no_discard

These wrote the predicate with the vertex shader, did a barrier and then
started the conditional rendering. However the cache flushes for the barrier
only happen on first draw, so after the predicate has been read.

Fixes: e45ba51ea4 "radv: add support for VK_EXT_conditional_rendering"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8c93ef5de9)
2019-01-11 19:19:09 +00:00
Dylan Baker
99da650b1f meson: Override C++ standard to gnu++11 when building with altivec on ppc64
Otherwise there will be symbol collisions for the vector name.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
Distro Bug: https://bugs.gentoo.org/673622
Fixes: 42ea0631f1
       ("meson: build clover")
Acked-by: Matt Turner <mattst88@gmail.com>

(cherry picked from commit 133a5b8383)
2019-01-11 19:19:09 +00:00
Dave Airlie
7e3fb7c0f9 virgl/vtest: fix front buffer flush with protocol version 0.
Older versions of virglrenderer before 33da7361aec486290df0aec4ad8dfa8ff6adde2c
in vtest mode, misrender gears.

Fixes: 9d81cd8e7c (virgl: Pass resource size and transfer offsets)
Reviewed-By: Gert  Wollny <gert.wollny@collabora.com>
(cherry picked from commit d1ce7eba8b)
2019-01-11 19:19:09 +00:00
Eric Anholt
4569cec173 gallium/ttn: Fix setup of outputs_written.
We need a 64-bit value, otherwise we only handle the low 32, and happen to
sign-extend to claim to write all varying slots if VARYING_SLOT_VAR2 was
used.

Fixes: 4d0b2c7aaa ("ttn: Update shader->info as we generate code.")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit 7d7ecfbcbc)
2019-01-11 19:19:09 +00:00
Lionel Landwerlin
be8c1c8981 anv: don't do partial resolve on layer > 0
We've made the choice not to use fast clears on layer > 0 with
multilayer images. This is partly because we would need to store
multiple clear colors for each layer, making the existing memory
layout, already including aux surfaces, fast clear color, image state,
etc... even more complex.

Partial resolves are the operations transfering the clear colors into
the auxiliary buffers. This operation is currently implemented in
Blorp by loading the clear color from the image's BO, into a shader
that then samples from the auxiliary buffer and writes the color only
if it isn't there already.

The problem here is that because we store only one clear color for all
layers and it is used for partial resolves. If you trigger a partial
clear on a layer > 0, then you're likely to deal with a color that is
not what you actually want. In the particular issues below, we have
multiple layers, each cleared with a different color but the partial
resolve just writes the wrong color into the auxiliary buffers for
layers > 0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108910
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit e2ae5f2f0a)
2019-01-11 19:19:09 +00:00
Axel Davy
5f76202eaf st/nine: Add src reference to nine_context_range_upload
Just like nine_context_box_upload, nine_context_range_upload
should reference the src, which holds the ram source buffer.

Fixes: https://github.com/iXit/Mesa-3D/issues/327
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 104681c5d5)
2019-01-11 19:19:09 +00:00
Axel Davy
bf6f68fc83 st/nine: Bind src not dst in nine_context_box_upload
nine_context_box_upload uploads a ram buffer (from src)
to a pipe_resource (dst).
We already have a refcount on the pipe_resource,
what needs to be protected from release is the ram buffer,
thus a reference to src.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 42d672fa6a)
2019-01-11 19:19:09 +00:00
Axel Davy
df3fd9f738 st/nine: Fix volumetexture dtor on ctor failure
The dtor is called on allocation failure,
thus we must check the volumes are allocated
before trying to release them.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit f91f748fab)
2019-01-11 19:19:08 +00:00
Alex Deucher
00c3af4f0c pci_ids: add new VegaM pci id
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 516160d717)
2019-01-11 19:19:08 +00:00
Emil Velikov
80bea2ba6e glx/test: meson: assorted include fixes
Swap '..' with the symbolic inc_glx and add glproto as dependency. That
will pull the correct include, effectively fixing the tests on macOS.

Fixes: a47c525f32 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit f331419f26)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/glx/tests/meson.build
2019-01-11 19:19:08 +00:00
Emil Velikov
abd89156cf glx: meson: wire up the dispatch-index-check test
Accidentally dropped with earlier commit.!

Fixes: 4ccb981673 ("meson: Use consistent style for tests")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit e139d7a8a3)
2019-01-11 19:19:08 +00:00
Emil Velikov
068d7550fd glx: meson: drop includes from a link-only library
When producing the final libGL.so/libGLX_mesa.so we only link the local
static helper lib (libglx). Thus there's no reason for the includes.

Fixes: a47c525f32 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit b44875e2dc)
2019-01-11 19:19:08 +00:00
Emil Velikov
62e5d649b7 TODO: glx: meson: build dri based glx tests, only with -Dglx=dri
The library itself (libGL) is only built when -Dglx=dri, yet it's
accompanying tests are build even with -Dglx=xlib.

Adjust the guards, so we don't build the tests when they are not
applicable

v2:
 - Reword commit message (Dylan)
 - Drop build_by_default hunk (Dylan)

Fixes: a47c525f32 ("meson: build glx")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 9527f9ea26)
2019-01-11 19:19:08 +00:00
Emil Velikov
1319c87304 pipe-loader: meson: reference correct library
The library is called libgalliumvl_stub - note singular.

Fixes: 42ea0631f1 ("meson: build clover")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 2eedb79e1a)
2019-01-11 19:19:08 +00:00
Emil Velikov
a8c9d5a9a2 meson: don't require glx/egl/gbm with gallium drivers
The gallium drivers do not require a DRI loader. Drop the artificial
and unnecessary restriction.

Fixes: af9d276134 ("meson: build libmesa_gallium")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 9d10581897)
2019-01-11 19:19:08 +00:00
Caio Marcelo de Oliveira Filho
bcfca5b35c nir: properly find the entry to keep in copy_prop_vars
When copy propagation handles a store/copy, it iterates the current
copy entries to remove aliases, but keeps the "equal" entry (if
exists) to be updated.

The removal step may swap the entries around (to ensure there are no
holes), invalidating previous iteration pointers.  The bug was saving
such pointer to use later.  Change the code to first perform the
removals and then find the remaining right entry.

This was causing updates to be lost since they were being made to an
entry that was not part of the current copies.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108624
Fixes: b3c6146925 "nir: Copy propagation between blocks"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 947f7b452a)
2019-01-11 19:19:08 +00:00
Caio Marcelo de Oliveira Filho
3af0438585 nir: properly clear the entry sources in copy_prop_vars
When updating a copy entry source value from a "non-SSA" (the data
come from a copy instruction) to a "SSA" (the data or parts of it come
from SSA values), it was possible to hold invalid data in ssa[0]
depending on the writemask.  Because the union, ssa[0] could contain a
pointer to a nir_deref_instr left-over from previous non-SSA usage.

Change code to clean up the array before use to avoid invalid data
around.

Fixes: 62332d139c "nir: Add a local variable-based copy propagation pass"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 0ddc911f4d)
2019-01-11 19:19:08 +00:00
Vinson Lee
778d11ddd9 meson: Fix libsensors detection.
Fixes: 5e71efef44 ("meson: Add lmsensors support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 0f7ba5758b)
2019-01-11 19:19:08 +00:00
Vinson Lee
f5461577e7 meson: Fix typo.
Fixes: 6b4c7047d5 ("meson: build gallium nine state_tracker")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 84f39e5971)
2019-01-11 19:19:08 +00:00
Ian Romanick
72a6f5d1a3 Revert "nir/lower_indirect: Bail early if modes == 0"
"There's no point in walking the program if we're never going to
    actually lower anything."

Except we might lower compacted local arrays.  In that case, modes will
be 0, but there is still lowering to be done.

This reverts commit 7f75cf2a94.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109081
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 29e4b949b4)
2019-01-11 19:19:08 +00:00
Dylan Baker
336c7bf597 meson: Add toggle for glx-direct
GNU Hurd needs to turn off glx-direct, rather than special case it,
we'll just add a toggle.

CC: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 7a90886921)
2019-01-11 19:19:08 +00:00
Dylan Baker
40c012a5aa meson: Add support for gnu hurd
CC: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 8c77f4c76d)
2019-01-11 19:19:08 +00:00
Dylan Baker
f96bc5357f meson: Fix ppc64 little endian detection
Old versions of meson returned ppc64le as the cpu_family for little
endian power8 cpus, versions >=0.48 don't do this, so the check wouldn't
work in that case. This generalizes the check to work for both old and
new versions of meson.

Fixes: 34bbb24ce7
       ("meson: Add support for ppc assembly/optimizations")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit e430a034b9)
2019-01-11 19:19:08 +00:00
Ian Romanick
e06618ca80 i965/vec4/dce: Don't narrow the write mask if the flags are used
In an instruction sequence like

            cmp(8).ge.f0.0 vgrf17:D, vgrf2.xxxx:D, vgrf9.xxxx:D
    (+f0.0) sel(8) vgrf1:UD, vgrf8.xyzw:UD, vgrf1.xyzw:UD

The other fields of vgrf17 may be unused, but the CMP still needs to
generate the other flag bits.

To my surprise, nothing in shader-db or any test suite appears to hit
this.  However, I have a change to brw_vec4_cmod_propagation that
creates cases where this can happen.  This fix prevents a couple dozen
regressions in that patch.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5df88c20 ("i965/vec4: Rewrite dead code elimination to use live in/out.")
(cherry picked from commit 440c051340)
2019-01-11 19:19:08 +00:00
Rhys Perry
e738fc1ec7 radv: don't set surf_index for stencil-only images
Fixes: f8d5b377c8 ('radv: set cb base tile swizzles for MRT speedups (v4)')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108116
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit bba94a3d85)
2019-01-11 19:19:08 +00:00
Jason Ekstrand
083f5fccb9 nir/constant_folding: Fix source bit size logic
Instead of looking at input_sizes[i] which contains the number of
components for each source, we look at the bit size of input_types[i].
This fixes a regression in the 1-bit boolean series though I have no
idea how we haven't seen it before now.

Fixes: 35baee5dce "nir/constant_folding: fix incorrect bit-size check"
Fixes: 9076c4e289 "nir: update opcode definitions for different bit sizes"
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 3595a0abf4)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/nir/nir_opt_constant_folding.c
2019-01-11 19:19:08 +00:00
Jan Vesely
ce2df23205 clover: Fix build after clang r348827
CodeGenOptions were moved to Basic.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
CC: mesa-stable@lists.freedesktop.org
(cherry picked from commit e4f9a37ace)
2019-01-11 16:43:42 +00:00
Eric Anholt
7d4cad25a6 v3d: Add missing flagging of SYNCB as a TSY op.
Fixes: f2e41daac5 ("broadcom/vc5: Update QPU instruction pack/unpack for v4.2.")
(cherry picked from commit ff80e58b38)
2019-01-11 16:43:42 +00:00
Eric Anholt
efc31a64ee v3d: Make sure that a thrsw doesn't split a multop from its umul24.
The thrsw will invalidate rtop, just like accumulators and flags.  Caught
by simulator assertions in CS imulextended/umulextended tests.

Fixes: 90269ba353 ("broadcom/vc5: Use THRSW to enable multi-threaded shaders.")
(cherry picked from commit 3f9bcf9136)
2019-01-11 16:43:42 +00:00
Alex Deucher
721f667509 pci_ids: add new vega20 pci id
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4db4b3447d)
2019-01-11 16:43:42 +00:00
Alex Deucher
16aa279d8d pci_ids: add new vega10 pci ids
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 56cf25a114)
2019-01-11 16:43:42 +00:00
Dave Airlie
8b7b2222f1 radv/xfb: fix counter buffer bounds checks.
If we gave this function 0 counter buffers, we'd still try and
access pCounterBuffers[0] as this check was incorrect.

Fixes crash with ext_transform_feedback-pipeline-basic-primgen
on zink on radv.

Fixes: 677b496b6 (radv: fix begin/end transform feedback with 0 counter buffers.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit b3f2b03ece)
2019-01-11 16:43:42 +00:00
Emil Velikov
76dd56bfd5 glx: mandate xf86vidmode only for "drm" dri platforms
Currently we have the three dri "platforms" - drm, apple and windows.

Since xf86vidmode is a thing only for the drm one, adjust the
preprocessor guards and correctly check for the dependency.

v2: terminate the GLX_USE_WINDOWSGL hunk

Cc: Jon TURNEY <jon.turney@dronecode.org.uk>
Fixes: 5bc509363b ("glx: make xf86vidmode mandatory for direct rendering")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit a95ec13879)

Squashed with commit:

glx: Fix compilation with GLX_USE_WINDOWSGL

Sadly, the GLX_USE_APPLEGL and GLX_USE_WINDOWSGL cases are not identical
(because GLX_USE_WINDOWSGL uses vtables rather than a maze of ifdefs)

Include <sys/time.h> again, as functions prototyped by it are used in
the GLX_USE_WINDOWSGL path.

Make the include guard around the __glxGetMscRate() definition match the
one at it's declaration again, as it's referenced from dri_common.c
which is built for GLX_USE_WINDOWSGL.

Fixes: a95ec138 ("glx: mandate xf86vidmode only for "drm" dri platforms")
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit d512b35b62)
2019-01-11 16:43:42 +00:00
Erik Faye-Lund
d66fcd1969 virgl: work around bad assumptions in virglrenderer
Virglrenderer does the wrong thing when given an instance divisor;
it tries to use the element-index rather than the binding-index as
the argument to glVertexBindingDivisor(). This worked fine as long
as there was a 1:1 relationship between elements and bindings,
which was the case util 19a91841c3 "st/mesa: Use Array._DrawVAO in
st_atom_array.c.".

So let's detect instance divisors, and restore a 1:1 relationship in
that case. This will make old versions of virglrenderer behave
correctly. For newer versions, we can consider making a better
interface, where the instance divisor isn't specified per element,
but rather per binding. But let's save that for another day.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 19a91841c3 "st/mesa: Use Array._DrawVAO in st_atom_array.c."
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit e888f28d1f)
2019-01-11 16:43:42 +00:00
Erik Faye-Lund
31198005ec virgl: wrap vertex element state in a struct
This just has one member for now; the handle. But this is about to
change.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 8447b64238)
2019-01-11 16:43:42 +00:00
Samuel Pitoiset
52f42f5b63 radv: switch on EOP when primitive restart is enabled with triangle strips
Otherwise, Yakuza hangs the GPU with DXVK. We don't know if
linetrip and pointlist are affected, so my point is to do that
only for triangle strips.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit d8325f1f07)
2019-01-11 16:43:42 +00:00
Emil Velikov
1c70209c6d cherry-ignore: meson: libfreedreno depends upon libdrm (for fence support)
The commit addresses b4476138d5

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-11 16:43:42 +00:00
Rob Clark
7594f63f21 mesa/st/nir: fix missing nir_compact_varyings
LinkedTransformFeedback is normally populated, which had nerf'd varying
packing since the check was introduced.

Fixes: dbd52585fa st/nir: Disable varying packing when doing transform feedback.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit cfe8220904)
2019-01-11 16:43:42 +00:00
Kirill Burtsev
734f78a783 loader: free error state, when checking the drawable type
Currently we distinguish if the drawable is a window or pixmap by
checking xcb_present_select_input throws an error or not.

Yet, we don't always free the error state returned by xcb.

Cc: Kirill Burtsev <kirill.burtsev@qt.io>
Cc: Boyan Ding <boyan.j.ding@gmail.com>
Fixes: 6bd9ba7d07 ("loader: Add dri3 helper")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit a539316485)
2019-01-11 16:43:42 +00:00
Eric Anholt
d1f14bade8 v3d: Fix a leak of the disassembled instruction string during debug dumps.
Fixes: ade416d023 ("broadcom: Add VC5 NIR compiler.")
(cherry picked from commit f1d98204c3)
2019-01-11 16:43:42 +00:00
Eric Anholt
61b8ae8cc8 vc4: Fix a leak of the transfer helper on screen destroy.
Fixes: d009463a65 ("vc4: Switch to using u_transfer_helper for MSAA maps.")
(cherry picked from commit 7f8d8b7d27)
2019-01-11 16:43:42 +00:00
Eric Anholt
638287ba17 v3d: Fix a leak of the transfer helper on screen destroy.
Fixes: 7a30517cce ("broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.")
(cherry picked from commit 3bd73d31a8)
2019-01-11 16:43:42 +00:00
Rob Clark
59c37f2988 freedreno/drm: fix memory leak
Fix an emberrasing memory leak with the non-softpin submit/rb
implementation.

Fixes: f3cc0d2747 freedreno: import libdrm_freedreno + redesign submit
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit d014af98b7)
2019-01-11 16:43:42 +00:00
Emil Velikov
6d3811d82b bin/get-pick-list.sh: warn when commit lists invalid sha
We had cases where people would list old/invalid sha in the commit.
Add a trivial checker to catch those and throw a warning.

CC: Juan A. Suarez <jasuarez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit e0dbfc9953)
2019-01-11 16:43:31 +00:00
Emil Velikov
6486d1c1a3 bin/get-pick-list.sh: rework handing of sha nominations
Currently our is_sha_nomination does:
 - folds any whitespace, attempting to extract sha-like information
 - checks that at least one of the shas has landed

Split it in two and do sha-like validation first.

This way, commits with mesa-stable and sha nominations will feature the
fixes/revert/etc instead of stable (a) or will be omitted if not
applicable for the respective branch (b).

Misc examples from 18.3

(a)
-[   stable ] 5bc509363b glx: make xf86vidmode mandatory for direct rendering
+[    fixes ] 5bc509363b glx: make xf86vidmode mandatory for direct rendering

(b)
-[   stable ] 9a7b319903 anv/query: flush render target before copying results

CC: Juan A. Suarez <jasuarez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6b296f64af)
2019-01-11 16:43:30 +00:00
Emil Velikov
d92c9ba789 docs: add sha256 checksums for 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-11 21:19:03 +00:00
Emil Velikov
f6ad9cf1eb docs: add release notes for 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-11 21:12:55 +00:00
Emil Velikov
0e715ae29b Update version to 18.3.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-11 19:14:22 +00:00
Jason Ekstrand
dff8f3bd0d anv,radv: Disable VK_EXT_pci_bus_info
The Vulkan working group recently discovered that we made a mistake in
assuming that PCI domains are 16-bit even though they can potentially be
32-bit values.  To fix this, the next spec update will change the types
in the VK_EXT_pci_bus_info struct to be 32 bits which will be a
backwards-incompatible change.  Normally, Khronos tries very hard to
never make backwards incompatible changes to specs.  Hopefully, the
extension is new enough (2 months) that there are no shipping apps which
use the extension so this should be safe.

This commit disables the extension for both anv and radv in mesa and
should be back-ported to 18.3 ASAP so we avoid any potential issues with
new apps running on old drivers.  I'll send out a commit (which we can
also back-port to 18.3 if we really care) to re-enable the extension in
both drivers once this week's spec update ships.  The one known use of
this extension is internal to mesa and will continue working with the
extension disabled and will naturally update when we get a new header.

Cc: "18.3" <mesa-stable@lists.freedesktop.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8f401b0ce6)
[Emil: resolve trivial conflict]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/intel/vulkan/anv_extensions.py
2018-12-11 18:00:26 +00:00
Emil Velikov
d81beab96a docs: add sha256 checksums for 18.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-07 11:27:49 +00:00
Emil Velikov
d603cd9d84 docs: update 18.3.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-07 11:20:00 +00:00
Emil Velikov
cb55bc8771 Update version to 18.3.0 (final)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-06 18:03:25 +00:00
Emil Velikov
af223b57a4 Update version to 18.3.0-rc6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-12-05 21:36:54 +00:00
Gurchetan Singh
c694d84f10 virgl: don't mark buffers as unclean after a write
We can mark the buffer unclean if it's ever bound as a TBO,
SSBO, ABO, or image.

This improves

dEQP-GLES3.performance.buffer.data_upload.function_call.map_buffer_range.new_specified_buffer.flag_write_full.stream_draw

from 9.58 MB/s to 451.17 MB/s.

v2: Track buffer cleanliness as a function of bindings (Ilia).
v3: virgl_modify_clean --> virgl_dirty_res (Erik)

Tested-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit 89b4798c06)

With this and previous two patches, the performance of virgl on top of
a r600 (AMD 6870 HD) host improves as follows:

         | FPS avg |  Score
--------------------------------
 before  |   8.2   |   343
 after   |  21.9   |   916

         | FPS avg |  Score
--------------------------------
 before  |  13.2   |   333
 after   |  32.3   |   790
2018-12-05 15:43:48 +00:00
Gurchetan Singh
a69ef11424 virgl: avoid large inline transfers
We flush everytime the command buffer (16 kB) is full, which is
quite costly.

This improves

dEQP-GLES3.performance.buffer.data_upload.function_call.buffer_data.new_buffer.usage_stream_draw

from 111.16 MB/s to 1930.36 MB/s.

In addition, I made the benchmark produce buffers from 0 --> VIRGL_MAX_CMDBUF_DWORDS * 4,
and tried ((VIRGL_MAX_CMDBUF_DWORDS * 4) / 2), ((VIRGL_MAX_CMDBUF_DWORDS * 4) / 4), etc.

I didn't notice any clear differences, so let's just go with the most obvious
heuristic.

Tested-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit d18492c64f)
2018-12-05 15:43:32 +00:00
Gurchetan Singh
4b715e3e59 virgl: quadruple command buffer size
Tested running WebGL aquarium on Nvidia host (10,000 fishes)

This moves us from 7 fps to 9 fps.  After quadrupling, performance
gains diminish.

v2: Remove change ID (Erik)

Tested-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit c0773315af)
2018-12-05 15:37:50 +00:00
Michal Srb
bd7edf473e drisw: Use separate drisw_loader_funcs for shm
The original code was modifying the global drisw_lf variable, which is bad
when there are multiple contexts in single process, each initialized with
different loader. One may support put_image_shm and the other not.

Since there are currently only two possible combinations, lets create two
global tables, one for each. Lets make them const, since we won't change them
and they can be shared.

This fixes crash in VLC. It used two GL contexts (each in different thread), one
was initialized by its Qt GUI, the other by its video output plugin. The first
one set the put_image_shm=drisw_put_image_shm, the second did not, but
since the same structure was used, the drisw_put_image_shm was used too. Then
it crashed because the second loader did not have putImageShm set.

Downstream bug:
https://bugzilla.opensuse.org/show_bug.cgi?id=1113533

v2: Added Fixes and described the VLC bug.

Fixes: 63c427fa71 ("drisw: use putImageShm if available")
Signed-off-by: Michal Srb <msrb@suse.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 63c0916ada)
2018-12-05 13:29:53 +00:00
Michal Srb
a34228e1b0 gallium: Constify drisw_loader_funcs struct
The content is not expected to change.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Michal Srb <msrb@suse.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c0ac038c97)
2018-12-05 13:29:51 +00:00
Samuel Pitoiset
d92bbe54ea radv: wait on the high 32 bits of timestamp queries
In case we are unlucky if the low part is 0xffffffff.

Fixes: 5d6a560a29 ("radv: do not use the availability bit for timestamp queries")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit c7ada4901a)
[Emil: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_query.c
2018-12-05 13:29:16 +00:00
Lionel Landwerlin
54acae83e0 anv/query: flush render target before copying results
This change tracks render target writes in the pipeline and applies a
render target flush before copying the query results to make sure the
preceding operations have landed in memory before the command streamer
initiates the copy.

v2: Simplify logic in CopyQueryResults (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108909
Fixes: 37f9788e9a ("anv: flush pipeline before query result copies")
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 9a7b319903)
2018-12-05 13:20:00 +00:00
Alex Smith
462bc0d5d4 radv: Flush before vkCmdWriteTimestamp() if needed
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool() calls if the shader path
was used to do the reset.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108925
Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit c1b6cb068c)
2018-12-05 13:19:58 +00:00
Samuel Pitoiset
055e0d7126 radv: rework the TC-compat HTILE hardware bug with COND_EXEC
After investigating on this, it appears that COND_WRITE doesn't
work correctly in some situations. I don't know exactly why does
it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK
also uses COND_EXEC I think there is a reason.

Now the driver stores a new metadata value in order to reflect
the last fast depth clear state. If a TC-compat HTILE is fast cleared
with 0.0f, we have to update ZRANGE_PRECISION to 0 in order to
work around that hardware bug.

This fixes rendering issues with The Forest and DXVK and doesn't
seem to introduce any regressions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108914
Fixes: 68dead112e ("radv: update the ZRANGE_PRECISION value for the TC-compat bug")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 824cfc1ee5)
2018-12-05 13:19:55 +00:00
Dave Airlie
5b50e6a7ec radv: use 3d shader for gfx9 copies if dst is 3d
This fixes some crucible 3d miptree tests I've been working on
when executed using the compute shader path.

Fixes: d08f267814 (radv/gfx9: fix 3d image to image transfers on compute queues.)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 1363a47c9c)
2018-12-05 13:19:53 +00:00
Bas Nieuwenhuizen
5594bb584d radv/android: Use buffer metadata to determine scanout compat.
These days we don't always allocate scanout compatible textures anymore.
That does mean we have to fix the radv android WSI though.

Fixes: b1444c9ccb "radv: Implement VK_ANDROID_native_buffer."
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 3bf48741e1)
2018-12-05 13:19:38 +00:00
Bas Nieuwenhuizen
d369bd91c3 radv/android: Mark android WSI image as shareable.
Fixes: b1444c9ccb "radv: Implement VK_ANDROID_native_buffer."
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 51091b3e1f)
2018-12-05 13:19:36 +00:00
Matt Turner
cc45108382 Revert "st/mesa: silenced unhanded enum warning in st_glsl_to_tgsi.cpp"
This reverts commit 198c50f487.

This needs to be reverted after commit 017199d2d2 ("mesa: Revert
INTEL_fragment_shader_ordering support")

(cherry picked from commit dd53bb7e1f)
2018-12-05 13:19:28 +00:00
Matt Turner
babf9ab7da mesa: Revert INTEL_fragment_shader_ordering support
This extension is not properly tested (testing for
GL_ARB_fragment_shader_interlock is not sufficient), and since this was
noted in review on August 28th no tests have been sent.

Revert "i965: Add INTEL_fragment_shader_ordering support."
Revert "mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering"

This reverts commit 03ecec9ed2.
This reverts commit 119435c877.

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 017199d2d2)
2018-12-05 13:19:21 +00:00
Tobias Klausmann
3985a62afc amd/vulkan: meson build - use radv_deps for libvulkan_radeon
Without this the build breaks with:

FAILED: src/amd/vulkan/src@amd@vulkan@@vulkan_radeon@sha/radv_pipeline.c.o
cc -Isrc/amd/vulkan/src@amd@vulkan@@vulkan_radeon@sha -Isrc/amd/vulkan
-I../src/amd/vulkan -Isrc/../include -I../src/../include -Isrc -I../src
-Isrc/mapi -I../src/mapi -Isrc/mesa -I../src/mesa -I../src/gallium/include
-Isrc/gallium/auxiliary -I../src/gallium/auxiliary -Isrc/amd -I../src/amd
-Isrc/amd/common -I../src/amd/common -Isrc/compiler -I../src/compiler
-Isrc/vulkan/util -I../src/vulkan/util -Isrc/vulkan/wsi -I../src/vulkan/wsi
-Isrc/compiler/nir -I../src/compiler/nir -I/usr/include -I/usr/include/libdrm
-fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch
-std=c99 -O2 -g '-DVERSION="18.3.0-rc5"' -DPACKAGE_VERSION=VERSION
'-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa"'
-DGLX_USE_TLS -DHAVE_ST_VDPAU -DENABLE_ST_OMX_BELLAGIO=0
-DENABLE_ST_OMX_TIZONIA=0 -DHAVE_X11_PLATFORM -DGLX_INDIRECT_RENDERING
-DGLX_DIRECT_RENDERING -DGLX_USE_DRM -DHAVE_DRM_PLATFORM -DENABLE_SHADER_CACHE
-DHAVE___BUILTIN_BSWAP32 -DHAVE___BUILTIN_BSWAP64 -DHAVE___BUILTIN_CLZ
-DHAVE___BUILTIN_CLZLL -DHAVE___BUILTIN_CTZ -DHAVE___BUILTIN_EXPECT
-DHAVE___BUILTIN_FFS -DHAVE___BUILTIN_FFSLL -DHAVE___BUILTIN_POPCOUNT
-DHAVE___BUILTIN_POPCOUNTLL -DHAVE___BUILTIN_UNREACHABLE
-DHAVE_FUNC_ATTRIBUTE_CONST -DHAVE_FUNC_ATTRIBUTE_FLATTEN
-DHAVE_FUNC_ATTRIBUTE_MALLOC -DHAVE_FUNC_ATTRIBUTE_PURE
-DHAVE_FUNC_ATTRIBUTE_UNUSED -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT
-DHAVE_FUNC_ATTRIBUTE_WEAK -DHAVE_FUNC_ATTRIBUTE_FORMAT
-DHAVE_FUNC_ATTRIBUTE_PACKED -DHAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL
-DHAVE_FUNC_ATTRIBUTE_VISIBILITY -DHAVE_FUNC_ATTRIBUTE_ALIAS
-DHAVE_FUNC_ATTRIBUTE_NORETURN -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS
-DUSE_X86_64_ASM -DMAJOR_IN_SYSMACROS -DHAVE_SYS_SYSCTL_H -DHAVE_LINUX_FUTEX_H
-DHAVE_ENDIAN_H -DHAVE_DLFCN_H -DHAVE_STRTOF -DHAVE_MKOSTEMP
-DHAVE_POSIX_MEMALIGN -DHAVE_TIMESPEC_GET -DHAVE_MEMFD_CREATE -DHAVE_STRTOD_L
-DHAVE_DLADDR -DHAVE_DL_ITERATE_PHDR -DHAVE_ZLIB -DHAVE_PTHREAD
-DHAVE_PTHREAD_SETAFFINITY -DHAVE_LIBDRM -DHAVE_LLVM=0x0600
-DMESA_LLVM_VERSION_PATCH=1 -DHAVE_WAYLAND_PLATFORM -DWL_HIDE_DEPRECATED
-DHAVE_DRI3 -DHAVE_DRI3_MODIFIERS -Werror=implicit-function-declaration
-Werror=missing-prototypes -Werror=return-type -fno-math-errno
-fno-trapping-math -Wno-missing-field-initializers -Wno-format-truncation -O2
-Wall -D_FORTIFY_SOURCE=2 -fstack-protector-strong -funwind-tables
-fasynchronous-unwind-tables -fstack-clash-protection -DNDEBUG -fPIC -pthread
-D__STDC_FORMAT_MACROS -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS
-D__STDC_LIMIT_MACROS -fvisibility=hidden -Wno-override-init
-DVK_USE_PLATFORM_XCB_KHR -DVK_USE_PLATFORM_XLIB_KHR
-DVK_USE_PLATFORM_WAYLAND_KHR -DVK_USE_PLATFORM_DISPLAY_KHR
-DVK_USE_PLATFORM_XLIB_XRANDR_EXT  -MD -MQ
'src/amd/vulkan/src@amd@vulkan@@vulkan_radeon@sha/radv_pipeline.c.o' -MF
'src/amd/vulkan/src@amd@vulkan@@vulkan_radeon@sha/radv_pipeline.c.o.d' -o
'src/amd/vulkan/src@amd@vulkan@@vulkan_radeon@sha/radv_pipeline.c.o' -c
../src/amd/vulkan/radv_pipeline.c
In file included from ../src/vulkan/util/vk_alloc.h:29,
                 from ../src/amd/vulkan/radv_private.h:52,
                 from ../src/amd/vulkan/radv_debug.h:27,
                 from ../src/amd/vulkan/radv_pipeline.c:30:
../src/../include/vulkan/vulkan.h:54:10: fatal error: wayland-client.h: Datei
oder Verzeichnis nicht gefunden
 #include <wayland-client.h>
          ^~~~~~~~~~~~~~~~~~
compilation terminated.

The above command misses the include directory for wayland:
    -I/usr/include/wayland

The missing include is contained in the (until now) unused radv_deps:

if with_platform_wayland
  radv_deps += dep_wayland_client
  radv_flags += '-DVK_USE_PLATFORM_WAYLAND_KHR'
  libradv_files += files('radv_wsi_wayland.c')
endif

Fixes: 673dda8330 "meson: build "radv" vulkan driver for radeon hardware"
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 9401a2f2e6)
2018-12-03 18:32:04 +00:00
Karol Herbst
a7c4368a66 nv50,nvc0: Fix gallium nine regression regarding sampler bindings
The new approach is that samplers don't get unbound even if they won't be used
in a draw and we should just leave them be as well.

Fixes a regression in multiple windows games using gallium nine and nouveau.

v2: adjust num_samplers to keep track of the highest sampler bound
v3: rework how to set the new value of num_samplers

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106577
Fixes: 4d6fab245e
       "cso: don't track the number of sampler states bound"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit fc0139d283)
2018-12-03 16:41:42 +00:00
Vinson Lee
ab83cfd2bf st/xvmc: Add X11 include path.
This patch fixes this build error.

  CC       tests/xvmc_bench.o
In file included from tests/xvmc_bench.c:35:
tests/testlib.h:38:10: fatal error: 'X11/Xlib.h' file not found
         ^~~~~~~~~~~~

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 4f74580d30)
2018-12-03 16:07:13 +00:00
Lionel Landwerlin
98d571d212 anv: flush pipeline before query result copies
Pipeline state pending bits should be taken into account when copying
results.

In the particular bug below, the results of the
vkCmdCopyQueryPoolResults() command was being overwritten by the
preceding vkCmdCopyBuffer() with a same destination buffer. This is
because we copy the buffers using the 3D pipeline whereas we copy the
query results using the command streamer. Those pieces of HW work in
parallel and the results are somewhat undefined.

v2: Unconditionally flush the pipeline before copying the results
    (Jason)

v3: Wrap & expressions (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108894
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 37f9788e9a)
2018-11-30 16:51:49 +00:00
Thomas Hellstrom
56f90f6213 winsys/svga: Fix a memory leak
The ioctl.cap_3d member was never freed.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 058f85d41c)
2018-11-30 16:51:46 +00:00
Thomas Hellstrom
c2a22a44a1 st/xa: Fix a memory leak
Free the context after destruction.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 7fce3ca375)
2018-11-30 16:51:44 +00:00
Dave Airlie
fe460ee8cd r600: make suballocator 256-bytes align
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108311
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 2ddd44d941)
2018-11-30 16:51:41 +00:00
Emil Velikov
b28aa1178a Update version to 18.3.0-rc5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-29 11:56:27 +00:00
Emil Velikov
bb4bbb5c2d cherry-ignore: egl/wayland: rather obvious build fix
Commit was squashed into the respective offenders

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-28 18:05:05 +00:00
Eric Engestrom
ce6a9169f0 vulkan/wsi: fix s/,/;/ typo
Fixes: 59e58c348e "vulkan/wsi: Only wait on semaphores on the first swapchain"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit e0f1f74eda)
2018-11-28 18:05:05 +00:00
Emil Velikov
bcc8332606 egl/wayland: plug memory leak in drm_handle_device()
As we fail to open the node, we leak the node/device name.

v2: Log and then free() (Eric)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit ce74a7bb8d)
2018-11-28 18:05:05 +00:00
Emil Velikov
ace4860a4f egl/wayland: bail out when drmGetMagic fails
Currently as the function fails, we pass uninitialized data to the
authentication function. Stop doing that and print an warning when
the function fails.

v2: Plug memory leak in error path (Eric)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit c59d3aa4b9)
2018-11-28 17:41:53 +00:00
Eric Engestrom
41671f5dc0 wsi/display: fix mem leak when freeing swapchains
Fixes: da997ebec9 "vulkan: Add KHR_display extension using DRM [v10]"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
(cherry picked from commit 9575cd2893)
2018-11-28 17:03:40 +00:00
Bas Nieuwenhuizen
ec659efcba radv: Align large buffers to the fragment size.
Improves performance in Talos by about 15% (and significant improvements
in RotR and possibly other but did not bench with final patch) on
kernel 4.19 and earlier.

On 4.20+ a similar effect comes from

433ca054949a "drm/amdgpu: try allocating VRAM as power of two"

v2: Do not impact the alignment of the physical memory.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6569644bb6)
2018-11-28 17:03:38 +00:00
Bas Nieuwenhuizen
a1f6ae4e27 radv: Clamp gfx9 image view extents to the allocated image extents.
Mirrors AMDVLK. Looks like if we go over the alignment of height
we actually start to change the addressing. Seems like the extra
miplevels actually work with this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108245
Fixes: f6cc15dccd "radv/gfx9: fix block compression texture views. (v2)"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 08ea6b9d9b)
2018-11-27 12:04:31 +00:00
Eric Engestrom
a32c568d39 anv: correctly use vulkan 1.0 by default
Per chapter 3.2 "Instances":
> Providing a NULL VkInstanceCreateInfo::pApplicationInfo or providing
> an apiVersion of 0 is equivalent to providing an apiVersion of
> VK_MAKE_VERSION(1,0,0).

Reported-by: Niklas Haas <git@haasn.xyz>
Fixes: 8c048af589 "anv: Copy the appliation info into the instance"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 56d126f8fd)
2018-11-27 12:04:25 +00:00
Erik Faye-Lund
d575455be6 mesa/main: fix incorrect depth-error
If glGetTexImage or glGetnTexImage is called with a level that doesn't
exist, we get an error message on this form:

Mesa: User error: GL_INVALID_VALUE in glGetTexImage(depth = 0)

This is clearly nonsensical, because these APIs don't even have a
depth-parameter. The reason is that get_texture_image_dims() return
all-zero dimensions for non-existent texture-images, and we go on to
validate these dimensions as if they were user-input, because
glGetTextureSubImage requires checking.

So let's split this logic in two, so glGetTextureSubImage can have
stricter input-validation. All arguments that are no longer validated
are generated internally by mesa, so there's no use in validating them.

Fixes: 42891dbaa1 "gettextsubimage: verify zoffset and depth are correct"
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit c120dbfe4d)
2018-11-26 15:50:30 +00:00
Erik Faye-Lund
7d8a9087ae mesa/main: check cube-completeness in common code
This check is the only part of dimensions_error_check that isn't about
error-checking the offset and size arguments of
glGet[Compressed]TextureSubImage(), so it doesn't really belong in here.

This doesn't make a difference right now, apart for changing the
presedence of this error. But it will make a difference  for the next
patch, where we no longer call this method from the non-sub tex-image
getters.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 38af69adfa)
2018-11-26 15:50:29 +00:00
Erik Faye-Lund
5598426132 mesa/main: factor out common error-checking
This error checking is the same for teximage and texsubimage getters, so
let's factor it out to its own function.

This will be useful when getteximage and gettexsubimage gets their own
error checking routines a bit later.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 42820c5727)
2018-11-26 15:50:28 +00:00
Erik Faye-Lund
35e9cd3428 mesa/main: factor out tex-image error-checking
This will be useful when we split error-checking for getteximage and
gettexsubimage later.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 5e0a84f31c)
2018-11-26 15:50:26 +00:00
Erik Faye-Lund
1a905e4c5b mesa/main: remove bogus error for zero-sized images
The explanation quotes the spec on the following wording to justify the
error:

"An INVALID_VALUE error is generated if xoffset + width is greater than
 the texture’s width, yoffset + height is greater than the  texture’s
 height, or zoffset + depth is greater than the texture’s depth."

However, this shouldn't generate an error in the case where *all three*
of width, xoffset and the texture's width are zero. In this case, we end
up generating an unspecified error.

So let's remove this check, and instead make sure that we consider this
as an empty texture.

So let's not generate an error, there's non mandated in the spec in
xoffset/yoffset/zoffset = 0 case. We already avoid doing any work in
this case, because of the final, non-error generating check in this
function.

Fixes: b37b35a5d2 "getteximage: assume texture image is empty for non defined levels"
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 38bbb61252)
2018-11-26 15:37:07 +00:00
Gert Wollny
6b9b7ce38c glsl: free or reuse memory allocated for TF varying
When a shader program is de-serialized the gl_shader_program passed in
may actually still hold memory allocations for the transform feedback
varyings. If that is the case, free the varying names and reallocate
the new storage for the names array.

This fixes a memory leak:
Direct leak of 48 byte(s) in 6 object(s) allocated from:
 in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880)
 in transform_feedback_varyings ../../samba/mesa/src/mesa/main/transformfeedback.c:875
 in _mesa_TransformFeedbackVaryings ../../samba/mesa/src/mesa/main/transformfeedback.c:985
 ...
Indirect leak of 42 byte(s) in 6 object(s) allocated from:
  in __interceptor_strdup (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0x761c8)
  in transform_feedback_varyings ../../samba/mesa/src/mesa/main/transformfeedback.c:887
  in _mesa_TransformFeedbackVaryings ../../samba/mesa/src/mesa/main/transformfeedback.c:985

Fixes: ab2643e4b0
   glsl: serialize data from glTransformFeedbackVaryings

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit f5d053702f)
2018-11-26 15:37:05 +00:00
Bas Nieuwenhuizen
02566b9725 radv: Fix opaque metadata descriptor last layer.
We used the layer count which results in an off by one error.

Not sure this really affects anything.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3c96a1e3a9)
2018-11-26 15:37:02 +00:00
Marek Olšák
825cb76860 winsys/amdgpu: fix a device handle leak in amdgpu_winsys_create
Cc: 18.2 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit d4e7d8b7f0)
2018-11-26 15:37:00 +00:00
Marek Olšák
a941399117 winsys/amdgpu: fix a buffer leak in amdgpu_bo_from_handle
Cc: 18.2 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 82aa07f81f)
2018-11-26 15:36:33 +00:00
Eric Engestrom
f7040d9107 glapi: add missing visibility args
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108829
Fixes: 3218056e0e "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 896c59d690)
2018-11-23 11:50:36 +00:00
Jason Ekstrand
b8502f1517 anv: Put robust buffer access in the pipeline hash
It affects apply_pipeline_layout.  Shaders compiled with the wrong value
will work but they may not be robust as requested by the app.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 617e402b3d)
2018-11-22 16:04:58 +00:00
Emil Velikov
33f1569f02 Update version to 18.3.0-rc4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-22 13:08:25 +00:00
Gert Wollny
3dd73ab248 r600: clean up the GS ring buffers when the context is destroyed
This fixes two memory leaks reported by ASAN:

Direct leak of 248 byte(s) in 1 object(s) allocated from:
   in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880)
   in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578
   in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600
   in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265
   in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:725
   in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291
   in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1482

Direct leak of 248 byte(s) in 1 object(s) allocated from:
   in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880)
   in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578
   in r600_buffer_create ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:600
   in r600_resource_create_common ../../samba/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1265
   in r600_resource_create ../../samba/mesa/src/gallium/drivers/r600/r600_pipe.c:722
   in pipe_buffer_create ../../samba/mesa/src/gallium/auxiliary/util/u_inlines.h:291
   in update_gs_block_state ../../samba/mesa/src/gallium/drivers/r600/r600_state_common.c:1489

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Fixes: 1371d65a7f
  r600g: initial support for geometry shaders on evergreen (v2)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 61b535437e)
2018-11-22 13:08:25 +00:00
Marek Olšák
3036ffa1a2 radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSED
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102597

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ea9f95e2a6)
2018-11-22 13:08:25 +00:00
Andrii Simiklit
8168ee7712 i965/batch: avoid reverting batch buffer if saved state is an empty
There's no point reverting to the last saved point if that save point is
the empty batch, we will just repeat ourselves.

v2: Merge with new commits, changes was minimized, added the 'fixes' tag
v3: Added in to patch series
v4: Fixed the regression which was introduced by this patch
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630
    Reported-by:  Mark Janes <mark.a.janes@intel.com>
    The solution provided by: Jordan Justen <jordan.l.justen@intel.com>

CC: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 3faf56ffbd "intel: Add an interface for saving/restoring
                     the batchbuffer state."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107626
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 (fixed in v4)
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b787dcf57b)
2018-11-20 20:36:50 +00:00
Emil Velikov
1869f3f6af travis: adding missing x11-xcb for meson+vulkan
Required by the x11 WSI

Fixes: df82012b2c ("travis: add meson build for vulkan drivers.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 982e012b3a)
2018-11-20 11:20:50 +00:00
Emil Velikov
200004fe03 glx: make xf86vidmode mandatory for direct rendering
Currently we detect the module and if missing, the glXGetMsc* API is
effectively a stub, always returning false.

This is what effectively has been happening with our meson build :-(

Thus users have no chance of using it - they cannot even distinguish
if the failure is due to a misconfigured build.

There's no reason for keeping xf86vidmode optional - it has been
available in all distributions for years.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: a47c525f32 "meson: build glx"
(cherry picked from commit 5bc509363b)
2018-11-20 11:20:47 +00:00
Emil Velikov
d7795a8431 travis: drop unneeded x11proto-xf86vidmode-dev
The only place where the package is needed is for building the DRI
based libGL library.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 84445a86d1)
2018-11-20 11:20:45 +00:00
Nicolai Hähnle
e299f1ba59 radeonsi: fix an out-of-bounds read reported by ASAN
We read 4 values out of sample_locs_8x, so make sure the array is
big enough.

Fixes: ac76aeef20 ("radeonsi: switch back to standard DX sample positions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 46a59ce026)
2018-11-20 10:56:48 +00:00
Lionel Landwerlin
2e393b483d egl/dri: fix error value with unknown drm format
According to the EGL_EXT_image_dma_buf_import spec, creating an EGL
image with a DRM format not supported should yield the BAD_MATCH
error :

"
       * If <target> is EGL_LINUX_DMA_BUF_EXT, and the EGL_LINUX_DRM_FOURCC_EXT
         attribute is set to a format not supported by the EGL, EGL_BAD_MATCH
         is generated.
"

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 20de7f9f22 ("egl/dri2: support for creating images out of dma buffers")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
(cherry picked from commit 1c56d21156)
2018-11-20 10:56:45 +00:00
Emil Velikov
4b3f884673 Update version to 18.3.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-16 11:58:55 +00:00
Connor Abbott
65926d5d94 Revert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT"
This reverts commit 647c2b90e9. There was
one recently-introduced bug in ac for dvec3 loads, but the other test
failures were actually bugs in the tests. See
9429e621c4

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit ba94a00c7c)
2018-11-16 10:24:33 +00:00
Eric Anholt
f25fb52eae vc4: Make sure we make ro scanout resources for create_with_modifiers.
The DRI3 create_with_modifiers paths don't set tmpl.bind to SCANOUT or
SHARED, with the theory that given that you've got modifiers, that's all
you need.  However, we were looking at the tmpl.bind for setting up the
KMS handle in the renderonly case, so we'd end up trying to use vc4's
handle on the hx8357d fd.

Fixes: 84ed8b67c5 ("vc4: Set shareable BOs as T tiled if possible")
(cherry picked from commit cc0bc76a38)
2018-11-16 10:24:33 +00:00
Danylo Piliaiev
0b48c82ad9 i965: Fix calculation of layers array length for isl_view
Handle all cases in calculation of layers count for isl_view
taking into account texture view and image unit.
st_convert_image was taken as a reference.

When u->Layered is true the whole level is taken with respect to
image view. In other case only one layer is taken.

v3: (Józef Kucia and Ilia Mirkin)
    - Rewrote patch by taking st_convert_image as a reference
    - Removed now unused get_image_num_layers function
    - Changed commit message

v4: (Jason Ekstrand)
    - Added assert

Fixes: 5a8c8903
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit f9fd0cf479)
2018-11-16 10:24:33 +00:00
Jason Ekstrand
087f1534ae nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16
It messes up when trying to lower.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 4266932c0b)
2018-11-16 10:24:33 +00:00
Eric Engestrom
a57a727617 egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache
Fixes dEQP-EGL.functional.get_proc_address.extension.egl_android_blob_cache
on builds with glvnd enabled.

Fixes: 6f5b57093b "egl: add support for EGL_ANDROID_blob_cache"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c973364967)

Squashed with commit:

egl: fix bad rebase

I screwed up a rebase over a refactor and didn't notice locally because
the uncommitted refactor hid the issue.

Fixes: c973364967 "egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 2b2f790e59)
2018-11-16 10:24:23 +00:00
Marek Olšák
971ce9f854 radeonsi: fix video APIs on Raven2
This was missed when I added the new enum.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Leo Liu <leo.liu@amd.com>
(cherry picked from commit 9367514524)
2018-11-16 10:22:08 +00:00
Emil Velikov
bfe7eda028 bin/get-pick-list.sh: handle reverts prior to the branchpoint
Currently we detect when a breaking commit:
 - has landed in stable, and
 - is referenced by a untagged fix in master

Yet we did not consider the case of breaking commit:
 - prior to the branchpoint, and
 - is referenced by a untagged fix in master

Addressing the latter is extremely slow, due to the size of the lookup.

That said, we can trivially use the existing is_sha_nomination() helper
to catch reverts.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit adbdfc6666)
2018-11-16 10:22:00 +00:00
Emil Velikov
221a8e3366 bin/get-pick-list.sh: use test instead of [ ]
Latter is rather picky wrt surrounding white space. The explicit `test`
doesn't have that problem, plus the statements read a bit easier.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c0012a0708)
2018-11-15 15:57:37 +00:00
Emil Velikov
c8fef27cd3 bin/get-pick-list.sh: handle unofficial "broken by" tag
We have a number of cases were devs will use a tag "broken by".
While it's not something officially documented or recommended, checking
for it is trivial enough.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 77ff0bfb5f)
2018-11-15 15:57:37 +00:00
Emil Velikov
4505df1676 bin/get-pick-list.sh: handle fixes tag with missing colon
Every so often, we forget to add the colon after "fixes". Trivially
tweak the script to catch it.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 209525aafb)
2018-11-15 15:57:37 +00:00
Emil Velikov
8b5ce5fa70 bin/get-pick-list.sh: flesh out is_sha_nomination
Refactor is_fixes_nomination into a is_sha_nomination helper. This way
we can reuse it for more than the usual "Fixes:" tag.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b7418d1f3f)
2018-11-15 15:57:37 +00:00
Emil Velikov
cfd333c768 bin/get-pick-list.sh: tweak the commit sha matching pattern
Currently we match on:
 - any arbitrary length of,
 - any a-z A-Z and 0-9 characters

At the same time, a commit sha consists of lowercase hexadecimal
numbers. Any sha shorter than 8 characters is ambiguous - in some cases
even 11+ are required.

So change the pattern to a-f0-9 and adjust the length to 8-40.

As we're here we could use a single grep, instead of the grep/sed combo.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 533fead423)
2018-11-15 15:57:37 +00:00
Emil Velikov
3853b9c14d bin/get-pick-list.sh: handle the fixes tag
Having a separate script to handle the fixes tag, brings a number of
issues, so let's fold it in get-pick-list.sh.

v2:
 - pass the sha as argument to the function
 - Keep original sed pattern

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 181203f3c5)
2018-11-15 15:57:37 +00:00
Emil Velikov
98c0d87acd bin/get-pick-list.sh: handle "typod" usecase.
As the comment in get-typod-pick-list.sh says, there's little point in
having a duplicate file.

Add the new pattern + tag to get-pick-list.sh and nuke this file.

v2:
 - pass the sha as argument to the function
 - grep -q instead of using a variable (Eric)

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit e6b3a3b201)
2018-11-15 15:57:37 +00:00
Emil Velikov
fc99358bdc bin/get-pick-list.sh: prefix output with "[stable] "
With later commits we'll fold all the different scripts into one.
Add the explicit prefix, so that we know the origin of the nomination

v2:
 - pass the sha as argument to the function
 - swap $tag = none for an else statment (Juan)
 - grep -q instead of using a variable (Eric)
 - print the tag and commit oneline separately (Eric)

v3:
 - drop unused "tag=none" assignment (Juan)
 - typo nomination

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v2)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit fac10169bb)
2018-11-15 15:57:37 +00:00
Emil Velikov
9650fc05a5 bin/get-pick-list.sh: simplify git oneline printing
Currently we force disable the pager via "|cat" where --no-pager
exists. Additionally we could use git show instead of git log -n1.

Use those for a slightly more understandable code.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 559c32d241)
2018-11-15 15:57:37 +00:00
Karol Herbst
e1dc5715b2 nir/spirv: cast shift operand to u32
v2: fix for specialization constants as well

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Karol Herbst <kherbst@redhat.com>
(cherry picked from commit b4380cb070)
2018-11-14 18:53:02 +00:00
Eric Engestrom
fbe2a54991 meson: fix wayland-less builds
Those empty variables in the !wayland case are useless and running that
meson.build with them breaks the build:

  [287/850] Generating wayland-drm-client-protocol.h with a custom command.
  FAILED: src/egl/wayland/wayland-drm/wayland-drm-client-protocol.h
  client-header ../src/egl/wayland/wayland-drm/wayland-drm.xml src/egl/wayland/wayland-drm/wayland-drm-client-protocol.h
  /bin/sh: client-header: command not found
  ninja: build stopped: subcommand failed.

Fixes: d1992255bb "meson: Add build Intel "anv" vulkan driver"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 4fa2fb3524)
2018-11-14 18:53:02 +00:00
Eric Engestrom
940d3a4ef8 gbm: remove unnecessary meson include
`inc_wayland_drm` is only used if wayland is built, and it's already
added in that case a few lines below.

Fixes: a29869e872 "gbm: Don't traverse backwards for includes"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 7df80de6e6)
2018-11-14 18:53:02 +00:00
Eric Engestrom
9d92b603f1 meson: only run vulkan's meson.build when building vulkan
Fixes: d1992255bb "meson: Add build Intel "anv" vulkan driver"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 3832db275e)
2018-11-14 18:53:02 +00:00
Gert Wollny
e2494a9387 mesa: Reference count shaders that are used by transform feedback objects
Transform feedback objects may hold a pointer to a shader program, and
at least in Gallium, this must be a valid pointer until
ctx->Driver.EndTransformFeedback in glEndTransformFeedback has been called
- which is conform with the spec that any program that is part of a
current rendering state should only be flagged for deletion by glDeleteProgram.
This was not handled properly for the transform feedback objects so that
a call sequence

  glUseProgram(x)
  glBeginTransformFreedback(...)
  glPauseTransformFeedback(...)
  glDeleteProgram(x)
  glEndTransformFeedback(...)

would result in a use after free bug. With this patch the transform
feedback object also updates the reference count to the used program
thereby keeping the program valid as long as the transform feedback
objects links to it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108713
Fixes: 654587696b
       mesa: add end_transform_feedback() helper

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit caa964b422)
2018-11-14 18:53:02 +00:00
Samuel Pitoiset
8a79c536d5 radv: binding streamout buffers doesn't change context regs
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit b5f213bb1d)
2018-11-14 18:53:02 +00:00
Matt Turner
cc572038bf util/ralloc: Make sizeof(linear_header) a multiple of 8
Prior to this patch sizeof(linear_header) was 20 bytes in a
non-debug build on 32-bit platforms. We do some pointer arithmetic to
calculate the next available location with

   ptr = (linear_size_chunk *)((char *)&latest[1] + latest->offset);

in linear_alloc_child(). The &latest[1] adds 20 bytes, so an allocation
would only be 4-byte aligned.

On 32-bit SPARC a 'sttw' instruction (which stores a consecutive pair of
4-byte registers to memory) requires an 8-byte aligned address. Such an
instruction is used to store to an 8-byte integer type, like intmax_t
which is used in glcpp's expression_value_t struct.

As a result of the 4-byte alignment returned by linear_alloc_child() we
would generate a SIGBUS (unaligned exception) on SPARC.

According to the GNU libc manual malloc() always returns memory that has
at least an alignment of 8-bytes [1]. I think our allocator should do
the same.

So, simple fix with two parts:

   (1) Increase SUBALLOC_ALIGNMENT to 8 unconditionally.
   (2) Mark linear_header with an aligned attribute, which will cause
       its sizeof to be rounded up to that alignment. (We already do
       this for ralloc_header)

With this done, all Mesa's unit tests now pass on SPARC.

[1] https://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html

Fixes: 47e1758692 ("glcpp: use the linear allocator for most objects")
Bug: https://bugs.gentoo.org/636326
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit efb1ccadca)

Conflicts:
	src/util/ralloc.c
2018-11-14 18:53:02 +00:00
Dylan Baker
ad99afdce6 meson: fix libatomic tests
There are two problems:
1) the extra underscore in MISSING_64BIT_ATOMICS
2) we should link with libatomic if the previous test decided we needed
   it

Fixes: d1992255bb
       ("meson: Add build Intel "anv" vulkan driver")
Reviewed-and-Tested-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 4eab98b66e)
2018-11-14 18:53:02 +00:00
Marek Olšák
7ea4e43c55 st/mesa: disable L3 thread pinning
This implementation can have massive drawbacks.

Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
(cherry picked from commit e0c7114eb3)
2018-11-14 18:53:02 +00:00
Dylan Baker
6a706763d0 meson: Don't set -Wall
meson does this for you with its warn levels, so we don't need to set
it ourselves.

Fixes: d1992255bb
       ("meson: Add build Intel "anv" vulkan driver")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 9c2a95b298)
2018-11-14 18:53:02 +00:00
Timothy Arceri
9b8380a4f9 nir: don't pack varyings ints with floats unless flat
Fixes: 1c9c42d16b ("nir: add varying component packing helpers")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit a068958692)
2018-11-14 18:53:02 +00:00
Timothy Arceri
fff64af317 nir: add glsl_type_is_integer() helper
Fixes: 1c9c42d16b ("nir: add varying component packing helpers")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 9dd737bb02)
2018-11-14 18:53:02 +00:00
Andre Heider
5f137e94b9 st/nine: fix stack corruption due to ABI mismatch
This fixes various crashes and hangs when using nine's 'thread_submit'
feature.

On 64bit, the thread function's data argument would just be NULL.
On 32bit, the data argument would be garbage depending on the compiler
flags (in my case -march>=core2).

Fixes: f3fa7e3068 ("st/nine: Use WINE thread for threadpool")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
(cherry picked from commit 10598c9667)
2018-11-14 18:53:02 +00:00
Samuel Pitoiset
c64a78ec0a radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+
Inclusive and exclusives scan are missing because older chips
don't have llvm.amdgcn.update.dpp.

This fixes crashes with dEQP-VK.subgroups.arithmetic.*.

CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 0dcd99c687)
2018-11-14 18:53:02 +00:00
Mark Janes
73f457f486 Revert "i965/batch: avoid reverting batch buffer if saved state is an empty"
This reverts commit a9031bf9b5.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630
(cherry picked from commit 5f312e95f8)
2018-11-14 18:53:02 +00:00
Emil Velikov
f55265776f Update version to 18.3.0-rc2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-09 11:00:00 +00:00
Gert Wollny
4c995fcae7 virgl/vtest-winsys: Use virgl version of bind flags
The bind flags defined by mesa/gallium might not always be in sync
with the ones copied to virglrenderer/gallium. Therefore, use the
flags defined in virgl like it is done for all the other calls to
create resources.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b710680093)
2018-11-08 16:14:24 +00:00
Erik Faye-Lund
09c5e548c4 glsl: do not allow implicit casts of unsized array initializers
The GLSL 4.6 specification (section 4.1.14. "Implicit Conversions")
says:

  "There are no implicit array or structure conversions. For
   example, an array of int cannot be implicitly converted to an
   array of float."

So let's add a check in place when assigning array initializers to
implicitly sized arrays, to avoid incorrectly allowing code on the
form:

int[] foo = float[](1.0, 2.0, 3.0)

This fixes the following dEQP test-cases:
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_float_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_float_fragment
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_uint_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.int_to_uint_fragment
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.uint_to_float_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es31.invalid.arrays.uint_to_float_fragment
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_float_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_float_fragment
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_uint_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.int_to_uint_fragment
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.uint_to_float_vertex
- dEQP-GLES31.functional.shaders.implicit_conversions.es32.invalid.arrays.uint_to_float_fragment

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 742dace825)
2018-11-08 16:05:38 +00:00
Sergii Romantsov
15442cac5c autotools: library-dependency when no sse and 32-bit
Building of 32bit Mesa may fail if __SSE__ is not specified.
Added missed dependency from libm.

v2: avoided dependecy on any flag, just link

v3: meson doesn't fail, but have added dependency on libm

CC: Dylan Baker <dylan@pnwbakers.com>
CC: Lionel G Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108560
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit ce837a5372)
2018-11-08 16:05:38 +00:00
Samuel Pitoiset
61c64f64d7 radv: disable conditional rendering for vkCmdCopyQueryPoolResults()
VK_EXT_conditional_rendering says that copy commands should not be
affected by conditional rendering.

Cc: 18.2 18.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 0a0aa2ba6c)

Conflicts:
	src/amd/vulkan/radv_query.c
2018-11-08 16:05:38 +00:00
Timothy Arceri
5b35600422 ac/nir_to_llvm: fix b2f for f64
Fixes: d7e0d47b9d ("nir: Add a bunch of b2[if] optimizations")

Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 9aa3c1915e)
2018-11-08 16:05:38 +00:00
Emil Velikov
ede46c67ea docs: document the staging branch and add reference to it
A while back we agreed that having a live/staging branch is beneficial.
Sadly we forgot to document that, so here is my first attempt.

Document the caveat that the branch history is not stable.

CC: Andres Gomez <agomez@igalia.com>
CC: Dylan Baker <dylan@pnwbakers.com>
CC: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 0a60708870e256432bdef1a22c98b09f83d8a440)
2018-11-08 16:05:06 +00:00
Lionel Landwerlin
ecb1bef871 anv/android: mark gralloc allocated BOs as external
Allocating through Gralloc implies buffers are going to be used
outside the driver. We have special MOCS settings for external BOs and
we probably want to use them here too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a1220e7311 ("anv/android: Set the BO flags in bo_cache_import (v2)")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 421fa01d64)
2018-11-08 16:05:06 +00:00
Olivier Fourdan
a93d19f542 wayland/egl: Resize EGL surface on update buffer for swrast
After commit a9fb331ea ("wayland/egl: update surface size on window
resize"), the surface size is updated as soon as the resize is done, and
`update_buffers()` would resize only if the surface size differs from
the attached size.

However, in the case of swrast, there is no resize callback and the
attached size is updated in `dri2_wl_swrast_commit_backbuffer()` prior
to the `swrast_update_buffers()` so the attached size is always up to
date when it reaches `swrast_update_buffers()` and the surface is never
resized.

This can be observed with "totem" using the GDK backend on Wayland (the
default) when running on software rendering:

  $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem

Resizing the window would leave the EGL surface size unchanged.

To avoid the issue, partially revert the part of commit a9fb331ea for
`swrast_update_buffers()` and resize on the win size and not the
attached size.

Fixes: a9fb331ea - wayland/egl: update surface size on window resize
Signed-off-by: Olivier Fourdan <ofourdan@redhat.com>
CC: Daniel Stone <daniel@fooishbar.org>
CC: Juan A. Suarez Romero <jasuarez@igalia.com>
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
(cherry picked from commit 55af17ffed)
2018-11-08 16:05:06 +00:00
Lionel Landwerlin
7053fe50c3 intel/decoders: fix instruction base address parsing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 00103db04a ("intel: Fix decoding for partial STATE_BASE_ADDRESS updates.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b47a69ed4c)
2018-11-08 16:05:06 +00:00
Marek Olšák
327330e77c st/va: fix incorrect use of resource_destroy
Fixes: 4373dd3215 ("st/va: Support YUV formats in vaCreateSurfaces")
Cc: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 04298a2f24)
2018-11-08 16:05:06 +00:00
Eric Engestrom
422c905f4b wsi/wayland: only finish() a successfully init()ed display
Fixes: 4369102498 "vulkan/wsi/wayland: Stop caching Wayland displays"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
(cherry picked from commit d515ded4d9)
2018-11-08 16:05:06 +00:00
Eric Engestrom
1348e6e255 wsi/wayland: use proper VkResult type
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit dcee22afed)
2018-11-08 16:05:06 +00:00
Samuel Pitoiset
97a3ef3d1c radv: add missing TFB queries support to CmdCopyQueryPoolsResults()
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Fixes: b4eb029062 ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b1b2dd06a7)
2018-11-08 16:05:06 +00:00
Vinson Lee
6463af186c r600/sb: Fix constant logical operand in assert.
Fixes: da977ad907 ("r600/sb: start adding GDS support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 64a9ed8848)
2018-11-08 16:05:06 +00:00
Mauro Rossi
45fe51a0ee android: radv: add libmesa_git_sha1 static dependency
libmesa_git_sha1 whole static dependency is added to get git_sha1.h header
and avoid following building error:

external/mesa/src/amd/vulkan/radv_device.c:46:10:
fatal error: 'git_sha1.h' file not found
         ^
1 error generated.

Fixes: 9d40ec2cf6 ("radv: Add support for VK_KHR_driver_properties.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit 5c0cff868a)
2018-11-08 16:05:05 +00:00
Dylan Baker
5adc1920ee meson: link gallium nine with pthreads
In some cases (not building with llvm, which automatically pulls in
pthreads) nine needs to be directly linked with pthreads. Fixes building
on x86 (32 bit) without llvm.

Distro bug: https://bugs.gentoo.org/670094
Fixes: 6b4c7047d5
       ("meson: build gallium nine state_tracker")
Tested-by: Rafal Lalik <rafallalik@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

(cherry picked from commit 7652931d33)
2018-11-08 16:05:05 +00:00
Timothy Arceri
6adbf17ce9 nir: fix condition propagation when src has a swizzle
We cannot use nir_build_alu() to create the new alu as it has no
way to know how many components of the src we will use. This
results in it guessing the max number of components from one of
its inputs.

Fixes the following CTS tests:

dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_frag
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_geom
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_tessc
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_vert

Fixes: 2975422ceb ("nir: propagates if condition evaluation down some alu chains")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 769ae9fb7f)
2018-11-08 16:04:53 +00:00
Timothy Arceri
d5e33d2aa6 nir: allow propagation of if evaluation for bcsel
Shader-db results Skylake:

total instructions in shared programs: 13109035 -> 13109024 (<.01%)
instructions in affected programs: 4777 -> 4766 (-0.23%)
helped: 11
HURT: 0

total cycles in shared programs: 332090418 -> 332090443 (<.01%)
cycles in affected programs: 19474 -> 19499 (0.13%)
helped: 6
HURT: 4

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit c7bdda8aa5)
2018-11-08 16:04:33 +00:00
Mauro Rossi
959a9d42d7 android: gallium/auxiliary: add include to get u_debug.h header
To avoid build error in u_debug_stack_android.cpp
due to now missing u_debug.h header:

external/mesa/src/gallium/auxiliary/util/u_debug_stack_android.cpp:26:10:
fatal error: 'u_debug.h' file not found
#include "u_debug.h"
         ^
1 error generated.

Fixes: 37db383abb ("util: Move u_debug to utils")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit b9dec214f5)
2018-11-07 17:20:51 +00:00
Dave Airlie
52e01585c4 radv: fix begin/end transform feedback with 0 counter buffers.
If the user gives 0 counterBuffers then the driver should still
enable transform feedback on all targets. This changes the
driver to always enable xfb, and use counter buffers where
one is defined for the target in question.

Fixes: b4eb029062 (radv: implement VK_EXT_transform_feedback)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 677b496b6b)
2018-11-07 17:20:50 +00:00
Dave Airlie
12c5eb2fd3 radv: apply xfb buffer offset at buffer binding time not later. (v2)
In order to handle pause/resume properly, the offset should
be added to the buffer binding not to the begin/end paths.

v2: don't add offset to size
Fixes ext_transform_feedback-alignment* under zink

Fixes: b4eb029062 (radv: implement VK_EXT_transform_feedback)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 7f37a52a21)
2018-11-07 17:20:50 +00:00
Emil Velikov
949b1048f7 Update version to 18.3.0-rc1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-06 15:31:07 +00:00
Emil Velikov
22201d2048 egl/glvnd: correctly report errors when vendor cannot be found
If the user provides an invalid display or device the ToVendor lookup
will fail.

In this case, the local [Mesa vendor] error code will be set. Thus on
sequential eglGetError(), the error will be EGL_SUCCESS.

To be more specific, GLVND remembers the last vendor and calls back
into it's eglGetError, although there's no guarantee to ever have had
one.

v2:
 - Add _eglError call, so the debug callback is executed (Kyle)
 - Drop XXX comment.

Piglit: tests/egl/spec/egl_ext_device_query
Fixes: ce562f9e3f ("EGL: Implement the libglvnd interface for EGL (v3)")
Cc: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kyle Brenneman <kbrenneman@nvidia.com>
(cherry picked from commit b3ade65387)
2018-11-05 22:16:10 +00:00
Emil Velikov
60fe2f6ecc egl: add EGL_EXT_device_base entrypoints
eglQueryDevicesEXT (unlike the other three functions) does not depend
on the display. It is implemented in GLVND, which calls into each
driver collecting the list of devices and presenting it to the user.

For the other entrypoints, GLVND acts as pass through stub calling into
the vendor library. The vendor implementation calls back into GLVND to
get the vendor dispatch. Then the driver proceeds to call itself via
the said dispatch.

This design makes is possible to keep using "old" GLVND with newer
vendor drivers. Since effectively all the extension code is within the
latter itself.

Without said entrypoints, any user will outright crash - as reported in
the bug report.

Note: there's a follow-up fix needed to our GLVND code, to make piglit
happy.

v2: add some beefy documentation in the commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108635
Fixes: 7552fcb7b9 ("egl: add base EGL_EXT_device_base implementation")
Reported-by: kyle.devir@mykolab.com
Cc: kyle.devir@mykolab.com
Acked-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 2a8fefdeb0)
2018-11-05 22:16:08 +00:00
1189 changed files with 37769 additions and 60654 deletions

View File

@@ -11,7 +11,6 @@ tab_width = 8
[*.{c,h,cpp,hpp,cc,hh}]
indent_style = space
indent_size = 3
max_line_length = 78
[{Makefile*,*.mk}]
indent_style = tab

View File

@@ -1,6 +1,7 @@
language: c
dist: xenial
sudo: false
dist: trusty
cache:
apt: true
@@ -15,7 +16,7 @@ env:
- GLPROTO_VERSION=glproto-1.4.17
- DRI2PROTO_VERSION=dri2proto-2.8
- LIBPCIACCESS_VERSION=libpciaccess-0.13.4
- LIBDRM_VERSION=libdrm-2.4.97
- LIBDRM_VERSION=libdrm-2.4.74
- XCBPROTO_VERSION=xcb-proto-1.13
- RANDRPROTO_VERSION=randrproto-1.3.0
- LIBXRANDR_VERSION=libXrandr-1.3.0
@@ -34,19 +35,20 @@ matrix:
- env:
- LABEL="meson Vulkan"
- BUILD=meson
- UNWIND="false"
- DRI_LOADERS="-Dglx=disabled -Dgbm=false -Degl=false -Dplatforms=x11,wayland,drm -Dosmesa=none"
- GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
- DRI_DRIVERS=""
- GALLIUM_DRIVERS=""
- VULKAN_DRIVERS="intel,amd"
- LLVM_VERSION=7
- LLVM_VERSION=6.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
- llvm-7-dev
# From sources above
- llvm-6.0-dev
# Common
- xz-utils
- libexpat1-dev
@@ -54,27 +56,23 @@ matrix:
- libelf-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson loaders/classic DRI"
- BUILD=meson
- UNWIND="false"
- DRI_LOADERS="-Dglx=dri -Dgbm=true -Degl=true -Dplatforms=x11,wayland,drm,surfaceless -Dosmesa=classic"
- DRI_DRIVERS="i915,i965,r100,r200,swrast,nouveau"
- GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
- GALLIUM_DRIVERS=""
- VULKAN_DRIVERS=""
addons:
apt:
packages:
- xz-utils
- x11proto-xf86vidmode-dev
- libxxf86vm-dev
- libexpat1-dev
- libx11-xcb-dev
- libxdamage-dev
- libxfixes-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="make loaders/classic DRI"
- BUILD=make
@@ -91,200 +89,11 @@ matrix:
packages:
- xz-utils
- x11proto-xf86vidmode-dev
- libxxf86vm-dev
- libexpat1-dev
- libx11-xcb-dev
- libxdamage-dev
- libxfixes-dev
- python3-pip
- python3-setuptools
- env:
# NOTE: Building SWR is 2x (yes two) times slower than all the other
# gallium drivers combined.
# Start this early so that it doesn't hunder the run time.
- LABEL="meson Gallium Drivers SWR"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
- GALLIUM_DRIVERS="swr"
- LLVM_VERSION=6.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
- llvm-6.0-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium Drivers RadeonSI"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
- GALLIUM_DRIVERS="radeonsi"
- LLVM_VERSION=7
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
packages:
# From sources above
- llvm-7-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium Drivers Other"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
- GALLIUM_DRIVERS="i915,nouveau,kmsro,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv"
- LLVM_VERSION=5.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- llvm-5.0-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium ST Clover LLVM-5.0"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
- GALLIUM_DRIVERS="r600"
- LLVM_VERSION=5.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- llvm-5.0-dev
- clang-5.0
- libclang-5.0-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium ST Clover LLVM-6.0"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
- GALLIUM_DRIVERS="r600"
- LLVM_VERSION=6.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
- libclc-dev
- llvm-6.0-dev
- clang-6.0
- libclang-6.0-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium ST Clover LLVM-7"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=false -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=icd"
- GALLIUM_DRIVERS="r600,radeonsi"
- LLVM_VERSION=7
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
packages:
- libclc-dev
# From sources above
- llvm-7-dev
- clang-7
- libclang-7-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
- LABEL="meson Gallium ST Other"
- BUILD=meson
- UNWIND="true"
- DRI_LOADERS="-Dglx=disabled -Degl=false -Dgbm=false"
- GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=true -Dgallium-xvmc=true -Dgallium-omx=bellagio -Dgallium-va=true -Dgallium-xa=true -Dgallium-nine=true -Dgallium-opencl=disabled -Dosmesa=gallium"
# We need swrast for osmesa and nine.
# Nouveau supports, or builds at least against all ST.
- GALLIUM_DRIVERS="nouveau,swrast"
- LLVM_VERSION=5.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
- llvm-5.0-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# Nine requires gcc 4.6... which is the one we have right ?
- libxvmc-dev
# Build locally, for now.
#- libvdpau-dev
#- libva-dev
- libomxil-bellagio-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- libunwind8-dev
- python3.5
- python3-pip
- python3-setuptools
- env:
# NOTE: Building SWR is 2x (yes two) times slower than all the other
# gallium drivers combined.
@@ -303,7 +112,12 @@ matrix:
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
# From sources above
- llvm-6.0-dev
# Common
- xz-utils
@@ -312,13 +126,12 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium Drivers RadeonSI"
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=7
- LLVM_VERSION=6.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
@@ -329,11 +142,12 @@ matrix:
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
# From sources above
- llvm-7-dev
- llvm-6.0-dev
# Common
- xz-utils
- libexpat1-dev
@@ -341,7 +155,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium Drivers Other"
- BUILD=make
@@ -349,17 +162,23 @@ matrix:
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=3.9
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_DRIVERS="i915,nouveau,kmsro,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv"
- GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv,imx"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-3.9
packages:
- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
- llvm-3.9-dev
# Common
- xz-utils
@@ -368,7 +187,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium ST Clover LLVM-3.9"
- BUILD=make
@@ -376,6 +194,10 @@ matrix:
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=3.9
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.7
- OVERRIDE_CXX=g++-4.7
# New binutils linker is required for llvm-3.9
- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -384,10 +206,15 @@ matrix:
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-3.9
packages:
- binutils-2.26
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.7
# From sources above
- llvm-3.9-dev
- clang-3.9
- libclang-3.9-dev
@@ -398,7 +225,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium ST Clover LLVM-4.0"
- BUILD=make
@@ -406,6 +232,8 @@ matrix:
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.8
- OVERRIDE_CXX=g++-4.8
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -414,10 +242,14 @@ matrix:
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-4.0
packages:
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.8
# From sources above
- llvm-4.0-dev
- clang-4.0
- libclang-4.0-dev
@@ -428,7 +260,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium ST Clover LLVM-5.0"
- BUILD=make
@@ -436,6 +267,8 @@ matrix:
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=5.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC=gcc-4.8
- OVERRIDE_CXX=g++-4.8
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
@@ -444,10 +277,14 @@ matrix:
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-5.0
packages:
- libclc-dev
# LLVM packaging is broken and misses these dependencies
- libedit-dev
- g++-4.8
# From sources above
- llvm-5.0-dev
- clang-5.0
- libclang-5.0-dev
@@ -458,7 +295,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium ST Clover LLVM-6.0"
- BUILD=make
@@ -469,13 +305,18 @@ matrix:
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
- GALLIUM_DRIVERS="r600"
- GALLIUM_DRIVERS="r600,radeonsi"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
apt:
sources:
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
- libclc-dev
# From sources above
- llvm-6.0-dev
- clang-6.0
- libclang-6.0-dev
@@ -486,7 +327,6 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Gallium ST Clover LLVM-7"
- BUILD=make
@@ -503,8 +343,10 @@ matrix:
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
- sourceline: 'deb http://apt.llvm.org/trusty/ llvm-toolchain-trusty-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
# llvm-7 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
- libclc-dev
# From sources above
@@ -522,7 +364,7 @@ matrix:
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
- LLVM_VERSION=3.5
- LLVM_VERSION=3.3
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
@@ -536,8 +378,8 @@ matrix:
addons:
apt:
packages:
# We actually want to test against llvm-3.3, yet 3.5 is available
- llvm-3.5-dev
# We actually want to test against llvm-3.3
- llvm-3.3-dev
# Nine requires gcc 4.6... which is the one we have right ?
- libxvmc-dev
# Build locally, for now.
@@ -553,13 +395,12 @@ matrix:
- libelf-dev
- libunwind8-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="make Vulkan"
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel check"
- LLVM_VERSION=7
- LLVM_VERSION=6.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl --with-platforms=x11,wayland"
- DRI_DRIVERS=""
@@ -570,18 +411,18 @@ matrix:
addons:
apt:
sources:
- sourceline: 'deb http://apt.llvm.org/xenial/ llvm-toolchain-xenial-7 main'
key_url: https://apt.llvm.org/llvm-snapshot.gpg.key
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
# From sources above
- llvm-7-dev
- llvm-6.0-dev
# Common
- xz-utils
- libexpat1-dev
- libx11-xcb-dev
- libelf-dev
- python3-pip
- python3-setuptools
- env:
- LABEL="scons"
- BUILD=scons
@@ -606,15 +447,14 @@ matrix:
- SCONS_TARGET="llvm=1"
# Keep it symmetrical to the make build.
- SCONS_CHECK_COMMAND="scons llvm=1 check"
- LLVM_VERSION=3.5
- LLVM_VERSION=3.3
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
packages:
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# We actually want to test against llvm-3.3, yet 3.5 is available
- llvm-3.5-dev
- llvm-3.3-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
@@ -632,7 +472,12 @@ matrix:
- SCONS_CHECK_COMMAND="true"
addons:
apt:
sources:
- llvm-toolchain-trusty-6.0
# llvm-6 requires libstdc++4.9 which is not in main repo
- ubuntu-toolchain-r-test
packages:
# From sources above
- llvm-6.0-dev
# Common
- xz-utils
@@ -650,9 +495,6 @@ matrix:
- env:
- LABEL="macOS meson"
- BUILD=meson
- UNWIND="false"
- DRI_LOADERS="-Dglx=dri -Dgbm=false -Degl=false -Dplatforms=x11 -Dosmesa=none"
- GALLIUM_ST="-Ddri3=true -Dgallium-vdpau=false -Dgallium-xvmc=false -Dgallium-omx=disabled -Dgallium-va=false -Dgallium-xa=false -Dgallium-nine=false -Dgallium-opencl=disabled"
os: osx
before_install:
@@ -680,8 +522,10 @@ before_install:
install:
# Install a more modern meson from pip, since the version in the
# ubuntu repos is often quite old.
# ubuntu repos is often quite old. This requires python>=3.5, so
# let's make it default
- if test "x$BUILD" = xmeson; then
sudo update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.5 10;
pip3 install --user meson;
pip3 install --user mako;
fi
@@ -697,6 +541,16 @@ install:
pip2 install --user mako;
fi
# Since libdrm gets updated in configure.ac regularly, try to pick up the
# latest version from there.
- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
old_ver=`echo $LIBDRM_VERSION | sed 's/libdrm-//'`;
new_ver=`echo $line | sed 's/.*REQUIRED=//'`;
if `echo "$old_ver,$new_ver" | tr ',' '\n' | sort -Vc 2> /dev/null`; then
export LIBDRM_VERSION="libdrm-$new_ver";
fi;
done
# Install dependencies where we require specific versions (or where
# disallowed by Travis CI's package whitelisting).
@@ -758,7 +612,7 @@ install:
tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
(cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && make install)
# Meson requires ninja >= 1.6, but xenial has 1.3.x
# Meson requires ninja >= 1.6, but trusty has 1.3.x
wget https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip
unzip ninja-linux.zip
mv ninja $HOME/prefix/bin/
@@ -801,13 +655,15 @@ install:
script:
- if test "x$BUILD" = xmake; then
test -n "$OVERRIDE_CC" && export CC="$OVERRIDE_CC";
test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
test -n "$OVERRIDE_PATH" && export PATH="$OVERRIDE_PATH:$PATH";
export CFLAGS="$CFLAGS -isystem`pwd`";
mkdir build &&
cd build &&
../autogen.sh
--enable-autotools
--enable-debug
../autogen.sh --enable-debug
$LIBUNWIND_FLAGS
$DRI_LOADERS
--with-dri-drivers=$DRI_DRIVERS
@@ -820,33 +676,41 @@ script:
fi
- if test "x$BUILD" = xscons; then
test -n "$OVERRIDE_CC" && export CC="$OVERRIDE_CC";
test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
fi
- |
if test "x$BUILD" = xmeson; then
if test -n "$LLVM_CONFIG"; then
# We need to control the version of llvm-config we're using, so we'll
# generate a native file to do so. This requires meson >=0.49
#
echo -e "[binaries]\nllvm-config = '`which $LLVM_CONFIG`'" > native.file
$LLVM_CONFIG --version
else
: > native.file
if test "x$TRAVIS_OS_NAME" == xosx; then
MESON_OPTIONS="-Degl=false"
fi
if test "x$TRAVIS_OS_NAME" == xlinux; then
MESON_OPTIONS="-Ddri-drivers=${DRI_DRIVERS:-[]} -Dgallium-drivers=${GALLIUM_DRIVERS:-[]} -Dvulkan-drivers=${VULKAN_DRIVERS:-[]}"
fi
# Travis CI has moved to LLVM 5.0, and meson is detecting
# automatically the available version in /usr/local/bin based on
# the PATH env variable order preference.
#
# As for 0.44.x, Meson cannot receive the path to the
# llvm-config binary as a configuration parameter. See
# https://github.com/mesonbuild/meson/issues/2887 and
# https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef
#
# We want to use the custom (APT) installed version. Therefore,
# let's make Meson find our wanted version sooner than the one
# at /usr/local/bin
#
# Once this is corrected, we would still need a patch similar
# to:
# https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html
test -f /usr/bin/$LLVM_CONFIG && ln -s /usr/bin/$LLVM_CONFIG $HOME/prefix/bin/llvm-config
export CFLAGS="$CFLAGS -isystem`pwd`"
meson _build \
--native-file=native.file \
-Dbuild-tests=true \
-Dlibunwind=${UNWIND} \
${DRI_LOADERS} \
-Ddri-drivers=${DRI_DRIVERS:-[]} \
${GALLIUM_ST} \
-Dgallium-drivers=${GALLIUM_DRIVERS:-[]} \
-Dvulkan-drivers=${VULKAN_DRIVERS:-[]}
meson configure _build
meson _build $MESON_OPTIONS
ninja -C _build
ninja -C _build test
fi

View File

@@ -37,6 +37,7 @@ LOCAL_CFLAGS += \
-Wno-missing-field-initializers \
-Wno-initializer-overrides \
-Wno-mismatched-tags \
-DVERSION=\"$(MESA_VERSION)\" \
-DPACKAGE_VERSION=\"$(MESA_VERSION)\" \
-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"

View File

@@ -24,7 +24,7 @@
# BOARD_GPU_DRIVERS should be defined. The valid values are
#
# classic drivers: i915 i965
# gallium drivers: swrast freedreno i915g nouveau kmsro r300g r600g radeonsi vc4 virgl vmwgfx etnaviv
# gallium drivers: swrast freedreno i915g nouveau pl111 r300g r600g radeonsi vc4 virgl vmwgfx etnaviv imx
#
# The main target is libGLES_mesa. For each classic driver enabled, a DRI
# module will also be built. DRI modules will be loaded by libGLES_mesa.
@@ -52,14 +52,15 @@ gallium_drivers := \
freedreno.HAVE_GALLIUM_FREEDRENO \
i915g.HAVE_GALLIUM_I915 \
nouveau.HAVE_GALLIUM_NOUVEAU \
kmsro.HAVE_GALLIUM_KMSRO \
pl111.HAVE_GALLIUM_PL111 \
r300g.HAVE_GALLIUM_R300 \
r600g.HAVE_GALLIUM_R600 \
radeonsi.HAVE_GALLIUM_RADEONSI \
vmwgfx.HAVE_GALLIUM_VMWGFX \
vc4.HAVE_GALLIUM_VC4 \
virgl.HAVE_GALLIUM_VIRGL \
etnaviv.HAVE_GALLIUM_ETNAVIV
etnaviv.HAVE_GALLIUM_ETNAVIV \
imx.HAVE_GALLIUM_IMX
ifeq ($(BOARD_GPU_DRIVERS),all)
MESA_BUILD_CLASSIC := $(filter HAVE_%, $(subst ., , $(classic_drivers)))

View File

@@ -22,7 +22,6 @@
SUBDIRS = src
AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-autotools \
--enable-dri \
--enable-dri3 \
--enable-egl \
@@ -46,7 +45,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-libunwind \
--with-platforms=x11,wayland,drm,surfaceless \
--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
--with-gallium-drivers=i915,nouveau,r300,kmsro,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv \
--with-gallium-drivers=i915,nouveau,r300,pl111,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv,imx \
--with-vulkan-drivers=intel,radeon
ACLOCAL_AMFLAGS = -I m4

View File

@@ -72,9 +72,7 @@ F: src/loader/
EGL
R: Eric Engestrom <eric@engestrom.ch>
R: Emil Velikov <emil.l.velikov@gmail.com>
F: src/egl/
F: include/EGL/
HAIKU
R: Alexander von Gluck IV <kallisti5@unixzen.com>
@@ -138,8 +136,3 @@ F: src/gallium/drivers/freedreno/
GLX
R: Adam Jackson <ajax@redhat.com>
F: src/glx/
VULKAN
R: Eric Engestrom <eric@engestrom.ch>
F: src/vulkan/
F: include/vulkan/

View File

@@ -1 +1 @@
19.0.2
18.3.6

View File

@@ -1,17 +1,54 @@
# Both of these were already merged with different shas
da48cba61ef6fefb799bf96e6364b70dbf4ec712
c812c740e60c14060eb89db66039111881a0f42f
# fixes: Commit was squashed into the respective offenders
c02390f8fcd367c7350db568feabb2f062efca14 egl/wayland: rather obvious build fix
# fixes: The commit addresses b4476138d5ad3f8d30c14ee61f2f375edfdbab2a
ff6f1dd0d3c6b4c15ca51b478b2884d14f6a1e06 meson: libfreedreno depends upon libdrm (for fence support)
# The commit these fix was reverted from 19.0, but fixed for 19.1 due
# to the number of fixes required to make that commit work
8d8f80af3a17354508f2ec9d6559c915d5be351d
0c0c69729b6d72a5297122856c8fe48510e90764
0881e90c09965818b02e359474a6f7446b41d647
b031c643491a92a5574c7a4bd659df33f2d89bb6
# fixes: This commit requires commits aeaf8dbd097 and 7484bc894b9 which did not
# land in branch.
f67dea5e19ef14187be0e8d0f61b1f764c7ccb4f radv: Fix multiview depth clears
# These were manually rebased by Jason, thanks!
8ab95b849e66f3221d80a67eef2ec6e3730901a8
5c30fffeec1732c21d600c036f95f8cdb1bb5487
# stable The commits aren't suitable in their present form.
bfe31c5e461a1330d6f606bf5310685eff1198dd nir/builder: Add nir_i2i and nir_u2u helpers which take a bit size
abfe674c54bee6f8fdcae411b07db89c10b9d530 spirv: Handle arbitrary bit sizes for deref array indices
# This doesn't actually appliy to 19.0
29179f58c6ba8099859ea25900214dbbd3814a92
# warn The commits refer stale sha, yet don't fix anything in particular.
98984b7cdd79c15cc7331c791f8be61e873b8bbd Revert "mapi/new: sort by slot number"
9f86f1da7c68b5b900cd6f60925610ff1225a72d egl: add glvnd entrypoints for EGL_MESA_query_driver
# stable Explicit 19.0 only nomination.
38f542783faa360020b77fdd76b97f207a9e0068 v50,nvc0: add explicit settings for recent caps
# stable Explicit 19.0 only nominations.
399215eb7a0517463e5757c598d6cff6ae2301d0 nvc0: add support for handling indirect draws with attrib conversion
4443b6ddf2e08d06f3d0457cf20a2e04244cde37 nvc0/ir: always use CG mode for loads from atomic-only buffers
5de5beedf21306b01730085f8e03d8f424729016 nvc0/ir: fix second tex argument after levelZero optimization
162352e6711b3ceab114686f7a3248074339e7f7 nvc0: fix 3d images on kepler
e00799d3dc0595dc3998dbf199ceec8b1eece966 nv50,nvc0: use condition for occlusion queries when already complete
6adb9b38bfb1f6ee4c94596bf0744225aa8e967a nvc0: stick zero values for the compute invocation counts
04593d9a73ea257a36cc3b9fb5cd41427beaaea5 gk110/ir: Add rcp f64 implementation
7937408052a1896f0b08b0110bb8a1790eeee351 gk110/ir: Add rsq f64 implementation
656ad060518d067a3b311db8c2de2a396fb41898 gk110/ir: Use the new rcp/rsq in library
12669d29705a26478aa691cb454149628be65f17 gk104/ir: Use the new rcp/rsq in library
815a8e59c6d462a7008653ea9e3010d40b6ba589 gm107/ir: add fp64 rcp
cce495572136a606dd2a35e79f45080c3796e2cc gm107/ir: add fp64 rsq
6010d7b8e8bee1bcea2b329cf6d3b44c5fc3ca66 gallium: add PIPE_CAP_MAX_VARYINGS
cbd1ad6165f0aea7fb7c6fd1b36ad5317dd65cb7 st/mesa: require RGBA2, RGB4, and RGBA4 to be renderable
# stable The commit addresses functionality not present in branch
1b8983c25be19073c02fe9630e949be55f8280fa radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
# stable Explicit 19.0 only nominations, require work which did not land in branch
8ab95b849e66f3221d80a67eef2ec6e3730901a8 anv: Refactor descriptor pushing a bit
5c30fffeec1732c21d600c036f95f8cdb1bb5487 anv: Take references to push descriptor set layouts
# sha Commit references invalid sha - a offender did not land in branch.
85ee157283c667372baf7c03259cba08853f0067 gitlab-ci: autotools needs to be told which llvm version to use
# revert The commit was reverted shortly after it was applied on master
47fc359822494935852de1e70e4d840b2fe6a25c anv: release memory allocated by glsl types during spirv_to_nir
# stable Explicitly 19.0 nomination, seemingly a performance patch
5ef2b8f1f2ebcdb4ffe5c98b3f4f48e584cb4b22 nir: Add a pass for lowering IO back to vector when possible
# fixes Temporary block perf. fix depending on previous opt. pass
6d5d89d25a0a4299dbfcbfeca71b6c7e65ef3d45 intel/nir: Vectorize all IO

View File

@@ -1,88 +0,0 @@
#!/usr/bin/env python3
# Copyright © 2019 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
"""This script reads a meson build directory and gives back the command line it
was configured with.
This only works for meson 0.49.0 and newer.
"""
import argparse
import ast
import configparser
import pathlib
import sys
def parse_args() -> argparse.Namespace:
"""Parse arguments."""
parser = argparse.ArgumentParser()
parser.add_argument(
'build_dir',
help='Path the meson build directory')
args = parser.parse_args()
return args
def load_config(path: pathlib.Path) -> configparser.ConfigParser:
"""Load config file."""
conf = configparser.ConfigParser()
with path.open() as f:
conf.read_file(f)
return conf
def build_cmd(conf: configparser.ConfigParser) -> str:
"""Rebuild the command line."""
args = []
for k, v in conf['options'].items():
if ' ' in v:
args.append(f'-D{k}="{v}"')
else:
args.append(f'-D{k}={v}')
cf = conf['properties'].get('cross_file')
if cf:
args.append('--cross-file={}'.format(cf))
nf = conf['properties'].get('native_file')
if nf:
# this will be in the form "['str', 'str']", so use ast.literal_eval to
# convert it to a list of strings.
nf = ast.literal_eval(nf)
args.extend(['--native-file={}'.format(f) for f in nf])
return ' '.join(args)
def main():
args = parse_args()
path = pathlib.Path(args.build_dir, 'meson-private', 'cmd_line.txt')
if not path.exists():
print('Cannot find the necessary file to rebuild command line. '
'Is your meson version >= 0.49.0?', file=sys.stderr)
sys.exit(1)
conf = load_config(path)
cmd = build_cmd(conf)
print(cmd)
if __name__ == '__main__':
main()

View File

@@ -52,19 +52,6 @@ mingw*)
;;
esac
AC_ARG_ENABLE(autotools,
[AS_HELP_STRING([--enable-autotools],
[Enable the use of this autotools based build configuration])],
[enable_autotools=$enableval], [enable_autotools=no])
if test "x$enable_autotools" != "xyes" ; then
AC_MSG_ERROR([the autotools build system has been deprecated in favour of
meson and will be removed eventually. For instructions on how to use meson
see https://www.mesa3d.org/meson.html.
If you still want to use the autotools build, then add --enable-autotools
to the configure command line.])
fi
# Support silent build rules, requires at least automake-1.11. Disable
# by either passing --disable-silent-rules to configure or passing V=1
# to make
@@ -87,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
# in the first entry.
LIBDRM_REQUIRED=2.4.75
LIBDRM_RADEON_REQUIRED=2.4.71
LIBDRM_AMDGPU_REQUIRED=2.4.97
LIBDRM_AMDGPU_REQUIRED=2.4.95
LIBDRM_INTEL_REQUIRED=2.4.75
LIBDRM_NVVIEUX_REQUIRED=2.4.66
LIBDRM_NOUVEAU_REQUIRED=2.4.66
@@ -120,9 +107,9 @@ dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=7.0.0
LLVM_REQUIRED_RADV=7.0.0
LLVM_REQUIRED_SWR=7.0.0
LLVM_REQUIRED_RADEONSI=6.0.0
LLVM_REQUIRED_RADV=6.0.0
LLVM_REQUIRED_SWR=6.0.0
dnl Check for progs
AC_PROG_CPP
@@ -1408,7 +1395,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast"
AC_ARG_WITH([gallium-drivers],
[AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@],
[comma delimited Gallium drivers list, e.g.
"i915,nouveau,r300,r600,radeonsi,freedreno,kmsro,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv"
"i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv,imx"
@<:@default=r300,r600,svga,swrast@:>@])],
[with_gallium_drivers="$withval"],
[with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"])
@@ -1922,7 +1909,7 @@ if test x"$enable_dri3" = xyes; then
dri3_modifier_modules="xcb-dri3 >= $XCBDRI3_MODIFIERS_REQUIRED xcb-present >= $XCBPRESENT_MODIFIERS_REQUIRED"
PKG_CHECK_MODULES([XCB_DRI3_MODIFIERS], [$dri3_modifier_modules], [have_dri3_modifiers=yes], [have_dri3_modifiers=no])
if test "x$have_dri3_modifiers" = xyes; then
if test "x$have_dri3_modifiers" == xyes; then
DEFINES="$DEFINES -DHAVE_DRI3_MODIFIERS"
fi
fi
@@ -2741,6 +2728,9 @@ if test -n "$with_gallium_drivers"; then
PKG_CHECK_MODULES([ETNAVIV], [libdrm >= $LIBDRM_ETNAVIV_REQUIRED libdrm_etnaviv >= $LIBDRM_ETNAVIV_REQUIRED])
require_libdrm "etnaviv"
;;
ximx)
HAVE_GALLIUM_IMX=yes
;;
xtegra)
HAVE_GALLIUM_TEGRA=yes
require_libdrm "tegra"
@@ -2827,8 +2817,8 @@ if test -n "$with_gallium_drivers"; then
DEFINES="$DEFINES -DUSE_V3D_SIMULATOR"],
[USE_V3D_SIMULATOR=no])
;;
xkmsro)
HAVE_GALLIUM_KMSRO=yes
xpl111)
HAVE_GALLIUM_PL111=yes
;;
xvirgl)
HAVE_GALLIUM_VIRGL=yes
@@ -2845,8 +2835,8 @@ if test -n "$with_gallium_drivers"; then
fi
# XXX: Keep in sync with LLVM_REQUIRED_SWR
AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x7.0.0 -a \
"x$LLVM_VERSION" != x7.0.1)
AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x6.0.0 -a \
"x$LLVM_VERSION" != x6.0.1)
if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
@@ -2861,8 +2851,12 @@ AM_CONDITIONAL(HAVE_SWR_BUILTIN, test "x$HAVE_SWR_BUILTIN" = xyes)
dnl We need to validate some needed dependencies for renderonly drivers.
if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_KMSRO" = xyes ; then
AC_MSG_ERROR([Building with kmsro requires vc4])
if test "x$HAVE_GALLIUM_ETNAVIV" != xyes -a "x$HAVE_GALLIUM_IMX" = xyes ; then
AC_MSG_ERROR([Building with imx requires etnaviv])
fi
if test "x$HAVE_GALLIUM_VC4" != xyes -a "x$HAVE_GALLIUM_PL111" = xyes ; then
AC_MSG_ERROR([Building with pl111 requires vc4])
fi
if test "x$HAVE_GALLIUM_NOUVEAU" != xyes -a "x$HAVE_GALLIUM_TEGRA" = xyes; then
@@ -2910,7 +2904,6 @@ if test "x$enable_llvm" = xyes; then
LLVM_LDFLAGS=`$LLVM_CONFIG --ldflags`
LLVM_CFLAGS=$LLVM_CPPFLAGS # CPPFLAGS seem to be sufficient
LLVM_CXXFLAGS=`strip_unwanted_llvm_flags "$LLVM_CONFIG --cxxflags"`
LLVM_CXXFLAGS="$CXX11_CXXFLAGS $LLVM_CXXFLAGS"
dnl Set LLVM_LIBS - This is done after the driver configuration so
dnl that drivers can add additional components to LLVM_COMPONENTS.
@@ -2949,7 +2942,7 @@ if test "x$enable_llvm" = xyes; then
dnl the LLVM library propagated in the Libs.private of the respective .pc
dnl file which ensures complete dependency information when statically
dnl linking.
if test "x$enable_glx" = xgallium-xlib; then
if test "x$enable_glx" == xgallium-xlib; then
GL_PC_LIB_PRIV="$GL_PC_LIB_PRIV $LLVM_LIBS"
fi
if test "x$enable_gallium_osmesa" = xyes; then
@@ -2959,13 +2952,14 @@ fi
AM_CONDITIONAL(HAVE_GALLIUM_SVGA, test "x$HAVE_GALLIUM_SVGA" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_I915, test "x$HAVE_GALLIUM_I915" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_KMSRO, test "x$HAVE_GALLIUM_KMSRO" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_PL111, test "x$HAVE_GALLIUM_PL111" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_R300, test "x$HAVE_GALLIUM_R300" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_R600, test "x$HAVE_GALLIUM_R600" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_RADEONSI, test "x$HAVE_GALLIUM_RADEONSI" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_NOUVEAU, test "x$HAVE_GALLIUM_NOUVEAU" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_ETNAVIV, test "x$HAVE_GALLIUM_ETNAVIV" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_IMX, test "x$HAVE_GALLIUM_IMX" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_TEGRA, test "x$HAVE_GALLIUM_TEGRA" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_SOFTPIPE, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes)
AM_CONDITIONAL(HAVE_GALLIUM_LLVMPIPE, test "x$HAVE_GALLIUM_LLVMPIPE" = xyes)
@@ -3004,7 +2998,6 @@ AM_CONDITIONAL(HAVE_AMD_DRIVERS, test "x$HAVE_GALLIUM_RADEONSI" = xyes -o \
AM_CONDITIONAL(HAVE_BROADCOM_DRIVERS, test "x$HAVE_GALLIUM_VC4" = xyes -o \
"x$HAVE_GALLIUM_V3D" = xyes)
AM_CONDITIONAL(HAVE_FREEDRENO_DRIVERS, test "x$HAVE_GALLIUM_FREEDRENO" = xyes)
AM_CONDITIONAL(HAVE_INTEL_DRIVERS, test "x$HAVE_INTEL_VULKAN" = xyes -o \
"x$HAVE_I965_DRI" = xyes)
@@ -3051,7 +3044,7 @@ AC_SUBST([XVMC_MAJOR], 1)
AC_SUBST([XVMC_MINOR], 0)
AC_SUBST([XA_MAJOR], 2)
AC_SUBST([XA_MINOR], 5)
AC_SUBST([XA_MINOR], 4)
AC_SUBST([XA_PATCH], 0)
AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
@@ -3097,7 +3090,6 @@ AC_CONFIG_FILES([Makefile
src/amd/vulkan/Makefile
src/broadcom/Makefile
src/compiler/Makefile
src/freedreno/Makefile
src/egl/Makefile
src/egl/main/egl.pc
src/egl/wayland/wayland-drm/Makefile
@@ -3108,7 +3100,7 @@ AC_CONFIG_FILES([Makefile
src/gallium/drivers/i915/Makefile
src/gallium/drivers/llvmpipe/Makefile
src/gallium/drivers/nouveau/Makefile
src/gallium/drivers/kmsro/Makefile
src/gallium/drivers/pl111/Makefile
src/gallium/drivers/r300/Makefile
src/gallium/drivers/r600/Makefile
src/gallium/drivers/radeonsi/Makefile
@@ -3117,6 +3109,7 @@ AC_CONFIG_FILES([Makefile
src/gallium/drivers/swr/Makefile
src/gallium/drivers/tegra/Makefile
src/gallium/drivers/etnaviv/Makefile
src/gallium/drivers/imx/Makefile
src/gallium/drivers/v3d/Makefile
src/gallium/drivers/vc4/Makefile
src/gallium/drivers/virgl/Makefile
@@ -3151,10 +3144,11 @@ AC_CONFIG_FILES([Makefile
src/gallium/tests/trivial/Makefile
src/gallium/tests/unit/Makefile
src/gallium/winsys/etnaviv/drm/Makefile
src/gallium/winsys/imx/drm/Makefile
src/gallium/winsys/freedreno/drm/Makefile
src/gallium/winsys/i915/drm/Makefile
src/gallium/winsys/nouveau/drm/Makefile
src/gallium/winsys/kmsro/drm/Makefile
src/gallium/winsys/pl111/drm/Makefile
src/gallium/winsys/radeon/drm/Makefile
src/gallium/winsys/amdgpu/drm/Makefile
src/gallium/winsys/svga/drm/Makefile

View File

@@ -26,12 +26,6 @@
</ul>
</ol>
<h2>ATTENTION:</h2>
<p>
The autotools build is being replaced by the <a href="meson.html">meson</a>
build system. If you haven't yet now is a good time to try using meson and
report any issues you run into.
</p>
<h2 id="basic">1. Basic Usage</h2>

View File

@@ -319,7 +319,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_EXT_memory_object DONE (radeonsi)
GL_EXT_memory_object_fd DONE (radeonsi)
GL_EXT_memory_object_win32 not started
GL_EXT_render_snorm DONE (i965, radeonsi)
GL_EXT_render_snorm DONE (i965)
GL_EXT_semaphore DONE (radeonsi)
GL_EXT_semaphore_fd DONE (radeonsi)
GL_EXT_semaphore_win32 not started
@@ -338,7 +338,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_OES_texture_float_linear DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
GL_OES_texture_half_float DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
GL_OES_texture_half_float_linear DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
GL_OES_texture_view DONE (freedreno, i965/gen8+, r600, radeonsi, nv50, nvc0, softpipe, llvmpipe, swr)
GL_OES_texture_view DONE (i965/gen8+)
GL_OES_viewport_array DONE (i965, nvc0, radeonsi)
GLX_ARB_context_flush_control not started
GLX_ARB_robustness_application_isolation not started

View File

@@ -15,53 +15,6 @@
<div class="content">
<h1>News</h1>
<h2>January 17, 2019</h2>
<p>
<a href="relnotes/18.3.2.html">Mesa 18.3.2</a> is released.
This is a bug-fix release.
</p>
<h2>December 27, 2018</h2>
<p>
<a href="relnotes/18.2.8.html">Mesa 18.2.8</a> is released.
This is a bug-fix release.
<br>
NOTE: It is anticipated that 18.2.8 will be the final release in the
18.2 series. Users of 18.2 are encouraged to migrate to the 18.3
series in order to obtain future fixes.
</p>
<h2>December 13, 2018</h2>
<p>
<a href="relnotes/18.2.7.html">Mesa 18.2.7</a> is released.
This is a bug-fix release.
</p>
<h2>December 11, 2018</h2>
<p>
<a href="relnotes/18.3.1.html">Mesa 18.3.1</a> is released.
This is a bug-fix release.
</p>
<h2>December 7, 2018</h2>
<p>
<a href="relnotes/18.3.0.html">Mesa 18.3.0</a> is released. This is a
new development release. See the release notes for more information
about the release.
</p>
<h2>November 28, 2018</h2>
<p>
<a href="relnotes/18.2.6.html">Mesa 18.2.6</a> is released.
This is a bug-fix release.
</p>
<h2>November 15, 2018</h2>
<p>
<a href="relnotes/18.2.5.html">Mesa 18.2.5</a> is released.
This is a bug-fix release.
</p>
<h2>October 31, 2018</h2>
<p>
<a href="relnotes/18.2.4.html">Mesa 18.2.4</a> is released.

View File

@@ -22,7 +22,6 @@
<li><a href="#prereq-general">General prerequisites</a>
<li><a href="#prereq-dri">For DRI and hardware acceleration</a>
</ul>
<li><a href="#meson">Building with meson</a>
<li><a href="#autoconf">Building with autoconf (Linux/Unix/X11)</a>
<li><a href="#scons">Building with SCons (Windows/Linux)</a>
<li><a href="#android">Building with AOSP (Android)</a>
@@ -40,10 +39,9 @@ Build system.
</p>
<ul>
<li><a href="https://mesonbuild.com">meson</a> is recommended when building on *nix platforms.
<li>Autoconf is another option when building on *nix platforms.
<li>Autoconf is required when building on *nix platforms.
<li><a href="http://www.scons.org/">SCons</a> is required for building on
Windows and optional for Linux (it's an alternative to autoconf/automake or meson.)
Windows and optional for Linux (it's an alternative to autoconf/automake.)
</li>
<li>Android Build system when building as native Android component. Autoconf
is used when when building ARC.
@@ -74,9 +72,7 @@ you think you've spotted a bug let developers know by filing a
<ul>
<li><a href="https://www.python.org/">Python</a> - Python is required.
When building with scons 2.7 is required.
When building with meson 3.5 or newer is required.
When building with autotools 2.7, or 3.5 or later are required.
Version 2.7 or later should work.
</li>
<li><a href="http://www.makotemplates.org/">Python Mako module</a> -
Python Mako module is required. Version 0.8.0 or later should work.
@@ -115,31 +111,11 @@ the packaging tool used by your distro.
... # others
</pre>
<h1 id="meson">2. Building with meson</h1>
<h1 id="autoconf">2. Building with autoconf (Linux/Unix/X11)</h1>
<p>
Meson is the latest build system in mesa, it is currently able to build for
*nix systems like Linux and BSD, and will be able to build for windows as well.
</p>
<p>
The general approach is:
</p>
<pre>
meson builddir/
ninja -C builddir/
sudo ninja -C builddir/ install
</pre>
<p>
Please read the <a href="meson.html">detailed meson instructions</a>
for more information
</p>
<h1 id="autoconf">3. Building with autoconf (Linux/Unix/X11)</h1>
<p>
Although meson is recommended, another supported way to build on *nix systems
is with autoconf.
The primary method to build Mesa on Unix systems is with autoconf.
</p>
<p>
@@ -157,7 +133,7 @@ for more details.
<h1 id="scons">4. Building with SCons (Windows/Linux)</h1>
<h1 id="scons">3. Building with SCons (Windows/Linux)</h1>
<p>
To build Mesa with SCons on Linux or Windows do
@@ -193,7 +169,7 @@ Additional information is available in <a href="README.WIN32">README.WIN32</a>.
<h1 id="android">5. Building with AOSP (Android)</h1>
<h1 id="android">4. Building with AOSP (Android)</h1>
<p>
Currently one can build Mesa for Android as part of the AOSP project, yet
@@ -212,7 +188,7 @@ Android-x86 and/or other resources.
</p>
<h1 id="libs">6. Library Information</h1>
<h1 id="libs">5. Library Information</h1>
<p>
When compilation has finished, look in the top-level <code>lib/</code>
@@ -250,7 +226,7 @@ versions of libGL and device drivers.
</p>
<h1 id="pkg-config">7. Building OpenGL programs with pkg-config</h1>
<h1 id="pkg-config">6. Building OpenGL programs with pkg-config</h1>
<p>
Running <code>make install</code> will install package configuration files

View File

@@ -29,9 +29,6 @@ pre {
/*font-family: monospace;*/
font-size: 10pt;
/*color: black;*/
background-color: #eee;
margin-left: 2em;
padding: .5em;
}
iframe {

View File

@@ -16,11 +16,6 @@
<h1>Compilation and Installation using Meson</h1>
<ul>
<li><a href="#basic">Basic Usage</a></li>
<li><a href="#cross-compilation">Cross-compilation and 32-bit builds</a></li>
</ul>
<h2 id="basic">1. Basic Usage</h2>
<p><strong>The Meson build system is generally considered stable and ready
@@ -53,13 +48,9 @@ To see a description of your options you can run <code>meson configure</code>
along with a build directory to view the selected options for. This will show
your meson global arguments and project arguments, along with their defaults
and your local settings.
</p>
<p>
Meson does not currently support listing options before configure a build
directory, but this feature is being discussed upstream.
For now, the only way to see what options exist is to look at the
<code>meson_options.txt</code> file at the root of the project.
</p>
<pre>
@@ -114,14 +105,14 @@ to invoke non-default targets for ninja to update them:
<dl>
<dt><code>Environment Variables</code></dt>
<dd><p>Meson supports the standard CC and CXX environment variables for
changing the default compiler. Meson does support CFLAGS, CXXFLAGS, etc. But
their use is discouraged because of the many caveats in using them. Instead it
is recomended to use <code>-D${lang}_args</code> and
<code>-D${lang}_link_args</code> instead. Among the benefits of these options
is that they are guaranteed to persist across rebuilds and reconfigurations.
changing the default compiler, and CFLAGS, CXXFLAGS, and LDFLAGS for setting
options to the compiler and linker during the initial configuration.
Meson does not allow changing compiler in a configured builddir, you will need
to create a new build dir for a different compiler.
These arguments are consumed and stored by meson when it is initialized. To
change these flags after the build is initialized (or when doing a first
initialization), consider using <code>-D${lang}_args</code> and
<code>-D${lang}_link_args</code> instead. Meson will never change compiler in a
configured build directory.
</p>
<pre>
@@ -144,56 +135,11 @@ the popular compilers, a complete list is available
<dt><code>LLVM</code></dt>
<dd><p>Meson includes upstream logic to wrap llvm-config using its standard
dependency interface.
dependency interface. It will search <code>$PATH</code> (or <code>%PATH%</code> on windows) for
llvm-config (and llvm-config$version and llvm-config-$version), so using an
LLVM from a non-standard path is as easy as
<code>PATH=/path/with/llvm-config:$PATH meson build</code>.
</p></dd>
<dd><p>
As of meson 0.49.0 meson also has the concept of a
<a href="https://mesonbuild.com/Native-environments.html">"native file"</a>,
these files provide information about the native build environment (as opposed
to a cross build environment). They are ini formatted and can override where to
find llvm-config:
custom-llvm.ini
<pre>
[binaries]
llvm-config = '/usr/local/bin/llvm/llvm-config'
</pre>
Then configure meson:
<pre>
meson builddir/ --native-file custom-llvm.ini
</pre>
</p></dd>
<dd><p>
For selecting llvm-config for cross compiling a
<a href="https://mesonbuild.com/Cross-compilation.html#defining-the-environment">"cross file"</a>
should be used. It uses the same format as the native file above:
cross-llvm.ini
<pre>
[binaries]
...
llvm-config = '/usr/lib/llvm-config-32'
</pre>
Then configure meson:
<pre>
meson builddir/ --cross-file cross-llvm.ini
</pre>
See the <a href="#cross-compilation">Cross Compilation</a> section for more information.
</dd></p>
<dd><p>
For older versions of meson <code>$PATH</code> (or <code>%PATH%</code> on
windows) will be searched for llvm-config (and llvm-config$version and
llvm-config-$version), you can override this environment variable to control
the search: <code>PATH=/path/with/llvm-config:$PATH meson build</code>.
</dd></p>
</dl>
<dl>
@@ -244,93 +190,6 @@ is unrelated to the <code>buildtype</code>; setting the latter to
</dd>
</dl>
<h2 id="cross-compilation">2. Cross-compilation and 32-bit builds</h2>
<p><a href="https://mesonbuild.com/Cross-compilation.html">Meson supports
cross-compilation</a> by specifying a number of binary paths and
settings in a file and passing this file to <code>meson</code> or
<code>meson configure</code> with the <code>--cross-file</code>
parameter.</p>
<p>This file can live at any location, but you can use the bare filename
(without the folder path) if you put it in $XDG_DATA_HOME/meson/cross or
~/.local/share/meson/cross</p>
<p>Below are a few example of cross files, but keep in mind that you
will likely have to alter them for your system.</p>
<p>
Those running on ArchLinux can use the AUR-maintained packages for some
of those, as they'll have the right values for your system:
<ul>
<li><a href="https://aur.archlinux.org/packages/meson-cross-x86-linux-gnu">meson-cross-x86-linux-gnu</a></li>
<li><a href="https://aur.archlinux.org/packages/meson-cross-aarch64-linux-gnu">meson-cross-aarch64-linux-gnu</a></li>
</ul>
</p>
<p>
32-bit build on x86 linux:
<pre>
[binaries]
c = '/usr/bin/gcc'
cpp = '/usr/bin/g++'
ar = '/usr/bin/gcc-ar'
strip = '/usr/bin/strip'
pkgconfig = '/usr/bin/pkg-config-32'
llvm-config = '/usr/bin/llvm-config32'
[properties]
c_args = ['-m32']
c_link_args = ['-m32']
cpp_args = ['-m32']
cpp_link_args = ['-m32']
[host_machine]
system = 'linux'
cpu_family = 'x86'
cpu = 'i686'
endian = 'little'
</pre>
</p>
<p>
64-bit build on ARM linux:
<pre>
[binaries]
c = '/usr/bin/aarch64-linux-gnu-gcc'
cpp = '/usr/bin/aarch64-linux-gnu-g++'
ar = '/usr/bin/aarch64-linux-gnu-gcc-ar'
strip = '/usr/bin/aarch64-linux-gnu-strip'
pkgconfig = '/usr/bin/aarch64-linux-gnu-pkg-config'
exe_wrapper = '/usr/bin/qemu-aarch64-static'
[host_machine]
system = 'linux'
cpu_family = 'aarch64'
cpu = 'aarch64'
endian = 'little'
</pre>
</p>
<p>
64-bit build on x86 windows:
<pre>
[binaries]
c = '/usr/bin/x86_64-w64-mingw32-gcc'
cpp = '/usr/bin/x86_64-w64-mingw32-g++'
ar = '/usr/bin/x86_64-w64-mingw32-ar'
strip = '/usr/bin/x86_64-w64-mingw32-strip'
pkgconfig = '/usr/bin/x86_64-w64-mingw32-pkg-config'
exe_wrapper = 'wine'
[host_machine]
system = 'windows'
cpu_family = 'x86_64'
cpu = 'i686'
endian = 'little'
</pre>
</p>
</div>
</body>
</html>

View File

@@ -23,16 +23,6 @@ Mesa provides feature/development and stable releases.
The table below lists the date and release manager that is expected to do the
specific release.
<br>
Regular updates will ensure that the schedule for the current and the
next two feature releases are shown in the table.
<br>
In order to keep the whole releasing team up to date with the tools
used, best practices and other details, the member in charge of the
next feature release will be in constant rotation.
<br>
The way the release schedule works is
explained <a href="releasing.html#schedule" target="_parent">here</a>.
<br>
Take a look <a href="submittingpatches.html#criteria" target="_parent">here</a>
if you'd like to nominate a patch in the next stable release.
</p>
@@ -49,129 +39,47 @@ if you'd like to nominate a patch in the next stable release.
<th>Notes</th>
</tr>
<tr>
<td rowspan="3">18.2</td>
<td>2018-11-14</td>
<td>18.2.5</td>
<td>Juan A. Suarez</td>
<td/>
</tr>
<tr>
<td>2018-11-28</td>
<td>18.2.6</td>
<td>Juan A. Suarez</td>
<td/>
</tr>
<tr>
<td>2018-12-12</td>
<td>18.2.7</td>
<td>Juan A. Suarez</td>
<td>Last planned 18.2.x release</td>
</tr>
<td rowspan="4">18.3</td>
<td>2019-01-30</td>
<td>18.3.3</td>
<td>2018-10-31</td>
<td>18.3.0-rc1</td>
<td>Emil Velikov</td>
<td>
<td></td>
</tr>
<tr>
<td>2019-02-13</td>
<td>18.3.4</td>
<td>2018-11-07</td>
<td>18.3.0-rc2</td>
<td>Emil Velikov</td>
<td>
<td/>
</tr>
<tr>
<td>2019-02-27</td>
<td>18.3.5</td>
<td>2018-11-14</td>
<td>18.3.0-rc3</td>
<td>Emil Velikov</td>
<td>
<td/>
</tr>
<tr>
<td>2019-03-13</td>
<td>18.3.6</td>
<td>2018-11-21</td>
<td>18.3.0-rc4</td>
<td>Emil Velikov</td>
<td>Last planned 18.3.x release</td>
</tr>
<tr>
<td rowspan="4">19.0</td>
<td>2019-01-29</td>
<td>19.0.0-rc1</td>
<td>Dylan Baker</td>
<td>
</tr>
<tr>
<td>2019-02-05</td>
<td>19.0.0-rc2</td>
<td>Dylan Baker</td>
<td>
</tr>
<tr>
<td>2019-02-12</td>
<td>19.0.0-rc3</td>
<td>Dylan Baker</td>
<td>
</tr>
<tr>
<td>2019-02-19</td>
<td>19.0.0-rc4</td>
<td>Dylan Baker</td>
<td>Last planned RC/Final release</td>
</tr>
<tr>
<td rowspan="4">19.1</td>
<td>2019-04-30</td>
<td>19.1.0-rc1</td>
<td>Andres Gomez</td>
<td>
</tr>
<tr>
<td>2019-05-07</td>
<td>19.1.0-rc2</td>
<td>Andres Gomez</td>
<td>
</tr>
<tr>
<td>2019-05-14</td>
<td>19.1.0-rc3</td>
<td>Andres Gomez</td>
<td>
</tr>
<tr>
<td>2019-05-21</td>
<td>19.1.0-rc4</td>
<td>Andres Gomez</td>
<td>Last planned RC/Final release</td>
</tr>
<tr>
<td rowspan="4">19.2</td>
<td>2019-08-06</td>
<td>19.2.0-rc1</td>
<td>Emil Velikov</td>
<td>
</tr>
<tr>
<td>2019-08-13</td>
<td>19.2.0-rc2</td>
<td>Emil Velikov</td>
<td>
</tr>
<tr>
<td>2019-08-20</td>
<td>19.2.0-rc3</td>
<td>Emil Velikov</td>
<td>
</tr>
<tr>
<td>2019-08-27</td>
<td>19.2.0-rc4</td>
<td>Emil Velikov</td>
<td>Last planned RC/Final release</td>
</tr>
<tr>
<td rowspan="4">19.3</td>
<td>2019-10-15</td>
<td>19.3.0-rc1</td>
<td>Juan A. Suarez</td>
<td>
</tr>
<tr>
<td>2019-10-22</td>
<td>19.3.0-rc2</td>
<td>Juan A. Suarez</td>
<td>
</tr>
<tr>
<td>2019-10-29</td>
<td>19.3.0-rc3</td>
<td>Juan A. Suarez</td>
<td>
</tr>
<tr>
<td>2019-11-05</td>
<td>19.3.0-rc4</td>
<td>Juan A. Suarez</td>
<td>Last planned RC/Final release</td>
<td>Last planned RC/final release</td>
</tr>
</table>

View File

@@ -56,10 +56,9 @@ For example:
<p>
Releases should happen on Wednesdays. Delays can occur although those
should be kept to a minimum.
should be keep to a minimum.
<br>
See our <a href="release-calendar.html" target="_parent">calendar</a>
for information about how the release schedule is planned, and the
See our <a href="release-calendar.html" target="_parent">calendar</a> for the
date and other details for individual releases.
</p>
@@ -68,9 +67,6 @@ date and other details for individual releases.
<li>Available approximately every three months.
<li>Initial timeplan available 2-4 weeks before the planned branchpoint (rc1)
on the mesa-announce@ mailing list.
<li>Typically, the final release will happen after 4
candidates. Additional ones may be needed in order to resolve blocking
regressions, though.
<li>A <a href="#prerelease">pre-release</a> announcement should be available
approximately 24 hours before the final (non-rc) release.
</ul>
@@ -88,12 +84,6 @@ Note: There is one or two releases overlap when changing branches. For example:
<br>
The final release from the 12.0 series Mesa 12.0.5 will be out around the same
time (or shortly after) 13.0.1 is out.
<br>
This also involves that, as a final release may be delayed due to the
need of additional candidates to solve some blocking regression(s),
the release manager might have to update
the <a href="release-calendar.html" target="_parent">calendar</a> with
additional bug fix releases of the current stable branch.
</p>
@@ -122,21 +112,18 @@ the autoconf and scons build.
<p>Done continuously up-to the <a href="#prerelease">pre-release</a> announcement.</p>
<p>
Developers can request, <em>as an exception</em>, patches to be applied up-to
the last one hour before the actual release. This is made <strong>only</strong>
with explicit permission/request, and the patch <strong>must</strong> be very
well contained. Thus it cannot affect more than one driver/subsystem.
As an exception, patches can be applied up-to the last ~1h before the actual
release. This is made <strong>only</strong> with explicit permission/request,
and the patch <strong>must</strong> be very well contained. Thus it cannot
affect more than one driver/subsystem.
</p>
<p>Following developers have requested permanent exception</p>
<ul>
<li><em>Ilia Mirkin</em>
<li><em>AMD team</em>
</ul>
<p>
Currently Ilia Mirkin and AMD devs have requested "permanent" exception.
</p>
<p>The following must pass:</p>
<ul>
<li>make distcheck, scons and scons check
<li>make distcheck, scons and scons check must pass
<li>Testing with different version of system components - LLVM and others is also
performed where possible.
<li>As a general rule, testing with various combinations of configure
@@ -144,9 +131,9 @@ switches, depending on the specific patchset.
</ul>
<p>
These are achieved by combination of <a href="basictesting">local testing</a>,
which includes mingw-w64 cross compilation and AppVeyor plus Travis-CI, the
latter two as part of their Github integration.
Achieved by combination of local ad-hoc scripts, mingw-w64 cross
compilation and AppVeyor plus Travis-CI, the latter as part of their
Github integration.
</p>
<p>
@@ -238,7 +225,7 @@ in the main repository under <code>staging/X.Y</code>. For example:
Notes:
</p>
<ul>
<li>People are encouraged to test the staging branch and report regressions.</li>
<li>People are encouraged to test the branch and report regressions.</li>
<li>The branch history is not stable and it <strong>will</strong> be rebased,</li>
</ul>
@@ -458,7 +445,7 @@ Ensure the latest code is available - both in your local master and the
relevant branch.
</p>
<h3 id="basictesting">Perform basic testing</h3>
<h3>Perform basic testing</h3>
<p>
Most of the testing should already be done during the

View File

@@ -21,13 +21,6 @@ The release notes summarize what's new or changed in each Mesa release.
</p>
<ul>
<li><a href="relnotes/18.3.2.html">18.3.2 release notes</a>
<li><a href="relnotes/18.2.8.html">18.2.8 release notes</a>
<li><a href="relnotes/18.2.7.html">18.2.7 release notes</a>
<li><a href="relnotes/18.3.1.html">18.3.1 release notes</a>
<li><a href="relnotes/18.3.0.html">18.3.0 release notes</a>
<li><a href="relnotes/18.2.6.html">18.2.6 release notes</a>
<li><a href="relnotes/18.2.5.html">18.2.5 release notes</a>
<li><a href="relnotes/18.2.4.html">18.2.4 release notes</a>
<li><a href="relnotes/18.2.3.html">18.2.3 release notes</a>
<li><a href="relnotes/18.2.2.html">18.2.2 release notes</a>

View File

@@ -1,172 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.5 Release Notes / November 15, 2018</h1>
<p>
Mesa 18.2.5 is a bug fix release which fixes bugs found since the 18.2.4 release.
</p>
<p>
Mesa 18.2.5 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
dddc28928b6f4083a0d5120b58c1c8e2dc189ab5c14299c08a386607fdbbdce7 mesa-18.2.5.tar.gz
b12c32872832e5353155e1e8026e1f1ab75bba9dc5b178d712045684d26c2b73 mesa-18.2.5.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105731">Bug 105731</a> - linker error &quot;fragment shader input ... has no matching output in the previous stage&quot; when previous stage's output declaration in a separate shader object</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107511">Bug 107511</a> - KHR/khrplatform.h not always installed when needed</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107626">Bug 107626</a> - [SNB] The graphical corruption and GPU hang occur sometimes on the piglit test &quot;arb_texture_multisample-large-float-texture&quot; with parameter --fp16</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108082">Bug 108082</a> - warning: unknown warning option '-Wno-format-truncation' [-Wunknown-warning-option]</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108560">Bug 108560</a> - Mesa 32 is built without sse</li>
</ul>
<h2>Changes</h2>
<p>Andre Heider (1):</p>
<ul>
<li>st/nine: fix stack corruption due to ABI mismatch</li>
</ul>
<p>Andrii Simiklit (1):</p>
<ul>
<li>i965/batch: don't ignore the 'brw_new_batch' call for a 'new batch'</li>
</ul>
<p>Dylan Baker (2):</p>
<ul>
<li>meson: link gallium nine with pthreads</li>
<li>meson: fix libatomic tests</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>egl/glvnd: correctly report errors when vendor cannot be found</li>
<li>m4: add Werror when checking for compiler flags</li>
</ul>
<p>Eric Engestrom (6):</p>
<ul>
<li>svga: add missing meson build dependency</li>
<li>clover: add missing meson build dependency</li>
<li>wsi/wayland: use proper VkResult type</li>
<li>wsi/wayland: only finish() a successfully init()ed display</li>
<li>configure: install KHR/khrplatform.h when needed</li>
<li>meson: install KHR/khrplatform.h when needed</li>
</ul>
<p>Gert Wollny (1):</p>
<ul>
<li>virgl/vtest-winsys: Use virgl version of bind flags</li>
</ul>
<p>Jonathan Gray (1):</p>
<ul>
<li>intel/tools: include stdarg.h in error2aub</li>
</ul>
<p>Juan A. Suarez Romero (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.4</li>
<li>cherry-ignore: add explicit 18.3 only nominations</li>
<li>cherry-ignore: i965/batch: avoid reverting batch buffer if saved state is an empty</li>
<li>Update version to 18.2.5</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv/android: mark gralloc allocated BOs as external</li>
</ul>
<p>Marek Olšák (3):</p>
<ul>
<li>ac: fix ac_build_fdiv for f64</li>
<li>st/va: fix incorrect use of resource_destroy</li>
<li>include: update GL &amp; GLES headers (v2)</li>
</ul>
<p>Matt Turner (2):</p>
<ul>
<li>util/ralloc: Switch from DEBUG to NDEBUG</li>
<li>util/ralloc: Make sizeof(linear_header) a multiple of 8</li>
</ul>
<p>Olivier Fourdan (1):</p>
<ul>
<li>wayland/egl: Resize EGL surface on update buffer for swrast</li>
</ul>
<p>Rhys Perry (1):</p>
<ul>
<li>glsl_to_tgsi: don't create 64-bit integer MAD/FMA</li>
</ul>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv: disable conditional rendering for vkCmdCopyQueryPoolResults()</li>
<li>radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+</li>
</ul>
<p>Sergii Romantsov (1):</p>
<ul>
<li>autotools: library-dependency when no sse and 32-bit</li>
</ul>
<p>Timothy Arceri (4):</p>
<ul>
<li>st/mesa: calculate buffer size correctly for packed uniforms</li>
<li>st/glsl_to_nir: fix next_stage gathering</li>
<li>nir: add glsl_type_is_integer() helper</li>
<li>nir: don't pack varyings ints with floats unless flat</li>
</ul>
<p>Vadym Shovkoplias (1):</p>
<ul>
<li>glsl/linker: Fix out variables linking during single stage</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>r600/sb: Fix constant logical operand in assert.</li>
</ul>
</div>
</body>
</html>

View File

@@ -1,179 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.6 Release Notes / November 28, 2018</h1>
<p>
Mesa 18.2.6 is a bug fix release which fixes bugs found since the 18.2.5 release.
</p>
<p>
Mesa 18.2.6 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
e0ea1236dbc6c412b02e1b5d7f838072525971a6630246fa82ae4466a6d8a587 mesa-18.2.6.tar.gz
9ebafa4f8249df0c718e93b9ca155e3593a1239af303aa2a8b0f2056a7efdc12 mesa-18.2.6.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107626">Bug 107626</a> - [SNB] The graphical corruption and GPU hang occur sometimes on the piglit test &quot;arb_texture_multisample-large-float-texture&quot; with parameter --fp16</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107856">Bug 107856</a> - i965 incorrectly calculates the number of layers for texture views (assert)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108630">Bug 108630</a> - [G965] piglit.spec.!opengl 1_2.tex3d-maxsize spins forever</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108713">Bug 108713</a> - Gallium: use after free with transform feedback</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108829">Bug 108829</a> - [meson] libglapi exports internal API</li>
</ul>
<h2>Changes</h2>
<p>Andrii Simiklit (1):</p>
<ul>
<li>i965/batch: avoid reverting batch buffer if saved state is an empty</li>
</ul>
<p>Bas Nieuwenhuizen (1):</p>
<ul>
<li>radv: Fix opaque metadata descriptor last layer.</li>
</ul>
<p>Brian Paul (1):</p>
<ul>
<li>scons/svga: remove opt from the list of valid build types</li>
</ul>
<p>Danylo Piliaiev (1):</p>
<ul>
<li>i965: Fix calculation of layers array length for isl_view</li>
</ul>
<p>Dylan Baker (2):</p>
<ul>
<li>meson: Don't set -Wall</li>
<li>meson: Don't force libva to required from auto</li>
</ul>
<p>Emil Velikov (13):</p>
<ul>
<li>bin/get-pick-list.sh: simplify git oneline printing</li>
<li>bin/get-pick-list.sh: prefix output with "[stable] "</li>
<li>bin/get-pick-list.sh: handle "typod" usecase.</li>
<li>bin/get-pick-list.sh: handle the fixes tag</li>
<li>bin/get-pick-list.sh: tweak the commit sha matching pattern</li>
<li>bin/get-pick-list.sh: flesh out is_sha_nomination</li>
<li>bin/get-pick-list.sh: handle fixes tag with missing colon</li>
<li>bin/get-pick-list.sh: handle unofficial "broken by" tag</li>
<li>bin/get-pick-list.sh: use test instead of [ ]</li>
<li>bin/get-pick-list.sh: handle reverts prior to the branchpoint</li>
<li>travis: drop unneeded x11proto-xf86vidmode-dev</li>
<li>glx: make xf86vidmode mandatory for direct rendering</li>
<li>travis: adding missing x11-xcb for meson+vulkan</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>vc4: Make sure we make ro scanout resources for create_with_modifiers.</li>
</ul>
<p>Eric Engestrom (5):</p>
<ul>
<li>meson: only run vulkan's meson.build when building vulkan</li>
<li>gbm: remove unnecessary meson include</li>
<li>meson: fix wayland-less builds</li>
<li>egl: add missing glvnd entrypoint for EGL_ANDROID_blob_cache</li>
<li>glapi: add missing visibility args</li>
</ul>
<p>Erik Faye-Lund (1):</p>
<ul>
<li>mesa/main: remove bogus error for zero-sized images</li>
</ul>
<p>Gert Wollny (3):</p>
<ul>
<li>mesa: Reference count shaders that are used by transform feedback objects</li>
<li>r600: clean up the GS ring buffers when the context is destroyed</li>
<li>glsl: free or reuse memory allocated for TF varying</li>
</ul>
<p>Jason Ekstrand (2):</p>
<ul>
<li>nir/lower_alu_to_scalar: Don't try to lower unpack_32_2x16</li>
<li>anv: Put robust buffer access in the pipeline hash</li>
</ul>
<p>Juan A. Suarez Romero (6):</p>
<ul>
<li>cherry-ignore: add explicit 18.3 only nominations</li>
<li>cherry-ignore: intel/aub_viewer: fix dynamic state printing</li>
<li>cherry-ignore: intel/aub_viewer: Print blend states properly</li>
<li>cherry-ignore: mesa/main: fix incorrect depth-error</li>
<li>docs: add sha256 checksums for 18.2.5</li>
<li>Update version to 18.2.6</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nir/spirv: cast shift operand to u32</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>i965: Add PCI IDs for new Amberlake parts that are Coffeelake based</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>egl/dri: fix error value with unknown drm format</li>
</ul>
<p>Marek Olšák (2):</p>
<ul>
<li>winsys/amdgpu: fix a buffer leak in amdgpu_bo_from_handle</li>
<li>winsys/amdgpu: fix a device handle leak in amdgpu_winsys_create</li>
</ul>
<p>Rodrigo Vivi (4):</p>
<ul>
<li>i965: Add a new CFL PCI ID.</li>
<li>intel: aubinator: Adding missed platforms to the error message.</li>
<li>intel: Introducing Amber Lake platform</li>
<li>intel: Introducing Whiskey Lake platform</li>
</ul>
</div>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.7 Release Notes / December 13, 2018</h1>
<p>
Mesa 18.2.7 is a bug fix release which fixes bugs found since the 18.2.6 release.
</p>
<p>
Mesa 18.2.7 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
092351cfbcd430ec595fbd3a3d8d253fd62c29074e1740d7198b00289ab400f8 mesa-18.2.7.tar.gz
9c7b02560d89d77ca279cd21f36ea9a49e9ffc5611f6fe35099357d744d07ae6 mesa-18.2.7.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106577">Bug 106577</a> - broken rendering with nine and nouveau (GM107)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108245">Bug 108245</a> - RADV/Vega: Low mip levels of large BCn textures get corrupted by vkCmdCopyBufferToImage</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108311">Bug 108311</a> - Query buffer object support is broken on r600.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108894">Bug 108894</a> - [anv] vkCmdCopyBuffer() and vkCmdCopyQueryPoolResults() write-after-write hazard</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108909">Bug 108909</a> - Vkd3d test failure test_resolve_non_issued_query_data()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108914">Bug 108914</a> - blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108925">Bug 108925</a> - vkCmdCopyQueryPoolResults(VK_QUERY_RESULT_WAIT_BIT) for timestamps with large query count hangs</li>
</ul>
<h2>Changes</h2>
<p>Alex Smith (1):</p>
<ul>
<li>radv: Flush before vkCmdWriteTimestamp() if needed</li>
</ul>
<p>Bas Nieuwenhuizen (4):</p>
<ul>
<li>radv: Align large buffers to the fragment size.</li>
<li>radv: Clamp gfx9 image view extents to the allocated image extents.</li>
<li>radv/android: Mark android WSI image as shareable.</li>
<li>radv/android: Use buffer metadata to determine scanout compat.</li>
</ul>
<p>Dave Airlie (2):</p>
<ul>
<li>r600: make suballocator 256-bytes align</li>
<li>radv: use 3d shader for gfx9 copies if dst is 3d</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>egl/wayland: bail out when drmGetMagic fails</li>
<li>egl/wayland: plug memory leak in drm_handle_device()</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>v3d: Fix a leak of the transfer helper on screen destroy.</li>
<li>vc4: Fix a leak of the transfer helper on screen destroy.</li>
<li>v3d: Fix a leak of the disassembled instruction string during debug dumps.</li>
</ul>
<p>Eric Engestrom (3):</p>
<ul>
<li>anv: correctly use vulkan 1.0 by default</li>
<li>wsi/display: fix mem leak when freeing swapchains</li>
<li>vulkan/wsi: fix s/,/;/ typo</li>
</ul>
<p>Gurchetan Singh (3):</p>
<ul>
<li>virgl: quadruple command buffer size</li>
<li>virgl: avoid large inline transfers</li>
<li>virgl: don't mark buffers as unclean after a write</li>
</ul>
<p>Juan A. Suarez Romero (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.6</li>
<li>cherry-ignore: freedreno: Fix autotools build.</li>
<li>cherry-ignore: mesa: Revert INTEL_fragment_shader_ordering support</li>
<li>Update version to 18.2.7</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nv50,nvc0: Fix gallium nine regression regarding sampler bindings</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>anv: flush pipeline before query result copies</li>
<li>anv/query: flush render target before copying results</li>
</ul>
<p>Michal Srb (2):</p>
<ul>
<li>gallium: Constify drisw_loader_funcs struct</li>
<li>drisw: Use separate drisw_loader_funcs for shm</li>
</ul>
<p>Nicolai Hähnle (2):</p>
<ul>
<li>egl/wayland: rather obvious build fix</li>
<li>meson: link LLVM 'native' component when LLVM is available</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: rework the TC-compat HTILE hardware bug with COND_EXEC</li>
</ul>
<p>Thomas Hellstrom (2):</p>
<ul>
<li>st/xa: Fix a memory leak</li>
<li>winsys/svga: Fix a memory leak</li>
</ul>
<p>Tobias Klausmann (1):</p>
<ul>
<li>amd/vulkan: meson build - use radv_deps for libvulkan_radeon</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>st/xvmc: Add X11 include path.</li>
</ul>
</div>
</body>
</html>

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@@ -1,183 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.8 Release Notes / December 27, 2018</h1>
<p>
Mesa 18.2.8 is a bug fix release which fixes bugs found since the 18.2.7 release.
</p>
<p>
Mesa 18.2.8 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
77512edc0a84e19c7131a0e2e5ebf1beaf1494dc4b71508fcc92d06d65f9f4f5 mesa-18.2.8.tar.gz
1d2ed9fd435d86d95b7215b287258d3e6b1180293a36f688e5a2efc18298d863 mesa-18.2.8.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108114">Bug 108114</a> - [vulkancts] new VK_KHR_16bit_storage tests fail.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108116">Bug 108116</a> - [vulkancts] stencil partial clear tests fail.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108910">Bug 108910</a> - Vkd3d test failure test_multisample_array_texture()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108911">Bug 108911</a> - Vkd3d test failure test_clear_render_target_view()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109081">Bug 109081</a> - [bisected] [HSW] Regression in clipping.user_defined.clip_* vulkancts tests</li>
</ul>
<h2>Changes</h2>
<p>Alex Deucher (3):</p>
<ul>
<li>pci_ids: add new vega10 pci ids</li>
<li>pci_ids: add new vega20 pci id</li>
<li>pci_ids: add new VegaM pci id</li>
</ul>
<p>Axel Davy (3):</p>
<ul>
<li>st/nine: Fix volumetexture dtor on ctor failure</li>
<li>st/nine: Bind src not dst in nine_context_box_upload</li>
<li>st/nine: Add src reference to nine_context_range_upload</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>nir: properly clear the entry sources in copy_prop_vars</li>
</ul>
<p>Dylan Baker (1):</p>
<ul>
<li>meson: Fix ppc64 little endian detection</li>
</ul>
<p>Emil Velikov (9):</p>
<ul>
<li>glx: mandate xf86vidmode only for "drm" dri platforms</li>
<li>bin/get-pick-list.sh: rework handing of sha nominations</li>
<li>bin/get-pick-list.sh: warn when commit lists invalid sha</li>
<li>meson: don't require glx/egl/gbm with gallium drivers</li>
<li>pipe-loader: meson: reference correct library</li>
<li>TODO: glx: meson: build dri based glx tests, only with -Dglx=dri</li>
<li>glx: meson: drop includes from a link-only library</li>
<li>glx: meson: wire up the dispatch-index-check test</li>
<li>glx/test: meson: assorted include fixes</li>
</ul>
<p>Eric Anholt (2):</p>
<ul>
<li>v3d: Make sure that a thrsw doesn't split a multop from its umul24.</li>
<li>v3d: Add missing flagging of SYNCB as a TSY op.</li>
</ul>
<p>Erik Faye-Lund (2):</p>
<ul>
<li>virgl: wrap vertex element state in a struct</li>
<li>virgl: work around bad assumptions in virglrenderer</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
</ul>
<p>Ian Romanick (2):</p>
<ul>
<li>i965/vec4/dce: Don't narrow the write mask if the flags are used</li>
<li>Revert "nir/lower_indirect: Bail early if modes == 0"</li>
</ul>
<p>Jan Vesely (1):</p>
<ul>
<li>clover: Fix build after clang r348827</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>nir/constant_folding: Fix source bit size logic</li>
</ul>
<p>Jon Turney (1):</p>
<ul>
<li>glx: Fix compilation with GLX_USE_WINDOWSGL</li>
</ul>
<p>Juan A. Suarez Romero (7):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.7</li>
<li>cherry-ignore: add explicit 18.3 only nominations</li>
<li>cherry-ignore: meson: libfreedreno depends upon libdrm (for fence support)</li>
<li>cherry-ignore: radv: Fix multiview depth clears</li>
<li>cherry-ignore: nir: properly find the entry to keep in copy_prop_vars</li>
<li>cherry-ignore: intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs</li>
<li>Update version to 18.2.8</li>
</ul>
<p>Kirill Burtsev (1):</p>
<ul>
<li>loader: free error state, when checking the drawable type</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv: don't do partial resolve on layer &gt; 0</li>
</ul>
<p>Rhys Perry (2):</p>
<ul>
<li>radv: don't set surf_index for stencil-only images</li>
<li>ac: split 16-bit ssbo loads that may not be dword aligned</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>mesa/st/nir: fix missing nir_compact_varyings</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: switch on EOP when primitive restart is enabled with triangle strips</li>
</ul>
<p>Vinson Lee (2):</p>
<ul>
<li>meson: Fix typo.</li>
<li>meson: Fix libsensors detection.</li>
</ul>
</div>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.3.3 Release Notes / January 31, 2019</h1>
<p>
Mesa 18.3.3 is a bug fix release which fixes bugs found since the 18.3.2 release.
</p>
<p>
Mesa 18.3.3 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
6b9893942fe8011c7736d51448deb6ef80ece2257e0fac27b02e997a6605d5e4 mesa-18.3.3.tar.gz
2ab6886a6966c532ccbcc3b240925e681464b658244f0cbed752615af3936299 mesa-18.3.3.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108877">Bug 108877</a> - OpenGL CTS gl43 test cases were interrupted due to segment fault</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109023">Bug 109023</a> - error: inlining failed in call to always_inline __m512 _mm512_and_ps(__m512, __m512): target specific option mismatch</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109129">Bug 109129</a> - format_types.h:1220: undefined reference to `_mm256_cvtps_ph'</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109229">Bug 109229</a> - glLinkProgram locks up for ~30 seconds</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109242">Bug 109242</a> - [RADV] The Witcher 3 system freeze</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109488">Bug 109488</a> - Mesa 18.3.2 crash on a specific fragment shader (assert triggered) / already fixed on the master branch.</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (2):</p>
<ul>
<li>bin/get-pick-list.sh: fix the oneline printing</li>
<li>bin/get-pick-list.sh: fix redirection in sh</li>
</ul>
<p>Axel Davy (1):</p>
<ul>
<li>st/nine: Immediately upload user provided textures</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Only use 32 KiB per threadgroup on Stoney.</li>
<li>radv: Set partial_vs_wave for pipelines with just GS, not tess.</li>
<li>nir: Account for atomics in copy propagation.</li>
</ul>
<p>Bruce Cherniak (1):</p>
<ul>
<li>gallium/swr: Fix multi-context sync fence deadlock.</li>
</ul>
<p>Carsten Haitzler (Rasterman) (2):</p>
<ul>
<li>vc4: Use named parameters for the NEON inline asm.</li>
<li>vc4: Declare the cpu pointers as being modified in NEON asm.</li>
</ul>
<p>Danylo Piliaiev (1):</p>
<ul>
<li>glsl: Fix copying function's out to temp if dereferenced by array</li>
</ul>
<p>Dave Airlie (3):</p>
<ul>
<li>dri_interface: add put shm image2 (v2)</li>
<li>glx: add support for putimageshm2 path (v2)</li>
<li>gallium: use put image shm2 path (v2)</li>
</ul>
<p>Dylan Baker (4):</p>
<ul>
<li>meson: allow building dri driver without window system if osmesa is classic</li>
<li>meson: fix swr KNL build</li>
<li>meson: Fix compiler checks for SWR with ICC</li>
<li>meson: Add warnings and errors when using ICC</li>
</ul>
<p>Emil Velikov (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.3.2</li>
<li>cherry-ignore: radv: Fix multiview depth clears</li>
<li>cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices</li>
<li>cherry-ignore: WARNING: Commit XXX lists invalid sha</li>
</ul>
<p>Eric Anholt (2):</p>
<ul>
<li>vc4: Don't leak the GPU fd for renderonly usage.</li>
<li>vc4: Enable NEON asm on meson cross-builds.</li>
</ul>
<p>Eric Engestrom (2):</p>
<ul>
<li>configure: EGL requirements only apply if EGL is built</li>
<li>meson/vdpau: add missing soversion</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>anv/device: fix maximum number of images supported</li>
</ul>
<p>Jason Ekstrand (3):</p>
<ul>
<li>anv/nir: Rework arguments to apply_pipeline_layout</li>
<li>anv: Only parse pImmutableSamplers if the descriptor has samplers</li>
<li>nir/xfb: Fix offset accounting for dvec3/4</li>
</ul>
<p>Karol Herbst (2):</p>
<ul>
<li>nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions</li>
<li>glsl/lower_output_reads: set invariant and precise flags on temporaries</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv: fix invalid binding table index computation</li>
</ul>
<p>Marek Olšák (4):</p>
<ul>
<li>radeonsi: also apply the GS hang workaround to draws without tessellation</li>
<li>radeonsi: fix a u_blitter crash after a shader with FBFETCH</li>
<li>radeonsi: fix rendering to tiny viewports where the viewport center is &gt; 8K</li>
<li>st/mesa: purge framebuffers when unbinding a context</li>
</ul>
<p>Niklas Haas (1):</p>
<ul>
<li>radv: correctly use vulkan 1.0 by default</li>
</ul>
<p>Pierre Moreau (1):</p>
<ul>
<li>meson: Fix with_gallium_icd to with_opencl_icd</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>loader: fix the no-modifiers case</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: clean up setting partial_es_wave for distributed tess on VI</li>
</ul>
<p>Timothy Arceri (5):</p>
<ul>
<li>ac/nir_to_llvm: fix interpolateAt* for arrays</li>
<li>ac/nir_to_llvm: fix clamp shadow reference for more hardware</li>
<li>radv/ac: fix some fp16 handling</li>
<li>glsl: use remap location when serialising uniform program resource data</li>
<li>glsl: Copy function out to temp if we don't directly ref a variable</li>
</ul>
<p>Tomeu Vizoso (1):</p>
<ul>
<li>etnaviv: Consolidate buffer references from framebuffers</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>meson: Fix typo.</li>
</ul>
</div>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.3.4 Release Notes / February 18, 2019</h1>
<p>
Mesa 18.3.4 is a bug fix release which fixes bugs found since the 18.3.3 release.
</p>
<p>
Mesa 18.3.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
e22e6fe4c3aca80fe872a0a7285b6c5523e0cfc0bfb57ffcc3b3d66d292593e4 mesa-18.3.4.tar.gz
32314da4365d37f80d84f599bd9625b00161c273c39600ba63b45002d500bb07 mesa-18.3.4.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109107">Bug 109107</a> - gallium/st/va: change va max_profiles when using Radeon VCN Hardware</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109401">Bug 109401</a> - [DXVK] Project Cars rendering problems</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109543">Bug 109543</a> - After upgrade mesa to 19.0.0~rc1 all vulkan based application stop working [&quot;vulkan-cube&quot; received SIGSEGV in radv_pipeline_init_blend_state at ../src/amd/vulkan/radv_pipeline.c:699]</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109603">Bug 109603</a> - nir_instr_as_deref: Assertion `parent &amp;&amp; parent-&gt;type == nir_instr_type_deref' failed.</li>
</ul>
<h2>Changes</h2>
<p>Bart Oldeman (1):</p>
<ul>
<li>gallium-xlib: query MIT-SHM before using it.</li>
</ul>
<p>Bas Nieuwenhuizen (2):</p>
<ul>
<li>radv: Only look at pImmutableSamples if the descriptor has a sampler.</li>
<li>amd/common: Use correct writemask for shared memory stores.</li>
</ul>
<p>Dylan Baker (2):</p>
<ul>
<li>get-pick-list: Add --pretty=medium to the arguments for Cc patches</li>
<li>meson: Add dependency on genxml to anvil</li>
</ul>
<p>Emil Velikov (5):</p>
<ul>
<li>docs: add sha256 checksums for 18.3.3</li>
<li>cherry-ignore: nv50,nvc0: add explicit settings for recent caps</li>
<li>cherry-ignore: add more 19.0 only nominations from Ilia</li>
<li>cherry-ignore: radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8</li>
<li>Update version to 18.3.4</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>vc4: Fix copy-and-paste fail in backport of NEON asm fixes.</li>
</ul>
<p>Eric Engestrom (2):</p>
<ul>
<li>xvmc: fix string comparison</li>
<li>xvmc: fix string comparison</li>
</ul>
<p>Ernestas Kulik (2):</p>
<ul>
<li>vc4: Fix leak in HW queries error path</li>
<li>v3d: Fix leak in resource setup error path</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
</ul>
<p>Ilia Mirkin (1):</p>
<ul>
<li>nvc0: we have 16k-sized framebuffers, fix default scissors</li>
</ul>
<p>Jason Ekstrand (3):</p>
<ul>
<li>intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()</li>
<li>intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode</li>
<li>nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks</li>
</ul>
<p>Juan A. Suarez Romero (1):</p>
<ul>
<li>anv/cmd_buffer: check for NULL framebuffer</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048</li>
</ul>
<p>Kristian H. Kristensen (1):</p>
<ul>
<li>freedreno/a6xx: Emit blitter dst with OUT_RELOCW</li>
</ul>
<p>Leo Liu (2):</p>
<ul>
<li>st/va: fix the incorrect max profiles report</li>
<li>st/va/vp9: set max reference as default of VP9 reference number</li>
</ul>
<p>Marek Olšák (4):</p>
<ul>
<li>meson: drop the xcb-xrandr version requirement</li>
<li>gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
<li>radeonsi: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
<li>winsys/amdgpu: don't drop manually added fence dependencies</li>
</ul>
<p>Mario Kleiner (2):</p>
<ul>
<li>egl/wayland: Allow client-&gt;server format conversion for PRIME offload. (v2)</li>
<li>egl/wayland-drm: Only announce formats via wl_drm which the driver supports.</li>
</ul>
<p>Oscar Blumberg (1):</p>
<ul>
<li>radeonsi: Fix guardband computation for large render targets</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>freedreno: stop frob'ing pipe_resource::nr_samples</li>
</ul>
<p>Rodrigo Vivi (1):</p>
<ul>
<li>intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.</li>
</ul>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv: fix compiler issues with GCC 9</li>
<li>radv: always export gl_SampleMask when the fragment shader uses it</li>
</ul>
</div>
</body>
</html>

271
docs/relnotes/18.3.5.html Normal file
View File

@@ -0,0 +1,271 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.3.5 Release Notes / March 18, 2019</h1>
<p>
Mesa 18.3.5 is a bug fix release which fixes bugs found since the 18.3.4 release.
</p>
<p>
Mesa 18.3.5 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
5f40a336cb2af9b1d66fa243bb03c2c8a3f9b3f067aab6aaaad4316d1bc0e58b mesa-18.3.5.tar.gz
4027aea82cc63240b3fcf60eec9eea882955f098c989b29357b01d1695747953 mesa-18.3.5.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104297">Bug 104297</a> - [i965] Downward causes GPU hangs and misrendering on Haswell</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104602">Bug 104602</a> - [apitrace] Graphical artifacts in Civilization VI on RX Vega</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107052">Bug 107052</a> - [Regression][bisected]. Crookz - The Big Heist Demo can't be launched despite the &quot;true&quot; flag in &quot;drirc&quot;</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107563">Bug 107563</a> - [RADV] Broken rendering in Unity demos</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108457">Bug 108457</a> - [OpenGL CTS] KHR-GL46.tessellation_shader.single.xfb_captures_data_from_correct_stage fails</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108999">Bug 108999</a> - Calculating the scissors fields when the y is flipped (0 on top) can generate negative numbers that will cause assertion failure later on.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109328">Bug 109328</a> - [BSW BXT GLK] dEQP-VK.subgroups.arithmetic.subgroup regressions</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109443">Bug 109443</a> - Build failure with MSVC when using Scons &gt;= 3.0.2</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109451">Bug 109451</a> - [IVB,SNB] LINE_STRIPs following a TRIANGLE_FAN fail to use primitive restart</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109594">Bug 109594</a> - totem assert failure: totem: src/intel/genxml/gen9_pack.h:72: __gen_uint: La declaración `v &lt;= max' no se cumple.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109597">Bug 109597</a> - wreckfest issues with transparent objects &amp; skybox</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109601">Bug 109601</a> - [Regression] RuneLite GPU rendering broken on 18.3.x</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109698">Bug 109698</a> - dri.pc contents invalid when built with meson</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109735">Bug 109735</a> - [Regression] broken font with mesa_vulkan_overlay</li>
</ul>
<h2>Changes</h2>
<p>Alok Hota (1):</p>
<ul>
<li>swr/rast: bypass size limit for non-sampled textures</li>
</ul>
<p>Andrii Simiklit (1):</p>
<ul>
<li>i965: re-emit index buffer state on a reset option change.</li>
</ul>
<p>Axel Davy (2):</p>
<ul>
<li>st/nine: Ignore window size if error</li>
<li>st/nine: Ignore multisample quality level if no ms</li>
</ul>
<p>Bas Nieuwenhuizen (4):</p>
<ul>
<li>radv: Sync ETC2 whitelisted devices.</li>
<li>radv: Fix float16 interpolation set up.</li>
<li>radv: Allow interpolation on non-float types.</li>
<li>radv: Interpolate less aggressively.</li>
</ul>
<p>Carlos Garnacho (1):</p>
<ul>
<li>wayland/egl: Ensure EGL surface is resized on DRI update_buffers()</li>
</ul>
<p>Danylo Piliaiev (1):</p>
<ul>
<li>glsl/linker: Fix unmatched TCS outputs being reduced to local variable</li>
</ul>
<p>David Shao (1):</p>
<ul>
<li>meson: ensure that xmlpool_options.h is generated for gallium targets that need it</li>
</ul>
<p>Eleni Maria Stea (1):</p>
<ul>
<li>i965: fixed clamping in set_scissor_bits when the y is flipped</li>
</ul>
<p>Emil Velikov (7):</p>
<ul>
<li>docs: add sha256 checksums for 18.3.4</li>
<li>meson: egl: correctly manage loader/xmlconfig</li>
<li>cherry-ignore: add 19.0 only anv/push buffer nominations</li>
<li>cherry-ignore: add gitlab-ci fixup commit</li>
<li>cherry-ignore: ignore glsl_types memory cleanup patch</li>
<li>cherry-ignore: add explicit 19.0 performance optimisations</li>
<li>Update version to 18.3.5</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>egl: fix libdrm-less builds</li>
</ul>
<p>Francisco Jerez (1):</p>
<ul>
<li>intel/fs: Implement extended strides greater than 4 for IR source regions.</li>
</ul>
<p>Ian Romanick (2):</p>
<ul>
<li>intel/fs: nir_op_extract_i8 extracts a byte, not a word</li>
<li>intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer</li>
</ul>
<p>Ilia Mirkin (1):</p>
<ul>
<li>glsl: fix recording of variables for XFB in TCS shaders</li>
</ul>
<p>Jason Ekstrand (10):</p>
<ul>
<li>intel/fs: Bail in optimize_extract_to_float if we have modifiers</li>
<li>compiler/types: Add a contains_64bit helper</li>
<li>nir/xfb: Properly align 64-bit values</li>
<li>nir/xfb: Work in terms of components rather than slots</li>
<li>nir/xfb: Handle compact arrays in gather_xfb_info</li>
<li>anv: Count surfaces for non-YCbCr images in GetDescriptorSetLayoutSupport</li>
<li>spirv: OpImageQueryLod requires a sampler</li>
<li>spirv: Pull offset/stride from the pointer for OpArrayLength</li>
<li>glsl/list: Add a list variant of insert_after</li>
<li>glsl/lower_vector_derefs: Don't use a temporary for TCS outputs</li>
</ul>
<p>Jose Maria Casanova Crespo (1):</p>
<ul>
<li>glsl: TCS outputs can not be transform feedback candidates on GLES</li>
</ul>
<p>José Fonseca (1):</p>
<ul>
<li>scons: Workaround failures with MSVC when using SCons 3.0.[2-4].</li>
</ul>
<p>Juan A. Suarez Romero (3):</p>
<ul>
<li>genxml: add missing field values for 3DSTATE_SF</li>
<li>anv: advertise 8 subpixel precision bits</li>
<li>anv: destroy descriptor sets when pool gets reset</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>intel/fs: Fix opt_peephole_csel to not throw away saturates.</li>
</ul>
<p>Kevin Strasser (1):</p>
<ul>
<li>egl/dri: Avoid out of bounds array access</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>intel: fix urb size for CFL GT1</li>
</ul>
<p>Marek Olšák (5):</p>
<ul>
<li>radeonsi: add driconf option radeonsi_enable_nir</li>
<li>radeonsi: always enable NIR for Civilization 6 to fix corruption</li>
<li>driconf: add Civ6Sub executable for Civilization 6</li>
<li>tgsi: don't set tgsi_info::uses_bindless_images for constbufs and hw atomics</li>
<li>radeonsi: compile clear and copy buffer compute shaders on demand</li>
</ul>
<p>Mauro Rossi (2):</p>
<ul>
<li>android: anv: fix generated files depedencies (v2)</li>
<li>android: anv: fix libexpat shared dependency</li>
</ul>
<p>Ray Zhang (1):</p>
<ul>
<li>glx: fix shared memory leak in X11</li>
</ul>
<p>Rhys Perry (2):</p>
<ul>
<li>radv: bitcast 16-bit outputs to integers</li>
<li>radv: ensure export arguments are always float</li>
</ul>
<p>Samuel Pitoiset (8):</p>
<ul>
<li>radv: write the alpha channel of MRT0 when alpha coverage is enabled</li>
<li>radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled</li>
<li>radv: fix clearing attachments in secondary command buffers</li>
<li>radv: fix out-of-bounds access when copying descriptors BO list</li>
<li>radv: don't copy buffer descriptors list for samplers</li>
<li>radv: properly align the fence and EOP bug VA on GFX9</li>
<li>radv: fix pointSizeRange limits</li>
<li>radv: always initialize HTILE when the src layout is UNDEFINED</li>
</ul>
<p>Sergii Romantsov (2):</p>
<ul>
<li>dri: meson: do not prefix user provided dri-drivers-path</li>
<li>d3d: meson: do not prefix user provided d3d-drivers-path</li>
</ul>
<p>Tapani Pälli (3):</p>
<ul>
<li>nir: initialize value in copy_prop_vars_block</li>
<li>anv: retain the is_array state in create_plane_tex_instr_implicit</li>
<li>anv: destroy descriptor sets when pool gets destroyed</li>
</ul>
<p>Timothy Arceri (1):</p>
<ul>
<li>glsl: fix shader cache for packed param list</li>
</ul>
<p>Yevhenii Kolesnikov (1):</p>
<ul>
<li>i965: Fix allow_higher_compat_version workaround limited by OpenGL 3.0</li>
</ul>
<p>pal1000 (1):</p>
<ul>
<li>scons: Compatibility with Scons development version string</li>
</ul>
</div>
</body>
</html>

View File

@@ -14,13 +14,13 @@
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.0.1 Release Notes / March 27, 2019</h1>
<h1>Mesa 18.3.6 Release Notes / April 5, 2019</h1>
<p>
Mesa 19.0.1 is a bug fix release which fixes bugs found since the 19.0.0 release.
Mesa 18.3.6 is a bug fix release which fixes bugs found since the 18.3.5 release.
</p>
<p>
Mesa 19.0.1 implements the OpenGL 4.5 API, but the version reported by
Mesa 18.3.6 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
@@ -31,8 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.tar.gz
6884163c0ea9e4c98378ab8fecd72fe7b5f437713a14471beda378df247999d4 mesa-19.0.1.tar.xz
4619d92afadf7072f7956599a2ccd0934fc45b4ddbc2eb865bdcb50ddf963f87 mesa-18.3.6.tar.gz
aaf17638dcf5a90b93b6389e152fdc9ef147768b09598f24d2c5cf482fcfc705 mesa-18.3.6.tar.xz
</pre>
@@ -46,9 +46,9 @@ f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.ta
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100316">Bug 100316</a> - Linking GLSL 1.30 shaders with invariant and deprecated variables triggers an 'mismatching invariant qualifiers' error</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107563">Bug 107563</a> - [RADV] Broken rendering in Unity demos</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108766">Bug 108766</a> - Mesa built with meson has RPATH entries</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109698">Bug 109698</a> - dri.pc contents invalid when built with meson</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109648">Bug 109648</a> - AMD Raven hang during va-api decoding</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109980">Bug 109980</a> - [i915 CI][HSW] spec&#64;arb_fragment_shader_interlock&#64;arb_fragment_shader_interlock-image-load-store - fail</li>
@@ -56,8 +56,11 @@ f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.ta
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110221">Bug 110221</a> - build error with meson</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110259">Bug 110259</a> - radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero (regression, bisected)</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (4):</p>
@@ -74,9 +77,8 @@ f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.ta
<li>ac/nir: Return frag_coord as integer.</li>
</ul>
<p>Danylo Piliaiev (2):</p>
<p>Danylo Piliaiev (1):</p>
<ul>
<li>anv: Treat zero size XFB buffer as disabled</li>
<li>glsl: Cross validate variable's invariance by explicit invariance only</li>
</ul>
@@ -85,44 +87,48 @@ f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.ta
<li>softpipe: fix texture view crashes</li>
</ul>
<p>Dylan Baker (5):</p>
<p>Dylan Baker (1):</p>
<ul>
<li>docs: Add SHA256 sums for 19.0.0</li>
<li>cherry-ignore: Add commit that doesn't apply</li>
<li>bin/install_megadrivers.py: Correctly handle DESTDIR=''</li>
<li>bin/install_megadrivers.py: Fix regression for set DESTDIR</li>
<li>bump version for 19.0.1</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>docs: add sha256 checksums for 18.3.5</li>
<li>Update version to 18.3.6</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>v3d: Fix leak of the renderonly struct on screen destruction.</li>
<li>dri3: Return the current swap interval from glXGetSwapIntervalMESA().</li>
</ul>
<p>Jason Ekstrand (6):</p>
<p>Eric Engestrom (1):</p>
<ul>
<li>meson: strip rpath from megadrivers</li>
</ul>
<p>Jason Ekstrand (2):</p>
<ul>
<li>glsl/lower_vector_derefs: Don't use a temporary for TCS outputs</li>
<li>glsl/list: Add a list variant of insert_after</li>
<li>anv/pass: Flag the need for a RT flush for resolve attachments</li>
<li>nir/builder: Add a vector extract helper</li>
<li>nir: Add a new pass to lower array dereferences on vectors</li>
<li>intel/nir: Lower array-deref-of-vector UBO and SSBO loads</li>
<li>Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"</li>
</ul>
<p>Józef Kucia (2):</p>
<ul>
<li>radv: Fix driverUUID</li>
<li>mesa: Fix GL_NUM_DEVICE_UUIDS_EXT</li>
<li>radv: Fix driverUUID</li>
</ul>
<p>Kenneth Graunke (1):</p>
<p>Leo Liu (2):</p>
<ul>
<li>intel/fs: Fix opt_peephole_csel to not throw away saturates.</li>
<li>radeon/vcn: add H.264 constrained baseline support</li>
<li>radeon/vcn/vp9: search the render target from the whole list</li>
</ul>
<p>Kevin Strasser (1):</p>
<p>Marek Olšák (1):</p>
<ul>
<li>egl/dri: Avoid out of bounds array access</li>
<li>radeonsi: fix assertion failure by using the correct type</li>
</ul>
<p>Mark Janes (1):</p>
@@ -135,25 +141,29 @@ f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.ta
<li>i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9</li>
</ul>
<p>Samuel Pitoiset (3):</p>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv: set the maximum number of IBs per submit to 192</li>
<li>radv: always initialize HTILE when the src layout is UNDEFINED</li>
<li>radv: fix binding transform feedback buffers</li>
<li>radv: do not always initialize HTILE in compressed state</li>
</ul>
<p>Sergii Romantsov (1):</p>
<p>Tapani Pälli (1):</p>
<ul>
<li>d3d: meson: do not prefix user provided d3d-drivers-path</li>
</ul>
<p>Tapani Pälli (2):</p>
<ul>
<li>isl: fix automake build when sse41 is not supported</li>
<li>anv/radv: release memory allocated by glsl types during spirv_to_nir</li>
</ul>
<p>Timothy Arceri (1):</p>
<ul>
<li>st/glsl_to_nir: fix incorrect arrary access</li>
</ul>
<p>Tobias Klausmann (1):</p>
<ul>
<li>vulkan/util: meson build - add wayland client include</li>
</ul>
</div>
</body>
</html>

File diff suppressed because it is too large Load Diff

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@@ -1,121 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.0.2 Release Notes / April 10, 2019</h1>
<p>
Mesa 19.0.2 is a bug fix release which fixes bugs found since the 19.0.1 release.
</p>
<p>
Mesa 19.0.2 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108766">Bug 108766</a> - Mesa built with meson has RPATH entries</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109648">Bug 109648</a> - AMD Raven hang during va-api decoding</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110257">Bug 110257</a> - Major artifacts in mpeg2 vaapi hw decoding</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110259">Bug 110259</a> - radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero (regression, bisected)</li>
</ul>
<h2>Changes</h2>
<p>Boyuan Zhang (1):</p>
<ul>
<li>st/va: reverse qt matrix back to its original order</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>nir: Take if_uses into account when repairing SSA</li>
</ul>
<p>Dylan Baker (2):</p>
<ul>
<li>docs: Add SHA256 sums for mesa 19.0.1</li>
<li>VERSION: bump version for 19.0.2</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>dri3: Return the current swap interval from glXGetSwapIntervalMESA().</li>
<li>v3d: Bump the maximum texture size to 4k for V3D 4.x.</li>
<li>v3d: Don't try to use the TFU blit path if a scissor is enabled.</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>meson: strip rpath from megadrivers</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nir/print: fix printing the image_array intrinsic index</li>
</ul>
<p>Leo Liu (2):</p>
<ul>
<li>radeon/vcn: add H.264 constrained baseline support</li>
<li>radeon/vcn/vp9: search the render target from the whole list</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>intel: add dependency on genxml generated files</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>radeonsi: fix assertion failure by using the correct type</li>
</ul>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv: skip updating depth/color metadata for conditional rendering</li>
<li>radv: do not always initialize HTILE in compressed state</li>
</ul>
</div>
</body>
</html>

View File

@@ -1,95 +0,0 @@
Name
MESA_query_driver
Name Strings
EGL_MESA_query_driver
Contact
Rob Clark <robdclark 'at' gmail.com>
Nicolai Hähnle <Nicolai.Haehnle 'at' amd.com>
Contibutors
Veluri Mithun <velurimithun38 'at' gmail.com>
Status
Complete
Version
Version 3, 2019-01-24
Number
EGL Extension 131
Dependencies
EGL 1.0 is required.
Overview
When an application has to query the name of a driver and for
obtaining driver's option list (UTF-8 encoded XML) of a driver
the below functions are useful.
XML file formally describes all available options and also
includes verbal descriptions in multiple languages. Its main purpose
is to be automatically processed by configuration GUIs.
The XML shall respect the following DTD:
<!ELEMENT driinfo (section*)>
<!ELEMENT section (description+, option+)>
<!ELEMENT description (enum*)>
<!ATTLIST description lang CDATA #REQUIRED
text CDATA #REQUIRED>
<!ELEMENT option (description+)>
<!ATTLIST option name CDATA #REQUIRED
type (bool|enum|int|float) #REQUIRED
default CDATA #REQUIRED
valid CDATA #IMPLIED>
<!ELEMENT enum EMPTY>
<!ATTLIST enum value CDATA #REQUIRED
text CDATA #REQUIRED>
New Procedures and Functions
char* eglGetDisplayDriverConfig(EGLDisplay dpy);
const char* eglGetDisplayDriverName(EGLDisplay dpy);
Description
By passing EGLDisplay as parameter to `eglGetDisplayDriverName` one can retrieve
driverName. Similarly passing EGLDisplay to `eglGetDisplayDriverConfig` we can retrieve
driverConfig options of the driver in XML format.
The string returned by `eglGetDisplayDriverConfig` is heap-allocated and caller
is responsible for freeing it.
EGL_BAD_DISPLAY is generated if `disp` is not an EGL display connection.
EGL_NOT_INITIALIZED is generated if `disp` has not been initialized.
If the implementation does not have enough resources to allocate the XML then an
EGL_BAD_ALLOC error is generated.
New Tokens
No new tokens
Issues
None
Revision History
Version 1, 2018-11-05 - First draft (Veluri Mithun)
Version 2, 2019-01-23 - Final version (Veluri Mithun)
Version 3, 2019-01-24 - Mark as complete, add Khronos extension
number, fix parameter name in prototypes,
write revision history (Eric Engestrom)

View File

@@ -20,11 +20,11 @@ Status
Version
Version 9, 09 November 2018
Version 8, 14-February-2014
Number
OpenGL Extension #446
TBD.
Dependencies
@@ -32,6 +32,9 @@ Dependencies
GLX_ARB_create_context and GLX_ARB_create_context_profile are required.
This extension interacts with GLX_EXT_create_context_es2_profile and
GLX_EXT_create_context_es_profile.
Overview
In many situations, applications want to detect characteristics of a
@@ -92,13 +95,18 @@ New Tokens
GLX_RENDERER_VENDOR_ID_MESA
GLX_RENDERER_DEVICE_ID_MESA
Accepted as an attribute name in <*attrib_list> in
glXCreateContextAttribsARB:
GLX_RENDERER_ID_MESA 0x818E
Additions to the OpenGL / WGL Specifications
None. This specification is written for GLX.
Additions to the GLX 1.4 Specification
[Add to Section 3.3.2 "GLX Versioning" of the GLX Specification]
[Add the following to Section X.Y.Z of the GLX Specification]
To obtain information about the available renderers for a particular
display and screen,
@@ -198,6 +206,29 @@ Additions to the GLX 1.4 Specification
format as the string that would be returned by glGetString of GL_RENDERER.
It may, however, have a different value.
[Add to section section 3.3.7 "Rendering Contexts"]
The attribute name GLX_RENDERER_ID_MESA specified the index of the render
against which the context should be created. The default value of
GLX_RENDERER_ID_MESA is 0.
[Add to list of errors for glXCreateContextAttribsARB in section section
3.3.7 "Rendering Contexts"]
* If the value of GLX_RENDERER_ID_MESA specifies a non-existent
renderer, BadMatch is generated.
Dependencies on GLX_EXT_create_context_es_profile and
GLX_EXT_create_context_es2_profile
If neither extension is supported, remove all mention of
GLX_RENDERER_OPENGL_ES2_PROFILE_VERSION_MESA from the spec.
If GLX_EXT_create_context_es_profile is not supported, remove all mention of
GLX_RENDERER_OPENGL_ES_PROFILE_VERSION_MESA from the spec.
Issues
1) How should the difference between on-card and GART memory be exposed?
@@ -377,9 +408,3 @@ Revision History
read GLX_RENDERER_ID_MESA. The VENDOR/DEVICE_ID
example given in issue #17 should be 0x5143 and
0xFFFFFFFF respectively.
Version 9, 2018/11/09 - Remove GLX_RENDERER_ID_MESA, which has never been
implemented. Remove the unnecessary interactions
with the GLX GLES profile extensions. Note the
official GL extension number. Specify the section
of the GLX spec to modify.

View File

@@ -21,7 +21,7 @@
<li><a href="#guidelines">Basic guidelines</a>
<li><a href="#formatting">Patch formatting</a>
<li><a href="#testing">Testing Patches</a>
<li><a href="#submit">Submitting Patches</a>
<li><a href="#mailing">Mailing Patches</a>
<li><a href="#reviewing">Reviewing Patches</a>
<li><a href="#nominations">Nominating a commit for a stable branch</a>
<li><a href="#criteria">Criteria for accepting patches to the stable branch</a>
@@ -42,10 +42,8 @@ components.
<code>git bisect</code>.)
<li>Patches should be properly <a href="#formatting">formatted</a>.
<li>Patches should be sufficiently <a href="#testing">tested</a> before submitting.
<li>Patches should be <a href="#submit">submitted</a>
to <a href="#mailing">mesa-dev</a> or with
a <a href="#merge-request">merge request</a>
for <a href="#reviewing">review</a>.
<li>Patches should be submitted to <a href="#mailing">mesa-dev</a>
for <a href="#reviewing">review</a> using <code>git send-email</code>.
</ul>
@@ -158,29 +156,18 @@ As mentioned at the begining, patches should be bisectable.
A good way to test this is to make use of the `git rebase` command,
to run your tests on each commit. Assuming your branch is based off
<code>origin/master</code>, you can run:
</p>
<pre>
$ git rebase --interactive --exec "make check" origin/master
</pre>
<p>
replacing <code>"make check"</code> with whatever other test you want to
run.
</p>
<h2 id="submit">Submitting Patches</h2>
<h2 id="mailing">Mailing Patches</h2>
<p>
Patches may be submitted to the Mesa project by
<a href="#mailing">email</a> or with a
GitLab <a href="#merge-request">merge request</a>. To prevent
duplicate code review, only use one method to submit your changes.
</p>
<h3 id="mailing">Mailing Patches</h3>
<p>
Patches may be sent to the mesa-dev mailing list for review:
Patches should be sent to the mesa-dev mailing list for review:
<a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev">
mesa-dev@lists.freedesktop.org</a>.
When submitting a patch make sure to use
@@ -214,65 +201,8 @@ disabled before sending your patches. (Note that you may need to contact
your email administrator for this.)
</p>
<h3 id="merge-request">GitLab Merge Requests</h3>
<p>
<a href="https://gitlab.freedesktop.org/mesa/mesa">GitLab</a> Merge
Requests (MR) can also be used to submit patches for Mesa.
</p>
<p>
If the MR may have interest for most of the Mesa community, you can
send an email to the mesa-dev email list including a link to the MR.
Don't send the patch to mesa-dev, just the MR link.
</p>
<p>
Add labels to your MR to help reviewers find it. For example:
<ul>
<li>Mesa changes affecting all drivers: mesa
<li>Hardware vendor specific code: amd, intel, nvidia, ...
<li>Driver specific code: anvil, freedreno, i965, iris, radeonsi,
radv, vc4, ...
<li>Other tag examples: gallium, util
</ul>
</p>
<p>
If you revise your patches based on code review and push an update
to your branch, you should maintain a <strong>clean</strong> history
in your patches. There should not be "fixup" patches in the history.
The series should be buildable and functional after every commit
whenever you push the branch.
</p>
<p>
It is your responsibility to keep the MR alive and making progress,
as there are no guarantees that a Mesa dev will independently take
interest in it.
</p>
<p>
Some other notes:
<ul>
<li>Make changes and update your branch based on feedback
<li>Old, stale MR may be closed, but you can reopen it if you
still want to pursue the changes
<li>You should periodically check to see if your MR needs to be
rebased
<li>Make sure your MR is closed if your patches get pushed outside
of GitLab
<li>Please send MRs from a personal fork rather than from the main
Mesa repository, as it clutters it unnecessarily.
</ul>
</p>
<h2 id="reviewing">Reviewing Patches</h2>
<p>
To participate in code review, you should monitor the
<a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev">
mesa-dev</a> email list and the GitLab
Mesa <a href="https://gitlab.freedesktop.org/mesa/mesa/merge_requests">Merge
Requests</a> page.
</p>
<p>
When you've reviewed a patch on the mailing list, please be unambiguous
about your review. That is, state either
@@ -299,29 +229,6 @@ which tells the patch author that the patch can be committed, as long
as the issues are resolved first.
</p>
<p>
These Reviewed-by, Acked-by, and Tested-by tags should also be amended
into commits in a MR before it is merged.
</p>
<p>
When providing a Reviewed-by, Acked-by, or Tested-by tag in a gitlab MR,
enclose the tag in backticks:
</p>
<pre>
`Reviewed-by: Joe Hacker &lt;jhacker@example.com&gt;`</pre>
<p>
This is the markdown format for literal, and will prevent gitlab from hiding
the &lt; and &gt; symbols.
</p>
<p>
Review by non-experts is encouraged. Understanding how someone else
goes about solving a problem is a great way to learn your way around
the project. The submitter is expected to evaluate whether they have
an appropriate amount of review feedback from people who also
understand the code before merging their patches.
</p>
<h2 id="nominations">Nominating a commit for a stable branch</h2>

View File

@@ -28,17 +28,17 @@ extern "C" {
** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
*/
/*
** This header is generated from the Khronos EGL XML API Registry.
** The current version of the Registry, generator scripts
** This header is generated from the Khronos OpenGL / OpenGL ES XML
** API Registry. The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
** Khronos $Git commit SHA1: a732b061e7 $ on $Git commit date: 2017-06-17 23:27:53 +0100 $
*/
#include <EGL/eglplatform.h>
/* Generated on date 20190124 */
/* Generated on date 20170627 */
/* Generated C header for:
* API: egl

View File

@@ -28,17 +28,17 @@ extern "C" {
** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
*/
/*
** This header is generated from the Khronos EGL XML API Registry.
** The current version of the Registry, generator scripts
** This header is generated from the Khronos OpenGL / OpenGL ES XML
** API Registry. The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
** Khronos $Git commit SHA1: bae3518c48 $ on $Git commit date: 2018-05-17 10:56:57 -0700 $
*/
#include <EGL/eglplatform.h>
#define EGL_EGLEXT_VERSION 20190124
#define EGL_EGLEXT_VERSION 20180517
/* Generated C header for:
* API: egl
@@ -681,7 +681,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
#ifndef EGL_EXT_device_drm
#define EGL_EXT_device_drm 1
#define EGL_DRM_DEVICE_FILE_EXT 0x3233
#define EGL_DRM_MASTER_FD_EXT 0x333C
#endif /* EGL_EXT_device_drm */
#ifndef EGL_EXT_device_enumeration
@@ -717,11 +716,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
#define EGL_GL_COLORSPACE_DISPLAY_P3_LINEAR_EXT 0x3362
#endif /* EGL_EXT_gl_colorspace_display_p3_linear */
#ifndef EGL_EXT_gl_colorspace_display_p3_passthrough
#define EGL_EXT_gl_colorspace_display_p3_passthrough 1
#define EGL_GL_COLORSPACE_DISPLAY_P3_PASSTHROUGH_EXT 0x3490
#endif /* EGL_EXT_gl_colorspace_display_p3_passthrough */
#ifndef EGL_EXT_gl_colorspace_scrgb
#define EGL_EXT_gl_colorspace_scrgb 1
#define EGL_GL_COLORSPACE_SCRGB_EXT 0x3351
@@ -1031,16 +1025,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglExportDMABUFImageMESA (EGLDisplay dpy, EGLImage
#define EGL_PLATFORM_SURFACELESS_MESA 0x31DD
#endif /* EGL_MESA_platform_surfaceless */
#ifndef EGL_MESA_query_driver
#define EGL_MESA_query_driver 1
typedef char *(EGLAPIENTRYP PFNEGLGETDISPLAYDRIVERCONFIGPROC) (EGLDisplay dpy);
typedef const char *(EGLAPIENTRYP PFNEGLGETDISPLAYDRIVERNAMEPROC) (EGLDisplay dpy);
#ifdef EGL_EGLEXT_PROTOTYPES
EGLAPI char *EGLAPIENTRY eglGetDisplayDriverConfig (EGLDisplay dpy);
EGLAPI const char *EGLAPIENTRY eglGetDisplayDriverName (EGLDisplay dpy);
#endif
#endif /* EGL_MESA_query_driver */
#ifndef EGL_NOK_swap_region
#define EGL_NOK_swap_region 1
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSWAPBUFFERSREGIONNOKPROC) (EGLDisplay dpy, EGLSurface surface, EGLint numRects, const EGLint *rects);

View File

@@ -1344,7 +1344,6 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FOURCC_NV16 0x3631564e
#define __DRI_IMAGE_FOURCC_YUYV 0x56595559
#define __DRI_IMAGE_FOURCC_UYVY 0x59565955
#define __DRI_IMAGE_FOURCC_AYUV 0x56555941
#define __DRI_IMAGE_FOURCC_YVU410 0x39555659
#define __DRI_IMAGE_FOURCC_YVU411 0x31315659
@@ -1371,7 +1370,6 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_COMPONENTS_Y_UV 0x3004
#define __DRI_IMAGE_COMPONENTS_Y_XUXV 0x3005
#define __DRI_IMAGE_COMPONENTS_Y_UXVX 0x3008
#define __DRI_IMAGE_COMPONENTS_AYUV 0x3009
#define __DRI_IMAGE_COMPONENTS_R 0x3006
#define __DRI_IMAGE_COMPONENTS_RG 0x3007

View File

@@ -298,19 +298,6 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
/*
* Qualcomm Compressed Format
*
* Refers to a compressed variant of the base format that is compressed.
* Implementation may be platform and base-format specific.
*
* Each macrotile consists of m x n (mostly 4 x 4) tiles.
* Pixel data pitch/stride is aligned with macrotile width.
* Pixel data height is aligned with macrotile height.
* Entire pixel data buffer is aligned with 4k(bytes).
*/
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
/* Vivante framebuffer modifiers */
/*

View File

@@ -36,7 +36,6 @@ extern "C" {
#define DRM_V3D_MMAP_BO 0x03
#define DRM_V3D_GET_PARAM 0x04
#define DRM_V3D_GET_BO_OFFSET 0x05
#define DRM_V3D_SUBMIT_TFU 0x06
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -44,7 +43,6 @@ extern "C" {
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -60,11 +58,6 @@ struct drm_v3d_submit_cl {
* coordinate shader to determine where primitives land on the screen,
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*
* This BCL will block on any previous BCL submitted on the
* same FD, but not on any RCL or BCLs submitted by other
* clients -- that is left up to the submitter to control
* using in_sync_bcl if necessary.
*/
__u32 bcl_start;
@@ -76,11 +69,6 @@ struct drm_v3d_submit_cl {
* This is the second set of commands executed, which will either
* execute the tiles that have been set up by the BCL, or a fixed set
* of tiles (in the case of RCL-only blits).
*
* This RCL will block on this submit's BCL, and any previous
* RCL submitted on the same FD, but not on any RCL or BCLs
* submitted by other clients -- that is left up to the
* submitter to control using in_sync_rcl if necessary.
*/
__u32 rcl_start;
@@ -181,7 +169,6 @@ enum drm_v3d_param {
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
DRM_V3D_PARAM_SUPPORTS_TFU,
};
struct drm_v3d_get_param {
@@ -200,28 +187,6 @@ struct drm_v3d_get_bo_offset {
__u32 offset;
};
struct drm_v3d_submit_tfu {
__u32 icfg;
__u32 iia;
__u32 iis;
__u32 ica;
__u32 iua;
__u32 ioa;
__u32 ios;
__u32 coef[4];
/* First handle is the output BO, following are other inputs.
* 0 for unused.
*/
__u32 bo_handles[4];
/* sync object to block on before running the TFU job. Each TFU
* job will execute in the order submitted to its FD. Synchronization
* against rendering jobs requires using sync objects.
*/
__u32 in_sync;
/* Sync object to signal when the TFU job is done. */
__u32 out_sync;
};
#if defined(__cplusplus)
}
#endif

View File

@@ -2,7 +2,7 @@
#define VULKAN_H_ 1
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.
@@ -39,6 +39,12 @@
#endif
#ifdef VK_USE_PLATFORM_MIR_KHR
#include <mir_toolkit/client_types.h>
#include "vulkan_mir.h"
#endif
#ifdef VK_USE_PLATFORM_VI_NN
#include "vulkan_vi.h"
#endif

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

File diff suppressed because it is too large Load Diff

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -0,0 +1,65 @@
#ifndef VULKAN_MIR_H_
#define VULKAN_MIR_H_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.
** You may obtain a copy of the License at
**
** http://www.apache.org/licenses/LICENSE-2.0
**
** Unless required by applicable law or agreed to in writing, software
** distributed under the License is distributed on an "AS IS" BASIS,
** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
** See the License for the specific language governing permissions and
** limitations under the License.
*/
/*
** This header is generated from the Khronos Vulkan XML API Registry.
**
*/
#define VK_KHR_mir_surface 1
#define VK_KHR_MIR_SURFACE_SPEC_VERSION 4
#define VK_KHR_MIR_SURFACE_EXTENSION_NAME "VK_KHR_mir_surface"
typedef VkFlags VkMirSurfaceCreateFlagsKHR;
typedef struct VkMirSurfaceCreateInfoKHR {
VkStructureType sType;
const void* pNext;
VkMirSurfaceCreateFlagsKHR flags;
MirConnection* connection;
MirSurface* mirSurface;
} VkMirSurfaceCreateInfoKHR;
typedef VkResult (VKAPI_PTR *PFN_vkCreateMirSurfaceKHR)(VkInstance instance, const VkMirSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface);
typedef VkBool32 (VKAPI_PTR *PFN_vkGetPhysicalDeviceMirPresentationSupportKHR)(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, MirConnection* connection);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkCreateMirSurfaceKHR(
VkInstance instance,
const VkMirSurfaceCreateInfoKHR* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkSurfaceKHR* pSurface);
VKAPI_ATTR VkBool32 VKAPI_CALL vkGetPhysicalDeviceMirPresentationSupportKHR(
VkPhysicalDevice physicalDevice,
uint32_t queueFamilyIndex,
MirConnection* connection);
#endif
#ifdef __cplusplus
}
#endif
#endif

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2015-2019 The Khronos Group Inc.
** Copyright (c) 2015-2018 The Khronos Group Inc.
**
** Licensed under the Apache License, Version 2.0 (the "License");
** you may not use this file except in compliance with the License.

View File

@@ -34,6 +34,8 @@ cpp = meson.get_compiler('cpp')
null_dep = dependency('', required : false)
system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
# Arguments for the preprocessor, put these in a separate array from the C and
# C++ (cpp in meson terminology) arguments since they need to be added to the
# default arguments for both C and C++.
@@ -41,7 +43,8 @@ pre_args = [
'-D__STDC_CONSTANT_MACROS',
'-D__STDC_FORMAT_MACROS',
'-D__STDC_LIMIT_MACROS',
'-DPACKAGE_VERSION="@0@"'.format(meson.project_version()),
'-DVERSION="@0@"'.format(meson.project_version()),
'-DPACKAGE_VERSION=VERSION',
'-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa"',
]
@@ -56,7 +59,7 @@ with_osmesa = get_option('osmesa')
with_swr_arches = get_option('swr-arches')
with_tools = get_option('tools')
if with_tools.contains('all')
with_tools = ['etnaviv', 'freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
endif
dri_drivers_path = get_option('dri-drivers-path')
@@ -131,7 +134,7 @@ if _drivers.contains('auto')
]
elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
_drivers = [
'kmsro', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau',
'pl111', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'imx', 'nouveau',
'tegra', 'virgl', 'swrast',
]
else
@@ -145,7 +148,7 @@ if _drivers.contains('auto')
host_machine.system()))
endif
endif
with_gallium_kmsro = _drivers.contains('kmsro')
with_gallium_pl111 = _drivers.contains('pl111')
with_gallium_radeonsi = _drivers.contains('radeonsi')
with_gallium_r300 = _drivers.contains('r300')
with_gallium_r600 = _drivers.contains('r600')
@@ -155,6 +158,7 @@ with_gallium_softpipe = _drivers.contains('swrast')
with_gallium_vc4 = _drivers.contains('vc4')
with_gallium_v3d = _drivers.contains('v3d')
with_gallium_etnaviv = _drivers.contains('etnaviv')
with_gallium_imx = _drivers.contains('imx')
with_gallium_tegra = _drivers.contains('tegra')
with_gallium_i915 = _drivers.contains('i915')
with_gallium_svga = _drivers.contains('svga')
@@ -209,8 +213,11 @@ endif
if with_dri_i915 and with_gallium_i915
error('Only one i915 provider can be built')
endif
if with_gallium_kmsro and not (with_gallium_vc4 or with_gallium_etnaviv or with_gallium_freedreno)
error('kmsro driver requires one or more renderonly drivers (vc4, etnaviv, freedreno)')
if with_gallium_imx and not with_gallium_etnaviv
error('IMX driver requires etnaviv driver')
endif
if with_gallium_pl111 and not with_gallium_vc4
error('pl111 driver requires vc4 driver')
endif
if with_gallium_tegra and not with_gallium_nouveau
error('tegra driver requires nouveau driver')
@@ -929,7 +936,7 @@ endif
# case of cross compiling where we can use asm, and that's x86_64 -> x86 when
# host OS == build OS, since in that case the build machine can run the host's
# binaries.
if with_asm and meson.is_cross_build()
if meson.is_cross_build()
if build_machine.system() != host_machine.system()
# TODO: It may be possible to do this with an exe_wrapper (like wine).
message('Cross compiling from one OS to another, disabling assembly.')
@@ -1113,7 +1120,7 @@ dep_libdrm_nouveau = null_dep
dep_libdrm_etnaviv = null_dep
dep_libdrm_intel = null_dep
_drm_amdgpu_ver = '2.4.97'
_drm_amdgpu_ver = '2.4.95'
_drm_radeon_ver = '2.4.71'
_drm_nouveau_ver = '2.4.66'
_drm_etnaviv_ver = '2.4.89'
@@ -1188,7 +1195,7 @@ if with_gallium_opencl
endif
if with_amd_vk or with_gallium_radeonsi
_llvm_version = '>= 7.0.0'
_llvm_version = '>= 6.0.0'
elif with_gallium_swr
_llvm_version = '>= 6.0.0'
elif with_gallium_opencl or with_gallium_r600
@@ -1365,7 +1372,7 @@ if with_platform_x11
dep_xfixes = dependency('xfixes')
dep_xcb_glx = dependency('xcb-glx', version : '>= 1.8.1')
endif
if (with_any_vk or with_glx == 'dri' or with_egl or
if (with_any_vk or with_glx == 'dri' or
(with_gallium_vdpau or with_gallium_xvmc or with_gallium_va or
with_gallium_omx != 'disabled'))
dep_xcb = dependency('xcb')

View File

@@ -58,8 +58,8 @@ option(
type : 'array',
value : ['auto'],
choices : [
'', 'auto', 'kmsro', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
'swrast', 'v3d', 'vc4', 'etnaviv', 'tegra', 'i915', 'svga', 'virgl',
'', 'auto', 'pl111', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
'swrast', 'v3d', 'vc4', 'etnaviv', 'imx', 'tegra', 'i915', 'svga', 'virgl',
'swr',
],
description : 'List of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
@@ -301,7 +301,7 @@ option(
'tools',
type : 'array',
value : [],
choices : ['etnaviv', 'freedreno', 'glsl', 'intel', 'intel-ui', 'nir', 'nouveau', 'xvmc', 'all'],
choices : ['freedreno', 'glsl', 'intel', 'intel-ui', 'nir', 'nouveau', 'xvmc', 'all'],
description : 'List of tools to build. (Note: `intel-ui` selects `intel`)',
)
option(

View File

@@ -81,10 +81,6 @@ if HAVE_BROADCOM_DRIVERS
SUBDIRS += broadcom
endif
if HAVE_FREEDRENO_DRIVERS
SUBDIRS += freedreno
endif
if NEED_OPENGL_COMMON
SUBDIRS += mesa
endif

View File

@@ -33,11 +33,12 @@ LOCAL_SRC_FILES := $(ADDRLIB_FILES)
LOCAL_C_INCLUDES := \
$(MESA_TOP)/src \
$(MESA_TOP)/src/amd/common \
$(MESA_TOP)/src/amd/addrlib/inc \
$(MESA_TOP)/src/amd/addrlib/src \
$(MESA_TOP)/src/amd/addrlib/src/core \
$(MESA_TOP)/src/amd/addrlib/src/chip/gfx9 \
$(MESA_TOP)/src/amd/addrlib/src/chip/r800
$(MESA_TOP)/src/amd/addrlib \
$(MESA_TOP)/src/amd/addrlib/core \
$(MESA_TOP)/src/amd/addrlib/inc/chip/gfx9 \
$(MESA_TOP)/src/amd/addrlib/inc/chip/r800 \
$(MESA_TOP)/src/amd/addrlib/gfx9/chip \
$(MESA_TOP)/src/amd/addrlib/r800/chip
LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \

View File

@@ -26,11 +26,12 @@ addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
-I$(top_srcdir)/src/ \
-I$(top_srcdir)/include \
-I$(srcdir)/common \
-I$(srcdir)/addrlib/inc \
-I$(srcdir)/addrlib/src \
-I$(srcdir)/addrlib/src/core \
-I$(srcdir)/addrlib/src/chip/gfx9 \
-I$(srcdir)/addrlib/src/chip/r800
-I$(srcdir)/addrlib \
-I$(srcdir)/addrlib/core \
-I$(srcdir)/addrlib/inc/chip/gfx9 \
-I$(srcdir)/addrlib/inc/chip/r800 \
-I$(srcdir)/addrlib/gfx9/chip \
-I$(srcdir)/addrlib/r800/chip
addrlib_libamdgpu_addrlib_la_CXXFLAGS = \
$(VISIBILITY_CXXFLAGS) $(CXX11_CXXFLAGS)

View File

@@ -5,33 +5,35 @@ COMMON_HEADER_FILES = \
common/amd_kernel_code_t.h
ADDRLIB_FILES = \
addrlib/inc/addrinterface.h \
addrlib/inc/addrtypes.h \
addrlib/src/addrinterface.cpp \
addrlib/src/amdgpu_asic_addr.h \
addrlib/src/core/addrcommon.h \
addrlib/src/core/addrelemlib.cpp \
addrlib/src/core/addrelemlib.h \
addrlib/src/core/addrlib.cpp \
addrlib/src/core/addrlib.h \
addrlib/src/core/addrlib1.cpp \
addrlib/src/core/addrlib1.h \
addrlib/src/core/addrlib2.cpp \
addrlib/src/core/addrlib2.h \
addrlib/src/core/addrobject.cpp \
addrlib/src/core/addrobject.h \
addrlib/src/core/coord.cpp \
addrlib/src/core/coord.h \
addrlib/src/gfx9/gfx9addrlib.cpp \
addrlib/src/gfx9/gfx9addrlib.h \
addrlib/src/chip/gfx9/gfx9_gb_reg.h \
addrlib/src/chip/r800/si_gb_reg.h \
addrlib/src/r800/ciaddrlib.cpp \
addrlib/src/r800/ciaddrlib.h \
addrlib/src/r800/egbaddrlib.cpp \
addrlib/src/r800/egbaddrlib.h \
addrlib/src/r800/siaddrlib.cpp \
addrlib/src/r800/siaddrlib.h
addrlib/addrinterface.cpp \
addrlib/addrinterface.h \
addrlib/addrtypes.h \
addrlib/amdgpu_asic_addr.h \
addrlib/core/addrcommon.h \
addrlib/core/addrelemlib.cpp \
addrlib/core/addrelemlib.h \
addrlib/core/addrlib.cpp \
addrlib/core/addrlib.h \
addrlib/core/addrlib1.cpp \
addrlib/core/addrlib1.h \
addrlib/core/addrlib2.cpp \
addrlib/core/addrlib2.h \
addrlib/core/addrobject.cpp \
addrlib/core/addrobject.h \
addrlib/gfx9/chip/gfx9_enum.h \
addrlib/gfx9/coord.cpp \
addrlib/gfx9/coord.h \
addrlib/gfx9/gfx9addrlib.cpp \
addrlib/gfx9/gfx9addrlib.h \
addrlib/inc/chip/gfx9/gfx9_gb_reg.h \
addrlib/inc/chip/r800/si_gb_reg.h \
addrlib/r800/chip/si_ci_vi_merged_enum.h \
addrlib/r800/ciaddrlib.cpp \
addrlib/r800/ciaddrlib.h \
addrlib/r800/egbaddrlib.cpp \
addrlib/r800/egbaddrlib.h \
addrlib/r800/siaddrlib.cpp \
addrlib/r800/siaddrlib.h
AMD_COMPILER_FILES = \
common/ac_binary.c \

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -61,13 +61,13 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
{
returnCode = Lib::Create(pAddrCreateIn, pAddrCreateOut);
}
return returnCode;
}
/**
****************************************************************************************************
* AddrDestroy
@@ -97,6 +97,8 @@ ADDR_E_RETURNCODE ADDR_API AddrDestroy(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -133,6 +135,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
return returnCode;
}
/**
****************************************************************************************************
* AddrComputeSurfaceAddrFromCoord
@@ -197,6 +201,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// HTile functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -298,6 +304,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// C-mask functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -400,6 +408,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// F-mask functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -500,6 +510,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// DCC key functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -534,6 +546,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
return returnCode;
}
///////////////////////////////////////////////////////////////////////////////
// Below functions are element related or helper functions
///////////////////////////////////////////////////////////////////////////////
@@ -836,34 +850,6 @@ BOOL_32 ADDR_API ElemGetExportNorm(
return enabled;
}
/**
****************************************************************************************************
* ElemSize
*
* @brief
* Get bits-per-element for specified format
*
* @return
* Bits-per-element of specified format
*
****************************************************************************************************
*/
UINT_32 ADDR_API ElemSize(
ADDR_HANDLE hLib,
AddrFormat format)
{
UINT_32 bpe = 0;
Addr::Lib* pLib = Lib::GetLib(hLib);
if (pLib != NULL)
{
bpe = pLib->GetBpe(format);
}
return bpe;
}
/**
****************************************************************************************************
* AddrConvertTileInfoToHW
@@ -1119,6 +1105,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface functions for Addr2
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1155,6 +1142,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeSurfaceAddrFromCoord
@@ -1187,6 +1175,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeSurfaceCoordFromAddr
@@ -1219,6 +1208,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// HTile functions for Addr2
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1255,6 +1246,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeHtileAddrFromCoord
@@ -1287,6 +1279,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeHtileCoordFromAddr
@@ -1320,6 +1313,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// C-mask functions for Addr2
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1357,6 +1352,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeCmaskAddrFromCoord
@@ -1389,6 +1385,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeCmaskCoordFromAddr
@@ -1422,6 +1419,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// F-mask functions for Addr2
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1458,6 +1457,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeFmaskAddrFromCoord
@@ -1490,6 +1490,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeFmaskCoordFromAddr
@@ -1522,6 +1523,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// DCC key functions for Addr2
////////////////////////////////////////////////////////////////////////////////////////////////////

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -177,6 +177,7 @@ typedef struct _ADDR_EQUATION
///< stacked vertically prior to swizzling
} ADDR_EQUATION;
/**
****************************************************************************************************
* @brief Alloc system memory flags.
@@ -408,6 +409,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
const ADDR_CREATE_INPUT* pAddrCreateIn,
ADDR_CREATE_OUTPUT* pAddrCreateOut);
/**
****************************************************************************************************
* AddrDestroy
@@ -422,6 +425,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCreate(
ADDR_E_RETURNCODE ADDR_API AddrDestroy(
ADDR_HANDLE hLib);
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -653,6 +658,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
@@ -741,6 +748,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
@@ -922,6 +931,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
@@ -984,6 +995,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
@@ -1044,6 +1057,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// C-mask functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1131,6 +1146,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
@@ -1191,6 +1208,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
@@ -1249,6 +1268,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// F-mask functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1329,6 +1350,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
@@ -1405,6 +1428,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
@@ -1478,6 +1503,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// Element/utility functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -1566,6 +1593,7 @@ ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
@@ -1623,6 +1651,8 @@ ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_COMPUTE_SLICESWIZZLE_INPUT
@@ -1649,6 +1679,8 @@ typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
///< README: When tileIndex is not -1, this must be valid
} ADDR_COMPUTE_SLICESWIZZLE_INPUT;
/**
****************************************************************************************************
* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
@@ -1679,6 +1711,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
/**
****************************************************************************************************
* AddrSwizzleGenOption
@@ -1769,6 +1802,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
/**
****************************************************************************************************
* ELEM_GETEXPORTNORM_INPUT
@@ -1809,6 +1844,8 @@ BOOL_32 ADDR_API ElemGetExportNorm(
ADDR_HANDLE hLib,
const ELEM_GETEXPORTNORM_INPUT* pIn);
/**
****************************************************************************************************
* ELEM_FLT32TODEPTHPIXEL_INPUT
@@ -1864,6 +1901,8 @@ ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
/**
****************************************************************************************************
* ELEM_FLT32TOCOLORPIXEL_INPUT
@@ -1917,21 +1956,6 @@ ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);
/**
****************************************************************************************************
* ElemSize
*
* @brief
* Get bits-per-element for specified format
*
* @return
* Bits-per-element of specified format
*
****************************************************************************************************
*/
UINT_32 ADDR_API ElemSize(
ADDR_HANDLE hLib,
AddrFormat format);
/**
****************************************************************************************************
@@ -1990,6 +2014,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_CONVERT_TILEINDEX_INPUT
@@ -2114,6 +2140,8 @@ ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_GET_TILEINDEX_INPUT
@@ -2159,6 +2187,8 @@ ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_PRT_INFO_INPUT
@@ -2203,6 +2233,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
const ADDR_PRT_INFO_INPUT* pIn,
ADDR_PRT_INFO_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// DCC key functions
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2263,6 +2295,8 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR_GET_MAX_ALINGMENTS_OUTPUT
@@ -2326,6 +2360,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
*
**/
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface functions for Gfx9
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2360,8 +2395,7 @@ typedef union _ADDR2_SURFACE_FLAGS
UINT_32 noMetadata : 1; ///< This resource has no metadata
UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array
UINT_32 reserved : 13; ///< Reserved bits
UINT_32 reserved : 14; ///< Reserved bits
};
UINT_32 value;
@@ -2489,6 +2523,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
@@ -2555,6 +2591,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
@@ -2620,6 +2658,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// HTile functions for Gfx9
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2670,10 +2710,8 @@ typedef struct _ADDR2_META_MIP_INFO
struct
{
UINT_32 offset; ///< Metadata offset within one slice,
/// the thickness of a slice is meta block depth.
UINT_32 sliceSize; ///< Metadata size within one slice,
/// the thickness of a slice is meta block depth.
UINT_32 offset;
UINT_32 sliceSize;
};
};
} ADDR2_META_MIP_INFO;
@@ -2697,9 +2735,7 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
UINT_32 firstMipIdInTail; /// Id of the first mip in tail,
/// if no mip is in tail, it should be set to
/// number of mip levels
UINT_32 firstMipIdInTail;
} ADDR2_COMPUTE_HTILE_INFO_INPUT;
/**
@@ -2741,6 +2777,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
@@ -2798,6 +2836,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
@@ -2856,6 +2896,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// C-mask functions for Gfx9
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2921,6 +2963,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
@@ -2982,6 +3026,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
@@ -3040,6 +3086,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// F-mask functions for Gfx9
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -3122,6 +3170,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
@@ -3181,6 +3231,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
@@ -3239,6 +3291,8 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// DCC key functions for Gfx9
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -3267,8 +3321,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
///< useful in meta linear case
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
/// it should be number of mip levels
UINT_32 firstMipIdInTail;
} ADDR2_COMPUTE_DCCINFO_INPUT;
/**
@@ -3303,9 +3356,7 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
union
{
UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's
/// the slize size of a mip chain, the thickness of a
/// a slice is meta block depth
UINT_32 dccRamSliceSize;
};
ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
@@ -3325,6 +3376,7 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
@@ -3576,55 +3628,6 @@ typedef union _ADDR2_SWTYPE_SET
UINT_32 value;
} ADDR2_SWTYPE_SET;
/**
****************************************************************************************************
* ADDR2_SWMODE_SET
*
* @brief
* Bit field that defines swizzle type
****************************************************************************************************
*/
typedef union _ADDR2_SWMODE_SET
{
struct
{
UINT_32 swLinear : 1;
UINT_32 sw256B_S : 1;
UINT_32 sw256B_D : 1;
UINT_32 sw256B_R : 1;
UINT_32 sw4KB_Z : 1;
UINT_32 sw4KB_S : 1;
UINT_32 sw4KB_D : 1;
UINT_32 sw4KB_R : 1;
UINT_32 sw64KB_Z : 1;
UINT_32 sw64KB_S : 1;
UINT_32 sw64KB_D : 1;
UINT_32 sw64KB_R : 1;
UINT_32 swVar_Z : 1;
UINT_32 swVar_S : 1;
UINT_32 swVar_D : 1;
UINT_32 swVar_R : 1;
UINT_32 sw64KB_Z_T : 1;
UINT_32 sw64KB_S_T : 1;
UINT_32 sw64KB_D_T : 1;
UINT_32 sw64KB_R_T : 1;
UINT_32 sw4KB_Z_X : 1;
UINT_32 sw4KB_S_X : 1;
UINT_32 sw4KB_D_X : 1;
UINT_32 sw4KB_R_X : 1;
UINT_32 sw64KB_Z_X : 1;
UINT_32 sw64KB_S_X : 1;
UINT_32 sw64KB_D_X : 1;
UINT_32 sw64KB_R_X : 1;
UINT_32 swVar_Z_X : 1;
UINT_32 swVar_S_X : 1;
UINT_32 swVar_D_X : 1;
UINT_32 swVar_R_X : 1;
};
UINT_32 value;
} ADDR2_SWMODE_SET;
/**
****************************************************************************************************
* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
@@ -3678,7 +3681,6 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
/// type
ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination
} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
/**

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -112,6 +112,7 @@ typedef int INT;
#define GC_FASTCALL ADDR_FASTCALL
#endif
#if defined(__GNUC__)
#define ADDR_INLINE static inline // inline needs to be static to link
#else
@@ -352,7 +353,7 @@ typedef enum _AddrFormat {
ADDR_FMT_3_3_2 = 0x00000003,
ADDR_FMT_RESERVED_4 = 0x00000004,
ADDR_FMT_16 = 0x00000005,
ADDR_FMT_16_FLOAT = ADDR_FMT_16,
ADDR_FMT_16_FLOAT = 0x00000006,
ADDR_FMT_8_8 = 0x00000007,
ADDR_FMT_5_6_5 = 0x00000008,
ADDR_FMT_6_5_5 = 0x00000009,
@@ -360,28 +361,28 @@ typedef enum _AddrFormat {
ADDR_FMT_4_4_4_4 = 0x0000000b,
ADDR_FMT_5_5_5_1 = 0x0000000c,
ADDR_FMT_32 = 0x0000000d,
ADDR_FMT_32_FLOAT = ADDR_FMT_32,
ADDR_FMT_32_FLOAT = 0x0000000e,
ADDR_FMT_16_16 = 0x0000000f,
ADDR_FMT_16_16_FLOAT = ADDR_FMT_16_16,
ADDR_FMT_16_16_FLOAT = 0x00000010,
ADDR_FMT_8_24 = 0x00000011,
ADDR_FMT_8_24_FLOAT = ADDR_FMT_8_24,
ADDR_FMT_8_24_FLOAT = 0x00000012,
ADDR_FMT_24_8 = 0x00000013,
ADDR_FMT_24_8_FLOAT = ADDR_FMT_24_8,
ADDR_FMT_24_8_FLOAT = 0x00000014,
ADDR_FMT_10_11_11 = 0x00000015,
ADDR_FMT_10_11_11_FLOAT = ADDR_FMT_10_11_11,
ADDR_FMT_10_11_11_FLOAT = 0x00000016,
ADDR_FMT_11_11_10 = 0x00000017,
ADDR_FMT_11_11_10_FLOAT = ADDR_FMT_11_11_10,
ADDR_FMT_11_11_10_FLOAT = 0x00000018,
ADDR_FMT_2_10_10_10 = 0x00000019,
ADDR_FMT_8_8_8_8 = 0x0000001a,
ADDR_FMT_10_10_10_2 = 0x0000001b,
ADDR_FMT_X24_8_32_FLOAT = 0x0000001c,
ADDR_FMT_32_32 = 0x0000001d,
ADDR_FMT_32_32_FLOAT = ADDR_FMT_32_32,
ADDR_FMT_32_32_FLOAT = 0x0000001e,
ADDR_FMT_16_16_16_16 = 0x0000001f,
ADDR_FMT_16_16_16_16_FLOAT = ADDR_FMT_16_16_16_16,
ADDR_FMT_16_16_16_16_FLOAT = 0x00000020,
ADDR_FMT_RESERVED_33 = 0x00000021,
ADDR_FMT_32_32_32_32 = 0x00000022,
ADDR_FMT_32_32_32_32_FLOAT = ADDR_FMT_32_32_32_32,
ADDR_FMT_32_32_32_32_FLOAT = 0x00000023,
ADDR_FMT_RESERVED_36 = 0x00000024,
ADDR_FMT_1 = 0x00000025,
ADDR_FMT_1_REVERSED = 0x00000026,
@@ -392,9 +393,9 @@ typedef enum _AddrFormat {
ADDR_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
ADDR_FMT_8_8_8 = 0x0000002c,
ADDR_FMT_16_16_16 = 0x0000002d,
ADDR_FMT_16_16_16_FLOAT = ADDR_FMT_16_16_16,
ADDR_FMT_16_16_16_FLOAT = 0x0000002e,
ADDR_FMT_32_32_32 = 0x0000002f,
ADDR_FMT_32_32_32_FLOAT = ADDR_FMT_32_32_32,
ADDR_FMT_32_32_32_FLOAT = 0x00000030,
ADDR_FMT_BC1 = 0x00000031,
ADDR_FMT_BC2 = 0x00000032,
ADDR_FMT_BC3 = 0x00000033,
@@ -549,6 +550,7 @@ typedef enum _AddrHtileBlockSize
ADDR_HTILE_BLOCKSIZE_8 = 8,
} AddrHtileBlockSize;
/**
****************************************************************************************************
* AddrPipeCfg
@@ -582,8 +584,7 @@ typedef enum _AddrPipeCfg
ADDR_PIPECFG_P8_32x64_32x32 = 15,
ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
ADDR_PIPECFG_P16_32x32_16x16 = 18,
ADDR_PIPECFG_RESERVED = 19, /// reserved for internal use
ADDR_PIPECFG_MAX = 20,
ADDR_PIPECFG_MAX = 19,
} AddrPipeCfg;
/**
@@ -711,6 +712,7 @@ typedef enum _AddrTileType
#define ADDR64D "lld" OR "I64d"
#endif
/// @brief Union for storing a 32-bit float or 32-bit integer
/// @ingroup type
///
@@ -726,6 +728,7 @@ typedef union {
float f;
} ADDR_FLT_32;
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Macros for controlling linking and building on multiple systems

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2017-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -96,6 +96,7 @@
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
// ASICREV_IS(eRevisionId, revisionName)
#define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
#define ASICREV_IS_TAHITI_P(r) ASICREV_IS(r, TAHITI)

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -99,6 +99,7 @@
#define ADDR_INFO(cond, a) \
{ if (!(cond)) { ADDR_PRNT(a); } }
/// @brief Macro for reporting error warning messages
/// @ingroup util
///
@@ -117,6 +118,7 @@
ADDR_PRNT((" WARNING in file %s, line %d\n", __FILE__, __LINE__)); \
} }
/// @brief Macro for reporting fatal error conditions
/// @ingroup util
///
@@ -259,8 +261,7 @@ union ConfigFlags
UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
UINT_32 disableLinearOpt : 1; ///< Disallow tile modes to be optimized to linear
UINT_32 use32bppFor422Fmt : 1; ///< View 422 formats as 32 bits per pixel element
UINT_32 reserved : 21; ///< Reserved bits for future use
UINT_32 reserved : 22; ///< Reserved bits for future use
};
UINT_32 value;
@@ -844,6 +845,7 @@ static inline VOID InitChannel(
pChanSet->index = index;
}
/**
****************************************************************************************************
* InitChannel

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -72,7 +72,6 @@ ElemLib::ElemLib(
default:
m_fp16ExportNorm = 1;
m_depthPlanarType = ADDR_DEPTH_PLANAR_R800;
break;
}
m_configFlags.value = 0;
@@ -347,6 +346,7 @@ VOID ElemLib::Int32sToPixel(
UINT_32 elemMask=0;
UINT_32 elementXor = 0; // address xor when reading bytes from elements
// @@ NOTE: assert if called on a compressed format!
if (properties.byteAligned) // Components are all byte-sized
@@ -1387,33 +1387,38 @@ UINT_32 ElemLib::GetBitsPerPixel(
case ADDR_FMT_8_8:
case ADDR_FMT_4_4_4_4:
case ADDR_FMT_16:
case ADDR_FMT_16_FLOAT:
bpp = 16;
break;
case ADDR_FMT_GB_GR:
case ADDR_FMT_GB_GR: // treat as FMT_8_8
elemMode = ADDR_PACKED_GBGR;
bpp = m_configFlags.use32bppFor422Fmt ? 32 : 16;
expandX = m_configFlags.use32bppFor422Fmt ? 2 : 1;
bpp = 16;
break;
case ADDR_FMT_BG_RG:
case ADDR_FMT_BG_RG: // treat as FMT_8_8
elemMode = ADDR_PACKED_BGRG;
bpp = m_configFlags.use32bppFor422Fmt ? 32 : 16;
expandX = m_configFlags.use32bppFor422Fmt ? 2 : 1;
bpp = 16;
break;
case ADDR_FMT_8_8_8_8:
case ADDR_FMT_2_10_10_10:
case ADDR_FMT_10_11_11:
case ADDR_FMT_11_11_10:
case ADDR_FMT_16_16:
case ADDR_FMT_16_16_FLOAT:
case ADDR_FMT_32:
case ADDR_FMT_32_FLOAT:
case ADDR_FMT_24_8:
case ADDR_FMT_24_8_FLOAT:
bpp = 32;
break;
case ADDR_FMT_16_16_16_16:
case ADDR_FMT_16_16_16_16_FLOAT:
case ADDR_FMT_32_32:
case ADDR_FMT_32_32_FLOAT:
case ADDR_FMT_CTX1:
bpp = 64;
break;
case ADDR_FMT_32_32_32_32:
case ADDR_FMT_32_32_32_32_FLOAT:
bpp = 128;
break;
case ADDR_FMT_INVALID:
@@ -1439,7 +1444,10 @@ UINT_32 ElemLib::GetBitsPerPixel(
case ADDR_FMT_32_AS_8:
case ADDR_FMT_32_AS_8_8:
case ADDR_FMT_8_24:
case ADDR_FMT_8_24_FLOAT:
case ADDR_FMT_10_10_10_2:
case ADDR_FMT_10_11_11_FLOAT:
case ADDR_FMT_11_11_10_FLOAT:
case ADDR_FMT_5_9_9_9_SHAREDEXP:
bpp = 32;
break;
@@ -1453,10 +1461,12 @@ UINT_32 ElemLib::GetBitsPerPixel(
expandX = 3;
break;
case ADDR_FMT_16_16_16:
case ADDR_FMT_16_16_16_FLOAT:
elemMode = ADDR_EXPANDED;
bpp = 48;//@@ 16; // read 3 elements per pixel
expandX = 3;
break;
case ADDR_FMT_32_32_32_FLOAT:
case ADDR_FMT_32_32_32:
elemMode = ADDR_EXPANDED;
expandX = 3;
@@ -1745,6 +1755,7 @@ BOOL_32 ElemLib::IsBlockCompressed(
((format >= ADDR_FMT_ASTC_4x4) && (format <= ADDR_FMT_ETC2_128BPP)));
}
/**
****************************************************************************************************
* ElemLib::IsCompressed
@@ -1786,7 +1797,9 @@ BOOL_32 ElemLib::IsExpand3x(
{
case ADDR_FMT_8_8_8:
case ADDR_FMT_16_16_16:
case ADDR_FMT_16_16_16_FLOAT:
case ADDR_FMT_32_32_32:
case ADDR_FMT_32_32_32_FLOAT:
is3x = TRUE;
break;
default:

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -157,6 +157,7 @@ Lib::~Lib()
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Initialization/Helper
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -206,7 +207,7 @@ ADDR_E_RETURNCODE Lib::Create(
pLib = SiHwlInit(&client);
break;
case FAMILY_VI:
case FAMILY_CZ:
case FAMILY_CZ: // VI based fusion(carrizo)
case FAMILY_CI:
case FAMILY_KV: // CI based fusion
pLib = CiHwlInit(&client);
@@ -485,10 +486,12 @@ UINT_32 Lib::Bits2Number(
return number;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Element lib
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
****************************************************************************************************
* Lib::Flt32ToColorPixel
@@ -604,6 +607,7 @@ ADDR_E_RETURNCODE Lib::Flt32ToColorPixel(
return returnCode;
}
/**
****************************************************************************************************
* Lib::GetExportNorm
@@ -637,19 +641,4 @@ BOOL_32 Lib::GetExportNorm(
return enabled;
}
/**
****************************************************************************************************
* Lib::GetBpe
*
* @brief
* Get bits-per-element for specified format
* @return
* bits-per-element of specified format
****************************************************************************************************
*/
UINT_32 Lib::GetBpe(AddrFormat format) const
{
return GetElemLib()->GetBitsPerPixel(format);
}
} // Addr

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -286,8 +286,6 @@ public:
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
UINT_32 GetBpe(AddrFormat format) const;
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2016 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -140,17 +140,19 @@ Lib* Lib::GetLib(
((pAddrLib->GetChipFamily() == ADDR_CHIP_FAMILY_IVLD) ||
(pAddrLib->GetChipFamily() > ADDR_CHIP_FAMILY_VI)))
{
// only valid and pre-VI ASIC can use AddrLib1 function.
// only valid and pre-VI AISC can use AddrLib1 function.
ADDR_ASSERT_ALWAYS();
hLib = NULL;
}
return static_cast<Lib*>(hLib);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface Methods
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
****************************************************************************************************
* Lib::ComputeSurfaceInfo
@@ -1228,6 +1230,8 @@ UINT_32 Lib::Thickness(
return ModeFlags[tileMode].thickness;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// CMASK/HTILE
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -2008,6 +2012,7 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo(
*pPitchOut = (pitchIn + macroWidth - 1) & ~(macroWidth - 1);
*pHeightOut = (heightIn + macroHeight - 1) & ~(macroHeight - 1);
sliceBytes = ComputeCmaskBytes(*pPitchOut,
*pHeightOut,
1);
@@ -2235,6 +2240,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
UINT_32 groupBits = 8 * m_pipeInterleaveBytes;
UINT_32 pipes = numPipes;
//
// Compute the micro tile size, in bits. And macro tile pitch and height.
//
@@ -2287,17 +2293,20 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
pitch = pitchAligned;
height = heightAligned;
//
// Convert byte address to bit address.
//
bitAddr = BYTES_TO_BITS(addr) + bitPosition;
//
// Remove pipe bits from address.
//
bitAddr = (bitAddr % groupBits) + ((bitAddr/groupBits/pipes)*groupBits);
elemOffset = bitAddr / elemBits;
tilesPerMacro = (macroTilePitch/factor) * macroTileHeight / MicroTilePixels >> numPipeBits;
@@ -2315,6 +2324,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
macroY = static_cast<UINT_32>((macroNumber % macrosPerSlice) / macrosPerPitch);
macroZ = static_cast<UINT_32>((macroNumber / macrosPerSlice));
microX = microNumber % (macroTilePitch / factor / MicroTileWidth);
microY = (microNumber / (macroTilePitch / factor / MicroTileHeight));
@@ -2325,6 +2335,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr(
microTileCoordY = ComputeXmaskCoordYFromPipe(pipe,
*pX/MicroTileWidth);
//
// Assemble final coordinates.
//
@@ -2384,6 +2395,7 @@ UINT_64 Lib::HwlComputeXmaskAddrFromCoord(
UINT_64 offsetHi;
UINT_64 groupMask;
UINT_32 elemBits = 0;
UINT_32 numPipes = m_pipes; // This function is accessed prior to si only
@@ -3346,6 +3358,7 @@ VOID Lib::PadDimensions(
heightAlign);
}
/**
****************************************************************************************************
* Lib::HwlPreHandleBaseLvl3xPitch
@@ -3407,6 +3420,7 @@ UINT_32 Lib::HwlPostHandleBaseLvl3xPitch(
return expPitch;
}
/**
****************************************************************************************************
* Lib::IsMacroTiled
@@ -3927,6 +3941,7 @@ VOID Lib::ComputeQbStereoInfo(
// 1D surface on SI may break this rule, but we can force it to meet by checking .qbStereo.
}
/**
****************************************************************************************************
* Lib::ComputePrtInfo

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2016 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -354,6 +354,7 @@ protected:
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const = 0;
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -113,17 +113,19 @@ Lib* Lib::GetLib(
if ((pAddrLib != NULL) &&
(pAddrLib->GetChipFamily() <= ADDR_CHIP_FAMILY_VI))
{
// only valid and GFX9+ ASIC can use AddrLib2 function.
// only valid and GFX9+ AISC can use AddrLib2 function.
ADDR_ASSERT_ALWAYS();
hLib = NULL;
}
return static_cast<Lib*>(hLib);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Surface Methods
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
************************************************************************************************************************
* Lib::ComputeSurfaceInfo
@@ -415,6 +417,7 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceCoordFromAddr(
return returnCode;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// CMASK/HTILE
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -830,6 +833,10 @@ ADDR_E_RETURNCODE Lib::ComputePipeBankXor(
{
returnCode = ADDR_INVALIDPARAMS;
}
else if (IsXor(pIn->swizzleMode) == FALSE)
{
returnCode = ADDR_NOTSUPPORTED;
}
else
{
returnCode = HwlComputePipeBankXor(pIn, pOut);
@@ -1878,6 +1885,7 @@ VOID Lib::ComputeQbStereoInfo(
pOut->surfSize <<= 1;
}
} // V2
} // Addr

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -83,39 +83,6 @@ struct Dim3d
UINT_32 d;
};
// Macro define resource block type
enum AddrBlockType
{
AddrBlockMicro = 0, // Resource uses 256B block
AddrBlock4KB = 1, // Resource uses 4KB block
AddrBlock64KB = 2, // Resource uses 64KB block
AddrBlockVar = 3, // Resource uses var block, only valid for GFX9
AddrBlockLinear = 4, // Resource uses linear swizzle mode
AddrBlockMaxTiledType = AddrBlock64KB + 1,
};
enum AddrBlockSet
{
AddrBlockSetMicro = 1 << AddrBlockMicro,
AddrBlockSetMacro4KB = 1 << AddrBlock4KB,
AddrBlockSetMacro64KB = 1 << AddrBlock64KB,
AddrBlockSetVar = 1 << AddrBlockVar,
AddrBlockSetLinear = 1 << AddrBlockLinear,
AddrBlockSetMacro = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
};
enum AddrSwSet
{
AddrSwSetZ = 1 << ADDR_SW_Z,
AddrSwSetS = 1 << ADDR_SW_S,
AddrSwSetD = 1 << ADDR_SW_D,
AddrSwSetR = 1 << ADDR_SW_R,
AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
};
/**
************************************************************************************************************************
* @brief This class contains asic independent address lib functionalities
@@ -223,7 +190,6 @@ protected:
Lib(const Client* pClient);
static const UINT_32 MaxNumOfBpp = 5;
static const UINT_32 MaxNumOfAA = 4;
static const Dim2d Block256_2d[MaxNumOfBpp];
static const Dim3d Block1K_3d[MaxNumOfBpp];
@@ -270,21 +236,6 @@ protected:
return m_swizzleModeTable[swizzleMode].isZ;
}
BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isStd;
}
BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isDisp;
}
BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isRot;
}
BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return HwlIsStandardSwizzle(resourceType, swizzleMode);
@@ -295,6 +246,11 @@ protected:
return HwlIsDisplaySwizzle(resourceType, swizzleMode);
}
BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isRot;
}
BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isXor;
@@ -540,6 +496,7 @@ protected:
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

File diff suppressed because it is too large Load Diff

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -28,11 +28,6 @@
#include "addrcommon.h"
#include "coord.h"
namespace Addr
{
namespace V2
{
Coordinate::Coordinate()
{
dim = 'x';
@@ -710,5 +705,3 @@ BOOL_32 CoordEq::operator!=(const CoordEq& b)
return !(*this == b);
}
} // V2
} // Addr

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -29,11 +29,6 @@
#ifndef __COORD_H
#define __COORD_H
namespace Addr
{
namespace V2
{
class Coordinate
{
public:
@@ -115,8 +110,5 @@ private:
CoordTerm m_eq[MaxEqBits];
};
} // V2
} // Addr
#endif

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -57,7 +57,6 @@ struct Gfx9ChipSettings
UINT_32 isRaven : 1;
UINT_32 isVega12 : 1;
UINT_32 isVega20 : 1;
UINT_32 reserved0 : 27;
// Display engine IP version name
UINT_32 isDce12 : 1;
@@ -85,155 +84,6 @@ enum Gfx9DataType
Gfx9DataFmask
};
const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR);
const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_256B_R);
const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X);
const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_R_T) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx9BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z) |
(1u << ADDR_SW_VAR_S) |
(1u << ADDR_SW_VAR_D) |
(1u << ADDR_SW_VAR_R) |
(1u << ADDR_SW_VAR_Z_X) |
(1u << ADDR_SW_VAR_S_X) |
(1u << ADDR_SW_VAR_D_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) |
(1u << ADDR_SW_64KB_Z) |
(1u << ADDR_SW_VAR_Z) |
(1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_VAR_Z_X);
const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_VAR_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_VAR_S_X);
const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_VAR_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_VAR_D_X);
const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_VAR_R) |
(1u << ADDR_SW_64KB_R_T) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_VAR_Z_X) |
(1u << ADDR_SW_VAR_S_X) |
(1u << ADDR_SW_VAR_D_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_R_T);
const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask |
Gfx9TSwModeMask;
const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask |
Gfx9ZSwModeMask |
Gfx9StandardSwModeMask |
Gfx9DisplaySwModeMask |
Gfx9RotateSwModeMask;
const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask;
const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask;
const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask;
const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask;
const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask;
const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask;
const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask;
const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_VAR_D) |
(1u << ADDR_SW_VAR_R) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_VAR_D_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_256B_R) |
Dce12NonBpp32SwModeMask;
const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_VAR_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_VAR_S_X);
const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_VAR_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_VAR_D_X) |
Dcn1NonBpp64SwModeMask;
/**
************************************************************************************************************************
* @brief GFX9 meta equation parameters
@@ -272,9 +122,6 @@ public:
return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
}
virtual BOOL_32 IsValidDisplaySwizzleMode(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
protected:
Gfx9Lib(const Client* pClient);
virtual ~Gfx9Lib();
@@ -521,6 +368,7 @@ protected:
return compressBlkDim;
}
static const UINT_32 MaxSeLog2 = 3;
static const UINT_32 MaxRbPerSeLog2 = 2;
@@ -584,37 +432,14 @@ private:
UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pMipmap0PaddedWidth,
UINT_32* pSlice0PaddedHeight,
ADDR2_MIP_INFO* pMipInfo = NULL) const;
static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_BLOCK_SET allowedBlockSet = {};
allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macro4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macro64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.var = (allowedSwModeSet.value & Gfx9BlkVarSwModeMask) ? TRUE : FALSE;
allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE;
return allowedBlockSet;
}
static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_SWTYPE_SET allowedSwSet = {};
allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE;
return allowedSwSet;
}
Gfx9ChipSettings m_settings;
CoordEq m_cachedMetaEq[MaxCachedMetaEq];

View File

@@ -2,7 +2,7 @@
#define __GFX9_GB_REG_H__
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2017 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -2,7 +2,7 @@
#define __SI_GB_REG_H__
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -19,33 +19,35 @@
# SOFTWARE.
files_addrlib = files(
'inc/addrinterface.h',
'inc/addrtypes.h',
'src/addrinterface.cpp',
'src/core/addrcommon.h',
'src/core/addrelemlib.cpp',
'src/core/addrelemlib.h',
'src/core/addrlib.cpp',
'src/core/addrlib.h',
'src/core/addrlib1.cpp',
'src/core/addrlib1.h',
'src/core/addrlib2.cpp',
'src/core/addrlib2.h',
'src/core/addrobject.cpp',
'src/core/addrobject.h',
'src/core/coord.cpp',
'src/core/coord.h',
'src/gfx9/gfx9addrlib.cpp',
'src/gfx9/gfx9addrlib.h',
'src/amdgpu_asic_addr.h',
'src/chip/gfx9/gfx9_gb_reg.h',
'src/chip/r800/si_gb_reg.h',
'src/r800/ciaddrlib.cpp',
'src/r800/ciaddrlib.h',
'src/r800/egbaddrlib.cpp',
'src/r800/egbaddrlib.h',
'src/r800/siaddrlib.cpp',
'src/r800/siaddrlib.h',
'addrinterface.cpp',
'addrinterface.h',
'addrtypes.h',
'core/addrcommon.h',
'core/addrelemlib.cpp',
'core/addrelemlib.h',
'core/addrlib.cpp',
'core/addrlib.h',
'core/addrlib1.cpp',
'core/addrlib1.h',
'core/addrlib2.cpp',
'core/addrlib2.h',
'core/addrobject.cpp',
'core/addrobject.h',
'gfx9/chip/gfx9_enum.h',
'gfx9/coord.cpp',
'gfx9/coord.h',
'gfx9/gfx9addrlib.cpp',
'gfx9/gfx9addrlib.h',
'amdgpu_asic_addr.h',
'inc/chip/gfx9/gfx9_gb_reg.h',
'inc/chip/r800/si_gb_reg.h',
'r800/chip/si_ci_vi_merged_enum.h',
'r800/ciaddrlib.cpp',
'r800/ciaddrlib.h',
'r800/egbaddrlib.cpp',
'r800/egbaddrlib.h',
'r800/siaddrlib.cpp',
'r800/siaddrlib.h',
)
libamdgpu_addrlib = static_library(
@@ -53,7 +55,7 @@ libamdgpu_addrlib = static_library(
files_addrlib,
include_directories : [
include_directories(
'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
),
inc_amd_common, inc_common, inc_src,
],

View File

@@ -0,0 +1,40 @@
/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#if !defined (SI_CI_VI_MERGED_ENUM_HEADER)
#define SI_CI_VI_MERGED_ENUM_HEADER
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
} PipeInterleaveSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x00000000,
ADDR_CONFIG_2KB_ROW = 0x00000001,
ADDR_CONFIG_4KB_ROW = 0x00000002,
} RowSize;
#endif

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -1038,6 +1038,7 @@ VOID CiLib::HwlOverrideTileMode(
{
switch (pInOut->format)
{
// see //gfxip/gcB/devel/cds/src/verif/tc/models/csim/tcp.cpp
// tcpError("Thick micro tiling is not supported for format...
case ADDR_FMT_X24_8_32_FLOAT:
case ADDR_FMT_32_AS_8:
@@ -2032,6 +2033,7 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
/// NOTE *2 because we are converting to Nibble address in this step
UINT_64 metaAddressInPipe = blockInBankpipeWithBankBits * 2 * metadataBitSize / 8;
///--------------------------------------------------------------------------------------------
/// Reinsert pipe bits back into the final address
///--------------------------------------------------------------------------------------------

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -151,14 +151,12 @@ protected:
UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, TileConfig* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
private:
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
@@ -199,3 +197,5 @@ private:
} // Addr
#endif

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -436,6 +436,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
&expPitch,
&expHeight);
pOut->pitch = expPitch;
pOut->height = expHeight;
pOut->depth = expNumSlices;
@@ -447,6 +448,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
return valid;
}
/**
****************************************************************************************************
* EgBasedLib::ComputeSurfaceInfoMacroTiled
@@ -753,6 +755,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
return valid;
}
/**
****************************************************************************************************
* EgBasedLib::HwlReduceBankWidthHeight
@@ -1814,6 +1817,7 @@ UINT_64 EgBasedLib::ComputeSurfaceAddrFromCoordMacroTiled(
tileSplitSlice,
pTileInfo);
//
// Split the offset to put some bits below the pipe+bank bits and some above.
//
@@ -2157,6 +2161,7 @@ VOID EgBasedLib::HwlComputePixelCoordFromOffset(
*pSlice += z;
}
/**
****************************************************************************************************
* EgBasedLib::DispatchComputeSurfaceCoordFromAddrDispatch
@@ -2301,6 +2306,7 @@ VOID EgBasedLib::DispatchComputeSurfaceCoordFromAddr(
}
}
/**
****************************************************************************************************
* EgBasedLib::ComputeSurfaceCoordFromAddrMacroTiled
@@ -2345,6 +2351,7 @@ VOID EgBasedLib::ComputeSurfaceCoordFromAddrMacroTiled(
UINT_32 tileIndex;
UINT_64 totalOffset;
UINT_32 bank;
UINT_32 pipe;
UINT_32 groupBits = m_pipeInterleaveBytes << 3;
@@ -2666,6 +2673,7 @@ ADDR_E_RETURNCODE EgBasedLib::HwlExtractBankPipeSwizzle(
return ADDR_OK;
}
/**
****************************************************************************************************
* EgBasedLib::HwlCombineBankPipeSwizzle
@@ -3035,6 +3043,7 @@ UINT_32 EgBasedLib::ComputeBankFromCoord(
break;
}
//
// Compute bank rotation for the tile split slice.
//
@@ -3132,6 +3141,8 @@ UINT_32 EgBasedLib::ComputePipeRotation(
return rotation;
}
/**
****************************************************************************************************
* EgBasedLib::ComputeBankRotation
@@ -3174,6 +3185,7 @@ UINT_32 EgBasedLib::ComputeBankRotation(
return rotation;
}
/**
****************************************************************************************************
* EgBasedLib::ComputeHtileBytes

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining

View File

@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -88,6 +88,7 @@ struct SiChipSettings
UINT_32 isPolaris11 : 1;
UINT_32 isPolaris12 : 1;
UINT_32 isVegaM : 1;
// VI fusion
UINT_32 isCarrizo : 1;
};

View File

@@ -233,7 +233,6 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
if (op == PKT3_SET_CONTEXT_REG ||
op == PKT3_SET_CONFIG_REG ||
op == PKT3_SET_UCONFIG_REG ||
op == PKT3_SET_UCONFIG_REG_INDEX ||
op == PKT3_SET_SH_REG)
fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
name, predicate);
@@ -253,7 +252,6 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
ac_parse_set_reg_packet(f, count, SI_CONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_UCONFIG_REG:
case PKT3_SET_UCONFIG_REG_INDEX:
ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib);
break;
case PKT3_SET_SH_REG:

View File

@@ -75,7 +75,7 @@ ac_llvm_context_init(struct ac_llvm_context *ctx,
ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
ctx->intptr = ctx->i32;
ctx->intptr = HAVE_32BIT_POINTERS ? ctx->i32 : ctx->i64;
ctx->f16 = LLVMHalfTypeInContext(ctx->context);
ctx->f32 = LLVMFloatTypeInContext(ctx->context);
ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
@@ -229,15 +229,6 @@ ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
return LLVMBuildBitCast(ctx->builder, v, ac_to_integer_type(ctx, type), "");
}
LLVMValueRef
ac_to_integer_or_pointer(struct ac_llvm_context *ctx, LLVMValueRef v)
{
LLVMTypeRef type = LLVMTypeOf(v);
if (LLVMGetTypeKind(type) == LLVMPointerTypeKind)
return v;
return ac_to_integer(ctx, v);
}
static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
{
if (t == ctx->i16 || t == ctx->f16)
@@ -954,14 +945,6 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
ctx->f32, args, 4, AC_FUNC_ATTR_READNONE);
}
LLVMValueRef
ac_build_gep_ptr(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
LLVMValueRef index)
{
return LLVMBuildGEP(ctx->builder, base_ptr, &index, 1, "");
}
LLVMValueRef
ac_build_gep0(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
@@ -1209,47 +1192,6 @@ ac_build_buffer_load_common(struct ac_llvm_context *ctx,
ac_get_load_intr_attribs(can_speculate));
}
static LLVMValueRef
ac_build_llvm8_buffer_load_common(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
LLVMValueRef vindex,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned num_channels,
bool glc,
bool slc,
bool can_speculate,
bool use_format,
bool structurized)
{
LLVMValueRef args[5];
int idx = 0;
args[idx++] = LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, "");
if (structurized)
args[idx++] = vindex ? vindex : ctx->i32_0;
args[idx++] = voffset ? voffset : ctx->i32_0;
args[idx++] = soffset ? soffset : ctx->i32_0;
args[idx++] = LLVMConstInt(ctx->i32, (glc ? 1 : 0) + (slc ? 2 : 0), 0);
unsigned func = CLAMP(num_channels, 1, 3) - 1;
LLVMTypeRef types[] = {ctx->f32, ctx->v2f32, ctx->v4f32};
const char *type_names[] = {"f32", "v2f32", "v4f32"};
const char *indexing_kind = structurized ? "struct" : "raw";
char name[256];
if (use_format) {
snprintf(name, sizeof(name), "llvm.amdgcn.%s.buffer.load.format.%s",
indexing_kind, type_names[func]);
} else {
snprintf(name, sizeof(name), "llvm.amdgcn.%s.buffer.load.%s",
indexing_kind, type_names[func]);
}
return ac_build_intrinsic(ctx, name, types[func], args,
idx,
ac_get_load_intr_attribs(can_speculate));
}
LLVMValueRef
ac_build_buffer_load(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
@@ -1269,8 +1211,8 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
if (soffset)
offset = LLVMBuildAdd(ctx->builder, offset, soffset, "");
if (allow_smem && !slc &&
(!glc || (HAVE_LLVM >= 0x0800 && ctx->chip_class >= VI))) {
/* TODO: VI and later generations can use SMEM with GLC=1.*/
if (allow_smem && !glc && !slc) {
assert(vindex == NULL);
LLVMValueRef result[8];
@@ -1280,19 +1222,11 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
offset = LLVMBuildAdd(ctx->builder, offset,
LLVMConstInt(ctx->i32, 4, 0), "");
}
const char *intrname =
HAVE_LLVM >= 0x0800 ? "llvm.amdgcn.s.buffer.load.f32"
: "llvm.SI.load.const.v4i32";
unsigned num_args = HAVE_LLVM >= 0x0800 ? 3 : 2;
LLVMValueRef args[3] = {
rsrc,
offset,
glc ? ctx->i32_1 : ctx->i32_0,
};
result[i] = ac_build_intrinsic(ctx, intrname,
ctx->f32, args, num_args,
LLVMValueRef args[2] = {rsrc, offset};
result[i] = ac_build_intrinsic(ctx, "llvm.SI.load.const.v4i32",
ctx->f32, args, 2,
AC_FUNC_ATTR_READNONE |
(HAVE_LLVM < 0x0800 ? AC_FUNC_ATTR_LEGACY : 0));
AC_FUNC_ATTR_LEGACY);
}
if (num_channels == 1)
return result[0];
@@ -1315,11 +1249,6 @@ LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
bool glc,
bool can_speculate)
{
if (HAVE_LLVM >= 0x800) {
return ac_build_llvm8_buffer_load_common(ctx, rsrc, vindex, voffset, ctx->i32_0,
num_channels, glc, false,
can_speculate, true, true);
}
return ac_build_buffer_load_common(ctx, rsrc, vindex, voffset,
num_channels, glc, false,
can_speculate, true);
@@ -1333,12 +1262,6 @@ LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
bool glc,
bool can_speculate)
{
if (HAVE_LLVM >= 0x800) {
return ac_build_llvm8_buffer_load_common(ctx, rsrc, vindex, voffset, ctx->i32_0,
num_channels, glc, false,
can_speculate, true, true);
}
LLVMValueRef elem_count = LLVMBuildExtractElement(ctx->builder, rsrc, LLVMConstInt(ctx->i32, 2, 0), "");
LLVMValueRef stride = LLVMBuildExtractElement(ctx->builder, rsrc, ctx->i32_1, "");
stride = LLVMBuildLShr(ctx->builder, stride, LLVMConstInt(ctx->i32, 16, 0), "");
@@ -1450,10 +1373,12 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
int idx,
LLVMValueRef val)
{
unsigned tl_lanes[4], trbl_lanes[4];
LLVMValueRef tl, trbl;
LLVMValueRef tl, trbl, args[2];
LLVMValueRef result;
if (HAVE_LLVM >= 0x0700) {
unsigned tl_lanes[4], trbl_lanes[4];
for (unsigned i = 0; i < 4; ++i) {
tl_lanes[i] = i & mask;
trbl_lanes[i] = (i & mask) + idx;
@@ -1465,13 +1390,82 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
trbl = ac_build_quad_swizzle(ctx, val,
trbl_lanes[0], trbl_lanes[1],
trbl_lanes[2], trbl_lanes[3]);
} else if (ctx->chip_class >= VI) {
LLVMValueRef thread_id, tl_tid, trbl_tid;
thread_id = ac_get_thread_id(ctx);
tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
LLVMConstInt(ctx->i32, mask, false), "");
trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
LLVMConstInt(ctx->i32, idx, false), "");
args[0] = LLVMBuildMul(ctx->builder, tl_tid,
LLVMConstInt(ctx->i32, 4, false), "");
args[1] = val;
tl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.bpermute", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
LLVMConstInt(ctx->i32, 4, false), "");
trbl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.bpermute", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
} else {
uint32_t masks[2] = {};
switch (mask) {
case AC_TID_MASK_TOP_LEFT:
masks[0] = 0x8000;
if (idx == 1)
masks[1] = 0x8055;
else
masks[1] = 0x80aa;
break;
case AC_TID_MASK_TOP:
masks[0] = 0x8044;
masks[1] = 0x80ee;
break;
case AC_TID_MASK_LEFT:
masks[0] = 0x80a0;
masks[1] = 0x80f5;
break;
default:
assert(0);
}
args[0] = val;
args[1] = LLVMConstInt(ctx->i32, masks[0], false);
tl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.swizzle", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
args[1] = LLVMConstInt(ctx->i32, masks[1], false);
trbl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.swizzle", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
}
tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
result = ac_build_intrinsic(ctx, "llvm.amdgcn.wqm.f32", ctx->f32,
if (HAVE_LLVM >= 0x0700) {
result = ac_build_intrinsic(ctx,
"llvm.amdgcn.wqm.f32", ctx->f32,
&result, 1, 0);
}
return result;
}
@@ -1716,6 +1710,171 @@ static const char *get_atomic_name(enum ac_atomic_op op)
unreachable("bad atomic op");
}
/* LLVM 6 and older */
static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
LLVMValueRef args[16];
LLVMTypeRef retty = ctx->v4f32;
const char *name = NULL;
const char *atomic_subop = "";
char intr_name[128], coords_type[64];
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
bool atomic = a->opcode == ac_image_atomic ||
a->opcode == ac_image_atomic_cmpswap;
bool da = a->dim == ac_image_cube ||
a->dim == ac_image_1darray ||
a->dim == ac_image_2darray ||
a->dim == ac_image_2darraymsaa;
if (a->opcode == ac_image_get_lod)
da = false;
unsigned num_coords =
a->opcode != ac_image_get_resinfo ? ac_num_coords(a->dim) : 0;
LLVMValueRef addr;
unsigned num_addr = 0;
if (a->opcode == ac_image_get_lod) {
switch (a->dim) {
case ac_image_1darray:
num_coords = 1;
break;
case ac_image_2darray:
case ac_image_cube:
num_coords = 2;
break;
default:
break;
}
}
if (a->offset)
args[num_addr++] = ac_to_integer(ctx, a->offset);
if (a->bias)
args[num_addr++] = ac_to_integer(ctx, a->bias);
if (a->compare)
args[num_addr++] = ac_to_integer(ctx, a->compare);
if (a->derivs[0]) {
unsigned num_derivs = ac_num_derivs(a->dim);
for (unsigned i = 0; i < num_derivs; ++i)
args[num_addr++] = ac_to_integer(ctx, a->derivs[i]);
}
for (unsigned i = 0; i < num_coords; ++i)
args[num_addr++] = ac_to_integer(ctx, a->coords[i]);
if (a->lod)
args[num_addr++] = ac_to_integer(ctx, a->lod);
unsigned pad_goal = util_next_power_of_two(num_addr);
while (num_addr < pad_goal)
args[num_addr++] = LLVMGetUndef(ctx->i32);
addr = ac_build_gather_values(ctx, args, num_addr);
unsigned num_args = 0;
if (atomic || a->opcode == ac_image_store || a->opcode == ac_image_store_mip) {
args[num_args++] = a->data[0];
if (a->opcode == ac_image_atomic_cmpswap)
args[num_args++] = a->data[1];
}
unsigned coords_arg = num_args;
if (sample)
args[num_args++] = ac_to_float(ctx, addr);
else
args[num_args++] = ac_to_integer(ctx, addr);
args[num_args++] = a->resource;
if (sample)
args[num_args++] = a->sampler;
if (!atomic) {
args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
if (sample)
args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
args[num_args++] = a->cache_policy & ac_glc ? ctx->i1true : ctx->i1false;
args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
args[num_args++] = ctx->i1false; /* lwe */
args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
} else {
args[num_args++] = ctx->i1false; /* r128 */
args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
}
switch (a->opcode) {
case ac_image_sample:
name = "llvm.amdgcn.image.sample";
break;
case ac_image_gather4:
name = "llvm.amdgcn.image.gather4";
break;
case ac_image_load:
name = "llvm.amdgcn.image.load";
break;
case ac_image_load_mip:
name = "llvm.amdgcn.image.load.mip";
break;
case ac_image_store:
name = "llvm.amdgcn.image.store";
retty = ctx->voidt;
break;
case ac_image_store_mip:
name = "llvm.amdgcn.image.store.mip";
retty = ctx->voidt;
break;
case ac_image_atomic:
case ac_image_atomic_cmpswap:
name = "llvm.amdgcn.image.atomic.";
retty = ctx->i32;
if (a->opcode == ac_image_atomic_cmpswap) {
atomic_subop = "cmpswap";
} else {
atomic_subop = get_atomic_name(a->atomic);
}
break;
case ac_image_get_lod:
name = "llvm.amdgcn.image.getlod";
break;
case ac_image_get_resinfo:
name = "llvm.amdgcn.image.getresinfo";
break;
default:
unreachable("invalid image opcode");
}
ac_build_type_name_for_intr(LLVMTypeOf(args[coords_arg]), coords_type,
sizeof(coords_type));
if (atomic) {
snprintf(intr_name, sizeof(intr_name), "llvm.amdgcn.image.atomic.%s.%s",
atomic_subop, coords_type);
} else {
bool lod_suffix =
a->lod && (a->opcode == ac_image_sample || a->opcode == ac_image_gather4);
snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.v4f32.%s.v8i32",
name,
a->compare ? ".c" : "",
a->bias ? ".b" :
lod_suffix ? ".l" :
a->derivs[0] ? ".d" :
a->level_zero ? ".lz" : "",
a->offset ? ".o" : "",
coords_type);
}
LLVMValueRef result =
ac_build_intrinsic(ctx, intr_name, retty, args, num_args,
a->attributes);
if (!sample && retty == ctx->v4f32) {
result = LLVMBuildBitCast(ctx->builder, result,
ctx->v4i32, "");
}
return result;
}
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
@@ -1740,6 +1899,9 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
(a->level_zero ? 1 : 0) +
(a->derivs[0] ? 1 : 0) <= 1);
if (HAVE_LLVM < 0x0700)
return ac_build_image_opcode_llvm6(ctx, a);
if (a->opcode == ac_image_get_lod) {
switch (dim) {
case ac_image_1darray:
@@ -2528,6 +2690,9 @@ LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type)
LLVMTypeRef ac_array_in_const32_addr_space(LLVMTypeRef elem_type)
{
if (!HAVE_32BIT_POINTERS)
return ac_array_in_const_addr_space(elem_type);
return LLVMPointerType(LLVMArrayType(elem_type, 0),
AC_ADDR_SPACE_CONST_32BIT);
}
@@ -2673,7 +2838,8 @@ void ac_build_endloop(struct ac_llvm_context *ctx, int label_id)
ctx->flow_depth--;
}
void ac_build_ifcc(struct ac_llvm_context *ctx, LLVMValueRef cond, int label_id)
static void if_cond_emit(struct ac_llvm_context *ctx, LLVMValueRef cond,
int label_id)
{
struct ac_llvm_flow *flow = push_flow(ctx);
LLVMBasicBlockRef if_block;
@@ -2690,7 +2856,7 @@ void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
{
LLVMValueRef cond = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
value, ctx->f32_0, "");
ac_build_ifcc(ctx, cond, label_id);
if_cond_emit(ctx, cond, label_id);
}
void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
@@ -2699,7 +2865,7 @@ void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
ac_to_integer(ctx, value),
ctx->i32_0, "");
ac_build_ifcc(ctx, cond, label_id);
if_cond_emit(ctx, cond, label_id);
}
LLVMValueRef ac_build_alloca_undef(struct ac_llvm_context *ac, LLVMTypeRef type,
@@ -3159,44 +3325,24 @@ ac_build_alu_op(struct ac_llvm_context *ctx, LLVMValueRef lhs, LLVMValueRef rhs,
}
}
/**
* \param maxprefix specifies that the result only needs to be correct for a
* prefix of this many threads
*
* TODO: add inclusive and excluse scan functions for SI chip class.
*/
/* TODO: add inclusive and excluse scan functions for SI chip class. */
static LLVMValueRef
ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValueRef identity,
unsigned maxprefix)
ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValueRef identity)
{
LLVMValueRef result, tmp;
result = src;
if (maxprefix <= 1)
return result;
tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(1), 0xf, 0xf, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 2)
return result;
tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(2), 0xf, 0xf, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 3)
return result;
tmp = ac_build_dpp(ctx, identity, src, dpp_row_sr(3), 0xf, 0xf, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 4)
return result;
tmp = ac_build_dpp(ctx, identity, result, dpp_row_sr(4), 0xf, 0xe, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 8)
return result;
tmp = ac_build_dpp(ctx, identity, result, dpp_row_sr(8), 0xf, 0xc, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 16)
return result;
tmp = ac_build_dpp(ctx, identity, result, dpp_row_bcast15, 0xa, 0xf, false);
result = ac_build_alu_op(ctx, result, tmp, op);
if (maxprefix <= 32)
return result;
tmp = ac_build_dpp(ctx, identity, result, dpp_row_bcast31, 0xc, 0xf, false);
result = ac_build_alu_op(ctx, result, tmp, op);
return result;
@@ -3205,24 +3351,14 @@ ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValu
LLVMValueRef
ac_build_inclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op)
{
LLVMValueRef result;
if (LLVMTypeOf(src) == ctx->i1 && op == nir_op_iadd) {
LLVMBuilderRef builder = ctx->builder;
src = LLVMBuildZExt(builder, src, ctx->i32, "");
result = ac_build_ballot(ctx, src);
result = ac_build_mbcnt(ctx, result);
result = LLVMBuildAdd(builder, result, src, "");
return result;
}
ac_build_optimization_barrier(ctx, &src);
LLVMValueRef identity =
get_reduction_identity(ctx, op, ac_get_type_size(LLVMTypeOf(src)));
result = LLVMBuildBitCast(ctx->builder, ac_build_set_inactive(ctx, src, identity),
LLVMValueRef result;
LLVMValueRef identity = get_reduction_identity(ctx, op,
ac_get_type_size(LLVMTypeOf(src)));
result = LLVMBuildBitCast(ctx->builder,
ac_build_set_inactive(ctx, src, identity),
LLVMTypeOf(identity), "");
result = ac_build_scan(ctx, op, result, identity, 64);
result = ac_build_scan(ctx, op, result, identity);
return ac_build_wwm(ctx, result);
}
@@ -3230,24 +3366,15 @@ ac_build_inclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op
LLVMValueRef
ac_build_exclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op)
{
LLVMValueRef result;
if (LLVMTypeOf(src) == ctx->i1 && op == nir_op_iadd) {
LLVMBuilderRef builder = ctx->builder;
src = LLVMBuildZExt(builder, src, ctx->i32, "");
result = ac_build_ballot(ctx, src);
result = ac_build_mbcnt(ctx, result);
return result;
}
ac_build_optimization_barrier(ctx, &src);
LLVMValueRef identity =
get_reduction_identity(ctx, op, ac_get_type_size(LLVMTypeOf(src)));
result = LLVMBuildBitCast(ctx->builder, ac_build_set_inactive(ctx, src, identity),
LLVMValueRef result;
LLVMValueRef identity = get_reduction_identity(ctx, op,
ac_get_type_size(LLVMTypeOf(src)));
result = LLVMBuildBitCast(ctx->builder,
ac_build_set_inactive(ctx, src, identity),
LLVMTypeOf(identity), "");
result = ac_build_dpp(ctx, identity, result, dpp_wf_sr1, 0xf, 0xf, false);
result = ac_build_scan(ctx, op, result, identity, 64);
result = ac_build_scan(ctx, op, result, identity);
return ac_build_wwm(ctx, result);
}
@@ -3305,175 +3432,6 @@ ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op, unsign
}
}
/**
* "Top half" of a scan that reduces per-wave values across an entire
* workgroup.
*
* The source value must be present in the highest lane of the wave, and the
* highest lane must be live.
*/
void
ac_build_wg_wavescan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
if (ws->maxwaves <= 1)
return;
const LLVMValueRef i32_63 = LLVMConstInt(ctx->i32, 63, false);
LLVMBuilderRef builder = ctx->builder;
LLVMValueRef tid = ac_get_thread_id(ctx);
LLVMValueRef tmp;
tmp = LLVMBuildICmp(builder, LLVMIntEQ, tid, i32_63, "");
ac_build_ifcc(ctx, tmp, 1000);
LLVMBuildStore(builder, ws->src, LLVMBuildGEP(builder, ws->scratch, &ws->waveidx, 1, ""));
ac_build_endif(ctx, 1000);
}
/**
* "Bottom half" of a scan that reduces per-wave values across an entire
* workgroup.
*
* The caller must place a barrier between the top and bottom halves.
*/
void
ac_build_wg_wavescan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
const LLVMTypeRef type = LLVMTypeOf(ws->src);
const LLVMValueRef identity =
get_reduction_identity(ctx, ws->op, ac_get_type_size(type));
if (ws->maxwaves <= 1) {
ws->result_reduce = ws->src;
ws->result_inclusive = ws->src;
ws->result_exclusive = identity;
return;
}
assert(ws->maxwaves <= 32);
LLVMBuilderRef builder = ctx->builder;
LLVMValueRef tid = ac_get_thread_id(ctx);
LLVMBasicBlockRef bbs[2];
LLVMValueRef phivalues_scan[2];
LLVMValueRef tmp, tmp2;
bbs[0] = LLVMGetInsertBlock(builder);
phivalues_scan[0] = LLVMGetUndef(type);
if (ws->enable_reduce)
tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, ws->numwaves, "");
else if (ws->enable_inclusive)
tmp = LLVMBuildICmp(builder, LLVMIntULE, tid, ws->waveidx, "");
else
tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, ws->waveidx, "");
ac_build_ifcc(ctx, tmp, 1001);
{
tmp = LLVMBuildLoad(builder, LLVMBuildGEP(builder, ws->scratch, &tid, 1, ""), "");
ac_build_optimization_barrier(ctx, &tmp);
bbs[1] = LLVMGetInsertBlock(builder);
phivalues_scan[1] = ac_build_scan(ctx, ws->op, tmp, identity, ws->maxwaves);
}
ac_build_endif(ctx, 1001);
const LLVMValueRef scan = ac_build_phi(ctx, type, 2, phivalues_scan, bbs);
if (ws->enable_reduce) {
tmp = LLVMBuildSub(builder, ws->numwaves, ctx->i32_1, "");
ws->result_reduce = ac_build_readlane(ctx, scan, tmp);
}
if (ws->enable_inclusive)
ws->result_inclusive = ac_build_readlane(ctx, scan, ws->waveidx);
if (ws->enable_exclusive) {
tmp = LLVMBuildSub(builder, ws->waveidx, ctx->i32_1, "");
tmp = ac_build_readlane(ctx, scan, tmp);
tmp2 = LLVMBuildICmp(builder, LLVMIntEQ, ws->waveidx, ctx->i32_0, "");
ws->result_exclusive = LLVMBuildSelect(builder, tmp2, identity, tmp, "");
}
}
/**
* Inclusive scan of a per-wave value across an entire workgroup.
*
* This implies an s_barrier instruction.
*
* Unlike ac_build_inclusive_scan, the caller \em must ensure that all threads
* of the workgroup are live. (This requirement cannot easily be relaxed in a
* useful manner because of the barrier in the algorithm.)
*/
void
ac_build_wg_wavescan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
ac_build_wg_wavescan_top(ctx, ws);
ac_build_s_barrier(ctx);
ac_build_wg_wavescan_bottom(ctx, ws);
}
/**
* "Top half" of a scan that reduces per-thread values across an entire
* workgroup.
*
* All lanes must be active when this code runs.
*/
void
ac_build_wg_scan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
if (ws->enable_exclusive) {
ws->extra = ac_build_exclusive_scan(ctx, ws->src, ws->op);
if (LLVMTypeOf(ws->src) == ctx->i1 && ws->op == nir_op_iadd)
ws->src = LLVMBuildZExt(ctx->builder, ws->src, ctx->i32, "");
ws->src = ac_build_alu_op(ctx, ws->extra, ws->src, ws->op);
} else {
ws->src = ac_build_inclusive_scan(ctx, ws->src, ws->op);
}
bool enable_inclusive = ws->enable_inclusive;
bool enable_exclusive = ws->enable_exclusive;
ws->enable_inclusive = false;
ws->enable_exclusive = ws->enable_exclusive || enable_inclusive;
ac_build_wg_wavescan_top(ctx, ws);
ws->enable_inclusive = enable_inclusive;
ws->enable_exclusive = enable_exclusive;
}
/**
* "Bottom half" of a scan that reduces per-thread values across an entire
* workgroup.
*
* The caller must place a barrier between the top and bottom halves.
*/
void
ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
bool enable_inclusive = ws->enable_inclusive;
bool enable_exclusive = ws->enable_exclusive;
ws->enable_inclusive = false;
ws->enable_exclusive = ws->enable_exclusive || enable_inclusive;
ac_build_wg_wavescan_bottom(ctx, ws);
ws->enable_inclusive = enable_inclusive;
ws->enable_exclusive = enable_exclusive;
/* ws->result_reduce is already the correct value */
if (ws->enable_inclusive)
ws->result_inclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->src, ws->op);
if (ws->enable_exclusive)
ws->result_exclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->extra, ws->op);
}
/**
* A scan that reduces per-thread values across an entire workgroup.
*
* The caller must ensure that all lanes are active when this code runs
* (WWM is insufficient!), because there is an implied barrier.
*/
void
ac_build_wg_scan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)
{
ac_build_wg_scan_top(ctx, ws);
ac_build_s_barrier(ctx);
ac_build_wg_scan_bottom(ctx, ws);
}
LLVMValueRef
ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src,
unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)

View File

@@ -34,12 +34,14 @@
extern "C" {
#endif
#define HAVE_32BIT_POINTERS (HAVE_LLVM >= 0x0700)
enum {
AC_ADDR_SPACE_FLAT = 0, /* Slower than global. */
AC_ADDR_SPACE_FLAT = HAVE_LLVM >= 0x0700 ? 0 : 4, /* Slower than global. */
AC_ADDR_SPACE_GLOBAL = 1,
AC_ADDR_SPACE_GDS = 2,
AC_ADDR_SPACE_GDS = HAVE_LLVM >= 0x0700 ? 2 : 5,
AC_ADDR_SPACE_LDS = 3,
AC_ADDR_SPACE_CONST = 4, /* Global allowing SMEM. */
AC_ADDR_SPACE_CONST = HAVE_LLVM >= 0x0700 ? 4 : 2, /* Global allowing SMEM. */
AC_ADDR_SPACE_CONST_32BIT = 6, /* same as CONST, but the pointer type has 32 bits */
};
@@ -126,7 +128,6 @@ unsigned ac_get_type_size(LLVMTypeRef type);
LLVMTypeRef ac_to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
LLVMValueRef ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v);
LLVMValueRef ac_to_integer_or_pointer(struct ac_llvm_context *ctx, LLVMValueRef v);
LLVMTypeRef ac_to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
LLVMValueRef ac_to_float(struct ac_llvm_context *ctx, LLVMValueRef v);
@@ -231,11 +232,6 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
LLVMValueRef attr_number,
LLVMValueRef params);
LLVMValueRef
ac_build_gep_ptr(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
LLVMValueRef index);
LLVMValueRef
ac_build_gep0(struct ac_llvm_context *ctx,
LLVMValueRef base_ptr,
@@ -493,7 +489,6 @@ void ac_build_continue(struct ac_llvm_context *ctx);
void ac_build_else(struct ac_llvm_context *ctx, int lable_id);
void ac_build_endif(struct ac_llvm_context *ctx, int lable_id);
void ac_build_endloop(struct ac_llvm_context *ctx, int lable_id);
void ac_build_ifcc(struct ac_llvm_context *ctx, LLVMValueRef cond, int label_id);
void ac_build_if(struct ac_llvm_context *ctx, LLVMValueRef value,
int lable_id);
void ac_build_uif(struct ac_llvm_context *ctx, LLVMValueRef value,
@@ -537,42 +532,6 @@ ac_build_exclusive_scan(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op
LLVMValueRef
ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_op op, unsigned cluster_size);
/**
* Common arguments for a scan/reduce operation that accumulates per-wave
* values across an entire workgroup, while respecting the order of waves.
*/
struct ac_wg_scan {
bool enable_reduce;
bool enable_exclusive;
bool enable_inclusive;
nir_op op;
LLVMValueRef src; /* clobbered! */
LLVMValueRef result_reduce;
LLVMValueRef result_exclusive;
LLVMValueRef result_inclusive;
LLVMValueRef extra;
LLVMValueRef waveidx;
LLVMValueRef numwaves; /* only needed for "reduce" operations */
/* T addrspace(LDS) pointer to the same type as value, at least maxwaves entries */
LLVMValueRef scratch;
unsigned maxwaves;
};
void
ac_build_wg_wavescan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
void
ac_build_wg_wavescan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
void
ac_build_wg_wavescan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
void
ac_build_wg_scan_top(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
void
ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
void
ac_build_wg_scan(struct ac_llvm_context *ctx, struct ac_wg_scan *ws);
LLVMValueRef
ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src,
unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3);

View File

@@ -39,6 +39,9 @@
#include <llvm/Transforms/IPO.h>
#include <llvm/IR/LegacyPassManager.h>
#if HAVE_LLVM < 0x0700
#include "llvm/Support/raw_ostream.h"
#endif
void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)
{
@@ -129,7 +132,9 @@ struct ac_compiler_passes *ac_create_llvm_passes(LLVMTargetMachineRef tm)
llvm::TargetMachine *TM = reinterpret_cast<llvm::TargetMachine*>(tm);
if (TM->addPassesToEmitFile(p->passmgr, p->ostream,
#if HAVE_LLVM >= 0x0700
nullptr,
#endif
llvm::TargetMachine::CGFT_ObjectFile)) {
fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n");
delete p;
@@ -165,5 +170,7 @@ void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr)
void ac_enable_global_isel(LLVMTargetMachineRef tm)
{
#if HAVE_LLVM >= 0x0700
reinterpret_cast<llvm::TargetMachine*>(tm)->setGlobalISel(true);
#endif
}

View File

@@ -30,7 +30,9 @@
#include <llvm-c/Support.h>
#include <llvm-c/Transforms/IPO.h>
#include <llvm-c/Transforms/Scalar.h>
#if HAVE_LLVM >= 0x0700
#include <llvm-c/Transforms/Utils.h>
#endif
#include "c11/threads.h"
#include "gallivm/lp_bld_misc.h"
#include "util/u_math.h"
@@ -130,11 +132,11 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_RAVEN:
return "gfx902";
case CHIP_VEGA12:
return "gfx904";
return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
case CHIP_VEGA20:
return "gfx906";
return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
case CHIP_RAVEN2:
return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
return "gfx902"; /* TODO: use gfx909 when it's available */
default:
return "";
}
@@ -151,8 +153,7 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
LLVMTargetRef target = ac_get_llvm_target(triple);
snprintf(features, sizeof(features),
"+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
@@ -301,6 +302,7 @@ ac_count_scratch_private_memory(LLVMValueRef function)
bool
ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
bool okay_to_leak_target_library_info,
enum radeon_family family,
enum ac_target_machine_options tm_options)
{
@@ -321,10 +323,12 @@ ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
goto fail;
}
if (okay_to_leak_target_library_info || (HAVE_LLVM >= 0x0700)) {
compiler->target_library_info =
ac_create_target_library_info(triple);
if (!compiler->target_library_info)
goto fail;
}
compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
tm_options & AC_TM_CHECK_IR);
@@ -342,8 +346,11 @@ ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
{
if (compiler->passmgr)
LLVMDisposePassManager(compiler->passmgr);
#if HAVE_LLVM >= 0x0700
/* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
if (compiler->target_library_info)
ac_dispose_target_library_info(compiler->target_library_info);
#endif
if (compiler->low_opt_tm)
LLVMDisposeTargetMachine(compiler->low_opt_tm);
if (compiler->tm)

View File

@@ -134,6 +134,7 @@ void ac_init_llvm_once(void);
bool ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
bool okay_to_leak_target_library_info,
enum radeon_family family,
enum ac_target_machine_options tm_options);
void ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler);

View File

@@ -270,9 +270,8 @@ static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
{
LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
ctx->i32_0, "");
return LLVMBuildSelect(ctx->builder, v,
ac_to_integer_or_pointer(ctx, src1),
ac_to_integer_or_pointer(ctx, src2), "");
return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
ac_to_integer(ctx, src2), "");
}
static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
@@ -429,12 +428,12 @@ static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
{
LLVMValueRef result;
if (HAVE_LLVM >= 0x0800) {
if (HAVE_LLVM < 0x0700) {
LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
} else {
/* FIXME: LLVM 7+ returns incorrect result when count is 0.
/* FIXME: LLVM 7 returns incorrect result when count is 0.
* https://bugs.freedesktop.org/show_bug.cgi?id=107276
*/
LLVMValueRef zero = ctx->i32_0;
@@ -687,34 +686,34 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
LLVMTypeOf(src[0]), ""),
"");
break;
case nir_op_ilt32:
case nir_op_ilt:
result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
break;
case nir_op_ine32:
case nir_op_ine:
result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
break;
case nir_op_ieq32:
case nir_op_ieq:
result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
break;
case nir_op_ige32:
case nir_op_ige:
result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
break;
case nir_op_ult32:
case nir_op_ult:
result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
break;
case nir_op_uge32:
case nir_op_uge:
result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
break;
case nir_op_feq32:
case nir_op_feq:
result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]);
break;
case nir_op_fne32:
case nir_op_fne:
result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
break;
case nir_op_flt32:
case nir_op_flt:
result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]);
break;
case nir_op_fge32:
case nir_op_fge:
result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]);
break;
case nir_op_fabs:
@@ -916,7 +915,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
else
result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
break;
case nir_op_b32csel:
case nir_op_bcsel:
result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
break;
case nir_op_find_lsb:
@@ -941,20 +940,16 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
src[1] = ac_to_integer(&ctx->ac, src[1]);
result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
break;
case nir_op_b2f16:
case nir_op_b2f32:
case nir_op_b2f64:
case nir_op_b2f:
result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
break;
case nir_op_f2b32:
case nir_op_f2b:
result = emit_f2b(&ctx->ac, src[0]);
break;
case nir_op_b2i16:
case nir_op_b2i32:
case nir_op_b2i64:
case nir_op_b2i:
result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
break;
case nir_op_i2b32:
case nir_op_i2b:
src[0] = ac_to_integer(&ctx->ac, src[0]);
result = emit_i2b(&ctx->ac, src[0]);
break;
@@ -1100,7 +1095,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
if (result) {
assert(instr->dest.dest.is_ssa);
result = ac_to_integer_or_pointer(&ctx->ac, result);
result = ac_to_integer(&ctx->ac, result);
ctx->ssa_defs[instr->dest.dest.ssa.index] = result;
}
}
@@ -1463,30 +1458,6 @@ static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueR
}
}
static unsigned get_cache_policy(struct ac_nir_context *ctx,
enum gl_access_qualifier access,
bool may_store_unaligned,
bool writeonly_memory)
{
unsigned cache_policy = 0;
/* SI has a TC L1 bug causing corruption of 8bit/16bit stores. All
* store opcodes not aligned to a dword are affected. The only way to
* get unaligned stores is through shader images.
*/
if (((may_store_unaligned && ctx->ac.chip_class == SI) ||
/* If this is write-only, don't keep data in L1 to prevent
* evicting L1 cache lines that may be needed by other
* instructions.
*/
writeonly_memory ||
access & (ACCESS_COHERENT | ACCESS_VOLATILE))) {
cache_policy |= ac_glc;
}
return cache_policy;
}
static void visit_store_ssbo(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
@@ -1495,9 +1466,10 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
int elem_size_bytes = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 8;
unsigned writemask = nir_intrinsic_write_mask(instr);
enum gl_access_qualifier access = nir_intrinsic_access(instr);
bool writeonly_memory = access & ACCESS_NON_READABLE;
unsigned cache_policy = get_cache_policy(ctx, access, false, writeonly_memory);
LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
LLVMValueRef glc = ctx->ac.i1false;
if (access & (ACCESS_VOLATILE | ACCESS_COHERENT))
glc = ctx->ac.i1true;
LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
get_src(ctx, instr->src[1]), true);
@@ -1653,8 +1625,10 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
int elem_size_bytes = instr->dest.ssa.bit_size / 8;
int num_components = instr->num_components;
enum gl_access_qualifier access = nir_intrinsic_access(instr);
unsigned cache_policy = get_cache_policy(ctx, access, false, false);
LLVMValueRef glc = (cache_policy & ac_glc) ? ctx->ac.i1true : ctx->ac.i1false;
LLVMValueRef glc = ctx->ac.i1false;
if (access & (ACCESS_VOLATILE | ACCESS_COHERENT))
glc = ctx->ac.i1true;
LLVMValueRef offset = get_src(ctx, instr->src[1]);
LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
@@ -1667,7 +1641,7 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
LLVMValueRef results[4];
for (int i = 0; i < num_components;) {
int num_elems = num_components - i;
if (elem_size_bytes < 4 && nir_intrinsic_align(instr) % 4 != 0)
if (elem_size_bytes < 4)
num_elems = 1;
if (num_elems * elem_size_bytes > 16)
num_elems = 16 / elem_size_bytes;
@@ -1884,36 +1858,23 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
LLVMValueRef values[8];
int idx = 0;
int idx = var->data.driver_location;
int ve = instr->dest.ssa.num_components;
unsigned comp = 0;
unsigned comp = var->data.location_frac;
LLVMValueRef indir_index;
LLVMValueRef ret;
unsigned const_index;
unsigned stride = 4;
int mode = nir_var_mem_shared;
if (var) {
unsigned stride = var->data.compact ? 1 : 4;
bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
var->data.mode == nir_var_shader_in;
idx = var->data.driver_location;
comp = var->data.location_frac;
mode = var->data.mode;
get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), vs_in, NULL, NULL,
&const_index, &indir_index);
if (var->data.compact) {
stride = 1;
const_index += comp;
comp = 0;
}
}
if (instr->dest.ssa.bit_size == 64)
ve *= 2;
switch (mode) {
switch (var->data.mode) {
case nir_var_shader_in:
if (ctx->stage == MESA_SHADER_TESS_CTRL ||
ctx->stage == MESA_SHADER_TESS_EVAL) {
@@ -1950,7 +1911,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
}
break;
case nir_var_function_temp:
case nir_var_local:
for (unsigned chan = 0; chan < ve; chan++) {
if (indir_index) {
unsigned count = glsl_count_attribute_slots(
@@ -1968,7 +1929,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
}
}
break;
case nir_var_mem_shared: {
case nir_var_shared: {
LLVMValueRef address = get_src(ctx, instr->src[0]);
LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
return LLVMBuildBitCast(ctx->ac.builder, val,
@@ -2010,28 +1971,18 @@ static void
visit_store_var(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
nir_variable *var = nir_deref_instr_get_variable(deref);
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
LLVMValueRef temp_ptr, value;
int idx = 0;
unsigned comp = 0;
int idx = var->data.driver_location;
unsigned comp = var->data.location_frac;
LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[1]));
int writemask = instr->const_index[0];
LLVMValueRef indir_index;
unsigned const_index;
if (var) {
get_deref_offset(ctx, deref, false,
get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), false,
NULL, NULL, &const_index, &indir_index);
idx = var->data.driver_location;
comp = var->data.location_frac;
if (var->data.compact) {
const_index += comp;
comp = 0;
}
}
if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
@@ -2044,7 +1995,7 @@ visit_store_var(struct ac_nir_context *ctx,
writemask = writemask << comp;
switch (deref->mode) {
switch (var->data.mode) {
case nir_var_shader_out:
if (ctx->stage == MESA_SHADER_TESS_CTRL) {
@@ -2053,8 +2004,8 @@ visit_store_var(struct ac_nir_context *ctx,
unsigned const_index = 0;
const bool is_patch = var->data.patch;
get_deref_offset(ctx, deref, false, NULL,
is_patch ? NULL : &vertex_index,
get_deref_offset(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr),
false, NULL, is_patch ? NULL : &vertex_index,
&const_index, &indir_index);
ctx->abi->store_tcs_outputs(ctx->abi, var,
@@ -2092,7 +2043,7 @@ visit_store_var(struct ac_nir_context *ctx,
}
}
break;
case nir_var_function_temp:
case nir_var_local:
for (unsigned chan = 0; chan < 8; chan++) {
if (!(writemask & (1 << chan)))
continue;
@@ -2117,7 +2068,7 @@ visit_store_var(struct ac_nir_context *ctx,
}
}
break;
case nir_var_mem_shared: {
case nir_var_shared: {
int writemask = instr->const_index[0];
LLVMValueRef address = get_src(ctx, instr->src[0]);
LLVMValueRef val = get_src(ctx, instr->src[1]);
@@ -2247,10 +2198,10 @@ static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
return sample_index;
}
static nir_deref_instr *get_image_deref(const nir_intrinsic_instr *instr)
static nir_variable *get_image_variable(const nir_intrinsic_instr *instr)
{
assert(instr->src[0].is_ssa);
return nir_instr_as_deref(instr->src[0].ssa->parent_instr);
return nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
}
static LLVMValueRef get_image_descriptor(struct ac_nir_context *ctx,
@@ -2265,7 +2216,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr,
struct ac_image_args *args)
{
const struct glsl_type *type = get_image_deref(instr)->type;
const struct glsl_type *type = glsl_without_array(get_image_variable(instr)->type);
LLVMValueRef src0 = get_src(ctx, instr->src[1]);
LLVMValueRef masks[] = {
@@ -2284,7 +2235,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
count = image_type_to_components_count(dim, is_array);
if (is_ms && instr->intrinsic == nir_intrinsic_image_deref_load) {
if (is_ms) {
LLVMValueRef fmask_load_address[3];
int chan;
@@ -2374,13 +2325,10 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMValueRef res;
const nir_deref_instr *image_deref = get_image_deref(instr);
const struct glsl_type *type = image_deref->type;
const nir_variable *var = nir_deref_instr_get_variable(image_deref);
struct ac_image_args args = {};
const nir_variable *var = get_image_variable(instr);
const struct glsl_type *type = var->type;
args.cache_policy =
get_cache_policy(ctx, var->data.image.access, false, false);
type = glsl_without_array(type);
const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
if (dim == GLSL_SAMPLER_DIM_BUF) {
@@ -2392,16 +2340,16 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
ctx->ac.i32_0, "");
/* TODO: set "can_speculate" when OpenGL needs it. */
/* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
ctx->ac.i32_0, num_channels,
!!(args.cache_policy & ac_glc),
false);
false, false);
res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
res = ac_trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
res = ac_to_integer(&ctx->ac, res);
} else {
struct ac_image_args args = {};
args.opcode = ac_image_load;
get_image_coords(ctx, instr, &args);
args.resource = get_image_descriptor(ctx, instr, AC_DESC_IMAGE, false);
@@ -2409,6 +2357,8 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
glsl_sampler_type_is_array(type));
args.dmask = 15;
args.attributes = AC_FUNC_ATTR_READONLY;
if (var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT))
args.cache_policy |= ac_glc;
res = ac_build_image_opcode(&ctx->ac, &args);
}
@@ -2419,15 +2369,13 @@ static void visit_image_store(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
LLVMValueRef params[8];
const nir_deref_instr *image_deref = get_image_deref(instr);
const struct glsl_type *type = image_deref->type;
const nir_variable *var = nir_deref_instr_get_variable(image_deref);
const nir_variable *var = get_image_variable(instr);
const struct glsl_type *type = glsl_without_array(var->type);
const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
bool writeonly_memory = var->data.image.access & ACCESS_NON_READABLE;
struct ac_image_args args = {};
args.cache_policy = get_cache_policy(ctx, var->data.image.access, true,
writeonly_memory);
LLVMValueRef glc = ctx->ac.i1false;
bool force_glc = ctx->ac.chip_class == SI;
if (force_glc)
glc = ctx->ac.i1true;
if (dim == GLSL_SAMPLER_DIM_BUF) {
char name[48];
@@ -2445,19 +2393,14 @@ static void visit_image_store(struct ac_nir_context *ctx,
ctx->ac.i32_0, ""); /* vindex */
params[3] = ctx->ac.i32_0; /* voffset */
snprintf(name, sizeof(name), "%s.%s",
HAVE_LLVM >= 0x800 ? "llvm.amdgcn.struct.buffer.store.format"
: "llvm.amdgcn.buffer.store.format",
"llvm.amdgcn.buffer.store.format",
types[CLAMP(src_channels, 1, 3) - 1]);
if (HAVE_LLVM >= 0x800) {
params[4] = ctx->ac.i32_0; /* soffset */
params[5] = (args.cache_policy & ac_glc) ? ctx->ac.i32_1 : ctx->ac.i32_0;
} else {
params[4] = LLVMConstInt(ctx->ac.i1, !!(args.cache_policy & ac_glc), 0);
params[4] = glc; /* glc */
params[5] = ctx->ac.i1false; /* slc */
}
ac_build_intrinsic(&ctx->ac, name, ctx->ac.voidt, params, 6, 0);
} else {
struct ac_image_args args = {};
args.opcode = ac_image_store;
args.data[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[3]));
get_image_coords(ctx, instr, &args);
@@ -2465,6 +2408,8 @@ static void visit_image_store(struct ac_nir_context *ctx,
args.dim = get_ac_image_dim(&ctx->ac, glsl_get_sampler_dim(type),
glsl_sampler_type_is_array(type));
args.dmask = 15;
if (force_glc || (var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT)))
args.cache_policy |= ac_glc;
ac_build_image_opcode(&ctx->ac, &args);
}
@@ -2476,12 +2421,13 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
{
LLVMValueRef params[7];
int param_count = 0;
const struct glsl_type *type = get_image_deref(instr)->type;
const nir_variable *var = get_image_variable(instr);
bool cmpswap = instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap;
const char *atomic_name;
char intrinsic_name[64];
char intrinsic_name[41];
enum ac_atomic_op atomic_subop;
const struct glsl_type *type = glsl_without_array(var->type);
MAYBE_UNUSED int length;
bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
@@ -2532,18 +2478,10 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
ctx->ac.i32_0, ""); /* vindex */
params[param_count++] = ctx->ac.i32_0; /* voffset */
if (HAVE_LLVM >= 0x800) {
params[param_count++] = ctx->ac.i32_0; /* soffset */
params[param_count++] = ctx->ac.i32_0; /* slc */
length = snprintf(intrinsic_name, sizeof(intrinsic_name),
"llvm.amdgcn.struct.buffer.atomic.%s.i32", atomic_name);
} else {
params[param_count++] = ctx->ac.i1false; /* slc */
length = snprintf(intrinsic_name, sizeof(intrinsic_name),
"llvm.amdgcn.buffer.atomic.%s", atomic_name);
}
assert(length < sizeof(intrinsic_name));
return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32,
@@ -2567,7 +2505,8 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
const struct glsl_type *type = get_image_deref(instr)->type;
const nir_variable *var = get_image_variable(instr);
const struct glsl_type *type = glsl_without_array(var->type);
struct ac_image_args args = { 0 };
args.dim = get_ac_sampler_dim(&ctx->ac, glsl_get_sampler_dim(type),
@@ -2585,7 +2524,8 @@ static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMValueRef res;
const struct glsl_type *type = get_image_deref(instr)->type;
const nir_variable *var = get_image_variable(instr);
const struct glsl_type *type = glsl_without_array(var->type);
if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
return get_buffer_size(ctx, get_image_descriptor(ctx, instr, AC_DESC_BUFFER, false), true);
@@ -2938,10 +2878,12 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
}
LLVMValueRef attrib_idx = ctx->ac.i32_0;
LLVMValueRef array_idx = ctx->ac.i32_0;
while(deref_instr->deref_type != nir_deref_type_var) {
if (deref_instr->deref_type == nir_deref_type_array) {
unsigned array_size = glsl_count_attribute_slots(deref_instr->type, false);
unsigned array_size = glsl_get_aoa_size(deref_instr->type);
if (!array_size)
array_size = 1;
LLVMValueRef offset;
nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
@@ -2954,26 +2896,23 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
LLVMConstInt(ctx->ac.i32, array_size, false), "");
}
attrib_idx = LLVMBuildAdd(ctx->ac.builder, attrib_idx, offset, "");
array_idx = LLVMBuildAdd(ctx->ac.builder, array_idx, offset, "");
deref_instr = nir_src_as_deref(deref_instr->parent);
} else if (deref_instr->deref_type == nir_deref_type_struct) {
LLVMValueRef offset;
unsigned sidx = deref_instr->strct.index;
deref_instr = nir_src_as_deref(deref_instr->parent);
offset = LLVMConstInt(ctx->ac.i32, glsl_get_record_location_offset(deref_instr->type, sidx), false);
attrib_idx = LLVMBuildAdd(ctx->ac.builder, attrib_idx, offset, "");
} else {
unreachable("Unsupported deref type");
}
}
unsigned attrib_size = glsl_count_attribute_slots(var->type, false);
unsigned input_array_size = glsl_get_aoa_size(var->type);
if (!input_array_size)
input_array_size = 1;
for (chan = 0; chan < 4; chan++) {
LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->ac.f32, attrib_size));
LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->ac.f32, input_array_size));
LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
for (unsigned idx = 0; idx < attrib_size; ++idx) {
for (unsigned idx = 0; idx < input_array_size; ++idx) {
LLVMValueRef v, attr_number;
attr_number = LLVMConstInt(ctx->ac.i32, input_base + idx, false);
@@ -2996,7 +2935,7 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
LLVMConstInt(ctx->ac.i32, idx, false), "");
}
result[chan] = LLVMBuildExtractElement(ctx->ac.builder, gather, attrib_idx, "");
result[chan] = LLVMBuildExtractElement(ctx->ac.builder, gather, array_idx, "");
}
return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
@@ -3319,27 +3258,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
}
}
static LLVMValueRef get_bindless_index_from_uniform(struct ac_nir_context *ctx,
unsigned base_index,
unsigned constant_index,
LLVMValueRef dynamic_index)
{
LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, base_index * 4, 0);
LLVMValueRef index = LLVMBuildAdd(ctx->ac.builder, dynamic_index,
LLVMConstInt(ctx->ac.i32, constant_index, 0), "");
/* Bindless uniforms are 64bit so multiple index by 8 */
index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->ac.i32, 8, 0), "");
offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
LLVMValueRef ubo_index = ctx->abi->load_ubo(ctx->abi, ctx->ac.i32_0);
LLVMValueRef ret = ac_build_buffer_load(&ctx->ac, ubo_index, 1, NULL, offset,
NULL, 0, false, false, true, true);
return LLVMBuildBitCast(ctx->ac.builder, ret, ctx->ac.i32, "");
}
static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
nir_deref_instr *deref_instr,
enum ac_descriptor_type desc_type,
@@ -3358,11 +3276,11 @@ static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
base_index = tex_instr->sampler_index;
} else {
while(deref_instr->deref_type != nir_deref_type_var) {
if (deref_instr->deref_type == nir_deref_type_array) {
unsigned array_size = glsl_get_aoa_size(deref_instr->type);
if (!array_size)
array_size = 1;
assert(deref_instr->deref_type == nir_deref_type_array);
nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
if (const_value) {
constant_index += array_size * const_value->u32[0];
@@ -3379,27 +3297,8 @@ static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
}
deref_instr = nir_src_as_deref(deref_instr->parent);
} else if (deref_instr->deref_type == nir_deref_type_struct) {
unsigned sidx = deref_instr->strct.index;
deref_instr = nir_src_as_deref(deref_instr->parent);
constant_index += glsl_get_record_location_offset(deref_instr->type, sidx);
} else {
unreachable("Unsupported deref type");
}
}
descriptor_set = deref_instr->var->data.descriptor_set;
if (deref_instr->var->data.bindless) {
/* For now just assert on unhandled variable types */
assert(deref_instr->var->data.mode == nir_var_uniform);
base_index = deref_instr->var->data.driver_location;
bindless = true;
index = index ? index : ctx->ac.i32_0;
index = get_bindless_index_from_uniform(ctx, base_index,
constant_index, index);
} else
base_index = deref_instr->var->data.binding;
}
@@ -3833,77 +3732,10 @@ static void visit_jump(struct ac_llvm_context *ctx,
}
}
static LLVMTypeRef
glsl_base_to_llvm_type(struct ac_llvm_context *ac,
enum glsl_base_type type)
{
switch (type) {
case GLSL_TYPE_INT:
case GLSL_TYPE_UINT:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_SUBROUTINE:
return ac->i32;
case GLSL_TYPE_INT16:
case GLSL_TYPE_UINT16:
return ac->i16;
case GLSL_TYPE_FLOAT:
return ac->f32;
case GLSL_TYPE_FLOAT16:
return ac->f16;
case GLSL_TYPE_INT64:
case GLSL_TYPE_UINT64:
return ac->i64;
case GLSL_TYPE_DOUBLE:
return ac->f64;
default:
unreachable("unknown GLSL type");
}
}
static LLVMTypeRef
glsl_to_llvm_type(struct ac_llvm_context *ac,
const struct glsl_type *type)
{
if (glsl_type_is_scalar(type)) {
return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
}
if (glsl_type_is_vector(type)) {
return LLVMVectorType(
glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
glsl_get_vector_elements(type));
}
if (glsl_type_is_matrix(type)) {
return LLVMArrayType(
glsl_to_llvm_type(ac, glsl_get_column_type(type)),
glsl_get_matrix_columns(type));
}
if (glsl_type_is_array(type)) {
return LLVMArrayType(
glsl_to_llvm_type(ac, glsl_get_array_element(type)),
glsl_get_length(type));
}
assert(glsl_type_is_struct(type));
LLVMTypeRef member_types[glsl_get_length(type)];
for (unsigned i = 0; i < glsl_get_length(type); i++) {
member_types[i] =
glsl_to_llvm_type(ac,
glsl_get_struct_field(type, i));
}
return LLVMStructTypeInContext(ac->context, member_types,
glsl_get_length(type), false);
}
static void visit_deref(struct ac_nir_context *ctx,
nir_deref_instr *instr)
{
if (instr->mode != nir_var_mem_shared)
if (instr->mode != nir_var_shared)
return;
LLVMValueRef result = NULL;
@@ -3921,27 +3753,6 @@ static void visit_deref(struct ac_nir_context *ctx,
result = ac_build_gep0(&ctx->ac, get_src(ctx, instr->parent),
get_src(ctx, instr->arr.index));
break;
case nir_deref_type_ptr_as_array:
result = ac_build_gep_ptr(&ctx->ac, get_src(ctx, instr->parent),
get_src(ctx, instr->arr.index));
break;
case nir_deref_type_cast: {
result = get_src(ctx, instr->parent);
LLVMTypeRef pointee_type = glsl_to_llvm_type(&ctx->ac, instr->type);
LLVMTypeRef type = LLVMPointerType(pointee_type, AC_ADDR_SPACE_LDS);
if (LLVMTypeOf(result) != type) {
if (LLVMGetTypeKind(LLVMTypeOf(result)) == LLVMVectorTypeKind) {
result = LLVMBuildBitCast(ctx->ac.builder, result,
type, "");
} else {
result = LLVMBuildIntToPtr(ctx->ac.builder, result,
type, "");
}
}
break;
}
default:
unreachable("Unhandled deref_instr deref type");
}
@@ -4090,6 +3901,68 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
}
}
static LLVMTypeRef
glsl_base_to_llvm_type(struct ac_llvm_context *ac,
enum glsl_base_type type)
{
switch (type) {
case GLSL_TYPE_INT:
case GLSL_TYPE_UINT:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_SUBROUTINE:
return ac->i32;
case GLSL_TYPE_FLOAT: /* TODO handle mediump */
return ac->f32;
case GLSL_TYPE_INT64:
case GLSL_TYPE_UINT64:
return ac->i64;
case GLSL_TYPE_DOUBLE:
return ac->f64;
default:
unreachable("unknown GLSL type");
}
}
static LLVMTypeRef
glsl_to_llvm_type(struct ac_llvm_context *ac,
const struct glsl_type *type)
{
if (glsl_type_is_scalar(type)) {
return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
}
if (glsl_type_is_vector(type)) {
return LLVMVectorType(
glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
glsl_get_vector_elements(type));
}
if (glsl_type_is_matrix(type)) {
return LLVMArrayType(
glsl_to_llvm_type(ac, glsl_get_column_type(type)),
glsl_get_matrix_columns(type));
}
if (glsl_type_is_array(type)) {
return LLVMArrayType(
glsl_to_llvm_type(ac, glsl_get_array_element(type)),
glsl_get_length(type));
}
assert(glsl_type_is_struct(type));
LLVMTypeRef member_types[glsl_get_length(type)];
for (unsigned i = 0; i < glsl_get_length(type); i++) {
member_types[i] =
glsl_to_llvm_type(ac,
glsl_get_struct_field(type, i));
}
return LLVMStructTypeInContext(ac->context, member_types,
glsl_get_length(type), false);
}
static void
setup_locals(struct ac_nir_context *ctx,
struct nir_function *func)
@@ -4159,13 +4032,13 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
setup_locals(&ctx, func);
if (gl_shader_stage_is_compute(nir->info.stage))
if (nir->info.stage == MESA_SHADER_COMPUTE)
setup_shared(&ctx, nir);
visit_cf_list(&ctx, &func->impl->body);
phi_post_pass(&ctx);
if (!gl_shader_stage_is_compute(nir->info.stage))
if (nir->info.stage != MESA_SHADER_COMPUTE)
ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
ctx.abi->outputs);
@@ -4208,168 +4081,7 @@ ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
* See the following thread for more details of the problem:
* https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
*/
indirect_mask |= nir_var_function_temp;
indirect_mask |= nir_var_local;
nir_lower_indirect_derefs(nir, indirect_mask);
}
static unsigned
get_inst_tessfactor_writemask(nir_intrinsic_instr *intrin)
{
if (intrin->intrinsic != nir_intrinsic_store_deref)
return 0;
nir_variable *var =
nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[0]));
if (var->data.mode != nir_var_shader_out)
return 0;
unsigned writemask = 0;
const int location = var->data.location;
unsigned first_component = var->data.location_frac;
unsigned num_comps = intrin->dest.ssa.num_components;
if (location == VARYING_SLOT_TESS_LEVEL_INNER)
writemask = ((1 << (num_comps + 1)) - 1) << first_component;
else if (location == VARYING_SLOT_TESS_LEVEL_OUTER)
writemask = (((1 << (num_comps + 1)) - 1) << first_component) << 4;
return writemask;
}
static void
scan_tess_ctrl(nir_cf_node *cf_node, unsigned *upper_block_tf_writemask,
unsigned *cond_block_tf_writemask,
bool *tessfactors_are_def_in_all_invocs, bool is_nested_cf)
{
switch (cf_node->type) {
case nir_cf_node_block: {
nir_block *block = nir_cf_node_as_block(cf_node);
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if (intrin->intrinsic == nir_intrinsic_barrier) {
/* If we find a barrier in nested control flow put this in the
* too hard basket. In GLSL this is not possible but it is in
* SPIR-V.
*/
if (is_nested_cf) {
*tessfactors_are_def_in_all_invocs = false;
return;
}
/* The following case must be prevented:
* gl_TessLevelInner = ...;
* barrier();
* if (gl_InvocationID == 1)
* gl_TessLevelInner = ...;
*
* If you consider disjoint code segments separated by barriers, each
* such segment that writes tess factor channels should write the same
* channels in all codepaths within that segment.
*/
if (upper_block_tf_writemask || cond_block_tf_writemask) {
/* Accumulate the result: */
*tessfactors_are_def_in_all_invocs &=
!(*cond_block_tf_writemask & ~(*upper_block_tf_writemask));
/* Analyze the next code segment from scratch. */
*upper_block_tf_writemask = 0;
*cond_block_tf_writemask = 0;
}
} else
*upper_block_tf_writemask |= get_inst_tessfactor_writemask(intrin);
}
break;
}
case nir_cf_node_if: {
unsigned then_tessfactor_writemask = 0;
unsigned else_tessfactor_writemask = 0;
nir_if *if_stmt = nir_cf_node_as_if(cf_node);
foreach_list_typed(nir_cf_node, nested_node, node, &if_stmt->then_list) {
scan_tess_ctrl(nested_node, &then_tessfactor_writemask,
cond_block_tf_writemask,
tessfactors_are_def_in_all_invocs, true);
}
foreach_list_typed(nir_cf_node, nested_node, node, &if_stmt->else_list) {
scan_tess_ctrl(nested_node, &else_tessfactor_writemask,
cond_block_tf_writemask,
tessfactors_are_def_in_all_invocs, true);
}
if (then_tessfactor_writemask || else_tessfactor_writemask) {
/* If both statements write the same tess factor channels,
* we can say that the upper block writes them too.
*/
*upper_block_tf_writemask |= then_tessfactor_writemask &
else_tessfactor_writemask;
*cond_block_tf_writemask |= then_tessfactor_writemask |
else_tessfactor_writemask;
}
break;
}
case nir_cf_node_loop: {
nir_loop *loop = nir_cf_node_as_loop(cf_node);
foreach_list_typed(nir_cf_node, nested_node, node, &loop->body) {
scan_tess_ctrl(nested_node, cond_block_tf_writemask,
cond_block_tf_writemask,
tessfactors_are_def_in_all_invocs, true);
}
break;
}
default:
unreachable("unknown cf node type");
}
}
bool
ac_are_tessfactors_def_in_all_invocs(const struct nir_shader *nir)
{
assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
/* The pass works as follows:
* If all codepaths write tess factors, we can say that all
* invocations define tess factors.
*
* Each tess factor channel is tracked separately.
*/
unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
/* Initial value = true. Here the pass will accumulate results from
* multiple segments surrounded by barriers. If tess factors aren't
* written at all, it's a shader bug and we don't care if this will be
* true.
*/
bool tessfactors_are_def_in_all_invocs = true;
nir_foreach_function(function, nir) {
if (function->impl) {
foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
scan_tess_ctrl(node, &main_block_tf_writemask,
&cond_block_tf_writemask,
&tessfactors_are_def_in_all_invocs,
false);
}
}
}
/* Accumulate the result for the last code segment separated by a
* barrier.
*/
if (main_block_tf_writemask || cond_block_tf_writemask) {
tessfactors_are_def_in_all_invocs &=
!(cond_block_tf_writemask & ~main_block_tf_writemask);
}
return tessfactors_are_def_in_all_invocs;
}

View File

@@ -47,8 +47,6 @@ static inline unsigned ac_llvm_reg_index_soa(unsigned index, unsigned chan)
void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
bool ac_are_tessfactors_def_in_all_invocs(const struct nir_shader *nir);
void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
struct nir_shader *nir);

View File

@@ -27,7 +27,7 @@
#include "ac_surface.h"
#include "amd_family.h"
#include "addrlib/src/amdgpu_asic_addr.h"
#include "addrlib/amdgpu_asic_addr.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
#include "util/u_atomic.h"
@@ -39,7 +39,7 @@
#include <amdgpu.h>
#include <amdgpu_drm.h>
#include "addrlib/inc/addrinterface.h"
#include "addrlib/addrinterface.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
@@ -1038,7 +1038,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
bool is_fmask, AddrSwizzleMode *swizzle_mode)
bool is_fmask, unsigned flags,
AddrSwizzleMode *swizzle_mode)
{
ADDR_E_RETURNCODE ret;
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
@@ -1063,6 +1064,16 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
sin.numSamples = in->numSamples;
sin.numFrags = in->numFrags;
if (flags & RADEON_SURF_SCANOUT) {
sin.preferredSwSet.sw_D = 1;
/* Raven only allows S for displayable surfaces with < 64 bpp, so
* allow it as fallback */
sin.preferredSwSet.sw_S = 1;
} else if (in->flags.depth || in->flags.stencil || is_fmask)
sin.preferredSwSet.sw_Z = 1;
else
sin.preferredSwSet.sw_S = 1;
if (is_fmask) {
sin.flags.display = 0;
sin.flags.color = 0;
@@ -1262,7 +1273,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
true, &fin.swizzleMode);
true, surf->flags,
&fin.swizzleMode);
if (ret != ADDR_OK)
return ret;
@@ -1412,13 +1424,11 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.bpp = surf->bpe * 8;
}
bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.color = is_color_surface &&
!(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
/* flags.texture currently refers to TC-compatible HTILE */
AddrSurfInfoIn.flags.texture = is_color_surface ||
AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
AddrSurfInfoIn.flags.opt4space = 1;
@@ -1466,7 +1476,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
}
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
false, &AddrSurfInfoIn.swizzleMode);
false, surf->flags,
&AddrSurfInfoIn.swizzleMode);
if (r)
return r;
break;
@@ -1502,7 +1513,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
if (!AddrSurfInfoIn.flags.depth) {
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
false, &AddrSurfInfoIn.swizzleMode);
false, surf->flags,
&AddrSurfInfoIn.swizzleMode);
if (r)
return r;
} else
@@ -1518,12 +1530,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
/* Query whether the surface is displayable. */
bool displayable = false;
if (!config->is_3d && !config->is_cube) {
r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
surf->bpe * 8, &displayable);
if (r)
return r;
}
surf->is_displayable = displayable;
switch (surf->u.gfx9.surf.swizzle_mode) {
@@ -1584,6 +1594,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
assert(0);
}
/* Temporary workaround to prevent VM faults and hangs. */
if (info->family == CHIP_VEGA12)
surf->fmask_size *= 8;
return 0;
}

View File

@@ -68,7 +68,6 @@ enum radeon_micro_mode {
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
#define RADEON_SURF_SHAREABLE (1 << 26)
#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
struct legacy_surf_level {
uint64_t offset;

View File

@@ -133,11 +133,11 @@
#define S_370_WR_ONE_ADDR(x) (((unsigned)(x) & 0x1) << 16)
#define S_370_DST_SEL(x) (((unsigned)(x) & 0xf) << 8)
#define V_370_MEM_MAPPED_REGISTER 0
#define V_370_MEM_GRBM 1 /* sync across GRBM */
#define V_370_MEMORY_SYNC 1
#define V_370_TC_L2 2
#define V_370_GDS 3
#define V_370_RESERVED 4
#define V_370_MEM 5 /* not on SI */
#define V_370_MEM_ASYNC 5
#define R_371_DST_ADDR_LO 0x371
#define R_372_DST_ADDR_HI 0x372
#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
@@ -211,14 +211,12 @@
#define PKT3_SET_SH_REG 0x76
#define PKT3_SET_SH_REG_OFFSET 0x77
#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */
#define PKT3_LOAD_CONST_RAM 0x80
#define PKT3_WRITE_CONST_RAM 0x81
#define PKT3_DUMP_CONST_RAM 0x83
#define PKT3_INCREMENT_CE_COUNTER 0x84
#define PKT3_INCREMENT_DE_COUNTER 0x85
#define PKT3_WAIT_ON_CE_COUNTER 0x86
#define PKT3_LOAD_CONTEXT_REG 0x9F /* new for VI */
#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
#define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
@@ -2437,9 +2435,6 @@
#define S_008F30_FILTER_MODE(x) (((unsigned)(x) & 0x03) << 29)
#define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03)
#define C_008F30_FILTER_MODE 0x9FFFFFFF
#define V_008F30_SQ_IMG_FILTER_MODE_BLEND 0x00
#define V_008F30_SQ_IMG_FILTER_MODE_MIN 0x01
#define V_008F30_SQ_IMG_FILTER_MODE_MAX 0x02
/* VI */
#define S_008F30_COMPAT_MODE(x) (((unsigned)(x) & 0x1) << 31)
#define G_008F30_COMPAT_MODE(x) (((x) >> 31) & 0x1)

View File

@@ -1,4 +1,4 @@
from __future__ import print_function, division, unicode_literals
from __future__ import print_function
CopyRight = '''
/*

View File

@@ -50,7 +50,6 @@ VULKAN_FILES := \
radv_meta_copy.c \
radv_meta_decompress.c \
radv_meta_fast_clear.c \
radv_meta_fmask_expand.c \
radv_meta_resolve.c \
radv_meta_resolve_cs.c \
radv_meta_resolve_fs.c \

View File

@@ -78,7 +78,6 @@ libradv_files = files(
'radv_meta_copy.c',
'radv_meta_decompress.c',
'radv_meta_fast_clear.c',
'radv_meta_fmask_expand.c',
'radv_meta_resolve.c',
'radv_meta_resolve_cs.c',
'radv_meta_resolve_fs.c',

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