VERSION: bump version for 19.2.7

docs: Add release notes for 19.2.7
radv: set writes_memory for global memory stores/atomics
2019-12-04 13:48:11 -08:00 · 2019-12-04 13:47:44 -08:00 · 2019-12-04 13:43:32 -08:00 · 2019-12-04 13:43:32 -08:00 · 2019-12-04 13:43:32 -08:00 · 2019-12-04 13:43:32 -08:00
49 changed files with 748 additions and 222 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-19.2.4
+19.2.7
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -27,3 +27,14 @@ bcd9224728dcb8d8fe4bcddc4bd9b2c36fcfe9dd
 869e32593a9096b845dd6106f8f86e1c41fac968
 a2c3c65a31de90fdb55f76f2894860dfbafe2043
 bb0c5c487e63e88acbb792f092dd8f392bad8540
+
+# This is reverted shortly after it was landed
+4432a2d14d80081d062f7939a950d65ea3a16eed
+
+# These aren't relevant for 19.2
+1a05811936dd8d0c3a367c6f00629624ef39d537
+911a8261419f48dcd756f78832fa5a5f4c5b8d93
+
+# This was manuall backported
+2afeed301010917c4eae55dcd2544f9d329df934
+4b392ced2d744fccffe95490ff57e6b41033c266
--- a/docs/relnotes/19.2.4.html
+++ b/docs/relnotes/19.2.4.html
@@ -35,7 +35,7 @@ depends on the particular driver being used.

 <h2>SHA256 checksum</h2>
 <pre>
-TBD.
+    09000a0f7dbbd82e193b81a8f1bf0c118eab7ca975c0329181968596e548e30f  mesa-19.2.4.tar.xz
 </pre>


--- a/docs/relnotes/19.2.5.html
+++ b/docs/relnotes/19.2.5.html
@@ -0,0 +1,115 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="content-type" content="text/html; charset=utf-8">
+<title>Mesa Release Notes</title>
+<link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+<h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.2.5 Release Notes / 2019-11-20</h1>
+
+<p>
+    Mesa 19.2.5 is a bug fix release which fixes bugs found since the 19.2.4 release.
+</p>
+<p>
+Mesa 19.2.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+<p>
+Mesa 19.2.5 implements the Vulkan 1.1 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+</p>
+
+<h2>SHA256 checksum</h2>
+<pre>
+    3d010a366b28d10bdd71e32091d8684baf1522e6466c5c5703667091b2108c8b  mesa-19.2.5.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<ul>
+    <li>None</li>
+</ul>
+
+<h2>Bug fixes</h2>
+
+<ul>
+    <li>HSW. Tropico 6 and SuperTuxKart have shadows flickering</li>
+    <li>glxgears segfaults on POWER / Xvnc</li>
+    <li>Cannot start Civ6 with AMD GPU on Linux</li>
+</ul>
+
+<h2>Changes</h2>
+
+<ul>
+    <p>Ben Crocker (1):</p>
+    <li>      llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders</li>
+    <p></p>
+    <p>Brian Paul (1):</p>
+    <li>      Call shmget() with permission 0600 instead of 0777</li>
+    <p></p>
+    <p>Caio Marcelo de Oliveira Filho (1):</p>
+    <li>      spirv: Don&#x27;t leak GS initialization to other stages</li>
+    <p></p>
+    <p>Danylo Piliaiev (1):</p>
+    <li>      i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround</li>
+    <p></p>
+    <p>Dylan Baker (2):</p>
+    <li>      docs: Add SHA256 sum for for 19.2.4</li>
+    <li>      cherry-ignore: Update for 19.2.4 cycle</li>
+    <p></p>
+    <p>Eric Engestrom (1):</p>
+    <li>      egl: fix _EGL_NATIVE_PLATFORM fallback</li>
+    <p></p>
+    <p>Ian Romanick (2):</p>
+    <li>      nir/algebraic: Add the ability to mark a replacement as exact</li>
+    <li>      nir/algebraic: Mark other comparison exact when removing a == a</li>
+    <p></p>
+    <p>Illia Iorin (1):</p>
+    <li>      mesa/main: Ignore filter state for MS texture completeness</li>
+    <p></p>
+    <p>Jason Ekstrand (1):</p>
+    <li>      anv: Stop bounds-checking pushed UBOs</li>
+    <p></p>
+    <p>Lepton Wu (1):</p>
+    <li>      gallium: dri2: Use index as plane number.</li>
+    <p></p>
+    <p>Lionel Landwerlin (3):</p>
+    <li>      anv: invalidate file descriptor of semaphore sync fd at vkQueueSubmit</li>
+    <li>      anv: remove list items on batch fini</li>
+    <li>      anv/wsi: signal the semaphore in the acquireNextImage</li>
+    <p></p>
+    <p>Marek Olšák (3):</p>
+    <li>      st/mesa: fix Sanctuary and Tropics by disabling ARB_gpu_shader5 for them</li>
+    <li>      tgsi_to_nir: fix masked out image loads</li>
+    <li>      tgsi_to_nir: handle PIPE_FORMAT_NONE in image opcodes</li>
+    <p></p>
+    <p>Paulo Zanoni (1):</p>
+    <li>      intel/compiler: fix nir_op_{i,u}*32 on ICL</li>
+    <p></p>
+    <p>Pierre-Eric Pelloux-Prayer (3):</p>
+    <li>      radeonsi: disable sdma for gfx10</li>
+    <li>      radeonsi: tell the shader disk cache what IR is used</li>
+    <li>      radeonsi: fix shader disk cache key</li>
+    <p></p>
+    <p></p>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.2.6.html
+++ b/docs/relnotes/19.2.6.html
@@ -0,0 +1,87 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="content-type" content="text/html; charset=utf-8">
+<title>Mesa Release Notes</title>
+<link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+<h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.2.6 Release Notes / 2019-11-21</h1>
+
+<p>
+    Mesa 19.2.6 is a bug fix release which fixes bugs found since the 19.2.5 release.
+</p>
+<p>
+Mesa 19.2.6 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+<p>
+Mesa 19.2.6 implements the Vulkan 1.1 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+</p>
+
+<h2>SHA256 checksum</h2>
+<pre>
+TBD.
+</pre>
+
+
+<h2>New features</h2>
+
+<ul>
+    <li>None</li>
+</ul>
+
+<h2>Bug fixes</h2>
+
+<ul>
+    <li>glesv2.pc is not built since fafd20f67dec9f589</li>
+    <li>textureSize(samplerExternalOES, int) missing in desktop mesa 19.1.7 implementation</li>
+    <li>[19.2.5] lp_bld_misc: broken #if PIPE_ARCH_LITTLE_ENDIAN on ppc64l</li>
+</ul>
+
+<h2>Changes</h2>
+
+<ul>
+    <p>Alejandro Piñeiro (1):</p>
+    <li>      v3d: adds an extra MOV for any sig.ld*</li>
+    <p></p>
+    <p>Dave Airlie (1):</p>
+    <li>      llvmpipe/ppc: fix if/ifdef confusion in backport.</li>
+    <p></p>
+    <p>Dylan Baker (2):</p>
+    <li>      docs/relnotes/19.2.5: Add SHA256 sum</li>
+    <li>      meson: generate .pc files for gles and gles2 with old glvnd</li>
+    <p></p>
+    <p>Eric Engestrom (1):</p>
+    <li>      vulkan: delete typo&#x27;d header</li>
+    <p></p>
+    <p>Hyunjun Ko (1):</p>
+    <li>      freedreno/ir3: fix printing output registers of FS.</li>
+    <p></p>
+    <p>Jose Maria Casanova Crespo (1):</p>
+    <li>      v3d: Fix predication with atomic image operations</li>
+    <p></p>
+    <p>Yevhenii Kolesnikov (1):</p>
+    <li>      glsl: Enable textureSize for samplerExternalOES</li>
+    <p></p>
+    <p></p>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.2.7.html
+++ b/docs/relnotes/19.2.7.html
@@ -0,0 +1,96 @@
+
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+<meta http-equiv="content-type" content="text/html; charset=utf-8">
+<title>Mesa Release Notes</title>
+<link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+<h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.2.7 Release Notes / 2019-12-04</h1>
+
+<p>
+    Mesa 19.2.7 is a bug fix release which fixes bugs found since the 19.2.6 release.
+</p>
+<p>
+Mesa 19.2.7 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+<p>
+Mesa 19.2.7 implements the Vulkan 1.1 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+</p>
+
+<h2>SHA256 checksum</h2>
+<pre>
+TBD.
+</pre>
+
+
+<h2>New features</h2>
+
+<ul>
+    <li>None</li>
+</ul>
+
+<h2>Bug fixes</h2>
+
+<ul>
+    <li>ld.lld: error: duplicate symbol (mesa-19.3.0-rc1)</li>
+    <li>triangle strip clipping with GL_FIRST_VERTEX_CONVENTION causes wrong vertex&#x27;s attribute to be broadcasted for flat interpolation</li>
+    <li>[bisected][regression][g45,g965,ilk] piglit arb_fragment_program kil failures</li>
+</ul>
+
+<h2>Changes</h2>
+
+<ul>
+    <p>Bas Nieuwenhuizen (2):</p>
+    <li>      radv: Allocate cmdbuffer space for buffer marker write.</li>
+    <li>      radv: Unify max_descriptor_set_size.</li>
+    <p></p>
+    <p>Boris Brezillon (1):</p>
+    <li>      gallium: Fix the -&gt;set_damage_region() implementation</li>
+    <p></p>
+    <p>Ian Romanick (1):</p>
+    <li>      intel/fs: Disable conditional discard optimization on Gen4 and Gen5</li>
+    <p></p>
+    <p>Jason Ekstrand (1):</p>
+    <li>      anv: Set up SBE_SWIZ properly for gl_Viewport</li>
+    <p></p>
+    <p>Jonathan Gray (2):</p>
+    <li>      winsys/amdgpu: avoid double simple_mtx_unlock()</li>
+    <li>      i965: update Makefile.sources for perf changes</li>
+    <p></p>
+    <p>Rhys Perry (1):</p>
+    <li>      radv: set writes_memory for global memory stores/atomics</li>
+    <p></p>
+    <p>Samuel Pitoiset (3):</p>
+    <li>      radv: fix enabling sample shading with SampleID/SamplePosition</li>
+    <li>      radv/gfx10: fix implementation of exclusive scans</li>
+    <li>      radv: fix compute pipeline keys when optimizations are disabled</li>
+    <p></p>
+    <p>Yevhenii Kolesnikov (1):</p>
+    <li>      meson: Fix linkage of libgallium_nine with libgalliumvl</li>
+    <p></p>
+    <p>Zebediah Figura (1):</p>
+    <li>      Revert &quot;draw: revert using correct order for prim decomposition.&quot;</li>
+    <p></p>
+    <p></p>
+</ul>
+
+</div>
+</body>
+</html>
--- a/include/vulkan/vulkan_xlib_randr.h
+++ b/include/vulkan/vulkan_xlib_randr.h
@@ -1,54 +0,0 @@
-#ifndef VULKAN_XLIB_RANDR_H_
-#define VULKAN_XLIB_RANDR_H_ 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-** Copyright (c) 2015-2017 The Khronos Group Inc.
-**
-** Licensed under the Apache License, Version 2.0 (the "License");
-** you may not use this file except in compliance with the License.
-** You may obtain a copy of the License at
-**
-**     http://www.apache.org/licenses/LICENSE-2.0
-**
-** Unless required by applicable law or agreed to in writing, software
-** distributed under the License is distributed on an "AS IS" BASIS,
-** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-** See the License for the specific language governing permissions and
-** limitations under the License.
-*/
-
-/*
-** This header is generated from the Khronos Vulkan XML API Registry.
-**
-*/
-
-
-#define VK_EXT_acquire_xlib_display 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_SPEC_VERSION 1
-#define VK_EXT_ACQUIRE_XLIB_DISPLAY_EXTENSION_NAME "VK_EXT_acquire_xlib_display"
-
-typedef VkResult (VKAPI_PTR *PFN_vkAcquireXlibDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, VkDisplayKHR display);
-typedef VkResult (VKAPI_PTR *PFN_vkGetRandROutputDisplayEXT)(VkPhysicalDevice physicalDevice, Display* dpy, RROutput rrOutput, VkDisplayKHR* pDisplay);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkAcquireXlibDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    VkDisplayKHR                                display);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetRandROutputDisplayEXT(
-    VkPhysicalDevice                            physicalDevice,
-    Display*                                    dpy,
-    RROutput                                    rrOutput,
-    VkDisplayKHR*                               pDisplay);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -4218,8 +4218,43 @@ ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValu
 {
 	LLVMValueRef result, tmp;

-	if (ctx->chip_class >= GFX10) {
-		result = inclusive ? src : identity;
+	if (inclusive) {
+		result = src;
+	} else if (ctx->chip_class >= GFX10) {
+		/* wavefront shift_right by 1 on GFX10 (emulate dpp_wf_sr1) */
+		LLVMValueRef active, tmp1, tmp2;
+		LLVMValueRef tid = ac_get_thread_id(ctx);
+
+		tmp1 = ac_build_dpp(ctx, identity, src, dpp_row_sr(1), 0xf, 0xf, false);
+
+		tmp2 = ac_build_permlane16(ctx, src, (uint64_t)~0, true, false);
+
+		if (maxprefix > 32) {
+			active = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tid,
+					       LLVMConstInt(ctx->i32, 32, false), "");
+
+			tmp2 = LLVMBuildSelect(ctx->builder, active,
+					       ac_build_readlane(ctx, src,
+								 LLVMConstInt(ctx->i32, 31, false)),
+					       tmp2, "");
+
+			active = LLVMBuildOr(ctx->builder, active,
+					     LLVMBuildICmp(ctx->builder, LLVMIntEQ,
+							   LLVMBuildAnd(ctx->builder, tid,
+									LLVMConstInt(ctx->i32, 0x1f, false), ""),
+							   LLVMConstInt(ctx->i32, 0x10, false), ""), "");
+			src = LLVMBuildSelect(ctx->builder, active, tmp2, tmp1, "");
+		} else if (maxprefix > 16) {
+			active = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tid,
+					       LLVMConstInt(ctx->i32, 16, false), "");
+
+			src = LLVMBuildSelect(ctx->builder, active, tmp2, tmp1, "");
+		}
+
+		result = src;
+	} else if (ctx->chip_class >= GFX8) {
+		src = ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false);
+		result = src;
 	} else {
 		if (!inclusive)
 			src = ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false);
@@ -4249,33 +4284,31 @@ ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValu
 		return result;

 	if (ctx->chip_class >= GFX10) {
-		/* dpp_row_bcast{15,31} are not supported on gfx10. */
-		LLVMBuilderRef builder = ctx->builder;
 		LLVMValueRef tid = ac_get_thread_id(ctx);
-		LLVMValueRef cc;
-		/* TODO-GFX10: Can we get better code-gen by putting this into
-		 * a branch so that LLVM generates EXEC mask manipulations? */
-		if (inclusive)
-			tmp = result;
-		else
-			tmp = ac_build_alu_op(ctx, result, src, op);
-		tmp = ac_build_permlane16(ctx, tmp, ~(uint64_t)0, true, false);
-		tmp = ac_build_alu_op(ctx, result, tmp, op);
-		cc = LLVMBuildAnd(builder, tid, LLVMConstInt(ctx->i32, 16, false), "");
-		cc = LLVMBuildICmp(builder, LLVMIntNE, cc, ctx->i32_0, "");
-		result = LLVMBuildSelect(builder, cc, tmp, result, "");
+		LLVMValueRef active;
+
+		tmp = ac_build_permlane16(ctx, result, ~(uint64_t)0, true, false);
+
+		active = LLVMBuildICmp(ctx->builder, LLVMIntNE,
+				       LLVMBuildAnd(ctx->builder, tid,
+						    LLVMConstInt(ctx->i32, 16, false), ""),
+				       ctx->i32_0, "");
+
+		tmp = LLVMBuildSelect(ctx->builder, active, tmp, identity, "");
+
+		result = ac_build_alu_op(ctx, result, tmp, op);
+
 		if (maxprefix <= 32)
 			return result;

-		if (inclusive)
-			tmp = result;
-		else
-			tmp = ac_build_alu_op(ctx, result, src, op);
-		tmp = ac_build_readlane(ctx, tmp, LLVMConstInt(ctx->i32, 31, false));
-		tmp = ac_build_alu_op(ctx, result, tmp, op);
-		cc = LLVMBuildICmp(builder, LLVMIntUGE, tid,
-				   LLVMConstInt(ctx->i32, 32, false), "");
-		result = LLVMBuildSelect(builder, cc, tmp, result, "");
+		tmp = ac_build_readlane(ctx, result, LLVMConstInt(ctx->i32, 31, false));
+
+		active = LLVMBuildICmp(ctx->builder, LLVMIntUGE, tid,
+				       LLVMConstInt(ctx->i32, 32, false), "");
+
+		tmp = LLVMBuildSelect(ctx->builder, active, tmp, identity, "");
+
+		result = ac_build_alu_op(ctx, result, tmp, op);
 		return result;
 	}

--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6001,6 +6001,8 @@ void radv_CmdWriteBufferMarkerAMD(

 	si_emit_cache_flush(cmd_buffer);

+	ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
+
 	if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
 		radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 		radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
@@ -6020,4 +6022,6 @@ void radv_CmdWriteBufferMarkerAMD(
 					   va, marker,
 					   cmd_buffer->gfx9_eop_bug_va);
 	}
+
+	assert(cmd_buffer->cs->cdw <= cdw_max);
 }
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1075,6 +1075,24 @@ void radv_GetPhysicalDeviceFeatures2(
 	return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
 }

+static size_t
+radv_max_descriptor_set_size()
+{
+	/* make sure that the entire descriptor set is addressable with a signed
+	 * 32-bit int. So the sum of all limits scaled by descriptor size has to
+	 * be at most 2 GiB. the combined image & samples object count as one of
+	 * both. This limit is for the pipeline layout, not for the set layout, but
+	 * there is no set limit, so we just set a pipeline limit. I don't think
+	 * any app is going to hit this soon. */
+	return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
+	                     - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
+	          (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
+	           32 /* storage buffer, 32 due to potential space wasted on alignment */ +
+	           32 /* sampler, largest when combined with image */ +
+	           64 /* sampled image */ +
+	           64 /* storage image */);
+}
+
 void radv_GetPhysicalDeviceProperties(
 	VkPhysicalDevice                            physicalDevice,
 	VkPhysicalDeviceProperties*                 pProperties)
@@ -1082,18 +1100,7 @@ void radv_GetPhysicalDeviceProperties(
 	RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
 	VkSampleCountFlags sample_counts = 0xf;

-	/* make sure that the entire descriptor set is addressable with a signed
-	 * 32-bit int. So the sum of all limits scaled by descriptor size has to
-	 * be at most 2 GiB. the combined image & samples object count as one of
-	 * both. This limit is for the pipeline layout, not for the set layout, but
-	 * there is no set limit, so we just set a pipeline limit. I don't think
-	 * any app is going to hit this soon. */
-	size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
-	          (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
-	           32 /* storage buffer, 32 due to potential space wasted on alignment */ +
-	           32 /* sampler, largest when combined with image */ +
-	           64 /* sampled image */ +
-	           64 /* storage image */);
+	size_t max_descriptor_set_size = radv_max_descriptor_set_size();

 	VkPhysicalDeviceLimits limits = {
 		.maxImageDimension1D                      = (1 << 14),
@@ -1362,13 +1369,7 @@ void radv_GetPhysicalDeviceProperties2(
 			properties->robustBufferAccessUpdateAfterBind = false;
 			properties->quadDivergentImplicitLod = false;

-			size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
-				MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
-			          (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
-			           32 /* storage buffer, 32 due to potential space wasted on alignment */ +
-			           32 /* sampler, largest when combined with image */ +
-			           64 /* sampled image */ +
-			           64 /* storage image */);
+			size_t max_descriptor_set_size = radv_max_descriptor_set_size();
 			properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
 			properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
 			properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1122,15 +1122,32 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 	int ps_iter_samples = 1;
 	uint32_t mask = 0xffff;

-	if (vkms)
+	if (vkms) {
 		ms->num_samples = vkms->rasterizationSamples;
-	else
-		ms->num_samples = 1;

-	if (vkms)
-		ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
-	if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
-		ps_iter_samples = ms->num_samples;
+		/* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
+		 *
+		 * "Sample shading is enabled for a graphics pipeline:
+		 *
+		 * - If the interface of the fragment shader entry point of the
+		 *   graphics pipeline includes an input variable decorated
+		 *   with SampleId or SamplePosition. In this case
+		 *   minSampleShadingFactor takes the value 1.0.
+		 * - Else if the sampleShadingEnable member of the
+		 *   VkPipelineMultisampleStateCreateInfo structure specified
+		 *   when creating the graphics pipeline is set to VK_TRUE. In
+		 *   this case minSampleShadingFactor takes the value of
+		 *   VkPipelineMultisampleStateCreateInfo::minSampleShading.
+		 *
+		 * Otherwise, sample shading is considered disabled."
+		 */
+		if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
+			ps_iter_samples = ms->num_samples;
+		} else {
+			ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
+		}
+	} else {
+		ms->num_samples = 1;
 	}

 	const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
@@ -4738,6 +4755,19 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
 	assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
 }

+static struct radv_pipeline_key
+radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
+				   const VkComputePipelineCreateInfo *pCreateInfo)
+{
+	struct radv_pipeline_key key;
+	memset(&key, 0, sizeof(key));
+
+	if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
+		key.optimisations_disabled = 1;
+
+	return key;
+}
+
 static VkResult radv_compute_pipeline_create(
 	VkDevice                                    _device,
 	VkPipelineCache                             _cache,
@@ -4770,7 +4800,11 @@ static VkResult radv_compute_pipeline_create(
 		stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];

 	pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
-	radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
+
+	struct radv_pipeline_key key =
+		radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
+
+	radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);

 	pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
 	pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -151,6 +151,13 @@ set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 			((wrmask >> (i * 4)) & 0xf) << comp;
 }

+static void
+set_writes_memory(const nir_shader *nir, struct radv_shader_info *info)
+{
+	if (nir->info.stage == MESA_SHADER_FRAGMENT)
+		info->ps.writes_memory = true;
+}
+
 static void
 gather_intrinsic_store_deref_info(const nir_shader *nir,
 				const nir_intrinsic_instr *instr,
@@ -304,8 +311,7 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 		    instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
 		    instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange ||
 		    instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
-			if (nir->info.stage == MESA_SHADER_FRAGMENT)
-				info->ps.writes_memory = true;
+			set_writes_memory(nir, info);
 		}
 		break;
 	}
@@ -320,15 +326,28 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 	case nir_intrinsic_ssbo_atomic_xor:
 	case nir_intrinsic_ssbo_atomic_exchange:
 	case nir_intrinsic_ssbo_atomic_comp_swap:
-		if (nir->info.stage == MESA_SHADER_FRAGMENT)
-			info->ps.writes_memory = true;
+		set_writes_memory(nir, info);
 		break;
 	case nir_intrinsic_load_deref:
 		gather_intrinsic_load_deref_info(nir, instr, info);
 		break;
 	case nir_intrinsic_store_deref:
 		gather_intrinsic_store_deref_info(nir, instr, info);
+		/* fallthrough */
+	case nir_intrinsic_deref_atomic_add:
+	case nir_intrinsic_deref_atomic_imin:
+	case nir_intrinsic_deref_atomic_umin:
+	case nir_intrinsic_deref_atomic_imax:
+	case nir_intrinsic_deref_atomic_umax:
+	case nir_intrinsic_deref_atomic_and:
+	case nir_intrinsic_deref_atomic_or:
+	case nir_intrinsic_deref_atomic_xor:
+	case nir_intrinsic_deref_atomic_exchange:
+	case nir_intrinsic_deref_atomic_comp_swap: {
+		if (nir_src_as_deref(instr->src[0])->mode & (nir_var_mem_global | nir_var_mem_ssbo))
+			set_writes_memory(nir, info);
 		break;
+	}
 	default:
 		break;
 	}
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -406,6 +406,20 @@ ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
        return qregs;
 }

+static bool
+is_ld_signal(const struct v3d_qpu_sig *sig)
+{
+        return (sig->ldunif ||
+                sig->ldunifa ||
+                sig->ldunifrf ||
+                sig->ldunifarf ||
+                sig->ldtmu ||
+                sig->ldvary ||
+                sig->ldvpm ||
+                sig->ldtlb ||
+                sig->ldtlbu);
+}
+
 /**
 * This function is responsible for getting VIR results into the associated
 * storage for a NIR instruction.
@@ -453,11 +467,12 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
                        _mesa_hash_table_search(c->def_ht, reg);
                struct qreg *qregs = entry->data;

-                /* Insert a MOV if the source wasn't an SSA def in the
-                 * previous instruction.
+                /* If the previous instruction can't be predicated for
+                 * the store into the nir_register, then emit a MOV
+                 * that can be.
                 */
-                if ((vir_in_nonuniform_control_flow(c) &&
-                     c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
+                if (vir_in_nonuniform_control_flow(c) &&
+                    is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) {
                        result = vir_MOV(c, result);
                        last_inst = c->defs[result.index];
                }
--- a/src/broadcom/compiler/v3d40_tex.c
+++ b/src/broadcom/compiler/v3d40_tex.c
@@ -388,9 +388,21 @@ v3d40_vir_emit_image_load_store(struct v3d_compile *c,
                }
        }

+        if (vir_in_nonuniform_control_flow(c) &&
+            instr->intrinsic != nir_intrinsic_image_deref_load) {
+           vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
+                      V3D_QPU_PF_PUSHZ);
+        }
+
        vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, ntq_get_src(c, instr->src[1], 0),
                      &tmu_writes);

+        if (vir_in_nonuniform_control_flow(c) &&
+            instr->intrinsic != nir_intrinsic_image_deref_load) {
+           struct qinst *last_inst= (struct  qinst *)c->cur_block->instructions.prev;
+           vir_set_cond(last_inst, V3D_QPU_COND_IFA);
+        }
+
        vir_emit_thrsw(c);

        /* The input FIFO has 16 slots across all threads, so make sure we
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -2094,6 +2094,8 @@ builtin_builder::create_builtins()
                _textureSize(texture_multisample_array, glsl_type::ivec3_type, glsl_type::sampler2DMSArray_type),
                _textureSize(texture_multisample_array, glsl_type::ivec3_type, glsl_type::isampler2DMSArray_type),
                _textureSize(texture_multisample_array, glsl_type::ivec3_type, glsl_type::usampler2DMSArray_type),
+
+                _textureSize(texture_external_es3, glsl_type::ivec2_type, glsl_type::samplerExternalOES_type),
                NULL);

   add_function("textureSize1D",
--- a/src/compiler/nir/nir_algebraic.py
+++ b/src/compiler/nir/nir_algebraic.py
@@ -200,7 +200,7 @@ class Value(object):
   ${val.cond if val.cond else 'NULL'},
   ${val.swizzle()},
 % elif isinstance(val, Expression):
-   ${'true' if val.inexact else 'false'},
+   ${'true' if val.inexact else 'false'}, ${'true' if val.exact else 'false'},
   ${val.comm_expr_idx}, ${val.comm_exprs},
   ${val.c_opcode()},
   { ${', '.join(src.c_value_ptr(cache) for src in val.sources)} },
@@ -348,7 +348,7 @@ class Variable(Value):
         return '{' + ', '.join([str(swizzles[c]) for c in self.swiz[1:]]) + '}'
      return '{0, 1, 2, 3}'

-_opcode_re = re.compile(r"(?P<inexact>~)?(?P<opcode>\w+)(?:@(?P<bits>\d+))?"
+_opcode_re = re.compile(r"(?P<inexact>~)?(?P<exact>!)?(?P<opcode>\w+)(?:@(?P<bits>\d+))?"
                        r"(?P<cond>\([^\)]+\))?")

 class Expression(Value):
@@ -362,8 +362,12 @@ class Expression(Value):
      self.opcode = m.group('opcode')
      self._bit_size = int(m.group('bits')) if m.group('bits') else None
      self.inexact = m.group('inexact') is not None
+      self.exact = m.group('exact') is not None
      self.cond = m.group('cond')

+      assert not self.inexact or not self.exact, \
+            'Expression cannot be both exact and inexact.'
+
      # "many-comm-expr" isn't really a condition.  It's notification to the
      # generator that this pattern is known to have too many commutative
      # expressions, and an error should not be generated for this case.
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -69,6 +69,9 @@ e = 'e'
 # expression this indicates that the constructed value should have that
 # bit-size.
 #
+# If the opcode in a replacement expression is prefixed by a '!' character,
+# this indicated that the new expression will be marked exact.
+#
 # A special condition "many-comm-expr" can be used with expressions to note
 # that the expression and its subexpressions have more commutative expressions
 # than nir_replace_instr can handle.  If this special condition is needed with
@@ -1327,8 +1330,8 @@ optimizations += [(bitfield_reverse('x@32'), ('bitfield_reverse', 'x'), '!option
 # and, if a is a NaN then the second comparison will fail anyway.
 for op in ['flt', 'fge', 'feq']:
   optimizations += [
-      (('iand', ('feq', a, a), (op, a, b)), (op, a, b)),
-      (('iand', ('feq', a, a), (op, b, a)), (op, b, a)),
+      (('iand', ('feq', a, a), (op, a, b)), ('!' + op, a, b)),
+      (('iand', ('feq', a, a), (op, b, a)), ('!' + op, b, a)),
   ]

 # Add optimizations to handle the case where the result of a ternary is
--- a/src/compiler/nir/nir_search.c
+++ b/src/compiler/nir/nir_search.c
@@ -472,7 +472,7 @@ construct_value(nir_builder *build,
       * expression we are replacing has any exact values, the entire
       * replacement should be exact.
       */
-      alu->exact = state->has_exact_alu;
+      alu->exact = state->has_exact_alu || expr->exact;

      for (unsigned i = 0; i < nir_op_infos[op].num_inputs; i++) {
         /* If the source is an explicitly sized source, then we need to reset
--- a/src/compiler/nir/nir_search.h
+++ b/src/compiler/nir/nir_search.h
@@ -138,6 +138,9 @@ typedef struct {
    */
   bool inexact;

+   /** In a replacement, requests that the instruction be marked exact. */
+   bool exact;
+
   /* Commutative expression index.  This is assigned by opt_algebraic.py when
    * search structures are constructed and is a unique (to this structure)
    * index within the commutative operation bitfield used for searching for
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -4647,7 +4647,8 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
   }

   /* Set shader info defaults */
-   b->shader->info.gs.invocations = 1;
+   if (stage == MESA_SHADER_GEOMETRY)
+      b->shader->info.gs.invocations = 1;

   b->specializations = spec;
   b->num_specializations = num_spec;
--- a/src/egl/main/egldisplay.c
+++ b/src/egl/main/egldisplay.c
@@ -135,15 +135,6 @@ _eglNativePlatformDetectNativeDisplay(void *nativeDisplay)
      if (first_pointer == gbm_create_device)
         return _EGL_PLATFORM_DRM;
 #endif
-
-#ifdef HAVE_X11_PLATFORM
-      /* If not matched to any other platform, fallback to x11. */
-      return _EGL_PLATFORM_X11;
-#endif
-
-#ifdef HAVE_HAIKU_PLATFORM
-      return _EGL_PLATFORM_HAIKU;
-#endif
   }

   return _EGL_INVALID_PLATFORM;
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -405,8 +405,9 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 	fprintf(out, "; %s: outputs:", type);
 	for (i = 0; i < so->outputs_count; i++) {
 		uint8_t regid = so->outputs[i].regid;
-		fprintf(out, " r%d.%c (%s)",
-				(regid >> 2), "xyzw"[regid & 0x3],
+		const char *reg_type = so->outputs[i].half ? "hr" : "r";
+		fprintf(out, " %s%d.%c (%s)",
+				reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 				output_name(so, i));
 	}
 	fprintf(out, "\n");
--- a/src/gallium/auxiliary/draw/draw_pt_decompose.h
+++ b/src/gallium/auxiliary/draw/draw_pt_decompose.h
@@ -3,8 +3,6 @@
   const boolean quads_flatshade_last =      \
      draw->quads_always_flatshade_last;     \
   const boolean last_vertex_last =          \
-      !(draw->rasterizer->flatshade &&       \
-        draw->rasterizer->flatshade_first);
-/* FIXME: the draw->rasterizer->flatshade part is really wrong */
+      !draw->rasterizer->flatshade_first;

 #include "draw_decompose_tmp.h"
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -692,7 +692,20 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
    * when not using MCJIT so no instructions are generated which the old JIT
    * can't handle. Not entirely sure if we really need to do anything yet.
    */
-#if defined(PIPE_ARCH_LITTLE_ENDIAN)  && defined(PIPE_ARCH_PPC_64)
+
+#ifdef PIPE_ARCH_PPC_64
+   /*
+    * Large programs, e.g. gnome-shell and firefox, may tax the addressability
+    * of the Medium code model once dynamically generated JIT-compiled shader
+    * programs are linked in and relocated.  Yet the default code model as of
+    * LLVM 8 is Medium or even Small.
+    * The cost of changing from Medium to Large is negligible:
+    * - an additional 8-byte pointer stored immediately before the shader entrypoint;
+    * - change an add-immediate (addis) instruction to a load (ld).
+    */
+   builder.setCodeModel(CodeModel::Large);
+
+#ifdef PIPE_ARCH_LITTLE_ENDIAN
   /*
    * Versions of LLVM prior to 4.0 lacked a table entry for "POWER8NVL",
    * resulting in (big-endian) "generic" being returned on
@@ -704,6 +717,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
    */
   if (MCPU == "generic")
      MCPU = "pwr8";
+#endif
 #endif
   builder.setMCPU(MCPU);
   if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1727,6 +1727,9 @@ static GLenum
 get_image_format(struct tgsi_full_instruction *tgsi_inst)
 {
   switch (tgsi_inst->Memory.Format) {
+   case PIPE_FORMAT_NONE:
+      return GL_NONE;
+
   case PIPE_FORMAT_R8_UNORM:
      return GL_R8;
   case PIPE_FORMAT_R8G8_UNORM:
@@ -1922,8 +1925,7 @@ ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)


   if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
-      nir_ssa_dest_init(&instr->instr, &instr->dest,
-                        util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
+      nir_ssa_dest_init(&instr->instr, &instr->dest, instr->num_components,
                        32, NULL);
      nir_builder_instr_insert(b, &instr->instr);
      ttn_move_dest(b, dest, &instr->dest.ssa);
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -20,6 +20,7 @@ DRI_CONF_SECTION_DEBUG
   DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
   DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
   DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
+   DRI_CONF_DISABLE_ARB_GPU_SHADER5("false")
   DRI_CONF_FORCE_GLSL_VERSION(0)
   DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
   DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION("false")
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -460,7 +460,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	if (!sctx->ctx)
 		goto fail;

-	if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
+	if (sscreen->info.num_sdma_rings &&
+	    !(sscreen->debug_flags & DBG(NO_ASYNC_DMA)) &&
+	    /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
+	     *    https://bugs.freedesktop.org/show_bug.cgi?id=111481
+	     *    https://gitlab.freedesktop.org/mesa/mesa/issues/1907
+	     */
+	    (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_DMA))) {
 		sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
 						   (void*)si_flush_dma_cs,
 						   sctx, stop_exec_on_failure);
@@ -871,6 +877,10 @@ static void si_disk_cache_create(struct si_screen *sscreen)
 	/* These flags affect shader compilation. */
 	#define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
 	uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
+	/* Reserve left-most bit for tgsi/nir selector */
+	assert(!(shader_debug_flags & (1u << 31)));
+	shader_debug_flags |= (uint32_t)
+		((sscreen->options.enable_nir & 0x1) << 31);

 	/* Add the high bits of 32-bit addresses, which affects
 	 * how 32-bit addresses are expanded to 64 bits.
@@ -993,6 +1003,13 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
 		return NULL;
 	}

+	{
+#define OPT_BOOL(name, dflt, description) \
+		sscreen->options.name = \
+			driQueryOptionb(config->options, "radeonsi_"#name);
+#include "si_debug_options.h"
+	}
+
 	si_disk_cache_create(sscreen);

 	/* Determine the number of shader compiler threads. */
@@ -1119,13 +1136,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
 	sscreen->commutative_blend_add =
 		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");

-	{
-#define OPT_BOOL(name, dflt, description) \
-		sscreen->options.name = \
-			driQueryOptionb(config->options, "radeonsi_"#name);
-#include "si_debug_options.h"
-	}
-
 	sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
 					sscreen->info.family == CHIP_RAVEN;
 	sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -219,6 +219,7 @@ struct st_config_options
 {
   bool disable_blend_func_extended;
   bool disable_glsl_line_continuations;
+   bool disable_arb_gpu_shader5;
   bool force_glsl_extensions_warn;
   unsigned force_glsl_version;
   bool allow_glsl_extension_directive_midshader;
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -907,7 +907,7 @@ dri2_create_image_from_fd(__DRIscreen *_screen,
      whandles[i].stride = (unsigned)strides[index];
      whandles[i].offset = (unsigned)offsets[index];
      whandles[i].modifier = modifier;
-      whandles[i].plane = i;
+      whandles[i].plane = index;
   }

   img = dri2_create_image_from_winsys(_screen, width, height, map,
@@ -1861,8 +1861,6 @@ static void
 dri2_set_damage_region(__DRIdrawable *dPriv, unsigned int nrects, int *rects)
 {
   struct dri_drawable *drawable = dri_drawable(dPriv);
-   struct pipe_resource *resource = drawable->textures[ST_ATTACHMENT_BACK_LEFT];
-   struct pipe_screen *screen = resource->screen;
   struct pipe_box *boxes = NULL;

   if (nrects) {
@@ -1876,8 +1874,25 @@ dri2_set_damage_region(__DRIdrawable *dPriv, unsigned int nrects, int *rects)
      }
   }

-   screen->set_damage_region(screen, resource, nrects, boxes);
-   FREE(boxes);
+   FREE(drawable->damage_rects);
+   drawable->damage_rects = boxes;
+   drawable->num_damage_rects = nrects;
+
+   /* Only apply the damage region if the BACK_LEFT texture is up-to-date. */
+   if (drawable->texture_stamp == drawable->dPriv->lastStamp &&
+       (drawable->texture_mask & (1 << ST_ATTACHMENT_BACK_LEFT))) {
+      struct pipe_screen *screen = drawable->screen->base.screen;
+      struct pipe_resource *resource;
+
+      if (drawable->stvis.samples > 1)
+         resource = drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT];
+      else
+         resource = drawable->textures[ST_ATTACHMENT_BACK_LEFT];
+
+      screen->set_damage_region(screen, resource,
+                                drawable->num_damage_rects,
+                                drawable->damage_rects);
+   }
 }

 static __DRI2bufferDamageExtension dri2BufferDamageExtension = {
--- a/src/gallium/state_trackers/dri/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/dri_drawable.c
@@ -95,6 +95,18 @@ dri_st_framebuffer_validate(struct st_context_iface *stctx,
      }
   } while (lastStamp != drawable->dPriv->lastStamp);

+   /* Flush the pending set_damage_region request. */
+   struct pipe_screen *pscreen = screen->base.screen;
+
+   if (new_mask & (1 << ST_ATTACHMENT_BACK_LEFT) &&
+       pscreen->set_damage_region) {
+      struct pipe_resource *resource = textures[ST_ATTACHMENT_BACK_LEFT];
+
+      pscreen->set_damage_region(pscreen, resource,
+                                 drawable->num_damage_rects,
+                                 drawable->damage_rects);
+   }
+
   if (!out)
      return true;

@@ -202,6 +214,7 @@ dri_destroy_buffer(__DRIdrawable * dPriv)
   /* Notify the st manager that this drawable is no longer valid */
   stapi->destroy_drawable(stapi, &drawable->base);

+   FREE(drawable->damage_rects);
   FREE(drawable);
 }

--- a/src/gallium/state_trackers/dri/dri_drawable.h
+++ b/src/gallium/state_trackers/dri/dri_drawable.h
@@ -56,6 +56,9 @@ struct dri_drawable
   unsigned old_w;
   unsigned old_h;

+   struct pipe_box *damage_rects;
+   unsigned int num_damage_rects;
+
   struct pipe_resource *textures[ST_ATTACHMENT_COUNT];
   struct pipe_resource *msaa_textures[ST_ATTACHMENT_COUNT];
   unsigned int texture_mask, texture_stamp;
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -65,6 +65,8 @@ dri_fill_st_options(struct dri_screen *screen)

   options->disable_blend_func_extended =
      driQueryOptionb(optionCache, "disable_blend_func_extended");
+   options->disable_arb_gpu_shader5 =
+      driQueryOptionb(optionCache, "disable_arb_gpu_shader5");
   options->disable_glsl_line_continuations =
      driQueryOptionb(optionCache, "disable_glsl_line_continuations");
   options->force_glsl_extensions_warn =
--- a/src/gallium/targets/d3dadapter9/meson.build
+++ b/src/gallium/targets/d3dadapter9/meson.build
@@ -28,12 +28,24 @@ nine_version = ['1', '0', '0']
 gallium_nine_c_args = []
 gallium_nine_ld_args = []
 gallium_nine_link_depends = []
+gallium_nine_link_with = [
+    libgallium, libnine_st,
+    libpipe_loader_static, libws_null, libwsw, libswdri,
+    libswkmsdri,
+]

 if with_ld_version_script
  gallium_nine_ld_args += ['-Wl,--version-script', join_paths(meson.current_source_dir(), 'd3dadapter9.sym')]
  gallium_nine_link_depends += files('d3dadapter9.sym')
 endif

+if (with_gallium_va or with_gallium_vdpau or with_gallium_omx != 'disabled' or
+    with_gallium_xvmc or with_dri)
+  gallium_nine_link_with += libgalliumvl
+else
+  gallium_nine_link_with += libgalliumvl_stub
+endif
+
 libgallium_nine = shared_library(
  'd3dadapter9',
  files('description.c', 'getproc.c', 'drm.c'),
@@ -47,11 +59,7 @@ libgallium_nine = shared_library(
  cpp_args : [cpp_vis_args],
  link_args : [ld_args_gc_sections, gallium_nine_ld_args],
  link_depends : gallium_nine_link_depends,
-  link_with : [
-    libgalliumvl_stub, libgallium, libnine_st,
-    libpipe_loader_static, libws_null, libwsw, libswdri,
-    libswkmsdri, libnir,
-  ],
+  link_with : gallium_nine_link_with,
  dependencies : [
    dep_selinux, dep_libdrm, dep_llvm, dep_thread, idep_xmlconfig, idep_mesautil,
    driver_swrast, driver_r300, driver_r600, driver_radeonsi, driver_nouveau,
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -326,7 +326,6 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
   aws = util_hash_table_get(dev_tab, dev);
   if (aws) {
      pipe_reference(NULL, &aws->reference);
-      simple_mtx_unlock(&dev_tab_mutex);

      /* Release the device handle, because we don't need it anymore.
       * This function is returning an existing winsys instance, which
--- a/src/gallium/winsys/sw/dri/dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
@@ -92,7 +92,8 @@ alloc_shm(struct dri_sw_displaytarget *dri_sw_dt, unsigned size)
 {
   char *addr;

-   dri_sw_dt->shmid = shmget(IPC_PRIVATE, size, IPC_CREAT|0777);
+   /* 0600 = user read+write */
+   dri_sw_dt->shmid = shmget(IPC_PRIVATE, size, IPC_CREAT | 0600);
   if (dri_sw_dt->shmid < 0)
      return NULL;

--- a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
+++ b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
@@ -126,7 +126,8 @@ alloc_shm(struct xlib_displaytarget *buf, unsigned size)
   shminfo->shmid = -1;
   shminfo->shmaddr = (char *) -1;

-   shminfo->shmid = shmget(IPC_PRIVATE, size, IPC_CREAT|0777);
+   /* 0600 = user read+write */
+   shminfo->shmid = shmget(IPC_PRIVATE, size, IPC_CREAT | 0600);
   if (shminfo->shmid < 0) {
      return NULL;
   }
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1329,7 +1329,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
      temp_op[0] = bld.fix_byte_src(op[0]);
      temp_op[1] = bld.fix_byte_src(op[1]);

-      const uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
+      const uint32_t bit_size = type_sz(temp_op[0].type) * 8;
      if (bit_size != 32)
         dest = bld.vgrf(temp_op[0].type, 1);

@@ -3368,7 +3368,14 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,

         if (alu != NULL &&
             alu->op != nir_op_bcsel &&
-             alu->op != nir_op_inot) {
+             alu->op != nir_op_inot &&
+             (devinfo->gen > 5 ||
+              (alu->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE ||
+              alu->op == nir_op_fne32 || alu->op == nir_op_feq32 ||
+              alu->op == nir_op_flt32 || alu->op == nir_op_fge32 ||
+              alu->op == nir_op_ine32 || alu->op == nir_op_ieq32 ||
+              alu->op == nir_op_ilt32 || alu->op == nir_op_ige32 ||
+              alu->op == nir_op_ult32 || alu->op == nir_op_uge32)) {
            /* Re-emit the instruction that generated the Boolean value, but
             * do not store it.  Since this instruction will be conditional,
             * other instructions that want to use the real Boolean value may
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -478,8 +478,10 @@ anv_batch_bo_list_clone(const struct list_head *list,
   }

   if (result != VK_SUCCESS) {
-      list_for_each_entry_safe(struct anv_batch_bo, bbo, new_list, link)
+      list_for_each_entry_safe(struct anv_batch_bo, bbo, new_list, link) {
+         list_del(&bbo->link);
         anv_batch_bo_destroy(bbo, cmd_buffer);
+      }
   }

   return result;
@@ -804,6 +806,7 @@ anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
   /* Destroy all of the batch buffers */
   list_for_each_entry_safe(struct anv_batch_bo, bbo,
                            &cmd_buffer->batch_bos, link) {
+      list_del(&bbo->link);
      anv_batch_bo_destroy(bbo, cmd_buffer);
   }
 }
@@ -1620,6 +1623,9 @@ anv_cmd_buffer_execbuf(struct anv_device *device,
         assert(!pdevice->has_syncobj);
         if (in_fence == -1) {
            in_fence = impl->fd;
+            if (in_fence == -1)
+               return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+            impl->fd = -1;
         } else {
            int merge = anv_gem_sync_file_merge(device, in_fence, impl->fd);
            if (merge == -1)
@@ -1627,10 +1633,9 @@ anv_cmd_buffer_execbuf(struct anv_device *device,

            close(impl->fd);
            close(in_fence);
+            impl->fd = -1;
            in_fence = merge;
         }
-
-         impl->fd = -1;
         break;

      case ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ:
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -247,12 +247,28 @@ VkResult anv_AcquireNextImage2KHR(
                                                    pAcquireInfo,
                                                    pImageIndex);

-   /* Thanks to implicit sync, the image is ready immediately.  However, we
-    * should wait for the current GPU state to finish.
+   /* Thanks to implicit sync, the image is ready immediately. However, we
+    * should wait for the current GPU state to finish. Regardless of the
+    * result of the presentation, we need to signal the semaphore & fence.
    */
+
+   if (pAcquireInfo->semaphore != VK_NULL_HANDLE) {
+      /* Put a dummy semaphore in temporary, this is the fastest way to avoid
+       * any kind of work yet still provide some kind of synchronization. This
+       * only works because the Mesa WSI code always returns an image
+       * immediately if available.
+       */
+      ANV_FROM_HANDLE(anv_semaphore, semaphore, pAcquireInfo->semaphore);
+      anv_semaphore_reset_temporary(device, semaphore);
+
+      struct anv_semaphore_impl *impl = &semaphore->temporary;
+
+      impl->type = ANV_SEMAPHORE_TYPE_DUMMY;
+   }
+
   if (pAcquireInfo->fence != VK_NULL_HANDLE) {
-      anv_QueueSubmit(anv_queue_to_handle(&device->queue), 0, NULL,
-                      pAcquireInfo->fence);
+      result = anv_QueueSubmit(anv_queue_to_handle(&device->queue),
+                               0, NULL, pAcquireInfo->fence);
   }

   return result;
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2553,20 +2553,12 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
               const struct anv_pipeline_binding *binding =
                  &bind_map->surface_to_descriptor[surface];

-               struct anv_address read_addr;
-               uint32_t read_len;
+               struct anv_address addr;
               if (binding->set == ANV_DESCRIPTOR_SET_SHADER_CONSTANTS) {
-                  struct anv_address constant_data = {
+                  addr = (struct anv_address) {
                     .bo = pipeline->device->dynamic_state_pool.block_pool.bo,
                     .offset = pipeline->shaders[stage]->constant_data.offset,
                  };
-                  unsigned constant_data_size =
-                     pipeline->shaders[stage]->constant_data_size;
-
-                  read_len = MIN2(range->length,
-                     DIV_ROUND_UP(constant_data_size, 32) - range->start);
-                  read_addr = anv_address_add(constant_data,
-                                              range->start * 32);
               } else if (binding->set == ANV_DESCRIPTOR_SET_DESCRIPTORS) {
                  /* This is a descriptor set buffer so the set index is
                   * actually given by binding->binding.  (Yes, that's
@@ -2574,45 +2566,27 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
                   */
                  struct anv_descriptor_set *set =
                     gfx_state->base.descriptors[binding->binding];
-                  struct anv_address desc_buffer_addr =
-                     anv_descriptor_set_address(cmd_buffer, set);
-                  const unsigned desc_buffer_size = set->desc_mem.alloc_size;
-
-                  read_len = MIN2(range->length,
-                     DIV_ROUND_UP(desc_buffer_size, 32) - range->start);
-                  read_addr = anv_address_add(desc_buffer_addr,
-                                              range->start * 32);
+                  addr = anv_descriptor_set_address(cmd_buffer, set);
               } else {
                  const struct anv_descriptor *desc =
                     anv_descriptor_for_binding(&gfx_state->base, binding);

                  if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
-                     read_len = MIN2(range->length,
-                        DIV_ROUND_UP(desc->buffer_view->range, 32) - range->start);
-                     read_addr = anv_address_add(desc->buffer_view->address,
-                                                 range->start * 32);
+                     addr = desc->buffer_view->address;
                  } else {
                     assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);

                     uint32_t dynamic_offset =
                        dynamic_offset_for_binding(&gfx_state->base, binding);
-                     uint32_t buf_offset =
-                        MIN2(desc->offset + dynamic_offset, desc->buffer->size);
-                     uint32_t buf_range =
-                        MIN2(desc->range, desc->buffer->size - buf_offset);
-
-                     read_len = MIN2(range->length,
-                        DIV_ROUND_UP(buf_range, 32) - range->start);
-                     read_addr = anv_address_add(desc->buffer->address,
-                                                 buf_offset + range->start * 32);
+                     addr = anv_address_add(desc->buffer->address,
+                                            desc->offset + dynamic_offset);
                  }
               }

-               if (read_len > 0) {
-                  c.ConstantBody.Buffer[n] = read_addr;
-                  c.ConstantBody.ReadLength[n] = read_len;
-                  n--;
-               }
+               c.ConstantBody.Buffer[n] =
+                  anv_address_add(addr, range->start * 32);
+               c.ConstantBody.ReadLength[n] = range->length;
+               n--;
            }

            struct anv_state state =
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -369,8 +369,8 @@ emit_3dstate_sbe(struct anv_pipeline *pipeline)
      if (input_index < 0)
         continue;

-      /* gl_Layer is stored in the VUE header */
-      if (attr == VARYING_SLOT_LAYER) {
+      /* gl_Viewport and gl_Layer are stored in the VUE header */
+      if (attr == VARYING_SLOT_VIEWPORT || attr == VARYING_SLOT_LAYER) {
         urb_entry_read_offset = 0;
         continue;
      }
--- a/src/mapi/meson.build
+++ b/src/mapi/meson.build
@@ -1,4 +1,4 @@
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2019 Intel Corporation

 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -35,11 +35,31 @@ if with_shared_glapi
 else
  libglapi = []
 endif
-if not with_glvnd
-  if with_gles1
+if with_gles1
+  if not with_glvnd
    subdir('es1api')
-  endif
-  if with_gles2
-    subdir('es2api')
+  elif not glvnd_has_headers_and_pc_files
+    pkg.generate(
+      name : 'glesv1_cm',
+      filebase : 'glesv1_cm',
+      description : 'Mesa OpenGL ES 1.1 CM library',
+      version : meson.project_version(),
+      libraries : '-L${libdir} -lGLESv1_CM',
+      libraries_private : gl_priv_libs,
+    )
+  endif
+endif
+if with_gles2
+  if not with_glvnd
+    subdir('es2api')
+  elif not glvnd_has_headers_and_pc_files
+    pkg.generate(
+      name : 'glesv2',
+      filebase : 'glesv2',
+      description : 'Mesa OpenGL ES 2.0 library',
+      version : meson.project_version(),
+      libraries : '-L${libdir} -lGLESv2',
+      libraries_private : gl_priv_libs,
+    )
  endif
 endif
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -35,9 +35,7 @@ i965_FILES = \
 	brw_object_purgeable.c \
 	brw_pipe_control.c \
 	brw_pipe_control.h \
-	brw_performance_query.h \
 	brw_performance_query.c \
-	brw_performance_query_metrics.h \
 	brw_program.c \
 	brw_program.h \
 	brw_program_binary.c \
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3051,7 +3051,7 @@ genX(upload_blend_state)(struct brw_context *brw)
 #endif
 }

-static const struct brw_tracked_state genX(blend_state) = {
+UNUSED static const struct brw_tracked_state genX(blend_state) = {
   .dirty = {
      .mesa = _NEW_BUFFERS |
              _NEW_COLOR |
@@ -3412,7 +3412,7 @@ genX(upload_color_calc_state)(struct brw_context *brw)
 #endif
 }

-static const struct brw_tracked_state genX(color_calc_state) = {
+UNUSED static const struct brw_tracked_state genX(color_calc_state) = {
   .dirty = {
      .mesa = _NEW_COLOR |
              _NEW_STENCIL |
@@ -3430,6 +3430,35 @@ static const struct brw_tracked_state genX(color_calc_state) = {
 };


+/* ---------------------------------------------------------------------- */
+
+#if GEN_IS_HASWELL
+static void
+genX(upload_color_calc_and_blend_state)(struct brw_context *brw)
+{
+   genX(upload_blend_state)(brw);
+   genX(upload_color_calc_state)(brw);
+}
+
+/* On Haswell when BLEND_STATE is emitted CC_STATE should also be re-emitted,
+ * this workarounds the flickering shadows in several games.
+ */
+static const struct brw_tracked_state genX(cc_and_blend_state) = {
+   .dirty = {
+      .mesa = _NEW_BUFFERS |
+              _NEW_COLOR |
+              _NEW_STENCIL |
+              _NEW_MULTISAMPLE,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
+             BRW_NEW_CC_STATE |
+             BRW_NEW_FS_PROG_DATA |
+             BRW_NEW_STATE_BASE_ADDRESS,
+   },
+   .emit = genX(upload_color_calc_and_blend_state),
+};
+#endif
+
 /* ---------------------------------------------------------------------- */

 #if GEN_GEN >= 7
@@ -5697,8 +5726,12 @@ genX(init_atoms)(struct brw_context *brw)
      &gen7_l3_state,
      &gen7_push_constant_space,
      &gen7_urb,
+#if GEN_IS_HASWELL
+      &genX(cc_and_blend_state),
+#else
      &genX(blend_state),		/* must do before cc unit */
      &genX(color_calc_state),	/* must do before cc unit */
+#endif
      &genX(depth_stencil_state),	/* must do before cc unit */

      &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
--- a/src/mesa/drivers/x11/xm_buffer.c
+++ b/src/mesa/drivers/x11/xm_buffer.c
@@ -89,8 +89,9 @@ alloc_back_shm_ximage(XMesaBuffer b, GLuint width, GLuint height)
      return GL_FALSE;
   }

+   /* 0600 = user read+write */
   b->shminfo.shmid = shmget(IPC_PRIVATE, b->backxrb->ximage->bytes_per_line
-			     * b->backxrb->ximage->height, IPC_CREAT|0777);
+                             * b->backxrb->ximage->height, IPC_CREAT | 0600);
   if (b->shminfo.shmid < 0) {
      _mesa_warning(NULL, "shmget failed while allocating back buffer.\n");
      XDestroyImage(b->backxrb->ximage);
--- a/src/mesa/main/texobj.h
+++ b/src/mesa/main/texobj.h
@@ -124,14 +124,28 @@ static inline GLboolean
 _mesa_is_texture_complete(const struct gl_texture_object *texObj,
                          const struct gl_sampler_object *sampler)
 {
+   struct gl_texture_image *img = texObj->Image[0][texObj->BaseLevel];
+   bool isMultisample = img && img->NumSamples >= 2;
+
   /*
    * According to ARB_stencil_texturing, NEAREST_MIPMAP_NEAREST would
    * be forbidden, however it is allowed per GL 4.5 rules, allow it
    * even without GL 4.5 since it was a spec mistake.
    */
-   if ((texObj->_IsIntegerFormat ||
+   /* Section 8.17 (texture completeness) of the OpenGL 4.6 core profile spec:
+    *
+    *  "The texture is not multisample; either the magnification filter is not
+    *  NEAREST, or the minification filter is neither NEAREST nor NEAREST_-
+    *  MIPMAP_NEAREST; and any of
+    *  – The internal format of the texture is integer.
+    *  – The internal format is STENCIL_INDEX.
+    *  – The internal format is DEPTH_STENCIL, and the value of DEPTH_-
+    *    STENCIL_TEXTURE_MODE for the texture is STENCIL_INDEX.""
+    */
+   if (!isMultisample &&
+       (texObj->_IsIntegerFormat ||
        (texObj->StencilSampling &&
-         texObj->Image[0][texObj->BaseLevel]->_BaseFormat == GL_DEPTH_STENCIL)) &&
+         img->_BaseFormat == GL_DEPTH_STENCIL)) &&
       (sampler->MagFilter != GL_NEAREST ||
        (sampler->MinFilter != GL_NEAREST &&
         sampler->MinFilter != GL_NEAREST_MIPMAP_NEAREST))) {
@@ -139,7 +153,12 @@ _mesa_is_texture_complete(const struct gl_texture_object *texObj,
      return GL_FALSE;
   }

-   if (_mesa_is_mipmap_filter(sampler))
+   /* Section 8.17 (texture completeness) of the OpenGL 4.6 core profile spec:
+    *
+    *  "The minification filter requires a mipmap (is neither NEAREST nor LINEAR),
+    *  the texture is not multisample, and the texture is not mipmap complete.""
+    */
+   if (!isMultisample &&_mesa_is_mipmap_filter(sampler))
      return texObj->_MipmapComplete;
   else
      return texObj->_BaseComplete;
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1091,7 +1091,7 @@ void st_init_extensions(struct pipe_screen *screen,
   if (api == API_OPENGLES2 && ESSLVersion >= 320)
      extensions->ARB_gpu_shader5 = GL_TRUE;

-   if (GLSLVersion >= 400)
+   if (GLSLVersion >= 400 && !options->disable_arb_gpu_shader5)
      extensions->ARB_gpu_shader5 = GL_TRUE;
   if (GLSLVersion >= 410)
      extensions->ARB_shader_precision = GL_TRUE;
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -56,11 +56,13 @@ TODO: document the other workarounds.
        <application name="Unigine Sanctuary" executable="Sanctuary">
            <option name="force_glsl_extensions_warn" value="true" />
            <option name="disable_blend_func_extended" value="true" />
+            <option name="disable_arb_gpu_shader5" value="true" />
        </application>

        <application name="Unigine Tropics" executable="Tropics">
            <option name="force_glsl_extensions_warn" value="true" />
            <option name="disable_blend_func_extended" value="true" />
+            <option name="disable_arb_gpu_shader5" value="true" />
        </application>

        <application name="Unigine Heaven (32-bit)" executable="heaven_x86">
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -80,6 +80,11 @@ DRI_CONF_OPT_BEGIN_B(disable_blend_func_extended, def) \
        DRI_CONF_DESC(en,gettext("Disable dual source blending")) \
 DRI_CONF_OPT_END

+#define DRI_CONF_DISABLE_ARB_GPU_SHADER5(def) \
+DRI_CONF_OPT_BEGIN_B(disable_arb_gpu_shader5, def) \
+        DRI_CONF_DESC(en,"Disable GL_ARB_gpu_shader5") \
+DRI_CONF_OPT_END
+
 #define DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(def) \
 DRI_CONF_OPT_BEGIN_B(dual_color_blend_by_location, def) \
        DRI_CONF_DESC(en,gettext("Identify dual color blending sources by location rather than index")) \
@@ -1 +1 @@
 .2.4
 .2.7