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14 Commits

Author SHA1 Message Date
Chad Versace
dad560939c anv: Advertise VK_EXT_image_drm_format_modifier 2019-08-01 16:36:00 -07:00
Chad Versace
178d22da49 WIP: anv: Fix assumptions broken by
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
2019-08-01 16:36:00 -07:00
Chad Versace
5d29487a44 FINISHME: anv: vkGetImageDrmFormatModifierPropertiesEXT 2019-08-01 16:36:00 -07:00
Chad Versace
489b735145 FINISHME: anv: Fix VkPhysicalDeviceExternalImageFormatInfo for VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT 2019-08-01 16:35:59 -07:00
Chad Versace
64a7c1174a FINISHME: anv: vkGetImageSubresourceLayout for VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT 2019-08-01 16:26:30 -07:00
Chad Versace
ba9eda13a7 FINISHME: anv: Support VkImageDrmFormatModifierExplicitCreateInfoEXT 2019-08-01 16:26:30 -07:00
Chad Versace
e37012b940 anv: Support VkImageDrmFormatModifierListCreateInfoEXT
A step toward support VK_EXT_image_drm_format_modifier.
2019-08-01 16:26:30 -07:00
Chad Versace
c20b8b9fee anv: Support VkPhysicalDeviceImageDrmFormatModifierInfoEXT
A step toward supporting VK_EXT_image_drm_format_modifier.
2019-08-01 15:57:28 -07:00
Chad Versace
8045a6538b anv: Rename param anv_get_image_format_properties()::info
Rename it to 'base_info', to distinguish it from 'drm_info' introduced
in upcoming commit.
2019-08-01 15:57:28 -07:00
Chad Versace
89f0c1d681 anv: Support VkDrmFormatModifierPropertiesListEXT
A step toward supporting VK_EXT_image_drm_format_modifier.
2019-08-01 15:57:25 -07:00
Chad Versace
77cc49c7a4 anv: Define struct anv_tiling
Refactor only. No intended behavioral change.

Much of the existing code assumes, with good justification, that tiling
is either VK_IMAGE_TILING_LINEAR or VK_IMAGE_TILING_OPTIMAL. But
VK_EXT_image_drm_format_modifier will void that assumption.

Some examples where currently valid assumptions become invalid:

    - Code written as
          if (tiling != VK_IMAGE_TILING_OPTIMAL)
      but whose true intent is
          if (tiling == VK_IMAGE_TILING_LINEAR)
      will break when tiling is VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.

    - Some code written as
          if (tilng == VK_IMAGE_TILING_LINEAR)
      will need updating to
          if (tiling == VK_IMAGE_TILING_LINEAR ||
              (tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT &&
               drm_format_mod == DRM_FORMAT_MOD_LINEAR))

    - Many query functions with a VkImageTiling parameter will require
      an additional parameter for the DRM format modifier.

The invalidity of many of the above cases become clearer if we generally abandon
using VkImageTiling to indicate tiling, and instead use a new type that
includes an optional DRM format modifier:

    struct anv_tiling {
        VkImageTiling vk;
        uint64_t drm_format_mod;
    };

This patch does not attempt to fix code with soon-to-be invalid
assumptions. Instead, it restricts itself to the following changes:

- Replace type of:
    - anv_get_format_features()::tiling
    - anv_get_format_plane()::tiling
    - anv_get_isl_format()::tiling
    - anv_image::tiling
- Fold anv_image::drm_format_mod into anv_image::tiling.
- Replace variables 'vk_tiling' with 'tiling.vk'.
2019-08-01 15:15:26 -07:00
Chad Versace
e94d1b12a5 anv: Reject linear depth/stencil in anv_get_format_plane()
anv_get_image_format_features() already reports that we do not support
linear images with depth/stencil formats. For consistency, teach
anv_get_format_plane() to do the same.
2019-08-01 14:29:06 -07:00
Chad Versace
5fb6ee5620 anv: Refactor struct anv_image_create_info
The field 'isl_tiling_flags' offered more flexibility than needed. The
driver set at most one flag, and when set the driver translated the sole
flag into a DRM format modifier. This patch enforces that convention by
replacing field 'isl_tiling_flags' with 'drm_format_mod'.

Now anv_image_create_info's behavior when overriding tiling is aligned
with VK_EXT_image_drm_format_modifier; that is,
anv_image_create_info::drm_format_mod is analagous to
VkImageDrmFormatModifierExplicitCreateInfoEXT::drmFormatModifier.
2019-08-01 14:27:24 -07:00
Chad Versace
2772852437 anv: Include drm_fourcc.h in anv_private.h
To allow use of DRM_FORMAT_MOD_INVALID in future inline functions for
struct anv_tiling.
2019-08-01 14:26:33 -07:00
914 changed files with 17202 additions and 36814 deletions

View File

@@ -14,7 +14,7 @@
# repository's registry will be used there as well.
variables:
UPSTREAM_REPO: mesa/mesa
DEBIAN_TAG: "2019-08-09"
DEBIAN_TAG: "2019-07-23"
DEBIAN_VERSION: stretch-slim
DEBIAN_IMAGE: "$CI_REGISTRY_IMAGE/debian/$DEBIAN_VERSION:$DEBIAN_TAG"
@@ -26,7 +26,6 @@ include:
stages:
- containers-build
- build+test
- test
# When to automatically run the CI
@@ -40,14 +39,6 @@ stages:
when:
- runner_system_failure
.ci-deqp-artifacts: &ci-deqp-artifacts
artifacts:
when: always
untracked: false
paths:
# Watch out! Artifacts are relative to the build dir.
# https://gitlab.com/gitlab-org/gitlab-ce/commit/8788fb925706cad594adf6917a6c5f6587dd1521
- artifacts
# CONTAINERS
@@ -86,12 +77,6 @@ debian:
- ccache --zero-stats || true
- ccache --show-stats || true
after_script:
# In case the install dir is being saved as artifacts, tar it up
# so that symlinks and hardlinks aren't each packed separately in
# the zip file.
- if [ -d install ]; then
tar -cf artifacts/install.tar install;
fi
- export CCACHE_DIR="$PWD/ccache"
- ccache --show-stats
@@ -115,8 +100,12 @@ debian:
# gallium drivers combined.
# Start this early so that it doesn't limit the total run time.
#
# We also stick the glvnd build here, since we want non-glvnd in
# meson-main for actual driver CI.
# We also put softpipe (and therefore gallium nine, which requires
# it) here, since softpipe/llvmpipe can't be built alongside classic
# swrast.
#
# Putting glvnd here is arbitrary, but we want it in one of the builds
# for coverage.
meson-swr-glvnd:
extends: .meson-build
variables:
@@ -131,9 +120,10 @@ meson-swr-glvnd:
-D gallium-omx=disabled
-D gallium-va=false
-D gallium-xa=false
-D gallium-nine=false
-D gallium-nine=true
-D gallium-opencl=disabled
GALLIUM_DRIVERS: "swr,iris"
-D osmesa=gallium
GALLIUM_DRIVERS: "swr,swrast,iris"
LLVM_VERSION: "6.0"
meson-clang:
@@ -173,25 +163,24 @@ meson-main:
-D gbm=true
-D egl=true
-D platforms=x11,wayland,drm,surfaceless
DRI_DRIVERS: "i915,i965,r100,r200,nouveau"
-D osmesa=classic
DRI_DRIVERS: "i915,i965,r100,r200,swrast,nouveau"
GALLIUM_ST: >
-D dri3=true
-D tools=drm-shim
-D gallium-extra-hud=true
-D gallium-vdpau=true
-D gallium-xvmc=true
-D gallium-omx=bellagio
-D gallium-va=true
-D gallium-xa=true
-D gallium-nine=true
-D gallium-nine=false
-D gallium-opencl=disabled
GALLIUM_DRIVERS: "iris,nouveau,kmsro,r300,r600,freedreno,swrast,svga,v3d,vc4,virgl,etnaviv,panfrost,lima"
GALLIUM_DRIVERS: "iris,nouveau,kmsro,r300,r600,freedreno,svga,v3d,vc4,virgl,etnaviv,panfrost,lima"
LLVM_VERSION: "7"
EXTRA_OPTION: >
-D osmesa=gallium
-D tools=all
MESON_SHADERDB: "true"
BUILDTYPE: "debugoptimized"
<<: *ci-deqp-artifacts
meson-clover:
extends: .meson-build
@@ -263,14 +252,19 @@ meson-vulkan:
-D gallium-xa=false
-D gallium-nine=false
-D llvm=false
<<: *ci-deqp-artifacts
CROSS: >
--cross /tmp/cross_file.txt
script:
- /usr/share/meson/debcrossgen --arch ${ARCH} -o /tmp/cross_file.txt
# Work around a bug in debcrossgen that should be fixed in the next release
- sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" /tmp/cross_file.txt
- .gitlab-ci/meson-build.sh
meson-armhf:
extends: .meson-cross
variables:
CROSS: armhf
ARCH: armhf
VULKAN_DRIVERS: freedreno
GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,tegra,v3d,vc4"
# Disable the tests since we're cross compiling.
@@ -282,7 +276,7 @@ meson-armhf:
meson-arm64:
extends: .meson-cross
variables:
CROSS: arm64
ARCH: arm64
VULKAN_DRIVERS: freedreno
GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,tegra,v3d,vc4"
# Disable the tests since we're cross compiling.
@@ -291,23 +285,17 @@ meson-arm64:
-D I-love-half-baked-turnips=true
-D vulkan-overlay-layer=true
# While the main point of this build is testing the i386 cross build,
# we also use this one to test some other options that are exclusive
# with meson-main's choices (classic swrast and osmesa)
meson-i386:
extends: .meson-cross
variables:
CROSS: i386
ARCH: i386
VULKAN_DRIVERS: intel
DRI_DRIVERS: "swrast"
GALLIUM_DRIVERS: "iris"
GALLIUM_DRIVERS: "swrast"
# Disable i386 tests, because u_format_tests gets precision
# failures in dxtn unpacking
EXTRA_OPTION: >
-D build-tests=false
-D vulkan-overlay-layer=true
-D llvm=false
-D osmesa=classic
scons-nollvm:
extends: .scons-build
@@ -323,60 +311,3 @@ scons-llvm:
LLVM_VERSION: "3.4"
# LLVM 3.4 packages were built with an old libstdc++ ABI
CXX: "g++ -D_GLIBCXX_USE_CXX11_ABI=0"
.deqp-test:
<<: *ci-run-policy
stage: test
image: $DEBIAN_IMAGE
variables:
GIT_STRATEGY: none # testing doesn't build anything from source
DEQP_SKIPS: deqp-default-skips.txt
script:
# Note: Build dir (and thus install) may be dirty due to GIT_STRATEGY
- rm -rf install
- tar -xf artifacts/install.tar
- ./artifacts/deqp-runner.sh
artifacts:
when: on_failure
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
- results/
test-llvmpipe-gles2:
parallel: 4
variables:
DEQP_VER: gles2
DEQP_EXPECTED_FAILS: deqp-llvmpipe-fails.txt
LIBGL_ALWAYS_SOFTWARE: "true"
DEQP_RENDERER_MATCH: "llvmpipe"
extends: .deqp-test
dependencies:
- meson-main
test-softpipe-gles2:
parallel: 4
variables:
DEQP_VER: gles2
DEQP_EXPECTED_FAILS: deqp-softpipe-fails.txt
LIBGL_ALWAYS_SOFTWARE: "true"
DEQP_RENDERER_MATCH: "softpipe"
GALLIUM_DRIVER: "softpipe"
extends: .deqp-test
dependencies:
- meson-main
# The GLES2 CTS run takes about 8 minutes of CPU time, while GLES3 is
# 25 minutes. Until we can get its runtime down, just do a partial
# (every 10 tests) run.
test-softpipe-gles3-limited:
variables:
DEQP_VER: gles3
DEQP_EXPECTED_FAILS: deqp-softpipe-fails.txt
LIBGL_ALWAYS_SOFTWARE: "true"
DEQP_RENDERER_MATCH: "softpipe"
GALLIUM_DRIVER: "softpipe"
CI_NODE_INDEX: 1
CI_NODE_TOTAL: 10
extends: .deqp-test
dependencies:
- meson-main

View File

@@ -49,7 +49,6 @@ echo "deb https://deb.debian.org/debian/ buster main" >/etc/apt/sources.list.d/b
echo "deb https://deb.debian.org/debian/ buster-updates main" >/etc/apt/sources.list.d/buster-updates.list
apt-get update
apt-get install -y \
git \
bzip2 \
zlib1g-dev \
pkg-config \
@@ -70,18 +69,19 @@ apt-get install -y \
libelf-dev \
libunwind-dev \
libglvnd-dev \
libgtk-3-dev \
libpng-dev \
libgbm-dev \
libgles2-mesa-dev \
python-mako \
python3-mako \
meson \
scons
# autotools build deps
apt-get install -y \
automake \
libtool \
bison \
flex \
gettext \
cmake \
meson \
scons
make
# Cross-build Mesa deps
for arch in $CROSS_ARCHITECTURES; do
@@ -120,14 +120,14 @@ export DRI2PROTO_VERSION=dri2proto-2.8
export LIBPCIACCESS_VERSION=libpciaccess-0.13.4
export LIBDRM_VERSION=libdrm-2.4.99
export XCBPROTO_VERSION=xcb-proto-1.13
export RANDRPROTO_VERSION=randrproto-1.5.0
export LIBXRANDR_VERSION=libXrandr-1.5.0
export RANDRPROTO_VERSION=randrproto-1.3.0
export LIBXRANDR_VERSION=libXrandr-1.3.0
export LIBXCB_VERSION=libxcb-1.13
export LIBXSHMFENCE_VERSION=libxshmfence-1.3
export LIBVDPAU_VERSION=libvdpau-1.1
export LIBVA_VERSION=libva-1.7.0
export LIBWAYLAND_VERSION=wayland-1.15.0
export WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.12
export WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
wget $XORG_RELEASES/util/$XORGMACROS_VERSION.tar.bz2
tar -xvf $XORGMACROS_VERSION.tar.bz2 && rm $XORGMACROS_VERSION.tar.bz2
@@ -212,74 +212,13 @@ apt-get install -y ccache
# We need xmllint to validate the XML files in Mesa
apt-get install -y libxml2-utils
# Generate cross build files for Meson
for arch in $CROSS_ARCHITECTURES; do
cross_file="/cross_file-$arch.txt"
/usr/share/meson/debcrossgen --arch "$arch" -o "$cross_file"
# Work around a bug in debcrossgen that should be fixed in the next release
if [ "$arch" = "i386" ]; then
sed -i "s|cpu_family = 'i686'|cpu_family = 'x86'|g" "$cross_file"
fi
done
############### Build dEQP
git config --global user.email "mesa@example.com"
git config --global user.name "Mesa CI"
# XXX: Use --depth 1 once we can drop the cherry-picks.
git clone \
https://github.com/KhronosGroup/VK-GL-CTS.git \
-b opengl-es-cts-3.2.5.1 \
/VK-GL-CTS
cd /VK-GL-CTS
# Fix surfaceless build
git cherry-pick -x 22f41e5e321c6dcd8569c4dad91bce89f06b3670
git cherry-pick -x 1daa8dff73161ea60ead965bd6c9f2a0a2165648
# surfaceless links against libkms and such despite not using it.
sed -i '/gbm/d' targets/surfaceless/surfaceless.cmake
sed -i '/libkms/d' targets/surfaceless/surfaceless.cmake
sed -i '/libgbm/d' targets/surfaceless/surfaceless.cmake
python3 external/fetch_sources.py
mkdir -p /deqp
cd /deqp
cmake -G Ninja \
-DDEQP_TARGET=surfaceless \
-DCMAKE_BUILD_TYPE=Release \
/VK-GL-CTS
ninja
# Copy out the mustpass lists we want from a bunch of other junk.
mkdir /deqp/mustpass
for gles in gles2 gles3 gles31; do
cp \
/deqp/external/openglcts/modules/gl_cts/data/mustpass/gles/aosp_mustpass/3.2.5.x/$gles-master.txt \
/deqp/mustpass/$gles-master.txt
done
# Remove the rest of the build products that we don't need.
rm -rf /deqp/external
rm -rf /deqp/modules/internal
rm -rf /deqp/executor
rm -rf /deqp/execserver
rm -rf /deqp/modules/egl
rm -rf /deqp/framework
du -sh *
rm -rf /VK-GL-CTS
############### Uninstall the build software
# Remove unused packages
apt-get purge -y \
automake \
git \
libtool \
curl \
unzip \
gnupg \
cmake \
git \
libgles2-mesa-dev \
libgbm-dev
software-properties-common
apt-get autoremove -y --purge

View File

@@ -1,10 +0,0 @@
# Note: skips lists for CI are just a list of lines that, when
# non-zero-length and not starting with '#', will regex match to
# delete lines from the test list. Be careful.
# Skip the perf/stress tests to keep runtime manageable
dEQP-GLES[0-9]*.performance
dEQP-GLES[0-9]*.stress
# These are really slow on tiling architectures (including llvmpipe).
dEQP-GLES[0-9]*.functional.flush_finish

View File

@@ -1,124 +0,0 @@
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES2.functional.clipping.point.wide_point_clip
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_center
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_corner
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_neg_y_neg_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_pos_y_pos_z_and_neg_x_neg_y_neg_z
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.color_clear.rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.depth.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.no_rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_depthbuffer.rebind_rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.no_rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.recreate_stencilbuffer.rebind_rbo_rgba4_stencil_index8
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4
dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.fbo.render.shared_depthbuffer.rbo_rgba4_depth_component16
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
dEQP-GLES2.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide
dEQP-GLES2.functional.rasterization.limits.points
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2d_bias
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2dproj_vec3_bias
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2dproj_vec4_bias
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_linear_clamp_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_linear_mirror_etc1
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_linear_mirror_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_linear_repeat_etc1
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_linear_repeat_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_clamp_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_mirror_etc1
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_mirror_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_repeat_etc1
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_repeat_l8
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_repeat_rgb888
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_repeat_rgba4444
dEQP-GLES2.functional.texture.filtering.2d.linear_mipmap_linear_nearest_repeat_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_linear_clamp_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_linear_mirror_etc1
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_linear_mirror_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_linear_repeat_etc1
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_linear_repeat_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_clamp_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_mirror_etc1
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_mirror_rgba8888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_repeat_etc1
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_repeat_l8
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_repeat_rgb888
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_repeat_rgba4444
dEQP-GLES2.functional.texture.filtering.2d.nearest_mipmap_linear_nearest_repeat_rgba8888
dEQP-GLES2.functional.texture.mipmap.2d.affine.linear_linear_repeat
dEQP-GLES2.functional.texture.mipmap.2d.affine.nearest_linear_clamp
dEQP-GLES2.functional.texture.mipmap.2d.affine.nearest_linear_mirror
dEQP-GLES2.functional.texture.mipmap.2d.affine.nearest_linear_repeat
dEQP-GLES2.functional.texture.mipmap.2d.basic.linear_linear_repeat
dEQP-GLES2.functional.texture.mipmap.2d.basic.linear_linear_repeat_non_square
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_clamp
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_clamp_non_square
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_mirror
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_mirror_non_square
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_repeat
dEQP-GLES2.functional.texture.mipmap.2d.basic.nearest_linear_repeat_non_square
dEQP-GLES2.functional.texture.mipmap.2d.projected.linear_linear_repeat
dEQP-GLES2.functional.texture.mipmap.2d.projected.nearest_linear_clamp
dEQP-GLES2.functional.texture.mipmap.2d.projected.nearest_linear_mirror
dEQP-GLES2.functional.texture.mipmap.2d.projected.nearest_linear_repeat
dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_linear
dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_nearest
dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_linear
dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_nearest
dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_linear
dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_nearest
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.linear_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.2d.filtering.nearest_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.mirror_repeat
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_clamp
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_mirror
dEQP-GLES2.functional.texture.vertex.2d.wrap.repeat_repeat
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_clamp
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_mirror
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_linear_repeat
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_nearest_clamp
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_nearest_mirror
dEQP-GLES2.functional.texture.vertex.cube.filtering.nearest_mipmap_linear_nearest_repeat
dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_clamp
dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_mirror
dEQP-GLES2.functional.texture.vertex.cube.wrap.clamp_repeat
dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_clamp
dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_mirror
dEQP-GLES2.functional.texture.vertex.cube.wrap.mirror_repeat
dEQP-GLES2.functional.texture.vertex.cube.wrap.repeat_clamp
dEQP-GLES2.functional.texture.vertex.cube.wrap.repeat_mirror
dEQP-GLES2.functional.texture.vertex.cube.wrap.repeat_repeat

View File

@@ -1,112 +0,0 @@
#!/bin/bash
set -ex
DEQP_OPTIONS=(--deqp-surface-width=256 --deqp-surface-height=256)
DEQP_OPTIONS+=(--deqp-surface-type=pbuffer)
DEQP_OPTIONS+=(--deqp-gl-config-name=rgba8888d24s8ms0)
DEQP_OPTIONS+=(--deqp-visibility=hidden)
DEQP_OPTIONS+=(--deqp-log-images=disable)
DEQP_OPTIONS+=(--deqp-watchdog=enable)
DEQP_OPTIONS+=(--deqp-crashhandler=enable)
if [ -z "$DEQP_VER" ]; then
echo 'DEQP_VER must be set to something like "gles2" or "gles31" for the test run'
exit 1
fi
if [ -z "$DEQP_SKIPS" ]; then
echo 'DEQP_SKIPS must be set to something like "deqp-default-skips.txt"'
exit 1
fi
# Prep the expected failure list
if [ -n "$DEQP_EXPECTED_FAILS" ]; then
export DEQP_EXPECTED_FAILS=`pwd`/artifacts/$DEQP_EXPECTED_FAILS
else
export DEQP_EXPECTED_FAILS=/tmp/expect-no-failures.txt
touch $DEQP_EXPECTED_FAILS
fi
sort < $DEQP_EXPECTED_FAILS > /tmp/expected-fails.txt
# Fix relative paths on inputs.
export DEQP_SKIPS=`pwd`/artifacts/$DEQP_SKIPS
# Be a good citizen on the shared runners.
export LP_NUM_THREADS=4
# Set up the driver environment.
export LD_LIBRARY_PATH=`pwd`/install/lib/
export EGL_PLATFORM=surfaceless
# the runner was failing to look for libkms in /usr/local/lib for some reason
# I never figured out.
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/lib
RESULTS=`pwd`/results
mkdir -p $RESULTS
cd /deqp/modules/$DEQP_VER
# Generate test case list file
cp /deqp/mustpass/$DEQP_VER-master.txt /tmp/case-list.txt
# Note: not using sorted input and comm, becuase I want to run the tests in
# the same order that dEQP would.
while read -r line; do
if echo "$line" | grep -q '^[^#]'; then
sed -i "/$line/d" /tmp/case-list.txt
fi
done < $DEQP_SKIPS
# If the job is parallel, take the corresponding fraction of the caselist.
# Note: N~M is a gnu sed extension to match every nth line (first line is #1).
if [ -n "$CI_NODE_INDEX" ]; then
sed -ni $CI_NODE_INDEX~$CI_NODE_TOTAL"p" /tmp/case-list.txt
fi
if [ ! -s /tmp/case-list.txt ]; then
echo "Caselist generation failed"
exit 1
fi
# Cannot use tee because dash doesn't have pipefail
touch /tmp/result.txt
tail -f /tmp/result.txt &
./deqp-$DEQP_VER "${DEQP_OPTIONS[@]}" --deqp-log-filename=$RESULTS/results.qpa --deqp-caselist-file=/tmp/case-list.txt >> /tmp/result.txt
DEQP_EXITCODE=$?
sed -ne \
'/StatusCode="Fail"/{x;p}; s/#beginTestCaseResult //; T; h' \
$RESULTS/results.qpa \
> /tmp/unsorted-fails.txt
# Scrape out the renderer that the test run used, so we can validate that the
# right driver was used.
if grep -q "dEQP-.*.info.renderer" /tmp/case-list.txt; then
# This is an ugly dependency on the .qpa format: Print 3 lines after the
# match, which happens to contain the result.
RENDERER=`sed -n '/#beginTestCaseResult dEQP-.*.info.renderer/{n;n;n;p}' $RESULTS/results.qpa | sed -n -E "s|<Text>(.*)</Text>|\1|p"`
echo "GL_RENDERER for this test run: $RENDERER"
if [ -n "$DEQP_RENDERER_MATCH" ]; then
echo $RENDERER | grep -q $DEQP_RENDERER_MATCH > /dev/null
fi
fi
if [ $DEQP_EXITCODE -ne 0 ]; then
exit $DEQP_EXITCODE
fi
sort < /tmp/unsorted-fails.txt > $RESULTS/fails.txt
comm -23 $RESULTS/fails.txt /tmp/expected-fails.txt > /tmp/new-fails.txt
if [ -s /tmp/new-fails.txt ]; then
echo "Unexpected failures:"
cat /tmp/new-fails.txt
exit 1
else
echo "No new failures"
fi

View File

@@ -1,445 +0,0 @@
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES2.functional.clipping.point.wide_point_clip
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_center
dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_corner
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_neg_y_neg_z_and_neg_x_neg_y_pos_z
dEQP-GLES2.functional.clipping.triangle_vertex.clip_two.clip_pos_y_pos_z_and_neg_x_neg_y_neg_z
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
dEQP-GLES2.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide
dEQP-GLES2.functional.rasterization.limits.points
dEQP-GLES2.functional.rasterization.primitives.points
dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_center
dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_corner
dEQP-GLES3.functional.clipping.point.wide_point_clip
dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_center
dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_corner
dEQP-GLES3.functional.clipping.triangle_vertex.clip_two.clip_neg_y_neg_z_and_neg_x_neg_y_pos_z
dEQP-GLES3.functional.clipping.triangle_vertex.clip_two.clip_pos_y_pos_z_and_neg_x_neg_y_neg_z
dEQP-GLES3.functional.draw.random.124
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth24_stencil8
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth32f_stencil8
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth_component16
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth_component24
dEQP-GLES3.functional.fbo.depth.depth_test_clamp.depth_component32f
dEQP-GLES3.functional.fbo.depth.depth_write_clamp.depth32f_stencil8
dEQP-GLES3.functional.fbo.depth.depth_write_clamp.depth_component32f
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_color
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_depth
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_depth_stencil
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_stencil
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_color
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_depth
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_depth_stencil
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_stencil
dEQP-GLES3.functional.fbo.msaa.2_samples.depth24_stencil8
dEQP-GLES3.functional.fbo.msaa.2_samples.depth32f_stencil8
dEQP-GLES3.functional.fbo.msaa.2_samples.depth_component16
dEQP-GLES3.functional.fbo.msaa.2_samples.depth_component24
dEQP-GLES3.functional.fbo.msaa.2_samples.depth_component32f
dEQP-GLES3.functional.fbo.msaa.2_samples.r11f_g11f_b10f
dEQP-GLES3.functional.fbo.msaa.2_samples.r16f
dEQP-GLES3.functional.fbo.msaa.2_samples.r8
dEQP-GLES3.functional.fbo.msaa.2_samples.rg16f
dEQP-GLES3.functional.fbo.msaa.2_samples.rg8
dEQP-GLES3.functional.fbo.msaa.2_samples.rgb10_a2
dEQP-GLES3.functional.fbo.msaa.2_samples.rgb565
dEQP-GLES3.functional.fbo.msaa.2_samples.rgb5_a1
dEQP-GLES3.functional.fbo.msaa.2_samples.rgb8
dEQP-GLES3.functional.fbo.msaa.2_samples.rgba4
dEQP-GLES3.functional.fbo.msaa.2_samples.rgba8
dEQP-GLES3.functional.fbo.msaa.2_samples.srgb8_alpha8
dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
dEQP-GLES3.functional.fbo.msaa.4_samples.depth24_stencil8
dEQP-GLES3.functional.fbo.msaa.4_samples.depth32f_stencil8
dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component16
dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component24
dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component32f
dEQP-GLES3.functional.fbo.msaa.4_samples.r11f_g11f_b10f
dEQP-GLES3.functional.fbo.msaa.4_samples.r16f
dEQP-GLES3.functional.fbo.msaa.4_samples.r8
dEQP-GLES3.functional.fbo.msaa.4_samples.rg16f
dEQP-GLES3.functional.fbo.msaa.4_samples.rg8
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb10_a2
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb565
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb5_a1
dEQP-GLES3.functional.fbo.msaa.4_samples.rgb8
dEQP-GLES3.functional.fbo.msaa.4_samples.rgba4
dEQP-GLES3.functional.fbo.msaa.4_samples.rgba8
dEQP-GLES3.functional.fbo.msaa.4_samples.srgb8_alpha8
dEQP-GLES3.functional.fbo.msaa.4_samples.stencil_index8
dEQP-GLES3.functional.multisample.fbo_max_samples.proportionality_alpha_to_coverage
dEQP-GLES3.functional.multisample.fbo_max_samples.proportionality_sample_coverage
dEQP-GLES3.functional.multisample.fbo_max_samples.proportionality_sample_coverage_inverted
dEQP-GLES3.functional.multisample.fbo_max_samples.sample_coverage_invert
dEQP-GLES3.functional.negative_api.buffer.blit_framebuffer_multisample
dEQP-GLES3.functional.negative_api.buffer.read_pixels_fbo_format_mismatch
dEQP-GLES3.functional.polygon_offset.default_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed24_displacement_with_units
dEQP-GLES3.functional.polygon_offset.float32_displacement_with_units
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.primitives.points
dEQP-GLES3.functional.rasterization.fbo.texture_2d.interpolation.lines_wide
dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.points
dEQP-GLES3.functional.rasterization.interpolation.basic.line_loop_wide
dEQP-GLES3.functional.rasterization.interpolation.basic.line_strip_wide
dEQP-GLES3.functional.rasterization.interpolation.basic.lines_wide
dEQP-GLES3.functional.rasterization.interpolation.projected.line_loop_wide
dEQP-GLES3.functional.rasterization.interpolation.projected.line_strip_wide
dEQP-GLES3.functional.rasterization.interpolation.projected.lines_wide
dEQP-GLES3.functional.rasterization.primitives.points
dEQP-GLES3.functional.rasterizer_discard.basic.write_depth_points
dEQP-GLES3.functional.rasterizer_discard.basic.write_stencil_points
dEQP-GLES3.functional.rasterizer_discard.fbo.write_depth_points
dEQP-GLES3.functional.rasterizer_discard.fbo.write_stencil_points
dEQP-GLES3.functional.rasterizer_discard.scissor.write_depth_points
dEQP-GLES3.functional.rasterizer_discard.scissor.write_stencil_points
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa2.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.nicest.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fastest.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa2.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec2_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec2_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec3_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec3_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec4_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.fbo_msaa4.vec4_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.float_highp
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.float_mediump
dEQP-GLES3.functional.shaders.derivate.dfdy.nicest.fbo_msaa4.vec2_highp
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dEQP-GLES3.functional.texture.filtering.3d.sizes.63x63x63_linear
dEQP-GLES3.functional.texture.filtering.3d.sizes.63x63x63_linear_mipmap_linear
dEQP-GLES3.functional.texture.filtering.3d.sizes.63x63x63_linear_mipmap_nearest
dEQP-GLES3.functional.texture.filtering.3d.sizes.63x63x63_nearest_mipmap_linear
dEQP-GLES3.functional.texture.filtering.3d.sizes.63x63x63_nearest_mipmap_nearest
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_linear_clamp
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_linear_mirror
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_linear_clamp
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_linear_mirror
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_nearest_clamp
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_nearest_mirror
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_linear_nearest_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_mipmap_nearest_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_nearest_clamp
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_nearest_mirror
dEQP-GLES3.functional.texture.vertex.3d.filtering.linear_nearest_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.nearest_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.nearest_mipmap_linear_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.filtering.nearest_mipmap_nearest_linear_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_clamp_clamp
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_clamp_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_clamp_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_mirror_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_mirror_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_repeat_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.clamp_repeat_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_clamp_clamp
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_clamp_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_clamp_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_mirror_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_mirror_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_repeat_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.mirror_repeat_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_clamp_clamp
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_clamp_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_clamp_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_mirror_clamp
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_mirror_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_mirror_repeat
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_repeat_clamp
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_repeat_mirror
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_repeat_repeat
dEQP-GLES3.functional.texture.wrap.astc_8x8.repeat_repeat_linear_divisible
dEQP-GLES3.functional.texture.wrap.astc_8x8.repeat_repeat_linear_not_divisible
dEQP-GLES3.functional.texture.wrap.astc_8x8_srgb.repeat_repeat_linear_divisible
dEQP-GLES3.functional.texture.wrap.astc_8x8_srgb.repeat_repeat_linear_not_divisible
dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads1
dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads256

View File

@@ -16,10 +16,9 @@ fi
rm -rf _build
meson _build --native-file=native.file \
${CROSS+--cross /cross_file-$CROSS.txt} \
-D prefix=`pwd`/install \
${CROSS} \
-D libdir=lib \
-D buildtype=${BUILDTYPE:-debug} \
-D buildtype=debug \
-D build-tests=true \
-D libunwind=${UNWIND} \
${DRI_LOADERS} \
@@ -33,30 +32,9 @@ cd _build
meson configure
ninja -j4
LC_ALL=C.UTF-8 ninja test
ninja install
DESTDIR=$PWD/../install ninja install
cd ..
if test -n "$MESON_SHADERDB"; then
./.gitlab-ci/run-shader-db.sh;
fi
# Delete 2MB of includes from artifacts.
rm -rf install/include
# Strip the drivers in the artifacts to cut 80% of the artifacts size.
if [ -n "$CROSS" ]; then
STRIP=`sed -n -E "s/strip\s*=\s*'(.*)'/\1/p" /cross_file-$CROSS.txt`
if [ -z "$STRIP" ]; then
echo "Failed to find strip command in cross file"
exit 1
fi
else
STRIP="strip"
fi
find install -name \*.so -exec $STRIP {} \;
# Test runs don't pull down the git tree, so put the dEQP helper
# script and associated bits there.
mkdir -p artifacts/
cp -Rp .gitlab-ci/deqp* artifacts/
# cp -Rp src/freedreno/ci/expected* artifacts/

View File

@@ -5,8 +5,8 @@ ARTIFACTSDIR=`pwd`/shader-db
mkdir -p $ARTIFACTSDIR
export DRM_SHIM_DEBUG=true
LIBDIR=`pwd`/install/lib
export LD_LIBRARY_PATH=$LIBDIR
LIBDIR=`pwd`/install/usr/local/lib
export LIBGL_DRIVERS_PATH=$LIBDIR/dri
cd /usr/local/shader-db

View File

@@ -9,22 +9,8 @@ env:
global:
- PKG_CONFIG_PATH=""
matrix:
include:
- env:
- BUILD=meson
- env:
- BUILD=scons
before_install:
- HOMEBREW_NO_AUTO_UPDATE=1 brew install expat gettext
- if test "x$BUILD" = xmeson; then
HOMEBREW_NO_AUTO_UPDATE=1 brew install python3 ninja;
fi
- if test "x$BUILD" = xscons; then
HOMEBREW_NO_AUTO_UPDATE=1 brew install python2 scons;
fi
- HOMEBREW_NO_AUTO_UPDATE=1 brew install python3 ninja expat gettext
# Set PATH for homebrew pip3 installs
- PATH="$HOME/Library/Python/3.6/bin:${PATH}"
# Set PKG_CONFIG_PATH for keg-only expat
@@ -42,21 +28,10 @@ before_install:
- PKG_CONFIG_PATH="/opt/X11/share/pkgconfig:/opt/X11/lib/pkgconfig:${PKG_CONFIG_PATH}"
install:
- if test "x$BUILD" = xmeson; then
pip3 install --user meson;
pip3 install --user mako;
fi
- if test "x$BUILD" = xscons; then
pip2 install --user mako;
fi
- pip3 install --user meson
- pip3 install --user mako
script:
- if test "x$BUILD" = xmeson; then
meson _build -Dbuild-tests=true;
ninja -C _build || travis_terminate 1;
ninja -C _build test || travis_terminate 1;
fi
- if test "x$BUILD" = xscons; then
scons || travis_terminate 1;
scons check || travis_terminate 1;
fi
- meson _build -Dbuild-tests=true
- ninja -C _build
- ninja -C _build test

View File

@@ -39,7 +39,7 @@ LOCAL_CFLAGS += \
-Wno-initializer-overrides \
-Wno-mismatched-tags \
-DPACKAGE_VERSION=\"$(MESA_VERSION)\" \
-DPACKAGE_BUGREPORT=\"https://gitlab.freedesktop.org/mesa/mesa/issues\"
-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"
# XXX: The following __STDC_*_MACROS defines should not be needed.
# It's likely due to a bug elsewhere, but let's temporarily add them
@@ -103,12 +103,9 @@ ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 26 && echo true),true)
LOCAL_CFLAGS += -DHAVE_SYS_SHM_H
endif
ifeq ($(strip $(MESA_ENABLE_ASM)),true)
ifeq ($(TARGET_ARCH),x86)
LOCAL_CFLAGS += \
-DUSE_X86_ASM
endif
endif
ifeq ($(ARCH_ARM_HAVE_NEON),true)
LOCAL_CFLAGS_arm += -DUSE_ARM_ASM

View File

@@ -83,13 +83,6 @@ endif
$(foreach d, $(MESA_BUILD_CLASSIC) $(MESA_BUILD_GALLIUM), $(eval $(d) := true))
# host and target must be the same arch to generate matypes.h
ifeq ($(TARGET_ARCH),$(HOST_ARCH))
MESA_ENABLE_ASM := true
else
MESA_ENABLE_ASM := false
endif
ifneq ($(filter true, $(HAVE_GALLIUM_RADEONSI)),)
MESA_ENABLE_LLVM := true
endif
@@ -122,8 +115,7 @@ SUBDIRS := \
src/broadcom \
src/intel \
src/mesa/drivers/dri \
src/vulkan \
src/panfrost \
src/vulkan
INC_DIRS := $(call all-named-subdir-makefiles,$(SUBDIRS))
INC_DIRS += $(call all-named-subdir-makefiles,src/gallium)

View File

@@ -73,7 +73,7 @@ with open("VERSION") as f:
mesa_version = f.read().strip()
env.Append(CPPDEFINES = [
('PACKAGE_VERSION', '\\"%s\\"' % mesa_version),
('PACKAGE_BUGREPORT', '\\"https://gitlab.freedesktop.org/mesa/mesa/issues\\"'),
('PACKAGE_BUGREPORT', '\\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\\"'),
])
# Includes

View File

@@ -1 +1 @@
19.2.4
19.2.0-devel

View File

@@ -1,29 +0,0 @@
# warnings that are not useful
da5ebe30105f70e3520ce3ae145793b755552569
6b8cb087568699ca9a6e9e8b7bf49179e622b59f
# Jason doesn't want this applied to 19.2 (it's a revert)
d15fe8ca8262d502435c4f83985ac414f950bc5f
# This doesn't apply to 19.2
f833b4cada07b746a10ffa4d93fcd821920c3cb1
d2db43fcad6a2ea2070ff5f7884411f4b7d3925c
66f2aa6ccd0b226eebe2c1a46281160b0a54d522
# The author requested that this not be applied to 19.2
dcc0e23438f3e5929c2ef74d57e8207be25ecb41
# This doesn't apply cleanly, and no one really cares about this file on stable
# branches anyway.
bcd9224728dcb8d8fe4bcddc4bd9b2c36fcfe9dd
# De-nominated by its author due to alternate fix not being backported
43041627445540afda1a05d11861935963660344
# This is immediately reverted, so just don't apply
19546108d3dd5541a189e36df4ea83b3f519e48f
# The authors requested these not be applied to 19.2
869e32593a9096b845dd6106f8f86e1c41fac968
a2c3c65a31de90fdb55f76f2894860dfbafe2043
bb0c5c487e63e88acbb792f092dd8f392bad8540

View File

35
bin/bugzilla_mesa.sh Executable file
View File

@@ -0,0 +1,35 @@
#!/bin/sh
# This script is used to generate the list of fixed bugs that
# appears in the release notes files, with HTML formatting.
#
# Note: This script could take a while until all details have
# been fetched from bugzilla.
#
# Usage examples:
#
# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3
# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 > bugfixes
# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee bugfixes
# regex pattern: trim before bug number
trim_before='s/.*show_bug.cgi?id=\([0-9]*\).*/\1/'
# regex pattern: reconstruct the url
use_after='s,^,https://bugs.freedesktop.org/show_bug.cgi?id=,'
echo "<ul>"
echo ""
# extract fdo urls from commit log
git log --pretty=medium $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before | sort -n -u | sed -e $use_after |\
while read url
do
id=$(echo $url | cut -d'=' -f2)
summary=$(wget --quiet -O - $url | grep -e '<title>.*</title>' | sed -e 's/ *<title>[0-9]\+ &ndash; \(.*\)<\/title>/\1/')
echo "<li><a href=\"$url\">Bug $id</a> - $summary</li>"
echo ""
done
echo "</ul>"

View File

@@ -1,272 +0,0 @@
#!/usr/bin/env python3
# Copyright © 2019 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
"""Generates release notes for a given version of mesa."""
import asyncio
import datetime
import os
import pathlib
import sys
import textwrap
import typing
import urllib.parse
import aiohttp
from mako.template import Template
from mako import exceptions
CURRENT_GL_VERSION = '4.5'
CURRENT_VK_VERSION = '1.1'
TEMPLATE = Template(textwrap.dedent("""\
<%!
import html
%>
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa ${next_version} Release Notes / ${today}</h1>
<p>
%if not bugfix:
Mesa ${next_version} is a new development release. People who are concerned
with stability and reliability should stick with a previous release or
wait for Mesa ${version[:-1]}1.
%else:
Mesa ${next_version} is a bug fix release which fixes bugs found since the ${version} release.
%endif
</p>
<p>
Mesa ${next_version} implements the OpenGL ${gl_version} API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL ${gl_version}. OpenGL
${gl_version} is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa ${next_version} implements the Vulkan ${vk_version} API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksum</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<ul>
%for f in features:
<li>${html.escape(f)}</li>
%endfor
</ul>
<h2>Bug fixes</h2>
<ul>
%for b in bugs:
<li>${html.escape(b)}</li>
%endfor
</ul>
<h2>Changes</h2>
<ul>
%for c, author in changes:
%if author:
<p>${html.escape(c)}</p>
%else:
<li>${html.escape(c)}</li>
%endif
%endfor
</ul>
</div>
</body>
</html>
"""))
async def gather_commits(version: str) -> str:
p = await asyncio.create_subprocess_exec(
'git', 'log', f'mesa-{version}..', '--grep', r'Closes: \(https\|#\).*',
stdout=asyncio.subprocess.PIPE)
out, _ = await p.communicate()
assert p.returncode == 0, f"git log didn't work: {version}"
return out.decode().strip()
async def gather_bugs(version: str) -> typing.List[str]:
commits = await gather_commits(version)
issues: typing.List[str] = []
for commit in commits.split('\n'):
sha, message = commit.split(maxsplit=1)
p = await asyncio.create_subprocess_exec(
'git', 'log', '--max-count', '1', r'--format=%b', sha,
stdout=asyncio.subprocess.PIPE)
_out, _ = await p.communicate()
out = _out.decode().split('\n')
for line in reversed(out):
if line.startswith('Closes:'):
bug = line.lstrip('Closes:').strip()
break
else:
raise Exception('No closes found?')
if bug.startswith('h'):
# This means we have a bug in the form "Closes: https://..."
issues.append(os.path.basename(urllib.parse.urlparse(bug).path))
else:
issues.append(bug.lstrip('#'))
loop = asyncio.get_event_loop()
async with aiohttp.ClientSession(loop=loop) as session:
results = await asyncio.gather(*[get_bug(session, i) for i in issues])
typing.cast(typing.Tuple[str, ...], results)
return list(results)
async def get_bug(session: aiohttp.ClientSession, bug_id: str) -> str:
"""Query gitlab to get the name of the issue that was closed."""
# Mesa's gitlab id is 176,
url = 'https://gitlab.freedesktop.org/api/v4/projects/176/issues'
params = {'iids[]': bug_id}
async with session.get(url, params=params) as response:
content = await response.json()
return content[0]['title']
async def get_shortlog(version: str) -> str:
"""Call git shortlog."""
p = await asyncio.create_subprocess_exec('git', 'shortlog', f'mesa-{version}..',
stdout=asyncio.subprocess.PIPE)
out, _ = await p.communicate()
assert p.returncode == 0, 'error getting shortlog'
assert out is not None, 'just for mypy'
return out.decode()
def walk_shortlog(log: str) -> typing.Generator[typing.Tuple[str, bool], None, None]:
for l in log.split('\n'):
if l.startswith(' '): # this means we have a patch description
yield l, False
else:
yield l, True
def calculate_next_version(version: str, is_point: bool) -> str:
"""Calculate the version about to be released."""
if '-' in version:
version = version.split('-')[0]
if is_point:
base = version.split('.')
base[2] = str(int(base[2]) + 1)
return '.'.join(base)
return version
def calculate_previous_version(version: str, is_point: bool) -> str:
"""Calculate the previous version to compare to.
In the case of -rc to final that verison is the previous .0 release,
(19.3.0 in the case of 20.0.0, for example). for point releases that is
the last point release. This value will be the same as the input value
for a point release, but different for a major release.
"""
if '-' in version:
version = version.split('-')[0]
if is_point:
return version
base = version.split('.')
if base[1] == '0':
base[0] = str(int(base[0]) - 1)
base[1] = '3'
else:
base[1] = str(int(base[1]) - 1)
return '.'.join(base)
def get_features(is_point_release: bool) -> typing.Generator[str, None, None]:
p = pathlib.Path(__file__).parent.parent / 'docs' / 'relnotes' / 'new_features.txt'
if p.exists():
if is_point_release:
print("WARNING: new features being introduced in a point release", file=sys.stderr)
with p.open('rt') as f:
for line in f:
yield line
else:
yield "None"
async def main() -> None:
v = pathlib.Path(__file__).parent.parent / 'VERSION'
with v.open('rt') as f:
raw_version = f.read().strip()
is_point_release = '-rc' not in raw_version
assert '-devel' not in raw_version, 'Do not run this script on -devel'
version = raw_version.split('-')[0]
previous_version = calculate_previous_version(version, is_point_release)
next_version = calculate_next_version(version, is_point_release)
shortlog, bugs = await asyncio.gather(
get_shortlog(previous_version),
gather_bugs(previous_version),
)
final = pathlib.Path(__file__).parent.parent / 'docs' / 'relnotes' / f'{next_version}.html'
with final.open('wt') as f:
try:
f.write(TEMPLATE.render(
bugfix=is_point_release,
bugs=bugs,
changes=walk_shortlog(shortlog),
features=get_features(is_point_release),
gl_version=CURRENT_GL_VERSION,
next_version=next_version,
today=datetime.date.today(),
version=previous_version,
vk_version=CURRENT_VK_VERSION,
))
except:
print(exceptions.text_error_template().render())
if __name__ == "__main__":
loop = asyncio.get_event_loop()
loop.run_until_complete(main())

View File

@@ -1,62 +0,0 @@
# Copyright © 2019 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
from unittest import mock
import pytest
from .gen_release_notes import *
@pytest.mark.parametrize(
'current, is_point, expected',
[
('19.2.0', True, '19.2.1'),
('19.3.6', True, '19.3.7'),
('20.0.0-rc4', False, '20.0.0'),
])
def test_next_version(current: str, is_point: bool, expected: str) -> None:
assert calculate_next_version(current, is_point) == expected
@pytest.mark.parametrize(
'current, is_point, expected',
[
('19.3.6', True, '19.3.6'),
('20.0.0-rc4', False, '19.3.0'),
])
def test_previous_version(current: str, is_point: bool, expected: str) -> None:
assert calculate_previous_version(current, is_point) == expected
@pytest.mark.asyncio
async def test_get_shortlog():
# Certainly not perfect, but it's something
version = '19.2.0'
out = await get_shortlog(version)
assert out
@pytest.mark.asyncio
async def test_gather_commits():
# Certainly not perfect, but it's something
version = '19.2.0'
out = await gather_commits(version)
assert out

View File

@@ -32,7 +32,7 @@ is_sha_nomination()
{
fixes=`git show --pretty=medium -s $1 | tr -d "\n" | \
sed -e 's/'"$2"'/\nfixes:/Ig' | \
grep -Eo 'fixes:[a-f0-9]{4,40}'`
grep -Eo 'fixes:[a-f0-9]{8,40}'`
fixes_count=`echo "$fixes" | grep "fixes:" | wc -l`
if test $fixes_count -eq 0; then
@@ -92,7 +92,7 @@ is_revert_nomination()
}
# Use the last branchpoint as our limit for the search
latest_branchpoint=`git merge-base upstream/master HEAD`
latest_branchpoint=`git merge-base origin/master HEAD`
# List all the commits between day 1 and the branch point...
git log --reverse --pretty=%H $latest_branchpoint > already_landed
@@ -103,7 +103,7 @@ git log --reverse --pretty=medium --grep="cherry picked from commit" $latest_bra
sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
# Grep for potential candidates
git log --reverse --pretty=%H -i --grep='^CC:.*mesa-stable\|^CC:.*mesa-dev\|\<fixes\>\|\<broken by\>\|This reverts commit' $latest_branchpoint..upstream/master |\
git log --reverse --pretty=%H -i --grep='^CC:.*mesa-stable\|^CC:.*mesa-dev\|\<fixes\>\|\<broken by\>\|This reverts commit' $latest_branchpoint..origin/master |\
while read sha
do
# Check to see whether the patch is on the ignore list.
@@ -143,7 +143,7 @@ do
esac
printf "[ %8s ] " "$tag"
git --no-pager show --no-patch --pretty=oneline $sha
git --no-pager show --no-patch --oneline $sha
done
rm -f already_picked

View File

@@ -1,117 +0,0 @@
#!/usr/bin/env python3
# Copyright © 2019 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
"""Update the main page, release notes, and calendar."""
import argparse
import calendar
import datetime
import pathlib
from lxml import (
etree,
html,
)
def calculate_previous_version(version: str, is_point: bool) -> str:
"""Calculate the previous version to compare to.
In the case of -rc to final that verison is the previous .0 release,
(19.3.0 in the case of 20.0.0, for example). for point releases that is
the last point release. This value will be the same as the input value
for a poiont release, but different for a major release.
"""
if '-' in version:
version = version.split('-')[0]
if is_point:
return version
base = version.split('.')
if base[1] == '0':
base[0] = str(int(base[0]) - 1)
base[1] = '3'
else:
base[1] = str(int(base[1]) - 1)
return '.'.join(base)
def is_point_release(version: str) -> bool:
return not version.endswith('.0')
def update_index(is_point: bool, version: str, previous_version: str) -> None:
p = pathlib.Path(__file__).parent.parent / 'docs' / 'index.html'
with p.open('rt') as f:
tree = html.parse(f)
news = tree.xpath('.//h1')[0]
date = datetime.date.today()
month = calendar.month_name[date.month]
header = etree.Element('h2')
header.text = f"{month} {date.day}, {date.year}"
body = etree.Element('p')
a = etree.SubElement(
body, 'a', attrib={'href': f'relnotes/{previous_version}.html'})
a.text = f"Mesa {previous_version}"
if is_point:
a.tail = " is released. This is a bug fix release."
else:
a.tail = (" is released. This is a new development release. "
"See the release notes for mor information about this release.")
root = news.getparent()
index = root.index(news) + 1
root.insert(index, body)
root.insert(index, header)
tree.write(p.as_posix(), method='html')
def update_release_notes(previous_version: str) -> None:
p = pathlib.Path(__file__).parent.parent / 'docs' / 'relnotes.html'
with p.open('rt') as f:
tree = html.parse(f)
li = etree.Element('li')
a = etree.SubElement(li, 'a', href=f'relnotes/{previous_version}.html')
a.text = f'{previous_version} release notes'
ul = tree.xpath('.//ul')[0]
ul.insert(0, li)
tree.write(p.as_posix(), method='html')
def main() -> None:
parser = argparse.ArgumentParser()
parser.add_argument('version', help="The released version.")
args = parser.parse_args()
is_point = is_point_release(args.version)
previous_version = calculate_previous_version(args.version, is_point)
update_index(is_point, args.version, previous_version)
update_release_notes(previous_version)
if __name__ == "__main__":
main()

29
bin/shortlog_mesa.sh Executable file
View File

@@ -0,0 +1,29 @@
#!/bin/sh
# This script is used to generate the list of changes that
# appears in the release notes files, with HTML formatting.
#
# Usage examples:
#
# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3
# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 > changes
# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee changes
in_log=0
git shortlog $* | while read l
do
if [ $in_log -eq 0 ]; then
echo '<p>'$l'</p>'
echo '<ul>'
in_log=1
elif echo "$l" | egrep -q '^$' ; then
echo '</ul>'
echo
in_log=0
else
mesg=$(echo $l | sed 's/ (cherry picked from commit [0-9a-f]\+)//;s/\&/&amp;/g;s/</\&lt;/g;s/>/\&gt;/g')
echo ' <li>'${mesg}'</li>'
fi
done

View File

@@ -1,9 +1,8 @@
#!/usr/bin/env python
import argparse
import os
import platform
import subprocess
import os
# This list contains symbols that _might_ be exported for some platforms
PLATFORM_SYMBOLS = [
@@ -24,22 +23,11 @@ def get_symbols(nm, lib):
List all the (non platform-specific) symbols exported by the library
'''
symbols = []
platform_name = platform.system()
output = subprocess.check_output([nm, '-gP', lib],
output = subprocess.check_output([nm, '--format=bsd', '-D', '--defined-only', lib],
stderr=open(os.devnull, 'w')).decode("ascii")
for line in output.splitlines():
fields = line.split()
if len(fields) == 2 or fields[1] == 'U':
continue
symbol_name = fields[0]
if platform_name == 'Linux':
if symbol_name in PLATFORM_SYMBOLS:
continue
elif platform_name == 'Darwin':
assert symbol_name[0] == '_'
symbol_name = symbol_name[1:]
(_, _, symbol_name) = line.split()
symbols.append(symbol_name)
return symbols
@@ -59,12 +47,7 @@ def main():
help='path to binary (or name in $PATH)')
args = parser.parse_args()
try:
lib_symbols = get_symbols(args.nm, args.lib)
except:
# We can't run this test, but we haven't technically failed it either
# Return the GNU "skip" error code
exit(77)
lib_symbols = get_symbols(args.nm, args.lib)
mandatory_symbols = []
optional_symbols = []
with open(args.symbols_file) as symbols_file:
@@ -109,6 +92,8 @@ def main():
continue
if symbol in optional_symbols:
continue
if symbol in PLATFORM_SYMBOLS:
continue
unknown_symbols.append(symbol)
missing_symbols = [

View File

@@ -17,9 +17,6 @@ import SCons.Script.SConscript
host_platform = _platform.system().lower()
if host_platform.startswith('cygwin'):
host_platform = 'cygwin'
# MSYS2 default platform selection.
if host_platform.startswith('mingw'):
host_platform = 'windows'
# Search sys.argv[] for a "platform=foo" argument since we don't have
# an 'env' variable at this point.
@@ -52,18 +49,9 @@ if 'PROCESSOR_ARCHITECTURE' in os.environ:
else:
host_machine = _platform.machine()
host_machine = _machine_map.get(host_machine, 'generic')
# MSYS2 default machine selection.
if _platform.system().lower().startswith('mingw') and 'MSYSTEM' in os.environ:
if os.environ['MSYSTEM'] == 'MINGW32':
host_machine = 'x86'
if os.environ['MSYSTEM'] == 'MINGW64':
host_machine = 'x86_64'
default_machine = host_machine
default_toolchain = 'default'
# MSYS2 default toolchain selection.
if _platform.system().lower().startswith('mingw'):
default_toolchain = 'mingw'
if target_platform == 'windows' and host_platform != 'windows':
default_machine = 'x86'

View File

@@ -24,8 +24,8 @@ The old bug database on SourceForge is no longer used.
<p>
To file a Mesa bug, go to
<a href="https://gitlab.freedesktop.org/mesa/mesa/issues">
GitLab on freedesktop.org</a>
<a href="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa">
Bugzilla on freedesktop.org</a>
</p>
<p>

View File

@@ -166,8 +166,8 @@ extern __thread struct _glapi_table *_glapi_tls_Dispatch
</blockquote>
<p>Use of this path is controlled by the preprocessor define
<code>USE_ELF_TLS</code>. Any platform capable of using ELF TLS should use this
as the default dispatch method.</p>
<code>GLX_USE_TLS</code>. Any platform capable of using TLS should use this as
the default dispatch method.</p>
<h3>3.3. Assembly Language Dispatch Stubs</h3>
@@ -204,7 +204,7 @@ terribly relevant.</p>
few preprocessor defines.</p>
<ul>
<li>If <code>USE_ELF_TLS</code> is defined, method #3 is used.</li>
<li>If <code>GLX_USE_TLS</code> is defined, method #3 is used.</li>
<li>If <code>HAVE_PTHREAD</code> is defined, method #2 is used.</li>
<li>If none of the preceding are defined, method #1 is used.</li>
</ul>

View File

@@ -215,7 +215,7 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi, r600
GL_ARB_clip_control DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
GL_ARB_conditional_render_inverted DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr, virgl)
GL_ARB_cull_distance DONE (i965, nv50, llvmpipe, softpipe, swr, virgl)
GL_ARB_derivative_control DONE (i965, nv50, softpipe, virgl)
GL_ARB_derivative_control DONE (i965, nv50, virgl)
GL_ARB_direct_state_access DONE (all drivers)
GL_ARB_get_texture_sub_image DONE (all drivers)
GL_ARB_shader_texture_image_samples DONE (i965, nv50, virgl)

View File

@@ -29,7 +29,7 @@ immediately checked into git because not enough people are testing them.
Just applying patches, testing and reporting back is helpful.
<li>
<b>Driver debugging.</b>
There are plenty of open bugs in the <a href="https://gitlab.freedesktop.org/mesa/mesa/issues">bug database</a>.
There are plenty of open bugs in the <a href="https://bugs.freedesktop.org/describecomponents.cgi?product=Mesa">bug database</a>.
<li>
<b>Remove aliasing warnings.</b>
Enable gcc's <code>-Wstrict-aliasing=2 -fstrict-aliasing</code> arguments, and

View File

@@ -16,12 +16,6 @@
<h1>News</h1>
<h2>August 7, 2019</h2>
<p>
<a href="relnotes/19.1.4.html">Mesa 19.1.4</a> is released.
This is a bug-fix release.
</p>
<h2>July 23, 2019</h2>
<p>
<a href="relnotes/19.1.3.html">Mesa 19.1.3</a> is released.

View File

@@ -51,7 +51,7 @@ There are several examples of OSMesa in the mesa/demos repository.
Configure and build Mesa with something like:
<pre>
meson builddir -Dosmesa=gallium -Dgallium-drivers=swrast -Ddri-drivers=[] -Dvulkan-drivers=[] -Dprefix=$PWD/builddir/install
meson builddir -Dosmesa=gallium -Dgallium-drivers=swrast -Ddri-drivers= -Dvulkan-drivers= -Dprefix=$PWD/builddir/install
ninja -C builddir install
</pre>

View File

@@ -60,7 +60,13 @@ if you'd like to nominate a patch in the next stable release.
<th>Notes</th>
</tr>
<tr>
<td rowspan="3">19.1</td>
<td rowspan="4">19.1</td>
<td>2019-08-06</td>
<td>19.1.4</td>
<td>Juan A. Suarez</td>
<td>
</tr>
<tr>
<td>2019-08-20</td>
<td>19.1.5</td>
<td>Juan A. Suarez</td>

View File

@@ -285,7 +285,7 @@ To setup the branchpoint:
<p>
Now go to
<a href="https://gitlab.freedesktop.org/mesa/mesa/-/milestones" target="_parent">gitlab</a> and add the new Mesa version X.Y.
<a href="https://bugs.freedesktop.org/editversions.cgi?action=add&amp;product=Mesa" target="_parent">Bugzilla</a> and add the new Mesa version X.Y.
</p>
<p>

View File

@@ -21,7 +21,6 @@ The release notes summarize what's new or changed in each Mesa release.
</p>
<ul>
<li><a href="relnotes/19.1.4.html">19.1.4 release notes</a>
<li><a href="relnotes/19.1.3.html">19.1.3 release notes</a>
<li><a href="relnotes/19.1.2.html">19.1.2 release notes</a>
<li><a href="relnotes/19.0.8.html">19.0.8 release notes</a>

View File

@@ -1,227 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.1.4 Release Notes / August 7, 2019</h1>
<p>
Mesa 19.1.4 is a bug fix release which fixes bugs found since the 19.1.3 release.
</p>
<p>
Mesa 19.1.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
a6d268a7d9edcfd92b6da80f2e34e6e0a7baaa442efbeba2fc66c404943c6bfb mesa-19.1.4.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109203">Bug 109203</a> - [cfl dxvk] GPU Crash Launching Monopoly Plus (Iris Plus 655 / Wine + DXVK)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109524">Bug 109524</a> - &quot;Invalid glsl version in shading_language_version()&quot; when trying to run directX games using wine</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110309">Bug 110309</a> - [icl][bisected] regression on piglit arb_gpu_shader_int 64.execution.fs-ishl-then-* tests</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110663">Bug 110663</a> - threads_posix.h:96: undefined reference to `pthread_once'</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110955">Bug 110955</a> - Mesa 18.2.8 implementation error: Invalid GLSL version in shading_language_version()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111010">Bug 111010</a> - Cemu Shader Cache Corruption Displaying Solid Color After commit 11e16ca7ce0</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111071">Bug 111071</a> - SPIR-V shader processing fails with message about &quot;extra dangling SSA sources&quot;</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111075">Bug 111075</a> - Processing of SPIR-V shader causes device hang, sometimes leading to system reboot</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111097">Bug 111097</a> - Can not detect VK_ERROR_OUT_OF_DATE_KHR or VK_SUBOPTIMAL_KHR when window resizing</li>
</ul>
<h2>Changes</h2>
<p>Andres Rodriguez (1):</p>
<ul>
<li>radv: fix queries with WAIT_BIT returning VK_NOT_READY</li>
</ul>
<p>Andrii Simiklit (2):</p>
<ul>
<li>intel/compiler: don't use a keyword struct for a class fs_reg</li>
<li>meson: add a warning for meson &lt; 0.46.0</li>
</ul>
<p>Arcady Goldmints-Orlov (1):</p>
<ul>
<li>anv: report HOST_ALLOCATION as supported for images</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Set correct metadata size for GFX9+.</li>
<li>radv: Take variable descriptor counts into account for buffer entries.</li>
<li>radv: Fix descriptor set allocation failure.</li>
</ul>
<p>Boyuan Zhang (4):</p>
<ul>
<li>radeon/uvd: fix poc for hevc encode</li>
<li>radeon/vcn: fix poc for hevc encode</li>
<li>radeon/uvd: enable rate control for hevc encoding</li>
<li>radeon/vcn: enable rate control for hevc encoding</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>anv: Remove special allocation for anv_push_constants</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>nir: Allow qualifiers on copy_deref and image instructions</li>
</ul>
<p>Daniel Schürmann (1):</p>
<ul>
<li>spirv: Fix order of barriers in SpvOpControlBarrier</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>st/nir: fix arb fragment stage conversion</li>
</ul>
<p>Dylan Baker (1):</p>
<ul>
<li>meson: allow building all glx without any drivers</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>egl/drm: ensure the backing gbm is set before using it</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>freedreno: Fix data races with allocating/freeing struct ir3.</li>
</ul>
<p>Eric Engestrom (5):</p>
<ul>
<li>nir: don't return void</li>
<li>util: fix no-op macro (bad number of arguments)</li>
<li>gallium+mesa: fix tgsi_semantic array type</li>
<li>scons+meson: suppress spammy build warning on MacOS</li>
<li>nir: remove explicit nir_intrinsic_index_flag values</li>
</ul>
<p>Francisco Jerez (1):</p>
<ul>
<li>intel/ir: Fix CFG corruption in opt_predicated_break().</li>
</ul>
<p>Ilia Mirkin (4):</p>
<ul>
<li>gallium/vl: fix compute tgsi shaders to not process undefined components</li>
<li>nv50,nvc0: update sampler/view bind functions to accept NULL array</li>
<li>nvc0: allow a non-user buffer to be bound at position 0</li>
<li>nv50/ir: handle insn not being there for definition of CVT arg</li>
</ul>
<p>Jason Ekstrand (6):</p>
<ul>
<li>intel/fs: Stop stack allocating large arrays</li>
<li>anv: Disable transform feedback on gen7</li>
<li>isl/formats: R8G8B8_UNORM_SRGB isn't supported on HSW</li>
<li>anv: Don't claim support for 24 and 48-bit formats on IVB</li>
<li>intel/fs: Use ALIGN16 instructions for all derivatives on gen &lt;= 7</li>
<li>intel/fs: Implement quad_swap_horizontal with a swizzle on gen7</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>docs: add sha256 checksums for 19.1.3</li>
<li>Update version to 19.1.4</li>
</ul>
<p>Kenneth Graunke (4):</p>
<ul>
<li>mesa: Fix ReadBuffers with pbuffers</li>
<li>egl: Quiet warning about front buffer rendering for pixmaps/pbuffers</li>
<li>egl: Make the 565 pbuffer-only config single buffered.</li>
<li>egl: Only expose 565 pbuffer configs if X can export them as DRI3 images</li>
</ul>
<p>Lionel Landwerlin (5):</p>
<ul>
<li>anv: fix use of comma operator</li>
<li>nir: add access to image_deref intrinsics</li>
<li>spirv: wrap push ssa/pointer values</li>
<li>spirv: propagate access qualifiers through ssa &amp; pointer</li>
<li>spirv: don't discard access set by vtn_pointer_dereference</li>
</ul>
<p>Mark Menzynski (1):</p>
<ul>
<li>nvc0/ir: Fix assert accessing null pointer</li>
</ul>
<p>Nataraj Deshpande (1):</p>
<ul>
<li>egl/android: Update color_buffers querying for buffer age</li>
</ul>
<p>Nicolas Dufresne (1):</p>
<ul>
<li>egl: Also query modifiers when exporting DMABuf</li>
</ul>
<p>Rhys Perry (1):</p>
<ul>
<li>ac/nir: fix txf_ms with an offset</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: fix crash in vkCmdClearAttachments with unused attachment</li>
</ul>
<p>Tapani Pälli (1):</p>
<ul>
<li>mesa: add glsl_type ref to one_time_init and decref to atexit</li>
</ul>
<p>Yevhenii Kolesnikov (1):</p>
<ul>
<li>main: Fix memleaks in mesa_use_program</li>
</ul>
</div>
</body>
</html>

View File

@@ -29,11 +29,6 @@ Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa 19.2.0 implements the Vulkan 1.1 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksums</h2>
<pre>
@@ -45,405 +40,21 @@ TBD.
<ul>
<li>GL_ARB_post_depth_coverage on radeonsi (Navi)</li>
<li>GL_ARB_seamless_cubemap_per_texture on etnaviv (if GPU supports SEAMLESS_CUBE_MAP)</li>
<li>GL_EXT_shader_image_load_store on radeonsi (with LLVM >= 10)</li>
<li>GL_EXT_shader_samples_identical on iris and radeonsi (if using NIR)</li>
<li>GL_EXT_texture_shadow_lod on i965, iris</li>
<li>EGL_EXT_platform_device</li>
<li>VK_AMD_buffer_marker on radv</li>
<li>VK_EXT_index_type_uint8 on radv</li>
<li>VK_EXT_post_depth_coverage on radv</li>
<li>VK_EXT_queue_family_foreign on radv</li>
<li>VK_EXT_sample_locations on radv</li>
<li>VK_EXT_queue_family_foreign for radv</li>
<li>VK_EXT_shader_demote_to_helper_invocation on Intel.</li>
<li>VK_KHR_depth_stencil_resolve on radv</li>
<li>VK_KHR_imageless_framebuffer on radv</li>
<li>VK_KHR_shader_atomic_int64 on radv</li>
<li>VK_KHR_uniform_buffer_standard_layout on radv</li>
</ul>
<h2>Bug fixes</h2>
<ul>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103674">Bug 103674</a> - u_queue.c:173:7: error: implicit declaration of function 'timespec_get' is invalid in C99</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104395">Bug 104395</a> - [CTS] GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels tests fail on 32bit Mesa</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110765">Bug 110765</a> - ANV regression: Assertion `pass-&gt;attachment_count == framebuffer-&gt;attachment_count' failed</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110814">Bug 110814</a> - KWin compositor crashes on launch</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111069">Bug 111069</a> - Assertion fails in nir_opt_remove_phis.c during compilation of SPIR-V shader</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111213">Bug 111213</a> - VA-API nouveau SIGSEGV and asserts</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111241">Bug 111241</a> - Shadertoy shader causing hang</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111248">Bug 111248</a> - Navi10 Font rendering issue in Overwatch</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111271">Bug 111271</a> - Crash in eglMakeCurrent</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111308">Bug 111308</a> - [Regression, NIR, bisected] Black squares in Unigine Heaven via DXVK</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111401">Bug 111401</a> - Vulkan overlay layer - async compute not supported, making overlay disappear in Doom</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111405">Bug 111405</a> - Some infinite 'do{}while' loops lead mesa to an infinite compilation</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111411">Bug 111411</a> - SPIR-V shader leads to GPU hang, sometimes making machine unstable</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111414">Bug 111414</a> - [REGRESSION] [BISECTED] Segmentation fault in si_bind_blend_state after removal of the blend state NULL check</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111467">Bug 111467</a> - WOLF RPG Editor + Gallium Nine Standalone: Rendering issue when using Iris driver</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111490">Bug 111490</a> - [REGRESSION] [BISECTED] Shadow Tactics: Blades of the Shogun - problems rendering water</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111493">Bug 111493</a> - In the game The Surge (378540) - textures disappear then appear again when I change the camera angle view</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111509">Bug 111509</a> - [regression][bisected] piglit.spec.ext_image_dma_buf_import.ext_image_dma_buf_import-export fails on iris</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111522">Bug 111522</a> - [bisected] Supraland no longer start</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111529">Bug 111529</a> - EGL_PLATFORM=drm doesn't expose MESA_query_driver extension</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111552">Bug 111552</a> - Geekbench 5.0 Vulkan compute benchmark fails on Anvil</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111566">Bug 111566</a> - [REGRESSION] [BISECTED] Large CS workgroup sizes broken in combination with FP64 on Intel.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111576">Bug 111576</a> - [bisected] Performance regression in X4:Foundations in 19.2</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111676">Bug 111676</a> - Tropico 6 apitrace throws error into logs</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111734">Bug 111734</a> - Geometry shader with double interpolators fails in LLVM</li>
</ul>
<li>TBD</li>
</ul>
<h2>Changes</h2>
<ul>
<p>Adam Jackson (1):</p>
<ul>
<li>docs: Update bug report URLs for the gitlab migration</li>
</ul>
<p>Alex Smith (1):</p>
<ul>
<li>radv: Change memory type order for GPUs without dedicated VRAM</li>
</ul>
<p>Alyssa Rosenzweig (1):</p>
<ul>
<li>pan/midgard: Fix writeout combining</li>
</ul>
<p>Andres Gomez (1):</p>
<ul>
<li>docs: Add the maximum implemented Vulkan API version in 19.2 rel notes</li>
</ul>
<p>Andres Rodriguez (1):</p>
<ul>
<li>radv: additional query fixes</li>
</ul>
<p>Arcady Goldmints-Orlov (1):</p>
<ul>
<li>anv: fix descriptor limits on gen8</li>
</ul>
<p>Bas Nieuwenhuizen (6):</p>
<ul>
<li>radv: Use correct vgpr_comp_cnt for VS if both prim_id and instance_id are needed.</li>
<li>radv: Emit VGT_GS_ONCHIP_CNTL for tess on GFX10.</li>
<li>radv: Disable NGG for geometry shaders.</li>
<li>Revert "ac/nir: Lower large indirect variables to scratch"</li>
<li>tu: Set up glsl types.</li>
<li>radv: Add workaround for hang in The Surge 2.</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (2):</p>
<ul>
<li>nir/lower_explicit_io: Handle 1 bit loads and stores</li>
<li>glsl/nir: Avoid overflow when setting max_uniform_location</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>radv: Call nir_propagate_invariant()</li>
</ul>
<p>Danylo Piliaiev (3):</p>
<ul>
<li>nir/loop_unroll: Prepare loop for unrolling in wrapper_unroll</li>
<li>nir/loop_analyze: Treat do{}while(false) loops as 0 iterations</li>
<li>tgsi_to_nir: Translate TGSI_INTERPOLATE_COLOR as INTERP_MODE_NONE</li>
</ul>
<p>Dave Airlie (2):</p>
<ul>
<li>virgl: fix format conversion for recent gallium changes.</li>
<li>gallivm: fix atomic compare-and-swap</li>
</ul>
<p>Dave Stevenson (1):</p>
<ul>
<li>broadcom/v3d: Allow importing linear BOs with arbitrary offset/stride.</li>
</ul>
<p>Dylan Baker (9):</p>
<ul>
<li>bump version to 19.2-rc2</li>
<li>nir: Add is_not_negative helper function</li>
<li>Bump version for rc3</li>
<li>meson: don't generate file into subdirs</li>
<li>add patches to be ignored</li>
<li>Bump version for 19.2.0-rc4</li>
<li>cherry-ignore: Add patches</li>
<li>rehardcode from origin/master to upstream/master</li>
<li>bin/get-pick-list: use --oneline=pretty instead of --oneline</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>Update version to 19.2.0-rc1</li>
</ul>
<p>Eric Engestrom (14):</p>
<ul>
<li>ttn: fix 64-bit shift on 32-bit `1`</li>
<li>egl: fix deadlock in malloc error path</li>
<li>util/os_file: fix double-close()</li>
<li>anv: fix format string in error message</li>
<li>freedreno/drm-shim: fix mem leak</li>
<li>nir: fix memleak in error path</li>
<li>anv: add support for driconf</li>
<li>wsi: add minImageCount override</li>
<li>anv: add support for vk_x11_override_min_image_count</li>
<li>amd: move adaptive sync to performance section, as it is defined in xmlpool</li>
<li>radv: add support for vk_x11_override_min_image_count</li>
<li>drirc: override minImageCount=2 for gfxbench</li>
<li>gl: drop incorrect pkg-config file for glvnd</li>
<li>meson: re-add incorrect pkg-config files with GLVND for backward compatibility</li>
</ul>
<p>Erik Faye-Lund (2):</p>
<ul>
<li>gallium/auxiliary/indices: consistently apply start only to input</li>
<li>util: fix SSE-version needed for double opcodes</li>
</ul>
<p>Haihao Xiang (1):</p>
<ul>
<li>i965: support AYUV/XYUV for external import only</li>
</ul>
<p>Hal Gentz (2):</p>
<ul>
<li>glx: Fix SEGV due to dereferencing a NULL ptr from XCB-GLX.</li>
<li>gallium/osmesa: Fix the inability to set no context as current.</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>v3d: make sure we have enough space in the CL for the primitive counts packet</li>
</ul>
<p>Ian Romanick (8):</p>
<ul>
<li>nir/algrbraic: Don't optimize open-coded bitfield reverse when lowering is enabled</li>
<li>intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardware</li>
<li>nir/algebraic: Mark some value range analysis-based optimizations imprecise</li>
<li>nir/range-analysis: Adjust result range of exp2 to account for flush-to-zero</li>
<li>nir/range-analysis: Adjust result range of multiplication to account for flush-to-zero</li>
<li>nir/range-analysis: Fix incorrect fadd range result for (ne_zero, ne_zero)</li>
<li>nir/range-analysis: Handle constants in nir_op_mov just like nir_op_bcsel</li>
<li>nir/algebraic: Do not apply late DPH optimization in vertex processing stages</li>
</ul>
<p>Ilia Mirkin (1):</p>
<ul>
<li>gallium/vl: use compute preference for all multimedia, not just blit</li>
</ul>
<p>Jason Ekstrand (9):</p>
<ul>
<li>anv: Bump maxComputeWorkgroupSize</li>
<li>nir: Handle complex derefs in nir_split_array_vars</li>
<li>nir: Don't infinitely recurse in lower_ssa_defs_to_regs_block</li>
<li>nir: Add a block_is_unreachable helper</li>
<li>nir/repair_ssa: Repair dominance for unreachable blocks</li>
<li>nir/repair_ssa: Insert deref casts when needed</li>
<li>nir/dead_cf: Repair SSA if the pass makes progress</li>
<li>intel/fs: Handle UNDEF in split_virtual_grfs</li>
<li>nir/repair_ssa: Replace the unreachable check with the phi builder</li>
</ul>
<p>Jonathan Marek (1):</p>
<ul>
<li>freedreno/a2xx: ir2: fix lowering of instructions after float lowering</li>
</ul>
<p>Jose Maria Casanova Crespo (1):</p>
<ul>
<li>mesa: recover target_check before get_current_tex_objects</li>
</ul>
<p>Juan A. Suarez Romero (1):</p>
<ul>
<li>bin/get-pick-list.sh: sha1 commits can be smaller than 8 chars</li>
</ul>
<p>Kenneth Graunke (20):</p>
<ul>
<li>gallium/ddebug: Wrap resource_get_param if available</li>
<li>gallium/trace: Wrap resource_get_param if available</li>
<li>gallium/rbug: Wrap resource_get_param if available</li>
<li>gallium/noop: Implement resource_get_param</li>
<li>iris: Replace devinfo-&gt;gen with GEN_GEN</li>
<li>iris: Fix broken aux.possible/sampler_usages bitmask handling</li>
<li>iris: Update fast clear colors on Gen9 with direct immediate writes.</li>
<li>iris: Drop copy format hacks from copy region based transfer path.</li>
<li>iris: Avoid unnecessary resolves on transfer maps</li>
<li>iris: Fix large timeout handling in rel2abs()</li>
<li>isl: Drop UnormPathInColorPipe for buffer surfaces.</li>
<li>isl: Don't set UnormPathInColorPipe for integer surfaces.</li>
<li>util: Add a _mesa_i64roundevenf() helper.</li>
<li>mesa: Fix _mesa_float_to_unorm() on 32-bit systems.</li>
<li>iris: Fix partial fast clear checks to account for miplevel.</li>
<li>iris: Report correct number of planes for planar images</li>
<li>iris: Fix constant buffer sizes for non-UBOs</li>
<li>gallium: Fix util_format_get_depth_only</li>
<li>iris: Initialize ice-&gt;state.prim_mode to an invalid value</li>
<li>intel: Increase Gen11 compute shader scratch IDs to 64.</li>
</ul>
<p>Lepton Wu (1):</p>
<ul>
<li>virgl: Fix pipe_resource leaks under multi-sample.</li>
</ul>
<p>Lionel Landwerlin (9):</p>
<ul>
<li>util/timespec: use unsigned 64 bit integers for nsec values</li>
<li>util: fix compilation on macos</li>
<li>egl: fix platform selection</li>
<li>vulkan/overlay: bounce image back to present layout</li>
<li>radv: store engine name</li>
<li>driconfig: add a new engine name/version parameter</li>
<li>vulkan: add vk_x11_strict_image_count option</li>
<li>util/xmlconfig: fix regexp compile failure check</li>
<li>drirc: include unreal engine version 0 to 23</li>
</ul>
<p>Marek Olšák (23):</p>
<ul>
<li>radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache</li>
<li>radeonsi: move some global shader cache flags to per-binary flags</li>
<li>radeonsi/gfx10: fix tessellation for the legacy pipeline</li>
<li>radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamout</li>
<li>radeonsi/gfx10: create the GS copy shader if using legacy streamout</li>
<li>radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64</li>
<li>radeonsi/gfx10: fix InstanceID for legacy VS+GS</li>
<li>radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0</li>
<li>radeonsi/gfx10: always use the legacy pipeline for streamout</li>
<li>radeonsi/gfx10: finish up Navi14, add PCI ID</li>
<li>radeonsi/gfx10: add AMD_DEBUG=nongg</li>
<li>winsys/amdgpu+radeon: process AMD_DEBUG in addition to R600_DEBUG</li>
<li>radeonsi: add PKT3_CONTEXT_REG_RMW</li>
<li>radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables</li>
<li>radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags</li>
<li>radeonsi: consolidate determining VGPR_COMP_CNT for API VS</li>
<li>radeonsi: unbind blend/DSA/rasterizer state correctly in delete functions</li>
<li>radeonsi: fix scratch buffer WAVESIZE setting leading to corruption</li>
<li>radeonsi/gfx10: don't call gfx10_destroy_query with compute-only contexts</li>
<li>radeonsi/gfx10: fix wave occupancy computations</li>
<li>radeonsi: add Navi12 PCI ID</li>
<li>amd: add more PCI IDs for Navi14</li>
<li>ac/addrlib: fix chip identification for Vega10, Arcturus, Raven2, Renoir</li>
</ul>
<p>Mauro Rossi (2):</p>
<ul>
<li>android: mesa: revert "Enable asm unconditionally"</li>
<li>android: anv: libmesa_vulkan_common: add libmesa_util static dependency</li>
</ul>
<p>Paulo Zanoni (2):</p>
<ul>
<li>intel/fs: grab fail_msg from v32 instead of v16 when v32-&gt;run_cs fails</li>
<li>intel/fs: fix SHADER_OPCODE_CLUSTER_BROADCAST for SIMD32</li>
</ul>
<p>Pierre-Eric Pelloux-Prayer (1):</p>
<ul>
<li>glsl: replace 'x + (-x)' with constant 0</li>
</ul>
<p>Rafael Antognolli (1):</p>
<ul>
<li>anv: Only re-emit non-dynamic state that has changed.</li>
</ul>
<p>Rhys Perry (1):</p>
<ul>
<li>radv: always emit a position export in gs copy shaders</li>
</ul>
<p>Samuel Iglesias Gonsálvez (1):</p>
<ul>
<li>intel/nir: do not apply the fsin and fcos trig workarounds for consts</li>
</ul>
<p>Samuel Pitoiset (11):</p>
<ul>
<li>radv: allow to enable VK_AMD_shader_ballot only on GFX8+</li>
<li>radv: add a new debug option called RADV_DEBUG=noshaderballot</li>
<li>radv: force enable VK_AMD_shader_ballot for Wolfenstein Youngblood</li>
<li>ac: fix exclusive scans on GFX8-GFX9</li>
<li>radv/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0</li>
<li>radv/gfx10: do not use NGG with NAVI14</li>
<li>radv: fix getting the index type size for uint8_t</li>
<li>nir: do not assume that the result of fexp2(a) is always an integral</li>
<li>radv: fix allocating number of user sgprs if streamout is used</li>
<li>radv: fix loading 64-bit GS inputs</li>
<li>radv/gfx10: fix VK_KHR_pipeline_executable_properties with NGG GS</li>
</ul>
<p>Sergii Romantsov (2):</p>
<ul>
<li>intel/dri: finish proper glthread</li>
<li>nir/large_constants: more careful data copying</li>
</ul>
<p>Tapani Pälli (5):</p>
<ul>
<li>util: fix os_create_anonymous_file on android</li>
<li>iris/android: fix build and link with libmesa_intel_perf</li>
<li>egl: reset blob cache set/get functions on terminate</li>
<li>iris: close screen fd on iris_destroy_screen</li>
<li>egl: check for NULL value like eglGetSyncAttribKHR does</li>
</ul>
<p>Thong Thai (1):</p>
<ul>
<li>Revert "radeonsi: don't emit PKT3_CONTEXT_CONTROL on amdgpu"</li>
</ul>
<p>Timur Kristóf (1):</p>
<ul>
<li>st/nine: Properly initialize GLSL types for NIR shaders.</li>
</ul>
<p>Vinson Lee (2):</p>
<ul>
<li>swr: Fix build with llvm-9.0 again.</li>
<li>travis: Fail build if any command in if statement fails.</li>
</ul>
<li>TBD</li>
</ul>
</div>

View File

@@ -1,159 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.2.1 Release Notes / 2019-10-09</h1>
<p>
Mesa 19.2.1 is a bug fix release which fixes bugs found since the 19.2.0 release.
</p>
<p>
Mesa 19.2.1 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa 19.2.1 implements the Vulkan 1.1 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksum</h2>
<pre>
4cc53ca1a8d12c6ff0e5ea44a5213c05c88447ab50d7e28bb350cd29199f01e9 mesa-19.2.1.tar.xz
</pre>
<h2>New features</h2>
<ul>
<li>None</li>
</ul>
<h2>Bug fixes</h2>
<ul>
<li>meson.build:1447:6: ERROR: Problem encountered: libdrm required for gallium video statetrackers when using x11</li>
<li>Mesa doesn't build with current Scons version (3.1.0)</li>
<li>libXvMC-1.0.12 breaks mesa build</li>
<li>Meson can't find 32-bit libXvMCW in non-standard path</li>
<li>Mesa installs gl.pc and egl.pc even with libglvnd >= 1.2.0</li>
</ul>
<h2>Changes</h2>
<ul>
<p>Andreas Gottschling (1):</p>
<li> drisw: Fix shared memory leak on drawable resize</li>
<p></p>
<p>Andres Gomez (1):</p>
<li> egl: Remove the 565 pbuffer-only EGL config under X11.</li>
<p></p>
<p>Andrii Simiklit (1):</p>
<li> glsl: disallow incompatible matrices multiplication</li>
<p></p>
<p>Bas Nieuwenhuizen (1):</p>
<li> radv: Fix condition for skipping the continue CS.</li>
<p></p>
<p>Connor Abbott (1):</p>
<li> nir/opt_large_constants: Handle store writemasks</li>
<p></p>
<p>Danylo Piliaiev (1):</p>
<li> st/nine: Ignore D3DSIO_RET if it is the last instruction in a shader</li>
<p></p>
<p>Dylan Baker (9):</p>
<li> meson: fix logic for generating .pc files with old glvnd</li>
<li> meson: Try finding libxvmcw via pkg-config before using find_library</li>
<li> meson: Link xvmc with libxv</li>
<li> meson: gallium media state trackers require libdrm with x11</li>
<li> .cherry-ignore: Update for 19.2.1 cycle</li>
<li> meson: Only error building gallium video without libdrm when the platform is drm</li>
<li> scripts: Add a gen_release_notes.py script</li>
<li> release: Add an update_release_calendar.py script</li>
<li> bin: delete unused releasing scripts</li>
<p></p>
<p>Eric Engestrom (3):</p>
<li> radv: fix s/load/store/ copy-paste typo</li>
<li> meson: drop -Wno-foo bug workaround for Meson < 0.46</li>
<li> meson: add missing idep_nir_headers in iris_gen_libs</li>
<p></p>
<p>Erik Faye-Lund (1):</p>
<li> glsl: correct bitcast-helpers</li>
<p></p>
<p>Ian Romanick (1):</p>
<li> nir/range-analysis: Bail if the types don't match</li>
<p></p>
<p>Jason Ekstrand (1):</p>
<li> intel/fs: Fix fs_inst::flags_read for ANY/ALL predicates</li>
<p></p>
<p>Ken Mays (1):</p>
<li> haiku: fix Mesa build</li>
<p></p>
<p>Kenneth Graunke (2):</p>
<li> iris: Disable CCS_E for 32-bit floating point textures.</li>
<li> iris: Fix iris_rebind_buffer() for VBOs with non-zero offsets.</li>
<p></p>
<p>Lionel Landwerlin (6):</p>
<li> anv: gem-stubs: return a valid fd got anv_gem_userptr()</li>
<li> intel: use proper label for Comet Lake skus</li>
<li> mesa: don't forget to clear _Layer field on texture unit</li>
<li> intel: fix topology query</li>
<li> intel: fix subslice computation from topology data</li>
<li> intel/isl: Set null surface format to R32_UINT</li>
<p></p>
<p>Marek Olšák (7):</p>
<li> gallium/vl: don't set PIPE_HANDLE_USAGE_EXPLICIT_FLUSH</li>
<li> gallium: extend resource_get_param to be as capable as resource_get_handle</li>
<li> radeonsi/gfx10: fix L2 cache rinse programming</li>
<li> ac: fix incorrect vram_size reported by the kernel</li>
<li> ac: fix num_good_cu_per_sh for harvested chips</li>
<li> ac: add radeon_info::tcc_harvested</li>
<li> radeonsi/gfx10: fix corruption for chips with harvested TCCs</li>
<p></p>
<p>Mauro Rossi (1):</p>
<li> android: compiler/nir: build nir_divergence_analysis.c</li>
<p></p>
<p>Michel Dänzer (1):</p>
<li> radeonsi: fix VAAPI segfault due to various bugs</li>
<p></p>
<p>Michel Zou (1):</p>
<li> scons: add py3 support</li>
<p></p>
<p>Prodea Alexandru-Liviu (1):</p>
<li> scons/MSYS2-MinGW-W64: Fix build options defaults</li>
<p></p>
<p>Rhys Perry (1):</p>
<li> nir/opt_remove_phis: handle phis with no sources</li>
<p></p>
<p>Stephen Barber (1):</p>
<li> nouveau: add idep_nir_headers as dep for libnouveau</li>
<p></p>
<p>Tapani Pälli (2):</p>
<li> iris: disable aux on first get_param if not created with aux</li>
<li> anv/android: fix images created with external format support</li>
<p></p>
<p>pal1000 (2):</p>
<li> scons: Fix MSYS2 Mingw-w64 build.</li>
<li> scons/windows: Support build with LLVM 9.</li>
<p></p>
<p></p>
</ul>
</div>
</body>
</html>

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@@ -1,147 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.2.2 Release Notes / 2019-10-23</h1>
<p>
Mesa 19.2.2 is a bug fix release which fixes bugs found since the 19.2.1 release.
</p>
<p>
Mesa 19.2.2 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa 19.2.2 implements the Vulkan 1.1 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksum</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<ul>
<li>None</li>
</ul>
<h2>Bug fixes</h2>
<ul>
<li>Vulkan version of &quot;Middle-earth: Shadow of Mordor&quot; has graphics glitches on RADV driver (part 2)</li>
<li>Vulkan version of &quot;Middle-earth: Shadow of Mordor&quot; has graphics glitches on RADV driver</li>
<li>[amdgpu][Navi][llvm] Minimap problem in Nier Automata</li>
<li>Black ground in Dirt 4</li>
<li>Superbibles examples crashing Mesa drivers (radeonsi) and causing gpu reset</li>
<li>[CTS] dEQP-VK.graphicsfuzz.write-red-in-loop-nest crashes</li>
<li>mesa and libglvnd install the same headers</li>
<li>Regression: Doom (2016) crashes on Mesa 19.2 and above and Radeon 380 with Vulkan (worked on Mesa 19.1)</li>
<li>Rocket League displays corruption when the game starts</li>
</ul>
<h2>Changes</h2>
<ul>
<p>Alan Coopersmith (6):</p>
<li> c99_compat.h: Don&#x27;t try to use &#x27;restrict&#x27; in C++ code</li>
<li> util: Make Solaris implemention of p_atomic_add work with gcc</li>
<li> util: Workaround lack of flock on Solaris</li>
<li> util: Solaris has linux-style pthread_setname_np</li>
<li> meson: recognize &quot;sunos&quot; as the system name for Solaris</li>
<li> intel/common: include unistd.h for ioctl() prototype on Solaris</li>
<p></p>
<p>Alejandro Piñeiro (1):</p>
<li> v3d: take into account prim_counts_offset</li>
<p></p>
<p>Bas Nieuwenhuizen (3):</p>
<li> radv: Disallow sparse shared images.</li>
<li> nir/dead_cf: Remove dead control flow after infinite loops.</li>
<li> radv: Fix single stage constant flush with merged shaders.</li>
<p></p>
<p>Clément Guérin (1):</p>
<li> radeonsi: enable zerovram for Rocket League</li>
<p></p>
<p>Connor Abbott (2):</p>
<li> nir/sink: Rewrite loop handling logic</li>
<li> nir/sink: Don&#x27;t sink load_ubo to outside of its defining loop</li>
<p></p>
<p>Dylan Baker (1):</p>
<li> docs: Add SHA256 sum for 19.2.1</li>
<p></p>
<p>Eric Engestrom (7):</p>
<li> GL: drop symbols mangling support</li>
<li> meson: rename `glvnd_missing_pc_files` to `not glvnd_has_headers_and_pc_files`</li>
<li> meson: move a couple of include installs around</li>
<li> meson: split headers one per line</li>
<li> meson: split Mesa headers as a separate installation</li>
<li> meson: skip installation of GLVND-provided headers</li>
<li> util/u_atomic: fix return type of p_atomic_{inc,dec}_return() and p_atomic_{cmp,}xchg()</li>
<p></p>
<p>Ian Romanick (2):</p>
<li> nir/search: Fix possible NULL dereference in is_fsign</li>
<li> intel/vec4: Don&#x27;t try both sources as immediates for DPH</li>
<p></p>
<p>James Xiong (1):</p>
<li> iris: finish aux import on get_param</li>
<p></p>
<p>Kenneth Graunke (2):</p>
<li> iris: Properly unreference extra VBOs for draw parameters</li>
<li> iris: Implement the Gen &lt; 9 tessellation quads workaround</li>
<p></p>
<p>Lepton Wu (1):</p>
<li> egl/android: Remove our own reference to buffers.</li>
<p></p>
<p>Lionel Landwerlin (3):</p>
<li> etnaviv: remove variable from global namespace</li>
<li> anv: fix vkUpdateDescriptorSets with inline uniform blocks</li>
<li> anv: fix memory leak on device destroy</li>
<p></p>
<p>Lucas Stach (3):</p>
<li> etnaviv: fix vertex buffer state emission for single stream GPUs</li>
<li> rbug: fix transmitted texture sizes</li>
<li> rbug: unwrap index buffer resource</li>
<p></p>
<p>Pierre-Eric Pelloux-Prayer (1):</p>
<li> mesa: fix invalid target error handling for teximage</li>
<p></p>
<p>Roland Scheidegger (1):</p>
<li> gallivm: Fix saturated signed psub/padd intrinsics on llvm 8</li>
<p></p>
<p>Samuel Pitoiset (6):</p>
<li> drirc: enable vk_x11_override_min_image_count for DOOM</li>
<li> radv: bump minTexelBufferOffsetAlignment to 4</li>
<li> radv: fix DCC fast clear code for intensity formats</li>
<li> Revert &quot;radv: do not emit PKT3_CONTEXT_CONTROL with AMDGPU 3.6.0+&quot;</li>
<li> radv: fix DCC fast clear code for intensity formats (correctly)</li>
<li> radv: fix updating bound fast ds clear values with different aspects</li>
<p></p>
<p>Timothy Arceri (1):</p>
<li> glsl: fix crash compiling bindless samplers inside unnamed UBOs</li>
<p></p>
<p></p>
</ul>
</div>
</body>
</html>

View File

@@ -1,146 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.2.3 Release Notes / 2019-11-06</h1>
<p>
Mesa 19.2.3 is a bug fix release which fixes bugs found since the 19.2.2 release.
</p>
<p>
Mesa 19.2.3 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa 19.2.3 implements the Vulkan 1.1 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksum</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<ul>
<li>None</li>
</ul>
<h2>Bug fixes</h2>
<ul>
<li>19.2.2 fails mesa:util / timespec test on x86</li>
<li>Objects leaving trails in Firefox with antialias and preserveDrawingBuffer in three.js WebGLRednerer with mesa 19.2</li>
<li>glLinkProgram crash when using gcc-9 -O3 -flto due to use of uninitialised value</li>
</ul>
<h2>Changes</h2>
<ul>
<p>Bas Nieuwenhuizen (4):</p>
<li> radv: Fix timeout handling in syncobj wait.</li>
<li> radv: Remove _mesa_locale_init/fini calls.</li>
<li> turnip: Remove _mesa_locale_init/fini calls.</li>
<li> anv: Remove _mesa_locale_init/fini calls.</li>
<p></p>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<li> anv: Fix output of INTEL_DEBUG=bat for chained batches</li>
<p></p>
<p>Danylo Piliaiev (1):</p>
<li> glsl: Initialize all fields of ir_variable in constructor</li>
<p></p>
<p>Dylan Baker (11):</p>
<li> bin/gen_release_notes.py: fix conditional of bugfix</li>
<li> bin/gen_release_notes.py: strip &#x27;#&#x27; from gitlab bugs</li>
<li> bin/gen_release_notes.py: Return &quot;None&quot; if there are no new features</li>
<li> bin/post_version.py: Pass version as an argument</li>
<li> bin/post_version.py: white space fixes</li>
<li> bin/post_release.py: Add .html to hrefs</li>
<li> bin/gen_release_notes.py: html escape all external data</li>
<li> bin/gen_release_notes.py: Add a warning if new features are introduced in a point release</li>
<li> cherry-ignore: update for 19.2.3 cycle</li>
<li> nir: correct use of identity check in python</li>
<li> meson: Add dep_glvnd to egl deps when building with glvnd</li>
<p></p>
<p>Ilia Mirkin (1):</p>
<li> nv50/ir: mark STORE destination inputs as used</li>
<p></p>
<p>Illia Iorin (1):</p>
<li> Revert &quot;mesa/main: Fix multisample texture initialize&quot;</li>
<p></p>
<p>Jason Ekstrand (2):</p>
<li> anv: Fix a potential BO handle leak</li>
<li> anv/tests: Zero-initialize instances</li>
<p></p>
<p>Jon Turney (2):</p>
<li> rbug: Fix use of alloca() without #include &quot;c99_alloca.h&quot;</li>
<li> Fix timespec_from_nsec test for 32-bit time_t</li>
<p></p>
<p>Jonathan Marek (1):</p>
<li> etnaviv: fix depth bias</li>
<p></p>
<p>Kenneth Graunke (1):</p>
<li> iris: Fix &quot;Force Zero RTA Index Enable&quot; setting again</li>
<p></p>
<p>Lionel Landwerlin (2):</p>
<li> anv: fix unwind of vkCreateDevice fail</li>
<li> mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv</li>
<p></p>
<p>Marek Olšák (1):</p>
<li> util/u_queue: skip util_queue_finish if num_threads is 0</li>
<p></p>
<p>Nanley Chery (5):</p>
<li> anv: Properly allocate aux-tracking space for CCS_E</li>
<li> intel/blorp: Disable depth testing for slow depth clears</li>
<li> iris: Clear ::has_hiz when disabling aux</li>
<li> iris: Don&#x27;t leak the resource for unsupported modifier</li>
<li> iris: Disallow incomplete resource creation</li>
<p></p>
<p>Paulo Zanoni (1):</p>
<li> intel/compiler: remove the operand restriction for src1 on GLK</li>
<p></p>
<p>Pierre-Eric Pelloux-Prayer (1):</p>
<li> mesa: enable msaa in clear_with_quad if needed</li>
<p></p>
<p>Sagar Ghuge (1):</p>
<li> intel/blorp: Assign correct view while clearing depth stencil</li>
<p></p>
<p>Samuel Pitoiset (4):</p>
<li> radv: do not create meta pipelines with 16 samples</li>
<li> radv: do not emit rbplus if attachments are undefined</li>
<li> radv/gfx10: fix 3D images</li>
<li> radv: fix vkUpdateDescriptorSets with inline uniform blocks</li>
<p></p>
<p>Tapani Pälli (1):</p>
<li> i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORM</li>
<p></p>
<p>Thomas Hellstrom (2):</p>
<li> svga: Fix banded DMA upload unmap</li>
<li> winsys/svga: Limit the maximum DMA hardware buffer size</li>
<p></p>
<p></p>
</ul>
</div>
</body>
</html>

View File

@@ -1,65 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.2.4 Release Notes / 2019-11-13</h1>
<p>
Mesa 19.2.4 is an emergency bug fix release to fix on ciritcal bug in 19.2.3.
</p>
<p>
Mesa 19.2.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<p>
Mesa 19.2.4 implements the Vulkan 1.1 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
</p>
<h2>SHA256 checksum</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<ul>
<li>None</li>
</ul>
<h2>Bug fixes</h2>
<ul>
<li>Dirt Rally: Menu system doesn&#x27;t show up with Mesa 19.2.3</li>
</ul>
<h2>Changes</h2>
<ul>
<p>Lionel Landwerlin (1):</p>
<li> mesa: check framebuffer completeness only after state update</li>
<p></p>
<p></p>
</ul>
</div>
</body>
</html>

View File

@@ -33,16 +33,12 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
** Khronos $Git commit SHA1: cb927ca98d $ on $Git commit date: 2019-08-08 01:05:38 -0700 $
** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
*/
#include <EGL/eglplatform.h>
#ifndef EGL_EGL_PROTOTYPES
#define EGL_EGL_PROTOTYPES 1
#endif
/* Generated on date 20190808 */
/* Generated on date 20190124 */
/* Generated C header for:
* API: egl
@@ -122,31 +118,6 @@ typedef void (*__eglMustCastToProperFunctionPointerType)(void);
#define EGL_VERSION 0x3054
#define EGL_WIDTH 0x3057
#define EGL_WINDOW_BIT 0x0004
typedef EGLBoolean (EGLAPIENTRYP PFNEGLCHOOSECONFIGPROC) (EGLDisplay dpy, const EGLint *attrib_list, EGLConfig *configs, EGLint config_size, EGLint *num_config);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLCOPYBUFFERSPROC) (EGLDisplay dpy, EGLSurface surface, EGLNativePixmapType target);
typedef EGLContext (EGLAPIENTRYP PFNEGLCREATECONTEXTPROC) (EGLDisplay dpy, EGLConfig config, EGLContext share_context, const EGLint *attrib_list);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEPBUFFERSURFACEPROC) (EGLDisplay dpy, EGLConfig config, const EGLint *attrib_list);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEPIXMAPSURFACEPROC) (EGLDisplay dpy, EGLConfig config, EGLNativePixmapType pixmap, const EGLint *attrib_list);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEWINDOWSURFACEPROC) (EGLDisplay dpy, EGLConfig config, EGLNativeWindowType win, const EGLint *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYCONTEXTPROC) (EGLDisplay dpy, EGLContext ctx);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYSURFACEPROC) (EGLDisplay dpy, EGLSurface surface);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLGETCONFIGATTRIBPROC) (EGLDisplay dpy, EGLConfig config, EGLint attribute, EGLint *value);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLGETCONFIGSPROC) (EGLDisplay dpy, EGLConfig *configs, EGLint config_size, EGLint *num_config);
typedef EGLDisplay (EGLAPIENTRYP PFNEGLGETCURRENTDISPLAYPROC) (void);
typedef EGLSurface (EGLAPIENTRYP PFNEGLGETCURRENTSURFACEPROC) (EGLint readdraw);
typedef EGLDisplay (EGLAPIENTRYP PFNEGLGETDISPLAYPROC) (EGLNativeDisplayType display_id);
typedef EGLint (EGLAPIENTRYP PFNEGLGETERRORPROC) (void);
typedef __eglMustCastToProperFunctionPointerType (EGLAPIENTRYP PFNEGLGETPROCADDRESSPROC) (const char *procname);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLINITIALIZEPROC) (EGLDisplay dpy, EGLint *major, EGLint *minor);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLMAKECURRENTPROC) (EGLDisplay dpy, EGLSurface draw, EGLSurface read, EGLContext ctx);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYCONTEXTPROC) (EGLDisplay dpy, EGLContext ctx, EGLint attribute, EGLint *value);
typedef const char *(EGLAPIENTRYP PFNEGLQUERYSTRINGPROC) (EGLDisplay dpy, EGLint name);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYSURFACEPROC) (EGLDisplay dpy, EGLSurface surface, EGLint attribute, EGLint *value);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSWAPBUFFERSPROC) (EGLDisplay dpy, EGLSurface surface);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLTERMINATEPROC) (EGLDisplay dpy);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLWAITGLPROC) (void);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLWAITNATIVEPROC) (EGLint engine);
#if EGL_EGL_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglChooseConfig (EGLDisplay dpy, const EGLint *attrib_list, EGLConfig *configs, EGLint config_size, EGLint *num_config);
EGLAPI EGLBoolean EGLAPIENTRY eglCopyBuffers (EGLDisplay dpy, EGLSurface surface, EGLNativePixmapType target);
EGLAPI EGLContext EGLAPIENTRY eglCreateContext (EGLDisplay dpy, EGLConfig config, EGLContext share_context, const EGLint *attrib_list);
@@ -171,7 +142,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglSwapBuffers (EGLDisplay dpy, EGLSurface surface
EGLAPI EGLBoolean EGLAPIENTRY eglTerminate (EGLDisplay dpy);
EGLAPI EGLBoolean EGLAPIENTRY eglWaitGL (void);
EGLAPI EGLBoolean EGLAPIENTRY eglWaitNative (EGLint engine);
#endif
#endif /* EGL_VERSION_1_0 */
#ifndef EGL_VERSION_1_1
@@ -190,16 +160,10 @@ EGLAPI EGLBoolean EGLAPIENTRY eglWaitNative (EGLint engine);
#define EGL_TEXTURE_RGB 0x305D
#define EGL_TEXTURE_RGBA 0x305E
#define EGL_TEXTURE_TARGET 0x3081
typedef EGLBoolean (EGLAPIENTRYP PFNEGLBINDTEXIMAGEPROC) (EGLDisplay dpy, EGLSurface surface, EGLint buffer);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLRELEASETEXIMAGEPROC) (EGLDisplay dpy, EGLSurface surface, EGLint buffer);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSURFACEATTRIBPROC) (EGLDisplay dpy, EGLSurface surface, EGLint attribute, EGLint value);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSWAPINTERVALPROC) (EGLDisplay dpy, EGLint interval);
#if EGL_EGL_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglBindTexImage (EGLDisplay dpy, EGLSurface surface, EGLint buffer);
EGLAPI EGLBoolean EGLAPIENTRY eglReleaseTexImage (EGLDisplay dpy, EGLSurface surface, EGLint buffer);
EGLAPI EGLBoolean EGLAPIENTRY eglSurfaceAttrib (EGLDisplay dpy, EGLSurface surface, EGLint attribute, EGLint value);
EGLAPI EGLBoolean EGLAPIENTRY eglSwapInterval (EGLDisplay dpy, EGLint interval);
#endif
#endif /* EGL_VERSION_1_1 */
#ifndef EGL_VERSION_1_2
@@ -235,18 +199,11 @@ typedef void *EGLClientBuffer;
#define EGL_SWAP_BEHAVIOR 0x3093
#define EGL_UNKNOWN EGL_CAST(EGLint,-1)
#define EGL_VERTICAL_RESOLUTION 0x3091
typedef EGLBoolean (EGLAPIENTRYP PFNEGLBINDAPIPROC) (EGLenum api);
typedef EGLenum (EGLAPIENTRYP PFNEGLQUERYAPIPROC) (void);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEPBUFFERFROMCLIENTBUFFERPROC) (EGLDisplay dpy, EGLenum buftype, EGLClientBuffer buffer, EGLConfig config, const EGLint *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLRELEASETHREADPROC) (void);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLWAITCLIENTPROC) (void);
#if EGL_EGL_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglBindAPI (EGLenum api);
EGLAPI EGLenum EGLAPIENTRY eglQueryAPI (void);
EGLAPI EGLSurface EGLAPIENTRY eglCreatePbufferFromClientBuffer (EGLDisplay dpy, EGLenum buftype, EGLClientBuffer buffer, EGLConfig config, const EGLint *attrib_list);
EGLAPI EGLBoolean EGLAPIENTRY eglReleaseThread (void);
EGLAPI EGLBoolean EGLAPIENTRY eglWaitClient (void);
#endif
#endif /* EGL_VERSION_1_2 */
#ifndef EGL_VERSION_1_3
@@ -275,10 +232,7 @@ EGLAPI EGLBoolean EGLAPIENTRY eglWaitClient (void);
#define EGL_OPENGL_API 0x30A2
#define EGL_OPENGL_BIT 0x0008
#define EGL_SWAP_BEHAVIOR_PRESERVED_BIT 0x0400
typedef EGLContext (EGLAPIENTRYP PFNEGLGETCURRENTCONTEXTPROC) (void);
#if EGL_EGL_PROTOTYPES
EGLAPI EGLContext EGLAPIENTRY eglGetCurrentContext (void);
#endif
#endif /* EGL_VERSION_1_4 */
#ifndef EGL_VERSION_1_5
@@ -330,17 +284,6 @@ typedef void *EGLImage;
#define EGL_GL_TEXTURE_CUBE_MAP_NEGATIVE_Z 0x30B8
#define EGL_IMAGE_PRESERVED 0x30D2
#define EGL_NO_IMAGE EGL_CAST(EGLImage,0)
typedef EGLSync (EGLAPIENTRYP PFNEGLCREATESYNCPROC) (EGLDisplay dpy, EGLenum type, const EGLAttrib *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYSYNCPROC) (EGLDisplay dpy, EGLSync sync);
typedef EGLint (EGLAPIENTRYP PFNEGLCLIENTWAITSYNCPROC) (EGLDisplay dpy, EGLSync sync, EGLint flags, EGLTime timeout);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLGETSYNCATTRIBPROC) (EGLDisplay dpy, EGLSync sync, EGLint attribute, EGLAttrib *value);
typedef EGLImage (EGLAPIENTRYP PFNEGLCREATEIMAGEPROC) (EGLDisplay dpy, EGLContext ctx, EGLenum target, EGLClientBuffer buffer, const EGLAttrib *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLDESTROYIMAGEPROC) (EGLDisplay dpy, EGLImage image);
typedef EGLDisplay (EGLAPIENTRYP PFNEGLGETPLATFORMDISPLAYPROC) (EGLenum platform, void *native_display, const EGLAttrib *attrib_list);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEPLATFORMWINDOWSURFACEPROC) (EGLDisplay dpy, EGLConfig config, void *native_window, const EGLAttrib *attrib_list);
typedef EGLSurface (EGLAPIENTRYP PFNEGLCREATEPLATFORMPIXMAPSURFACEPROC) (EGLDisplay dpy, EGLConfig config, void *native_pixmap, const EGLAttrib *attrib_list);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLWAITSYNCPROC) (EGLDisplay dpy, EGLSync sync, EGLint flags);
#if EGL_EGL_PROTOTYPES
EGLAPI EGLSync EGLAPIENTRY eglCreateSync (EGLDisplay dpy, EGLenum type, const EGLAttrib *attrib_list);
EGLAPI EGLBoolean EGLAPIENTRY eglDestroySync (EGLDisplay dpy, EGLSync sync);
EGLAPI EGLint EGLAPIENTRY eglClientWaitSync (EGLDisplay dpy, EGLSync sync, EGLint flags, EGLTime timeout);
@@ -351,7 +294,6 @@ EGLAPI EGLDisplay EGLAPIENTRY eglGetPlatformDisplay (EGLenum platform, void *nat
EGLAPI EGLSurface EGLAPIENTRY eglCreatePlatformWindowSurface (EGLDisplay dpy, EGLConfig config, void *native_window, const EGLAttrib *attrib_list);
EGLAPI EGLSurface EGLAPIENTRY eglCreatePlatformPixmapSurface (EGLDisplay dpy, EGLConfig config, void *native_pixmap, const EGLAttrib *attrib_list);
EGLAPI EGLBoolean EGLAPIENTRY eglWaitSync (EGLDisplay dpy, EGLSync sync, EGLint flags);
#endif
#endif /* EGL_VERSION_1_5 */
#ifdef __cplusplus

View File

@@ -33,12 +33,12 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
** Khronos $Git commit SHA1: cb927ca98d $ on $Git commit date: 2019-08-08 01:05:38 -0700 $
** Khronos $Git commit SHA1: 9ed2ec4c67 $ on $Git commit date: 2019-01-09 17:54:35 -0800 $
*/
#include <EGL/eglplatform.h>
#define EGL_EGLEXT_VERSION 20190808
#define EGL_EGLEXT_VERSION 20190124
/* Generated C header for:
* API: egl
@@ -462,10 +462,6 @@ EGLAPI EGLint EGLAPIENTRY eglWaitSyncKHR (EGLDisplay dpy, EGLSyncKHR sync, EGLin
#endif
#endif /* EGL_KHR_wait_sync */
#ifndef EGL_ANDROID_GLES_layers
#define EGL_ANDROID_GLES_layers 1
#endif /* EGL_ANDROID_GLES_layers */
#ifndef EGL_ANDROID_blob_cache
#define EGL_ANDROID_blob_cache 1
typedef khronos_ssize_t EGLsizeiANDROID;
@@ -1133,11 +1129,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglPostSubBufferNV (EGLDisplay dpy, EGLSurface sur
#endif
#endif /* EGL_NV_post_sub_buffer */
#ifndef EGL_NV_quadruple_buffer
#define EGL_NV_quadruple_buffer 1
#define EGL_QUADRUPLE_BUFFER_NV 0x3231
#endif /* EGL_NV_quadruple_buffer */
#ifndef EGL_NV_robustness_video_memory_purge
#define EGL_NV_robustness_video_memory_purge 1
#define EGL_GENERATE_RESET_ON_VIDEO_MEMORY_PURGE_NV 0x334C
@@ -1179,12 +1170,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglStreamConsumerGLTextureExternalAttribsNV (EGLDi
#define EGL_STREAM_CROSS_SYSTEM_NV 0x334F
#endif /* EGL_NV_stream_cross_system */
#ifndef EGL_NV_stream_dma
#define EGL_NV_stream_dma 1
#define EGL_STREAM_DMA_NV 0x3371
#define EGL_STREAM_DMA_SERVER_NV 0x3372
#endif /* EGL_NV_stream_dma */
#ifndef EGL_NV_stream_fifo_next
#define EGL_NV_stream_fifo_next 1
#define EGL_PENDING_FRAME_NV 0x3329
@@ -1236,21 +1221,6 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryStreamMetadataNV (EGLDisplay dpy, EGLStrea
#endif
#endif /* EGL_NV_stream_metadata */
#ifndef EGL_NV_stream_origin
#define EGL_NV_stream_origin 1
#define EGL_STREAM_FRAME_ORIGIN_X_NV 0x3366
#define EGL_STREAM_FRAME_ORIGIN_Y_NV 0x3367
#define EGL_STREAM_FRAME_MAJOR_AXIS_NV 0x3368
#define EGL_CONSUMER_AUTO_ORIENTATION_NV 0x3369
#define EGL_PRODUCER_AUTO_ORIENTATION_NV 0x336A
#define EGL_LEFT_NV 0x336B
#define EGL_RIGHT_NV 0x336C
#define EGL_TOP_NV 0x336D
#define EGL_BOTTOM_NV 0x336E
#define EGL_X_AXIS_NV 0x336F
#define EGL_Y_AXIS_NV 0x3370
#endif /* EGL_NV_stream_origin */
#ifndef EGL_NV_stream_remote
#define EGL_NV_stream_remote 1
#define EGL_STREAM_STATE_INITIALIZING_NV 0x3240
@@ -1347,11 +1317,6 @@ EGLAPI EGLuint64NV EGLAPIENTRY eglGetSystemTimeNV (void);
#endif /* KHRONOS_SUPPORT_INT64 */
#endif /* EGL_NV_system_time */
#ifndef EGL_NV_triple_buffer
#define EGL_NV_triple_buffer 1
#define EGL_TRIPLE_BUFFER_NV 0x3230
#endif /* EGL_NV_triple_buffer */
#ifndef EGL_TIZEN_image_native_buffer
#define EGL_TIZEN_image_native_buffer 1
#define EGL_NATIVE_BUFFER_TIZEN 0x32A0

View File

@@ -77,17 +77,11 @@ typedef HDC EGLNativeDisplayType;
typedef HBITMAP EGLNativePixmapType;
typedef HWND EGLNativeWindowType;
#elif defined(__EMSCRIPTEN__)
typedef int EGLNativeDisplayType;
typedef int EGLNativePixmapType;
typedef int EGLNativeWindowType;
#elif defined(__WINSCW__) || defined(__SYMBIAN32__) /* Symbian */
typedef int EGLNativeDisplayType;
typedef void *EGLNativePixmapType;
typedef void *EGLNativeWindowType;
typedef void *EGLNativePixmapType;
#elif defined(WL_EGL_PLATFORM)
@@ -106,15 +100,15 @@ typedef void *EGLNativeWindowType;
struct ANativeWindow;
struct egl_native_pixmap_t;
typedef void* EGLNativeDisplayType;
typedef struct egl_native_pixmap_t* EGLNativePixmapType;
typedef struct ANativeWindow* EGLNativeWindowType;
typedef struct egl_native_pixmap_t* EGLNativePixmapType;
typedef void* EGLNativeDisplayType;
#elif defined(USE_OZONE)
typedef intptr_t EGLNativeDisplayType;
typedef intptr_t EGLNativePixmapType;
typedef intptr_t EGLNativeWindowType;
typedef intptr_t EGLNativePixmapType;
#elif defined(__unix__) || defined(__APPLE__)

View File

@@ -27,6 +27,11 @@
#ifndef __gl_h_
#define __gl_h_
#if defined(USE_MGL_NAMESPACE)
#include "gl_mangle.h"
#endif
/**********************************************************************
* Begin system-specific stuff.
*/
@@ -2096,6 +2101,13 @@ typedef void (APIENTRYP PFNGLEGLIMAGETARGETRENDERBUFFERSTORAGEOESPROC) (GLenum t
#endif
/**
** NOTE!!!!! If you add new functions to this file, or update
** glext.h be sure to regenerate the gl_mangle.h file. See comments
** in that file for details.
**/
#ifdef __cplusplus
}
#endif

2809
include/GL/gl_mangle.h Normal file

File diff suppressed because it is too large Load Diff

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@@ -32,6 +32,11 @@
#include <GL/gl.h>
#if defined(USE_MGL_NAMESPACE)
#include "glx_mangle.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif

82
include/GL/glx_mangle.h Normal file
View File

@@ -0,0 +1,82 @@
/*
* Mesa 3-D graphics library
*
* Copyright (C) 1999-2006 Brian Paul All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GLX_MANGLE_H
#define GLX_MANGLE_H
#define glXChooseVisual mglXChooseVisual
#define glXCreateContext mglXCreateContext
#define glXDestroyContext mglXDestroyContext
#define glXMakeCurrent mglXMakeCurrent
#define glXCopyContext mglXCopyContext
#define glXSwapBuffers mglXSwapBuffers
#define glXCreateGLXPixmap mglXCreateGLXPixmap
#define glXDestroyGLXPixmap mglXDestroyGLXPixmap
#define glXQueryExtension mglXQueryExtension
#define glXQueryVersion mglXQueryVersion
#define glXIsDirect mglXIsDirect
#define glXGetConfig mglXGetConfig
#define glXGetCurrentContext mglXGetCurrentContext
#define glXGetCurrentDrawable mglXGetCurrentDrawable
#define glXWaitGL mglXWaitGL
#define glXWaitX mglXWaitX
#define glXUseXFont mglXUseXFont
#define glXQueryExtensionsString mglXQueryExtensionsString
#define glXQueryServerString mglXQueryServerString
#define glXGetClientString mglXGetClientString
#define glXCreateGLXPixmapMESA mglXCreateGLXPixmapMESA
#define glXReleaseBuffersMESA mglXReleaseBuffersMESA
#define glXCopySubBufferMESA mglXCopySubBufferMESA
#define glXGetVideoSyncSGI mglXGetVideoSyncSGI
#define glXWaitVideoSyncSGI mglXWaitVideoSyncSGI
/* GLX 1.2 */
#define glXGetCurrentDisplay mglXGetCurrentDisplay
/* GLX 1.3 */
#define glXChooseFBConfig mglXChooseFBConfig
#define glXGetFBConfigAttrib mglXGetFBConfigAttrib
#define glXGetFBConfigs mglXGetFBConfigs
#define glXGetVisualFromFBConfig mglXGetVisualFromFBConfig
#define glXCreateWindow mglXCreateWindow
#define glXDestroyWindow mglXDestroyWindow
#define glXCreatePixmap mglXCreatePixmap
#define glXDestroyPixmap mglXDestroyPixmap
#define glXCreatePbuffer mglXCreatePbuffer
#define glXDestroyPbuffer mglXDestroyPbuffer
#define glXQueryDrawable mglXQueryDrawable
#define glXCreateNewContext mglXCreateNewContext
#define glXMakeContextCurrent mglXMakeContextCurrent
#define glXGetCurrentReadDrawable mglXGetCurrentReadDrawable
#define glXQueryContext mglXQueryContext
#define glXSelectEvent mglXSelectEvent
#define glXGetSelectedEvent mglXGetSelectedEvent
/* GLX 1.4 */
#define glXGetProcAddress mglXGetProcAddress
#define glXGetProcAddressARB mglXGetProcAddressARB
#endif

View File

@@ -85,7 +85,6 @@ typedef struct __DRI2throttleExtensionRec __DRI2throttleExtension;
typedef struct __DRI2fenceExtensionRec __DRI2fenceExtension;
typedef struct __DRI2interopExtensionRec __DRI2interopExtension;
typedef struct __DRI2blobExtensionRec __DRI2blobExtension;
typedef struct __DRI2bufferDamageExtensionRec __DRI2bufferDamageExtension;
typedef struct __DRIimageLoaderExtensionRec __DRIimageLoaderExtension;
typedef struct __DRIimageDriverExtensionRec __DRIimageDriverExtension;
@@ -489,48 +488,6 @@ struct __DRI2interopExtensionRec {
struct mesa_glinterop_export_out *out);
};
/**
* Extension for limiting window system back buffer rendering to user-defined
* scissor region.
*/
#define __DRI2_BUFFER_DAMAGE "DRI2_BufferDamage"
#define __DRI2_BUFFER_DAMAGE_VERSION 1
struct __DRI2bufferDamageExtensionRec {
__DRIextension base;
/**
* Provides an array of rectangles representing an overriding scissor region
* for rendering operations performed to the specified drawable. These
* rectangles do not replace client API scissor regions or draw
* co-ordinates, but instead inform the driver of the overall bounds of all
* operations which will be issued before the next flush.
*
* Any rendering operations writing pixels outside this region to the
* drawable will have an undefined effect on the entire drawable.
*
* This entrypoint may only be called after the drawable has either been
* newly created or flushed, and before any rendering operations which write
* pixels to the drawable. Calling this entrypoint at any other time will
* have an undefined effect on the entire drawable.
*
* Calling this entrypoint with @nrects 0 and @rects NULL will reset the
* region to the buffer's full size. This entrypoint may be called once to
* reset the region, followed by a second call with a populated region,
* before a rendering call is made.
*
* Used to implement EGL_KHR_partial_update.
*
* \param drawable affected drawable
* \param nrects number of rectangles provided
* \param rects the array of rectangles, lower-left origin
*/
void (*set_damage_region)(__DRIdrawable *drawable, unsigned int nrects,
int *rects);
};
/*@}*/
/**

View File

@@ -12,6 +12,7 @@ Normal Haiku Op*enGL layout:
* headers/os/opengl/GLView.h
* headers/os/opengl/GLRenderer.h
* headers/os/opengl/GL/gl.h
* headers/os/opengl/GL/gl_mangle.h
* headers/os/opengl/GL/glext.h
* headers/os/opengl/GL/osmesa.h (needed?)

View File

@@ -2,7 +2,7 @@
#define __khrplatform_h_
/*
** Copyright (c) 2008-2018 The Khronos Group Inc.
** Copyright (c) 2008-2009 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
@@ -26,16 +26,18 @@
/* Khronos platform-specific types and definitions.
*
* The master copy of khrplatform.h is maintained in the Khronos EGL
* Registry repository at https://github.com/KhronosGroup/EGL-Registry
* The last semantic modification to khrplatform.h was at commit ID:
* 67a3e0864c2d75ea5287b9f3d2eb74a745936692
* $Revision: 32517 $ on $Date: 2016-03-11 02:41:19 -0800 (Fri, 11 Mar 2016) $
*
* Adopters may modify this file to suit their platform. Adopters are
* encouraged to submit platform specific modifications to the Khronos
* group so that they can be included in future versions of this file.
* Please submit changes by filing pull requests or issues on
* the EGL Registry repository linked above.
* Please submit changes by sending them to the public Khronos Bugzilla
* (http://khronos.org/bugzilla) by filing a bug against product
* "Khronos (general)" component "Registry".
*
* A predefined template which fills in some of the bug fields can be
* reached using http://tinyurl.com/khrplatform-h-bugreport, but you
* must create a Bugzilla login first.
*
*
* See the Implementer's Guidelines for information about where this file
@@ -90,20 +92,12 @@
* int arg2) KHRONOS_APIATTRIBUTES;
*/
#if defined(__SCITECH_SNAP__) && !defined(KHRONOS_STATIC)
# define KHRONOS_STATIC 1
#endif
/*-------------------------------------------------------------------------
* Definition of KHRONOS_APICALL
*-------------------------------------------------------------------------
* This precedes the return type of the function in the function prototype.
*/
#if defined(KHRONOS_STATIC)
/* If the preprocessor constant KHRONOS_STATIC is defined, make the
* header compatible with static linking. */
# define KHRONOS_APICALL
#elif defined(_WIN32)
#if defined(_WIN32) && !defined(__SCITECH_SNAP__)
# define KHRONOS_APICALL __declspec(dllimport)
#elif defined (__SYMBIAN32__)
# define KHRONOS_APICALL IMPORT_C
@@ -121,7 +115,7 @@
* This follows the return type of the function and precedes the function
* name in the function prototype.
*/
#if defined(_WIN32) && !defined(_WIN32_WCE) && !defined(KHRONOS_STATIC)
#if defined(_WIN32) && !defined(_WIN32_WCE) && !defined(__SCITECH_SNAP__)
/* Win32 but not WinCE */
# define KHRONOS_APIENTRY __stdcall
#else

View File

@@ -1,27 +0,0 @@
/* Copyright 2019 Intel Corporation */
/* SPDX-License-Identifier: MIT */
#include "no_extern_c.h"
#ifndef _C11_COMPAT_H_
#define _C11_COMPAT_H_
#if defined(__cplusplus)
/* This is C++ code, not C */
#elif (__STDC_VERSION__ >= 201112L)
/* Already C11 */
#else
/*
* C11 static_assert() macro
* assert.h only defines that name for C11 and above
*/
#ifndef static_assert
#define static_assert _Static_assert
#endif
#endif /* !C++ && !C11 */
#endif /* _C11_COMPAT_H_ */

View File

@@ -96,7 +96,7 @@
* - http://cellperformance.beyond3d.com/articles/2006/05/demystifying-the-restrict-keyword.html
*/
#ifndef restrict
# if (__STDC_VERSION__ >= 199901L) && !defined(__cplusplus)
# if (__STDC_VERSION__ >= 199901L)
/* C99 */
# elif defined(__GNUC__)
# define restrict __restrict__

View File

@@ -18,9 +18,6 @@ extern "C" {
#define DRM_PANFROST_MMAP_BO 0x03
#define DRM_PANFROST_GET_PARAM 0x04
#define DRM_PANFROST_GET_BO_OFFSET 0x05
#define DRM_PANFROST_PERFCNT_ENABLE 0x06
#define DRM_PANFROST_PERFCNT_DUMP 0x07
#define DRM_PANFROST_MADVISE 0x08
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
@@ -28,16 +25,6 @@ extern "C" {
#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo)
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise)
/*
* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
* param is set to true.
* All these ioctl(s) are subject to deprecation, so please don't rely on
* them for anything but debugging purpose.
*/
#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable)
#define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump)
#define PANFROST_JD_REQ_FS (1 << 0)
/**
@@ -84,9 +71,6 @@ struct drm_panfrost_wait_bo {
__s64 timeout_ns; /* absolute */
};
#define PANFROST_BO_NOEXEC 1
#define PANFROST_BO_HEAP 2
/**
* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
*
@@ -132,45 +116,6 @@ struct drm_panfrost_mmap_bo {
enum drm_panfrost_param {
DRM_PANFROST_PARAM_GPU_PROD_ID,
DRM_PANFROST_PARAM_GPU_REVISION,
DRM_PANFROST_PARAM_SHADER_PRESENT,
DRM_PANFROST_PARAM_TILER_PRESENT,
DRM_PANFROST_PARAM_L2_PRESENT,
DRM_PANFROST_PARAM_STACK_PRESENT,
DRM_PANFROST_PARAM_AS_PRESENT,
DRM_PANFROST_PARAM_JS_PRESENT,
DRM_PANFROST_PARAM_L2_FEATURES,
DRM_PANFROST_PARAM_CORE_FEATURES,
DRM_PANFROST_PARAM_TILER_FEATURES,
DRM_PANFROST_PARAM_MEM_FEATURES,
DRM_PANFROST_PARAM_MMU_FEATURES,
DRM_PANFROST_PARAM_THREAD_FEATURES,
DRM_PANFROST_PARAM_MAX_THREADS,
DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ,
DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ,
DRM_PANFROST_PARAM_COHERENCY_FEATURES,
DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
DRM_PANFROST_PARAM_TEXTURE_FEATURES1,
DRM_PANFROST_PARAM_TEXTURE_FEATURES2,
DRM_PANFROST_PARAM_TEXTURE_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES0,
DRM_PANFROST_PARAM_JS_FEATURES1,
DRM_PANFROST_PARAM_JS_FEATURES2,
DRM_PANFROST_PARAM_JS_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES4,
DRM_PANFROST_PARAM_JS_FEATURES5,
DRM_PANFROST_PARAM_JS_FEATURES6,
DRM_PANFROST_PARAM_JS_FEATURES7,
DRM_PANFROST_PARAM_JS_FEATURES8,
DRM_PANFROST_PARAM_JS_FEATURES9,
DRM_PANFROST_PARAM_JS_FEATURES10,
DRM_PANFROST_PARAM_JS_FEATURES11,
DRM_PANFROST_PARAM_JS_FEATURES12,
DRM_PANFROST_PARAM_JS_FEATURES13,
DRM_PANFROST_PARAM_JS_FEATURES14,
DRM_PANFROST_PARAM_JS_FEATURES15,
DRM_PANFROST_PARAM_NR_CORE_GROUPS,
DRM_PANFROST_PARAM_THREAD_TLS_ALLOC,
};
struct drm_panfrost_get_param {
@@ -190,39 +135,6 @@ struct drm_panfrost_get_bo_offset {
__u64 offset;
};
struct drm_panfrost_perfcnt_enable {
__u32 enable;
/*
* On bifrost we have 2 sets of counters, this parameter defines the
* one to track.
*/
__u32 counterset;
};
struct drm_panfrost_perfcnt_dump {
__u64 buf_ptr;
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */
struct drm_panfrost_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, PANFROST_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
#if defined(__cplusplus)
}
#endif

View File

@@ -22,77 +22,52 @@ inc_include = include_directories('.')
inc_d3d9 = include_directories('D3D9')
inc_haikugl = include_directories('HaikuGL')
if not glvnd_has_headers_and_pc_files
if with_gles1 or with_gles2 or with_opengl or with_egl
install_headers('KHR/khrplatform.h', subdir : 'KHR')
endif
if with_gles1
install_headers(
'GLES/egl.h',
'GLES/gl.h',
'GLES/glext.h',
'GLES/glplatform.h',
subdir : 'GLES',
)
endif
if with_gles2
install_headers(
'GLES2/gl2.h',
'GLES2/gl2ext.h',
'GLES2/gl2platform.h',
subdir : 'GLES2',
)
install_headers(
'GLES3/gl3.h',
'GLES3/gl31.h',
'GLES3/gl32.h',
'GLES3/gl3ext.h',
'GLES3/gl3platform.h',
subdir : 'GLES3',
)
endif
if with_opengl
install_headers(
'GL/gl.h',
'GL/glcorearb.h',
'GL/glext.h',
subdir : 'GL',
)
endif
if with_glx != 'disabled'
install_headers(
'GL/glx.h',
'GL/glxext.h',
subdir : 'GL')
endif
if with_egl
install_headers(
'EGL/egl.h',
'EGL/eglext.h',
'EGL/eglplatform.h',
subdir : 'EGL',
)
endif
if with_gles1
install_headers(
'GLES/egl.h', 'GLES/gl.h', 'GLES/glext.h', 'GLES/glplatform.h',
subdir : 'GLES',
)
endif
# Non-upstream headers
if with_egl
if with_gles2
install_headers(
'EGL/eglmesaext.h',
'EGL/eglextchromium.h',
subdir : 'EGL',
'GLES2/gl2.h', 'GLES2/gl2ext.h', 'GLES2/gl2platform.h',
subdir : 'GLES2',
)
install_headers(
'GLES3/gl3.h', 'GLES3/gl31.h', 'GLES3/gl32.h', 'GLES3/gl3ext.h',
'GLES3/gl3platform.h',
subdir : 'GLES3',
)
endif
if with_gles1 or with_gles2 or with_opengl or with_egl
install_headers('KHR/khrplatform.h', subdir : 'KHR')
endif
if with_opengl
install_headers(
'GL/gl.h', 'GL/glext.h', 'GL/glcorearb.h', 'GL/gl_mangle.h',
subdir : 'GL',
)
endif
if with_glx != 'disabled'
install_headers('GL/glx.h', 'GL/glxext.h', 'GL/glx_mangle.h', subdir : 'GL')
endif
if with_osmesa != 'none'
install_headers('GL/osmesa.h', subdir : 'GL')
endif
if with_egl
install_headers(
'EGL/eglext.h', 'EGL/egl.h', 'EGL/eglextchromium.h', 'EGL/eglmesaext.h',
'EGL/eglplatform.h',
subdir : 'EGL',
)
endif
if with_dri
install_headers('GL/internal/dri_interface.h', subdir : 'GL/internal')
endif

View File

@@ -186,29 +186,29 @@ CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA1, cfl_gt1, "Intel(R) UHD Graphics (Whiskey Lake 2x6 GT1)")
CHIPSET(0x3EA4, cfl_gt1, "Intel(R) UHD Graphics (Whiskey Lake 3x8 GT1)")
CHIPSET(0x3EA0, cfl_gt2, "Intel(R) UHD Graphics (Whiskey Lake 3x8 GT2)")
CHIPSET(0x3EA3, cfl_gt2, "Intel(R) UHD Graphics (Whiskey Lake 3x8 GT2)")
CHIPSET(0x3EA2, cfl_gt3, "Intel(R) UHD Graphics (Whiskey Lake 3x8 GT3)")
CHIPSET(0x9B21, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA0, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA2, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA4, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA5, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA8, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAA, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAB, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAC, cfl_gt1, "Intel(R) UHD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9B41, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC0, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC2, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC4, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC5, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC8, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCA, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCB, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCC, cfl_gt2, "Intel(R) UHD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 2x6 GT1)")
CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT1)")
CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)")
CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT3)")
CHIPSET(0x9B21, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA0, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA2, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA4, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA5, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BA8, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAA, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAB, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9BAC, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)")
CHIPSET(0x9B41, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC0, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC2, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC4, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC5, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BC8, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCA, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCB, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x9BCC, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)")
CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")

View File

@@ -254,8 +254,6 @@ CHIPSET(0x66AF, VEGA20)
CHIPSET(0x15DD, RAVEN)
CHIPSET(0x15D8, RAVEN)
CHIPSET(0x1636, RENOIR)
CHIPSET(0x738C, ARCTURUS)
CHIPSET(0x7388, ARCTURUS)
CHIPSET(0x738E, ARCTURUS)
@@ -267,9 +265,3 @@ CHIPSET(0x7319, NAVI10)
CHIPSET(0x731A, NAVI10)
CHIPSET(0x731B, NAVI10)
CHIPSET(0x731F, NAVI10)
CHIPSET(0x7360, NAVI12)
CHIPSET(0x7340, NAVI14)
CHIPSET(0x7341, NAVI14)
CHIPSET(0x7347, NAVI14)

View File

@@ -43,7 +43,7 @@ extern "C" {
#define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
#define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
// Version of this file
#define VK_HEADER_VERSION 119
#define VK_HEADER_VERSION 117
#define VK_NULL_HANDLE 0
@@ -447,7 +447,6 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_MEMORY_HOST_POINTER_PROPERTIES_EXT = 1000178001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT = 1000178002,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR = 1000180000,
VK_STRUCTURE_TYPE_PIPELINE_COMPILER_CONTROL_CREATE_INFO_AMD = 1000183000,
VK_STRUCTURE_TYPE_CALIBRATED_TIMESTAMP_INFO_EXT = 1000184000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD = 1000185000,
VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD = 1000189000,
@@ -488,8 +487,6 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT = 1000221000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT = 1000225000,
VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT = 1000225001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT = 1000225002,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD = 1000227000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT = 1000237000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT = 1000238000,
VK_STRUCTURE_TYPE_MEMORY_PRIORITY_ALLOCATE_INFO_EXT = 1000238001,
@@ -518,12 +515,6 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT = 1000259002,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT = 1000261000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT = 1000265000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR = 1000269000,
VK_STRUCTURE_TYPE_PIPELINE_INFO_KHR = 1000269001,
VK_STRUCTURE_TYPE_PIPELINE_EXECUTABLE_PROPERTIES_KHR = 1000269002,
VK_STRUCTURE_TYPE_PIPELINE_EXECUTABLE_INFO_KHR = 1000269003,
VK_STRUCTURE_TYPE_PIPELINE_EXECUTABLE_STATISTIC_KHR = 1000269004,
VK_STRUCTURE_TYPE_PIPELINE_EXECUTABLE_INTERNAL_REPRESENTATION_KHR = 1000269005,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT = 1000276000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT = 1000281000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT = 1000281001,
@@ -1673,8 +1664,6 @@ typedef enum VkPipelineCreateFlagBits {
VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT = 0x00000008,
VK_PIPELINE_CREATE_DISPATCH_BASE = 0x00000010,
VK_PIPELINE_CREATE_DEFER_COMPILE_BIT_NV = 0x00000020,
VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR = 0x00000040,
VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR = 0x00000080,
VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR = VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT,
VK_PIPELINE_CREATE_DISPATCH_BASE_KHR = VK_PIPELINE_CREATE_DISPATCH_BASE,
VK_PIPELINE_CREATE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
@@ -6372,99 +6361,6 @@ typedef struct VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR {
#define VK_KHR_pipeline_executable_properties 1
#define VK_KHR_PIPELINE_EXECUTABLE_PROPERTIES_SPEC_VERSION 1
#define VK_KHR_PIPELINE_EXECUTABLE_PROPERTIES_EXTENSION_NAME "VK_KHR_pipeline_executable_properties"
typedef enum VkPipelineExecutableStatisticFormatKHR {
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_BOOL32_KHR = 0,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_INT64_KHR = 1,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR = 2,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_FLOAT64_KHR = 3,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_BEGIN_RANGE_KHR = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_BOOL32_KHR,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_END_RANGE_KHR = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_FLOAT64_KHR,
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_RANGE_SIZE_KHR = (VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_FLOAT64_KHR - VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_BOOL32_KHR + 1),
VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_MAX_ENUM_KHR = 0x7FFFFFFF
} VkPipelineExecutableStatisticFormatKHR;
typedef struct VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR {
VkStructureType sType;
void* pNext;
VkBool32 pipelineExecutableInfo;
} VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR;
typedef struct VkPipelineInfoKHR {
VkStructureType sType;
const void* pNext;
VkPipeline pipeline;
} VkPipelineInfoKHR;
typedef struct VkPipelineExecutablePropertiesKHR {
VkStructureType sType;
void* pNext;
VkShaderStageFlags stages;
char name[VK_MAX_DESCRIPTION_SIZE];
char description[VK_MAX_DESCRIPTION_SIZE];
uint32_t subgroupSize;
} VkPipelineExecutablePropertiesKHR;
typedef struct VkPipelineExecutableInfoKHR {
VkStructureType sType;
const void* pNext;
VkPipeline pipeline;
uint32_t executableIndex;
} VkPipelineExecutableInfoKHR;
typedef union VkPipelineExecutableStatisticValueKHR {
VkBool32 b32;
int64_t i64;
uint64_t u64;
double f64;
} VkPipelineExecutableStatisticValueKHR;
typedef struct VkPipelineExecutableStatisticKHR {
VkStructureType sType;
void* pNext;
char name[VK_MAX_DESCRIPTION_SIZE];
char description[VK_MAX_DESCRIPTION_SIZE];
VkPipelineExecutableStatisticFormatKHR format;
VkPipelineExecutableStatisticValueKHR value;
} VkPipelineExecutableStatisticKHR;
typedef struct VkPipelineExecutableInternalRepresentationKHR {
VkStructureType sType;
void* pNext;
char name[VK_MAX_DESCRIPTION_SIZE];
char description[VK_MAX_DESCRIPTION_SIZE];
VkBool32 isText;
size_t dataSize;
void* pData;
} VkPipelineExecutableInternalRepresentationKHR;
typedef VkResult (VKAPI_PTR *PFN_vkGetPipelineExecutablePropertiesKHR)(VkDevice device, const VkPipelineInfoKHR* pPipelineInfo, uint32_t* pExecutableCount, VkPipelineExecutablePropertiesKHR* pProperties);
typedef VkResult (VKAPI_PTR *PFN_vkGetPipelineExecutableStatisticsKHR)(VkDevice device, const VkPipelineExecutableInfoKHR* pExecutableInfo, uint32_t* pStatisticCount, VkPipelineExecutableStatisticKHR* pStatistics);
typedef VkResult (VKAPI_PTR *PFN_vkGetPipelineExecutableInternalRepresentationsKHR)(VkDevice device, const VkPipelineExecutableInfoKHR* pExecutableInfo, uint32_t* pInternalRepresentationCount, VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkGetPipelineExecutablePropertiesKHR(
VkDevice device,
const VkPipelineInfoKHR* pPipelineInfo,
uint32_t* pExecutableCount,
VkPipelineExecutablePropertiesKHR* pProperties);
VKAPI_ATTR VkResult VKAPI_CALL vkGetPipelineExecutableStatisticsKHR(
VkDevice device,
const VkPipelineExecutableInfoKHR* pExecutableInfo,
uint32_t* pStatisticCount,
VkPipelineExecutableStatisticKHR* pStatistics);
VKAPI_ATTR VkResult VKAPI_CALL vkGetPipelineExecutableInternalRepresentationsKHR(
VkDevice device,
const VkPipelineExecutableInfoKHR* pExecutableInfo,
uint32_t* pInternalRepresentationCount,
VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations);
#endif
#define VK_EXT_debug_report 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkDebugReportCallbackEXT)
#define VK_EXT_DEBUG_REPORT_SPEC_VERSION 9
@@ -8845,22 +8741,6 @@ VKAPI_ATTR void VKAPI_CALL vkCmdWriteBufferMarkerAMD(
#endif
#define VK_AMD_pipeline_compiler_control 1
#define VK_AMD_PIPELINE_COMPILER_CONTROL_SPEC_VERSION 1
#define VK_AMD_PIPELINE_COMPILER_CONTROL_EXTENSION_NAME "VK_AMD_pipeline_compiler_control"
typedef enum VkPipelineCompilerControlFlagBitsAMD {
VK_PIPELINE_COMPILER_CONTROL_FLAG_BITS_MAX_ENUM_AMD = 0x7FFFFFFF
} VkPipelineCompilerControlFlagBitsAMD;
typedef VkFlags VkPipelineCompilerControlFlagsAMD;
typedef struct VkPipelineCompilerControlCreateInfoAMD {
VkStructureType sType;
const void* pNext;
VkPipelineCompilerControlFlagsAMD compilerControlFlags;
} VkPipelineCompilerControlCreateInfoAMD;
#define VK_EXT_calibrated_timestamps 1
#define VK_EXT_CALIBRATED_TIMESTAMPS_SPEC_VERSION 1
#define VK_EXT_CALIBRATED_TIMESTAMPS_EXTENSION_NAME "VK_EXT_calibrated_timestamps"
@@ -9408,15 +9288,8 @@ typedef struct VkPhysicalDeviceScalarBlockLayoutFeaturesEXT {
#define VK_EXT_subgroup_size_control 1
#define VK_EXT_SUBGROUP_SIZE_CONTROL_SPEC_VERSION 2
#define VK_EXT_SUBGROUP_SIZE_CONTROL_SPEC_VERSION 1
#define VK_EXT_SUBGROUP_SIZE_CONTROL_EXTENSION_NAME "VK_EXT_subgroup_size_control"
typedef struct VkPhysicalDeviceSubgroupSizeControlFeaturesEXT {
VkStructureType sType;
void* pNext;
VkBool32 subgroupSizeControl;
VkBool32 computeFullSubgroups;
} VkPhysicalDeviceSubgroupSizeControlFeaturesEXT;
typedef struct VkPhysicalDeviceSubgroupSizeControlPropertiesEXT {
VkStructureType sType;
void* pNext;
@@ -9434,23 +9307,6 @@ typedef struct VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT {
#define VK_AMD_shader_core_properties2 1
#define VK_AMD_SHADER_CORE_PROPERTIES_2_SPEC_VERSION 1
#define VK_AMD_SHADER_CORE_PROPERTIES_2_EXTENSION_NAME "VK_AMD_shader_core_properties2"
typedef enum VkShaderCorePropertiesFlagBitsAMD {
VK_SHADER_CORE_PROPERTIES_FLAG_BITS_MAX_ENUM_AMD = 0x7FFFFFFF
} VkShaderCorePropertiesFlagBitsAMD;
typedef VkFlags VkShaderCorePropertiesFlagsAMD;
typedef struct VkPhysicalDeviceShaderCoreProperties2AMD {
VkStructureType sType;
void* pNext;
VkShaderCorePropertiesFlagsAMD shaderCoreFeatures;
uint32_t activeComputeUnitCount;
} VkPhysicalDeviceShaderCoreProperties2AMD;
#define VK_EXT_memory_budget 1
#define VK_EXT_MEMORY_BUDGET_SPEC_VERSION 1
#define VK_EXT_MEMORY_BUDGET_EXTENSION_NAME "VK_EXT_memory_budget"

View File

@@ -26,7 +26,7 @@ project(
).stdout(),
license : 'MIT',
meson_version : '>= 0.46',
default_options : ['buildtype=debugoptimized', 'b_ndebug=if-release', 'c_std=c99', 'cpp_std=c++14']
default_options : ['buildtype=debugoptimized', 'b_ndebug=if-release', 'c_std=c99', 'cpp_std=c++11']
)
cc = meson.get_compiler('c')
@@ -42,7 +42,7 @@ pre_args = [
'-D__STDC_FORMAT_MACROS',
'-D__STDC_LIMIT_MACROS',
'-DPACKAGE_VERSION="@0@"'.format(meson.project_version()),
'-DPACKAGE_BUGREPORT="https://gitlab.freedesktop.org/mesa/mesa/issues"',
'-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa"',
]
with_vulkan_icd_dir = get_option('vulkan-icd-dir')
@@ -61,8 +61,6 @@ if with_tools.contains('all')
'freedreno',
'glsl',
'intel',
'intel-ui',
'lima',
'nir',
'nouveau',
'xvmc',
@@ -93,7 +91,7 @@ with_shared_glapi = get_option('shared-glapi')
# shared-glapi is required if at least two OpenGL APIs are being built
if not with_shared_glapi
if ((with_gles1 == 'true' and with_gles2 == 'true') or
if ((with_gles1 == 'true' and with_gles2 == 'true') or
(with_gles1 == 'true' and with_opengl) or
(with_gles2 == 'true' and with_opengl))
error('shared-glapi required for building two or more of OpenGL, OpenGL ES 1.x, OpenGL ES 2.x')
@@ -117,7 +115,7 @@ with_any_opengl = with_opengl or with_gles1 or with_gles2
# Only build shared_glapi if at least one OpenGL API is enabled
with_shared_glapi = get_option('shared-glapi') and with_any_opengl
system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'gnu/kfreebsd', 'dragonfly', 'linux', 'sunos'].contains(host_machine.system())
system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'gnu/kfreebsd', 'dragonfly', 'linux'].contains(host_machine.system())
dri_drivers = get_option('dri-drivers')
if dri_drivers.contains('auto')
@@ -160,7 +158,7 @@ if gallium_drivers.contains('auto')
elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
gallium_drivers = [
'kmsro', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau',
'tegra', 'virgl', 'lima', 'panfrost', 'swrast'
'tegra', 'virgl', 'lima', 'swrast'
]
else
error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
@@ -377,15 +375,11 @@ if with_egl and not (with_platform_drm or with_platform_surfaceless or with_plat
endif
endif
# Android uses emutls for versions <= P/28. For USE_ELF_TLS we need ELF TLS.
if not with_platform_android or get_option('platform-sdk-version') >= 29
pre_args += '-DUSE_ELF_TLS'
endif
pre_args += '-DGLX_USE_TLS'
if with_glx != 'disabled'
if not (with_platform_x11 and with_any_opengl)
error('Cannot build GLX support without X11 platform support and at least one OpenGL API')
elif with_glx == 'gallium-xlib'
elif with_glx == 'gallium-xlib'
if not with_gallium
error('Gallium-xlib based GLX requires at least one gallium driver')
elif not with_gallium_softpipe
@@ -393,7 +387,7 @@ if with_glx != 'disabled'
elif with_dri
error('gallium-xlib conflicts with any dri driver')
endif
elif with_glx == 'xlib'
elif with_glx == 'xlib'
if with_dri
error('xlib conflicts with any dri driver')
endif
@@ -502,12 +496,10 @@ elif not (with_gallium_r600 or with_gallium_nouveau)
endif
endif
dep_xvmc = null_dep
dep_xv = null_dep
with_gallium_xvmc = false
if _xvmc != 'false'
dep_xvmc = dependency('xvmc', version : '>= 1.0.6', required : _xvmc == 'true')
dep_xv = dependency('xv', required : _xvmc == 'true')
with_gallium_xvmc = dep_xvmc.found() and dep_xv.found()
with_gallium_xvmc = dep_xvmc.found()
endif
xvmc_drivers_path = get_option('xvmc-libs-path')
@@ -781,11 +773,6 @@ if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
error('When using GCC, version 4.4.6 or later is required.')
endif
# Support systems without ETIME (e.g. FreeBSD)
if cc.get_define('ETIME', prefix : '#include <errno.h>') == ''
pre_args += '-DETIME=ETIMEDOUT'
endif
# Define DEBUG for debug builds only (debugoptimized is not included on this one)
if get_option('buildtype') == 'debug'
pre_args += '-DDEBUG'
@@ -858,8 +845,6 @@ endif
# TODO: this is very incomplete
if ['linux', 'cygwin', 'gnu', 'gnu/kfreebsd'].contains(host_machine.system())
pre_args += '-D_GNU_SOURCE'
elif host_machine.system() == 'sunos'
pre_args += '-D__EXTENSIONS__'
endif
# Check for generic C arguments
@@ -869,8 +854,6 @@ foreach a : ['-Werror=implicit-function-declaration',
'-Werror=incompatible-pointer-types',
'-Werror=format',
'-Wformat-security',
'-Wno-missing-field-initializers',
'-Wno-format-truncation',
'-fno-math-errno',
'-fno-trapping-math', '-Qunused-arguments']
if cc.has_argument(a)
@@ -878,6 +861,12 @@ foreach a : ['-Werror=implicit-function-declaration',
endif
endforeach
foreach a : ['missing-field-initializers', 'format-truncation']
if cc.has_argument('-W' + a)
c_args += '-Wno-' + a
endif
endforeach
c_vis_args = []
if cc.has_argument('-fvisibility=hidden')
c_vis_args += '-fvisibility=hidden'
@@ -888,9 +877,6 @@ cpp_args = []
foreach a : ['-Werror=return-type',
'-Werror=format',
'-Wformat-security',
'-Wno-non-virtual-dtor',
'-Wno-missing-field-initializers',
'-Wno-format-truncation',
'-fno-math-errno', '-fno-trapping-math',
'-Qunused-arguments']
if cpp.has_argument(a)
@@ -898,11 +884,19 @@ foreach a : ['-Werror=return-type',
endif
endforeach
# For some reason, the test for -Wno-foo always succeeds with gcc, even if the
# option is not supported. Hence, check for -Wfoo instead.
foreach a : ['non-virtual-dtor', 'missing-field-initializers', 'format-truncation']
if cpp.has_argument('-W' + a)
cpp_args += '-Wno-' + a
endif
endforeach
no_override_init_args = []
foreach a : ['-Wno-override-init',
'-Wno-initializer-overrides']
if cc.has_argument(a)
no_override_init_args += a
foreach a : ['override-init', 'initializer-overrides']
if cc.has_argument('-W' + a)
no_override_init_args += '-Wno-' + a
endif
endforeach
@@ -1030,13 +1024,13 @@ elif cc.has_header_symbol('sys/mkdev.h', 'major')
pre_args += '-DMAJOR_IN_MKDEV'
endif
foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'execinfo.h', 'sys/shm.h', 'cet.h']
foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'execinfo.h', 'sys/shm.h']
if cc.compiles('#include <@0@>'.format(h), name : '@0@'.format(h))
pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
endif
endforeach
foreach f : ['strtof', 'mkostemp', 'posix_memalign', 'timespec_get', 'memfd_create', 'random_r', 'flock']
foreach f : ['strtof', 'mkostemp', 'posix_memalign', 'timespec_get', 'memfd_create', 'random_r']
if cc.has_function(f)
pre_args += '-DHAVE_@0@'.format(f.to_upper())
endif
@@ -1139,12 +1133,6 @@ if dep_thread.found() and host_machine.system() != 'windows'
args : '-D_GNU_SOURCE')
pre_args += '-DHAVE_PTHREAD_SETAFFINITY'
endif
if cc.has_function(
'pthread_setaffinity_np',
dependencies : dep_thread,
prefix : '#include <pthread_np.h>')
pre_args += '-DPTHREAD_SETAFFINITY_IN_NP_HEADER'
endif
endif
dep_expat = dependency('expat')
# this only exists on linux so either this is linux and it will be found, or
@@ -1302,12 +1290,8 @@ else
endif
dep_glvnd = null_dep
glvnd_has_headers_and_pc_files = false
if with_glvnd
dep_glvnd = dependency('libglvnd', version : '>= 0.2.0')
# GLVND before 1.2 was missing its pkg-config and header files, forcing every
# vendor to provide them and the distro maintainers to resolve the conflict.
glvnd_has_headers_and_pc_files = dep_glvnd.version().version_compare('>= 1.2.0')
pre_args += '-DUSE_LIBGLVND=1'
endif
@@ -1341,6 +1325,9 @@ else
endif
if with_osmesa != 'none'
if with_osmesa == 'classic' and not with_dri_swrast
error('OSMesa classic requires dri (classic) swrast.')
endif
if with_osmesa == 'gallium' and not with_gallium_softpipe
error('OSMesa gallium requires gallium softpipe or llvmpipe.')
endif
@@ -1418,9 +1405,6 @@ if with_platform_x11
with_gallium_omx != 'disabled'))
dep_xcb = dependency('xcb')
dep_x11_xcb = dependency('x11-xcb')
if with_dri_platform == 'drm' and not dep_libdrm.found()
error('libdrm required for gallium video statetrackers when using x11')
endif
endif
if with_any_vk or with_egl or (with_glx == 'dri' and with_dri_platform == 'drm')
dep_xcb_dri2 = dependency('xcb-dri2', version : '>= 1.8')
@@ -1441,7 +1425,7 @@ if with_platform_x11
if with_glx == 'dri' or with_glx == 'gallium-xlib'
dep_glproto = dependency('glproto', version : '>= 1.4.14')
endif
if with_glx == 'dri'
if with_glx == 'dri'
if with_dri_platform == 'drm'
dep_dri2proto = dependency('dri2proto', version : '>= 2.8')
dep_xxf86vm = dependency('xxf86vm')

View File

@@ -128,9 +128,9 @@ def generate(env):
if not path:
path = []
if SCons.Util.is_String(path):
path = str.split(path, os.pathsep)
path = string.split(path, os.pathsep)
env['ENV']['PATH'] = str.join(os.pathsep, [dir] + path)
env['ENV']['PATH'] = string.join([dir] + path, os.pathsep)
# Most of mingw is the same as gcc and friends...
gnu_tools = ['gcc', 'g++', 'gnulink', 'ar', 'gas']

View File

@@ -262,12 +262,8 @@ def parse_source_list(env, filename, names=None):
sym_table = parser.parse(src.abspath)
if names:
if sys.version_info[0] >= 3:
if isinstance(names, str):
names = [names]
else:
if isinstance(names, basestring):
names = [names]
if isinstance(names, basestring):
names = [names]
symbols = names
else:

View File

@@ -132,7 +132,7 @@ def check_cc(env, cc, expr, cpp_opt = '-E'):
sys.stdout.write('Checking for %s ... ' % cc)
source = tempfile.NamedTemporaryFile(suffix='.c', delete=False)
source.write(('#if !(%s)\n#error\n#endif\n' % expr).encode())
source.write('#if !(%s)\n#error\n#endif\n' % expr)
source.close()
# sys.stderr.write('%r %s %s\n' % (env['CC'], cpp_opt, source.name));
@@ -237,9 +237,6 @@ def generate(env):
hosthost_platform = host_platform.system().lower()
if hosthost_platform.startswith('cygwin'):
hosthost_platform = 'cygwin'
# Avoid spurious crosscompilation in MSYS2 environment.
if hosthost_platform.startswith('mingw'):
hosthost_platform = 'windows'
host_machine = os.environ.get('PROCESSOR_ARCHITEW6432', os.environ.get('PROCESSOR_ARCHITECTURE', host_platform.machine()))
host_machine = {
'x86': 'x86',
@@ -406,8 +403,10 @@ def generate(env):
]
if env['build'] in ('debug', 'checked'):
cppdefines += ['_DEBUG']
if platform == 'windows':
cppdefines += ['PIPE_SUBSYSTEM_WINDOWS_USER']
if env['embedded']:
cppdefines += ['EMBEDDED_DEVICE']
cppdefines += ['PIPE_SUBSYSTEM_EMBEDDED']
env.Append(CPPDEFINES = cppdefines)
# C compiler options

View File

@@ -30,7 +30,6 @@ Tool-specific initialization for LLVM
import os
import os.path
import re
import platform as host_platform
import sys
import distutils.version
@@ -101,36 +100,8 @@ def generate(env):
env.Prepend(CPPPATH = [os.path.join(llvm_dir, 'include')])
env.Prepend(LIBPATH = [os.path.join(llvm_dir, 'lib')])
# LLVM 5.0 and newer requires MinGW w/ pthreads due to use of std::thread and friends.
if llvm_version >= distutils.version.LooseVersion('5.0') and env['crosscompile']:
assert env['gcc']
env.AppendUnique(CXXFLAGS = ['-posix'])
# LIBS should match the output of `llvm-config --libs engine mcjit bitwriter x86asmprinter irreader` for LLVM<=7.0
# and `llvm-config --libs engine irreader` for LLVM>=8.0
# LLVMAggressiveInstCombine library part of engine component can be safely omitted as it's not used.
if llvm_version >= distutils.version.LooseVersion('9.0'):
env.Prepend(LIBS = [
'LLVMX86Disassembler', 'LLVMX86AsmParser',
'LLVMX86CodeGen', 'LLVMSelectionDAG', 'LLVMAsmPrinter',
'LLVMDebugInfoCodeView', 'LLVMCodeGen',
'LLVMScalarOpts', 'LLVMInstCombine',
'LLVMTransformUtils',
'LLVMBitWriter', 'LLVMX86Desc',
'LLVMMCDisassembler', 'LLVMX86Info',
'LLVMX86Utils',
'LLVMMCJIT', 'LLVMExecutionEngine', 'LLVMTarget',
'LLVMAnalysis', 'LLVMProfileData',
'LLVMRuntimeDyld', 'LLVMObject', 'LLVMMCParser',
'LLVMBitReader', 'LLVMMC', 'LLVMCore',
'LLVMSupport',
'LLVMIRReader', 'LLVMAsmParser',
'LLVMDemangle', 'LLVMGlobalISel', 'LLVMDebugInfoMSF',
'LLVMBinaryFormat',
'LLVMRemarks', 'LLVMBitstreamReader', 'LLVMDebugInfoDWARF',
])
elif llvm_version >= distutils.version.LooseVersion('5.0'):
# LIBS should match the output of `llvm-config --libs engine mcjit bitwriter x86asmprinter irreader`
if llvm_version >= distutils.version.LooseVersion('5.0'):
env.Prepend(LIBS = [
'LLVMX86Disassembler', 'LLVMX86AsmParser',
'LLVMX86CodeGen', 'LLVMSelectionDAG', 'LLVMAsmPrinter',
@@ -149,6 +120,10 @@ def generate(env):
'LLVMDemangle', 'LLVMGlobalISel', 'LLVMDebugInfoMSF',
'LLVMBinaryFormat',
])
if env['platform'] == 'windows' and env['crosscompile']:
# LLVM 5.0 requires MinGW w/ pthreads due to use of std::thread and friends.
assert env['gcc']
env.AppendUnique(CXXFLAGS = ['-posix'])
elif llvm_version >= distutils.version.LooseVersion('4.0'):
env.Prepend(LIBS = [
'LLVMX86Disassembler', 'LLVMX86AsmParser',
@@ -242,12 +217,6 @@ def generate(env):
'uuid',
])
# Mingw-w64 zlib is required when building with LLVM support in MSYS2 environment
if host_platform.system().lower().startswith('mingw'):
env.Append(LIBS = [
'z',
])
if env['msvc']:
# Some of the LLVM C headers use the inline keyword without
# defining it.
@@ -300,7 +269,7 @@ def generate(env):
env.ParseConfig('%s --ldflags' % llvm_config)
if llvm_version >= distutils.version.LooseVersion('3.5'):
env.ParseConfig('%s --system-libs' % llvm_config)
env.Append(CXXFLAGS = ['-std=c++14'])
env.Append(CXXFLAGS = ['-std=c++11'])
except OSError:
print('scons: llvm-config version %s failed' % llvm_version)
return

View File

@@ -77,22 +77,24 @@
#define AMDGPU_ICELAND_RANGE 0x01, 0x14
#define AMDGPU_TONGA_RANGE 0x14, 0x28
#define AMDGPU_FIJI_RANGE 0x3C, 0x50
#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
#define AMDGPU_CARRIZO_RANGE 0x01, 0x21
#define AMDGPU_BRISTOL_RANGE 0x10, 0x21
#define AMDGPU_STONEY_RANGE 0x61, 0xFF
#define AMDGPU_VEGA10_RANGE 0x01, 0x14
#define AMDGPU_VEGA12_RANGE 0x14, 0x28
#define AMDGPU_VEGA20_RANGE 0x28, 0x32
#define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF
#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0x91
#define AMDGPU_RENOIR_RANGE 0x91, 0xFF
#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
#define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
@@ -128,6 +130,7 @@
#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
@@ -135,11 +138,11 @@
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR)
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12)

View File

@@ -1312,11 +1312,6 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
m_settings.applyAliasFix = 1;
}
if (ASICREV_IS_RENOIR(uChipRevision))
{
m_settings.isRaven = 1;
}
m_settings.isDcn1 = m_settings.isRaven;
m_settings.metaBaseAlignFix = 1;

View File

@@ -26,7 +26,6 @@
#include "ac_gpu_info.h"
#include "sid.h"
#include "util/macros.h"
#include "util/u_math.h"
#include <stdio.h>
@@ -92,14 +91,6 @@ static bool has_syncobj(int fd)
return value ? true : false;
}
static uint64_t fix_vram_size(uint64_t size)
{
/* The VRAM size is underreported, so we need to fix it, because
* it's used to compute the number of memory modules for harvesting.
*/
return align64(size, 256*1024*1024);
}
bool ac_query_gpu_info(int fd, void *dev_p,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
@@ -273,7 +264,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
/* Note: usable_heap_size values can be random and can't be relied on. */
info->gart_size = meminfo.gtt.total_heap_size;
info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
info->vram_size = meminfo.vram.total_heap_size;
info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
} else {
/* This is a deprecated interface, which reports usable sizes
@@ -304,7 +295,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
}
info->gart_size = gtt.heap_size;
info->vram_size = fix_vram_size(vram.heap_size);
info->vram_size = vram.heap_size;
info->vram_vis_size = vram_vis.heap_size;
}
@@ -427,9 +418,6 @@ bool ac_query_gpu_info(int fd, void *dev_p,
}
if (info->chip_class >= GFX10) {
info->tcc_cache_line_size = 128;
/* This is a hack, but it's all we can do without a kernel upgrade. */
info->tcc_harvested =
(info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
} else {
info->tcc_cache_line_size = 64;
}
@@ -461,12 +449,6 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->num_good_cu_per_sh = info->num_good_compute_units /
(info->max_se * info->max_sh_per_se);
/* Round down to the nearest multiple of 2, because the hw can't
* disable CUs. It can only disable whole WGPs (dual-CUs).
*/
if (info->chip_class >= GFX10)
info->num_good_cu_per_sh -= info->num_good_cu_per_sh % 2;
memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
sizeof(amdinfo->gb_tile_mode));
info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
@@ -478,7 +460,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->gart_page_size = alignment_info.size_remote;
if (info->chip_class == GFX6)
info->gfx_ib_pad_with_type2 = true;
info->gfx_ib_pad_with_type2 = TRUE;
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
@@ -495,8 +477,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
if (info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
info->family == CHIP_RAVEN2 ||
info->family == CHIP_RENOIR)) {
info->family == CHIP_RAVEN2)) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else
@@ -551,7 +532,6 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
printf(" tcc_harvested = %u\n", info->tcc_harvested);
printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);

View File

@@ -58,7 +58,6 @@ struct radeon_info {
uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
bool tcc_harvested;
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
@@ -174,7 +173,7 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info,
unsigned max_waves_per_sh,
unsigned threadgroups_per_cu);
static inline unsigned ac_get_max_wave64_per_simd(enum radeon_family family)
static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
{
switch (family) {
@@ -189,26 +188,10 @@ static inline unsigned ac_get_max_wave64_per_simd(enum radeon_family family)
}
}
static inline unsigned ac_get_num_physical_vgprs(enum chip_class chip_class,
unsigned wave_size)
{
/* The number is per SIMD. */
if (chip_class >= GFX10)
return wave_size == 32 ? 1024 : 512;
else
return 256;
}
static inline uint32_t
ac_get_num_physical_sgprs(const struct radeon_info *info)
ac_get_num_physical_sgprs(enum chip_class chip_class)
{
/* The number is per SIMD. There is enough SGPRs for the maximum number
* of Wave32, which is double the number for Wave64.
*/
if (info->chip_class >= GFX10)
return 128 * ac_get_max_wave64_per_simd(info->family) * 2;
return info->chip_class >= GFX8 ? 800 : 512;
return chip_class >= GFX8 ? 800 : 512;
}
#ifdef __cplusplus

View File

@@ -60,8 +60,7 @@ void
ac_llvm_context_init(struct ac_llvm_context *ctx,
struct ac_llvm_compiler *compiler,
enum chip_class chip_class, enum radeon_family family,
enum ac_float_mode float_mode, unsigned wave_size,
unsigned ballot_mask_bits)
enum ac_float_mode float_mode, unsigned wave_size)
{
LLVMValueRef args[1];
@@ -70,7 +69,6 @@ ac_llvm_context_init(struct ac_llvm_context *ctx,
ctx->chip_class = chip_class;
ctx->family = family;
ctx->wave_size = wave_size;
ctx->ballot_mask_bits = ballot_mask_bits;
ctx->module = ac_create_module(wave_size == 32 ? compiler->tm_wave32
: compiler->tm,
ctx->context);
@@ -95,7 +93,6 @@ ac_llvm_context_init(struct ac_llvm_context *ctx,
ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
ctx->iN_wavemask = LLVMIntTypeInContext(ctx->context, ctx->wave_size);
ctx->iN_ballotmask = LLVMIntTypeInContext(ctx->context, ballot_mask_bits);
ctx->i8_0 = LLVMConstInt(ctx->i8, 0, false);
ctx->i8_1 = LLVMConstInt(ctx->i8, 1, false);
@@ -629,22 +626,6 @@ ac_build_expand(struct ac_llvm_context *ctx,
return ac_build_gather_values(ctx, chan, dst_channels);
}
/* Extract components [start, start + channels) from a vector.
*/
LLVMValueRef
ac_extract_components(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned start,
unsigned channels)
{
LLVMValueRef chan[channels];
for (unsigned i = 0; i < channels; i++)
chan[i] = ac_llvm_extract_elem(ctx, value, i + start);
return ac_build_gather_values(ctx, chan, channels);
}
/* Expand a scalar or vector to <4 x type> by filling the remaining channels
* with undef. Extract at most num_channels components from the input.
*/
@@ -2599,8 +2580,6 @@ static const char *get_atomic_name(enum ac_atomic_op op)
case ac_atomic_and: return "and";
case ac_atomic_or: return "or";
case ac_atomic_xor: return "xor";
case ac_atomic_inc_wrap: return "inc";
case ac_atomic_dec_wrap: return "dec";
}
unreachable("bad atomic op");
}
@@ -3861,8 +3840,6 @@ ac_build_readlane(struct ac_llvm_context *ctx, LLVMValueRef src, LLVMValueRef la
LLVMConstInt(ctx->i32, i, 0), "");
}
}
if (LLVMGetTypeKind(src_type) == LLVMPointerTypeKind)
return LLVMBuildIntToPtr(ctx->builder, ret, src_type, "");
return LLVMBuildBitCast(ctx->builder, ret, src_type, "");
}
@@ -4221,9 +4198,10 @@ ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMValueRef src, LLVMValu
if (ctx->chip_class >= GFX10) {
result = inclusive ? src : identity;
} else {
if (!inclusive)
src = ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false);
result = src;
if (inclusive)
result = src;
else
result = ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false);
}
if (maxprefix <= 1)
return result;

View File

@@ -81,7 +81,6 @@ struct ac_llvm_context {
LLVMTypeRef v4f32;
LLVMTypeRef v8i32;
LLVMTypeRef iN_wavemask;
LLVMTypeRef iN_ballotmask;
LLVMValueRef i8_0;
LLVMValueRef i8_1;
@@ -115,9 +114,7 @@ struct ac_llvm_context {
enum chip_class chip_class;
enum radeon_family family;
unsigned wave_size;
unsigned ballot_mask_bits;
LLVMValueRef lds;
};
@@ -126,8 +123,7 @@ void
ac_llvm_context_init(struct ac_llvm_context *ctx,
struct ac_llvm_compiler *compiler,
enum chip_class chip_class, enum radeon_family family,
enum ac_float_mode float_mode, unsigned wave_size,
unsigned ballot_mask_bits);
enum ac_float_mode float_mode, unsigned wave_size);
void
ac_llvm_context_dispose(struct ac_llvm_context *ctx);
@@ -194,13 +190,6 @@ LLVMValueRef
ac_build_gather_values(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count);
LLVMValueRef
ac_extract_components(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned start,
unsigned channels);
LLVMValueRef ac_build_expand_to_vec4(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned num_channels);
@@ -527,8 +516,6 @@ enum ac_atomic_op {
ac_atomic_and,
ac_atomic_or,
ac_atomic_xor,
ac_atomic_inc_wrap,
ac_atomic_dec_wrap,
};
enum ac_image_dim {

View File

@@ -132,7 +132,6 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_VEGA20:
return "gfx906";
case CHIP_RAVEN2:
case CHIP_RENOIR:
return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
case CHIP_ARCTURUS:
return "gfx908";

View File

@@ -153,6 +153,12 @@ static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
return (LLVMBasicBlockRef)entry->data;
}
static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
LLVMValueRef src0)
{
return ac_build_imax(ctx, src0, LLVMBuildNeg(ctx->builder, src0, ""));
}
static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
nir_alu_src src,
unsigned num_components)
@@ -187,8 +193,38 @@ static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
swizzle, "");
}
}
assert(!src.negate);
assert(!src.abs);
LLVMTypeRef type = LLVMTypeOf(value);
if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
type = LLVMGetElementType(type);
if (src.abs) {
if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind) {
value = emit_iabs(&ctx->ac, value);
} else {
char name[128];
unsigned fsize = type == ctx->ac.f16 ? 16 :
type == ctx->ac.f32 ? 32 : 64;
if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
snprintf(name, sizeof(name), "llvm.fabs.v%uf%u",
LLVMGetVectorSize(LLVMTypeOf(value)), fsize);
} else {
snprintf(name, sizeof(name), "llvm.fabs.f%u", fsize);
}
value = ac_build_intrinsic(&ctx->ac, name, LLVMTypeOf(value),
&value, 1, AC_FUNC_ATTR_READNONE);
}
}
if (src.negate) {
if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
value = LLVMBuildNeg(ctx->ac.builder, value, "");
else
value = LLVMBuildFNeg(ctx->ac.builder, value, "");
}
return value;
}
@@ -278,12 +314,6 @@ static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
ac_to_integer_or_pointer(ctx, src2), "");
}
static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
LLVMValueRef src0)
{
return ac_build_imax(ctx, src0, LLVMBuildNeg(ctx->builder, src0, ""));
}
static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
const char *intrin,
LLVMValueRef src0, LLVMValueRef src1)
@@ -1547,9 +1577,6 @@ static unsigned get_cache_policy(struct ac_nir_context *ctx,
cache_policy |= ac_glc;
}
if (access & ACCESS_STREAM_CACHE_POLICY)
cache_policy |= ac_slc;
return cache_policy;
}
@@ -1641,71 +1668,13 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
}
}
static LLVMValueRef emit_ssbo_comp_swap_64(struct ac_nir_context *ctx,
LLVMValueRef descriptor,
LLVMValueRef offset,
LLVMValueRef compare,
LLVMValueRef exchange)
{
LLVMBasicBlockRef start_block = NULL, then_block = NULL;
if (ctx->abi->robust_buffer_access) {
LLVMValueRef size = ac_llvm_extract_elem(&ctx->ac, descriptor, 2);
LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, offset, size, "");
start_block = LLVMGetInsertBlock(ctx->ac.builder);
ac_build_ifcc(&ctx->ac, cond, -1);
then_block = LLVMGetInsertBlock(ctx->ac.builder);
}
LLVMValueRef ptr_parts[2] = {
ac_llvm_extract_elem(&ctx->ac, descriptor, 0),
LLVMBuildAnd(ctx->ac.builder,
ac_llvm_extract_elem(&ctx->ac, descriptor, 1),
LLVMConstInt(ctx->ac.i32, 65535, 0), "")
};
ptr_parts[1] = LLVMBuildTrunc(ctx->ac.builder, ptr_parts[1], ctx->ac.i16, "");
ptr_parts[1] = LLVMBuildSExt(ctx->ac.builder, ptr_parts[1], ctx->ac.i32, "");
offset = LLVMBuildZExt(ctx->ac.builder, offset, ctx->ac.i64, "");
LLVMValueRef ptr = ac_build_gather_values(&ctx->ac, ptr_parts, 2);
ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->ac.i64, "");
ptr = LLVMBuildAdd(ctx->ac.builder, ptr, offset, "");
ptr = LLVMBuildIntToPtr(ctx->ac.builder, ptr, LLVMPointerType(ctx->ac.i64, AC_ADDR_SPACE_GLOBAL), "");
LLVMValueRef result = ac_build_atomic_cmp_xchg(&ctx->ac, ptr, compare, exchange, "singlethread-one-as");
result = LLVMBuildExtractValue(ctx->ac.builder, result, 0, "");
if (ctx->abi->robust_buffer_access) {
ac_build_endif(&ctx->ac, -1);
LLVMBasicBlockRef incoming_blocks[2] = {
start_block,
then_block,
};
LLVMValueRef incoming_values[2] = {
LLVMConstInt(ctx->ac.i64, 0, 0),
result,
};
LLVMValueRef ret = LLVMBuildPhi(ctx->ac.builder, ctx->ac.i64, "");
LLVMAddIncoming(ret, incoming_values, incoming_blocks, 2);
return ret;
} else {
return result;
}
}
static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMTypeRef return_type = LLVMTypeOf(get_src(ctx, instr->src[2]));
const char *op;
char name[64], type[8];
LLVMValueRef params[6], descriptor;
LLVMValueRef params[6];
int arg_count = 0;
switch (instr->intrinsic) {
@@ -1743,22 +1712,13 @@ static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
abort();
}
descriptor = ctx->abi->load_ssbo(ctx->abi,
get_src(ctx, instr->src[0]),
true);
if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap &&
return_type == ctx->ac.i64) {
return emit_ssbo_comp_swap_64(ctx, descriptor,
get_src(ctx, instr->src[1]),
get_src(ctx, instr->src[2]),
get_src(ctx, instr->src[3]));
}
if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
}
params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
params[arg_count++] = descriptor;
params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
get_src(ctx, instr->src[0]),
true);
if (HAVE_LLVM >= 0x900) {
/* XXX: The new raw/struct atomic intrinsics are buggy with
@@ -2439,7 +2399,7 @@ static void get_image_coords(struct ac_nir_context *ctx,
fmask_load_address[2],
sample_index,
get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr),
AC_DESC_FMASK, &instr->instr, true, false));
AC_DESC_FMASK, &instr->instr, false, false));
}
if (count == 1 && !gfx9_1d) {
if (instr->src[1].ssa->num_components)
@@ -2678,27 +2638,6 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
atomic_name = "cmpswap";
atomic_subop = 0; /* not used */
break;
case nir_intrinsic_bindless_image_atomic_inc_wrap:
case nir_intrinsic_image_deref_atomic_inc_wrap: {
atomic_name = "inc";
atomic_subop = ac_atomic_inc_wrap;
/* ATOMIC_INC instruction does:
* value = (value + 1) % (data + 1)
* but we want:
* value = (value + 1) % data
* So replace 'data' by 'data - 1'.
*/
ctx->ssa_defs[instr->src[3].ssa->index] =
LLVMBuildSub(ctx->ac.builder,
ctx->ssa_defs[instr->src[3].ssa->index],
ctx->ac.i32_1, "");
break;
}
case nir_intrinsic_bindless_image_atomic_dec_wrap:
case nir_intrinsic_image_deref_atomic_dec_wrap:
atomic_name = "dec";
atomic_subop = ac_atomic_dec_wrap;
break;
default:
abort();
}
@@ -3102,9 +3041,6 @@ static LLVMValueRef barycentric_at_sample(struct ac_nir_context *ctx,
unsigned mode,
LLVMValueRef sample_id)
{
if (ctx->abi->interp_at_sample_force_center)
return barycentric_center(ctx, mode);
LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
/* fetch sample ID */
@@ -3203,8 +3139,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
switch (instr->intrinsic) {
case nir_intrinsic_ballot:
result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
if (ctx->ac.ballot_mask_bits > ctx->ac.wave_size)
result = LLVMBuildZExt(ctx->ac.builder, result, ctx->ac.iN_ballotmask, "");
break;
case nir_intrinsic_read_invocation:
result = ac_build_readlane(&ctx->ac, get_src(ctx, instr->src[0]),
@@ -3313,10 +3247,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_load_color1:
result = ctx->abi->color1;
break;
case nir_intrinsic_load_user_data_amd:
assert(LLVMTypeOf(ctx->abi->user_data) == ctx->ac.v4i32);
result = ctx->abi->user_data;
break;
case nir_intrinsic_load_instance_id:
result = ctx->abi->instance_id;
break;
@@ -3412,8 +3342,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_bindless_image_atomic_xor:
case nir_intrinsic_bindless_image_atomic_exchange:
case nir_intrinsic_bindless_image_atomic_comp_swap:
case nir_intrinsic_bindless_image_atomic_inc_wrap:
case nir_intrinsic_bindless_image_atomic_dec_wrap:
result = visit_image_atomic(ctx, instr, true);
break;
case nir_intrinsic_image_deref_atomic_add:
@@ -3424,8 +3352,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_image_deref_atomic_xor:
case nir_intrinsic_image_deref_atomic_exchange:
case nir_intrinsic_image_deref_atomic_comp_swap:
case nir_intrinsic_image_deref_atomic_inc_wrap:
case nir_intrinsic_image_deref_atomic_dec_wrap:
result = visit_image_atomic(ctx, instr, false);
break;
case nir_intrinsic_bindless_image_size:
@@ -3537,16 +3463,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->load_tess_coord(ctx->abi);
break;
case nir_intrinsic_load_tess_level_outer:
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER, false);
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
break;
case nir_intrinsic_load_tess_level_inner:
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER, false);
break;
case nir_intrinsic_load_tess_level_outer_default:
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER, true);
break;
case nir_intrinsic_load_tess_level_inner_default:
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER, true);
result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
break;
case nir_intrinsic_load_patch_vertices_in:
result = ctx->abi->load_patch_vertices_in(ctx->abi);

View File

@@ -65,7 +65,6 @@ struct ac_shader_abi {
LLVMValueRef prim_mask;
LLVMValueRef color0;
LLVMValueRef color1;
LLVMValueRef user_data;
/* CS */
LLVMValueRef local_invocation_ids;
LLVMValueRef num_work_groups;
@@ -139,8 +138,7 @@ struct ac_shader_abi {
LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
unsigned varying_id,
bool load_default_state);
unsigned varying_id);
LLVMValueRef (*load_ubo)(struct ac_shader_abi *abi, LLVMValueRef index);
@@ -205,15 +203,11 @@ struct ac_shader_abi {
/* Whether to clamp the shadow reference value to [0,1]on GFX8. Radeonsi currently
* uses it due to promoting D16 to D32, but radv needs it off. */
bool clamp_shadow_reference;
bool interp_at_sample_force_center;
/* Whether to workaround GFX9 ignoring the stride for the buffer size if IDXEN=0
* and LLVM optimizes an indexed load with constant index to IDXEN=0. */
bool gfx9_stride_size_workaround;
bool gfx9_stride_size_workaround_for_atomic;
/* Whether bounds checks are required */
bool robust_buffer_access;
};
#endif /* AC_SHADER_ABI_H */

View File

@@ -1265,7 +1265,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
return ret;
surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
if (addrout.addr > UINT16_MAX)
if (addrout.addr > USHRT_MAX)
surf->u.gfx9.dcc_retile_use_uint16 = false;
/* Compute dst DCC address */
@@ -1278,7 +1278,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
return ret;
surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
if (addrout.addr > UINT16_MAX)
if (addrout.addr > USHRT_MAX)
surf->u.gfx9.dcc_retile_use_uint16 = false;
assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);

View File

@@ -97,7 +97,6 @@ enum radeon_family {
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_RAVEN2,
CHIP_RENOIR,
CHIP_ARCTURUS,
CHIP_NAVI10,
CHIP_NAVI12,

View File

@@ -181,7 +181,6 @@
/* fix CP DMA before uncommenting: */
/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */
#define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */
#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
#define PKT3_REWIND 0x59 /* VI+ [any ring] or CIK [compute ring only] */

View File

@@ -153,11 +153,12 @@ libvulkan_radeon = shared_library(
],
link_with : [
libamd_common, libamdgpu_addrlib, libvulkan_wsi,
libmesa_util, libxmlconfig
],
dependencies : [
dep_llvm, dep_libdrm_amdgpu, dep_thread, dep_elf, dep_dl, dep_m,
dep_valgrind, radv_deps,
idep_mesautil, idep_nir, idep_vulkan_util, idep_amdgfxregs_h, idep_xmlconfig,
idep_nir, idep_vulkan_util, idep_amdgfxregs_h,
],
c_args : [c_vis_args, no_override_init_args, radv_flags],
cpp_args : [cpp_vis_args, radv_flags],

View File

@@ -54,9 +54,7 @@ enum {
static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
bool src_render_loop,
VkImageLayout dst_layout,
bool dst_render_loop,
uint32_t src_family,
uint32_t dst_family,
const VkImageSubresourceRange *range,
@@ -992,15 +990,13 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
return;
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
unsigned sx_ps_downconvert = 0;
unsigned sx_blend_opt_epsilon = 0;
unsigned sx_blend_opt_control = 0;
if (!cmd_buffer->state.attachments || !subpass)
return;
for (unsigned i = 0; i < subpass->color_count; ++i) {
if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
@@ -1009,7 +1005,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
}
int idx = subpass->color_attachments[i].attachment;
struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;
struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
unsigned format = G_028C70_FORMAT(cb->cb_color_info);
unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
@@ -1288,16 +1284,16 @@ radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
int index,
struct radv_color_buffer_info *cb,
struct radv_attachment_info *att,
struct radv_image_view *iview,
VkImageLayout layout,
bool in_render_loop)
VkImageLayout layout)
{
bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
struct radv_color_buffer_info *cb = &att->cb;
uint32_t cb_color_info = cb->cb_color_info;
struct radv_image *image = iview->image;
if (!radv_layout_dcc_compressed(cmd_buffer->device, image, layout, in_render_loop,
if (!radv_layout_dcc_compressed(image, layout,
radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) {
@@ -1399,7 +1395,7 @@ static void
radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
struct radv_ds_buffer_info *ds,
struct radv_image *image, VkImageLayout layout,
bool in_render_loop, bool requires_cond_exec)
bool requires_cond_exec)
{
uint32_t db_z_info = ds->db_z_info;
uint32_t db_z_info_reg;
@@ -1408,7 +1404,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
!radv_image_is_tc_compat_htile(image))
return;
if (!radv_layout_has_htile(image, layout, in_render_loop,
if (!radv_layout_has_htile(image, layout,
radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) {
@@ -1445,13 +1441,12 @@ static void
radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
struct radv_ds_buffer_info *ds,
struct radv_image *image,
VkImageLayout layout,
bool in_render_loop)
VkImageLayout layout)
{
uint32_t db_z_info = ds->db_z_info;
uint32_t db_stencil_info = ds->db_stencil_info;
if (!radv_layout_has_htile(image, layout, in_render_loop,
if (!radv_layout_has_htile(image, layout,
radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index))) {
@@ -1519,7 +1514,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
}
/* Update the ZRANGE_PRECISION value for the TC-compat bug. */
radv_update_zrange_precision(cmd_buffer, ds, image, layout, in_render_loop, true);
radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
ds->pa_su_poly_offset_db_fmt_cntl);
@@ -1535,33 +1530,26 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
VkClearDepthStencilValue ds_clear_value,
VkImageAspectFlags aspects)
{
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_attachment_info *att;
uint32_t att_idx;
if (!cmd_buffer->state.attachments || !subpass)
if (!framebuffer || !subpass)
return;
if (!subpass->depth_stencil_attachment)
return;
att_idx = subpass->depth_stencil_attachment->attachment;
if (cmd_buffer->state.attachments[att_idx].iview->image != image)
att = &framebuffer->attachments[att_idx];
if (att->attachment->image != image)
return;
if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
VK_IMAGE_ASPECT_STENCIL_BIT)) {
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
radeon_emit(cs, ds_clear_value.stencil);
radeon_emit(cs, fui(ds_clear_value.depth));
} else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
radeon_emit(cs, fui(ds_clear_value.depth));
} else {
assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
radeon_emit(cs, ds_clear_value.stencil);
}
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
radeon_emit(cs, ds_clear_value.stencil);
radeon_emit(cs, fui(ds_clear_value.depth));
/* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
* only needed when clearing Z to 0.0.
@@ -1569,10 +1557,9 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
ds_clear_value.depth == 0.0) {
VkImageLayout layout = subpass->depth_stencil_attachment->layout;
bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, image,
layout, in_render_loop, false);
radv_update_zrange_precision(cmd_buffer, &att->ds, image,
layout, false);
}
cmd_buffer->state.context_roll_without_scissor_emitted = true;
@@ -1793,18 +1780,21 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
int cb_idx,
uint32_t color_values[2])
{
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_attachment_info *att;
uint32_t att_idx;
if (!cmd_buffer->state.attachments || !subpass)
if (!framebuffer || !subpass)
return;
att_idx = subpass->color_attachments[cb_idx].attachment;
if (att_idx == VK_ATTACHMENT_UNUSED)
return;
if (cmd_buffer->state.attachments[att_idx].iview->image != image)
att = &framebuffer->attachments[att_idx];
if (att->attachment->image != image)
return;
radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
@@ -1929,15 +1919,15 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
}
int idx = subpass->color_attachments[i].attachment;
struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
struct radv_attachment_info *att = &framebuffer->attachments[idx];
struct radv_image_view *iview = att->attachment;
VkImageLayout layout = subpass->color_attachments[i].layout;
bool in_render_loop = subpass->color_attachments[i].in_render_loop;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->bo);
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, in_render_loop);
radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
radv_load_color_clear_metadata(cmd_buffer, iview, i);
}
@@ -1945,21 +1935,21 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
if (subpass->depth_stencil_attachment) {
int idx = subpass->depth_stencil_attachment->attachment;
VkImageLayout layout = subpass->depth_stencil_attachment->layout;
bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop;
struct radv_image *image = cmd_buffer->state.attachments[idx].iview->image;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo);
struct radv_attachment_info *att = &framebuffer->attachments[idx];
struct radv_image *image = att->attachment->image;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
/* We currently don't support writing decompressed HTILE */
assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) ==
radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask));
assert(radv_layout_has_htile(image, layout, queue_mask) ==
radv_layout_is_htile_compressed(image, layout, queue_mask));
radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, image, layout, in_render_loop);
radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
if (cmd_buffer->state.attachments[idx].ds.offset_scale != cmd_buffer->state.offset_scale) {
if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
cmd_buffer->state.offset_scale = cmd_buffer->state.attachments[idx].ds.offset_scale;
cmd_buffer->state.offset_scale = att->ds.offset_scale;
}
radv_load_ds_clear_metadata(cmd_buffer, image);
} else {
@@ -2281,15 +2271,14 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
return;
radv_foreach_stage(stage, stages) {
shader = radv_get_shader(pipeline, stage);
if (!shader)
if (!pipeline->shaders[stage])
continue;
need_push_constants |= shader->info.info.loads_push_constants;
need_push_constants |= shader->info.info.loads_dynamic_offsets;
need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
uint8_t base = shader->info.info.base_inline_push_consts;
uint8_t count = shader->info.info.num_inline_push_consts;
uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
AC_UD_INLINE_PUSH_CONSTANTS,
@@ -2858,7 +2847,7 @@ radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_cmd_state *state = &cmd_buffer->state;
uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
struct radv_image_view *view = state->attachments[att_idx].iview;
struct radv_image_view *view = state->framebuffer->attachments[att_idx].attachment;
if (view->image->info.samples == 1)
return NULL;
@@ -2897,7 +2886,7 @@ static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buf
bool begin_subpass)
{
unsigned idx = att.attachment;
struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
struct radv_sample_locations_state *sample_locs;
VkImageSubresourceRange range;
range.aspectMask = 0;
@@ -2926,12 +2915,9 @@ static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buf
radv_handle_image_transition(cmd_buffer,
view->image,
cmd_buffer->state.attachments[idx].current_layout,
cmd_buffer->state.attachments[idx].current_in_render_loop,
att.layout, att.in_render_loop,
0, 0, &range, sample_locs);
att.layout, 0, 0, &range, sample_locs);
cmd_buffer->state.attachments[idx].current_layout = att.layout;
cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;
}
@@ -2954,6 +2940,7 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
vk_find_struct_const(info->pNext,
RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT);
struct radv_cmd_state *state = &cmd_buffer->state;
struct radv_framebuffer *framebuffer = state->framebuffer;
if (!sample_locs) {
state->subpass_sample_locs = NULL;
@@ -2964,7 +2951,8 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
const VkAttachmentSampleLocationsEXT *att_sample_locs =
&sample_locs->pAttachmentInitialSampleLocations[i];
uint32_t att_idx = att_sample_locs->attachmentIndex;
struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;
struct radv_attachment_info *att = &framebuffer->attachments[att_idx];
struct radv_image *image = att->attachment->image;
assert(vk_format_is_depth_or_stencil(image->vk_format));
@@ -3032,13 +3020,6 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
const VkRenderPassBeginInfo *info)
{
struct radv_cmd_state *state = &cmd_buffer->state;
const struct VkRenderPassAttachmentBeginInfoKHR *attachment_info = NULL;
if (info) {
attachment_info = vk_find_struct_const(info->pNext,
RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
}
if (pass->attachment_count == 0) {
state->attachments = NULL;
@@ -3088,20 +3069,6 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
state->attachments[i].current_layout = att->initial_layout;
state->attachments[i].sample_location.count = 0;
struct radv_image_view *iview;
if (attachment_info && attachment_info->attachmentCount > i) {
iview = radv_image_view_from_handle(attachment_info->pAttachments[i]);
} else {
iview = state->framebuffer->attachments[i];
}
state->attachments[i].iview = iview;
if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
} else {
radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
}
}
return VK_SUCCESS;
@@ -3221,11 +3188,9 @@ VkResult radv_BeginCommandBuffer(
struct radv_subpass *subpass =
&cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
if (cmd_buffer->state.framebuffer) {
result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
if (result != VK_SUCCESS)
return result;
}
result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
if (result != VK_SUCCESS)
return result;
radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
}
@@ -3335,7 +3300,7 @@ void radv_CmdBindIndexBuffer(
cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
cmd_buffer->state.index_va += index_buffer->offset + offset;
int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType));
int index_size = radv_get_vgt_index_size(indexType);
cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
@@ -3385,13 +3350,7 @@ void radv_CmdBindDescriptorSets(
for (unsigned i = 0; i < descriptorSetCount; ++i) {
unsigned idx = i + firstSet;
RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
/* If the set is already bound we only need to update the
* (potentially changed) dynamic offsets. */
if (descriptors_state->sets[idx] != set ||
!(descriptors_state->valid & (1u << idx))) {
radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
}
radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
@@ -5092,9 +5051,7 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
bool src_render_loop,
VkImageLayout dst_layout,
bool dst_render_loop,
unsigned src_queue_mask,
unsigned dst_queue_mask,
const VkImageSubresourceRange *range,
@@ -5106,18 +5063,18 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
if (radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop,
if (radv_layout_is_htile_compressed(image, dst_layout,
dst_queue_mask)) {
clear_value = 0;
}
radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (radv_layout_is_htile_compressed(image, src_layout, src_render_loop, src_queue_mask) &&
!radv_layout_is_htile_compressed(image, dst_layout, dst_render_loop, dst_queue_mask)) {
} else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
!radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
VkImageSubresourceRange local_range = *range;
local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
local_range.baseMipLevel = 0;
@@ -5221,9 +5178,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
bool src_render_loop,
VkImageLayout dst_layout,
bool dst_render_loop,
unsigned src_queue_mask,
unsigned dst_queue_mask,
const VkImageSubresourceRange *range)
@@ -5247,8 +5202,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
uint32_t value = 0xffffffffu; /* Fully expanded mode. */
bool need_decompress_pass = false;
if (radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout,
dst_render_loop,
if (radv_layout_dcc_compressed(image, dst_layout,
dst_queue_mask)) {
value = 0x20202020u;
need_decompress_pass = true;
@@ -5274,17 +5228,14 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
bool src_render_loop,
VkImageLayout dst_layout,
bool dst_render_loop,
unsigned src_queue_mask,
unsigned dst_queue_mask,
const VkImageSubresourceRange *range)
{
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
radv_init_color_image_metadata(cmd_buffer, image,
src_layout, src_render_loop,
dst_layout, dst_render_loop,
src_layout, dst_layout,
src_queue_mask, dst_queue_mask,
range);
return;
@@ -5293,18 +5244,18 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe
if (radv_dcc_enabled(image, range->baseMipLevel)) {
if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
} else if (radv_layout_dcc_compressed(cmd_buffer->device, image, src_layout, src_render_loop, src_queue_mask) &&
!radv_layout_dcc_compressed(cmd_buffer->device, image, dst_layout, dst_render_loop, dst_queue_mask)) {
} else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
!radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
radv_decompress_dcc(cmd_buffer, image, range);
} else if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
} else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
}
} else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
bool fce_eliminate = false, fmask_expand = false;
if (radv_layout_can_fast_clear(image, src_layout, src_render_loop, src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout, dst_render_loop, dst_queue_mask)) {
if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
fce_eliminate = true;
}
@@ -5329,9 +5280,7 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe
static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
bool src_render_loop,
VkImageLayout dst_layout,
bool dst_render_loop,
uint32_t src_family,
uint32_t dst_family,
const VkImageSubresourceRange *range,
@@ -5370,14 +5319,12 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
if (vk_format_is_depth(image->vk_format)) {
radv_handle_depth_image_transition(cmd_buffer, image,
src_layout, src_render_loop,
dst_layout, dst_render_loop,
src_layout, dst_layout,
src_queue_mask, dst_queue_mask,
range, sample_locs);
} else {
radv_handle_color_image_transition(cmd_buffer, image,
src_layout, src_render_loop,
dst_layout, dst_render_loop,
src_layout, dst_layout,
src_queue_mask, dst_queue_mask,
range);
}
@@ -5474,9 +5421,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
radv_handle_image_transition(cmd_buffer, image,
pImageMemoryBarriers[i].oldLayout,
false, /* Outside of a renderpass we are never in a renderloop */
pImageMemoryBarriers[i].newLayout,
false, /* Outside of a renderpass we are never in a renderloop */
pImageMemoryBarriers[i].srcQueueFamilyIndex,
pImageMemoryBarriers[i].dstQueueFamilyIndex,
&pImageMemoryBarriers[i].subresourceRange,

View File

@@ -42,7 +42,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{
assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONFIG_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));

View File

@@ -503,8 +503,9 @@ radv_dump_shader(struct radv_pipeline *pipeline,
radv_print_spirv(shader->spirv, shader->spirv_size, f);
}
if (shader->nir_string) {
fprintf(f, "NIR:\n%s\n", shader->nir_string);
if (shader->nir) {
fprintf(f, "NIR:\n");
nir_print_shader(shader->nir, f);
}
fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string);

View File

@@ -53,7 +53,6 @@ enum {
RADV_DEBUG_NOBINNING = 0x800000,
RADV_DEBUG_NO_LOAD_STORE_OPT = 0x1000000,
RADV_DEBUG_NO_NGG = 0x2000000,
RADV_DEBUG_NO_SHADER_BALLOT = 0x4000000,
};
enum {
@@ -66,8 +65,6 @@ enum {
RADV_PERFTEST_SHADER_BALLOT = 0x40,
RADV_PERFTEST_TC_COMPAT_CMASK = 0x80,
RADV_PERFTEST_CS_WAVE_32 = 0x100,
RADV_PERFTEST_PS_WAVE_32 = 0x200,
RADV_PERFTEST_GE_WAVE_32 = 0x400,
};
bool

View File

@@ -1076,14 +1076,6 @@ void radv_update_descriptor_sets(
src_ptr += src_binding_layout->offset / 4;
dst_ptr += dst_binding_layout->offset / 4;
if (src_binding_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
src_ptr += copyset->srcArrayElement / 4;
dst_ptr += copyset->dstArrayElement / 4;
memcpy(dst_ptr, src_ptr, copyset->descriptorCount);
continue;
}
src_ptr += src_binding_layout->size * copyset->srcArrayElement / 4;
dst_ptr += dst_binding_layout->size * copyset->dstArrayElement / 4;

View File

@@ -34,6 +34,7 @@
#include "radv_shader.h"
#include "radv_cs.h"
#include "util/disk_cache.h"
#include "util/strtod.h"
#include "vk_util.h"
#include <xf86drm.h>
#include <amdgpu.h>
@@ -172,11 +173,12 @@ radv_physical_device_init_mem_types(struct radv_physical_device *device)
.heapIndex = vram_index,
};
}
if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
if (gart_index >= 0) {
device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
(device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
.heapIndex = gart_index,
};
}
@@ -189,19 +191,6 @@ radv_physical_device_init_mem_types(struct radv_physical_device *device)
.heapIndex = visible_vram_index,
};
}
if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
/* Put GTT after visible VRAM for GPUs without dedicated VRAM
* as they have identical property flags, and according to the
* spec, for types with identical flags, the one with greater
* performance must be given a lower index. */
device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = gart_index,
};
}
if (gart_index >= 0) {
device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
@@ -359,8 +348,7 @@ radv_physical_device_init(struct radv_physical_device *device,
device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
device->rad_info.family == CHIP_VEGA12 ||
device->rad_info.family == CHIP_RAVEN ||
device->rad_info.family == CHIP_RAVEN2 ||
device->rad_info.family == CHIP_RENOIR;
device->rad_info.family == CHIP_RAVEN2;
}
/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
@@ -391,27 +379,16 @@ radv_physical_device_init(struct radv_physical_device *device,
device->rad_info.me_fw_feature >= 41);
device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
device->rad_info.family == CHIP_RENOIR ||
device->rad_info.chip_class >= GFX10;
device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
/* Determine the number of threads per wave for all stages. */
device->cs_wave_size = 64;
device->ps_wave_size = 64;
device->ge_wave_size = 64;
if (device->rad_info.chip_class >= GFX10) {
if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
device->cs_wave_size = 32;
/* For pixel shaders, wave64 is recommanded. */
if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
device->ps_wave_size = 32;
if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
device->ge_wave_size = 32;
}
radv_physical_device_init_mem_types(device);
@@ -507,7 +484,6 @@ static const struct debug_control radv_debug_options[] = {
{"nobinning", RADV_DEBUG_NOBINNING},
{"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
{"nongg", RADV_DEBUG_NO_NGG},
{"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
{NULL, 0}
};
@@ -527,8 +503,6 @@ static const struct debug_control radv_perftest_options[] = {
{"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
{"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
{"cswave32", RADV_PERFTEST_CS_WAVE_32},
{"pswave32", RADV_PERFTEST_PS_WAVE_32},
{"gewave32", RADV_PERFTEST_GE_WAVE_32},
{NULL, 0}
};
@@ -566,22 +540,6 @@ radv_handle_per_app_options(struct radv_instance *instance,
*/
if (HAVE_LLVM < 0x900)
instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
} else if (!strcmp(name, "Wolfenstein: Youngblood")) {
if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
/* Force enable VK_AMD_shader_ballot because it looks
* safe and it gives a nice boost (+20% on Vega 56 at
* this time).
*/
instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
}
} else if (!strcmp(name, "Fledge")) {
/*
* Zero VRAM for "The Surge 2"
*
* This avoid a hang when when rendering any level. Likely
* uninitialized data in an indirect draw.
*/
instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
}
}
@@ -596,10 +554,8 @@ static int radv_get_instance_extension_index(const char *name)
static const char radv_dri_options_xml[] =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_SECTION_QUALITY
DRI_CONF_ADAPTIVE_SYNC("true")
DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
DRI_CONF_SECTION_END
DRI_CONF_END;
@@ -608,9 +564,7 @@ static void radv_init_dri_options(struct radv_instance *instance)
driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
driParseConfigFiles(&instance->dri_options,
&instance->available_dri_options,
0, "radv", NULL,
instance->engineName,
instance->engineVersion);
0, "radv", NULL);
}
VkResult radv_CreateInstance(
@@ -631,13 +585,6 @@ VkResult radv_CreateInstance(
client_version = VK_API_VERSION_1_0;
}
const char *engine_name = NULL;
uint32_t engine_version = 0;
if (pCreateInfo->pApplicationInfo) {
engine_name = pCreateInfo->pApplicationInfo->pEngineName;
engine_version = pCreateInfo->pApplicationInfo->engineVersion;
}
instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
if (!instance)
@@ -681,10 +628,7 @@ VkResult radv_CreateInstance(
return vk_error(instance, result);
}
instance->engineName = vk_strdup(&instance->alloc, engine_name,
VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
instance->engineVersion = engine_version;
_mesa_locale_init();
glsl_type_singleton_init_or_ref();
VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
@@ -710,11 +654,10 @@ void radv_DestroyInstance(
radv_physical_device_finish(instance->physicalDevices + i);
}
vk_free(&instance->alloc, instance->engineName);
VG(VALGRIND_DESTROY_MEMPOOL(instance));
glsl_type_singleton_decref();
_mesa_locale_fini();
driDestroyOptionCache(&instance->dri_options);
driDestroyOptionInfo(&instance->available_dri_options);
@@ -1019,8 +962,11 @@ void radv_GetPhysicalDeviceFeatures2(
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
(VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
/* TODO: Enable this once the driver supports 64-bit
* compare&swap atomic operations.
*/
features->shaderBufferInt64Atomics = false;
features->shaderSharedInt64Atomics = false;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
@@ -1056,18 +1002,6 @@ void radv_GetPhysicalDeviceFeatures2(
features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
(VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
features->imagelessFramebuffer = true;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
(VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
features->pipelineExecutableInfo = true;
break;
}
default:
break;
}
@@ -1167,7 +1101,7 @@ void radv_GetPhysicalDeviceProperties(
.viewportBoundsRange = { INT16_MIN, INT16_MAX },
.viewportSubPixelBits = 8,
.minMemoryMapAlignment = 4096, /* A page */
.minTexelBufferOffsetAlignment = 4,
.minTexelBufferOffsetAlignment = 1,
.minUniformBufferOffsetAlignment = 4,
.minStorageBufferOffsetAlignment = 4,
.minTexelOffset = -32,
@@ -1328,7 +1262,7 @@ void radv_GetPhysicalDeviceProperties2(
/* SGPR. */
properties->sgprsPerSimd =
ac_get_num_physical_sgprs(&pdevice->rad_info);
ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
properties->minSgprAllocation =
pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
properties->maxSgprAllocation =
@@ -1944,9 +1878,6 @@ VkResult radv_CreateDevice(
device->enabled_extensions.EXT_descriptor_indexing ||
device->enabled_extensions.EXT_buffer_device_address;
device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
pCreateInfo->pEnabledFeatures->robustBufferAccess;
mtx_init(&device->shader_slab_mutex, mtx_plain);
list_inithead(&device->shader_slabs);
@@ -1983,10 +1914,10 @@ VkResult radv_CreateDevice(
device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
!(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
/* Disabled and not implemented for now. */
device->dfsm_allowed = device->pbb_allowed &&
(device->physical_device->rad_info.family == CHIP_RAVEN ||
device->physical_device->rad_info.family == CHIP_RAVEN2 ||
device->physical_device->rad_info.family == CHIP_RENOIR);
device->physical_device->rad_info.family == CHIP_RAVEN2);
#ifdef ANDROID
device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
@@ -2667,8 +2598,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
*initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
*initial_preamble_cs = queue->initial_preamble_cs;
*continue_preamble_cs = queue->continue_preamble_cs;
if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size &&
!needs_tess_rings && !needs_sample_positions)
if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
*continue_preamble_cs = NULL;
return VK_SUCCESS;
}
@@ -4411,7 +4341,7 @@ radv_init_dcc_control_reg(struct radv_device *device,
S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
}
void
static void
radv_initialise_color_surface(struct radv_device *device,
struct radv_color_buffer_info *cb,
struct radv_image_view *iview)
@@ -4470,15 +4400,15 @@ radv_initialise_color_surface(struct radv_device *device,
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
if (radv_image_has_fmask(iview->image)) {
if (device->physical_device->rad_info.chip_class >= GFX7)
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without FMASK. */
if (device->physical_device->rad_info.chip_class >= GFX7)
@@ -4490,7 +4420,7 @@ radv_initialise_color_surface(struct radv_device *device,
/* CMASK variables */
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->cmask_offset;
va += iview->image->cmask.offset;
cb->cb_color_cmask = va >> 8;
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
@@ -4519,9 +4449,9 @@ radv_initialise_color_surface(struct radv_device *device,
}
if (radv_image_has_fmask(iview->image)) {
va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
cb->cb_color_fmask = va >> 8;
cb->cb_color_fmask |= surf->fmask_tile_swizzle;
cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
@@ -4532,7 +4462,7 @@ radv_initialise_color_surface(struct radv_device *device,
format = radv_translate_colorformat(iview->vk_format);
if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
radv_finishme("Illegal color\n");
swap = radv_translate_colorswap(iview->vk_format, false);
swap = radv_translate_colorswap(iview->vk_format, FALSE);
endian = radv_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
@@ -4571,7 +4501,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (radv_image_has_fmask(iview->image)) {
cb->cb_color_info |= S_028C70_COMPRESSION(1);
if (device->physical_device->rad_info.chip_class == GFX6) {
unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
@@ -4671,7 +4601,7 @@ radv_calc_decompress_on_z_planes(struct radv_device *device,
return max_zplanes;
}
void
static void
radv_initialise_ds_surface(struct radv_device *device,
struct radv_ds_buffer_info *ds,
struct radv_image_view *iview)
@@ -4865,15 +4795,11 @@ VkResult radv_CreateFramebuffer(
{
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_framebuffer *framebuffer;
const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
vk_find_struct_const(pCreateInfo->pNext,
FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
size_t size = sizeof(*framebuffer);
if (!imageless_create_info)
size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
size_t size = sizeof(*framebuffer) +
sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (framebuffer == NULL)
@@ -4883,23 +4809,18 @@ VkResult radv_CreateFramebuffer(
framebuffer->width = pCreateInfo->width;
framebuffer->height = pCreateInfo->height;
framebuffer->layers = pCreateInfo->layers;
if (imageless_create_info) {
for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
const VkFramebufferAttachmentImageInfoKHR *attachment =
imageless_create_info->pAttachmentImageInfos + i;
framebuffer->width = MIN2(framebuffer->width, attachment->width);
framebuffer->height = MIN2(framebuffer->height, attachment->height);
framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
}
} else {
for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
VkImageView _iview = pCreateInfo->pAttachments[i];
struct radv_image_view *iview = radv_image_view_from_handle(_iview);
framebuffer->attachments[i] = iview;
framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
VkImageView _iview = pCreateInfo->pAttachments[i];
struct radv_image_view *iview = radv_image_view_from_handle(_iview);
framebuffer->attachments[i].attachment = iview;
if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
} else {
radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
}
framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
}
*pFramebuffer = radv_framebuffer_to_handle(framebuffer);

View File

@@ -75,17 +75,15 @@ EXTENSIONS = [
Extension('VK_KHR_get_physical_device_properties2', 1, True),
Extension('VK_KHR_get_surface_capabilities2', 1, 'RADV_HAS_SURFACE'),
Extension('VK_KHR_image_format_list', 1, True),
Extension('VK_KHR_imageless_framebuffer', 1, True),
Extension('VK_KHR_incremental_present', 1, 'RADV_HAS_SURFACE'),
Extension('VK_KHR_maintenance1', 1, True),
Extension('VK_KHR_maintenance2', 1, True),
Extension('VK_KHR_maintenance3', 1, True),
Extension('VK_KHR_pipeline_executable_properties', 1, True),
Extension('VK_KHR_push_descriptor', 1, True),
Extension('VK_KHR_relaxed_block_layout', 1, True),
Extension('VK_KHR_sampler_mirror_clamp_to_edge', 1, True),
Extension('VK_KHR_sampler_ycbcr_conversion', 1, True),
Extension('VK_KHR_shader_atomic_int64', 1, 'HAVE_LLVM >= 0x0900'),
Extension('VK_KHR_shader_atomic_int64', 1, False),
Extension('VK_KHR_shader_draw_parameters', 1, True),
Extension('VK_KHR_shader_float16_int8', 1, True),
Extension('VK_KHR_storage_buffer_storage_class', 1, True),

View File

@@ -1305,10 +1305,6 @@ get_external_image_format_properties(const VkPhysicalDeviceImageFormatInfo2 *pIm
VkExternalMemoryFeatureFlagBits flags = 0;
VkExternalMemoryHandleTypeFlags export_flags = 0;
VkExternalMemoryHandleTypeFlags compat_flags = 0;
if (pImageFormatInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
return;
switch (handleType) {
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT:
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
@@ -1385,9 +1381,14 @@ VkResult radv_GetPhysicalDeviceImageFormatProperties2(
* present and VkExternalImageFormatProperties will be ignored.
*/
if (external_info && external_info->handleType != 0) {
get_external_image_format_properties(base_info, external_info->handleType,
&external_props->externalMemoryProperties);
if (!external_props->externalMemoryProperties.externalMemoryFeatures) {
switch (external_info->handleType) {
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT:
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT:
get_external_image_format_properties(base_info, external_info->handleType,
&external_props->externalMemoryProperties);
break;
default:
/* From the Vulkan 1.0.97 spec:
*
* If handleType is not compatible with the [parameters] specified

View File

@@ -454,8 +454,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
unsigned plane_id,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
bool is_storage_image, bool disable_compression,
uint32_t *state)
bool is_storage_image, uint32_t *state)
{
struct radv_image_plane *plane = &image->planes[plane_id];
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
@@ -480,23 +479,21 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= GFX8) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (!disable_compression && radv_dcc_enabled(image, first_level)) {
if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
meta_va |= dcc_tile_swizzle;
} else if (!disable_compression &&
} else if (!is_storage_image &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
}
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
if (chip_class <= GFX9)
if (chip_class <= GFX9) {
state[7] = meta_va >> 8;
state[7] |= plane->surface.tile_swizzle;
}
}
}
@@ -620,7 +617,7 @@ static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
return bc_swizzle;
}
bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
static bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
{
const struct vk_format_description *desc = vk_format_description(format);
@@ -694,7 +691,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
*/
state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
S_00A010_BASE_ARRAY(first_layer);
state[5] = S_00A014_ARRAY_PITCH(0) |
state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
S_00A014_MAX_MIP(image->info.samples > 1 ?
util_logbase2(image->info.samples) :
image->info.levels - 1) |
@@ -716,7 +713,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
va = gpu_address + image->offset + image->fmask_offset;
va = gpu_address + image->offset + image->fmask.offset;
switch (image->info.samples) {
case 2:
@@ -880,7 +877,7 @@ si_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
va = gpu_address + image->offset + image->fmask_offset;
va = gpu_address + image->offset + image->fmask.offset;
if (device->physical_device->rad_info.chip_class == GFX9) {
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
@@ -916,7 +913,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
fmask_state[0] = va >> 8;
fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT(fmask_format) |
S_008F14_NUM_FORMAT(num_format);
@@ -940,20 +937,20 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
va = gpu_address + image->offset + image->cmask.offset;
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
}
} else {
fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
va = gpu_address + image->offset + image->cmask.offset;
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
@@ -1027,7 +1024,7 @@ radv_query_opaque_metadata(struct radv_device *device,
desc, NULL);
si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
image->planes[0].surface.blk_w, false, false, false, desc);
image->planes[0].surface.blk_w, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
@@ -1102,38 +1099,82 @@ radv_image_override_offset_stride(struct radv_device *device,
}
}
/* The number of samples can be specified independently of the texture. */
static void
radv_image_get_fmask_info(struct radv_device *device,
struct radv_image *image,
unsigned nr_samples,
struct radv_fmask_info *out)
{
if (device->physical_device->rad_info.chip_class >= GFX9) {
out->alignment = image->planes[0].surface.fmask_alignment;
out->size = image->planes[0].surface.fmask_size;
out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
return;
}
out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
out->alignment = image->planes[0].surface.fmask_alignment;
out->size = image->planes[0].surface.fmask_size;
assert(!out->tile_swizzle || !image->shareable);
}
static void
radv_image_alloc_fmask(struct radv_device *device,
struct radv_image *image)
{
unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
image->fmask_offset = align64(image->size, fmask_alignment);
image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
image->alignment = MAX2(image->alignment, fmask_alignment);
image->fmask.offset = align64(image->size, image->fmask.alignment);
image->size = image->fmask.offset + image->fmask.size;
image->alignment = MAX2(image->alignment, image->fmask.alignment);
}
static void
radv_image_get_cmask_info(struct radv_device *device,
struct radv_image *image,
struct radv_cmask_info *out)
{
assert(image->plane_count == 1);
if (device->physical_device->rad_info.chip_class >= GFX9) {
out->alignment = image->planes[0].surface.cmask_alignment;
out->size = image->planes[0].surface.cmask_size;
return;
}
out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
out->alignment = image->planes[0].surface.cmask_alignment;
out->slice_size = image->planes[0].surface.cmask_slice_size;
out->size = image->planes[0].surface.cmask_size;
}
static void
radv_image_alloc_cmask(struct radv_device *device,
struct radv_image *image)
{
unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
unsigned cmask_size = image->planes[0].surface.cmask_size;
uint32_t clear_value_size = 0;
radv_image_get_cmask_info(device, image, &image->cmask);
if (!cmask_size)
if (!image->cmask.size)
return;
assert(cmask_alignment);
assert(image->cmask.alignment);
image->cmask_offset = align64(image->size, cmask_alignment);
image->cmask.offset = align64(image->size, image->cmask.alignment);
/* + 8 for storing the clear values */
if (!image->clear_value_offset) {
image->clear_value_offset = image->cmask_offset + cmask_size;
image->clear_value_offset = image->cmask.offset + image->cmask.size;
clear_value_size = 8;
}
image->size = image->cmask_offset + cmask_size + clear_value_size;
image->alignment = MAX2(image->alignment, cmask_alignment);
image->size = image->cmask.offset + image->cmask.size + clear_value_size;
image->alignment = MAX2(image->alignment, image->cmask.alignment);
}
static void
@@ -1401,8 +1442,8 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
struct radv_device *device,
VkFormat vk_format,
const VkComponentMapping *components,
bool is_storage_image, bool disable_compression,
unsigned plane_id, unsigned descriptor_plane_id)
bool is_storage_image, unsigned plane_id,
unsigned descriptor_plane_id)
{
struct radv_image *image = iview->image;
struct radv_image_plane *plane = &image->planes[plane_id];
@@ -1449,9 +1490,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
plane_id,
iview->base_mip,
iview->base_mip,
blk_w, is_stencil, is_storage_image,
is_storage_image || disable_compression,
descriptor->plane_descriptors[descriptor_plane_id]);
blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
}
static unsigned
@@ -1491,8 +1530,7 @@ radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
void
radv_image_view_init(struct radv_image_view *iview,
struct radv_device *device,
const VkImageViewCreateInfo* pCreateInfo,
const struct radv_image_view_extra_create_info* extra_create_info)
const VkImageViewCreateInfo* pCreateInfo)
{
RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
@@ -1592,23 +1630,15 @@ radv_image_view_init(struct radv_image_view *iview,
iview->base_mip = range->baseMipLevel;
iview->level_count = radv_get_levelCount(image, range);
bool disable_compression = extra_create_info ? extra_create_info->disable_compression: false;
for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
radv_image_view_make_descriptor(iview, device, format,
&pCreateInfo->components,
false, disable_compression,
iview->plane_id + i, i);
radv_image_view_make_descriptor(iview, device,
format, &pCreateInfo->components,
true, disable_compression,
iview->plane_id + i, i);
radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
}
}
bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
if (radv_image_is_tc_compat_htile(image))
@@ -1622,7 +1652,6 @@ bool radv_layout_has_htile(const struct radv_image *image,
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
if (radv_image_is_tc_compat_htile(image))
@@ -1636,16 +1665,13 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
}
bool radv_layout_dcc_compressed(const struct radv_device *device,
const struct radv_image *image,
bool radv_layout_dcc_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
/* Don't compress compute transfer dst, as image stores are not supported. */
@@ -1778,7 +1804,7 @@ radv_CreateImageView(VkDevice _device,
if (view == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
radv_image_view_init(view, device, pCreateInfo, NULL);
radv_image_view_init(view, device, pCreateInfo);
*pView = radv_image_view_to_handle(view);

View File

@@ -28,10 +28,8 @@
class radv_llvm_per_thread_info {
public:
radv_llvm_per_thread_info(enum radeon_family arg_family,
enum ac_target_machine_options arg_tm_options,
unsigned arg_wave_size)
: family(arg_family), tm_options(arg_tm_options),
wave_size(arg_wave_size), passes(NULL), passes_wave32(NULL) {}
enum ac_target_machine_options arg_tm_options)
: family(arg_family), tm_options(arg_tm_options), passes(NULL) {}
~radv_llvm_per_thread_info()
{
@@ -49,28 +47,19 @@ public:
if (!passes)
return false;
if (llvm_info.tm_wave32) {
passes_wave32 = ac_create_llvm_passes(llvm_info.tm_wave32);
if (!passes_wave32)
return false;
}
return true;
}
bool compile_to_memory_buffer(LLVMModuleRef module,
char **pelf_buffer, size_t *pelf_size)
{
struct ac_compiler_passes *p = wave_size == 32 ? passes_wave32 : passes;
return ac_compile_module_to_elf(p, module, pelf_buffer, pelf_size);
return ac_compile_module_to_elf(passes, module, pelf_buffer, pelf_size);
}
bool is_same(enum radeon_family arg_family,
enum ac_target_machine_options arg_tm_options,
unsigned arg_wave_size) {
enum ac_target_machine_options arg_tm_options) {
if (arg_family == family &&
arg_tm_options == tm_options &&
arg_wave_size == wave_size)
arg_tm_options == tm_options)
return true;
return false;
}
@@ -78,9 +67,7 @@ public:
private:
enum radeon_family family;
enum ac_target_machine_options tm_options;
unsigned wave_size;
struct ac_compiler_passes *passes;
struct ac_compiler_passes *passes_wave32;
};
/* we have to store a linked list per thread due to the possiblity of multiple gpus being required */
@@ -112,18 +99,17 @@ bool radv_compile_to_elf(struct ac_llvm_compiler *info,
bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool thread_compiler,
enum radeon_family family,
enum ac_target_machine_options tm_options,
unsigned wave_size)
enum ac_target_machine_options tm_options)
{
if (thread_compiler) {
for (auto &I : radv_llvm_per_thread_list) {
if (I.is_same(family, tm_options, wave_size)) {
if (I.is_same(family, tm_options)) {
*info = I.llvm_info;
return true;
}
}
radv_llvm_per_thread_list.emplace_back(family, tm_options, wave_size);
radv_llvm_per_thread_list.emplace_back(family, tm_options);
radv_llvm_per_thread_info &tinfo = radv_llvm_per_thread_list.back();
if (!tinfo.init()) {

View File

@@ -660,7 +660,7 @@ void radv_CmdBlitImage(
.baseArrayLayer = dest_array_slice,
.layerCount = 1
},
}, NULL);
});
radv_image_view_init(&src_iview, cmd_buffer->device,
&(VkImageViewCreateInfo) {
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
@@ -674,7 +674,7 @@ void radv_CmdBlitImage(
.baseArrayLayer = src_array_slice,
.layerCount = 1
},
}, NULL);
});
meta_emit_blit(cmd_buffer,
src_image, &src_iview, srcImageLayout,
src_offset_0, src_offset_1,

View File

@@ -79,7 +79,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = surf->layer,
.layerCount = 1
},
}, NULL);
});
}
static void
@@ -408,7 +408,7 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
unsigned num_rects,
struct radv_meta_blit2d_rect *rects)
{
bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class == GFX9 &&
(src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
@@ -698,7 +698,7 @@ radv_device_finish_meta_blit2d_state(struct radv_device *device)
state->blit2d_stencil_only_rp[j], &state->alloc);
}
for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; ++log2_samples) {
for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; ++log2_samples) {
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
radv_DestroyPipelineLayout(radv_device_to_handle(device),
state->blit2d[log2_samples].p_layouts[src],
@@ -1308,9 +1308,9 @@ VkResult
radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand)
{
VkResult result;
bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
bool create_3d = device->physical_device->rad_info.chip_class == GFX9;
for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; log2_samples++) {
for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; log2_samples++) {
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
continue;

View File

@@ -135,7 +135,7 @@ radv_device_init_meta_itob_state(struct radv_device *device)
struct radv_shader_module cs_3d = { .nir = NULL };
cs.nir = build_nir_itob_compute_shader(device, false);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
cs_3d.nir = build_nir_itob_compute_shader(device, true);
/*
@@ -211,7 +211,7 @@ radv_device_init_meta_itob_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
if (device->physical_device->rad_info.chip_class >= GFX9) {
if (device->physical_device->rad_info.chip_class == GFX9) {
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -256,7 +256,7 @@ radv_device_finish_meta_itob_state(struct radv_device *device)
&state->alloc);
radv_DestroyPipeline(radv_device_to_handle(device),
state->itob.pipeline, &state->alloc);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
radv_DestroyPipeline(radv_device_to_handle(device),
state->itob.pipeline_3d, &state->alloc);
}
@@ -361,7 +361,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device)
struct radv_shader_module cs = { .nir = NULL };
struct radv_shader_module cs_3d = { .nir = NULL };
cs.nir = build_nir_btoi_compute_shader(device, false);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
cs_3d.nir = build_nir_btoi_compute_shader(device, true);
/*
* two descriptors one for the image being sampled
@@ -436,7 +436,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
if (device->physical_device->rad_info.chip_class >= GFX9) {
if (device->physical_device->rad_info.chip_class == GFX9) {
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -785,7 +785,7 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
struct radv_shader_module cs = { .nir = NULL };
struct radv_shader_module cs_3d = { .nir = NULL };
cs.nir = build_nir_itoi_compute_shader(device, false);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
cs_3d.nir = build_nir_itoi_compute_shader(device, true);
/*
* two descriptors one for the image being sampled
@@ -860,7 +860,7 @@ radv_device_init_meta_itoi_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
if (device->physical_device->rad_info.chip_class >= GFX9) {
if (device->physical_device->rad_info.chip_class == GFX9) {
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
@@ -904,7 +904,7 @@ radv_device_finish_meta_itoi_state(struct radv_device *device)
&state->alloc);
radv_DestroyPipeline(radv_device_to_handle(device),
state->itoi.pipeline, &state->alloc);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
radv_DestroyPipeline(radv_device_to_handle(device),
state->itoi.pipeline_3d, &state->alloc);
}
@@ -1191,7 +1191,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device)
struct radv_shader_module cs = { .nir = NULL };
struct radv_shader_module cs_3d = { .nir = NULL };
cs.nir = build_nir_cleari_compute_shader(device, false);
if (device->physical_device->rad_info.chip_class >= GFX9)
if (device->physical_device->rad_info.chip_class == GFX9)
cs_3d.nir = build_nir_cleari_compute_shader(device, true);
/*
@@ -1261,7 +1261,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device)
goto fail;
if (device->physical_device->rad_info.chip_class >= GFX9) {
if (device->physical_device->rad_info.chip_class == GFX9) {
/* compute shader */
VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -1552,7 +1552,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = surf->layer,
.layerCount = 1
},
}, NULL);
});
}
static void
@@ -1706,7 +1706,7 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view);
itob_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
if (device->physical_device->rad_info.chip_class == GFX9 &&
src->image->type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.itob.pipeline_3d;
@@ -1875,7 +1875,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
create_iview(cmd_buffer, dst, &dst_view);
btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
if (device->physical_device->rad_info.chip_class == GFX9 &&
dst->image->type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -2060,7 +2060,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
if (device->physical_device->rad_info.chip_class == GFX9 &&
(src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D))
pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
@@ -2201,7 +2201,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer,
create_iview(cmd_buffer, dst, &dst_iview);
cleari_bind_descriptors(cmd_buffer, &dst_iview);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
if (device->physical_device->rad_info.chip_class == GFX9 &&
dst->image->type == VK_IMAGE_TYPE_3D)
pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d;

View File

@@ -367,10 +367,10 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_device *device = cmd_buffer->device;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t subpass_att = clear_att->colorAttachment;
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
const struct radv_image_view *iview = cmd_buffer->state.attachments ?
cmd_buffer->state.attachments[pass_att].iview : NULL;
const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
uint32_t samples, samples_log2;
VkFormat format;
unsigned fs_key;
@@ -629,7 +629,6 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image_view *iview,
VkImageAspectFlags aspects,
VkImageLayout layout,
bool in_render_loop,
const VkClearRect *clear_rect,
VkClearDepthStencilValue clear_value)
{
@@ -652,7 +651,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
iview->base_mip == 0 &&
iview->base_layer == 0 &&
iview->layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(iview->image, layout, in_render_loop, queue_mask) &&
radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
radv_image_extent_compare(iview->image, &iview->extent))
return true;
return false;
@@ -665,12 +664,10 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
int samples_log2,
VkImageAspectFlags aspects,
VkImageLayout layout,
bool in_render_loop,
const VkClearRect *clear_rect,
VkClearDepthStencilValue clear_value)
{
bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout,
in_render_loop, clear_rect, clear_value);
bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
int index = DEPTH_CLEAR_SLOW;
VkPipeline *pipeline;
@@ -724,11 +721,11 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *meta_state = &device->meta_state;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const uint32_t pass_att = ds_att->attachment;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
VkImageAspectFlags aspects = clear_att->aspectMask;
const struct radv_image_view *iview = cmd_buffer->state.attachments ?
cmd_buffer->state.attachments[pass_att].iview : NULL;
const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
uint32_t samples, samples_log2;
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
@@ -766,7 +763,6 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
samples_log2,
aspects,
ds_att->layout,
ds_att->in_render_loop,
clear_rect,
clear_value);
if (!pipeline)
@@ -784,8 +780,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
pipeline);
if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
ds_att->layout, ds_att->in_render_loop,
clear_rect, clear_value))
ds_att->layout, clear_rect, clear_value))
radv_update_ds_clear_metadata(cmd_buffer, iview->image,
clear_value, aspects);
@@ -986,7 +981,6 @@ static bool
radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image_view *iview,
VkImageLayout image_layout,
bool in_render_loop,
VkImageAspectFlags aspects,
const VkClearRect *clear_rect,
const VkClearDepthStencilValue clear_value,
@@ -995,10 +989,7 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
return false;
if (!radv_layout_is_htile_compressed(iview->image, image_layout, in_render_loop,
radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index)))
if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
return false;
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
@@ -1339,18 +1330,15 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
uint64_t offset = image->offset + image->cmask_offset;
uint64_t offset = image->offset + image->cmask.offset;
uint64_t size;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
/* TODO: clear layers. */
size = image->planes[0].surface.cmask_size;
size = image->cmask.size;
} else {
unsigned cmask_slice_size =
image->planes[0].surface.cmask_slice_size;
offset += cmask_slice_size * range->baseArrayLayer;
size = cmask_slice_size * radv_get_layerCount(image, range);
offset += image->cmask.slice_size * range->baseArrayLayer;
size = image->cmask.slice_size * radv_get_layerCount(image, range);
}
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
@@ -1362,7 +1350,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
uint64_t offset = image->offset + image->fmask_offset;
uint64_t offset = image->offset + image->fmask.offset;
uint64_t size;
/* MSAA images do not support mipmap levels. */
@@ -1371,14 +1359,10 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
/* TODO: clear layers. */
size = image->planes[0].surface.fmask_size;
size = image->fmask.size;
} else {
unsigned fmask_slice_size =
image->planes[0].surface.u.legacy.fmask.slice_size;
offset += fmask_slice_size * range->baseArrayLayer;
size = fmask_slice_size * radv_get_layerCount(image, range);
offset += image->fmask.slice_size * range->baseArrayLayer;
size = image->fmask.slice_size * radv_get_layerCount(image, range);
}
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
@@ -1444,9 +1428,7 @@ enum {
RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U
};
static void vi_get_fast_clear_parameters(struct radv_device *device,
VkFormat image_format,
VkFormat view_format,
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
bool *can_avoid_fast_clear_elim)
@@ -1455,20 +1437,18 @@ static void vi_get_fast_clear_parameters(struct radv_device *device,
int extra_channel;
bool main_value = false;
bool extra_value = false;
bool has_color = false;
bool has_alpha = false;
int i;
*can_avoid_fast_clear_elim = false;
*reset_value = RADV_DCC_CLEAR_REG;
const struct vk_format_description *desc = vk_format_description(view_format);
if (view_format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
view_format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
view_format == VK_FORMAT_B5G6R5_UNORM_PACK16)
const struct vk_format_description *desc = vk_format_description(format);
if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
format == VK_FORMAT_B5G6R5_UNORM_PACK16)
extra_channel = -1;
else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
if (vi_alpha_is_on_msb(device, view_format))
if (radv_translate_colorswap(format, false) <= 1)
extra_channel = desc->nr_channels - 1;
else
extra_channel = 0;
@@ -1503,21 +1483,12 @@ static void vi_get_fast_clear_parameters(struct radv_device *device,
return;
}
if (index == extra_channel) {
if (index == extra_channel)
extra_value = values[i];
has_alpha = true;
} else {
else
main_value = values[i];
has_color = true;
}
}
/* If alpha isn't present, make it the same as color, and vice versa. */
if (!has_alpha)
extra_value = main_value;
else if (!has_color)
main_value = extra_value;
for (int i = 0; i < 4; ++i)
if (values[i] != main_value &&
desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
@@ -1539,7 +1510,6 @@ static bool
radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image_view *iview,
VkImageLayout image_layout,
bool in_render_loop,
const VkClearRect *clear_rect,
VkClearColorValue clear_value,
uint32_t view_mask)
@@ -1549,10 +1519,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview))
return false;
if (!radv_layout_can_fast_clear(iview->image, image_layout, in_render_loop,
radv_image_queue_family_mask(iview->image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index)))
if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
return false;
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
@@ -1577,9 +1544,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
bool can_avoid_fast_clear_elim;
uint32_t reset_value;
vi_get_fast_clear_parameters(cmd_buffer->device,
iview->image->vk_format,
iview->vk_format,
vi_get_fast_clear_parameters(iview->vk_format,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
@@ -1651,9 +1616,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
bool can_avoid_fast_clear_elim;
bool need_decompress_pass = false;
vi_get_fast_clear_parameters(cmd_buffer->device,
iview->image->vk_format,
iview->vk_format,
vi_get_fast_clear_parameters(iview->vk_format,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
@@ -1709,11 +1672,10 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
return;
VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
bool in_render_loop = subpass->color_attachments[subpass_att].in_render_loop;
const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[pass_att].iview : NULL;
const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
VkClearColorValue clear_value = clear_att->clearValue.color;
if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout, in_render_loop,
if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout,
clear_rect, clear_value, view_mask)) {
radv_fast_clear_color(cmd_buffer, iview, clear_att,
subpass_att, pre_flush,
@@ -1731,16 +1693,15 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
return;
VkImageLayout image_layout = ds_att->layout;
bool in_render_loop = ds_att->in_render_loop;
const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL;
const struct radv_image_view *iview = fb ? fb->attachments[ds_att->attachment].attachment : NULL;
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
VK_IMAGE_ASPECT_STENCIL_BIT));
if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout,
in_render_loop, aspects, clear_rect,
clear_value, view_mask)) {
aspects, clear_rect, clear_value,
view_mask)) {
radv_fast_clear_depth(cmd_buffer, iview, clear_att,
pre_flush, post_flush);
} else {
@@ -1913,7 +1874,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = range->baseArrayLayer + layer,
.layerCount = 1
},
}, NULL);
});
VkFramebuffer fb;
radv_CreateFramebuffer(device_h,
@@ -2024,7 +1985,6 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkFormat format,
VkImageLayout image_layout,
bool in_render_loop,
const VkImageSubresourceRange *range,
const VkClearValue *clear_val)
{
@@ -2043,7 +2003,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = range->baseArrayLayer,
.layerCount = range->layerCount,
},
}, NULL);
});
VkClearRect clear_rect = {
.rect = {
@@ -2064,8 +2024,8 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
};
if (vk_format_is_color(format)) {
if (radv_can_fast_clear_color(cmd_buffer, &iview, image_layout,
in_render_loop, &clear_rect,
if (radv_can_fast_clear_color(cmd_buffer, &iview,
image_layout, &clear_rect,
clear_att.clearValue.color, 0)) {
radv_fast_clear_color(cmd_buffer, &iview, &clear_att,
clear_att.colorAttachment,
@@ -2074,9 +2034,8 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer,
}
} else {
if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout,
in_render_loop,range->aspectMask,
&clear_rect, clear_att.clearValue.depthStencil,
0)) {
range->aspectMask, &clear_rect,
clear_att.clearValue.depthStencil, 0)) {
radv_fast_clear_depth(cmd_buffer, &iview, &clear_att,
NULL, NULL);
return true;
@@ -2126,7 +2085,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
*/
if (!cs &&
radv_fast_clear_range(cmd_buffer, image, format,
image_layout, false, range,
image_layout, range,
&internal_clear_value)) {
continue;
}

View File

@@ -191,7 +191,7 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
bool compressed = radv_layout_dcc_compressed(cmd_buffer->device, image, layout, false, queue_mask);
bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
@@ -335,7 +335,7 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
bool compressed = radv_layout_dcc_compressed(cmd_buffer->device, image, layout, false, queue_mask);
bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
@@ -464,11 +464,11 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
uint32_t dst_queue_mask = radv_image_queue_family_mask(dest_image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
bool dst_compressed = radv_layout_dcc_compressed(cmd_buffer->device, dest_image, dest_image_layout, false, dst_queue_mask);
bool dst_compressed = radv_layout_dcc_compressed(dest_image, dest_image_layout, dst_queue_mask);
uint32_t src_queue_mask = radv_image_queue_family_mask(src_image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
bool src_compressed = radv_layout_dcc_compressed(cmd_buffer->device, src_image, src_image_layout, false, src_queue_mask);
bool src_compressed = radv_layout_dcc_compressed(src_image, src_image_layout, src_queue_mask);
if (!src_compressed || radv_dcc_formats_compatible(b_src.format, b_dst.format)) {
b_src.format = b_dst.format;

View File

@@ -433,7 +433,7 @@ static void radv_process_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = subresourceRange->baseArrayLayer + layer,
.layerCount = 1,
},
}, NULL);
});
VkFramebuffer fb_h;

View File

@@ -590,7 +590,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = range->baseArrayLayer + layer,
.layerCount = 1,
},
}, NULL);
});
VkFramebuffer fb_h;
radv_CreateFramebuffer(radv_device_to_handle(device),
@@ -782,8 +782,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
const VkImageSubresourceRange *subresourceRange)
{
struct radv_meta_saved_state saved_state;
struct radv_image_view load_iview = {0};
struct radv_image_view store_iview = {0};
struct radv_image_view iview = {0};
struct radv_device *device = cmd_buffer->device;
/* This assumes the image is 2d with 1 layer */
@@ -820,7 +819,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
subresourceRange->baseMipLevel + l);
for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
radv_image_view_init(&load_iview, cmd_buffer->device,
radv_image_view_init(&iview, cmd_buffer->device,
&(VkImageViewCreateInfo) {
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
@@ -833,22 +832,6 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
.layerCount = 1
},
}, NULL);
radv_image_view_init(&store_iview, cmd_buffer->device,
&(VkImageViewCreateInfo) {
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = image->vk_format,
.subresourceRange = {
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = subresourceRange->baseMipLevel + l,
.levelCount = 1,
.baseArrayLayer = subresourceRange->baseArrayLayer + s,
.layerCount = 1
},
}, &(struct radv_image_view_extra_create_info) {
.disable_compression = true
});
radv_meta_push_descriptor_set(cmd_buffer,
@@ -866,7 +849,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.pImageInfo = (VkDescriptorImageInfo[]) {
{
.sampler = VK_NULL_HANDLE,
.imageView = radv_image_view_to_handle(&load_iview),
.imageView = radv_image_view_to_handle(&iview),
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
},
}
@@ -880,7 +863,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
.pImageInfo = (VkDescriptorImageInfo[]) {
{
.sampler = VK_NULL_HANDLE,
.imageView = radv_image_view_to_handle(&store_iview),
.imageView = radv_image_view_to_handle(&iview),
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
},
}

View File

@@ -139,7 +139,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = subresourceRange->baseArrayLayer + l,
.layerCount = 1,
},
}, NULL);
});
radv_meta_push_descriptor_set(cmd_buffer,
VK_PIPELINE_BIND_POINT_COMPUTE,

View File

@@ -330,12 +330,10 @@ enum radv_resolve_method {
RESOLVE_FRAGMENT,
};
static void radv_pick_resolve_method_images(struct radv_device *device,
struct radv_image *src_image,
static void radv_pick_resolve_method_images(struct radv_image *src_image,
VkFormat src_format,
struct radv_image *dest_image,
VkImageLayout dest_image_layout,
bool dest_render_loop,
struct radv_cmd_buffer *cmd_buffer,
enum radv_resolve_method *method)
@@ -354,8 +352,7 @@ static void radv_pick_resolve_method_images(struct radv_device *device,
dest_image->info.array_size > 1)
*method = RESOLVE_COMPUTE;
if (radv_layout_dcc_compressed(device, dest_image, dest_image_layout,
dest_render_loop, queue_mask)) {
if (radv_layout_dcc_compressed(dest_image, dest_image_layout, queue_mask)) {
*method = RESOLVE_FRAGMENT;
} else if (dest_image->planes[0].surface.micro_tile_mode !=
src_image->planes[0].surface.micro_tile_mode) {
@@ -434,10 +431,9 @@ void radv_CmdResolveImage(
} else
resolve_method = RESOLVE_COMPUTE;
radv_pick_resolve_method_images(cmd_buffer->device, src_image,
src_image->vk_format, dest_image,
dest_image_layout, false, cmd_buffer,
&resolve_method);
radv_pick_resolve_method_images(src_image, src_image->vk_format,
dest_image, dest_image_layout,
cmd_buffer, &resolve_method);
if (resolve_method == RESOLVE_FRAGMENT) {
radv_meta_resolve_fragment_image(cmd_buffer,
@@ -553,7 +549,7 @@ void radv_CmdResolveImage(
.baseArrayLayer = src_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
struct radv_image_view dest_iview;
radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -569,7 +565,7 @@ void radv_CmdResolveImage(
.baseArrayLayer = dest_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
VkFramebuffer fb_h;
radv_CreateFramebuffer(device_h,
@@ -645,16 +641,14 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
struct radv_image_view *src_iview =
cmd_buffer->state.attachments[src_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
struct radv_image_view *dst_iview =
cmd_buffer->state.attachments[dst_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
radv_pick_resolve_method_images(cmd_buffer->device,
src_iview->image,
radv_pick_resolve_method_images(src_iview->image,
src_iview->vk_format,
dst_iview->image,
dst_att.layout,
dst_att.in_render_loop,
cmd_buffer,
&resolve_method);
@@ -700,14 +694,12 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
/* Make sure to not clear color attachments after resolves. */
cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects = 0;
struct radv_image *dst_img = cmd_buffer->state.attachments[dest_att.attachment].iview->image;
struct radv_image_view *src_iview= cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
struct radv_image_view *src_iview= cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
struct radv_image *src_img = src_iview->image;
radv_pick_resolve_method_images(cmd_buffer->device, src_img,
src_iview->vk_format, dst_img,
dest_att.layout,
dest_att.in_render_loop,
radv_pick_resolve_method_images(src_img, src_iview->vk_format,
dst_img, dest_att.layout,
cmd_buffer, &resolve_method);
if (resolve_method == RESOLVE_FRAGMENT) {
@@ -733,7 +725,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
struct radv_image_view *dest_iview = cmd_buffer->state.attachments[dest_att.attachment].iview;
struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
struct radv_image *dst_img = dest_iview->image;
if (radv_dcc_enabled(dst_img, dest_iview->base_mip)) {
@@ -795,7 +787,8 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image_view *src_iview =
fb->attachments[src_att.attachment].attachment;
struct radv_image *src_image = src_iview->image;
VkImageResolve region = {};
@@ -810,7 +803,8 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
if (subpass->ds_resolve_attachment) {
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
struct radv_image_view *src_iview = fb->attachments[src_att.attachment];
struct radv_image_view *src_iview =
fb->attachments[src_att.attachment].attachment;
struct radv_image *src_image = src_iview->image;
VkImageResolve region = {};

View File

@@ -863,7 +863,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = src_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
struct radv_image_view dest_iview;
radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -879,7 +879,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = dest_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
emit_resolve(cmd_buffer,
&src_iview,
@@ -921,8 +921,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image_view *dst_iview = cmd_buffer->state.attachments[dst_att.attachment].iview;
struct radv_image_view *src_iview = fb->attachments[src_att.attachment].attachment;
struct radv_image_view *dst_iview = fb->attachments[dst_att.attachment].attachment;
VkImageResolve region = {
.extent = (VkExtent3D){ fb->width, fb->height, 0 },
@@ -989,9 +989,9 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
struct radv_subpass_attachment dest_att = *subpass->ds_resolve_attachment;
struct radv_image_view *src_iview =
cmd_buffer->state.attachments[src_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
struct radv_image_view *dst_iview =
cmd_buffer->state.attachments[dest_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
struct radv_image *src_image = src_iview->image;
struct radv_image *dst_image = dst_iview->image;
@@ -1011,7 +1011,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = src_iview->base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
struct radv_image_view tdst_iview;
radv_image_view_init(&tdst_iview, cmd_buffer->device,
@@ -1027,7 +1027,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = dst_iview->base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview,
&(VkOffset2D) { 0, 0 },

View File

@@ -535,7 +535,7 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device,
.pAttachments = &(VkAttachmentDescription) {
.format = src_format,
.loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
.storeOp = VK_ATTACHMENT_STORE_OP_DONT_CARE,
.storeOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
@@ -1050,7 +1050,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = src_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
struct radv_image_view dest_iview;
radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -1066,7 +1066,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = dest_base_layer + layer,
.layerCount = 1,
},
}, NULL);
});
VkFramebuffer fb;
@@ -1146,8 +1146,8 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
struct radv_image_view *dest_iview = cmd_buffer->state.attachments[dest_att.attachment].iview;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
struct radv_subpass resolve_subpass = {
.color_count = 1,
@@ -1201,10 +1201,10 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
struct radv_image_view *src_iview =
cmd_buffer->state.attachments[src_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
struct radv_image *src_image = src_iview->image;
struct radv_image_view *dst_iview =
cmd_buffer->state.attachments[dst_att.attachment].iview;
cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
struct radv_subpass resolve_subpass = {
.color_count = 0,
@@ -1228,7 +1228,7 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
.baseArrayLayer = 0,
.layerCount = 1,
},
}, NULL);
});
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
&(VkOffset2D) { 0, 0 },

View File

@@ -295,7 +295,7 @@ get_tcs_num_patches(struct radv_shader_context *ctx)
/* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
if (ctx->options->chip_class == GFX6) {
unsigned one_wave = ctx->options->wave_size / MAX2(num_tcs_input_cp, num_tcs_output_cp);
unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
num_patches = MIN2(num_patches, one_wave);
}
return num_patches;
@@ -754,7 +754,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
if (ctx->shader_info->info.loads_push_constants)
user_sgpr_count++;
if (ctx->shader_info->info.so.num_outputs)
if (ctx->streamout_buffers)
user_sgpr_count++;
uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
@@ -1703,18 +1703,6 @@ load_tes_input(struct ac_shader_abi *abi,
return result;
}
static LLVMValueRef
radv_emit_fetch_64bit(struct radv_shader_context *ctx,
LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
{
LLVMValueRef values[2] = {
ac_to_integer(&ctx->ac, a),
ac_to_integer(&ctx->ac, b),
};
LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
}
static LLVMValueRef
load_gs_input(struct ac_shader_abi *abi,
unsigned location,
@@ -1743,14 +1731,6 @@ load_gs_input(struct ac_shader_abi *abi,
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
value[i] = ac_lds_load(&ctx->ac, dw_addr);
if (ac_get_type_size(type) == 8) {
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
}
} else {
LLVMValueRef soffset =
LLVMConstInt(ctx->ac.i32,
@@ -1762,21 +1742,6 @@ load_gs_input(struct ac_shader_abi *abi,
ctx->ac.i32_0,
vtx_offset, soffset,
0, ac_glc, true, false);
if (ac_get_type_size(type) == 8) {
soffset = LLVMConstInt(ctx->ac.i32,
(param * 4 + i + const_index + 1) * 256,
false);
LLVMValueRef tmp =
ac_build_buffer_load(&ctx->ac,
ctx->esgs_ring, 1,
ctx->ac.i32_0,
vtx_offset, soffset,
0, ac_glc, true, false);
value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
}
}
if (ac_get_type_size(type) == 2) {
@@ -3073,8 +3038,7 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
LLVMBuildMul(ctx->ac.builder, wave_idx,
LLVMConstInt(ctx->ac.i32,
ctx->ac.wave_size, false), ""), "");
LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
}
@@ -3176,7 +3140,7 @@ static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp;
tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
LLVMConstInt(ctx->ac.i32, 64, false), "");
return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
}
@@ -4226,7 +4190,7 @@ ac_setup_rings(struct radv_shader_context *ctx)
*/
LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
uint64_t stream_offset = 0;
unsigned num_records = ctx->ac.wave_size;
unsigned num_records = 64;
LLVMValueRef base_ring;
base_ring =
@@ -4259,7 +4223,7 @@ ac_setup_rings(struct radv_shader_context *ctx)
ring = LLVMBuildInsertElement(ctx->ac.builder,
ring, tmp, ctx->ac.i32_0, "");
stream_offset += stride * ctx->ac.wave_size;
stream_offset += stride * 64;
ring = LLVMBuildBitCast(ctx->ac.builder, ring,
ctx->ac.v4i32, "");
@@ -4293,8 +4257,23 @@ radv_nir_get_max_workgroup_size(enum chip_class chip_class,
gl_shader_stage stage,
const struct nir_shader *nir)
{
const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
return radv_get_max_workgroup_size(chip_class, stage, nir ? nir->info.cs.local_size : backup_sizes);
switch (stage) {
case MESA_SHADER_TESS_CTRL:
return chip_class >= GFX7 ? 128 : 64;
case MESA_SHADER_GEOMETRY:
return chip_class >= GFX9 ? 128 : 64;
case MESA_SHADER_COMPUTE:
break;
default:
return 0;
}
if (!nir)
return chip_class >= GFX9 ? 128 : 64;
unsigned max_workgroup_size = nir->info.cs.local_size[0] *
nir->info.cs.local_size[1] *
nir->info.cs.local_size[2];
return max_workgroup_size;
}
/* Fixup the HW not emitting the TCS regs if there are no HS threads. */
@@ -4338,6 +4317,15 @@ static void declare_esgs_ring(struct radv_shader_context *ctx)
LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
}
static uint8_t
radv_nir_shader_wave_size(struct nir_shader *const *shaders, int shader_count,
const struct radv_nir_compiler_options *options)
{
if (shaders[0]->info.stage == MESA_SHADER_COMPUTE)
return options->cs_wave_size;
return 64;
}
static
LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
struct nir_shader *const *shaders,
@@ -4354,9 +4342,11 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
AC_FLOAT_MODE_DEFAULT;
uint8_t wave_size = radv_nir_shader_wave_size(shaders,
shader_count, options);
ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
options->family, float_mode, options->wave_size,
options->wave_size);
options->family, float_mode, wave_size);
ctx.context = ctx.ac.context;
radv_nir_shader_info_init(&shader_info->info);
@@ -4396,7 +4386,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ctx.abi.load_resource = radv_load_resource;
ctx.abi.clamp_shadow_reference = false;
ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;
ctx.abi.robust_buffer_access = options->robust_buffer_access;
/* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
* we fallback to the old intrinsics for atomic buffer image operations
@@ -4757,7 +4746,6 @@ radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
shader_info->gs.es_type = nir[0]->info.stage;
}
}
shader_info->info.wave_size = options->wave_size;
}
static void
@@ -4789,7 +4777,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
LLVMBasicBlockRef bb;
unsigned offset;
if (stream > 0 && !num_components)
if (!num_components)
continue;
if (stream > 0 && !ctx->shader_info->info.so.num_outputs)
@@ -4870,7 +4858,7 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
AC_FLOAT_MODE_DEFAULT;
ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
options->family, float_mode, 64, 64);
options->family, float_mode, 64);
ctx.context = ctx.ac.context;
ctx.is_gs_copy_shader = true;

View File

@@ -148,24 +148,6 @@ radv_render_pass_compile(struct radv_render_pass *pass)
subpass->has_color_resolve = true;
}
}
for (uint32_t j = 0; j < subpass->input_count; ++j) {
if (subpass->input_attachments[j].attachment == VK_ATTACHMENT_UNUSED)
continue;
for (uint32_t k = 0; k < subpass->color_count; ++k) {
if (subpass->color_attachments[k].attachment == subpass->input_attachments[j].attachment) {
subpass->input_attachments[j].in_render_loop = true;
subpass->color_attachments[k].in_render_loop = true;
}
}
if (subpass->depth_stencil_attachment &&
subpass->depth_stencil_attachment->attachment == subpass->input_attachments[j].attachment) {
subpass->input_attachments[j].in_render_loop = true;
subpass->depth_stencil_attachment->in_render_loop = true;
}
}
}
}

View File

@@ -178,12 +178,6 @@ static uint32_t get_hash_flags(struct radv_device *device)
hash_flags |= RADV_HASH_SHADER_NO_NGG;
if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
hash_flags |= RADV_HASH_SHADER_SISCHED;
if (device->physical_device->cs_wave_size == 32)
hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
if (device->physical_device->ps_wave_size == 32)
hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
if (device->physical_device->ge_wave_size == 32)
hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
return hash_flags;
}
@@ -1788,7 +1782,7 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
/* Round up towards full wave sizes for better ALU utilization. */
if (!max_vert_out_per_gs_instance) {
const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
const unsigned wavesize = 64;
unsigned orig_max_esverts;
unsigned orig_max_gsprims;
do {
@@ -2320,7 +2314,6 @@ radv_fill_shader_keys(struct radv_device *device,
}
if (device->physical_device->rad_info.chip_class >= GFX10 &&
device->physical_device->rad_info.family != CHIP_NAVI14 &&
!(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
@@ -2340,26 +2333,6 @@ radv_fill_shader_keys(struct radv_device *device,
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
}
/*
* Disable NGG with geometry shaders. There are a bunch of
* issues still:
* * GS primitives in pipeline statistic queries do not get
* updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
* * dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom* failures
* * Interactions with tessellation failing:
* dEQP-VK.tessellation.geometry_interaction.passthrough.tessellate_isolines_passthrough_geometry_no_change
* * General issues with the last primitive missing/corrupt:
* https://bugs.freedesktop.org/show_bug.cgi?id=111248
*
* Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
*/
if (nir[MESA_SHADER_GEOMETRY]) {
if (nir[MESA_SHADER_TESS_CTRL])
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
else
keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
}
/* TODO: Implement streamout support for NGG. */
gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
@@ -2480,7 +2453,6 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
unsigned char hash[20], gs_copy_hash[20];
bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
radv_start_feedback(pipeline_feedback);
@@ -2501,15 +2473,14 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
gs_copy_hash[0] ^= 1;
bool found_in_application_cache = true;
if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
if (modules[MESA_SHADER_GEOMETRY]) {
struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
&found_in_application_cache);
pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
}
if (!keep_executable_info &&
radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
&found_in_application_cache) &&
(!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
radv_stop_feedback(pipeline_feedback, found_in_application_cache);
@@ -2557,12 +2528,12 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (nir[i]) {
NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
nir_lower_non_uniform_ubo_access |
nir_lower_non_uniform_ssbo_access |
nir_lower_non_uniform_texture_access |
nir_lower_non_uniform_image_access);
NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
}
if (radv_can_dump_shader(device, modules[i], false))
@@ -2578,7 +2549,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
pipeline->shaders[MESA_SHADER_FRAGMENT] =
radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
pipeline->layout, keys + MESA_SHADER_FRAGMENT,
keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
&binaries[MESA_SHADER_FRAGMENT]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
}
@@ -2608,8 +2579,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
pipeline->layout,
&key, keep_executable_info,
&binaries[MESA_SHADER_TESS_CTRL]);
&key, &binaries[MESA_SHADER_TESS_CTRL]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
}
@@ -2627,8 +2597,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
pipeline->layout,
&keys[pre_stage], keep_executable_info,
&binaries[MESA_SHADER_GEOMETRY]);
&keys[pre_stage] , &binaries[MESA_SHADER_GEOMETRY]);
radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
}
@@ -2649,8 +2618,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
pipeline->layout,
keys + i, keep_executable_info,
&binaries[i]);
keys + i, &binaries[i]);
radv_stop_feedback(stage_feedbacks[i], false);
}
@@ -2662,11 +2630,10 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
!radv_pipeline_has_ngg(pipeline)) {
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
keep_executable_info,
keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
}
if (!keep_executable_info && pipeline->gs_copy_shader) {
if (pipeline->gs_copy_shader) {
struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
@@ -2681,15 +2648,14 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
free(gs_copy_binary);
}
if (!keep_executable_info) {
radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
binaries);
}
radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
binaries);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(binaries[i]);
if (nir[i]) {
ralloc_free(nir[i]);
if (!pipeline->device->keep_shader_info)
ralloc_free(nir[i]);
if (radv_can_dump_shader_stats(device, modules[i]))
radv_shader_dump_stats(device,
@@ -3211,10 +3177,8 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
persistent_states_per_bin = 1;
fpovs_per_batch = 63;
} else {
/* The context states are affected by the scissor bug. */
context_states_per_bin = pipeline->device->physical_device->has_scissor_bug ? 1 : 6;
/* 32 causes hangs for RAVEN. */
persistent_states_per_bin = 16;
context_states_per_bin = 6;
persistent_states_per_bin = 32;
fpovs_per_batch = 63;
}
@@ -3833,14 +3797,6 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
else
radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
tess->ls_hs_config);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
!radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
S_028A44_ES_VERTS_PER_SUBGRP(250) |
S_028A44_GS_PRIMS_PER_SUBGRP(126) |
S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
}
}
static void
@@ -4104,8 +4060,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
ps->config.spi_ps_input_addr);
radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
S_0286D8_NUM_INTERP(ps->info.fs.num_interp) |
S_0286D8_PS_W32_EN(ps->info.info.wave_size == 32));
S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
@@ -4169,30 +4124,6 @@ radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
if (radv_pipeline_has_tess(pipeline))
hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.wave_size;
if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.wave_size;
if (pipeline->gs_copy_shader)
vs_size = pipeline->gs_copy_shader->info.info.wave_size;
} else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.info.wave_size;
else if (pipeline->shaders[MESA_SHADER_VERTEX])
vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.info.wave_size;
if (radv_pipeline_has_ngg(pipeline))
gs_size = vs_size;
/* legacy GS only supports Wave64 */
stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
}
return stages;
}
@@ -4811,325 +4742,3 @@ VkResult radv_CreateComputePipelines(
return result;
}
static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
{
uint32_t ret = 0;
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!pipeline->shaders[i])
continue;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(pipeline)) {
ret += 2u;
} else {
ret += 1u;
}
}
return ret;
}
static struct radv_shader_variant *
radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
{
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!pipeline->shaders[i])
continue;
if (!index) {
*stage = i;
return pipeline->shaders[i];
}
--index;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(pipeline)) {
if (!index) {
*stage = i;
return pipeline->gs_copy_shader;
}
--index;
}
}
*stage = -1;
return NULL;
}
/* Basically strlcpy (which does not exist on linux) specialized for
* descriptions. */
static void desc_copy(char *desc, const char *src) {
int len = strlen(src);
assert(len < VK_MAX_DESCRIPTION_SIZE);
memcpy(desc, src, len);
memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
}
VkResult radv_GetPipelineExecutablePropertiesKHR(
VkDevice _device,
const VkPipelineInfoKHR* pPipelineInfo,
uint32_t* pExecutableCount,
VkPipelineExecutablePropertiesKHR* pProperties)
{
RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
const uint32_t total_count = radv_get_executable_count(pipeline);
if (!pProperties) {
*pExecutableCount = total_count;
return VK_SUCCESS;
}
const uint32_t count = MIN2(total_count, *pExecutableCount);
for (unsigned i = 0, executable_idx = 0;
i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
if (!pipeline->shaders[i])
continue;
pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
const char *name = NULL;
const char *description = NULL;
switch(i) {
case MESA_SHADER_VERTEX:
name = "Vertex Shader";
description = "Vulkan Vertex Shader";
break;
case MESA_SHADER_TESS_CTRL:
if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
name = "Vertex + Tessellation Control Shaders";
description = "Combined Vulkan Vertex and Tessellation Control Shaders";
} else {
name = "Tessellation Control Shader";
description = "Vulkan Tessellation Control Shader";
}
break;
case MESA_SHADER_TESS_EVAL:
name = "Tessellation Evaluation Shader";
description = "Vulkan Tessellation Evaluation Shader";
break;
case MESA_SHADER_GEOMETRY:
if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
name = "Tessellation Evaluation + Geometry Shaders";
description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
} else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
name = "Vertex + Geometry Shader";
description = "Combined Vulkan Vertex and Geometry Shaders";
} else {
name = "Geometry Shader";
description = "Vulkan Geometry Shader";
}
break;
case MESA_SHADER_FRAGMENT:
name = "Fragment Shader";
description = "Vulkan Fragment Shader";
break;
case MESA_SHADER_COMPUTE:
name = "Compute Shader";
description = "Vulkan Compute Shader";
break;
}
desc_copy(pProperties[executable_idx].name, name);
desc_copy(pProperties[executable_idx].description, description);
++executable_idx;
if (i == MESA_SHADER_GEOMETRY &&
!radv_pipeline_has_ngg(pipeline)) {
assert(pipeline->gs_copy_shader);
if (executable_idx >= count)
break;
pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
desc_copy(pProperties[executable_idx].description,
"Extra shader stage that loads the GS output ringbuffer into the rasterizer");
++executable_idx;
}
}
for (unsigned i = 0; i < count; ++i)
pProperties[i].subgroupSize = 64;
VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
*pExecutableCount = count;
return result;
}
VkResult radv_GetPipelineExecutableStatisticsKHR(
VkDevice _device,
const VkPipelineExecutableInfoKHR* pExecutableInfo,
uint32_t* pStatisticCount,
VkPipelineExecutableStatisticKHR* pStatistics)
{
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
gl_shader_stage stage;
struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
unsigned max_waves = radv_get_max_waves(device, shader, stage);
VkPipelineExecutableStatisticKHR *s = pStatistics;
VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
VkResult result = VK_SUCCESS;
if (s < end) {
desc_copy(s->name, "SGPRs");
desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.num_sgprs;
}
++s;
if (s < end) {
desc_copy(s->name, "VGPRs");
desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.num_vgprs;
}
++s;
if (s < end) {
desc_copy(s->name, "Spilled SGPRs");
desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.spilled_sgprs;
}
++s;
if (s < end) {
desc_copy(s->name, "Spilled VGPRs");
desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.spilled_vgprs;
}
++s;
if (s < end) {
desc_copy(s->name, "PrivMem VGPRs");
desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->info.private_mem_vgprs;
}
++s;
if (s < end) {
desc_copy(s->name, "Code size");
desc_copy(s->description, "Code size in bytes");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->code_size;
}
++s;
if (s < end) {
desc_copy(s->name, "LDS size");
desc_copy(s->description, "LDS size in bytes per workgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.lds_size * lds_increment;
}
++s;
if (s < end) {
desc_copy(s->name, "Scratch size");
desc_copy(s->description, "Private memory in bytes per subgroup");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = shader->config.scratch_bytes_per_wave;
}
++s;
if (s < end) {
desc_copy(s->name, "Subgroups per SIMD");
desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
s->value.u64 = max_waves;
}
++s;
if (!pStatistics)
*pStatisticCount = s - pStatistics;
else if (s > end) {
*pStatisticCount = end - pStatistics;
result = VK_INCOMPLETE;
} else {
*pStatisticCount = s - pStatistics;
}
return result;
}
static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
{
size_t total_size = strlen(src) + 1;
if (!data) {
*data_size = total_size;
return VK_SUCCESS;
}
size_t size = MIN2(total_size, *data_size);
memcpy(data, src, size);
if (size)
*((char*)data + size - 1) = 0;
return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
}
VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
VkDevice device,
const VkPipelineExecutableInfoKHR* pExecutableInfo,
uint32_t* pInternalRepresentationCount,
VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
{
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
gl_shader_stage stage;
struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
VkResult result = VK_SUCCESS;
/* optimized NIR */
if (p < end) {
p->isText = true;
desc_copy(p->name, "NIR Shader(s)");
desc_copy(p->description, "The optimized NIR shader(s)");
if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
result = VK_INCOMPLETE;
}
++p;
/* LLVM IR */
if (p < end) {
p->isText = true;
desc_copy(p->name, "LLVM IR");
desc_copy(p->description, "The LLVM IR after some optimizations");
if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
result = VK_INCOMPLETE;
}
++p;
/* Disassembler */
if (p < end) {
p->isText = true;
desc_copy(p->name, "Assembly");
desc_copy(p->description, "Final Assembly");
if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
result = VK_INCOMPLETE;
}
++p;
if (!pInternalRepresentations)
*pInternalRepresentationCount = p - pInternalRepresentations;
else if(p > end) {
result = VK_INCOMPLETE;
*pInternalRepresentationCount = end - pInternalRepresentations;
} else {
*pInternalRepresentationCount = p - pInternalRepresentations;
}
return result;
}

View File

@@ -59,7 +59,8 @@ radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
* cache. Disable caching when we want to keep shader debug info, since
* we don't get the debug info on cached shaders. */
if (cache->hash_table == NULL ||
(device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
(device->instance->debug_flags & RADV_DEBUG_NO_CACHE) ||
device->keep_shader_info)
cache->table_size = 0;
else
memset(cache->hash_table, 0, byte_size);
@@ -240,7 +241,8 @@ radv_is_cache_disabled(struct radv_device *device)
/* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
* MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
*/
return (device->instance->debug_flags & RADV_DEBUG_NO_CACHE);
return (device->instance->debug_flags & RADV_DEBUG_NO_CACHE) ||
device->keep_shader_info;
}
bool
@@ -306,7 +308,7 @@ radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
memcpy(binary, p, entry->binary_sizes[i]);
p += entry->binary_sizes[i];
entry->variants[i] = radv_shader_variant_create(device, binary, false);
entry->variants[i] = radv_shader_variant_create(device, binary);
free(binary);
} else if (entry->binary_sizes[i]) {
p += entry->binary_sizes[i];

View File

@@ -206,7 +206,6 @@ radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
* propagating errors. Might be useful to plug in a stack trace here.
*/
struct radv_image_view;
struct radv_instance;
VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
@@ -303,9 +302,7 @@ struct radv_physical_device {
bool has_dcc_constant_encode;
/* Number of threads per wave. */
uint8_t ps_wave_size;
uint8_t cs_wave_size;
uint8_t ge_wave_size;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
@@ -329,9 +326,6 @@ struct radv_instance {
int physicalDeviceCount;
struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
char * engineName;
uint32_t engineVersion;
uint64_t debug_flags;
uint64_t perftest_flags;
@@ -465,7 +459,7 @@ struct radv_meta_state {
VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
} clear[MAX_SAMPLES_LOG2];
} clear[1 + MAX_SAMPLES_LOG2];
VkPipelineLayout clear_color_p_layout;
VkPipelineLayout clear_depth_p_layout;
@@ -508,7 +502,7 @@ struct radv_meta_state {
VkPipeline depth_only_pipeline[5];
VkPipeline stencil_only_pipeline[5];
} blit2d[MAX_SAMPLES_LOG2];
} blit2d[1 + MAX_SAMPLES_LOG2];
VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
@@ -613,7 +607,7 @@ struct radv_meta_state {
VkPipeline decompress_pipeline;
VkPipeline resummarize_pipeline;
VkRenderPass pass;
} depth_decomp[MAX_SAMPLES_LOG2];
} depth_decomp[1 + MAX_SAMPLES_LOG2];
struct {
VkPipelineLayout p_layout;
@@ -754,9 +748,6 @@ struct radv_device {
struct radv_device_extension_table enabled_extensions;
/* Whether the app has enabled the robustBufferAccess feature. */
bool robust_buffer_access;
/* Whether the driver uses a global BO list. */
bool use_global_bo_list;
@@ -1043,54 +1034,6 @@ radv_get_debug_option_name(int id);
const char *
radv_get_perftest_option_name(int id);
struct radv_color_buffer_info {
uint64_t cb_color_base;
uint64_t cb_color_cmask;
uint64_t cb_color_fmask;
uint64_t cb_dcc_base;
uint32_t cb_color_slice;
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
uint32_t cb_color_attrib2; /* GFX9 and later */
uint32_t cb_color_attrib3; /* GFX10 and later */
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
union {
uint32_t cb_color_pitch; // GFX6-GFX8
uint32_t cb_mrt_epitch; // GFX9+
};
};
struct radv_ds_buffer_info {
uint64_t db_z_read_base;
uint64_t db_stencil_read_base;
uint64_t db_z_write_base;
uint64_t db_stencil_write_base;
uint64_t db_htile_data_base;
uint32_t db_depth_info;
uint32_t db_z_info;
uint32_t db_stencil_info;
uint32_t db_depth_view;
uint32_t db_depth_size;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
uint32_t pa_su_poly_offset_db_fmt_cntl;
uint32_t db_z_info2; /* GFX9 only */
uint32_t db_stencil_info2; /* GFX9 only */
float offset_scale;
};
void
radv_initialise_color_surface(struct radv_device *device,
struct radv_color_buffer_info *cb,
struct radv_image_view *iview);
void
radv_initialise_ds_surface(struct radv_device *device,
struct radv_ds_buffer_info *ds,
struct radv_image_view *iview);
/**
* Attachment state when recording a renderpass instance.
*
@@ -1101,14 +1044,7 @@ struct radv_attachment_state {
uint32_t cleared_views;
VkClearValue clear_value;
VkImageLayout current_layout;
bool current_in_render_loop;
struct radv_sample_locations_state sample_location;
union {
struct radv_color_buffer_info cb;
struct radv_ds_buffer_info ds;
};
struct radv_image_view *iview;
};
struct radv_descriptor_state {
@@ -1426,9 +1362,6 @@ struct radv_shader_module;
#define RADV_HASH_SHADER_SISCHED (1 << 1)
#define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
#define RADV_HASH_SHADER_NO_NGG (1 << 3)
#define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
#define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
#define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
void
radv_hash_shaders(unsigned char *hash,
@@ -1614,6 +1547,27 @@ bool radv_dcc_formats_compatible(VkFormat format1,
VkFormat format2);
bool radv_device_supports_etc(struct radv_physical_device *physical_device);
struct radv_fmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
unsigned pitch_in_pixels;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
unsigned tile_swizzle;
uint64_t slice_size;
};
struct radv_cmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
unsigned slice_size;
};
struct radv_image_plane {
VkFormat format;
struct radeon_surf surface;
@@ -1647,8 +1601,8 @@ struct radv_image {
bool tc_compatible_htile;
bool tc_compatible_cmask;
uint64_t cmask_offset;
uint64_t fmask_offset;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
uint64_t clear_value_offset;
uint64_t fce_pred_offset;
uint64_t dcc_pred_offset;
@@ -1672,7 +1626,6 @@ struct radv_image {
* the image. */
bool radv_layout_has_htile(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask);
/* Whether the image has a htile that is known consistent with the contents of
@@ -1683,18 +1636,14 @@ bool radv_layout_has_htile(const struct radv_image *image,
*/
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask);
bool radv_layout_can_fast_clear(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask);
bool radv_layout_dcc_compressed(const struct radv_device *device,
const struct radv_image *image,
bool radv_layout_dcc_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask);
/**
@@ -1703,7 +1652,7 @@ bool radv_layout_dcc_compressed(const struct radv_device *device,
static inline bool
radv_image_has_cmask(const struct radv_image *image)
{
return image->cmask_offset;
return image->cmask.size;
}
/**
@@ -1712,7 +1661,7 @@ radv_image_has_cmask(const struct radv_image *image)
static inline bool
radv_image_has_fmask(const struct radv_image *image)
{
return image->fmask_offset;
return image->fmask.size;
}
/**
@@ -1882,8 +1831,6 @@ VkResult radv_image_create(VkDevice _device,
const VkAllocationCallbacks* alloc,
VkImage *pImage);
bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
VkResult
radv_image_from_gralloc(VkDevice device_h,
const VkImageCreateInfo *base_info,
@@ -1891,14 +1838,9 @@ radv_image_from_gralloc(VkDevice device_h,
const VkAllocationCallbacks *alloc,
VkImage *out_image_h);
struct radv_image_view_extra_create_info {
bool disable_compression;
};
void radv_image_view_init(struct radv_image_view *view,
struct radv_device *device,
const VkImageViewCreateInfo *pCreateInfo,
const struct radv_image_view_extra_create_info* extra_create_info);
const VkImageViewCreateInfo* pCreateInfo);
VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
@@ -1969,13 +1911,60 @@ struct radv_sampler {
struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
};
struct radv_color_buffer_info {
uint64_t cb_color_base;
uint64_t cb_color_cmask;
uint64_t cb_color_fmask;
uint64_t cb_dcc_base;
uint32_t cb_color_slice;
uint32_t cb_color_view;
uint32_t cb_color_info;
uint32_t cb_color_attrib;
uint32_t cb_color_attrib2; /* GFX9 and later */
uint32_t cb_color_attrib3; /* GFX10 and later */
uint32_t cb_dcc_control;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
union {
uint32_t cb_color_pitch; // GFX6-GFX8
uint32_t cb_mrt_epitch; // GFX9+
};
};
struct radv_ds_buffer_info {
uint64_t db_z_read_base;
uint64_t db_stencil_read_base;
uint64_t db_z_write_base;
uint64_t db_stencil_write_base;
uint64_t db_htile_data_base;
uint32_t db_depth_info;
uint32_t db_z_info;
uint32_t db_stencil_info;
uint32_t db_depth_view;
uint32_t db_depth_size;
uint32_t db_depth_slice;
uint32_t db_htile_surface;
uint32_t pa_su_poly_offset_db_fmt_cntl;
uint32_t db_z_info2; /* GFX9 only */
uint32_t db_stencil_info2; /* GFX9 only */
float offset_scale;
};
struct radv_attachment_info {
union {
struct radv_color_buffer_info cb;
struct radv_ds_buffer_info ds;
};
struct radv_image_view *attachment;
};
struct radv_framebuffer {
uint32_t width;
uint32_t height;
uint32_t layers;
uint32_t attachment_count;
struct radv_image_view *attachments[0];
struct radv_attachment_info attachments[0];
};
struct radv_subpass_barrier {
@@ -1990,7 +1979,6 @@ void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
struct radv_subpass_attachment {
uint32_t attachment;
VkImageLayout layout;
bool in_render_loop;
};
struct radv_subpass {

View File

@@ -1124,11 +1124,10 @@ VkResult radv_GetQueryPoolResults(
switch (pool->type) {
case VK_QUERY_TYPE_TIMESTAMP: {
volatile uint64_t const *src64 = (volatile uint64_t const *)src;
available = *src64 != TIMESTAMP_NOT_READY;
available = *(uint64_t *)src != TIMESTAMP_NOT_READY;
if (flags & VK_QUERY_RESULT_WAIT_BIT) {
while (*src64 == TIMESTAMP_NOT_READY)
while (*(volatile uint64_t *)src == TIMESTAMP_NOT_READY)
;
available = true;
}
@@ -1138,11 +1137,11 @@ VkResult radv_GetQueryPoolResults(
if (flags & VK_QUERY_RESULT_64_BIT) {
if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
*(uint64_t*)dest = *src64;
*(uint64_t*)dest = *(uint64_t*)src;
dest += 8;
} else {
if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
*(uint32_t*)dest = *(volatile uint32_t*)src;
*(uint32_t*)dest = *(uint32_t*)src;
dest += 4;
}
break;
@@ -1190,13 +1189,13 @@ VkResult radv_GetQueryPoolResults(
if (flags & VK_QUERY_RESULT_WAIT_BIT)
while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
;
available = *(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
result = VK_NOT_READY;
const volatile uint64_t *start = (uint64_t*)src;
const volatile uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
const uint64_t *start = (uint64_t*)src;
const uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
if (flags & VK_QUERY_RESULT_64_BIT) {
uint64_t *dst = (uint64_t*)dest;
dest += util_bitcount(pool->pipeline_stats_mask) * 8;

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