VERSION: bump version for 19.3.1

Now that the .0 is done, we shouldn't have any more new features added
to the branch

VERSION

@@ -1 +1 @@
-19.3.0-rc6
+19.3.1

bin/.cherry-ignore

@@ -1,6 +1,11 @@
 # This is reverted shortly after landing
 4432a2d14d80081d062f7939a950d65ea3a16eed
 
-# This was manually backported
+# These were manually backported
 21be5c8edd3ad156f6cbfbceb96e7939716d9f2c
 4b392ced2d744fccffe95490ff57e6b41033c266
+b6905438514ae4de0b7f85c861e3d811ddaadda9
+
+# This isn't worth the effort to backport, as it only affects build with
+# asserts enable, which hopefully wont happen in a stable branch.
+937b9055698be0dfdb7d2e0673a989e2ecc05912

docs/relnotes/new_features.txt

@@ -1,20 +0,0 @@
-GL_ARB_gl_spirv on i965, iris.
-GL_ARB_spirv_extensions on i965, iris.
-GL_EXT_demote_to_helper_invocation on iris, i965.
-OpenGL 4.6 on i965, iris.
-EGL_EXT_image_flush_external
-VK_ANDROID_external_memory_android_hardware_buffer on RADV.
-VK_KHR_shader_clock on Intel, RADV.
-VK_KHR_shader_float_controls on Intel, RADV.
-VK_KHR_spirv_1_4 on Intel, RADV.
-VK_KHR_timeline_semaphore on RADV.
-VK_KHR_vulkan_memory_model on Intel.
-VK_EXT_shader_subgroup_ballot on Intel.
-VK_EXT_shader_subgroup_vote on Intel.
-VK_EXT_texel_buffer_alignment on RADV.
-VK_INTEL_performance_query on Intel.
-Meson support for windows using MSVC and MinGW
-scons has been deprecated for non windows
-Initial Intel gen12 (Tigerlake) support on anvil and iris
-New compiler backend "ACO" for RADV (RADV_PERFTEST=aco)
-VK_EXT_shader_demote_to_helper_invocation on RADV/ACO.

include/EGL/eglext.h

@@ -1362,6 +1362,20 @@ EGLAPI EGLuint64NV EGLAPIENTRY eglGetSystemTimeNV (void);
 #define EGL_NATIVE_SURFACE_TIZEN          0x32A1
 #endif /* EGL_TIZEN_image_native_surface */
 
+#ifndef EGL_EXT_image_flush_external
+#define EGL_EXT_image_flush_external 1
+#define EGL_IMAGE_EXTERNAL_FLUSH_EXT 0x32A2
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLIMAGEFLUSHEXTERNALEXTPROC) (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLIMAGEINVALIDATEEXTERNALEXTPROC) (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLBoolean EGLAPIENTRY eglImageFlushExternalEXT (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
+EGLAPI EGLBoolean EGLAPIENTRY eglImageInvalidateExternalEXT (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
+#endif
+#endif /* EGL_EXT_image_flush_external */
+
+#include <EGL/eglmesaext.h>
+#include <EGL/eglextchromium.h>
+
 #ifdef __cplusplus
 }
 #endif

include/EGL/eglextchromium.h

@@ -53,17 +53,6 @@ typedef EGLBoolean (EGLAPIENTRYP PFNEGLGETSYNCVALUESCHROMIUMPROC)
 #endif
 #endif
 
-#ifndef EGL_EXT_image_flush_external
-#define EGL_EXT_image_flush_external 1
-#define EGL_IMAGE_EXTERNAL_FLUSH_EXT 0x32A2
-typedef EGLBoolean (EGLAPIENTRYP PFNEGLIMAGEFLUSHEXTERNALEXTPROC) (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
-typedef EGLBoolean (EGLAPIENTRYP PFNEGLIMAGEINVALIDATEEXTERNALEXTPROC) (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
-#ifdef EGL_EGLEXT_PROTOTYPES
-EGLAPI EGLBoolean EGLAPIENTRY eglImageFlushExternalEXT (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
-EGLAPI EGLBoolean EGLAPIENTRY eglImageInvalidateExternalEXT (EGLDisplay dpy, EGLImageKHR image, const EGLAttrib *attrib_list);
-#endif
-#endif /* EGL_EXT_image_flush_external */
-
 #ifdef __cplusplus
 }
 #endif

include/GL/internal/dri_interface.h

@@ -1343,6 +1343,7 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_UYVY         0x1013
 #define __DRI_IMAGE_FORMAT_XBGR16161616F 0x1014
 #define __DRI_IMAGE_FORMAT_ABGR16161616F 0x1015
+#define __DRI_IMAGE_FORMAT_SXRGB8       0x1016
 
 #define __DRI_IMAGE_USE_SHARE		0x0001
 #define __DRI_IMAGE_USE_SCANOUT		0x0002
@@ -1370,6 +1371,7 @@ struct __DRIdri2ExtensionRec {
 
 #define __DRI_IMAGE_FOURCC_SARGB8888	0x83324258
 #define __DRI_IMAGE_FOURCC_SABGR8888	0x84324258
+#define __DRI_IMAGE_FOURCC_SXRGB8888	0x85324258
 
 /**
  * Queryable on images created by createImageFromNames.

src/amd/common/ac_surface.c

@@ -344,7 +344,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 	    surf_level->mode == RADEON_SURF_MODE_2D &&
 	    level == 0 &&
 	    !(surf->flags & RADEON_SURF_NO_HTILE)) {
-		AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
+		AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
 		AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 		AddrHtileIn->height = AddrSurfInfoOut->height;
 		AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
@@ -779,19 +779,12 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 			if (level > 0)
 				continue;
 
-			/* Check that we actually got a TC-compatible HTILE if
-			 * we requested it (only for level 0, since we're not
-			 * supporting HTILE on higher mip levels anyway). */
-			assert(AddrSurfInfoOut.tcCompatible ||
-			       !AddrSurfInfoIn.flags.tcCompatible ||
-			       AddrSurfInfoIn.flags.matchStencilTileCfg);
+			if (!AddrSurfInfoOut.tcCompatible) {
+				AddrSurfInfoIn.flags.tcCompatible = 0;
+				surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
+			}
 
 			if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
-				if (!AddrSurfInfoOut.tcCompatible) {
-					AddrSurfInfoIn.flags.tcCompatible = 0;
-					surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
-				}
-
 				AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
 				AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
 				stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;

src/amd/llvm/ac_nir_to_llvm.c

@@ -3713,11 +3713,21 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 		break;
 	}
 	case nir_intrinsic_load_constant: {
+		unsigned base = nir_intrinsic_base(instr);
+		unsigned range = nir_intrinsic_range(instr);
+
 		LLVMValueRef offset = get_src(ctx, instr->src[0]);
-		LLVMValueRef base = LLVMConstInt(ctx->ac.i32,
-						 nir_intrinsic_base(instr),
-						 false);
-		offset = LLVMBuildAdd(ctx->ac.builder, offset, base, "");
+		offset = LLVMBuildAdd(ctx->ac.builder, offset,
+				      LLVMConstInt(ctx->ac.i32, base, false), "");
+
+		/* Clamp the offset to avoid out-of-bound access because global
+		 * instructions can't handle them.
+		 */
+		LLVMValueRef size = LLVMConstInt(ctx->ac.i32, base + range, false);
+		LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
+						  offset, size, "");
+		offset = LLVMBuildSelect(ctx->ac.builder, cond, offset, size, "");
+
 		LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->constant_data,
 						 offset);
 		LLVMTypeRef comp_type =

src/amd/vulkan/radv_android.c

@@ -392,8 +392,8 @@ vk_format_from_android(unsigned android_format, unsigned android_usage)
 {
 	switch (android_format) {
 	case AHARDWAREBUFFER_FORMAT_R8G8B8A8_UNORM:
-		return VK_FORMAT_R8G8B8A8_UNORM;
 	case AHARDWAREBUFFER_FORMAT_R8G8B8X8_UNORM:
+		return VK_FORMAT_R8G8B8A8_UNORM;
 	case AHARDWAREBUFFER_FORMAT_R8G8B8_UNORM:
 		return VK_FORMAT_R8G8B8_UNORM;
 	case AHARDWAREBUFFER_FORMAT_R5G6B5_UNORM:

src/amd/vulkan/radv_device.c

@@ -1985,8 +1985,16 @@ static int install_seccomp_filter() {
 		BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
 
 		/* Futex is required for mutex locks */
+		#if defined __NR__newselect
+		BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
+		BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
+		#elif defined __NR_select
 		BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
 		BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
+		#else
+		BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
+		BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
+		#endif
 
 		/* Allow system exit calls for the forked process */
 		BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),

src/broadcom/cle/meson.build

@@ -58,6 +58,6 @@ libbroadcom_cle = static_library(
   'v3d_decoder.c',
   include_directories : [inc_common, inc_broadcom],
   c_args : [c_vis_args, no_override_init_args],
-  dependencies : [dep_libdrm, dep_valgrind],
+  dependencies : [dep_libdrm, dep_valgrind, dep_expat, dep_zlib],
   build_by_default : false,
 )

src/compiler/glsl/gl_nir_linker.c

@@ -34,32 +34,11 @@
  */
 
 static bool
-add_interface_variables(const struct gl_context *cts,
-                        struct gl_shader_program *prog,
-                        struct set *resource_set,
-                        unsigned stage, GLenum programInterface)
+add_vars_from_list(const struct gl_context *ctx,
+                   struct gl_shader_program *prog, struct set *resource_set,
+                   const struct exec_list *var_list, unsigned stage,
+                   GLenum programInterface)
 {
-   const struct exec_list *var_list = NULL;
-
-   struct gl_linked_shader *sh = prog->_LinkedShaders[stage];
-   if (!sh)
-      return true;
-
-   nir_shader *nir = sh->Program->nir;
-   assert(nir);
-
-   switch (programInterface) {
-   case GL_PROGRAM_INPUT:
-      var_list = &nir->inputs;
-      break;
-   case GL_PROGRAM_OUTPUT:
-      var_list = &nir->outputs;
-      break;
-   default:
-      assert("!Should not get here");
-      break;
-   }
-
    nir_foreach_variable(var, var_list) {
       if (var->data.how_declared == nir_var_hidden)
          continue;
@@ -108,6 +87,38 @@ add_interface_variables(const struct gl_context *cts,
    return true;
 }
 
+static bool
+add_interface_variables(const struct gl_context *ctx,
+                        struct gl_shader_program *prog,
+                        struct set *resource_set,
+                        unsigned stage, GLenum programInterface)
+{
+   struct gl_linked_shader *sh = prog->_LinkedShaders[stage];
+   if (!sh)
+      return true;
+
+   nir_shader *nir = sh->Program->nir;
+   assert(nir);
+
+   switch (programInterface) {
+   case GL_PROGRAM_INPUT: {
+      bool result = add_vars_from_list(ctx, prog, resource_set,
+                                       &nir->inputs, stage, programInterface);
+      result &= add_vars_from_list(ctx, prog, resource_set, &nir->system_values,
+                                   stage, programInterface);
+      return result;
+   }
+   case GL_PROGRAM_OUTPUT:
+      return add_vars_from_list(ctx, prog, resource_set, &nir->outputs, stage,
+                                programInterface);
+   default:
+      assert("!Should not get here");
+      break;
+   }
+
+   return false;
+}
+
 /* TODO: as we keep adding features, this method is becoming more and more
  * similar to its GLSL counterpart at linker.cpp. Eventually it would be good
  * to check if they could be refactored, and reduce code duplication somehow

src/compiler/nir/nir_lower_clip.c

@@ -316,6 +316,17 @@ nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables, bool use_vars,
    if (!ucp_enables)
       return false;
 
+   /* find clipvertex/position outputs: */
+   nir_foreach_variable(var, &shader->outputs) {
+      int loc = var->data.driver_location;
+
+      /* keep track of last used driver-location.. we'll be
+       * appending CLIP_DIST0/CLIP_DIST1 after last existing
+       * output:
+       */
+      maxloc = MAX2(maxloc, loc);
+   }
+
    nir_builder_init(&b, impl);
 
    /* NIR should ensure that, even in case of loops/if-else, there

src/egl/generate/gen_egl_dispatch.py

@@ -100,8 +100,6 @@ def generateHeader(functions):
 
     #include <EGL/egl.h>
     #include <EGL/eglext.h>
-    #include <EGL/eglmesaext.h>
-    #include <EGL/eglextchromium.h>
     #include "glvnd/libeglabi.h"
 
     """.lstrip("\n"))

src/egl/main/egltypedefs.h

@@ -33,8 +33,6 @@
 
 #include <EGL/egl.h>
 #include <EGL/eglext.h>
-#include <EGL/eglmesaext.h>
-#include <EGL/eglextchromium.h>
 
 #ifdef __cplusplus
 extern "C" {

src/gallium/auxiliary/Android.mk

@@ -77,3 +77,14 @@ LOCAL_GENERATED_SOURCES += $(MESA_GEN_NIR_H)
 
 include $(GALLIUM_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
+
+# Build libmesa_galliumvl used by radeonsi
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := \
+	$(VL_SOURCES)
+
+LOCAL_MODULE := libmesa_galliumvl
+
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

src/gallium/auxiliary/util/u_prim.h

@@ -338,7 +338,14 @@ u_stream_outputs_for_vertices(enum pipe_prim_type primitive, unsigned nr)
    /* Extraneous vertices don't contribute to stream outputs */
    u_trim_pipe_prim(primitive, &nr);
 
-   /* Consider how many primitives are actually generated */
+   /* Polygons are special, since they are a single primitive with many
+    * vertices. In this case, we just have an output for each vertex (after
+    * trimming) */
+
+   if (primitive == PIPE_PRIM_POLYGON)
+      return nr;
+
+   /* Normally, consider how many primitives are actually generated */
    unsigned prims = u_decomposed_prims_for_vertices(primitive, nr);
 
    /* One output per vertex after decomposition */

src/gallium/drivers/freedreno/a4xx/fd4_screen.c

@@ -60,9 +60,9 @@ fd4_screen_is_format_supported(struct pipe_screen *pscreen,
 	}
 
 	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+			(fd4_pipe2tex(format) != (enum a4xx_tex_fmt)~0) &&
 			(target == PIPE_BUFFER ||
-			 util_format_get_blocksize(format) != 12) &&
-			(fd4_pipe2tex(format) != (enum a4xx_tex_fmt)~0)) {
+			 util_format_get_blocksize(format) != 12)) {
 		retval |= PIPE_BIND_SAMPLER_VIEW;
 	}
 

src/gallium/drivers/freedreno/a5xx/fd5_screen.c

@@ -76,9 +76,9 @@ fd5_screen_is_format_supported(struct pipe_screen *pscreen,
 	}
 
 	if ((usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) &&
+			(fd5_pipe2tex(format) != (enum a5xx_tex_fmt)~0) &&
 			(target == PIPE_BUFFER ||
-			 util_format_get_blocksize(format) != 12) &&
-			(fd5_pipe2tex(format) != (enum a5xx_tex_fmt)~0)) {
+			 util_format_get_blocksize(format) != 12)) {
 		retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
 	}
 

src/gallium/drivers/freedreno/a6xx/fd6_screen.c

@@ -82,9 +82,9 @@ fd6_screen_is_format_supported(struct pipe_screen *pscreen,
 	}
 
 	if ((usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) &&
+			(fd6_pipe2tex(format) != (enum a6xx_tex_fmt)~0) &&
 			(target == PIPE_BUFFER ||
-			 util_format_get_blocksize(format) != 12) &&
-			(fd6_pipe2tex(format) != (enum a6xx_tex_fmt)~0)) {
+			 util_format_get_blocksize(format) != 12)) {
 		retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
 	}
 

src/gallium/drivers/iris/iris_bufmgr.c

@@ -1294,7 +1294,8 @@ iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
 }
 
 struct iris_bo *
-iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd)
+iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
+                      uint32_t tiling, uint32_t stride)
 {
    uint32_t handle;
    struct iris_bo *bo;
@@ -1345,9 +1346,15 @@ iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd)
    if (gen_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
       goto err;
 
-   bo->tiling_mode = get_tiling.tiling_mode;
-   bo->swizzle_mode = get_tiling.swizzle_mode;
-   /* XXX stride is unknown */
+   if (get_tiling.tiling_mode == tiling || tiling > I915_TILING_LAST) {
+      bo->tiling_mode = get_tiling.tiling_mode;
+      bo->swizzle_mode = get_tiling.swizzle_mode;
+       /* XXX stride is unknown */
+   } else {
+      if (bo_set_tiling_internal(bo, tiling, stride)) {
+         goto err;
+      }
+   }
 
 out:
    mtx_unlock(&bufmgr->lock);

src/gallium/drivers/iris/iris_bufmgr.h

@@ -352,7 +352,8 @@ int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 
 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
-struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd);
+struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
+                                      uint32_t tiling, uint32_t stride);
 
 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
 

src/gallium/drivers/iris/iris_resource.c

@@ -807,6 +807,8 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
       if (templ->usage == PIPE_USAGE_STAGING ||
           templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
          tiling_flags = ISL_TILING_LINEAR_BIT;
+      else if (templ->bind & PIPE_BIND_SCANOUT)
+         tiling_flags = ISL_TILING_X_BIT;
    }
 
    isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
@@ -960,12 +962,21 @@ iris_resource_from_handle(struct pipe_screen *pscreen,
    struct gen_device_info *devinfo = &screen->devinfo;
    struct iris_bufmgr *bufmgr = screen->bufmgr;
    struct iris_resource *res = iris_alloc_resource(pscreen, templ);
+   const struct isl_drm_modifier_info *mod_inf =
+	   isl_drm_modifier_get_info(whandle->modifier);
+   uint32_t tiling;
+
    if (!res)
       return NULL;
 
    switch (whandle->type) {
    case WINSYS_HANDLE_TYPE_FD:
-      res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
+      if (mod_inf)
+         tiling = isl_tiling_to_i915_tiling(mod_inf->tiling);
+      else
+         tiling = I915_TILING_LAST + 1;
+      res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
+                                      tiling, whandle->stride);
       break;
    case WINSYS_HANDLE_TYPE_SHARED:
       res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
@@ -979,12 +990,14 @@ iris_resource_from_handle(struct pipe_screen *pscreen,
 
    res->offset = whandle->offset;
 
-   uint64_t modifier = whandle->modifier;
-   if (modifier == DRM_FORMAT_MOD_INVALID) {
-      modifier = tiling_to_modifier(res->bo->tiling_mode);
+   if (mod_inf == NULL) {
+      mod_inf =
+         isl_drm_modifier_get_info(tiling_to_modifier(res->bo->tiling_mode));
    }
-   res->mod_info = isl_drm_modifier_get_info(modifier);
-   assert(res->mod_info);
+   assert(mod_inf);
+
+   res->external_format = whandle->format;
+   res->mod_info = mod_inf;
 
    isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
 
@@ -995,7 +1008,8 @@ iris_resource_from_handle(struct pipe_screen *pscreen,
    if (templ->target == PIPE_BUFFER) {
       res->surf.tiling = ISL_TILING_LINEAR;
    } else {
-      if (whandle->modifier == DRM_FORMAT_MOD_INVALID || whandle->plane == 0) {
+      /* Create a surface for each plane specified by the external format. */
+      if (whandle->plane < util_format_get_num_planes(whandle->format)) {
          UNUSED const bool isl_surf_created_successfully =
             isl_surf_init(&screen->isl_dev, &res->surf,
                           .dim = target_to_isl_surf_dim(templ->target),
@@ -1173,6 +1187,8 @@ iris_resource_get_handle(struct pipe_screen *pscreen,
       whandle->stride = res->surf.row_pitch_B;
       bo = res->bo;
    }
+
+   whandle->format = res->external_format;
    whandle->modifier =
       res->mod_info ? res->mod_info->modifier
                     : tiling_to_modifier(res->bo->tiling_mode);

src/gallium/drivers/iris/iris_resource.h

@@ -162,6 +162,13 @@ struct iris_resource {
       uint16_t has_hiz;
    } aux;
 
+   /**
+    * For external surfaces, this is format that was used to create or import
+    * the surface. For internal surfaces, this will always be
+    * PIPE_FORMAT_NONE.
+    */
+   enum pipe_format external_format;
+
    /**
     * For external surfaces, this is DRM format modifier that was used to
     * create or import the surface.  For internal surfaces, this will always

src/gallium/drivers/radeonsi/Android.mk

@@ -40,7 +40,9 @@ LOCAL_C_INCLUDES := \
 	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_amd_common,,)/common \
 	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_nir,,)/nir
 
-LOCAL_STATIC_LIBRARIES := libmesa_amd_common
+LOCAL_STATIC_LIBRARIES := \
+	libmesa_amd_common \
+	libmesa_galliumvl
 
 LOCAL_SHARED_LIBRARIES := libdrm_radeon
 LOCAL_MODULE := libmesa_pipe_radeonsi

src/gallium/drivers/radeonsi/si_texture.c

@@ -199,7 +199,8 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen,
 
 		/* Each texture is an array of slices. Each slice is an array
 		 * of mipmap levels. */
-		return box->z * tex->surface.u.gfx9.surf_slice_size +
+		return tex->surface.u.gfx9.surf_offset +
+		       box->z * tex->surface.u.gfx9.surf_slice_size +
 		       tex->surface.u.gfx9.offset[level] +
 		       (box->y / tex->surface.blk_h *
 			tex->surface.u.gfx9.surf_pitch +
@@ -1721,10 +1722,12 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 		tex->plane_index = i;
 		tex->num_planes = num_planes;
 
-		if (!last_plane)
+		if (!plane0) {
 			plane0 = last_plane = tex;
-		else
+		} else {
 			last_plane->buffer.b.b.next = &tex->buffer.b.b;
+			last_plane = tex;
+		}
 	}
 
 	return (struct pipe_resource *)plane0;

src/gallium/drivers/virgl/virgl_encode.c

@@ -492,12 +492,13 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
          if (virgl_debug & VIRGL_DEBUG_VERBOSE)
             debug_printf("Failed to translate shader in available space - trying again\n");
          old_size = str_total_size;
-         str_total_size = 65536 * ++retry_size;
+         str_total_size = 65536 * retry_size;
+         retry_size *= 2;
          str = REALLOC(str, old_size, str_total_size);
          if (!str)
             return -1;
       }
-   } while (bret == false && retry_size < 10);
+   } while (bret == false && retry_size < 1024);
 
    if (bret == false)
       return -1;

src/gallium/include/state_tracker/winsys_handle.h

@@ -49,6 +49,12 @@ struct winsys_handle
     */
    unsigned offset;
 
+   /**
+    * Input to resource_from_handle.
+    * Output from resource_get_handle.
+    */
+   uint64_t format;
+
    /**
     * Input to resource_from_handle.
     * Output from resource_get_handle.

src/gallium/state_trackers/dri/dri2.c

@@ -547,6 +547,7 @@ dri2_allocate_textures(struct dri_context *ctx,
          whandle.handle = buf->name;
          whandle.stride = buf->pitch;
          whandle.offset = 0;
+         whandle.format = format;
          whandle.modifier = DRM_FORMAT_MOD_INVALID;
          if (screen->can_share_buffer)
             whandle.type = WINSYS_HANDLE_TYPE_SHARED;
@@ -777,18 +778,12 @@ dri2_create_image_from_winsys(__DRIscreen *_screen,
    for (i = num_handles - 1; i >= 0; i--) {
       struct pipe_resource *tex;
 
-      if (whandle[i].modifier == DRM_FORMAT_MOD_INVALID) {
-         templ.width0 = width >> map->planes[i].width_shift;
-         templ.height0 = height >> map->planes[i].height_shift;
-         if (is_yuv)
-            templ.format = dri2_get_pipe_format_for_dri_format(map->planes[i].dri_format);
-         else
-            templ.format = map->pipe_format;
-      } else {
-         templ.width0 = width;
-         templ.height0 = height;
+      templ.width0 = width >> map->planes[i].width_shift;
+      templ.height0 = height >> map->planes[i].height_shift;
+      if (is_yuv)
+         templ.format = dri2_get_pipe_format_for_dri_format(map->planes[i].dri_format);
+      else
          templ.format = map->pipe_format;
-      }
       assert(templ.format != PIPE_FORMAT_NONE);
 
       tex = pscreen->resource_from_handle(pscreen,
@@ -826,6 +821,7 @@ dri2_create_image_from_name(__DRIscreen *_screen,
    memset(&whandle, 0, sizeof(whandle));
    whandle.type = WINSYS_HANDLE_TYPE_SHARED;
    whandle.handle = name;
+   whandle.format = map->pipe_format;
    whandle.modifier = DRM_FORMAT_MOD_INVALID;
 
    whandle.stride = pitch * util_format_get_blocksize(map->pipe_format);
@@ -844,8 +840,13 @@ dri2_create_image_from_name(__DRIscreen *_screen,
 }
 
 static unsigned
-dri2_get_modifier_num_planes(uint64_t modifier)
+dri2_get_modifier_num_planes(uint64_t modifier, int fourcc)
 {
+   const struct dri2_format_mapping *map = dri2_get_mapping_by_fourcc(fourcc);
+
+   if (!map)
+      return 0;
+
    switch (modifier) {
    case I915_FORMAT_MOD_Y_TILED_CCS:
       return 2;
@@ -867,8 +868,8 @@ dri2_get_modifier_num_planes(uint64_t modifier)
    /* FD_FORMAT_MOD_QCOM_TILED is not in drm_fourcc.h */
    case I915_FORMAT_MOD_X_TILED:
    case I915_FORMAT_MOD_Y_TILED:
-      return 1;
    case DRM_FORMAT_MOD_INVALID:
+      return map->nplanes;
    default:
       return 0;
    }
@@ -886,15 +887,13 @@ dri2_create_image_from_fd(__DRIscreen *_screen,
    __DRIimage *img = NULL;
    unsigned err = __DRI_IMAGE_ERROR_SUCCESS;
    int i, expected_num_fds;
-   uint64_t mod_planes = dri2_get_modifier_num_planes(modifier);
+   int num_handles = dri2_get_modifier_num_planes(modifier, fourcc);
 
-   if (!map || (modifier != DRM_FORMAT_MOD_INVALID && mod_planes == 0)) {
+   if (!map || num_handles == 0) {
       err = __DRI_IMAGE_ERROR_BAD_MATCH;
       goto exit;
    }
 
-   int num_handles = mod_planes > 0 ? mod_planes : map->nplanes;
-
    switch (fourcc) {
    case DRM_FORMAT_YUYV:
    case DRM_FORMAT_UYVY:
@@ -914,7 +913,7 @@ dri2_create_image_from_fd(__DRIscreen *_screen,
 
    for (i = 0; i < num_handles; i++) {
       int fdnum = i >= num_fds ? 0 : i;
-      int index = mod_planes > 0 ? i : map->planes[i].buffer_index;
+      int index = i >= map->nplanes ? i : map->planes[i].buffer_index;
       if (fds[fdnum] < 0) {
          err = __DRI_IMAGE_ERROR_BAD_ALLOC;
          goto exit;
@@ -924,6 +923,7 @@ dri2_create_image_from_fd(__DRIscreen *_screen,
       whandles[i].handle = (unsigned)fds[fdnum];
       whandles[i].stride = (unsigned)strides[index];
       whandles[i].offset = (unsigned)offsets[index];
+      whandles[i].format = map->pipe_format;
       whandles[i].modifier = modifier;
       whandles[i].plane = index;
    }
@@ -1314,6 +1314,7 @@ dri2_from_names(__DRIscreen *screen, int width, int height, int format,
    whandle.handle = names[0];
    whandle.stride = strides[0];
    whandle.offset = offsets[0];
+   whandle.format = map->pipe_format;
    whandle.modifier = DRM_FORMAT_MOD_INVALID;
 
    img = dri2_create_image_from_winsys(screen, width, height, map,
@@ -1411,7 +1412,7 @@ dri2_query_dma_buf_format_modifier_attribs(__DRIscreen *_screen,
 {
    switch (attrib) {
    case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT: {
-      uint64_t mod_planes = dri2_get_modifier_num_planes(modifier);
+      uint64_t mod_planes = dri2_get_modifier_num_planes(modifier, fourcc);
       if (mod_planes > 0)
          *value = mod_planes;
       return mod_planes > 0;

src/gallium/targets/dri/Android.mk

@@ -57,7 +57,8 @@ endif
 LOCAL_STATIC_LIBRARIES += \
 	libfreedreno_drm \
 	libfreedreno_ir3 \
-	libpanfrost_shared \
+	libmesa_gallium \
+	libpanfrost_shared
 
 ifeq ($(USE_LIBBACKTRACE),true)
 	LOCAL_SHARED_LIBRARIES += libbacktrace
@@ -75,7 +76,6 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
 	libmesa_nir \
 	libmesa_dri_common \
 	libmesa_megadriver_stub \
-	libmesa_gallium \
 	libmesa_pipe_loader \
 	libmesa_util \
 	libmesa_loader

src/intel/compiler/brw_eu_compact.c

@@ -1512,10 +1512,10 @@ has_immediate(const struct gen_device_info *devinfo, const brw_inst *inst,
 {
    if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
       *type = brw_inst_src0_type(devinfo, inst);
-      return *type != -1;
+      return *type != (enum brw_reg_type)-1;
    } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
       *type = brw_inst_src1_type(devinfo, inst);
-      return *type != -1;
+      return *type != (enum brw_reg_type)-1;
    }
 
    return false;

src/intel/perf/gen_perf.c

@@ -71,6 +71,8 @@
 #define MAP_READ  (1 << 0)
 #define MAP_WRITE (1 << 1)
 
+#define OA_REPORT_INVALID_CTX_ID (0xffffffff)
+
 /**
  * Periodic OA samples are read() into these buffer structures via the
  * i915 perf kernel interface and appended to the
@@ -1137,7 +1139,9 @@ gen_perf_query_result_accumulate(struct gen_perf_query_result *result,
 {
    int i, idx = 0;
 
-   result->hw_id = start[2];
+   if (result->hw_id == OA_REPORT_INVALID_CTX_ID &&
+       start[2] != OA_REPORT_INVALID_CTX_ID)
+      result->hw_id = start[2];
    result->reports_accumulated++;
 
    switch (query->oa_format) {
@@ -1175,7 +1179,7 @@ void
 gen_perf_query_result_clear(struct gen_perf_query_result *result)
 {
    memset(result, 0, sizeof(*result));
-   result->hw_id = 0xffffffff; /* invalid */
+   result->hw_id = OA_REPORT_INVALID_CTX_ID; /* invalid */
 }
 
 static void
@@ -1456,8 +1460,8 @@ get_free_sample_buf(struct gen_perf_context *perf_ctx)
 
       exec_node_init(&buf->link);
       buf->refcount = 0;
-      buf->len = 0;
    }
+   buf->len = 0;
 
    return buf;
 }
@@ -1974,7 +1978,8 @@ read_oa_samples_until(struct gen_perf_context *perf_ctx,
       exec_list_get_tail(&perf_ctx->sample_buffers);
    struct oa_sample_buf *tail_buf =
       exec_node_data(struct oa_sample_buf, tail_node, link);
-   uint32_t last_timestamp = tail_buf->last_timestamp;
+   uint32_t last_timestamp =
+      tail_buf->len == 0 ? start_timestamp : tail_buf->last_timestamp;
 
    while (1) {
       struct oa_sample_buf *buf = get_free_sample_buf(perf_ctx);
@@ -1989,12 +1994,13 @@ read_oa_samples_until(struct gen_perf_context *perf_ctx,
          exec_list_push_tail(&perf_ctx->free_sample_buffers, &buf->link);
 
          if (len < 0) {
-            if (errno == EAGAIN)
-               return ((last_timestamp - start_timestamp) >=
+            if (errno == EAGAIN) {
+               return ((last_timestamp - start_timestamp) < INT32_MAX &&
+                       (last_timestamp - start_timestamp) >=
                        (end_timestamp - start_timestamp)) ?
                       OA_READ_STATUS_FINISHED :
                       OA_READ_STATUS_UNFINISHED;
-            else {
+            } else {
                DBG("Error reading i915 perf samples: %m\n");
             }
          } else
@@ -2210,6 +2216,17 @@ discard_all_queries(struct gen_perf_context *perf_ctx)
    }
 }
 
+/* Looks for the validity bit of context ID (dword 2) of an OA report. */
+static bool
+oa_report_ctx_id_valid(const struct gen_device_info *devinfo,
+                       const uint32_t *report)
+{
+   assert(devinfo->gen >= 8);
+   if (devinfo->gen == 8)
+      return (report[0] & (1 << 25)) != 0;
+   return (report[0] & (1 << 16)) != 0;
+}
+
 /**
  * Accumulate raw OA counter values based on deltas between pairs of
  * OA reports.
@@ -2237,7 +2254,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
    uint32_t *last;
    uint32_t *end;
    struct exec_node *first_samples_node;
-   bool in_ctx = true;
+   bool last_report_ctx_match = true;
    int out_duration = 0;
 
    assert(query->oa.map != NULL);
@@ -2266,7 +2283,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
    first_samples_node = query->oa.samples_head->next;
 
    foreach_list_typed_from(struct oa_sample_buf, buf, link,
-                           &perf_ctx.sample_buffers,
+                           &perf_ctx->sample_buffers,
                            first_samples_node)
    {
       int offset = 0;
@@ -2283,6 +2300,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
          switch (header->type) {
          case DRM_I915_PERF_RECORD_SAMPLE: {
             uint32_t *report = (uint32_t *)(header + 1);
+            bool report_ctx_match = true;
             bool add = true;
 
             /* Ignore reports that come before the start marker.
@@ -2311,35 +2329,30 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
              * of OA counters while any other context is acctive.
              */
             if (devinfo->gen >= 8) {
-               if (in_ctx && report[2] != query->oa.result.hw_id) {
-                  DBG("i915 perf: Switch AWAY (observed by ID change)\n");
-                  in_ctx = false;
+               /* Consider that the current report matches our context only if
+                * the report says the report ID is valid.
+                */
+               report_ctx_match = oa_report_ctx_id_valid(devinfo, report) &&
+                  report[2] == start[2];
+               if (report_ctx_match)
                   out_duration = 0;
-               } else if (in_ctx == false && report[2] == query->oa.result.hw_id) {
-                  DBG("i915 perf: Switch TO\n");
-                  in_ctx = true;
-
-                  /* From experimentation in IGT, we found that the OA unit
-                   * might label some report as "idle" (using an invalid
-                   * context ID), right after a report for a given context.
-                   * Deltas generated by those reports actually belong to the
-                   * previous context, even though they're not labelled as
-                   * such.
-                   *
-                   * We didn't *really* Switch AWAY in the case that we e.g.
-                   * saw a single periodic report while idle...
-                   */
-                  if (out_duration >= 1)
-                     add = false;
-               } else if (in_ctx) {
-                  assert(report[2] == query->oa.result.hw_id);
-                  DBG("i915 perf: Continuation IN\n");
-               } else {
-                  assert(report[2] != query->oa.result.hw_id);
-                  DBG("i915 perf: Continuation OUT\n");
-                  add = false;
+               else
                   out_duration++;
-               }
+
+               /* Only add the delta between <last, report> if the last report
+                * was clearly identified as our context, or if we have at most
+                * 1 report without a matching ID.
+                *
+                * The OA unit will sometimes label reports with an invalid
+                * context ID when i915 rewrites the execlist submit register
+                * with the same context as the one currently running. This
+                * happens when i915 wants to notify the HW of ringbuffer tail
+                * register update. We have to consider this report as part of
+                * our context as the 3d pipeline behind the OACS unit is still
+                * processing the operations started at the previous execlist
+                * submission.
+                */
+               add = last_report_ctx_match && out_duration < 2;
             }
 
             if (add) {
@@ -2349,6 +2362,7 @@ accumulate_oa_reports(struct gen_perf_context *perf_ctx,
             }
 
             last = report;
+            last_report_ctx_match = report_ctx_match;
 
             break;
          }

src/intel/vulkan/anv_cmd_buffer.c

@@ -345,6 +345,9 @@ VkResult anv_ResetCommandBuffer(
    case 11:                                        \
       gen11_##func(__VA_ARGS__);                   \
       break;                                       \
+   case 12:                                        \
+      gen12_##func(__VA_ARGS__);                   \
+      break;                                       \
    default:                                        \
       assert(!"Unknown hardware generation");      \
    }

src/intel/vulkan/anv_device.c

@@ -1683,7 +1683,7 @@ void anv_GetPhysicalDeviceProperties2(
          VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
             (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
          properties->filterMinmaxImageComponentMapping = pdevice->info.gen >= 9;
-         properties->filterMinmaxSingleComponentFormats = true;
+         properties->filterMinmaxSingleComponentFormats = pdevice->info.gen >= 9;
          break;
       }
 
@@ -3000,6 +3000,14 @@ VkResult anv_DeviceWaitIdle(
 bool
 anv_vma_alloc(struct anv_device *device, struct anv_bo *bo)
 {
+   const struct anv_physical_device *pdevice = &device->instance->physicalDevice;
+   const struct gen_device_info *devinfo = &pdevice->info;
+   /* Gen12 CCS surface addresses need to be 64K aligned. We have no way of
+    * telling what this allocation is for so pick the largest alignment.
+    */
+   const uint32_t vma_alignment =
+      devinfo->gen >= 12 ? (64 * 1024) : (4 * 1024);
+
    if (!(bo->flags & EXEC_OBJECT_PINNED))
       return true;
 
@@ -3009,7 +3017,8 @@ anv_vma_alloc(struct anv_device *device, struct anv_bo *bo)
 
    if (bo->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS &&
        device->vma_hi_available >= bo->size) {
-      uint64_t addr = util_vma_heap_alloc(&device->vma_hi, bo->size, 4096);
+      uint64_t addr =
+         util_vma_heap_alloc(&device->vma_hi, bo->size, vma_alignment);
       if (addr) {
          bo->offset = gen_canonical_address(addr);
          assert(addr == gen_48b_address(bo->offset));
@@ -3018,7 +3027,8 @@ anv_vma_alloc(struct anv_device *device, struct anv_bo *bo)
    }
 
    if (bo->offset == 0 && device->vma_lo_available >= bo->size) {
-      uint64_t addr = util_vma_heap_alloc(&device->vma_lo, bo->size, 4096);
+      uint64_t addr =
+         util_vma_heap_alloc(&device->vma_lo, bo->size, vma_alignment);
       if (addr) {
          bo->offset = gen_canonical_address(addr);
          assert(addr == gen_48b_address(bo->offset));
@@ -3267,9 +3277,10 @@ VkResult anv_AllocateMemory(
                                       i915_tiling);
          if (ret) {
             anv_bo_cache_release(device, &device->bo_cache, mem->bo);
-            return vk_errorf(device->instance, NULL,
-                             VK_ERROR_OUT_OF_DEVICE_MEMORY,
-                             "failed to set BO tiling: %m");
+            result = vk_errorf(device->instance, NULL,
+                               VK_ERROR_OUT_OF_DEVICE_MEMORY,
+                               "failed to set BO tiling: %m");
+            goto fail;
          }
       }
    }

src/intel/vulkan/anv_queue.c

@@ -681,7 +681,11 @@ anv_wait_for_fences(struct anv_device *device,
    if (fenceCount <= 1 || waitAll) {
       for (uint32_t i = 0; i < fenceCount; i++) {
          ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
-         switch (fence->permanent.type) {
+         struct anv_fence_impl *impl =
+            fence->temporary.type != ANV_FENCE_TYPE_NONE ?
+            &fence->temporary : &fence->permanent;
+
+         switch (impl->type) {
          case ANV_FENCE_TYPE_BO:
             result = anv_wait_for_bo_fences(device, 1, &pFences[i],
                                             true, abs_timeout);
@@ -716,7 +720,10 @@ static bool anv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
 {
    for (uint32_t i = 0; i < fenceCount; ++i) {
       ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
-      if (fence->permanent.type != ANV_FENCE_TYPE_SYNCOBJ)
+      struct anv_fence_impl *impl =
+         fence->temporary.type != ANV_FENCE_TYPE_NONE ?
+         &fence->temporary : &fence->permanent;
+      if (impl->type != ANV_FENCE_TYPE_SYNCOBJ)
          return false;
    }
    return true;
@@ -726,7 +733,10 @@ static bool anv_all_fences_bo(uint32_t fenceCount, const VkFence *pFences)
 {
    for (uint32_t i = 0; i < fenceCount; ++i) {
       ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
-      if (fence->permanent.type != ANV_FENCE_TYPE_BO)
+      struct anv_fence_impl *impl =
+         fence->temporary.type != ANV_FENCE_TYPE_NONE ?
+         &fence->temporary : &fence->permanent;
+      if (impl->type != ANV_FENCE_TYPE_BO)
          return false;
    }
    return true;

src/intel/vulkan/genX_cmd_buffer.c

@@ -3893,6 +3893,13 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
          vfe.NumberofURBEntries     = 2;
          vfe.URBEntryAllocationSize = 2;
       }
+
+      /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
+       * invalid. Set the compute pipeline to dirty to force a re-emit of the
+       * pipeline in case we get back-to-back dispatch calls with the same
+       * pipeline and a PIPELINE_SELECT in between.
+       */
+      cmd_buffer->state.compute.pipeline_dirty = true;
    }
 #endif
 

src/loader/loader_dri3_helper.c

@@ -1119,6 +1119,7 @@ dri3_cpp_for_format(uint32_t format) {
    case  __DRI_IMAGE_FORMAT_ABGR2101010:
    case  __DRI_IMAGE_FORMAT_SARGB8:
    case  __DRI_IMAGE_FORMAT_SABGR8:
+   case  __DRI_IMAGE_FORMAT_SXRGB8:
       return 4;
    case __DRI_IMAGE_FORMAT_XBGR16161616F:
    case __DRI_IMAGE_FORMAT_ABGR16161616F:
@@ -1172,6 +1173,7 @@ image_format_to_fourcc(int format)
    switch (format) {
    case __DRI_IMAGE_FORMAT_SARGB8: return __DRI_IMAGE_FOURCC_SARGB8888;
    case __DRI_IMAGE_FORMAT_SABGR8: return __DRI_IMAGE_FOURCC_SABGR8888;
+   case __DRI_IMAGE_FORMAT_SXRGB8: return __DRI_IMAGE_FOURCC_SXRGB8888;
    case __DRI_IMAGE_FORMAT_RGB565: return DRM_FORMAT_RGB565;
    case __DRI_IMAGE_FORMAT_XRGB8888: return DRM_FORMAT_XRGB8888;
    case __DRI_IMAGE_FORMAT_ARGB8888: return DRM_FORMAT_ARGB8888;

src/mesa/drivers/dri/common/dri_util.c

@@ -950,6 +950,10 @@ static const struct {
       .image_format = __DRI_IMAGE_FORMAT_SARGB8,
       .mesa_format  =        MESA_FORMAT_B8G8R8A8_SRGB,
    },
+   {
+      .image_format = __DRI_IMAGE_FORMAT_SXRGB8,
+      .mesa_format  =        MESA_FORMAT_B8G8R8X8_SRGB,
+   },
    {
       .image_format = __DRI_IMAGE_FORMAT_R16,
       .mesa_format  =        MESA_FORMAT_R_UNORM16,

src/mesa/drivers/dri/i965/intel_screen.c

@@ -218,6 +218,9 @@ static const struct intel_image_format intel_image_formats[] = {
    { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
      { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
 
+   { __DRI_IMAGE_FOURCC_SXRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
+     { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8, 4 } } },
+
    { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
      { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
 
@@ -1334,12 +1337,13 @@ intel_query_dma_buf_formats(__DRIscreen *_screen, int max,
    int num_formats = 0, i;
 
    for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
-      /* These two formats are valid DRI formats but do not exist in
-       * drm_fourcc.h in the Linux kernel.  We don't want to accidentally
-       * advertise them through the EGL layer.
+      /* These formats are valid DRI formats but do not exist in drm_fourcc.h
+       * in the Linux kernel. We don't want to accidentally advertise them
+       * them through the EGL layer.
        */
       if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
-          intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888)
+          intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888 ||
+          intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SXRGB8888)
          continue;
 
       if (!intel_image_format_is_supported(&screen->devinfo,
@@ -1759,12 +1763,14 @@ intelCreateBuffer(__DRIscreen *dri_screen,
    } else if (mesaVis->redBits == 5) {
       rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
                                            : MESA_FORMAT_B5G6R5_UNORM;
+   } else if (mesaVis->alphaBits == 0) {
+      rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
+                                           : MESA_FORMAT_B8G8R8X8_SRGB;
+      fb->Visual.sRGBCapable = true;
    } else if (mesaVis->sRGBCapable) {
       rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
                                            : MESA_FORMAT_B8G8R8A8_SRGB;
-   } else if (mesaVis->alphaBits == 0) {
-      rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
-                                           : MESA_FORMAT_B8G8R8X8_UNORM;
+      fb->Visual.sRGBCapable = true;
    } else {
       rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
                                            : MESA_FORMAT_B8G8R8A8_SRGB;
@@ -2222,6 +2228,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
       MESA_FORMAT_B8G8R8X8_UNORM,
 
       MESA_FORMAT_B8G8R8A8_SRGB,
+      MESA_FORMAT_B8G8R8X8_SRGB,
 
       /* For 10 bpc, 30 bit depth framebuffers. */
       MESA_FORMAT_B10G10R10A2_UNORM,

src/mesa/main/performance_query.c

@@ -48,6 +48,12 @@ free_performance_query(GLuint key, void *data, void *user)
    struct gl_perf_query_object *m = data;
    struct gl_context *ctx = user;
 
+   /* Don't confuse the implementation by deleting an active query. We can
+    * toggle Active/Used to false because we're tearing down the GL context
+    * and it's already idle (see _mesa_free_context_data).
+    */
+   m->Active = false;
+   m->Used = false;
    ctx->Driver.DeletePerfQuery(ctx, m);
 }