version: bump version to 20.2.3

Icelake's sampler message header introduces a field in m0.3 bit 0
which controls whether the sampler state pointer should be relative
to bindless sampler state base address or dynamic state base address.

g0.3 bit 0 is part of the per-thread scratch space field.  On older
hardware, we were able to copy that along because the sampler ignored
bits 4:0.  Now, however, we need to mask them out.

Fixes various textureGatherOffsets piglit tests when forcing the FS
to run with 2048 bytes of per-thread scratch space (which is a
per-thread scratch space encoding of 1, meaning bit 0 will be set).

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6735>
(cherry picked from commit 31290f9806)

VERSION

@@ -1 +1 @@
-20.2.2
+20.2.3

docs/relnotes/20.2.2.rst

@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-    TBD.
+    1f93eb1090cf71490cd0e204e04f8427a82b6ed534b7f49ca50cea7dcc89b861  mesa-20.2.2.tar.xz
 
 
 New features

docs/relnotes/20.2.3.rst

@@ -0,0 +1,184 @@
+Mesa 20.2.3 Release Notes / 2020-11-23
+======================================
+
+Mesa 20.2.3 is a bug fix release which fixes bugs found since the 20.2.2 release.
+
+Mesa 20.2.3 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 20.2.3 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+    TBD.
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- glcpp test 084-unbalanced-parentheses fails with bison 3.6.y
+- iris: glClear with FBO imported from DMA-BUF doesn't work
+- [spirv-fuzz] Shader causes an assertion failure in nir_opt_large_constants
+- Regnum Online UBO break after game update
+- Random corruption in KDE with Mesa 20.2 in VMware
+
+
+Changes
+-------
+
+Bas Nieuwenhuizen (1):
+
+- radv: Add ETC2 support on RAVEN2.
+
+Brendan Dougherty (1):
+
+- mesa: Fix vertex_format_to_pipe_format index.
+
+Chad Versace (2):
+
+- anv/image: Check DISJOINT in vkGetPhysicalDeviceImageFormatProperties2 (v2)
+- anv/image: Fix isl_surf_usage_flags for stencil images
+
+Christian Gmeiner (1):
+
+- etnaviv: nir: do not run opt loop after nir_lower_bool_xxx(..)
+
+Dave Airlie (1):
+
+- draw: fix tess eval pipeline statistics.
+
+Dylan Baker (6):
+
+- dcs: Add sha256 sums for 20.2.2
+- .pick_status.json: Update to bf5cea7232f9ee2934c212211ebefb6fe766526d
+- .pick_status.json: Update to 87dc3106b077199b829a082e32ec33d0c6d400ab
+- .pick_status.json: Mark 87934f02f9da94f1a493096049c229b973e4785c as backported
+- .pick_status.json: Mark ea326912575fad09af59486ad62d126c4ea0ede7 as backported
+- .pick_status.json: Update to bac6cc586fe4c1b24351e0574d3a961eb631f6ae
+
+Eric Anholt (3):
+
+- freedreno/cffdec: When .mergedregs is set, don't count half regs.
+- util/set: Fix the _mesa_set_clear function to not leave tombstones.
+- freedreno: Fix leak of shader binary on disk cache hits.
+
+Erik Faye-Lund (2):
+
+- gallium/util: do not pass undefined sample-count
+- mesa/main: add missing include in glformats.h
+
+Gert Wollny (1):
+
+- r600: revert disabling llvm draw
+
+Igor V. Kovalenko (1):
+
+- r600: amend space check for chips older than EVERGREEN
+
+Jason Ekstrand (4):
+
+- mesa/spirv: Lower variable initializers for global variables
+- nir: Handle incomplete derefs in split_struct_vars
+- nir/opt_intrinsics: Report progress for the gl_SampleMask optimization
+- intel/fs: Fix use of undefined value in fixup_nomask_control_flow
+
+Kenneth Graunke (2):
+
+- iris: fix source/destination layers for 3D blits
+- intel/fs: Fix sampler message headers on Gen11+ when using scratch
+
+Krunal Patel (2):
+
+- gallium/auxiliary/vl: Odd Dimensions are failing
+- radeon/vcn: Bitrate not updated when changing framerate
+
+Louis Li (1):
+
+- radeon/radeon_vce: fix out of target bitrate in CBR mode (H.264)
+
+Marcin Ślusarz (2):
+
+- anv: always annotate memory returned from anv_gem_mmap
+- nir: handle float atomics in copy propagation pass
+
+Marek Olšák (3):
+
+- radeonsi: do VGT_FLUSH when switching NGG -> legacy on Sienna Cichlid
+- radeonsi: only do VGT_FLUSH for fast launch if previous draw was normal launch
+- radeonsi: fix scan_instruction for bindless inc_wrap/dec_wrap atomics
+
+Matt Turner (1):
+
+- glcpp: Handle bison-3.6 error message changes
+
+Michel Dänzer (2):
+
+- i965/bufmgr: Handle NULL bufmgr in brw_bufmgr_get_for_fd
+- iris/bufmgr: Handle NULL bufmgr in iris_bufmgr_get_for_fd
+
+Nanley Chery (4):
+
+- iris: Flush dmabufs during context flushes
+- mesa: Add and use _mesa_has_depth_float_channel
+- mesa: Clamp some depth values in glClearBufferfv
+- mesa: Clamp some depth values in glClearBufferfi
+
+Raven (1):
+
+- winsys/svga: fix display corruption after surface_init
+
+Rhys Perry (4):
+
+- radv: fix shader caching with discard->demote workaround
+- radv: fix shader caching with NaN fixup workaround
+- nir: add nir_alu_src_is_trivial_ssa()
+- nir: skip bcsel with non-trivial swizzle in opt_simplify_bcsel_of_phi()
+
+Rob Clark (2):
+
+- freedreno: Protect gmem_cache ralloc allocations
+- freedreno/ir3: Fix crash in shader compile fail path
+
+Tapani Pälli (3):
+
+- mesa/st: call memobj_destroy only if there is memory imported
+- mesa: do not throw _mesa_problem when invalid enum is used
+- egl/dri2: fix race between image create and egl_image_target_texture
+
+Timothy Arceri (1):
+
+- glsl: add extra pp tokens workaround and enable for CoR
+
+Tony Wasserka (1):
+
+- aco/ra: Fix counting of subdword variables in get_reg_create_vector
+
+Vinson Lee (4):
+
+- os: Fix open result check.
+- amd/addrlib: Add missing va_end.
+- frontends/va: Fix *num_entrypoints check.
+- vdpau: Add missing printf format specifier.
+
+Woody Chow (1):
+
+- st/mesa: Fix EGLImageTargetTexture2D for GL_TEXTURE_2D
+
+Yevhenii Kolesnikov (1):
+
+- nir/large_constants: only search for constant duplicates

src/amd/addrlib/src/core/addrobject.cpp

@@ -230,6 +230,7 @@ VOID Object::DebugPrint(
         m_client.callbacks.debugPrint(&debugPrintInput);
 
         va_end(ap);
+        va_end(debugPrintInput.ap);
     }
 #endif
 }

src/amd/compiler/aco_register_allocation.cpp

@@ -1349,7 +1349,7 @@ PhysReg get_reg_create_vector(ra_ctx& ctx,
                PhysReg reg;
                reg.reg_b = j * 4;
                unsigned bytes_left = bytes - (j - reg_lo) * 4;
-               for (unsigned k = 0; k < MIN2(bytes_left, 4); k++, reg.reg_b++)
+               for (unsigned byte_idx = 0; byte_idx < MIN2(bytes_left, 4); byte_idx++, reg.reg_b++)
                   k += reg_file.test(reg, 1);
             } else {
                k += 4;

src/amd/vulkan/radv_formats.c

@@ -624,6 +624,7 @@ radv_device_supports_etc(struct radv_physical_device *physical_device)
 {
 	return physical_device->rad_info.family == CHIP_VEGA10 ||
 	       physical_device->rad_info.family == CHIP_RAVEN ||
+	       physical_device->rad_info.family == CHIP_RAVEN2 ||
 	       physical_device->rad_info.family == CHIP_STONEY;
 }
 

src/amd/vulkan/radv_pipeline.c

@@ -219,6 +219,10 @@ static uint32_t get_hash_flags(struct radv_device *device)
 		hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
 	if (device->physical_device->use_llvm)
 		hash_flags |= RADV_HASH_SHADER_LLVM;
+	if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
+		hash_flags |= RADV_HASH_SHADER_DISCARD_TO_DEMOTE;
+	if (device->instance->enable_mrt_output_nan_fixup)
+		hash_flags |= RADV_HASH_SHADER_MRT_NAN_FIXUP;
 	return hash_flags;
 }
 

src/amd/vulkan/radv_private.h

@@ -1589,6 +1589,8 @@ struct radv_shader_module;
 #define RADV_HASH_SHADER_PS_WAVE32           (1 << 2)
 #define RADV_HASH_SHADER_GE_WAVE32           (1 << 3)
 #define RADV_HASH_SHADER_LLVM                (1 << 4)
+#define RADV_HASH_SHADER_DISCARD_TO_DEMOTE   (1 << 5)
+#define RADV_HASH_SHADER_MRT_NAN_FIXUP       (1 << 6)
 
 void
 radv_hash_shaders(unsigned char *hash,

src/compiler/glsl/glcpp/glcpp-parse.y

@@ -781,7 +781,10 @@ replacement_list:
 junk:
 	/* empty */
 |	pp_tokens {
-		glcpp_error(&@1, parser, "extra tokens at end of directive");
+		if (parser->gl_ctx->Const.AllowExtraPPTokens)
+			glcpp_warning(&@1, parser, "extra tokens at end of directive");
+		else
+			glcpp_error(&@1, parser, "extra tokens at end of directive");
 	}
 ;
 

src/compiler/glsl/glcpp/tests/084-unbalanced-parentheses.c.expected

@@ -1,2 +1,2 @@
-0:2(8): preprocessor error: syntax error, unexpected $end
+0:2(8): preprocessor error: syntax error, unexpected end of file
 

src/compiler/glsl/glcpp/tests/glcpp_test.py

@@ -79,6 +79,10 @@ def test_output(glcpp, filename, expfile, nl_format='\n'):
     with open(expfile, 'r') as f:
         expected = f.read()
 
+    # Bison 3.6 changed '$end' to 'end of file' in its error messages
+    # See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3181
+    actual = actual.replace('$end', 'end of file')
+
     if actual == expected:
         return (True, [])
     return (False, difflib.unified_diff(actual.splitlines(), expected.splitlines()))

src/compiler/nir/nir.c

@@ -271,6 +271,20 @@ nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
    dest->saturate = src->saturate;
 }
 
+bool
+nir_alu_src_is_trivial_ssa(const nir_alu_instr *alu, unsigned srcn)
+{
+   static uint8_t trivial_swizzle[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+   STATIC_ASSERT(ARRAY_SIZE(trivial_swizzle) == NIR_MAX_VEC_COMPONENTS);
+
+   const nir_alu_src *src = &alu->src[srcn];
+   unsigned num_components = nir_ssa_alu_instr_src_components(alu, srcn);
+
+   return src->src.is_ssa && (src->src.ssa->num_components == num_components) &&
+          !src->abs && !src->negate &&
+          (memcmp(src->swizzle, trivial_swizzle, num_components) == 0);
+}
+
 
 static void
 cf_init(nir_cf_node *node, nir_cf_node_type type)

src/compiler/nir/nir.h

@@ -1406,6 +1406,8 @@ bool nir_alu_srcs_negative_equal(const nir_alu_instr *alu1,
                                  const nir_alu_instr *alu2,
                                  unsigned src1, unsigned src2);
 
+bool nir_alu_src_is_trivial_ssa(const nir_alu_instr *alu, unsigned srcn);
+
 typedef enum {
    nir_deref_type_var,
    nir_deref_type_array,

src/compiler/nir/nir_opt_copy_prop_vars.c

@@ -185,15 +185,19 @@ gather_vars_written(struct copy_prop_var_state *state,
             break;
 
          case nir_intrinsic_deref_atomic_add:
+         case nir_intrinsic_deref_atomic_fadd:
          case nir_intrinsic_deref_atomic_imin:
          case nir_intrinsic_deref_atomic_umin:
+         case nir_intrinsic_deref_atomic_fmin:
          case nir_intrinsic_deref_atomic_imax:
          case nir_intrinsic_deref_atomic_umax:
+         case nir_intrinsic_deref_atomic_fmax:
          case nir_intrinsic_deref_atomic_and:
          case nir_intrinsic_deref_atomic_or:
          case nir_intrinsic_deref_atomic_xor:
          case nir_intrinsic_deref_atomic_exchange:
          case nir_intrinsic_deref_atomic_comp_swap:
+         case nir_intrinsic_deref_atomic_fcomp_swap:
          case nir_intrinsic_store_deref:
          case nir_intrinsic_copy_deref: {
             /* Destination in all of store_deref, copy_deref and the atomics is src[0]. */
@@ -1057,15 +1061,19 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
       }
 
       case nir_intrinsic_deref_atomic_add:
+      case nir_intrinsic_deref_atomic_fadd:
       case nir_intrinsic_deref_atomic_imin:
       case nir_intrinsic_deref_atomic_umin:
+      case nir_intrinsic_deref_atomic_fmin:
       case nir_intrinsic_deref_atomic_imax:
       case nir_intrinsic_deref_atomic_umax:
+      case nir_intrinsic_deref_atomic_fmax:
       case nir_intrinsic_deref_atomic_and:
       case nir_intrinsic_deref_atomic_or:
       case nir_intrinsic_deref_atomic_xor:
       case nir_intrinsic_deref_atomic_exchange:
       case nir_intrinsic_deref_atomic_comp_swap:
+      case nir_intrinsic_deref_atomic_fcomp_swap:
          if (debug) dump_instr(instr);
 
          nir_deref_instr *dst = nir_src_as_deref(intrin->src[0]);

src/compiler/nir/nir_opt_if.c

@@ -644,14 +644,13 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop)
 
       bool match = true;
       for (unsigned i = 0; i < 3; i++) {
-         /* FINISHME: The abs and negate cases could be handled by adding
-          * move instructions at the bottom of the continue block and more
-          * phi nodes in the header_block.
+         /* FINISHME: The abs, negate and swizzled cases could be handled by
+          * adding move instructions at the bottom of the continue block and
+          * more phi nodes in the header_block.
           */
-         if (!bcsel->src[i].src.is_ssa ||
+         if (!nir_alu_src_is_trivial_ssa(bcsel, i) ||
              bcsel->src[i].src.ssa->parent_instr->type != nir_instr_type_phi ||
-             bcsel->src[i].src.ssa->parent_instr->block != header_block ||
-             bcsel->src[i].negate || bcsel->src[i].abs) {
+             bcsel->src[i].src.ssa->parent_instr->block != header_block) {
             match = false;
             break;
          }

src/compiler/nir/nir_opt_intrinsics.c

@@ -86,6 +86,7 @@ opt_intrinsics_impl(nir_function_impl *impl,
                      nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa,
                                               nir_src_for_ssa(new_expr));
                      nir_instr_remove(&alu->instr);
+                     progress = true;
                      continue;
                   }
                }

src/compiler/nir/nir_opt_large_constants.c

@@ -50,7 +50,9 @@ var_info_cmp(const void *_a, const void *_b)
    uint32_t a_size = a->constant_data_size;
    uint32_t b_size = b->constant_data_size;
 
-   if (a_size < b_size) {
+   if (a->is_constant != b->is_constant) {
+      return (int)a->is_constant - (int)b->is_constant;
+   } else if (a_size < b_size) {
       return -1;
    } else if (a_size > b_size) {
       return 1;

src/compiler/nir/nir_split_vars.c

@@ -232,6 +232,14 @@ split_struct_derefs_impl(nir_function_impl *impl,
             continue;
 
          nir_variable *base_var = nir_deref_instr_get_variable(deref);
+         /* If we can't chase back to the variable, then we're a complex use.
+          * This should have been detected by get_complex_used_vars() and the
+          * variable should not have been split.  However, we have no way of
+          * knowing that here, so we just have to trust it.
+          */
+         if (base_var == NULL)
+            continue;
+
          struct hash_entry *entry =
             _mesa_hash_table_search(var_field_map, base_var);
          if (!entry)

src/egl/drivers/dri2/egl_dri2.c

@@ -685,7 +685,10 @@ dri2_lookup_egl_image(__DRIscreen *screen, void *image, void *data)
 
    (void) screen;
 
+   mtx_lock(&disp->Mutex);
    img = _eglLookupImage(image, disp);
+   mtx_unlock(&disp->Mutex);
+
    if (img == NULL) {
       _eglError(EGL_BAD_PARAMETER, "dri2_lookup_egl_image");
       return NULL;

src/freedreno/ir3/disasm-a3xx.c

@@ -266,7 +266,7 @@ static void print_reg_stats(struct disasm_ctx *ctx)
 	 * assigned to shader:
 	 */
 	fullreg = (fullreg + 3) / 4;
-	halfreg = (halfreg + 3) / 4;
+	halfreg = ctx->regs.used.mergedregs ? 0 : (halfreg + 3) / 4;
 
 	// Note this count of instructions includes rptN, which matches
 	// up to how mesa prints this:

src/freedreno/ir3/ir3.c

@@ -986,7 +986,7 @@ void * ir3_assemble(struct ir3_shader_variant *v)
 	return ptr;
 
 fail:
-	free(ptr);
+	ralloc_free(ptr);
 	return NULL;
 }
 

src/freedreno/ir3/ir3_disk_cache.c

@@ -126,7 +126,7 @@ retrieve_variant(struct blob_reader *blob, struct ir3_shader_variant *v)
 	 * pointers need special handling:
 	 */
 
-	v->bin = malloc(4 * v->info.sizedwords);
+	v->bin = rzalloc_size(v, 4 * v->info.sizedwords);
 	blob_copy_bytes(blob, v->bin, 4 * v->info.sizedwords);
 
 	if (!v->binning_pass) {

src/gallium/auxiliary/draw/draw_tess.c

@@ -350,9 +350,6 @@ int draw_tess_eval_shader_run(struct draw_tess_eval_shader *shader,
    shader->input_vertex_stride = input_stride;
    shader->input_info = input_info;
 
-   if (shader->draw->collect_statistics) {
-      shader->draw->statistics.ds_invocations += input_prim->primitive_count;
-   }
 #ifdef LLVM_AVAILABLE
    struct pipe_tessellation_factors factors;
    struct pipe_tessellator_data data = { 0 };
@@ -394,6 +391,10 @@ int draw_tess_eval_shader_run(struct draw_tess_eval_shader *shader,
       output += vert_start * vertex_size;
       llvm_tes_run(shader, i, num_input_vertices_per_patch, &data, &factors, (struct vertex_header *)output);
 
+      if (shader->draw->collect_statistics) {
+         shader->draw->statistics.ds_invocations += data.num_domain_points;
+      }
+
       uint32_t prim_len = u_prim_vertex_count(output_prims->prim)->min;
       output_prims->primitive_count += data.num_indices / prim_len;
       output_prims->primitive_lengths = REALLOC(output_prims->primitive_lengths, prim_start * sizeof(uint32_t),

src/gallium/auxiliary/os/os_process.c

@@ -122,7 +122,7 @@ os_get_command_line(char *cmdline, size_t size)
    }
 #elif defined(PIPE_OS_LINUX)
    int f = open("/proc/self/cmdline", O_RDONLY);
-   if (f) {
+   if (f != -1) {
       const int n = read(f, cmdline, size - 1);
       int i;
       assert(n < size);

src/gallium/auxiliary/pipe-loader/driinfo_gallium.h

@@ -22,6 +22,7 @@ DRI_CONF_SECTION_DEBUG
    DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
    DRI_CONF_DISABLE_ARB_GPU_SHADER5("false")
    DRI_CONF_FORCE_GLSL_VERSION(0)
+   DRI_CONF_ALLOW_EXTRA_PP_TOKENS("false")
    DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
    DRI_CONF_ALLOW_GLSL_120_SUBSET_IN_110("false")
    DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION("false")

src/gallium/auxiliary/util/u_blitter.c

@@ -2721,7 +2721,7 @@ void util_blitter_custom_shader(struct blitter_context *blitter,
 {
    struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
    struct pipe_context *pipe = ctx->base.pipe;
-   struct pipe_framebuffer_state fb_state;
+   struct pipe_framebuffer_state fb_state = { 0 };
 
    ctx->custom_vs = custom_vs;
 
@@ -2747,7 +2747,6 @@ void util_blitter_custom_shader(struct blitter_context *blitter,
    fb_state.height = dstsurf->height;
    fb_state.nr_cbufs = 1;
    fb_state.cbufs[0] = dstsurf;
-   fb_state.zsbuf = 0;
    pipe->set_framebuffer_state(pipe, &fb_state);
    pipe->set_sample_mask(pipe, ~0);
 

src/gallium/auxiliary/vl/vl_video_buffer.h

@@ -54,14 +54,14 @@ vl_video_buffer_adjust_size(unsigned *width, unsigned *height, unsigned plane,
                             bool interlaced)
 {
    if (interlaced) {
-      *height /= 2;
+      *height = align(*height, 2) / 2;
    }
    if (plane > 0) {
       if (chroma_format == PIPE_VIDEO_CHROMA_FORMAT_420) {
-         *width /= 2;
-         *height /= 2;
+         *width = align(*width, 2) / 2;
+         *height = align(*height, 2) / 2;
       } else if (chroma_format == PIPE_VIDEO_CHROMA_FORMAT_422) {
-         *width /= 2;
+         *width = align(*width, 2) / 2;
       }
    }
 }

src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c

@@ -1117,8 +1117,6 @@ etna_compile_shader_nir(struct etna_shader_variant *v)
       NIR_PASS_V(s, nir_lower_bool_to_int32);
    }
 
-   etna_optimize_loop(s);
-
    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
       nir_print_shader(s, stdout);
 

src/gallium/drivers/freedreno/freedreno_gmem.c

@@ -521,11 +521,15 @@ lookup_gmem_state(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
 	struct fd_screen *screen = batch->ctx->screen;
 	struct fd_gmem_cache *cache = &screen->gmem_cache;
 	struct fd_gmem_stateobj *gmem = NULL;
+
+	/* Lock before allocating gmem_key, since that a screen-wide
+	 * ralloc pool and ralloc itself is not thread-safe.
+	 */
+	fd_screen_lock(screen);
+
 	struct gmem_key *key = gmem_key_init(batch, assume_zs, no_scis_opt);
 	uint32_t hash = gmem_key_hash(key);
 
-	fd_screen_lock(screen);
-
 	struct hash_entry *entry =
 		_mesa_hash_table_search_pre_hashed(cache->ht, hash, key);
 	if (entry) {

src/gallium/drivers/iris/iris_blit.c

@@ -485,15 +485,28 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
    else
       main_mask = PIPE_MASK_RGBA;
 
+   float src_z_step = (float)info->src.box.depth / (float)info->dst.box.depth;
+
+   /* There is no interpolation to the pixel center during rendering, so
+    * add the 0.5 offset ourselves here.
+    */
+   float depth_center_offset = 0;
+   if (src_res->surf.dim == ISL_SURF_DIM_3D)
+      depth_center_offset = 0.5 / info->dst.box.depth * info->src.box.depth;
+
    if (info->mask & main_mask) {
       for (int slice = 0; slice < info->dst.box.depth; slice++) {
+         unsigned dst_z = info->dst.box.z + slice;
+         float src_z = info->src.box.z + slice * src_z_step +
+                       depth_center_offset;
+
          iris_batch_maybe_flush(batch, 1500);
          iris_batch_sync_region_start(batch);
 
          blorp_blit(&blorp_batch,
-                    &src_surf, info->src.level, info->src.box.z + slice,
+                    &src_surf, info->src.level, src_z,
                     src_fmt.fmt, src_fmt.swizzle,
-                    &dst_surf, info->dst.level, info->dst.box.z + slice,
+                    &dst_surf, info->dst.level, dst_z,
                     dst_fmt.fmt, dst_fmt.swizzle,
                     src_x0, src_y0, src_x1, src_y1,
                     dst_x0, dst_y0, dst_x1, dst_y1,

src/gallium/drivers/iris/iris_bufmgr.c

@@ -1940,7 +1940,8 @@ iris_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd, bool bo_reuse)
    }
 
    bufmgr = iris_bufmgr_create(devinfo, fd, bo_reuse);
-   list_addtail(&bufmgr->link, &global_bufmgr_list);
+   if (bufmgr)
+      list_addtail(&bufmgr->link, &global_bufmgr_list);
 
  unlock:
    mtx_unlock(&global_bufmgr_list_mutex);

src/gallium/drivers/iris/iris_clear.c

@@ -107,10 +107,6 @@ can_fast_clear_color(struct iris_context *ice,
       return false;
    }
 
-   /* XXX: if (irb->mt->supports_fast_clear)
-    * see intel_miptree_create_for_dri_image()
-    */
-
    if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color))
       return false;
 

src/gallium/drivers/iris/iris_context.c

@@ -185,6 +185,49 @@ iris_get_sample_position(struct pipe_context *ctx,
    out_value[1] = u.a.y[sample_index];
 }
 
+static bool
+create_dirty_dmabuf_set(struct iris_context *ice)
+{
+   assert(ice->dirty_dmabufs == NULL);
+
+   ice->dirty_dmabufs = _mesa_pointer_set_create(ice);
+   return ice->dirty_dmabufs != NULL;
+}
+
+void
+iris_mark_dirty_dmabuf(struct iris_context *ice,
+                       struct pipe_resource *res)
+{
+   if (!_mesa_set_search(ice->dirty_dmabufs, res)) {
+      _mesa_set_add(ice->dirty_dmabufs, res);
+      pipe_reference(NULL, &res->reference);
+   }
+}
+
+static void
+clear_dirty_dmabuf_set(struct iris_context *ice)
+{
+   set_foreach(ice->dirty_dmabufs, entry) {
+      struct pipe_resource *res = (struct pipe_resource *)entry->key;
+      if (pipe_reference(&res->reference, NULL))
+         res->screen->resource_destroy(res->screen, res);
+   }
+
+   _mesa_set_clear(ice->dirty_dmabufs, NULL);
+}
+
+void
+iris_flush_dirty_dmabufs(struct iris_context *ice)
+{
+   set_foreach(ice->dirty_dmabufs, entry) {
+      struct pipe_resource *res = (struct pipe_resource *)entry->key;
+      ice->ctx.flush_resource(&ice->ctx, res);
+   }
+
+   clear_dirty_dmabuf_set(ice);
+}
+
+
 /**
  * Destroy a context, freeing any associated memory.
  */
@@ -197,6 +240,8 @@ iris_destroy_context(struct pipe_context *ctx)
    if (ctx->stream_uploader)
       u_upload_destroy(ctx->stream_uploader);
 
+   clear_dirty_dmabuf_set(ice);
+
    screen->vtbl.destroy_state(ice);
    iris_destroy_program_cache(ice);
    iris_destroy_border_color_pool(ice);
@@ -261,6 +306,11 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
    }
    ctx->const_uploader = ctx->stream_uploader;
 
+   if (!create_dirty_dmabuf_set(ice)) {
+      ralloc_free(ice);
+      return NULL;
+   }
+
    ctx->destroy = iris_destroy_context;
    ctx->set_debug_callback = iris_set_debug_callback;
    ctx->set_device_reset_callback = iris_set_device_reset_callback;

src/gallium/drivers/iris/iris_context.h

@@ -25,6 +25,7 @@
 
 #include "pipe/p_context.h"
 #include "pipe/p_state.h"
+#include "util/set.h"
 #include "util/slab.h"
 #include "util/u_debug.h"
 #include "intel/blorp/blorp.h"
@@ -536,6 +537,9 @@ struct iris_context {
    /** A device reset status callback for notifying that the GPU is hosed. */
    struct pipe_device_reset_callback reset;
 
+   /** A set of dmabuf resources dirtied beyond their default aux-states. */
+   struct set *dirty_dmabufs;
+
    /** Slab allocator for iris_transfer_map objects. */
    struct slab_child_pool transfer_pool;
 
@@ -772,6 +776,10 @@ iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 
 void iris_lost_context_state(struct iris_batch *batch);
 
+void iris_mark_dirty_dmabuf(struct iris_context *ice,
+                            struct pipe_resource *res);
+void iris_flush_dirty_dmabufs(struct iris_context *ice);
+
 void iris_init_blit_functions(struct pipe_context *ctx);
 void iris_init_clear_functions(struct pipe_context *ctx);
 void iris_init_program_functions(struct pipe_context *ctx);

src/gallium/drivers/iris/iris_fence.c

@@ -241,6 +241,8 @@ iris_fence_flush(struct pipe_context *ctx,
       }
    }
 
+   iris_flush_dirty_dmabufs(ice);
+
    if (!deferred) {
       for (unsigned i = 0; i < IRIS_BATCH_COUNT; i++)
          iris_batch_flush(&ice->batches[i]);

src/gallium/drivers/iris/iris_resolve.c

@@ -808,6 +808,15 @@ iris_resource_set_aux_state(struct iris_context *ice,
          ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
       }
    }
+
+   if (res->mod_info && !res->mod_info->supports_clear_color) {
+      assert(res->mod_info->aux_usage != ISL_AUX_USAGE_NONE);
+      if (aux_state == ISL_AUX_STATE_CLEAR ||
+          aux_state == ISL_AUX_STATE_COMPRESSED_CLEAR ||
+          aux_state == ISL_AUX_STATE_PARTIAL_CLEAR) {
+         iris_mark_dirty_dmabuf(ice, &res->base);
+      }
+   }
 }
 
 enum isl_aux_usage

src/gallium/drivers/r600/r600_pipe_common.c

@@ -1286,10 +1286,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
 	rscreen->family = rscreen->info.family;
 	rscreen->chip_class = rscreen->info.chip_class;
 	rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
-	int has_draw_use_llvm = debug_get_bool_option("DRAW_USE_LLVM", FALSE);
-	if (!has_draw_use_llvm)
-	   setenv("DRAW_USE_LLVM", "no", 0);
-
 
 	r600_disk_cache_create(rscreen);
 

src/gallium/drivers/r600/r600_state_common.c

@@ -2062,7 +2062,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 	unsigned index_size = info->index_size;
 	int index_bias;
 	struct r600_shader_atomic combined_atomics[8];
-	uint8_t atomic_used_mask;
+	uint8_t atomic_used_mask = 0;
 
 	if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
 		return;

src/gallium/drivers/radeon/radeon_vce_52.c

@@ -47,7 +47,17 @@ static void get_rate_control_param(struct rvce_encoder *enc, struct pipe_h264_en
    enc->enc_pic.rc.frame_rate_num = pic->rate_ctrl.frame_rate_num;
    enc->enc_pic.rc.frame_rate_den = pic->rate_ctrl.frame_rate_den;
    enc->enc_pic.rc.max_qp = 51;
-   enc->enc_pic.rc.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
+
+   /* For CBR mode, to guarantee bitrate of generated stream complies with
+    * target bitrate (e.g. no over +/-10%), vbv_buffer_size should be same
+    * as target bitrate.
+    */
+   if (enc->enc_pic.rc.rc_method == PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT) {
+           enc->enc_pic.rc.vbv_buffer_size = pic->rate_ctrl.target_bitrate;
+   } else {
+           enc->enc_pic.rc.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
+   }
+
    enc->enc_pic.rc.vbv_buf_lv = pic->rate_ctrl.vbv_buf_lv;
    enc->enc_pic.rc.fill_data_enable = pic->rate_ctrl.fill_data_enable;
    enc->enc_pic.rc.enforce_hrd = pic->rate_ctrl.enforce_hrd;

src/gallium/drivers/radeon/radeon_vcn_enc.c

@@ -271,7 +271,9 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
       struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
       need_rate_control =
-         enc->enc_pic.rc_layer_init.target_bit_rate != pic->rate_ctrl.target_bitrate;
+         (enc->enc_pic.rc_layer_init.target_bit_rate != pic->rate_ctrl.target_bitrate) ||
+         (enc->enc_pic.rc_layer_init.frame_rate_num != pic->rate_ctrl.frame_rate_num) ||
+         (enc->enc_pic.rc_layer_init.frame_rate_den != pic->rate_ctrl.frame_rate_den);
    } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
       struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
       need_rate_control = enc->enc_pic.rc_layer_init.target_bit_rate != pic->rc.target_bitrate;

src/gallium/drivers/radeonsi/si_gfx_cs.c

@@ -403,6 +403,10 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
    ctx->flags |= SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE |
                  SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS;
 
+   /* We don't know if the last draw call used GS fast launch, so assume it didn't. */
+   if (ctx->ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
+      ctx->flags |= SI_CONTEXT_VGT_FLUSH;
+
    radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->border_color_buffer,
                              RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
    if (ctx->shadowed_regs) {

src/gallium/drivers/radeonsi/si_shader_nir.c

@@ -288,6 +288,8 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info
       case nir_intrinsic_bindless_image_atomic_xor:
       case nir_intrinsic_bindless_image_atomic_exchange:
       case nir_intrinsic_bindless_image_atomic_comp_swap:
+      case nir_intrinsic_bindless_image_atomic_inc_wrap:
+      case nir_intrinsic_bindless_image_atomic_dec_wrap:
          info->uses_bindless_images = true;
          info->writes_memory = true;
          info->num_memory_instructions++; /* we only care about stores */

src/gallium/drivers/radeonsi/si_state_draw.c

@@ -1911,7 +1911,8 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
          /* Insert a VGT_FLUSH when enabling fast launch changes to prevent hangs.
           * See issues #2418, #2426, #2434
           */
-         if (ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
+         if (ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL &&
+             !(sctx->ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL))
             sctx->flags |= SI_CONTEXT_VGT_FLUSH;
          sctx->ngg_culling = ngg_culling;
          sctx->do_update_shaders = true;

src/gallium/drivers/radeonsi/si_state_shaders.c

@@ -2954,7 +2954,7 @@ bool si_update_ngg(struct si_context *sctx)
        * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
        * pointers are set.
        */
-      if (sctx->chip_class == GFX10 && !new_ngg)
+      if ((sctx->chip_class == GFX10 || sctx->family == CHIP_SIENNA_CICHLID) && !new_ngg)
          sctx->flags |= SI_CONTEXT_VGT_FLUSH;
 
       sctx->ngg = new_ngg;

src/gallium/drivers/svga/svga_resource_buffer_upload.c

@@ -229,12 +229,12 @@ svga_buffer_create_host_surface(struct svga_screen *ss,
       /* Add the new surface to the buffer surface list */
       ret = svga_buffer_add_host_surface(sbuf, sbuf->handle, &sbuf->key,
                                          bind_flags);
-   }
 
-   if (ss->sws->have_gb_objects) {
-      /* Initialize the surface with zero */
-      ss->sws->surface_init(ss->sws, sbuf->handle, svga_surface_size(&sbuf->key),
-                            sbuf->key.flags);
+      if (ss->sws->have_gb_objects) {
+         /* Initialize the surface with zero */
+         ss->sws->surface_init(ss->sws, sbuf->handle, svga_surface_size(&sbuf->key),
+                               sbuf->key.flags);
+      }
    }
 
    return ret;

src/gallium/frontends/dri/dri_screen.c

@@ -73,6 +73,8 @@ dri_fill_st_options(struct dri_screen *screen)
       driQueryOptionb(optionCache, "force_glsl_extensions_warn");
    options->force_glsl_version =
       driQueryOptioni(optionCache, "force_glsl_version");
+   options->allow_extra_pp_tokens =
+      driQueryOptionb(optionCache, "allow_extra_pp_tokens");
    options->allow_glsl_extension_directive_midshader =
       driQueryOptionb(optionCache, "allow_glsl_extension_directive_midshader");
    options->allow_glsl_120_subset_in_110 =

src/gallium/frontends/va/config.c

@@ -99,7 +99,7 @@ vlVaQueryConfigEntrypoints(VADriverContextP ctx, VAProfile profile,
 				PIPE_VIDEO_CAP_SUPPORTED))
       entrypoint_list[(*num_entrypoints)++] = VAEntrypointEncSlice;
 
-   if (num_entrypoints == 0)
+   if (*num_entrypoints == 0)
       return VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
 
    assert(*num_entrypoints <= ctx->max_entrypoints);

src/gallium/frontends/vdpau/mixer.c

@@ -143,7 +143,7 @@ vlVdpVideoMixerCreate(VdpDevice device,
    }
    ret = VDP_STATUS_INVALID_VALUE;
    if (vmixer->max_layers > 4) {
-      VDPAU_MSG(VDPAU_WARN, "[VDPAU] Max layers > 4 not supported\n", vmixer->max_layers);
+      VDPAU_MSG(VDPAU_WARN, "[VDPAU] Max layers %u > 4 not supported\n", vmixer->max_layers);
       goto no_params;
    }
 

src/gallium/include/frontend/api.h

@@ -220,6 +220,7 @@ struct st_config_options
    bool disable_arb_gpu_shader5;
    bool force_glsl_extensions_warn;
    unsigned force_glsl_version;
+   bool allow_extra_pp_tokens;
    bool allow_glsl_extension_directive_midshader;
    bool allow_glsl_120_subset_in_110;
    bool allow_glsl_builtin_const_expression;

src/gallium/winsys/svga/drm/vmw_surface.c

@@ -44,15 +44,15 @@ vmw_svga_winsys_surface_init(struct svga_winsys_screen *sws,
    struct pb_buffer *pb_buf;
    uint32_t pb_flags;
    struct vmw_winsys_screen *vws = vsrf->screen;
-   pb_flags = PIPE_TRANSFER_READ_WRITE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
+   pb_flags = PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 
    struct pb_manager *provider;
    struct pb_desc desc;
 
-   data = vmw_svga_winsys_buffer_map(&vws->base, vsrf->buf,
-                                     PIPE_TRANSFER_DONTBLOCK | pb_flags);
+   mtx_lock(&vsrf->mutex);
+   data = vmw_svga_winsys_buffer_map(&vws->base, vsrf->buf, pb_flags);
    if (data)
-      goto out_unlock;
+      goto out_mapped;
 
    provider = vws->pools.mob_fenced;
    memset(&desc, 0, sizeof(desc));
@@ -64,24 +64,25 @@ vmw_svga_winsys_surface_init(struct svga_winsys_screen *sws,
 
       data = vmw_svga_winsys_buffer_map(&vws->base, vbuf, pb_flags);
       if (data) {
-         if (vsrf->buf) {
+         vsrf->rebind = TRUE;
+         if (vsrf->buf)
             vmw_svga_winsys_buffer_destroy(&vws->base, vsrf->buf);
-            vsrf->buf = vbuf;
-            goto out_unlock;
-         } else
-            vmw_svga_winsys_buffer_destroy(&vws->base, vbuf);
+         vsrf->buf = vbuf;
+         goto out_mapped;
+      } else {
+         vmw_svga_winsys_buffer_destroy(&vws->base, vbuf);
+         goto out_unlock;
       }
    }
-
-   data = vmw_svga_winsys_buffer_map(&vws->base, vsrf->buf, pb_flags);
-   if (data == NULL)
+   else {
+      /* Cannot create a buffer, just unlock */
       goto out_unlock;
+   }
 
-out_unlock:
+out_mapped:
    mtx_unlock(&vsrf->mutex);
 
-   if (data)
-   {
+   if (data) {
       if (flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT) {
          memset(data, 0, surf_size + sizeof(SVGA3dDXSOState));
       }
@@ -89,8 +90,10 @@ out_unlock:
          memset(data, 0, surf_size);
       }
    }
+
    mtx_lock(&vsrf->mutex);
    vmw_svga_winsys_buffer_unmap(&vsrf->screen->base, vsrf->buf);
+out_unlock:
    mtx_unlock(&vsrf->mutex);
 }
 

src/intel/compiler/brw_fs.cpp

@@ -4987,21 +4987,38 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
           */
          ubld1.MOV(component(header, 3), sampler_handle);
       } else if (is_high_sampler(devinfo, sampler)) {
+         fs_reg sampler_state_ptr =
+            retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD);
+
+         /* Gen11+ sampler message headers include bits in 4:0 which conflict
+          * with the ones included in g0.3 bits 4:0.  Mask them out.
+          */
+         if (devinfo->gen >= 11) {
+            sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
+            ubld1.AND(sampler_state_ptr,
+                      retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
+                      brw_imm_ud(INTEL_MASK(31, 5)));
+         }
+
          if (sampler.file == BRW_IMMEDIATE_VALUE) {
             assert(sampler.ud >= 16);
             const int sampler_state_size = 16; /* 16 bytes */
 
-            ubld1.ADD(component(header, 3),
-                      retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
+            ubld1.ADD(component(header, 3), sampler_state_ptr,
                       brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size));
          } else {
             fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
             ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0));
             ubld1.SHL(tmp, tmp, brw_imm_ud(4));
-            ubld1.ADD(component(header, 3),
-                      retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
-                      tmp);
+            ubld1.ADD(component(header, 3), sampler_state_ptr, tmp);
          }
+      } else if (devinfo->gen >= 11) {
+         /* Gen11+ sampler message headers include bits in 4:0 which conflict
+          * with the ones included in g0.3 bits 4:0.  Mask them out.
+          */
+         ubld1.AND(component(header, 3),
+                   retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
+                   brw_imm_ud(INTEL_MASK(31, 5)));
       }
    }
 
@@ -7606,7 +7623,8 @@ fs_visitor::fixup_3src_null_dest()
 static const fs_inst *
 find_halt_control_flow_region_start(const fs_visitor *v)
 {
-   if (brw_wm_prog_data(v->prog_data)->uses_kill) {
+   if (v->stage == MESA_SHADER_FRAGMENT &&
+       brw_wm_prog_data(v->prog_data)->uses_kill) {
       foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
          if (inst->opcode == FS_OPCODE_DISCARD_JUMP ||
              inst->opcode == FS_OPCODE_PLACEHOLDER_HALT)

src/intel/vulkan/anv_formats.c

@@ -923,6 +923,31 @@ anv_get_image_format_properties(
       }
    }
 
+   if (info->flags & VK_IMAGE_CREATE_DISJOINT_BIT) {
+      /* From the Vulkan 1.2.149 spec, VkImageCreateInfo:
+       *
+       *    If format is a multi-planar format, and if imageCreateFormatFeatures
+       *    (as defined in Image Creation Limits) does not contain
+       *    VK_FORMAT_FEATURE_DISJOINT_BIT, then flags must not contain
+       *    VK_IMAGE_CREATE_DISJOINT_BIT.
+       */
+      if (format->n_planes > 1 &&
+          !(format_feature_flags & VK_FORMAT_FEATURE_DISJOINT_BIT)) {
+         goto unsupported;
+      }
+
+      /* From the Vulkan 1.2.149 spec, VkImageCreateInfo:
+       *
+       * If format is not a multi-planar format, and flags does not include
+       * VK_IMAGE_CREATE_ALIAS_BIT, flags must not contain
+       * VK_IMAGE_CREATE_DISJOINT_BIT.
+       */
+      if (format->n_planes == 1 &&
+          !(info->flags & VK_IMAGE_CREATE_ALIAS_BIT)) {
+          goto unsupported;
+      }
+   }
+
    if (info->usage & VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT) {
       /* Nothing to check. */
    }

src/intel/vulkan/anv_gem.c

@@ -105,7 +105,6 @@ anv_gem_mmap_legacy(struct anv_device *device, uint32_t gem_handle,
    if (ret != 0)
       return MAP_FAILED;
 
-   VG(VALGRIND_MALLOCLIKE_BLOCK(gem_mmap.addr_ptr, gem_mmap.size, 0, 1));
    return (void *)(uintptr_t) gem_mmap.addr_ptr;
 }
 
@@ -116,10 +115,16 @@ void*
 anv_gem_mmap(struct anv_device *device, uint32_t gem_handle,
              uint64_t offset, uint64_t size, uint32_t flags)
 {
+   void *map;
    if (device->physical->has_mmap_offset)
-      return anv_gem_mmap_offset(device, gem_handle, offset, size, flags);
+      map = anv_gem_mmap_offset(device, gem_handle, offset, size, flags);
    else
-      return anv_gem_mmap_legacy(device, gem_handle, offset, size, flags);
+      map = anv_gem_mmap_legacy(device, gem_handle, offset, size, flags);
+
+   if (map != MAP_FAILED)
+      VG(VALGRIND_MALLOCLIKE_BLOCK(map, size, 0, 1));
+
+   return map;
 }
 
 /* This is just a wrapper around munmap, but it also notifies valgrind that
@@ -128,8 +133,7 @@ anv_gem_mmap(struct anv_device *device, uint32_t gem_handle,
 void
 anv_gem_munmap(struct anv_device *device, void *p, uint64_t size)
 {
-   if (!device->physical->has_mmap_offset)
-      VG(VALGRIND_FREELIKE_BLOCK(p, 0));
+   VG(VALGRIND_FREELIKE_BLOCK(p, 0));
    munmap(p, size);
 }
 

src/intel/vulkan/anv_image.c

@@ -540,14 +540,14 @@ make_surface(struct anv_device *device,
       anv_get_format_plane(&device->info, image->vk_format, aspect, image->tiling);
    struct anv_surface *anv_surf = &image->planes[plane].surface;
 
-   const isl_surf_usage_flags_t usage =
-      choose_isl_surf_usage(image->create_flags, image->usage,
-                            isl_extra_usage_flags, aspect);
-
    VkImageUsageFlags plane_vk_usage =
       aspect == VK_IMAGE_ASPECT_STENCIL_BIT ?
       image->stencil_usage : image->usage;
 
+   const isl_surf_usage_flags_t usage =
+      choose_isl_surf_usage(image->create_flags, plane_vk_usage,
+                            isl_extra_usage_flags, aspect);
+
    bool needs_shadow =
       anv_image_plane_needs_shadow_surface(&device->info,
                                    plane_format,

src/mesa/drivers/dri/i965/brw_bufmgr.c

@@ -1947,7 +1947,8 @@ brw_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd, bool bo_reuse)
    }
 
    bufmgr = brw_bufmgr_create(devinfo, fd, bo_reuse);
-   list_addtail(&bufmgr->link, &global_bufmgr_list);
+   if (bufmgr)
+      list_addtail(&bufmgr->link, &global_bufmgr_list);
 
  unlock:
    mtx_unlock(&global_bufmgr_list_mutex);

src/mesa/drivers/dri/i965/intel_screen.c

@@ -84,6 +84,7 @@ DRI_CONF_BEGIN
       DRI_CONF_FORCE_GLSL_VERSION(0)
       DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
       DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
+      DRI_CONF_ALLOW_EXTRA_PP_TOKENS("false")
       DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
       DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
       DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")

src/mesa/main/clear.c

@@ -30,6 +30,7 @@
 
 
 
+#include "glformats.h"
 #include "glheader.h"
 #include "clear.h"
 #include "context.h"
@@ -589,7 +590,20 @@ clear_bufferfv(struct gl_context *ctx, GLenum buffer, GLint drawbuffer,
           * hook instead.
           */
          const GLclampd clearSave = ctx->Depth.Clear;
-         ctx->Depth.Clear = *value;
+
+         /* Page 263 (page 279 of the PDF) of the OpenGL 3.0 spec says:
+          *
+          *     "If buffer is DEPTH, drawbuffer must be zero, and value points
+          *     to the single depth value to clear the depth buffer to.
+          *     Clamping and type conversion for fixed-point depth buffers are
+          *     performed in the same fashion as for ClearDepth."
+          */
+         const struct gl_renderbuffer *rb =
+            ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
+         const bool is_float_depth =
+            _mesa_has_depth_float_channel(rb->InternalFormat);
+         ctx->Depth.Clear = is_float_depth ? *value : SATURATE(*value);
+
          ctx->Driver.Clear(ctx, BUFFER_BIT_DEPTH);
          ctx->Depth.Clear = clearSave;
       }
@@ -724,8 +738,20 @@ clear_bufferfi(struct gl_context *ctx, GLenum buffer, GLint drawbuffer,
       const GLclampd clearDepthSave = ctx->Depth.Clear;
       const GLuint clearStencilSave = ctx->Stencil.Clear;
 
-      /* set new clear values */
-      ctx->Depth.Clear = depth;
+      /* set new clear values
+       *
+       * Page 263 (page 279 of the PDF) of the OpenGL 3.0 spec says:
+       *
+       *     "depth and stencil are the values to clear the depth and stencil
+       *     buffers to, respectively. Clamping and type conversion for
+       *     fixed-point depth buffers are performed in the same fashion as
+       *     for ClearDepth."
+       */
+      const struct gl_renderbuffer *rb =
+         ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
+      const bool has_float_depth = rb &&
+         _mesa_has_depth_float_channel(rb->InternalFormat);
+      ctx->Depth.Clear = has_float_depth ? depth : SATURATE(depth);
       ctx->Stencil.Clear = stencil;
 
       /* clear buffers */

src/mesa/main/get.c

@@ -1704,6 +1704,7 @@ get_value_size(enum value_type type, const union value *v)
    case TYPE_MATRIX_T:
       return sizeof (GLfloat) * 16;
    default:
+      assert(!"invalid value_type given for get_value_size()");
       return -1;
    }
 }
@@ -2349,9 +2350,6 @@ _mesa_GetUnsignedBytevEXT(GLenum pname, GLubyte *data)
 
    d = find_value(func, pname, &p, &v);
    size = get_value_size(d->type, &v);
-   if (size <= 0) {
-      _mesa_problem(ctx, "invalid value type in GetUnsignedBytevEXT()");
-   }
 
    switch (d->type) {
    case TYPE_BIT_0:
@@ -3262,9 +3260,6 @@ _mesa_GetUnsignedBytei_vEXT(GLenum target, GLuint index, GLubyte *data)
 
    type = find_value_indexed(func, target, index, &v);
    size = get_value_size(type, &v);
-   if (size <= 0) {
-      _mesa_problem(ctx, "invalid value type in GetUnsignedBytei_vEXT()");
-   }
 
    switch (type) {
    case TYPE_UINT:

src/mesa/main/glformats.c

@@ -1335,6 +1335,15 @@ _mesa_is_depth_or_stencil_format(GLenum format)
    }
 }
 
+/**
+ * Test if the given image format has a floating-point depth component.
+ */
+GLboolean
+_mesa_has_depth_float_channel(GLenum internalFormat)
+{
+   return internalFormat == GL_DEPTH32F_STENCIL8 ||
+          internalFormat == GL_DEPTH_COMPONENT32F;
+}
 
 /**
  * Test if an image format is a supported compressed format.

src/mesa/main/glformats.h

@@ -29,6 +29,7 @@
 
 
 #include <stdbool.h>
+#include <stdint.h>
 #include <GL/gl.h>
 
 
@@ -104,6 +105,9 @@ _mesa_is_depthstencil_format(GLenum format);
 extern GLboolean
 _mesa_is_depth_or_stencil_format(GLenum format);
 
+extern GLboolean
+_mesa_has_depth_float_channel(GLenum internalFormat);
+
 extern GLboolean
 _mesa_is_compressed_format(const struct gl_context *ctx, GLenum format);
 

src/mesa/main/glspirv.c

@@ -295,6 +295,13 @@ _mesa_spirv_to_nir(struct gl_context *ctx,
    }
    assert(exec_list_length(&nir->functions) == 1);
 
+   /* Now that we've deleted all but the main function, we can go ahead and
+    * lower the rest of the constant initializers.  We do this here so that
+    * nir_remove_dead_variables and split_per_member_structs below see the
+    * corresponding stores.
+    */
+   NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
+
    /* Split member structs.  We do this before lower_io_to_temporaries so that
     * it doesn't lower system values to temporaries by accident.
     */

src/mesa/main/mtypes.h

@@ -3875,6 +3875,14 @@ struct gl_constants
     */
    GLboolean AllowLayoutQualifiersOnFunctionParameters;
 
+   /**
+    * Allow extra tokens at end of preprocessor directives. The CTS now tests
+    * to make sure these are not allowed. However, previously drivers would
+    * allow them to exist and just issue a warning so some old applications
+    * depend on this.
+    */
+   GLboolean AllowExtraPPTokens;
+
    /**
     * Force computing the absolute value for sqrt() and inversesqrt() to follow
     * D3D9 when apps rely on this behaviour.

src/mesa/main/readpix.c

@@ -910,8 +910,7 @@ read_pixels_es3_error_check(struct gl_context *ctx, GLenum format, GLenum type,
    const GLenum data_type = _mesa_get_format_datatype(rb->Format);
    GLboolean is_unsigned_int = GL_FALSE;
    GLboolean is_signed_int = GL_FALSE;
-   GLboolean is_float_depth = (internalFormat == GL_DEPTH_COMPONENT32F) ||
-         (internalFormat == GL_DEPTH32F_STENCIL8);
+   GLboolean is_float_depth = _mesa_has_depth_float_channel(internalFormat);
 
    is_unsigned_int = _mesa_is_enum_format_unsigned_int(internalFormat);
    if (!is_unsigned_int) {

src/mesa/main/varray.c

@@ -459,8 +459,7 @@ static const uint16_t vertex_formats[][4][4] = {
  */
 static enum pipe_format
 vertex_format_to_pipe_format(GLubyte size, GLenum16 type, GLenum16 format,
-                             GLboolean normalized, GLboolean integer,
-                             GLboolean doubles)
+                             bool normalized, bool integer, bool doubles)
 {
    assert(size >= 1 && size <= 4);
    assert(format == GL_RGBA || format == GL_BGRA);
@@ -674,8 +673,8 @@ validate_array_format(struct gl_context *ctx, const char *func,
                       struct gl_vertex_array_object *vao,
                       GLuint attrib, GLbitfield legalTypesMask,
                       GLint sizeMin, GLint sizeMax,
-                      GLint size, GLenum type, GLboolean normalized,
-                      GLboolean integer, GLboolean doubles,
+                      GLint size, GLenum type, bool normalized,
+                      bool integer, bool doubles,
                       GLuint relativeOffset, GLenum format)
 {
    GLbitfield typeBit;

src/mesa/state_tracker/st_cb_eglimage.c

@@ -327,7 +327,9 @@ st_egl_image_target_texture_2d(struct gl_context *ctx, GLenum target,
                          &native_supported))
       return;
 
-   st_bind_egl_image(ctx, texObj, texImage, &stimg, false, native_supported);
+   st_bind_egl_image(ctx, texObj, texImage, &stimg,
+                     target != GL_TEXTURE_EXTERNAL_OES,
+                     native_supported);
    pipe_resource_reference(&stimg.texture, NULL);
 }
 

src/mesa/state_tracker/st_cb_memoryobjects.c

@@ -59,7 +59,8 @@ st_memoryobj_free(struct gl_context *ctx,
    struct pipe_context *pipe = st->pipe;
    struct pipe_screen *screen = pipe->screen;
 
-   screen->memobj_destroy(screen, st_obj->memory);
+   if (st_obj->memory)
+      screen->memobj_destroy(screen, st_obj->memory);
    _mesa_delete_memory_object(ctx, obj);
 }
 

src/mesa/state_tracker/st_extensions.c

@@ -1124,6 +1124,8 @@ void st_init_extensions(struct pipe_screen *screen,
       consts->ForceGLSLVersion = options->force_glsl_version;
    }
 
+   consts->AllowExtraPPTokens = options->allow_extra_pp_tokens;
+
    consts->AllowHigherCompatVersion = options->allow_higher_compat_version;
 
    consts->ForceGLSLAbsSqrt = options->force_glsl_abs_sqrt;

src/util/00-mesa-defaults.conf

@@ -246,6 +246,10 @@ TODO: document the other workarounds.
             <option name="allow_glsl_layout_qualifier_on_function_parameters" value="true" />
         </application>
 
+        <application name="Champions of Regnum" executable="game">
+            <option name="allow_extra_pp_tokens" value="true" />
+        </application>
+
         <application name="Wolfenstein The Old Blood" executable="WolfOldBlood_x64.exe">
             <option name="force_compat_profile" value="true" />
         </application>

src/util/driconf.h

@@ -157,6 +157,11 @@ DRI_CONF_OPT_BEGIN_V(force_glsl_version, int, def, "0:999") \
         DRI_CONF_DESC("Force a default GLSL version for shaders that lack an explicit #version line") \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_ALLOW_EXTRA_PP_TOKENS(def) \
+DRI_CONF_OPT_BEGIN_B(allow_extra_pp_tokens, def) \
+    DRI_CONF_DESC("Allow extra tokens at end of preprocessor directives.") \
+DRI_CONF_OPT_END
+
 #define DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER(def) \
 DRI_CONF_OPT_BEGIN_B(allow_glsl_extension_directive_midshader, def) \
         DRI_CONF_DESC("Allow GLSL #extension directives in the middle of shaders") \

src/util/set.c

@@ -203,13 +203,17 @@ _mesa_set_clear(struct set *set, void (*delete_function)(struct set_entry *entry
    if (!set)
       return;
 
-   set_foreach (set, entry) {
-      if (delete_function)
+   struct set_entry *entry;
+
+   for (entry = set->table; entry != set->table + set->size; entry++) {
+      if (entry_is_present(entry) && delete_function != NULL)
          delete_function(entry);
-      entry->key = deleted_key;
+
+      entry->key = NULL;
    }
 
-   set->entries = set->deleted_entries = 0;
+   set->entries = 0;
+   set->deleted_entries = 0;
 }
 
 /**