docs: update sha256 for 22.0.5

These were spilled unconditionally.

Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16708>
(cherry picked from commit 8e41c66639)

.editorconfig

@@ -16,26 +16,14 @@ max_line_length = 78
 [{Makefile*,*.mk}]
 indent_style = tab
 
-[{*.py,SCons*}]
+[*.py]
 indent_style = space
 indent_size = 4
 
-[*.pl]
-indent_style = space
-indent_size = 4
-
-[*.m4]
-indent_style = space
-indent_size = 2
-
 [*.yml]
 indent_style = space
 indent_size = 2
 
-[*.html]
-indent_style = space
-indent_size = 2
-
 [*.rst]
 indent_style = space
 indent_size = 3

VERSION

@@ -1 +1 @@
-22.0.4
+22.0.5

docs/drivers/zink.rst

@@ -29,8 +29,6 @@ Here's a list of those requirements:
 
   * ``logicOp``
   * ``fillModeNonSolid``
-  * ``wideLines``
-  * ``largePoints``
   * ``alphaToOne``
   * ``shaderClipDistance``
 

docs/relnotes/22.0.4.rst

@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-    TBD.
+   c7971f58fa826e474617cda53250c6600fce60994b9fac5b641522e21f471ed4  mesa-22.0.4.tar.xz
 
 
 New features

docs/relnotes/22.0.5.rst

@@ -0,0 +1,139 @@
+Mesa 22.0.5 Release Notes / 2022-06-01
+======================================
+
+Mesa 22.0.5 is a bug fix release which fixes bugs found since the 22.0.4 release.
+
+Mesa 22.0.5 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.0.5 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+   5ee2dc06eff19e19b2867f12eb0db0905c9691c07974f6253f2f1443df4c7a35  mesa-22.0.5.tar.xz
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- nir_lower_phis_to_regs_block: Assertion \`src->src.is_ssa' failed.
+- Build failure on sparc
+- Signal 6 (Aborted) when opening GTK3 applications
+- radv: Conditional rendering on compute queue
+- anv: line failure
+- panfrost midgard - major issues with MelonDS emulator - not able to trace properly too
+- Nheko misrendering on RK3399 (Mali T860)
+
+
+Changes
+-------
+
+Daniel Schürmann (1):
+
+- aco: fix spilling of phis without temp operands
+
+Dave Airlie (2):
+
+- meson: add build-id to pipe libraries
+- lavapipe: fix depth bias offset flag enables.
+
+Dylan Baker (6):
+
+- docs: add sha256sum to 22.0.4 notes
+- .pick_status.json: Update to 95d4e5435bf63239105a50370ebbbbdeb7fed2f8
+- .pick_status.json: Update to ee2278de654853f1d6107e6ef6fc8537a668866e
+- .pick_status.json: Update to 9773ed1dc74b98019640d909cdc2b5d6cffae85a
+- .pick_status.json: Update to 5067a26f4432ae5e9690e70ef2498ea24798593e
+- .pick_status.json: Update to 1c63a0beafefccec599ddbe355ec5a8b61df6438
+
+Erik Faye-Lund (4):
+
+- editorconfig: remove scons-ism
+- editorconfig: remove html-rule
+- editorconfig: remove m4-rule
+- editorconfig: remove pl-rule
+
+Filip Gawin (1):
+
+- r300: keep negation if w is an inline constant
+
+Hans-Kristian Arntzen (1):
+
+- radv: Fix RTPSO hashing of pGroups.
+
+Icecream95 (5):
+
+- panfrost: Copy blend constant into variant even when reusing it
+- nir: Add store_combined_output_pan BASE back
+- pan/bi: Read base for combined stores
+- pan/mdg: Read base for combined stores
+- panfrost: Only write depth / stencil once if MRT is used
+
+Jason Ekstrand (6):
+
+- intel/fs: Copy color_outputs_valid into wm_prog_data
+- anv: Drop alpha_to_coverage from the NULL FS optimization
+- anv: Handle the null FS optimization after compiling shaders
+- anv: Don't disable the fragment shader if XFB is enabled
+- nir: Handle register sources in lower_phis_to_regs_block
+- glsl/nir: Stop leaking varyings_info
+
+Matt Turner (1):
+
+- mesa: Drop dead #include "sparc/sparc.h"
+
+Michael Skorokhodov (1):
+
+- anv: Update line range
+
+Mike Blumenkrantz (13):
+
+- spirv: fix barrier scope assert
+- zink: only reject non-blittable resource creation if it has no other binds
+- zink: add extra validation for resource creation
+- zink: remove input attachment usage when pruning surface usage
+- zink: add extended usage and retry if resource creation fails
+- zink: fix surface/bufferview cache comparisons
+- zink: force render target usage for sampler-only resources
+- zink: fix non-dynamic vertex stride update flagging
+- turnip: fix assert for max xfb outputs
+- zink: require draw params ext/cap in ntv if drawid is used
+- zink: emit spirv cap for subgroup vote ops
+- zink: drop wideLines requirement
+- zink: drop largePoints requirement
+
+Pierre-Eric Pelloux-Prayer (2):
+
+- glx: set max values for pbuffer width / height
+- radeonsi: don't use sel->nir in si_check_blend_dst_sampler_noop
+
+Qiang Yu (1):
+
+- radeonsi: lower nir_intrinsic_sparse_residency_code_and
+
+Rhys Perry (1):
+
+- aco: fix p_constaddr with a non-zero offset
+
+Samuel Pitoiset (1):
+
+- radv: fix writing buffer markers with non-zero memory offset
+
+Timur Kristóf (1):
+
+- radv: Implement conditional rendering for async compute queue.

src/amd/compiler/aco_assembler.cpp

@@ -82,10 +82,12 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
       instr->opcode = aco_opcode::s_getpc_b64;
       instr->operands.pop_back();
    } else if (instr->opcode == aco_opcode::p_constaddr_addlo) {
-      ctx.constaddrs[instr->operands[1].constantValue()].add_literal = out.size() + 1;
+      ctx.constaddrs[instr->operands[2].constantValue()].add_literal = out.size() + 1;
 
       instr->opcode = aco_opcode::s_add_u32;
-      instr->operands[1] = Operand::zero();
+      instr->operands.pop_back();
+      assert(instr->operands[1].isConstant());
+      /* in case it's an inline constant, make it a literal */
       instr->operands[1].setFixed(PhysReg(255));
    }
 

src/amd/compiler/aco_lower_to_hw_instr.cpp

@@ -2100,7 +2100,7 @@ lower_to_hw_instr(Program* program)
                PhysReg reg = instr->definitions[0].physReg();
                bld.sop1(aco_opcode::p_constaddr_getpc, instr->definitions[0], Operand::c32(id));
                bld.sop2(aco_opcode::p_constaddr_addlo, Definition(reg, s1), bld.def(s1, scc),
-                        Operand(reg, s1), Operand::c32(id));
+                        Operand(reg, s1), instr->operands[0], Operand::c32(id));
                bld.sop2(aco_opcode::s_addc_u32, Definition(reg.advance(4), s1), bld.def(s1, scc),
                         Operand(reg.advance(4), s1), Operand::zero(), Operand(scc, s1));
                break;

src/amd/compiler/aco_spill.cpp

@@ -697,25 +697,22 @@ init_live_in_vars(spill_ctx& ctx, Block* block, unsigned block_idx)
 
       std::vector<unsigned>& preds =
          phi->opcode == aco_opcode::p_phi ? block->logical_preds : block->linear_preds;
-      bool spill = true;
-
+      bool is_all_spilled = true;
       for (unsigned i = 0; i < phi->operands.size(); i++) {
-         /* non-temp operands can increase the register pressure */
-         if (!phi->operands[i].isTemp()) {
-            partial_spills.insert(phi->definitions[0].getTemp());
+         if (phi->operands[i].isUndefined())
             continue;
-         }
-
-         if (!ctx.spills_exit[preds[i]].count(phi->operands[i].getTemp()))
-            spill = false;
-         else
-            partial_spills.insert(phi->definitions[0].getTemp());
+         is_all_spilled &= phi->operands[i].isTemp() &&
+                           ctx.spills_exit[preds[i]].count(phi->operands[i].getTemp());
       }
-      if (spill) {
+
+      if (is_all_spilled) {
+         /* The phi is spilled at all predecessors. Keep it spilled. */
          ctx.spills_entry[block_idx][phi->definitions[0].getTemp()] =
             ctx.allocate_spill_id(phi->definitions[0].regClass());
-         partial_spills.erase(phi->definitions[0].getTemp());
          spilled_registers += phi->definitions[0].getTemp();
+      } else {
+         /* Phis might increase the register pressure. */
+         partial_spills.insert(phi->definitions[0].getTemp());
       }
    }
 

src/amd/compiler/tests/test_assembler.cpp

@@ -222,7 +222,7 @@ BEGIN_TEST(assembler.long_jump.constaddr)
    //! s_add_u32 s0, s0, 0xe0                                      ; 8000ff00 000000e0
    bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg(0), s2), Operand::zero());
    bld.sop2(aco_opcode::p_constaddr_addlo, Definition(PhysReg(0), s1), bld.def(s1, scc),
-            Operand(PhysReg(0), s1), Operand::zero());
+            Operand(PhysReg(0), s1), Operand::zero(), Operand::zero());
 
    program->blocks[2].linear_preds.push_back(0u);
    program->blocks[2].linear_preds.push_back(1u);

src/amd/vulkan/radv_cmd_buffer.c

@@ -6034,6 +6034,26 @@ radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
    }
 }
 
+/**
+ * Emulates predication for MEC using COND_EXEC.
+ * When the current command buffer is predicating, emit a COND_EXEC packet
+ * so that the MEC skips the next few dwords worth of packets.
+ */
+static void
+radv_cs_emit_compute_predication(struct radv_cmd_buffer *cmd_buffer, unsigned dwords)
+{
+   if (!cmd_buffer->state.predicating)
+      return;
+
+   struct radeon_cmdbuf *cs = cmd_buffer->cs;
+
+   radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0));
+   radeon_emit(cs, cmd_buffer->state.predication_va);
+   radeon_emit(cs, cmd_buffer->state.predication_va >> 32);
+   radeon_emit(cs, 0); /* Cache policy */
+   radeon_emit(cs, dwords); /* Size of the predicated packet(s) in DWORDs. */
+}
+
 static void
 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint32_t vertex_count,
                          uint32_t use_opaque)
@@ -7195,7 +7215,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipel
 
    loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
 
-   ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 25);
+   ASSERTED unsigned cdw_max = radeon_check_space(ws, cs, 30);
 
    if (compute_shader->info.wave_size == 32) {
       assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);
@@ -7218,7 +7238,8 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipel
       }
 
       if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
-         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) | PKT3_SHADER_TYPE_S(1));
+         radv_cs_emit_compute_predication(cmd_buffer, 4 /* DISPATCH_INDIRECT size */);
+         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) | PKT3_SHADER_TYPE_S(1));
          radeon_emit(cs, info->va);
          radeon_emit(cs, info->va >> 32);
          radeon_emit(cs, dispatch_initiator);
@@ -7289,6 +7310,11 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipel
          dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
       }
 
+      if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
+         radv_cs_emit_compute_predication(cmd_buffer, 5 /* DISPATCH_DIRECT size */);
+         predicating = false;
+      }
+
       radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) | PKT3_SHADER_TYPE_S(1));
       radeon_emit(cs, blocks[0]);
       radeon_emit(cs, blocks[1]);
@@ -8624,11 +8650,59 @@ radv_CmdBeginConditionalRenderingEXT(
       pred_op = PREDICATION_OP_BOOL64;
    }
 
-   /* Enable predication for this command buffer. */
-   si_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va);
-   cmd_buffer->state.predicating = true;
+
+   if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
+      /* MEC does not support real predication, so we have to emulate that
+       * using COND_EXEC packets before each dispatch.
+       */
+
+      if (!draw_visible) {
+         /* COND_EXEC can only skip the next packet(s) when the condition is 0.
+          * When using inverted conditional rendering, we allocate some space in
+          * the upload BO and emit some packets to invert the condition.
+          */
+
+         uint64_t pred_value = 0, pred_va;
+         unsigned pred_offset;
+
+         radv_cmd_buffer_upload_data(cmd_buffer, 4, &pred_value, &pred_offset);
+         pred_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
+
+         /* Write 1 to the new predication VA. */
+         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
+                         COPY_DATA_WR_CONFIRM);
+         radeon_emit(cs, 1);
+         radeon_emit(cs, 0);
+         radeon_emit(cs, pred_va);
+         radeon_emit(cs, pred_va >> 32);
+
+         /* If the API predication VA == 0, skip next command. */
+         radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0));
+         radeon_emit(cs, va);
+         radeon_emit(cs, va >> 32);
+         radeon_emit(cs, 0);
+         radeon_emit(cs, 6); /* 1x COPY_DATA size */
+
+         /* Write 0 to the new predication VA (when the API condition != 0) */
+         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
+                         COPY_DATA_WR_CONFIRM);
+         radeon_emit(cs, 0);
+         radeon_emit(cs, 0);
+         radeon_emit(cs, pred_va);
+         radeon_emit(cs, pred_va >> 32);
+
+         va = pred_va;
+         draw_visible = true;
+      }
+   } else {
+      /* Enable predication for this command buffer. */
+      si_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va);
+   }
 
    /* Store conditional rendering user info. */
+   cmd_buffer->state.predicating = true;
    cmd_buffer->state.predication_type = draw_visible;
    cmd_buffer->state.predication_op = pred_op;
    cmd_buffer->state.predication_va = va;
@@ -8639,11 +8713,16 @@ radv_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)
 {
    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   /* Disable predication for this command buffer. */
-   si_emit_set_predication_state(cmd_buffer, false, 0, 0);
-   cmd_buffer->state.predicating = false;
+   /* Note, MEC doesn't support predication, so we
+    * don't have to emit anything for MEC here.
+    */
+   if (!radv_cmd_buffer_uses_mec(cmd_buffer)) {
+      /* Disable predication for this command buffer. */
+      si_emit_set_predication_state(cmd_buffer, false, 0, 0);
+   }
 
    /* Reset conditional rendering user info. */
+   cmd_buffer->state.predicating = false;
    cmd_buffer->state.predication_type = -1;
    cmd_buffer->state.predication_op = 0;
    cmd_buffer->state.predication_va = 0;
@@ -9035,7 +9114,7 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag
    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
    RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
    struct radeon_cmdbuf *cs = cmd_buffer->cs;
-   uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
+   uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset + dstOffset;
 
    si_emit_cache_flush(cmd_buffer);
 

src/amd/vulkan/radv_pipeline_cache.c

@@ -172,8 +172,18 @@ radv_hash_rt_shaders(unsigned char *hash, const VkRayTracingPipelineCreateInfoKH
       }
    }
 
-   _mesa_sha1_update(&ctx, pCreateInfo->pGroups,
-                     pCreateInfo->groupCount * sizeof(*pCreateInfo->pGroups));
+   for (uint32_t i = 0; i < pCreateInfo->groupCount; i++) {
+      _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].type,
+                        sizeof(pCreateInfo->pGroups[i].type));
+      _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].generalShader,
+                        sizeof(pCreateInfo->pGroups[i].generalShader));
+      _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].anyHitShader,
+                        sizeof(pCreateInfo->pGroups[i].anyHitShader));
+      _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].closestHitShader,
+                        sizeof(pCreateInfo->pGroups[i].closestHitShader));
+      _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].intersectionShader,
+                        sizeof(pCreateInfo->pGroups[i].intersectionShader));
+   }
 
    if (!radv_rt_pipeline_has_dynamic_stack_size(pCreateInfo))
       _mesa_sha1_update(&ctx, &pCreateInfo->maxPipelineRayRecursionDepth, 4);

src/compiler/glsl/gl_nir_link_xfb.c

@@ -193,4 +193,5 @@ gl_nir_link_assign_xfb_resources(const struct gl_constants *consts,
    linked_xfb->ActiveBuffers = buffers;
 
    ralloc_free(xfb_info);
+   ralloc_free(varyings_info);
 }

src/compiler/nir/nir_from_ssa.c

@@ -1006,10 +1006,16 @@ nir_lower_phis_to_regs_block(nir_block *block)
       nir_ssa_def_rewrite_uses(&phi->dest.ssa, def);
 
       nir_foreach_phi_src(src, phi) {
-         assert(src->src.is_ssa);
-         _mesa_set_add(visited_blocks, src->src.ssa->parent_instr->block);
-         place_phi_read(&b, reg, src->src.ssa, src->pred, visited_blocks);
-         _mesa_set_clear(visited_blocks, NULL);
+         if (src->src.is_ssa) {
+            _mesa_set_add(visited_blocks, src->src.ssa->parent_instr->block);
+            place_phi_read(&b, reg, src->src.ssa, src->pred, visited_blocks);
+            _mesa_set_clear(visited_blocks, NULL);
+         } else {
+            b.cursor = nir_after_block_before_jump(src->pred);
+            nir_ssa_def *src_ssa =
+               nir_ssa_for_src(&b, src->src, phi->dest.ssa.num_components);
+            nir_store_reg(&b, reg, src_ssa, ~0);
+         }
       }
 
       nir_instr_remove(&phi->instr);

src/compiler/nir/nir_intrinsics.py

@@ -1153,7 +1153,7 @@ intrinsic("shared_atomic_comp_swap_dxil", src_comp=[1, 1, 1], dest_comp=1)
 
 # src[] = { value }
 store("raw_output_pan", [], [])
-store("combined_output_pan", [1, 1, 1, 4], [COMPONENT, SRC_TYPE, DEST_TYPE])
+store("combined_output_pan", [1, 1, 1, 4], [BASE, COMPONENT, SRC_TYPE, DEST_TYPE])
 load("raw_output_pan", [1], [BASE], [CAN_ELIMINATE, CAN_REORDER])
 
 # Loads the sampler paramaters <min_lod, max_lod, lod_bias>

src/compiler/spirv/spirv_to_nir.c

@@ -4128,8 +4128,8 @@ vtn_emit_memory_barrier(struct vtn_builder *b, SpvScope scope,
       return;
    }
 
-   /* There's only two scopes thing left */
-   vtn_assert(scope == SpvScopeInvocation || scope == SpvScopeDevice);
+   /* There's only three scopes left */
+   vtn_assert(scope == SpvScopeInvocation || scope == SpvScopeDevice || scope == SpvScopeQueueFamily);
 
    /* Map the GLSL memoryBarrier() construct and any barriers with more than one
     * semantic to the corresponding NIR one.

src/freedreno/vulkan/tu_shader.c

@@ -680,7 +680,7 @@ tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
          output_map[var->data.location + i] = var->data.driver_location + i;
    }
 
-   assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
+   assert(xfb->output_count <= IR3_MAX_SO_OUTPUTS);
    info->num_outputs = xfb->output_count;
 
    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++) {

src/gallium/drivers/r300/compiler/radeon_dataflow_swizzles.c

@@ -29,6 +29,8 @@
  * Tom Stellard <thomas.stellard@amd.com>
  */
 
+#include <stdbool.h>
+
 #include "radeon_dataflow.h"
 
 #include "radeon_code.h"
@@ -97,6 +99,7 @@ static unsigned try_rewrite_constant(struct radeon_compiler *c,
 {
 	unsigned new_swizzle, chan, swz0, swz1, swz2, swz3, found_swizzle, swz;
 	unsigned all_inline = 0;
+	bool w_inline_constant = false;
 	float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f};
 
 	if (!rc_src_reg_is_immediate(c, reg->File, reg->Index)) {
@@ -321,7 +324,9 @@ static unsigned try_rewrite_constant(struct radeon_compiler *c,
 	swz3 = GET_SWZ(reg->Swizzle, 3);
 
 	/* We can skip this if the swizzle in channel w is an inline constant. */
-	if (swz3 <= RC_SWIZZLE_W) {
+	if (is_swizzle_inline_constant(swz3)) {
+		w_inline_constant = true;
+	} else {
 		for (chan = 0; chan < 3; chan++) {
 			unsigned old_swz = GET_SWZ(reg->Swizzle, chan);
 			unsigned new_swz = GET_SWZ(new_swizzle, chan);
@@ -372,7 +377,7 @@ static unsigned try_rewrite_constant(struct radeon_compiler *c,
 		 *
 		 * Swizzles with a value > RC_SWIZZLE_W are inline constants.
 		 */
-		if (chan == 3 && old_swz > RC_SWIZZLE_W) {
+		if (chan == 3 && w_inline_constant) {
 			continue;
 		}
 
@@ -409,7 +414,7 @@ static unsigned try_rewrite_constant(struct radeon_compiler *c,
 	 * ONE, ZERO, HALF).
 	 */
 	reg->File = RC_FILE_CONSTANT;
-	reg->Negate = 0;
+	reg->Negate = w_inline_constant ? reg->Negate & (1 << 3) : 0;
 	return 1;
 }
 

src/gallium/drivers/r300/compiler/radeon_program_constants.h

@@ -115,6 +115,11 @@ typedef enum {
 	RC_SWIZZLE_UNUSED
 } rc_swizzle;
 
+static inline int is_swizzle_inline_constant(rc_swizzle swizzle){
+	return swizzle >= RC_SWIZZLE_ZERO;
+
+}
+
 #define RC_MAKE_SWIZZLE(a,b,c,d) (((a)<<0) | ((b)<<3) | ((c)<<6) | ((d)<<9))
 #define RC_MAKE_SWIZZLE_SMEAR(a) RC_MAKE_SWIZZLE((a),(a),(a),(a))
 #define GET_SWZ(swz, idx)      (((swz) >> ((idx)*3)) & 0x7)

src/gallium/drivers/radeonsi/si_shader_nir.c

@@ -325,6 +325,8 @@ lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy)
    case nir_intrinsic_is_sparse_texels_resident:
       /* code==0 means sparse texels are resident */
       return nir_ieq_imm(b, intrin->src[0].ssa, 0);
+   case nir_intrinsic_sparse_residency_code_and:
+      return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa);
    default:
       return NULL;
    }

src/gallium/drivers/radeonsi/si_state.c

@@ -641,6 +641,12 @@ static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
 {
    if (sctx->framebuffer.state.nr_cbufs == 1) {
       struct si_shader_selector *sel = sctx->shader.ps.cso;
+
+      /* Wait for the shader to be ready. */
+      util_queue_fence_wait(&sel->ready);
+
+      assert(!sel->nir);
+
       bool free_nir;
       if (unlikely(sel->info.writes_1_if_tex_is_1 == 0xff)) {
          struct nir_shader *nir = si_get_nir_shader(sel, &sctx->shader.ps.key, &free_nir);
@@ -658,6 +664,7 @@ static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
             sel->info.writes_1_if_tex_is_1 = 0;
          }
 
+         assert(free_nir);
          if (free_nir)
             ralloc_free(nir);
       }

src/gallium/drivers/zink/ci/zink-lvp-fails.txt

@@ -103,7 +103,6 @@ spec@!opengl 1.1@linestipple@Factor 2x,Fail
 spec@!opengl 1.1@linestipple@Factor 3x,Fail
 spec@!opengl 1.1@linestipple@Line loop,Fail
 spec@!opengl 1.1@linestipple@Line strip,Fail
-spec@!opengl 1.1@polygon-offset,Fail
 spec@!opengl 1.1@polygon-mode,Fail
 spec@!opengl 1.1@polygon-mode-facing,Fail
 spec@!opengl 1.1@polygon-mode-offset,Fail

src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c

@@ -2635,6 +2635,7 @@ emit_vote(struct ntv_context *ctx, nir_intrinsic_instr *intr)
    default:
       unreachable("unknown vote intrinsic");
    }
+   spirv_builder_emit_cap(&ctx->builder, SpvCapabilityGroupNonUniformVote);
    SpvId result = spirv_builder_emit_vote(&ctx->builder, op, get_src(ctx, &intr->src[0]));
    store_dest_raw(ctx, &intr->dest, result);
 }
@@ -3732,6 +3733,7 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, uint32_
 
    case MESA_SHADER_VERTEX:
       if (BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID) ||
+          BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_DRAW_ID) ||
           BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
           BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX)) {
          spirv_builder_emit_extension(&ctx.builder, "SPV_KHR_shader_draw_parameters");

src/gallium/drivers/zink/zink_context.c

@@ -962,18 +962,19 @@ zink_set_vertex_buffers(struct pipe_context *pctx,
                         const struct pipe_vertex_buffer *buffers)
 {
    struct zink_context *ctx = zink_context(pctx);
+   const bool have_input_state = zink_screen(pctx->screen)->info.have_EXT_vertex_input_dynamic_state;
    const bool need_state_change = !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state &&
-                                  !zink_screen(pctx->screen)->info.have_EXT_vertex_input_dynamic_state;
+                                  !have_input_state;
    uint32_t enabled_buffers = ctx->gfx_pipeline_state.vertex_buffers_enabled_mask;
    enabled_buffers |= u_bit_consecutive(start_slot, num_buffers);
    enabled_buffers &= ~u_bit_consecutive(start_slot + num_buffers, unbind_num_trailing_slots);
+   bool stride_changed = false;
 
    if (buffers) {
-      if (need_state_change)
-         ctx->vertex_state_changed = true;
       for (unsigned i = 0; i < num_buffers; ++i) {
          const struct pipe_vertex_buffer *vb = buffers + i;
          struct pipe_vertex_buffer *ctx_vb = &ctx->vertex_buffers[start_slot + i];
+         stride_changed |= ctx_vb->stride != vb->stride;
          update_existing_vbo(ctx, start_slot + i);
          if (!take_ownership)
             pipe_resource_reference(&ctx_vb->buffer.resource, vb->buffer.resource);
@@ -995,8 +996,6 @@ zink_set_vertex_buffers(struct pipe_context *pctx,
          }
       }
    } else {
-      if (need_state_change)
-         ctx->vertex_state_changed = true;
       for (unsigned i = 0; i < num_buffers; ++i) {
          update_existing_vbo(ctx, start_slot + i);
          pipe_resource_reference(&ctx->vertex_buffers[start_slot + i].buffer.resource, NULL);
@@ -1006,6 +1005,10 @@ zink_set_vertex_buffers(struct pipe_context *pctx,
       update_existing_vbo(ctx, start_slot + i);
       pipe_resource_reference(&ctx->vertex_buffers[start_slot + i].buffer.resource, NULL);
    }
+   if (need_state_change)
+      ctx->vertex_state_changed = true;
+   else if (!have_input_state && (stride_changed || ctx->gfx_pipeline_state.vertex_buffers_enabled_mask != enabled_buffers))
+      ctx->vertex_state_changed = true;
    ctx->gfx_pipeline_state.vertex_buffers_enabled_mask = enabled_buffers;
    ctx->vertex_buffers_dirty = num_buffers > 0;
 #ifndef NDEBUG

src/gallium/drivers/zink/zink_resource.c

@@ -69,13 +69,19 @@
 static bool
 equals_ivci(const void *a, const void *b)
 {
-   return memcmp(a, b, sizeof(VkImageViewCreateInfo)) == 0;
+   const uint8_t *pa = a;
+   const uint8_t *pb = b;
+   size_t offset = offsetof(VkImageViewCreateInfo, flags);
+   return memcmp(pa + offset, pb + offset, sizeof(VkImageViewCreateInfo) - offset) == 0;
 }
 
 static bool
 equals_bvci(const void *a, const void *b)
 {
-   return memcmp(a, b, sizeof(VkBufferViewCreateInfo)) == 0;
+   const uint8_t *pa = a;
+   const uint8_t *pb = b;
+   size_t offset = offsetof(VkBufferViewCreateInfo, flags);
+   return memcmp(pa + offset, pb + offset, sizeof(VkBufferViewCreateInfo) - offset) == 0;
 }
 
 static void
@@ -223,14 +229,25 @@ check_ici(struct zink_screen *screen, VkImageCreateInfo *ici, uint64_t modifier)
    } else
       ret = VKSCR(GetPhysicalDeviceImageFormatProperties)(screen->pdev, ici->format, ici->imageType,
                                                    ici->tiling, ici->usage, ici->flags, &image_props);
-   return ret == VK_SUCCESS;
+   if (ret != VK_SUCCESS)
+      return false;
+   if (ici->extent.depth > image_props.maxExtent.depth ||
+       ici->extent.height > image_props.maxExtent.height ||
+       ici->extent.width > image_props.maxExtent.width)
+      return false;
+   if (ici->mipLevels > image_props.maxMipLevels)
+      return false;
+   if (ici->arrayLayers > image_props.maxArrayLayers)
+      return false;
+   return true;
 }
 
 static VkImageUsageFlags
-get_image_usage_for_feats(struct zink_screen *screen, VkFormatFeatureFlags feats, const struct pipe_resource *templ, unsigned bind)
+get_image_usage_for_feats(struct zink_screen *screen, VkFormatFeatureFlags feats, const struct pipe_resource *templ, unsigned bind, bool *need_extended)
 {
    VkImageUsageFlags usage = 0;
    bool is_planar = util_format_get_num_planes(templ->format) > 1;
+   *need_extended = false;
 
    if (bind & ZINK_BIND_TRANSIENT)
       usage |= VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT;
@@ -254,9 +271,18 @@ get_image_usage_for_feats(struct zink_screen *screen, VkFormatFeatureFlags feats
          usage |= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
          if ((bind & (PIPE_BIND_LINEAR | PIPE_BIND_SHARED)) != (PIPE_BIND_LINEAR | PIPE_BIND_SHARED))
             usage |= VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
-      } else if (templ->nr_samples || !(feats & VK_FORMAT_FEATURE_BLIT_DST_BIT))
-         /* this can't be populated, so we can't do it */
+      } else {
+         /* trust that gallium isn't going to give us anything wild */
+         *need_extended = true;
          return 0;
+      }
+   } else if ((bind & PIPE_BIND_SAMPLER_VIEW) && !util_format_is_depth_or_stencil(templ->format)) {
+      if (!(feats & VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT)) {
+         /* ensure we can u_blitter this later */
+         *need_extended = true;
+         return 0;
+      }
+      usage |= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
    }
 
    if (bind & PIPE_BIND_DEPTH_STENCIL) {
@@ -294,6 +320,7 @@ static VkImageUsageFlags
 get_image_usage(struct zink_screen *screen, VkImageCreateInfo *ici, const struct pipe_resource *templ, unsigned bind, unsigned modifiers_count, const uint64_t *modifiers, uint64_t *mod)
 {
    VkImageTiling tiling = ici->tiling;
+   bool need_extended = false;
    *mod = DRM_FORMAT_MOD_INVALID;
    if (modifiers_count) {
       bool have_linear = false;
@@ -308,7 +335,8 @@ get_image_usage(struct zink_screen *screen, VkImageCreateInfo *ici, const struct
          }
          VkFormatFeatureFlags feats = find_modifier_feats(prop, modifiers[i], mod);
          if (feats) {
-            VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind);
+            VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind, &need_extended);
+            assert(!need_extended);
             if (usage) {
                ici->usage = usage;
                if (check_ici(screen, ici, *mod))
@@ -320,7 +348,8 @@ get_image_usage(struct zink_screen *screen, VkImageCreateInfo *ici, const struct
       if (have_linear) {
          VkFormatFeatureFlags feats = find_modifier_feats(prop, DRM_FORMAT_MOD_LINEAR, mod);
          if (feats) {
-            VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind);
+            VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind, &need_extended);
+            assert(!need_extended);
             if (usage) {
                ici->usage = usage;
                if (check_ici(screen, ici, *mod))
@@ -332,7 +361,14 @@ get_image_usage(struct zink_screen *screen, VkImageCreateInfo *ici, const struct
    {
       VkFormatProperties props = screen->format_props[templ->format];
       VkFormatFeatureFlags feats = tiling == VK_IMAGE_TILING_LINEAR ? props.linearTilingFeatures : props.optimalTilingFeatures;
-      VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind);
+      if (ici->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT)
+         feats = UINT32_MAX;
+      VkImageUsageFlags usage = get_image_usage_for_feats(screen, feats, templ, bind, &need_extended);
+      if (need_extended) {
+         ici->flags |= VK_IMAGE_CREATE_EXTENDED_USAGE_BIT;
+         feats = UINT32_MAX;
+         usage = get_image_usage_for_feats(screen, feats, templ, bind, &need_extended);
+      }
       if (usage) {
          ici->usage = usage;
          if (check_ici(screen, ici, *mod))
@@ -427,6 +463,7 @@ create_ici(struct zink_screen *screen, VkImageCreateInfo *ici, const struct pipe
    bool first = true;
    bool tried[2] = {0};
    uint64_t mod = DRM_FORMAT_MOD_INVALID;
+retry:
    while (!ici->usage) {
       if (!first) {
          switch (ici->tiling) {
@@ -448,8 +485,15 @@ create_ici(struct zink_screen *screen, VkImageCreateInfo *ici, const struct pipe
             unreachable("unhandled tiling mode");
          }
          if (tried[ici->tiling]) {
-            *success = false;
+            if (ici->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT) {
+               *success = false;
                return DRM_FORMAT_MOD_INVALID;
+            }
+            ici->flags |= VK_IMAGE_CREATE_EXTENDED_USAGE_BIT;
+            tried[0] = false;
+            tried[1] = false;
+            first = true;
+            goto retry;
          }
       }
       ici->usage = get_image_usage(screen, ici, templ, bind, modifiers_count, modifiers, &mod);

src/gallium/drivers/zink/zink_screen.c

@@ -2015,8 +2015,6 @@ check_base_requirements(struct zink_screen *screen)
 {
    if (!screen->info.feats.features.logicOp ||
        !screen->info.feats.features.fillModeNonSolid ||
-       !screen->info.feats.features.wideLines ||
-       !screen->info.feats.features.largePoints ||
        !screen->info.feats.features.shaderClipDistance ||
        !(screen->info.feats12.scalarBlockLayout ||
          screen->info.have_EXT_scalar_block_layout) ||
@@ -2031,8 +2029,6 @@ check_base_requirements(struct zink_screen *screen)
          fprintf(stderr, "%s ", #X)
       CHECK_OR_PRINT(feats.features.logicOp);
       CHECK_OR_PRINT(feats.features.fillModeNonSolid);
-      CHECK_OR_PRINT(feats.features.wideLines);
-      CHECK_OR_PRINT(feats.features.largePoints);
       CHECK_OR_PRINT(feats.features.shaderClipDistance);
       if (!screen->info.feats12.scalarBlockLayout && !screen->info.have_EXT_scalar_block_layout)
          printf("scalarBlockLayout OR EXT_scalar_block_layout ");

src/gallium/drivers/zink/zink_surface.c

@@ -136,7 +136,7 @@ create_surface(struct pipe_context *pctx,
    VkFormatFeatureFlags feats = res->optimal_tiling ?
                                 screen->format_props[templ->format].optimalTilingFeatures :
                                 screen->format_props[templ->format].linearTilingFeatures;
-   VkImageUsageFlags attachment = (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
+   VkImageUsageFlags attachment = (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT);
    usage_info.usage = res->obj->vkusage & ~attachment;
    if ((res->obj->vkusage & attachment) &&
        !(feats & (VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT | VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT))) {

src/gallium/frontends/lavapipe/lvp_execute.c

@@ -255,8 +255,14 @@ static void emit_state(struct rendering_state *state)
       assert(offsetof(struct pipe_rasterizer_state, offset_clamp) - offsetof(struct pipe_rasterizer_state, offset_units) == sizeof(float) * 2);
       if (state->depth_bias.enabled) {
          memcpy(&state->rs_state.offset_units, &state->depth_bias, sizeof(float) * 3);
+         state->rs_state.offset_tri = true;
+         state->rs_state.offset_line = true;
+         state->rs_state.offset_point = true;
       } else {
          memset(&state->rs_state.offset_units, 0, sizeof(float) * 3);
+         state->rs_state.offset_tri = false;
+         state->rs_state.offset_line = false;
+         state->rs_state.offset_point = false;
       }
       cso_set_rasterizer(state->cso, &state->rs_state);
       state->rs_dirty = false;

src/gallium/targets/pipe-loader/meson.build

@@ -18,7 +18,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-pipe_loader_link_args = [ld_args_gc_sections]
+pipe_loader_link_args = [ld_args_gc_sections, ld_args_build_id]
 pipe_loader_link_deps = []
 pipe_loader_link_with = [libgallium]
 pipe_loader_comp_args = []

src/glx/glxconfig.c

@@ -145,10 +145,10 @@ glx_config_get(struct glx_config * mode, int attribute, int *value_return)
       *value_return = mode->fbconfigID;
       return 0;
    case GLX_MAX_PBUFFER_WIDTH:
-      *value_return = mode->maxPbufferWidth;
+      *value_return = 4096; /* _EGL_MAX_PBUFFER_WIDTH */
       return 0;
    case GLX_MAX_PBUFFER_HEIGHT:
-      *value_return = mode->maxPbufferHeight;
+      *value_return = 4096; /* _EGL_MAX_PBUFFER_HEIGHT */
       return 0;
    case GLX_MAX_PBUFFER_PIXELS:
       *value_return = mode->maxPbufferPixels;

src/intel/compiler/brw_compiler.h

@@ -850,6 +850,7 @@ struct brw_wm_prog_data {
       /** @} */
    } binding_table;
 
+   uint8_t color_outputs_written;
    uint8_t computed_depth_mode;
    bool computed_stencil;
 

src/intel/compiler/brw_fs.cpp

@@ -9683,6 +9683,7 @@ brw_nir_populate_wm_prog_data(const nir_shader *shader,
                           key->emit_alpha_test;
    prog_data->uses_omask = !key->ignore_sample_mask_out &&
       (shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK));
+   prog_data->color_outputs_written = key->color_outputs_valid;
    prog_data->computed_depth_mode = computed_depth_mode(shader);
    prog_data->computed_stencil =
       shader->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL);

src/intel/vulkan/anv_device.c

@@ -1941,7 +1941,7 @@ void anv_GetPhysicalDeviceProperties(
        * Since the Windows driver does the same, it's probably fair to assume
        * that no one needs more than this.
        */
-      .lineWidthRange                           = { 0.0, 7.9921875 },
+      .lineWidthRange                           = { 0.0, devinfo->ver >= 9 ? 8.0 : 7.9921875 },
       .pointSizeGranularity                     = (1.0 / 8.0),
       .lineWidthGranularity                     = (1.0 / 128.0),
       .strictLines                              = false,

src/intel/vulkan/anv_pipeline.c

@@ -1352,21 +1352,6 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
    fs_stage->num_stats = (uint32_t)fs_stage->prog_data.wm.dispatch_8 +
                          (uint32_t)fs_stage->prog_data.wm.dispatch_16 +
                          (uint32_t)fs_stage->prog_data.wm.dispatch_32;
-
-   if (fs_stage->key.wm.color_outputs_valid == 0 &&
-       !fs_stage->prog_data.wm.has_side_effects &&
-       !fs_stage->prog_data.wm.uses_omask &&
-       !fs_stage->key.wm.alpha_to_coverage &&
-       !fs_stage->prog_data.wm.uses_kill &&
-       fs_stage->prog_data.wm.computed_depth_mode == BRW_PSCDEPTH_OFF &&
-       !fs_stage->prog_data.wm.computed_stencil) {
-      /* This fragment shader has no outputs and no side effects.  Go ahead
-       * and return the code pointer so we don't accidentally think the
-       * compile failed but zero out prog_data which will set program_size to
-       * zero and disable the stage.
-       */
-      memset(&fs_stage->prog_data, 0, sizeof(fs_stage->prog_data));
-   }
 }
 
 static void
@@ -2015,15 +2000,25 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
 
 done:
 
-   if (pipeline->shaders[MESA_SHADER_FRAGMENT] &&
-       pipeline->shaders[MESA_SHADER_FRAGMENT]->prog_data->program_size == 0) {
-      /* This can happen if we decided to implicitly disable the fragment
-       * shader.  See anv_pipeline_compile_fs().
-       */
-      anv_shader_bin_unref(pipeline->base.device,
-                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
-      pipeline->shaders[MESA_SHADER_FRAGMENT] = NULL;
-      pipeline->active_stages &= ~VK_SHADER_STAGE_FRAGMENT_BIT;
+   if (pipeline->shaders[MESA_SHADER_FRAGMENT] != NULL) {
+      struct anv_shader_bin *fs = pipeline->shaders[MESA_SHADER_FRAGMENT];
+      const struct brw_wm_prog_data *wm_prog_data =
+         brw_wm_prog_data_const(fs->prog_data);
+
+      if (wm_prog_data->color_outputs_written == 0 &&
+          !wm_prog_data->has_side_effects &&
+          !wm_prog_data->uses_omask &&
+          !wm_prog_data->uses_kill &&
+          wm_prog_data->computed_depth_mode == BRW_PSCDEPTH_OFF &&
+          !wm_prog_data->computed_stencil &&
+          fs->xfb_info == NULL) {
+         /* This can happen if we decided to implicitly disable the fragment
+          * shader.  See anv_pipeline_compile_fs().
+          */
+         anv_shader_bin_unref(pipeline->base.device, fs);
+         pipeline->shaders[MESA_SHADER_FRAGMENT] = NULL;
+         pipeline->active_stages &= ~VK_SHADER_STAGE_FRAGMENT_BIT;
+      }
    }
 
    pipeline_feedback.duration = os_time_get_nano() - pipeline_start;

src/mesa/main/context.c

@@ -143,10 +143,6 @@
 #include "macros.h"
 #include "git_sha1.h"
 
-#ifdef USE_SPARC_ASM
-#include "sparc/sparc.h"
-#endif
-
 #include "compiler/glsl_types.h"
 #include "compiler/glsl/builtin_functions.h"
 #include "compiler/glsl/glsl_parser_extras.h"

src/panfrost/bifrost/bifrost_compile.c

@@ -582,16 +582,11 @@ bi_emit_fragment_out(bi_builder *b, nir_intrinsic_instr *instr)
         bool emit_blend = writeout & (PAN_WRITEOUT_C);
         bool emit_zs = writeout & (PAN_WRITEOUT_Z | PAN_WRITEOUT_S);
 
-        unsigned loc = ~0;
+        const nir_variable *var =
+                nir_find_variable_with_driver_location(b->shader->nir,
+                                                       nir_var_shader_out, nir_intrinsic_base(instr));
 
-        if (!combined) {
-                const nir_variable *var =
-                        nir_find_variable_with_driver_location(b->shader->nir,
-                                        nir_var_shader_out, nir_intrinsic_base(instr));
-                assert(var);
-
-                loc = var->data.location;
-        }
+        unsigned loc = var ? var->data.location : 0;
 
         bi_index src0 = bi_src_index(&instr->src[0]);
 
@@ -641,7 +636,7 @@ bi_emit_fragment_out(bi_builder *b, nir_intrinsic_instr *instr)
         }
 
         if (emit_blend) {
-                unsigned rt = combined ? 0 : (loc - FRAG_RESULT_DATA0);
+                unsigned rt = loc ? (loc - FRAG_RESULT_DATA0) : 0;
                 bool dual = (writeout & PAN_WRITEOUT_2);
                 bi_index color = bi_src_index(&instr->src[0]);
                 bi_index color2 = dual ? bi_src_index(&instr->src[4]) : bi_null();

src/panfrost/lib/pan_blend.c

@@ -802,7 +802,6 @@ GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
 
         if (shader->nvariants < PAN_BLEND_SHADER_MAX_VARIANTS) {
                 variant = rzalloc(shader, struct pan_blend_shader_variant);
-                memcpy(variant->constants, state->constants, sizeof(variant->constants));
                 util_dynarray_init(&variant->binary, variant);
                 list_add(&variant->node, &shader->variants);
                 shader->nvariants++;
@@ -813,6 +812,8 @@ GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
                 util_dynarray_clear(&variant->binary);
         }
 
+        memcpy(variant->constants, state->constants, sizeof(variant->constants));
+
         nir_shader *nir =
                 GENX(pan_blend_create_shader)(dev, state, src0_type, src1_type, rt);
 

src/panfrost/midgard/midgard_compile.c

@@ -1875,20 +1875,18 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                         enum midgard_rt_id rt;
 
                         unsigned reg_z = ~0, reg_s = ~0, reg_2 = ~0;
+                        unsigned writeout = PAN_WRITEOUT_C;
                         if (combined) {
-                                unsigned writeout = nir_intrinsic_component(instr);
+                                writeout = nir_intrinsic_component(instr);
                                 if (writeout & PAN_WRITEOUT_Z)
                                         reg_z = nir_src_index(ctx, &instr->src[2]);
                                 if (writeout & PAN_WRITEOUT_S)
                                         reg_s = nir_src_index(ctx, &instr->src[3]);
                                 if (writeout & PAN_WRITEOUT_2)
                                         reg_2 = nir_src_index(ctx, &instr->src[4]);
+                        }
 
-                                if (writeout & PAN_WRITEOUT_C)
-                                        rt = MIDGARD_COLOR_RT0;
-                                else
-                                        rt = MIDGARD_ZS_RT;
-                        } else {
+                        if (writeout & PAN_WRITEOUT_C) {
                                 const nir_variable *var =
                                         nir_find_variable_with_driver_location(ctx->nir, nir_var_shader_out,
                                                  nir_intrinsic_base(instr));
@@ -1898,6 +1896,8 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
 
                                 rt = MIDGARD_COLOR_RT0 + var->data.location -
                                      FRAG_RESULT_DATA0;
+                        } else {
+                                rt = MIDGARD_ZS_RT;
                         }
 
                         /* Dual-source blend writeout is done by leaving the

src/panfrost/util/pan_lower_writeout.c

@@ -55,6 +55,8 @@ pan_nir_emit_combined_store(nir_builder *b,
 
         intr->num_components = rt0_store ? rt0_store->src[0].ssa->num_components : 4;
 
+        if (rt0_store)
+                nir_intrinsic_set_base(intr, nir_intrinsic_base(rt0_store));
         nir_intrinsic_set_src_type(intr, pan_nir_rt_store_type(rt0_store));
         nir_intrinsic_set_dest_type(intr, pan_nir_rt_store_type(stores[2]));
         nir_intrinsic_set_component(intr, writeout);
@@ -171,7 +173,12 @@ pan_nir_lower_zs_store(nir_shader *nir)
                                 nir_builder_init(&b, function->impl);
                                 b.cursor = nir_after_block_before_jump(instr->block);
 
-                                pan_nir_emit_combined_store(&b, intr, writeout | PAN_WRITEOUT_C, stores);
+                                /* Trying to write depth twice results in the
+                                 * wrong blend shader being executed on
+                                 * Midgard */
+                                unsigned this_store = PAN_WRITEOUT_C | (replaced ? 0 : writeout);
+
+                                pan_nir_emit_combined_store(&b, intr, this_store, stores);
 
                                 nir_instr_remove(instr);