bump VERSION for 20.3.0-rc2 release

In bison's commit 72c9fa4510eb (skeletons: use "end of file" instead of
"$end") in bison-3.6, '$end' was changed to 'end of file' in error
messages. Since our glcpp test cases contain the expected output text,
they rely on the particular messages printed by bison. The test case
084-unbalanced-parentheses fails when Mesa is built with bison-3.6 due
to this change.

To allow the test to pass on all supported versions of bison, we:

   1. Change '$end' -> 'end of file' in the .expected file, and
   2. Normalize the error generated by the test case with the same
      replacement

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3181
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7659>
(cherry picked from commit df29d0a111)

.gitlab-ci.yml

@@ -414,7 +414,7 @@ arm64_test:
   extends:
     - .use-arm_test-base
   variables:
-    FDO_DISTRIBUTION_TAG: &arm64_test "2020-11-03-deqp-runner"
+    FDO_DISTRIBUTION_TAG: &arm64_test "2020-11-09-kmod"
 
 .use-arm64_test:
   variables:

.gitlab-ci/container/lava_build.sh

@@ -156,8 +156,10 @@ for i in /usr/bin/*-ld /usr/bin/ld; do
 done
 export PATH=`pwd`/ld-links:$PATH
 
-# Disable all modules in defconfig, so we only build the ones we want
-sed -i 's/=m/=n/g' ${DEFCONFIG}
+if [ -n "$INSTALL_KERNEL_MODULES" ]; then
+    # Disable all modules in defconfig, so we only build the ones we want
+    sed -i 's/=m/=n/g' ${DEFCONFIG}
+fi
 
 ./scripts/kconfig/merge_config.sh ${DEFCONFIG} ../.gitlab-ci/${KERNEL_ARCH}.config
 make ${KERNEL_IMAGE_NAME}
@@ -170,8 +172,10 @@ if [[ -n ${DEVICE_TREES} ]]; then
     cp ${DEVICE_TREES} /lava-files/.
 fi
 
-make modules
-INSTALL_MOD_PATH=/lava-files/rootfs-${DEBIAN_ARCH}/ make modules_install
+if [ -n "$INSTALL_KERNEL_MODULES" ]; then
+    make modules
+    INSTALL_MOD_PATH=/lava-files/rootfs-${DEBIAN_ARCH}/ make modules_install
+fi
 
 if [[ ${DEBIAN_ARCH} = "arm64" ]] && which mkimage > /dev/null; then
     make Image.lzma

.gitlab-ci/deqp-panfrost-g52-fails.txt

@@ -13,79 +13,16 @@ dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.rg8,Fail
 dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.rgb10_a2,Fail
 dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.rgb_half_float_oes,Fail
 dEQP-GLES2.functional.fbo.completeness.size.distinct,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb565,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_npot_rbo_rgb565_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_npot_tex2d_rgb,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_npot_tex2d_rgb_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb565,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_rbo_rgb565_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_tex2d_rgb,Fail
-dEQP-GLES2.functional.fbo.render.color.blend_tex2d_rgb_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgb565_stencil_index8,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_depth_component16,Fail
-dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgb_stencil_index8,Fail
-dEQP-GLES2.functional.fbo.render.texsubimage.between_render_tex2d_rgb,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.constant_color_dst_alpha,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.constant_color_dst_color,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.constant_color_one_minus_dst_alpha,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.constant_color_one_minus_dst_color,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.one_minus_constant_color_dst_alpha,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.one_minus_constant_color_dst_color,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.one_minus_constant_color_one_minus_dst_alpha,Fail
-dEQP-GLES2.functional.fragment_ops.blend.rgb_func_alpha_func.src.one_minus_constant_color_one_minus_dst_color,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.14,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.22,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.31,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.32,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.42,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.43,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.61,Fail
-dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.67,Fail
-dEQP-GLES2.functional.fragment_ops.random.11,Fail
-dEQP-GLES2.functional.fragment_ops.random.24,Fail
-dEQP-GLES2.functional.fragment_ops.random.41,Fail
-dEQP-GLES2.functional.fragment_ops.random.45,Fail
-dEQP-GLES2.functional.fragment_ops.random.48,Fail
-dEQP-GLES2.functional.fragment_ops.random.5,Fail
-dEQP-GLES2.functional.fragment_ops.random.51,Fail
-dEQP-GLES2.functional.fragment_ops.random.67,Fail
-dEQP-GLES2.functional.fragment_ops.random.98,Fail
 dEQP-GLES2.functional.negative_api.shader.uniform_matrixfv_invalid_transpose,Fail
 dEQP-GLES2.functional.negative_api.texture.generatemipmap_zero_level_array_compressed,Fail
-dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz,Fail
 dEQP-GLES2.functional.shaders.random.all_features.fragment.88,Fail
 dEQP-GLES2.functional.shaders.texture_functions.vertex.texturecubelod,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_non_square_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_non_square_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.la88_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.la88_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.la88_non_square_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.2d.generate.la88_non_square_nicest,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_linear,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_nearest,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_linear,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.bias.linear_nearest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.a8_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.a8_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.l8_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.l8_nicest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.la88_fastest,Fail
-dEQP-GLES2.functional.texture.mipmap.cube.generate.la88_nicest,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_linear,Fail
 dEQP-GLES2.functional.texture.mipmap.cube.projected.linear_nearest,Fail
-dEQP-GLES2.functional.texture.specification.basic_copyteximage2d.2d_alpha,Fail
-dEQP-GLES2.functional.texture.specification.basic_copyteximage2d.cube_alpha,Fail
-dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.2d_alpha,Fail
-dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.cube_alpha,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_clamp,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_linear_mirror,Fail
 dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_nearest_clamp,Fail

.gitlab-ci/deqp-softpipe-fails.txt

@@ -93,12 +93,6 @@ dEQP-GLES3.functional.rasterization.interpolation.basic.lines_wide,Fail
 dEQP-GLES3.functional.rasterization.interpolation.projected.line_loop_wide,Fail
 dEQP-GLES3.functional.rasterization.interpolation.projected.line_strip_wide,Fail
 dEQP-GLES3.functional.rasterization.interpolation.projected.lines_wide,Fail
-dEQP-GLES3.functional.rasterizer_discard.basic.write_depth_points,Fail
-dEQP-GLES3.functional.rasterizer_discard.basic.write_stencil_points,Fail
-dEQP-GLES3.functional.rasterizer_discard.fbo.write_depth_points,Fail
-dEQP-GLES3.functional.rasterizer_discard.fbo.write_stencil_points,Fail
-dEQP-GLES3.functional.rasterizer_discard.scissor.write_depth_points,Fail
-dEQP-GLES3.functional.rasterizer_discard.scissor.write_stencil_points,Fail
 dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.float_highp,Fail
 dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.float_mediump,Fail
 dEQP-GLES3.functional.shaders.derivate.dfdx.fastest.fbo_msaa4.vec2_highp,Fail
@@ -848,7 +842,6 @@ KHR-GL33.transform_feedback.capture_geometry_interleaved_test,Fail
 KHR-GL33.transform_feedback.capture_geometry_separate_test,Fail
 KHR-GL33.transform_feedback.capture_vertex_interleaved_test,Fail
 KHR-GL33.transform_feedback.capture_vertex_separate_test,Fail
-KHR-GL33.transform_feedback.discard_geometry_test,Fail
 KHR-GL33.transform_feedback.discard_vertex_test,Fail
 KHR-GL33.transform_feedback.draw_xfb_instanced_test,Crash
 KHR-GL33.transform_feedback.draw_xfb_stream_instanced_test,Crash

.gitlab-ci/lava-gitlab-ci.yml

@@ -1,5 +1,5 @@
 variables:
-  DISTRIBUTION_TAG: "2020-11-05-deqp-runner"
+  DISTRIBUTION_TAG: "2020-11-09-kmod-fix"
 
 .kernel+rootfs:
   stage: container-2
@@ -9,6 +9,7 @@ variables:
     GIT_STRATEGY: fetch
     KERNEL_URL: "https://gitlab.freedesktop.org/tomeu/linux/-/archive/v5.10-rc2-for-mesa-ci/linux-v5.10-rc2-for-mesa-ci.tar.gz"
     UPLOAD_FOR_LAVA: 1
+    INSTALL_KERNEL_MODULES: 1
   script:
     - .gitlab-ci/container/lava_build.sh
 

VERSION

@@ -1 +1 @@
-20.3.0-devel
+20.3.0-rc2

src/amd/compiler/aco_optimizer.cpp

@@ -1286,7 +1286,7 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
                ctx.info[instr->operands[i].tempId()].set_omod2(instr.get());
             } else if (instr->operands[!i].constantValue() == (fp16 ? 0x4400 : 0x40800000)) { /* 4.0 */
                ctx.info[instr->operands[i].tempId()].set_omod4(instr.get());
-            } else if (instr->operands[!i].constantValue() == (fp16 ? 0xb800 : 0x3f000000)) { /* 0.5 */
+            } else if (instr->operands[!i].constantValue() == (fp16 ? 0x3800 : 0x3f000000)) { /* 0.5 */
                ctx.info[instr->operands[i].tempId()].set_omod5(instr.get());
             } else if (instr->operands[!i].constantValue() == (fp16 ? 0x3c00 : 0x3f800000) &&
                        !(fp16 ? block.fp_mode.must_flush_denorms16_64 : block.fp_mode.must_flush_denorms32)) { /* 1.0 */
@@ -1786,6 +1786,31 @@ bool combine_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
    return true;
 }
 
+bool is_operand_constant(opt_ctx &ctx, Operand op, unsigned bit_size, uint64_t *value)
+{
+   if (op.isConstant()) {
+      *value = op.constantValue64();
+      return true;
+   } else if (op.isTemp()) {
+      unsigned id = original_temp_id(ctx, op.getTemp());
+      if (!ctx.info[id].is_constant_or_literal(bit_size))
+         return false;
+      *value = get_constant_op(ctx, ctx.info[id], bit_size).constantValue64();
+      return true;
+   }
+   return false;
+}
+
+bool is_constant_nan(uint64_t value, unsigned bit_size)
+{
+   if (bit_size == 16)
+      return ((value >> 10) & 0x1f) == 0x1f && (value & 0x3ff);
+   else if (bit_size == 32)
+      return ((value >> 23) & 0xff) == 0xff && (value & 0x7fffff);
+   else
+      return ((value >> 52) & 0x7ff) == 0x7ff && (value & 0xfffffffffffff);
+}
+
 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
  * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
 bool combine_constant_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
@@ -1811,7 +1836,8 @@ bool combine_constant_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& in
    else if (get_f32_cmp(nan_test->opcode) != expected_nan_test)
       return false;
 
-   if (!is_cmp(cmp->opcode) || get_cmp_bitsize(cmp->opcode) != get_cmp_bitsize(nan_test->opcode))
+   unsigned bit_size = get_cmp_bitsize(cmp->opcode);
+   if (!is_cmp(cmp->opcode) || get_cmp_bitsize(nan_test->opcode) != bit_size)
       return false;
 
    if (!nan_test->operands[0].isTemp() || !nan_test->operands[1].isTemp())
@@ -1840,22 +1866,10 @@ bool combine_constant_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& in
    if (constant_operand == -1)
       return false;
 
-   uint32_t constant;
-   if (cmp->operands[constant_operand].isConstant()) {
-      constant = cmp->operands[constant_operand].constantValue();
-   } else if (cmp->operands[constant_operand].isTemp()) {
-      Temp tmp = cmp->operands[constant_operand].getTemp();
-      unsigned id = original_temp_id(ctx, tmp);
-      if (!ctx.info[id].is_constant_or_literal(32))
-         return false;
-      constant = ctx.info[id].val;
-   } else {
+   uint64_t constant_value;
+   if (!is_operand_constant(ctx, cmp->operands[constant_operand], bit_size, &constant_value))
       return false;
-   }
-
-   float constantf;
-   memcpy(&constantf, &constant, 4);
-   if (isnan(constantf))
+   if (is_constant_nan(constant_value, bit_size))
       return false;
 
    if (cmp->operands[0].isTemp())
@@ -1958,7 +1972,8 @@ bool match_op3_for_vop3(opt_ctx &ctx, aco_opcode op1, aco_opcode op2,
                         Instruction* op1_instr, bool swap, const char *shuffle_str,
                         Operand operands[3], bool neg[3], bool abs[3], uint8_t *opsel,
                         bool *op1_clamp, uint8_t *op1_omod,
-                        bool *inbetween_neg, bool *inbetween_abs, bool *inbetween_opsel)
+                        bool *inbetween_neg, bool *inbetween_abs, bool *inbetween_opsel,
+                        bool *precise)
 {
    /* checks */
    if (op1_instr->opcode != op1)
@@ -1999,6 +2014,9 @@ bool match_op3_for_vop3(opt_ctx &ctx, aco_opcode op1, aco_opcode op2,
    else if (op1_vop3 && op1_vop3->opsel & (1 << swap))
       return false;
 
+   *precise = op1_instr->definitions[0].isPrecise() ||
+              op2_instr->definitions[0].isPrecise();
+
    int shuffle[3];
    shuffle[shuffle_str[0] - '0'] = 0;
    shuffle[shuffle_str[1] - '0'] = 1;
@@ -2051,12 +2069,12 @@ bool combine_three_valu_op(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode
          continue;
 
       Operand operands[3];
-      bool neg[3], abs[3], clamp;
+      bool neg[3], abs[3], clamp, precise;
       uint8_t opsel = 0, omod = 0;
       if (match_op3_for_vop3(ctx, instr->opcode, op2,
                              instr.get(), swap, shuffle,
                              operands, neg, abs, &opsel,
-                             &clamp, &omod, NULL, NULL, NULL)) {
+                             &clamp, &omod, NULL, NULL, NULL, &precise)) {
          ctx.uses[instr->operands[swap].tempId()]--;
          create_vop3_for_op3(ctx, new_op, instr, operands, neg, abs, opsel, clamp, omod);
          return true;
@@ -2074,13 +2092,13 @@ bool combine_minmax(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode opposi
     * max(-min(a, b), c) -> max3(-a, -b, c) */
    for (unsigned swap = 0; swap < 2; swap++) {
       Operand operands[3];
-      bool neg[3], abs[3], clamp;
+      bool neg[3], abs[3], clamp, precise;
       uint8_t opsel = 0, omod = 0;
       bool inbetween_neg;
       if (match_op3_for_vop3(ctx, instr->opcode, opposite,
                              instr.get(), swap, "012",
                              operands, neg, abs, &opsel,
-                             &clamp, &omod, &inbetween_neg, NULL, NULL) &&
+                             &clamp, &omod, &inbetween_neg, NULL, NULL, &precise) &&
           inbetween_neg) {
          ctx.uses[instr->operands[swap].tempId()]--;
          neg[1] = true;
@@ -2320,11 +2338,17 @@ bool combine_clamp(opt_ctx& ctx, aco_ptr<Instruction>& instr,
 
    for (unsigned swap = 0; swap < 2; swap++) {
       Operand operands[3];
-      bool neg[3], abs[3], clamp;
+      bool neg[3], abs[3], clamp, precise;
       uint8_t opsel = 0, omod = 0;
       if (match_op3_for_vop3(ctx, instr->opcode, other_op, instr.get(), swap,
                              "012", operands, neg, abs, &opsel,
-                             &clamp, &omod, NULL, NULL, NULL)) {
+                             &clamp, &omod, NULL, NULL, NULL, &precise)) {
+         /* max(min(src, upper), lower) returns upper if src is NaN, but
+          * med3(src, lower, upper) returns lower.
+          */
+         if (precise && instr->opcode != min)
+            continue;
+
          int const0_idx = -1, const1_idx = -1;
          uint32_t const0 = 0, const1 = 0;
          for (int i = 0; i < 3; i++) {
@@ -2524,9 +2548,14 @@ bool apply_omod_clamp(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
    if (!instr->isSDWA() && !can_vop3)
       return false;
 
-   /* omod has no effect if denormals are enabled */
-   bool can_use_omod = (instr->definitions[0].bytes() == 4 ? block.fp_mode.denorm32 : block.fp_mode.denorm16_64) == 0;
-   can_use_omod = can_use_omod && (can_vop3 || ctx.program->chip_class >= GFX9); /* SDWA omod is GFX9+ */
+   /* omod flushes -0 to +0 and has no effect if denormals are enabled */
+   bool can_use_omod = (can_vop3 || ctx.program->chip_class >= GFX9); /* SDWA omod is GFX9+ */
+   if (instr->definitions[0].bytes() == 4)
+      can_use_omod = can_use_omod && block.fp_mode.denorm32 == 0 &&
+                     !block.fp_mode.preserve_signed_zero_inf_nan32;
+   else
+      can_use_omod = can_use_omod && block.fp_mode.denorm16_64 == 0 &&
+                     !block.fp_mode.preserve_signed_zero_inf_nan16_64;
 
    ssa_info& def_info = ctx.info[instr->definitions[0].tempId()];
 
@@ -2824,7 +2853,7 @@ void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr
       else combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xor3_b32, "012", 1 | 2);
    } else if (instr->opcode == aco_opcode::v_add_u32) {
       if (combine_add_sub_b2i(ctx, instr, aco_opcode::v_addc_co_u32, 1 | 2)) ;
-      else if (ctx.program->chip_class >= GFX9) {
+      else if (ctx.program->chip_class >= GFX9 && !instr->usesModifiers()) {
          if (combine_three_valu_op(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ;
          else if (combine_three_valu_op(ctx, instr, aco_opcode::v_xor_b32, aco_opcode::v_xad_u32, "120", 1 | 2)) ;
          else if (combine_three_valu_op(ctx, instr, aco_opcode::s_add_i32, aco_opcode::v_add3_u32, "012", 1 | 2)) ;

src/amd/compiler/tests/test_optimizer.cpp

@@ -122,3 +122,132 @@ BEGIN_TEST(optimize.cndmask)
       finish_opt_test();
    }
 END_TEST
+
+BEGIN_TEST(optimize.clamp)
+   //>> v1: %a, v1: %b, v1: %c, s2: %_:exec = p_startpgm
+   if (!setup_cs("v1 v1 v1", GFX9))
+      return;
+
+   //! v1: %res0 = v_med3_f32 4.0, 0, %a
+   //! p_unit_test 0, %res0
+   writeout(0, bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0x40800000u),
+                        bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), inputs[0])));
+
+   //! v1: %res1 = v_med3_f32 0, 4.0, %a
+   //! p_unit_test 1, %res1
+   writeout(1, bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u),
+                        bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0x40800000u), inputs[0])));
+
+   /* correct NaN behaviour with precise */
+
+   //! v1: %res2 = v_med3_f32 4.0, 0, %a
+   //! p_unit_test 2, %res2
+   Builder::Result max = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), inputs[0]);
+   max.def(0).setPrecise(true);
+   Builder::Result min = bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0x40800000u), max);
+   max.def(0).setPrecise(true);
+   writeout(2, min);
+
+   //! v1: (precise)%res3_tmp = v_min_f32 4.0, %a
+   //! v1: %res3 = v_max_f32 0, %res3_tmp
+   //! p_unit_test 3, %res3
+   min = bld.vop2(aco_opcode::v_min_f32, bld.def(v1), Operand(0x40800000u), inputs[0]);
+   min.def(0).setPrecise(true);
+   writeout(3, bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), min));
+
+   finish_opt_test();
+END_TEST
+
+BEGIN_TEST(optimize.const_comparison_ordering)
+   //>> v1: %a, v1: %b, v2: %c, v1: %d, s2: %_:exec = p_startpgm
+   if (!setup_cs("v1 v1 v2 v1", GFX9))
+      return;
+
+   /* optimize to unordered comparison */
+   //! s2: %res0 = v_cmp_nge_f32 4.0, %a
+   //! p_unit_test 0, %res0
+   writeout(0, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_neq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), Operand(0x40800000u), inputs[0])));
+
+   //! s2: %res1 = v_cmp_nge_f32 4.0, %a
+   //! p_unit_test 1, %res1
+   writeout(1, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_neq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_nge_f32, bld.def(bld.lm), Operand(0x40800000u), inputs[0])));
+
+   //! s2: %res2 = v_cmp_nge_f32 0x40a00000, %a
+   //! p_unit_test 2, %res2
+   writeout(2, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_neq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), bld.copy(bld.def(v1), Operand(0x40a00000u)), inputs[0])));
+
+   /* optimize to ordered comparison */
+   //! s2: %res3 = v_cmp_lt_f32 4.0, %a
+   //! p_unit_test 3, %res3
+   writeout(3, bld.sop2(aco_opcode::s_and_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_nge_f32, bld.def(bld.lm), Operand(0x40800000u), inputs[0])));
+
+   //! s2: %res4 = v_cmp_lt_f32 4.0, %a
+   //! p_unit_test 4, %res4
+   writeout(4, bld.sop2(aco_opcode::s_and_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), Operand(0x40800000u), inputs[0])));
+
+   //! s2: %res5 = v_cmp_lt_f32 0x40a00000, %a
+   //! p_unit_test 5, %res5
+   writeout(5, bld.sop2(aco_opcode::s_and_b64, bld.def(bld.lm), bld.def(s1, scc),
+                        bld.vopc(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                        bld.vopc(aco_opcode::v_cmp_nge_f32, bld.def(bld.lm), bld.copy(bld.def(v1), Operand(0x40a00000u)), inputs[0])));
+
+   /* NaN */
+   uint16_t nan16 = 0x7e00;
+   uint32_t nan32 = 0x7fc00000;
+
+   //! s2: %tmp6_0 = v_cmp_lt_f16 0x7e00, %a
+   //! s2: %tmp6_1 = v_cmp_neq_f16 %a, %a
+   //! s2: %res6, s1: %_:scc = s_or_b64 %tmp6_1, %tmp6_0
+   //! p_unit_test 6, %res6
+   writeout(6, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
+                         bld.vopc(aco_opcode::v_cmp_neq_f16, bld.def(bld.lm), inputs[0], inputs[0]),
+                         bld.vopc(aco_opcode::v_cmp_lt_f16, bld.def(bld.lm), Operand(nan16), inputs[0])));
+
+   //! s2: %tmp7_0 = v_cmp_lt_f32 0x7fc00000, %a
+   //! s2: %tmp7_1 = v_cmp_neq_f32 %a, %a
+   //! s2: %res7, s1: %_:scc = s_or_b64 %tmp7_1, %tmp7_0
+   //! p_unit_test 7, %res7
+   writeout(7, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
+                         bld.vopc(aco_opcode::v_cmp_neq_f32, bld.def(bld.lm), inputs[0], inputs[0]),
+                         bld.vopc(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), Operand(nan32), inputs[0])));
+
+   finish_opt_test();
+END_TEST
+
+BEGIN_TEST(optimize.add3)
+   //>> v1: %a, v1: %b, v1: %c, s2: %_:exec = p_startpgm
+   if (!setup_cs("v1 v1 v1", GFX9))
+      return;
+
+   //! v1: %res0 = v_add3_u32 %a, %b, %c
+   //! p_unit_test 0, %res0
+   Builder::Result tmp = bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
+   writeout(0, bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp));
+
+   //! v1: %tmp1 = v_add_u32 %b, %c clamp
+   //! v1: %res1 = v_add_u32 %a, %tmp1
+   //! p_unit_test 1, %res1
+   tmp = bld.vop2_e64(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
+   static_cast<VOP3A_instruction *>(tmp.instr)->clamp = true;
+   writeout(1, bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp));
+
+   //! v1: %tmp2 = v_add_u32 %b, %c
+   //! v1: %res2 = v_add_u32 %a, %tmp2 clamp
+   //! p_unit_test 2, %res2
+   tmp = bld.vop2(aco_opcode::v_add_u32, bld.def(v1), inputs[1], inputs[2]);
+   tmp = bld.vop2_e64(aco_opcode::v_add_u32, bld.def(v1), inputs[0], tmp);
+   static_cast<VOP3A_instruction *>(tmp.instr)->clamp = true;
+   writeout(2, tmp);
+
+   finish_opt_test();
+END_TEST

src/compiler/glsl/glcpp/tests/084-unbalanced-parentheses.c.expected

@@ -1,2 +1,2 @@
-0:2(8): preprocessor error: syntax error, unexpected $end
+0:2(8): preprocessor error: syntax error, unexpected end of file
 

src/compiler/glsl/glcpp/tests/glcpp_test.py

@@ -83,6 +83,10 @@ def test_output(glcpp, filename, expfile, nl_format='\n'):
     with open(expfile, 'r') as f:
         expected = f.read()
 
+    # Bison 3.6 changed '$end' to 'end of file' in its error messages
+    # See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3181
+    actual = actual.replace('$end', 'end of file')
+
     if actual == expected:
         return (True, [])
     return (False, difflib.unified_diff(actual.splitlines(), expected.splitlines()))

src/compiler/nir/nir_opt_copy_prop_vars.c

@@ -218,15 +218,19 @@ gather_vars_written(struct copy_prop_var_state *state,
             break;
 
          case nir_intrinsic_deref_atomic_add:
+         case nir_intrinsic_deref_atomic_fadd:
          case nir_intrinsic_deref_atomic_imin:
          case nir_intrinsic_deref_atomic_umin:
+         case nir_intrinsic_deref_atomic_fmin:
          case nir_intrinsic_deref_atomic_imax:
          case nir_intrinsic_deref_atomic_umax:
+         case nir_intrinsic_deref_atomic_fmax:
          case nir_intrinsic_deref_atomic_and:
          case nir_intrinsic_deref_atomic_or:
          case nir_intrinsic_deref_atomic_xor:
          case nir_intrinsic_deref_atomic_exchange:
          case nir_intrinsic_deref_atomic_comp_swap:
+         case nir_intrinsic_deref_atomic_fcomp_swap:
          case nir_intrinsic_store_deref:
          case nir_intrinsic_copy_deref:
          case nir_intrinsic_memcpy_deref: {
@@ -1118,15 +1122,19 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
 
       case nir_intrinsic_memcpy_deref:
       case nir_intrinsic_deref_atomic_add:
+      case nir_intrinsic_deref_atomic_fadd:
       case nir_intrinsic_deref_atomic_imin:
       case nir_intrinsic_deref_atomic_umin:
+      case nir_intrinsic_deref_atomic_fmin:
       case nir_intrinsic_deref_atomic_imax:
       case nir_intrinsic_deref_atomic_umax:
+      case nir_intrinsic_deref_atomic_fmax:
       case nir_intrinsic_deref_atomic_and:
       case nir_intrinsic_deref_atomic_or:
       case nir_intrinsic_deref_atomic_xor:
       case nir_intrinsic_deref_atomic_exchange:
       case nir_intrinsic_deref_atomic_comp_swap:
+      case nir_intrinsic_deref_atomic_fcomp_swap:
          if (debug) dump_instr(instr);
 
          nir_deref_instr *dst = nir_src_as_deref(intrin->src[0]);

src/egl/drivers/dri2/egl_dri2.c

@@ -685,7 +685,10 @@ dri2_lookup_egl_image(__DRIscreen *screen, void *image, void *data)
 
    (void) screen;
 
+   mtx_lock(&disp->Mutex);
    img = _eglLookupImage(image, disp);
+   mtx_unlock(&disp->Mutex);
+
    if (img == NULL) {
       _eglError(EGL_BAD_PARAMETER, "dri2_lookup_egl_image");
       return NULL;

src/freedreno/ir3/ir3.c

@@ -997,7 +997,7 @@ void * ir3_assemble(struct ir3_shader_variant *v)
 	return ptr;
 
 fail:
-	free(ptr);
+	ralloc_free(ptr);
 	return NULL;
 }
 

src/freedreno/ir3/ir3_disk_cache.c

@@ -126,7 +126,7 @@ retrieve_variant(struct blob_reader *blob, struct ir3_shader_variant *v)
 	 * pointers need special handling:
 	 */
 
-	v->bin = malloc(4 * v->info.sizedwords);
+	v->bin = rzalloc_size(v, 4 * v->info.sizedwords);
 	blob_copy_bytes(blob, v->bin, 4 * v->info.sizedwords);
 
 	if (!v->binning_pass) {

src/freedreno/vulkan/tu_drm.c

@@ -913,8 +913,6 @@ tu_syncobj_to_fd(struct tu_device *device, struct tu_syncobj *sync)
    int ret;
 
    ret = ioctl(device->fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &handle);
-   if (ret)
-      return 0;
 
    return ret ? -1 : handle.fd;
 }

src/freedreno/vulkan/tu_wsi_display.c

@@ -282,12 +282,12 @@ tu_RegisterDeviceEventEXT(VkDevice                    _device,
                                       allocator,
                                       NULL,
                                       sync_fd);
+
+      close(sync_fd);
    } else {
       ret = VK_ERROR_OUT_OF_HOST_MEMORY;
    }
 
-   close(sync_fd);
-
    if (ret != VK_SUCCESS)
       tu_DestroyFence(_device, *_fence, allocator);
 
@@ -319,12 +319,12 @@ tu_RegisterDisplayEventEXT(VkDevice                           _device,
                                        allocator,
                                        NULL,
                                        sync_fd);
+
+      close(sync_fd);
    } else {
       ret = VK_ERROR_OUT_OF_HOST_MEMORY;
    }
 
-   close(sync_fd);
-
    if (ret != VK_SUCCESS)
       tu_DestroyFence(_device, *_fence, allocator);
 

src/gallium/auxiliary/draw/draw_context.c

@@ -200,7 +200,7 @@ void draw_new_instance(struct draw_context *draw)
 void draw_destroy( struct draw_context *draw )
 {
    struct pipe_context *pipe;
-   unsigned i, j;
+   unsigned i, j, k;
 
    if (!draw)
       return;
@@ -211,8 +211,10 @@ void draw_destroy( struct draw_context *draw )
     */
    for (i = 0; i < 2; i++) {
       for (j = 0; j < 2; j++) {
-         if (draw->rasterizer_no_cull[i][j]) {
-            pipe->delete_rasterizer_state(pipe, draw->rasterizer_no_cull[i][j]);
+         for (k = 0; k < 2; k++) {
+            if (draw->rasterizer_no_cull[i][j][k]) {
+               pipe->delete_rasterizer_state(pipe, draw->rasterizer_no_cull[i][j][k]);
+            }
          }
       }
    }
@@ -1056,26 +1058,26 @@ draw_current_shader_num_written_culldistances(const struct draw_context *draw)
  */
 void *
 draw_get_rasterizer_no_cull( struct draw_context *draw,
-                             boolean scissor,
-                             boolean flatshade )
+                             const struct pipe_rasterizer_state *base_rast )
 {
-   if (!draw->rasterizer_no_cull[scissor][flatshade]) {
+   if (!draw->rasterizer_no_cull[base_rast->scissor][base_rast->flatshade][base_rast->rasterizer_discard]) {
       /* create now */
       struct pipe_context *pipe = draw->pipe;
       struct pipe_rasterizer_state rast;
 
       memset(&rast, 0, sizeof(rast));
-      rast.scissor = scissor;
-      rast.flatshade = flatshade;
+      rast.scissor = base_rast->scissor;
+      rast.flatshade = base_rast->flatshade;
+      rast.rasterizer_discard = base_rast->rasterizer_discard;
       rast.front_ccw = 1;
       rast.half_pixel_center = draw->rasterizer->half_pixel_center;
       rast.bottom_edge_rule = draw->rasterizer->bottom_edge_rule;
       rast.clip_halfz = draw->rasterizer->clip_halfz;
 
-      draw->rasterizer_no_cull[scissor][flatshade] =
+      draw->rasterizer_no_cull[base_rast->scissor][base_rast->flatshade][base_rast->rasterizer_discard] =
          pipe->create_rasterizer_state(pipe, &rast);
    }
-   return draw->rasterizer_no_cull[scissor][flatshade];
+   return draw->rasterizer_no_cull[base_rast->scissor][base_rast->flatshade][base_rast->rasterizer_discard];
 }
 
 void

src/gallium/auxiliary/draw/draw_pipe_aaline.c

@@ -529,7 +529,7 @@ aaline_first_line(struct draw_stage *stage, struct prim_header *header)
    draw->suspend_flushing = TRUE;
 
    /* Disable triangle culling, stippling, unfilled mode etc. */
-   r = draw_get_rasterizer_no_cull(draw, rast->scissor, rast->flatshade);
+   r = draw_get_rasterizer_no_cull(draw, rast);
    pipe->bind_rasterizer_state(pipe, r);
 
    draw->suspend_flushing = FALSE;

src/gallium/auxiliary/draw/draw_pipe_aapoint.c

@@ -597,7 +597,7 @@ aapoint_first_point(struct draw_stage *stage, struct prim_header *header)
    draw->suspend_flushing = TRUE;
 
    /* Disable triangle culling, stippling, unfilled mode etc. */
-   r = draw_get_rasterizer_no_cull(draw, rast->scissor, rast->flatshade);
+   r = draw_get_rasterizer_no_cull(draw, rast);
    pipe->bind_rasterizer_state(pipe, r);
 
    draw->suspend_flushing = FALSE;

src/gallium/auxiliary/draw/draw_pipe_wide_line.c

@@ -147,7 +147,7 @@ static void wideline_first_line( struct draw_stage *stage,
    void *r;
 
    /* Disable triangle culling, stippling, unfilled mode etc. */
-   r = draw_get_rasterizer_no_cull(draw, rast->scissor, rast->flatshade);
+   r = draw_get_rasterizer_no_cull(draw, rast);
    draw->suspend_flushing = TRUE;
    pipe->bind_rasterizer_state(pipe, r);
    draw->suspend_flushing = FALSE;

src/gallium/auxiliary/draw/draw_pipe_wide_point.c

@@ -213,7 +213,7 @@ widepoint_first_point(struct draw_stage *stage,
    }
 
    /* Disable triangle culling, stippling, unfilled mode etc. */
-   r = draw_get_rasterizer_no_cull(draw, rast->scissor, rast->flatshade);
+   r = draw_get_rasterizer_no_cull(draw, rast);
    draw->suspend_flushing = TRUE;
    pipe->bind_rasterizer_state(pipe, r);
    draw->suspend_flushing = FALSE;

src/gallium/auxiliary/draw/draw_private.h

@@ -265,7 +265,7 @@ struct draw_context
    void *rast_handle;
 
    /** Rasterizer CSOs without culling/stipple/etc */
-   void *rasterizer_no_cull[2][2];
+   void *rasterizer_no_cull[2][2][2];
 
    struct pipe_viewport_state viewports[PIPE_MAX_VIEWPORTS];
    boolean identity_viewport;
@@ -536,8 +536,7 @@ void draw_do_flush( struct draw_context *draw, unsigned flags );
 
 void *
 draw_get_rasterizer_no_cull( struct draw_context *draw,
-                             boolean scissor,
-                             boolean flatshade );
+                             const struct pipe_rasterizer_state *rast );
 
 void
 draw_stats_clipper_primitives(struct draw_context *draw,

src/gallium/auxiliary/draw/draw_tess.c

@@ -350,9 +350,6 @@ int draw_tess_eval_shader_run(struct draw_tess_eval_shader *shader,
    shader->input_vertex_stride = input_stride;
    shader->input_info = input_info;
 
-   if (shader->draw->collect_statistics) {
-      shader->draw->statistics.ds_invocations += input_prim->primitive_count;
-   }
 #ifdef LLVM_AVAILABLE
    struct pipe_tessellation_factors factors;
    struct pipe_tessellator_data data = { 0 };
@@ -394,6 +391,10 @@ int draw_tess_eval_shader_run(struct draw_tess_eval_shader *shader,
       output += vert_start * vertex_size;
       llvm_tes_run(shader, i, num_input_vertices_per_patch, &data, &factors, (struct vertex_header *)output);
 
+      if (shader->draw->collect_statistics) {
+         shader->draw->statistics.ds_invocations += data.num_domain_points;
+      }
+
       uint32_t prim_len = u_prim_vertex_count(output_prims->prim)->min;
       output_prims->primitive_count += data.num_indices / prim_len;
       output_prims->primitive_lengths = REALLOC(output_prims->primitive_lengths, prim_start * sizeof(uint32_t),

src/gallium/auxiliary/util/u_blitter.c

@@ -1819,7 +1819,10 @@ static void do_blits(struct blitter_context_priv *ctx,
       int dst_z;
       for (dst_z = 0; dst_z < dstbox->depth; dst_z++) {
          struct pipe_surface *old;
-         float dst2src_scale = srcbox->depth / (float)dstbox->depth;
+         bool flipped = (srcbox->depth < 0);
+         float depth_center_offset = 0.0;
+         int src_depth = abs(srcbox->depth);
+         float src_z_step = src_depth / (float)dstbox->depth;
 
          /* Scale Z properly if the blit is scaled.
           *
@@ -1835,12 +1838,17 @@ static void do_blits(struct blitter_context_priv *ctx,
           *   src Z:  0 1 2 3 4 5 6 7
           *   dst Z:   0   1   2   3
           *
-          * dst_offset defines the offset needed for centering the pixels and
-          * it works with any scaling (not just 2x).
+          * This calculation is taken from the radv driver.
           */
-         float dst_offset = ((srcbox->depth - 1) -
-                             (dstbox->depth - 1) * dst2src_scale) * 0.5;
-         float src_z = (dst_z + dst_offset) * dst2src_scale;
+         if (src_target == PIPE_TEXTURE_3D)
+            depth_center_offset = 0.5 / dstbox->depth * src_depth;
+
+         if (flipped) {
+            src_z_step *= - 1;
+            depth_center_offset *= -1;
+         }
+
+         float src_z = dst_z * src_z_step + depth_center_offset;
 
          /* Set framebuffer state. */
          if (is_zsbuf) {

src/gallium/auxiliary/util/u_framebuffer.c

@@ -244,7 +244,7 @@ util_framebuffer_get_num_samples(const struct pipe_framebuffer_state *fb)
                   fb->zsbuf->nr_samples);
    }
 
-   return 1;
+   return MAX2(fb->samples, 1);
 }
 
 

src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c

@@ -1118,8 +1118,6 @@ etna_compile_shader_nir(struct etna_shader_variant *v)
       NIR_PASS_V(s, nir_lower_bool_to_int32);
    }
 
-   etna_optimize_loop(s);
-
    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
       nir_print_shader(s, stdout);
 

src/gallium/drivers/etnaviv/etnaviv_texture_desc.c

@@ -83,6 +83,8 @@ etna_create_sampler_state_desc(struct pipe_context *pipe,
    if (!cs)
       return NULL;
 
+   cs->base = *ss;
+
    cs->SAMP_CTRL0 =
       VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
       VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
@@ -290,16 +292,17 @@ etna_emit_texture_desc(struct etna_context *ctx)
          if ((1 << x) & active_samplers) {
             struct etna_sampler_state_desc *ss = etna_sampler_state_desc(ctx->sampler[x]);
             struct etna_sampler_view_desc *sv = etna_sampler_view_desc(ctx->sampler_view[x]);
+            uint32_t SAMP_CTRL0 = ss->SAMP_CTRL0 | sv->SAMP_CTRL0;
 
             if (texture_use_int_filter(&sv->base, &ss->base, true))
-               sv->SAMP_CTRL0 |= VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER;
+               SAMP_CTRL0 |= VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER;
 
             etna_set_state(stream, VIVS_NTE_DESCRIPTOR_TX_CTRL(x),
                COND(sv->ts.enable, VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE) |
                VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(sv->ts.mode) |
                VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x)|
                COND(sv->ts.comp, VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION));
-            etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(x), ss->SAMP_CTRL0 | sv->SAMP_CTRL0);
+            etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(x), SAMP_CTRL0);
             etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(x), ss->SAMP_CTRL1 | sv->SAMP_CTRL1);
             etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(x), ss->SAMP_LOD_MINMAX);
             etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(x), ss->SAMP_LOD_BIAS);

src/gallium/drivers/etnaviv/etnaviv_texture_state.c

@@ -93,6 +93,8 @@ etna_create_sampler_state_state(struct pipe_context *pipe,
    if (!cs)
       return NULL;
 
+   cs->base = *ss;
+
    cs->TE_SAMPLER_CONFIG0 =
       VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
       VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
@@ -348,11 +350,12 @@ etna_emit_texture_state(struct etna_context *ctx)
          if ((1 << x) & active_samplers) {
             ss = etna_sampler_state(ctx->sampler[x]);
             sv = etna_sampler_view(ctx->sampler_view[x]);
+            uint32_t TE_SAMPLER_LOG_SIZE = sv->TE_SAMPLER_LOG_SIZE;
 
             if (texture_use_int_filter(&sv->base, &ss->base, false))
-               sv->TE_SAMPLER_LOG_SIZE |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
+               TE_SAMPLER_LOG_SIZE |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
 
-            /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
+            /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), TE_SAMPLER_LOG_SIZE);
          }
       }
    }

src/gallium/drivers/freedreno/freedreno_gmem.c

@@ -528,11 +528,15 @@ lookup_gmem_state(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
 	struct fd_screen *screen = batch->ctx->screen;
 	struct fd_gmem_cache *cache = &screen->gmem_cache;
 	struct fd_gmem_stateobj *gmem = NULL;
+
+	/* Lock before allocating gmem_key, since that a screen-wide
+	 * ralloc pool and ralloc itself is not thread-safe.
+	 */
+	fd_screen_lock(screen);
+
 	struct gmem_key *key = gmem_key_init(batch, assume_zs, no_scis_opt);
 	uint32_t hash = gmem_key_hash(key);
 
-	fd_screen_lock(screen);
-
 	struct hash_entry *entry =
 		_mesa_hash_table_search_pre_hashed(cache->ht, hash, key);
 	if (entry) {

src/gallium/drivers/iris/iris_genx_protos.h

@@ -29,6 +29,7 @@
 
 /* iris_state.c */
 void genX(init_state)(struct iris_context *ice);
+void genX(init_screen_state)(struct iris_screen *screen);
 void genX(emit_hashing_mode)(struct iris_context *ice,
                              struct iris_batch *batch,
                              unsigned width, unsigned height,

src/gallium/drivers/iris/iris_screen.c

@@ -58,6 +58,24 @@
 #include "intel/common/gen_uuid.h"
 #include "iris_monitor.h"
 
+#define genX_call(devinfo, func, ...)             \
+   switch (devinfo.gen) {                        \
+   case 12:                                       \
+      gen12_##func(__VA_ARGS__);                  \
+      break;                                      \
+   case 11:                                       \
+      gen11_##func(__VA_ARGS__);                  \
+      break;                                      \
+   case 9:                                        \
+      gen9_##func(__VA_ARGS__);                   \
+      break;                                      \
+   case 8:                                        \
+      gen8_##func(__VA_ARGS__);                   \
+      break;                                      \
+   default:                                       \
+      unreachable("Unknown hardware generation"); \
+   }
+
 static void
 iris_flush_frontbuffer(struct pipe_screen *_screen,
                        struct pipe_resource *resource,
@@ -847,6 +865,8 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
    pscreen->get_driver_query_info = iris_get_monitor_info;
 
+   genX_call(screen->devinfo, init_screen_state, screen);
+
    glsl_type_singleton_init_or_ref();
 
    return pscreen;

src/gallium/drivers/iris/iris_state.c

@@ -7761,6 +7761,41 @@ iris_set_frontend_noop(struct pipe_context *ctx, bool enable)
    }
 }
 
+void
+genX(init_screen_state)(struct iris_screen *screen)
+{
+   screen->vtbl.destroy_state = iris_destroy_state;
+   screen->vtbl.init_render_context = iris_init_render_context;
+   screen->vtbl.init_compute_context = iris_init_compute_context;
+   screen->vtbl.upload_render_state = iris_upload_render_state;
+   screen->vtbl.update_surface_base_address = iris_update_surface_base_address;
+   screen->vtbl.upload_compute_state = iris_upload_compute_state;
+   screen->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
+   screen->vtbl.emit_mi_report_perf_count = iris_emit_mi_report_perf_count;
+   screen->vtbl.rebind_buffer = iris_rebind_buffer;
+   screen->vtbl.load_register_reg32 = iris_load_register_reg32;
+   screen->vtbl.load_register_reg64 = iris_load_register_reg64;
+   screen->vtbl.load_register_imm32 = iris_load_register_imm32;
+   screen->vtbl.load_register_imm64 = iris_load_register_imm64;
+   screen->vtbl.load_register_mem32 = iris_load_register_mem32;
+   screen->vtbl.load_register_mem64 = iris_load_register_mem64;
+   screen->vtbl.store_register_mem32 = iris_store_register_mem32;
+   screen->vtbl.store_register_mem64 = iris_store_register_mem64;
+   screen->vtbl.store_data_imm32 = iris_store_data_imm32;
+   screen->vtbl.store_data_imm64 = iris_store_data_imm64;
+   screen->vtbl.copy_mem_mem = iris_copy_mem_mem;
+   screen->vtbl.derived_program_state_size = iris_derived_program_state_size;
+   screen->vtbl.store_derived_program_state = iris_store_derived_program_state;
+   screen->vtbl.create_so_decl_list = iris_create_so_decl_list;
+   screen->vtbl.populate_vs_key = iris_populate_vs_key;
+   screen->vtbl.populate_tcs_key = iris_populate_tcs_key;
+   screen->vtbl.populate_tes_key = iris_populate_tes_key;
+   screen->vtbl.populate_gs_key = iris_populate_gs_key;
+   screen->vtbl.populate_fs_key = iris_populate_fs_key;
+   screen->vtbl.populate_cs_key = iris_populate_cs_key;
+   screen->vtbl.lost_genx_state = iris_lost_genx_state;
+}
+
 void
 genX(init_state)(struct iris_context *ice)
 {
@@ -7809,37 +7844,6 @@ genX(init_state)(struct iris_context *ice)
    ctx->set_stream_output_targets = iris_set_stream_output_targets;
    ctx->set_frontend_noop = iris_set_frontend_noop;
 
-   screen->vtbl.destroy_state = iris_destroy_state;
-   screen->vtbl.init_render_context = iris_init_render_context;
-   screen->vtbl.init_compute_context = iris_init_compute_context;
-   screen->vtbl.upload_render_state = iris_upload_render_state;
-   screen->vtbl.update_surface_base_address = iris_update_surface_base_address;
-   screen->vtbl.upload_compute_state = iris_upload_compute_state;
-   screen->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
-   screen->vtbl.emit_mi_report_perf_count = iris_emit_mi_report_perf_count;
-   screen->vtbl.rebind_buffer = iris_rebind_buffer;
-   screen->vtbl.load_register_reg32 = iris_load_register_reg32;
-   screen->vtbl.load_register_reg64 = iris_load_register_reg64;
-   screen->vtbl.load_register_imm32 = iris_load_register_imm32;
-   screen->vtbl.load_register_imm64 = iris_load_register_imm64;
-   screen->vtbl.load_register_mem32 = iris_load_register_mem32;
-   screen->vtbl.load_register_mem64 = iris_load_register_mem64;
-   screen->vtbl.store_register_mem32 = iris_store_register_mem32;
-   screen->vtbl.store_register_mem64 = iris_store_register_mem64;
-   screen->vtbl.store_data_imm32 = iris_store_data_imm32;
-   screen->vtbl.store_data_imm64 = iris_store_data_imm64;
-   screen->vtbl.copy_mem_mem = iris_copy_mem_mem;
-   screen->vtbl.derived_program_state_size = iris_derived_program_state_size;
-   screen->vtbl.store_derived_program_state = iris_store_derived_program_state;
-   screen->vtbl.create_so_decl_list = iris_create_so_decl_list;
-   screen->vtbl.populate_vs_key = iris_populate_vs_key;
-   screen->vtbl.populate_tcs_key = iris_populate_tcs_key;
-   screen->vtbl.populate_tes_key = iris_populate_tes_key;
-   screen->vtbl.populate_gs_key = iris_populate_gs_key;
-   screen->vtbl.populate_fs_key = iris_populate_fs_key;
-   screen->vtbl.populate_cs_key = iris_populate_cs_key;
-   screen->vtbl.lost_genx_state = iris_lost_genx_state;
-
    ice->state.dirty = ~0ull;
    ice->state.stage_dirty = ~0ull;
 

src/gallium/drivers/llvmpipe/lp_setup_line.c

@@ -597,16 +597,9 @@ try_setup_line( struct lp_setup_context *setup,
     * Determine how many scissor planes we need, that is drop scissor
     * edges if the bounding box of the tri is fully inside that edge.
     */
-   if (setup->scissor_test) {
-      /* why not just use draw_regions */
-      scissor = &setup->scissors[viewport_index];
-      scissor_planes_needed(s_planes, &bboxpos, scissor);
-      nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
-   } else {
-      scissor = &setup->draw_regions[viewport_index];
-      scissor_planes_needed(s_planes, &bboxpos, scissor);
-      nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
-   }
+   scissor = &setup->draw_regions[viewport_index];
+   scissor_planes_needed(s_planes, &bboxpos, scissor);
+   nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
 
    line = lp_setup_alloc_triangle(scene,
                                   key->num_inputs,

src/gallium/drivers/llvmpipe/lp_setup_tri.c

@@ -359,16 +359,9 @@ do_triangle_ccw(struct lp_setup_context *setup,
     * Determine how many scissor planes we need, that is drop scissor
     * edges if the bounding box of the tri is fully inside that edge.
     */
-   if (setup->scissor_test) {
-      /* why not just use draw_regions */
-      scissor = &setup->scissors[viewport_index];
-      scissor_planes_needed(s_planes, &bboxpos, scissor);
-      nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
-   } else {
-      scissor = &setup->draw_regions[viewport_index];
-      scissor_planes_needed(s_planes, &bboxpos, scissor);
-      nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
-   }
+   scissor = &setup->draw_regions[viewport_index];
+   scissor_planes_needed(s_planes, &bboxpos, scissor);
+   nr_planes += s_planes[0] + s_planes[1] + s_planes[2] + s_planes[3];
 
    tri = lp_setup_alloc_triangle(scene,
                                  key->num_inputs,

src/gallium/drivers/panfrost/pan_assemble.c

@@ -284,9 +284,6 @@ panfrost_shader_compile(struct panfrost_context *ctx,
         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
 
-        /* On Bifrost it's a sysval, on Midgard it's a varying */
-        state->reads_frag_coord = s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD);
-
         state->writes_global = s->info.writes_memory;
 
         switch (stage) {
@@ -342,7 +339,8 @@ panfrost_shader_compile(struct panfrost_context *ctx,
         state->helper_invocations = s->info.fs.needs_helper_invocations;
         state->stack_size = program->tls_size;
 
-        state->reads_frag_coord = s->info.inputs_read & (1 << VARYING_SLOT_POS);
+        state->reads_frag_coord = (s->info.inputs_read & (1 << VARYING_SLOT_POS)) ||
+                                  (s->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD));
         state->reads_point_coord = s->info.inputs_read & (1 << VARYING_SLOT_PNTC);
         state->reads_face = (s->info.inputs_read & (1 << VARYING_SLOT_FACE)) ||
                             (s->info.system_values_read & (1 << SYSTEM_VALUE_FRONT_FACE));

src/gallium/drivers/panfrost/pan_cmdstream.c

@@ -296,7 +296,10 @@ panfrost_emit_bifrost_blend(struct panfrost_batch *batch,
                                 else
                                         cfg.bifrost.internal.mode = MALI_BIFROST_BLEND_MODE_FIXED_FUNCTION;
 
-                                cfg.bifrost.internal.fixed_function.num_comps = format_desc->nr_channels;
+                                /* If we want the conversion to work properly,
+                                 * num_comps must be set to 4
+                                 */
+                                cfg.bifrost.internal.fixed_function.num_comps = 4;
                                 cfg.bifrost.internal.fixed_function.conversion.memory_format.format =
                                         panfrost_format_to_bifrost_blend(format_desc, true);
                                 if (dev->quirks & HAS_SWIZZLES) {

src/gallium/drivers/panfrost/pan_resource.c

@@ -728,6 +728,20 @@ pan_alloc_staging(struct panfrost_context *ctx, struct panfrost_resource *rsc,
         return pan_resource(pstaging);
 }
 
+static enum pipe_format
+pan_blit_format(enum pipe_format fmt)
+{
+        const struct util_format_description *desc;
+        desc = util_format_description(fmt);
+
+        /* This must be an emulated format (using u_transfer_helper) as if it
+         * was real RGTC we wouldn't have used AFBC and needed a blit. */
+        if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC)
+                fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
+
+        return fmt;
+}
+
 static void
 pan_blit_from_staging(struct pipe_context *pctx, struct panfrost_transfer *trans)
 {
@@ -735,14 +749,14 @@ pan_blit_from_staging(struct pipe_context *pctx, struct panfrost_transfer *trans
         struct pipe_blit_info blit = {0};
 
         blit.dst.resource = dst;
-        blit.dst.format   = dst->format;
+        blit.dst.format   = pan_blit_format(dst->format);
         blit.dst.level    = trans->base.level;
         blit.dst.box      = trans->base.box;
         blit.src.resource = trans->staging.rsrc;
-        blit.src.format   = trans->staging.rsrc->format;
+        blit.src.format   = pan_blit_format(trans->staging.rsrc->format);
         blit.src.level    = 0;
         blit.src.box      = trans->staging.box;
-        blit.mask = util_format_get_mask(trans->staging.rsrc->format);
+        blit.mask = util_format_get_mask(blit.src.format);
         blit.filter = PIPE_TEX_FILTER_NEAREST;
 
         panfrost_blit(pctx, &blit);
@@ -755,14 +769,14 @@ pan_blit_to_staging(struct pipe_context *pctx, struct panfrost_transfer *trans)
         struct pipe_blit_info blit = {0};
 
         blit.src.resource = src;
-        blit.src.format   = src->format;
+        blit.src.format   = pan_blit_format(src->format);
         blit.src.level    = trans->base.level;
         blit.src.box      = trans->base.box;
         blit.dst.resource = trans->staging.rsrc;
-        blit.dst.format   = trans->staging.rsrc->format;
+        blit.dst.format   = pan_blit_format(trans->staging.rsrc->format);
         blit.dst.level    = 0;
         blit.dst.box      = trans->staging.box;
-        blit.mask = util_format_get_mask(trans->staging.rsrc->format);
+        blit.mask = util_format_get_mask(blit.dst.format);
         blit.filter = PIPE_TEX_FILTER_NEAREST;
 
         panfrost_blit(pctx, &blit);

src/gallium/drivers/softpipe/sp_screen.c

@@ -89,7 +89,8 @@ static const nir_shader_compiler_options sp_compiler_options = {
 
 static const void *
 softpipe_get_compiler_options(struct pipe_screen *pscreen,
-                              enum pipe_shader_ir ir, unsigned shader)
+                              enum pipe_shader_ir ir,
+                              enum pipe_shader_type shader)
 {
    assert(ir == PIPE_SHADER_IR_NIR);
    return &sp_compiler_options;

src/gallium/drivers/zink/zink_blit.c

@@ -14,8 +14,11 @@ blit_resolve(struct zink_context *ctx, const struct pipe_blit_info *info)
        util_format_get_mask(info->src.format) != info->mask ||
        util_format_is_depth_or_stencil(info->dst.format) ||
        info->scissor_enable ||
-       info->alpha_blend ||
-       info->render_condition_enable)
+       info->alpha_blend)
+      return false;
+
+   if (info->render_condition_enable &&
+       ctx->render_condition_active)
       return false;
 
    struct zink_resource *src = zink_resource(info->src.resource);
@@ -67,8 +70,11 @@ blit_native(struct zink_context *ctx, const struct pipe_blit_info *info)
    if (util_format_get_mask(info->dst.format) != info->mask ||
        util_format_get_mask(info->src.format) != info->mask ||
        info->scissor_enable ||
-       info->alpha_blend ||
-       info->render_condition_enable)
+       info->alpha_blend)
+      return false;
+
+   if (info->render_condition_enable &&
+       ctx->render_condition_active)
       return false;
 
    if (util_format_is_depth_or_stencil(info->dst.format) &&

src/gallium/drivers/zink/zink_context.h

@@ -130,7 +130,7 @@ struct zink_context {
 
    struct list_head suspended_queries;
    struct list_head primitives_generated_queries;
-   bool queries_disabled;
+   bool queries_disabled, render_condition_active;
 
    struct pipe_resource *dummy_buffer;
    struct pipe_resource *null_buffers[5]; /* used to create zink_framebuffer->null_surface, one buffer per samplecount */

src/gallium/drivers/zink/zink_query.c

@@ -492,6 +492,7 @@ zink_render_condition(struct pipe_context *pctx,
 
    if (query == NULL) {
       screen->vk_CmdEndConditionalRenderingEXT(batch->cmdbuf);
+      ctx->render_condition_active = false;
       return;
    }
 
@@ -528,6 +529,7 @@ zink_render_condition(struct pipe_context *pctx,
    begin_info.buffer = res->buffer;
    begin_info.flags = begin_flags;
    screen->vk_CmdBeginConditionalRenderingEXT(batch->cmdbuf, &begin_info);
+   ctx->render_condition_active = true;
 
    zink_batch_reference_resource_rw(batch, res, true);
 

src/gallium/frontends/clover/spirv/invocation.cpp

@@ -199,6 +199,7 @@ namespace {
             default:
                break;
             }
+            break;
 
          case SpvOpDecorate: {
             const auto id = get<SpvId>(inst, 1);

src/gallium/frontends/lavapipe/lvp_device.c

@@ -312,7 +312,7 @@ void lvp_GetPhysicalDeviceFeatures(
       .depthBounds                              = (pdevice->pscreen->get_param(pdevice->pscreen, PIPE_CAP_DEPTH_BOUNDS_TEST) != 0),
       .wideLines                                = false,
       .largePoints                              = true,
-      .alphaToOne                               = false,
+      .alphaToOne                               = true,
       .multiViewport                            = true,
       .samplerAnisotropy                        = false, /* FINISHME */
       .textureCompressionETC2                   = false,

src/gallium/frontends/lavapipe/lvp_formats.c

@@ -208,7 +208,9 @@ lvp_physical_device_get_format_properties(struct lvp_physical_device *physical_d
    if (physical_device->pscreen->is_format_supported(physical_device->pscreen, pformat,
                                                      PIPE_TEXTURE_2D, 0, 0, PIPE_BIND_RENDER_TARGET)) {
       features |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT;
-      features |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
+      /* SNORM blending on llvmpipe fails CTS - disable for now */
+      if (!util_format_is_snorm(pformat))
+         features |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
       features |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
    }
 

src/gallium/frontends/va/config.c

@@ -99,7 +99,7 @@ vlVaQueryConfigEntrypoints(VADriverContextP ctx, VAProfile profile,
 				PIPE_VIDEO_CAP_SUPPORTED))
       entrypoint_list[(*num_entrypoints)++] = VAEntrypointEncSlice;
 
-   if (num_entrypoints == 0)
+   if (*num_entrypoints == 0)
       return VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
 
    assert(*num_entrypoints <= ctx->max_entrypoints);

src/gallium/frontends/vdpau/mixer.c

@@ -143,7 +143,7 @@ vlVdpVideoMixerCreate(VdpDevice device,
    }
    ret = VDP_STATUS_INVALID_VALUE;
    if (vmixer->max_layers > 4) {
-      VDPAU_MSG(VDPAU_WARN, "[VDPAU] Max layers > 4 not supported\n", vmixer->max_layers);
+      VDPAU_MSG(VDPAU_WARN, "[VDPAU] Max layers %u > 4 not supported\n", vmixer->max_layers);
       goto no_params;
    }
 

src/intel/compiler/brw_fs.cpp

@@ -7800,7 +7800,8 @@ fs_visitor::fixup_3src_null_dest()
 static const fs_inst *
 find_halt_control_flow_region_start(const fs_visitor *v)
 {
-   if (brw_wm_prog_data(v->prog_data)->uses_kill) {
+   if (v->stage == MESA_SHADER_FRAGMENT &&
+       brw_wm_prog_data(v->prog_data)->uses_kill) {
       foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
          if (inst->opcode == FS_OPCODE_DISCARD_JUMP ||
              inst->opcode == FS_OPCODE_PLACEHOLDER_HALT)

src/intel/vulkan/anv_formats.c

@@ -923,6 +923,31 @@ anv_get_image_format_properties(
       }
    }
 
+   if (info->flags & VK_IMAGE_CREATE_DISJOINT_BIT) {
+      /* From the Vulkan 1.2.149 spec, VkImageCreateInfo:
+       *
+       *    If format is a multi-planar format, and if imageCreateFormatFeatures
+       *    (as defined in Image Creation Limits) does not contain
+       *    VK_FORMAT_FEATURE_DISJOINT_BIT, then flags must not contain
+       *    VK_IMAGE_CREATE_DISJOINT_BIT.
+       */
+      if (format->n_planes > 1 &&
+          !(format_feature_flags & VK_FORMAT_FEATURE_DISJOINT_BIT)) {
+         goto unsupported;
+      }
+
+      /* From the Vulkan 1.2.149 spec, VkImageCreateInfo:
+       *
+       * If format is not a multi-planar format, and flags does not include
+       * VK_IMAGE_CREATE_ALIAS_BIT, flags must not contain
+       * VK_IMAGE_CREATE_DISJOINT_BIT.
+       */
+      if (format->n_planes == 1 &&
+          !(info->flags & VK_IMAGE_CREATE_ALIAS_BIT)) {
+          goto unsupported;
+      }
+   }
+
    if (info->usage & VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT) {
       /* Nothing to check. */
    }

src/intel/vulkan/anv_image.c

@@ -563,14 +563,14 @@ make_surface(struct anv_device *device,
       anv_get_format_plane(&device->info, image->vk_format, aspect, image->tiling);
    struct anv_surface *anv_surf = &image->planes[plane].surface;
 
-   const isl_surf_usage_flags_t usage =
-      choose_isl_surf_usage(image->create_flags, image->usage,
-                            isl_extra_usage_flags, aspect);
-
    VkImageUsageFlags plane_vk_usage =
       aspect == VK_IMAGE_ASPECT_STENCIL_BIT ?
       image->stencil_usage : image->usage;
 
+   const isl_surf_usage_flags_t usage =
+      choose_isl_surf_usage(image->create_flags, plane_vk_usage,
+                            isl_extra_usage_flags, aspect);
+
    bool needs_shadow =
       anv_image_plane_needs_shadow_surface(&device->info,
                                    plane_format,

src/mesa/main/clear.c

@@ -30,6 +30,7 @@
 
 
 
+#include "glformats.h"
 #include "glheader.h"
 #include "clear.h"
 #include "context.h"
@@ -589,7 +590,20 @@ clear_bufferfv(struct gl_context *ctx, GLenum buffer, GLint drawbuffer,
           * hook instead.
           */
          const GLclampd clearSave = ctx->Depth.Clear;
-         ctx->Depth.Clear = *value;
+
+         /* Page 263 (page 279 of the PDF) of the OpenGL 3.0 spec says:
+          *
+          *     "If buffer is DEPTH, drawbuffer must be zero, and value points
+          *     to the single depth value to clear the depth buffer to.
+          *     Clamping and type conversion for fixed-point depth buffers are
+          *     performed in the same fashion as for ClearDepth."
+          */
+         const struct gl_renderbuffer *rb =
+            ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
+         const bool is_float_depth =
+            _mesa_has_depth_float_channel(rb->InternalFormat);
+         ctx->Depth.Clear = is_float_depth ? *value : SATURATE(*value);
+
          ctx->Driver.Clear(ctx, BUFFER_BIT_DEPTH);
          ctx->Depth.Clear = clearSave;
       }
@@ -724,8 +738,20 @@ clear_bufferfi(struct gl_context *ctx, GLenum buffer, GLint drawbuffer,
       const GLclampd clearDepthSave = ctx->Depth.Clear;
       const GLuint clearStencilSave = ctx->Stencil.Clear;
 
-      /* set new clear values */
-      ctx->Depth.Clear = depth;
+      /* set new clear values
+       *
+       * Page 263 (page 279 of the PDF) of the OpenGL 3.0 spec says:
+       *
+       *     "depth and stencil are the values to clear the depth and stencil
+       *     buffers to, respectively. Clamping and type conversion for
+       *     fixed-point depth buffers are performed in the same fashion as
+       *     for ClearDepth."
+       */
+      const struct gl_renderbuffer *rb =
+         ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
+      const bool has_float_depth = rb &&
+         _mesa_has_depth_float_channel(rb->InternalFormat);
+      ctx->Depth.Clear = has_float_depth ? depth : SATURATE(depth);
       ctx->Stencil.Clear = stencil;
 
       /* clear buffers */

src/mesa/main/glformats.c

@@ -1335,6 +1335,15 @@ _mesa_is_depth_or_stencil_format(GLenum format)
    }
 }
 
+/**
+ * Test if the given image format has a floating-point depth component.
+ */
+GLboolean
+_mesa_has_depth_float_channel(GLenum internalFormat)
+{
+   return internalFormat == GL_DEPTH32F_STENCIL8 ||
+          internalFormat == GL_DEPTH_COMPONENT32F;
+}
 
 /**
  * Test if an image format is a supported compressed format.

src/mesa/main/glformats.h

@@ -29,6 +29,7 @@
 
 
 #include <stdbool.h>
+#include <stdint.h>
 #include <GL/gl.h>
 
 
@@ -104,6 +105,9 @@ _mesa_is_depthstencil_format(GLenum format);
 extern GLboolean
 _mesa_is_depth_or_stencil_format(GLenum format);
 
+extern GLboolean
+_mesa_has_depth_float_channel(GLenum internalFormat);
+
 extern GLboolean
 _mesa_is_compressed_format(const struct gl_context *ctx, GLenum format);
 

src/mesa/main/readpix.c

@@ -910,8 +910,7 @@ read_pixels_es3_error_check(struct gl_context *ctx, GLenum format, GLenum type,
    const GLenum data_type = _mesa_get_format_datatype(rb->Format);
    GLboolean is_unsigned_int = GL_FALSE;
    GLboolean is_signed_int = GL_FALSE;
-   GLboolean is_float_depth = (internalFormat == GL_DEPTH_COMPONENT32F) ||
-         (internalFormat == GL_DEPTH32F_STENCIL8);
+   GLboolean is_float_depth = _mesa_has_depth_float_channel(internalFormat);
 
    is_unsigned_int = _mesa_is_enum_format_unsigned_int(internalFormat);
    if (!is_unsigned_int) {

src/mesa/main/varray.c

@@ -459,8 +459,7 @@ static const uint16_t vertex_formats[][4][4] = {
  */
 static enum pipe_format
 vertex_format_to_pipe_format(GLubyte size, GLenum16 type, GLenum16 format,
-                             GLboolean normalized, GLboolean integer,
-                             GLboolean doubles)
+                             bool normalized, bool integer, bool doubles)
 {
    assert(size >= 1 && size <= 4);
    assert(format == GL_RGBA || format == GL_BGRA);
@@ -674,8 +673,8 @@ validate_array_format(struct gl_context *ctx, const char *func,
                       struct gl_vertex_array_object *vao,
                       GLuint attrib, GLbitfield legalTypesMask,
                       GLint sizeMin, GLint sizeMax,
-                      GLint size, GLenum type, GLboolean normalized,
-                      GLboolean integer, GLboolean doubles,
+                      GLint size, GLenum type, bool normalized,
+                      bool integer, bool doubles,
                       GLuint relativeOffset, GLenum format)
 {
    GLbitfield typeBit;

src/mesa/state_tracker/st_glsl_to_nir.cpp

@@ -834,6 +834,8 @@ st_link_nir(struct gl_context *ctx,
        */
       shader_info old_info = prog->info;
       prog->info = prog->nir->info;
+      prog->info.name = old_info.name;
+      prog->info.label = old_info.label;
       prog->info.num_ssbos = old_info.num_ssbos;
       prog->info.num_ubos = old_info.num_ubos;
       prog->info.num_abos = old_info.num_abos;

src/panfrost/bifrost/bir.c

@@ -168,6 +168,10 @@ bi_writes_component(bi_instruction *ins, unsigned comp)
         return comp < bi_get_component_count(ins, -1);
 }
 
+/* Determine effective writemask for RA/DCE, noting that we currently act
+ * per-register hence aligning. TODO: when real write masks are handled in
+ * packing (not for a while), update this routine, removing the align */
+
 unsigned
 bi_writemask(bi_instruction *ins)
 {
@@ -175,7 +179,7 @@ bi_writemask(bi_instruction *ins)
         unsigned size = nir_alu_type_get_type_size(T);
         unsigned bytes_per_comp = size / 8;
         unsigned components = bi_get_component_count(ins, -1);
-        unsigned bytes = bytes_per_comp * components;
+        unsigned bytes = ALIGN_POT(bytes_per_comp * components, 4);
         unsigned mask = (1 << bytes) - 1;
         unsigned shift = ins->dest_offset * 4; /* 32-bit words */
         return (mask << shift);

src/panfrost/lib/pan_blit.c

@@ -569,7 +569,7 @@ bifrost_load_emit_blend_rt(struct pan_pool *pool, void *out,
                         cfg.bifrost.equation.alpha.b = MALI_BLEND_OPERAND_B_SRC;
                         cfg.bifrost.equation.alpha.c = MALI_BLEND_OPERAND_C_ZERO;
                         cfg.bifrost.equation.color_mask = 0xf;
-                        cfg.bifrost.internal.fixed_function.num_comps = format_desc->nr_channels;
+                        cfg.bifrost.internal.fixed_function.num_comps = 4;
                         cfg.bifrost.internal.fixed_function.conversion.memory_format.format =
                                 panfrost_format_to_bifrost_blend(format_desc, true);
                         cfg.bifrost.internal.fixed_function.conversion.register_format =

src/panfrost/lib/pan_scratch.c

@@ -67,7 +67,7 @@ unsigned
 panfrost_get_stack_shift(unsigned stack_size)
 {
         if (stack_size)
-                return util_logbase2(DIV_ROUND_UP(stack_size, 16));
+                return util_logbase2_ceil(DIV_ROUND_UP(stack_size, 16));
         else
                 return 0;
 }

src/util/set.c

@@ -223,13 +223,17 @@ _mesa_set_clear(struct set *set, void (*delete_function)(struct set_entry *entry
    if (!set)
       return;
 
-   set_foreach (set, entry) {
-      if (delete_function)
+   struct set_entry *entry;
+
+   for (entry = set->table; entry != set->table + set->size; entry++) {
+      if (entry_is_present(entry) && delete_function != NULL)
          delete_function(entry);
-      entry->key = deleted_key;
+
+      entry->key = NULL;
    }
 
-   set->entries = set->deleted_entries = 0;
+   set->entries = 0;
+   set->deleted_entries = 0;
 }
 
 /**