Compare commits
9 Commits
mesa-23.3.
...
mesa-23.3.
Author | SHA1 | Date | |
---|---|---|---|
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1fbdd37d4c | ||
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421a8aaff1 | ||
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dced0dba02 | ||
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3ff4768692 | ||
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54f93b1788 | ||
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2525258917 | ||
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94ad18d1e7 | ||
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3ed7b95a55 | ||
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dd56f591e5 |
@@ -1,4 +1,244 @@
|
||||
[
|
||||
{
|
||||
"sha": "f843b14c171299e1696ca6d971ccaa496f60c3ab",
|
||||
"description": "d3d12: Fix hevc encoder 32-bit build (uint64_t -> size_t)",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "ae62fc01fa95d7121451ae10d1988a73ff645c9b",
|
||||
"description": "d3d12: Fix h264 encoder 32-bit build (uint64_t -> size_t)",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "500955b6cbc367439549a92498201d34b1f3d5d9",
|
||||
"description": "nak: Only insert barriers around ifs if they actually re-converge",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "804201a3d70af2c78612052ab3e9c13ee0bdbbcb",
|
||||
"description": "nak: Run rustfmt",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "e93935dd0497c1908c5cb6558258266bba07230e",
|
||||
"description": "nvk: Limit shader stages to supported stages",
|
||||
"nominated": false,
|
||||
"nomination_type": 1,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": "c7c73d6d17b38a2f4c899a34614eb3750eea6034",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "6f9be9a2a055ecbf7850eccae2cb2c819469e241",
|
||||
"description": "hasvk: ensure we reapply always pipeline dynamic state in runtime state",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "2d98236dd525622527df22179756f7b0f1466afa",
|
||||
"description": "ac/nir: fix partial mesh shader output writes on GFX11",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "240e16fc8e27ba76afa1bf5adbd6d70c680027ac",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "f59665bb62b579c6cc26155a26ce557f9f3357d2",
|
||||
"description": "venus: Do not submit batch manually when no feedback is required",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "a55d26b566f1ba67f770f689e4de9b0f70c0d47b",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "1924cdc2898b0a14a8afd13db3a06dab9e1d032e",
|
||||
"description": "d3d12: Fix multidimensional array ordering",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "a6740ee7a4de17ce05fa10c872d6a6f08b39b77c",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "da3f3a46b19ade5de11d964cba1f495c5c2c9615",
|
||||
"description": "ci: uprev vkd3d-proton to 2.11",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "cf510e38a51250702ec90bece7a9d397669ae28f",
|
||||
"description": "intel/ci: fix .hasvk-manual-rules",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "570acf56554a619ca2bf6ed697c876c6b12d7b31",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "19420731123e850e10c68eb3cd672b00561c48d7",
|
||||
"description": "intel/perf: fix regex escaping",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "aa04b47c6e43e6cc35611a43c1712ef750f161d9",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "1492d24f89f6e156d83d6f579d1d308eaae996ef",
|
||||
"description": "lp: make sure 0xff is unsigned before shifting it past signed int range",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "023fa0aa5d3ab9baa4a9061d9d7c74e20b723d1f",
|
||||
"description": "etnaviv: Mark etna_rs_gen_clear_surface(..) private",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "9342544ca5c9ec2d7c100fe80f3cb6ac41547231",
|
||||
"description": "etnaviv: rs: Call etna_rs_gen_clear_surface(..) when needed",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "945288ffaecac106c978d10cd4d8512fa2992c47",
|
||||
"description": "radeonsi: check sctx->tess_rings is valid before using it",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "c89ca3b47f11ce2c2e6953d37590021e89c1d119",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "b6e98677c38a479aa187bc48a1acd5bd8049d4a1",
|
||||
"description": "nir/print: print PATCH0 and VARn_16BIT names instead of numbers for TCS and TES",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "5c8730ebe880d05a36462904e401ed02afae7c4f",
|
||||
"description": "nir: don't declare illegal varyings in nir_create_passthrough_tcs",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "7a9b73fcb81126faa92397d82b627db64e1b8e0f",
|
||||
"description": "nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO",
|
||||
"nominated": true,
|
||||
"nomination_type": 1,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": "10be706778bd670197a66765c550cbb3a0cfda6d",
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "827bbe48298b7e32d46c1b9b777511109762f305",
|
||||
"description": "ci: use released version of meson",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "698344b93c49a9f3a257a0ef4546edf5cd3a9130",
|
||||
"description": "d3d12/driconf: Force on ARB_texture_view for Blender",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "9feecda201d632ec0300d98b9f89a10d309d3f03",
|
||||
"description": "docs: add another -rc",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "69d1e29dc318bb0f1c395c9a9ba1a94056d4dbef",
|
||||
"description": "docs: update calendar for 23.0.0-rc5",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "28ae3210e1697c0506ca2581ebfceac22992da8f",
|
||||
"description": "nvk: Wire up MESA_VK_VERSION_OVERRIDE",
|
||||
"nominated": false,
|
||||
"nomination_type": 3,
|
||||
"resolution": 4,
|
||||
"main_sha": null,
|
||||
"because_sha": null,
|
||||
"notes": null
|
||||
},
|
||||
{
|
||||
"sha": "b07a58157d0b110dbc09a42cffe7046c3200dd3b",
|
||||
"description": "radeonsi: remove the LAYER output if the framebuffer state has only 1 layer",
|
||||
|
@@ -3903,6 +3903,7 @@ ms_store_arrayed_output_intrin(nir_builder *b,
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nir_def *soffset = nir_load_ring_attr_offset_amd(b);
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nir_store_buffer_amd(b, store_val, ring, base_addr_off, soffset, arr_index,
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.base = const_off + param_offset * 16,
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||||
.write_mask = write_mask,
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||||
.memory_modes = nir_var_shader_out,
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||||
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
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||||
} else if (out_mode == ms_out_mode_var) {
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||||
|
@@ -410,10 +410,16 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
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{
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uint64_t slot_mask = 0;
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uint16_t slot_mask_16bit = 0;
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bool is_patch_special = false;
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if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
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nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
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is_patch_special = semantics.location == VARYING_SLOT_TESS_LEVEL_INNER ||
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semantics.location == VARYING_SLOT_TESS_LEVEL_OUTER ||
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semantics.location == VARYING_SLOT_BOUNDING_BOX0 ||
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semantics.location == VARYING_SLOT_BOUNDING_BOX1;
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||||
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if (semantics.location >= VARYING_SLOT_PATCH0 &&
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semantics.location <= VARYING_SLOT_PATCH31) {
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||||
/* Generic per-patch I/O. */
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||||
@@ -516,7 +522,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
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case nir_intrinsic_load_input_vertex:
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case nir_intrinsic_load_interpolated_input:
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||||
if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
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instr->intrinsic == nir_intrinsic_load_input) {
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instr->intrinsic == nir_intrinsic_load_input &&
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!is_patch_special) {
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shader->info.patch_inputs_read |= slot_mask;
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if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
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shader->info.patch_inputs_read_indirectly |= slot_mask;
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@@ -541,7 +548,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_load_per_primitive_output:
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if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
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instr->intrinsic == nir_intrinsic_load_output) {
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instr->intrinsic == nir_intrinsic_load_output &&
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!is_patch_special) {
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shader->info.patch_outputs_read |= slot_mask;
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if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
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shader->info.patch_outputs_accessed_indirectly |= slot_mask;
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@@ -575,7 +583,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
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case nir_intrinsic_store_per_vertex_output:
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case nir_intrinsic_store_per_primitive_output:
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if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
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instr->intrinsic == nir_intrinsic_store_output) {
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instr->intrinsic == nir_intrinsic_store_output &&
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!is_patch_special) {
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shader->info.patch_outputs_written |= slot_mask;
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if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
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shader->info.patch_outputs_accessed_indirectly |= slot_mask;
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||||
|
@@ -71,7 +71,7 @@ struct d3d12_bo {
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uint8_t local_reference_mask[16];
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d3d12_context_state_table_entry local_context_states[16];
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uint8_t local_reference_state[8][16];
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uint8_t local_reference_state[16][8];
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};
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||||
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||||
struct d3d12_buffer {
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||||
|
@@ -617,7 +617,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
|
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}
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||||
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||||
/* tess factors are loaded as input instead of system value */
|
||||
info->reads_tess_factors = nir->info.patch_inputs_read &
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||||
info->reads_tess_factors = nir->info.inputs_read &
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||||
(BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) |
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||||
BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER));
|
||||
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||||
|
@@ -4274,8 +4274,16 @@ static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertic
|
||||
if (sctx->patch_vertices != patch_vertices) {
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||||
sctx->patch_vertices = patch_vertices;
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||||
si_update_tess_in_out_patch_vertices(sctx);
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||||
if (sctx->shader.tcs.current)
|
||||
si_update_tess_io_layout_state(sctx);
|
||||
if (sctx->shader.tcs.current) {
|
||||
/* Update the io layout now if possible,
|
||||
* otherwise make sure it's done by si_update_shaders.
|
||||
*/
|
||||
if (sctx->tess_rings)
|
||||
si_update_tess_io_layout_state(sctx);
|
||||
else
|
||||
sctx->do_update_shaders = true;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
@@ -118,7 +118,7 @@
|
||||
- !reference [.vulkan-manual-rules, rules]
|
||||
- changes:
|
||||
- src/intel/**/*
|
||||
when: on_success
|
||||
when: manual
|
||||
|
||||
# ruleset to trigger on changes affecting either anv or iris, for jobs using both (piglit, skqp)
|
||||
.intel-rules:
|
||||
|
@@ -251,10 +251,10 @@ hw_vars["$QueryMode"] = "perf->sys_vars.query_mode"
|
||||
def resolve_variable(name, set, allow_counters):
|
||||
if name in hw_vars:
|
||||
return hw_vars[name]
|
||||
m = re.search('\$GtSlice([0-9]+)$', name)
|
||||
m = re.search(r'\$GtSlice([0-9]+)$', name)
|
||||
if m:
|
||||
return 'intel_device_info_slice_available(&perf->devinfo, {0})'.format(m.group(1))
|
||||
m = re.search('\$GtSlice([0-9]+)XeCore([0-9]+)$', name)
|
||||
m = re.search(r'\$GtSlice([0-9]+)XeCore([0-9]+)$', name)
|
||||
if m:
|
||||
return 'intel_device_info_subslice_available(&perf->devinfo, {0}, {1})'.format(m.group(1), m.group(2))
|
||||
if allow_counters and name in set.counter_vars:
|
||||
|
@@ -1405,9 +1405,7 @@ vn_QueueBindSparse(VkQueue queue,
|
||||
/* if feedback isn't used in the batch, can directly submit */
|
||||
if (!submit.has_feedback_fence && !submit.has_feedback_semaphore &&
|
||||
!submit.has_feedback_query) {
|
||||
result = vn_queue_bind_sparse_submit(&submit);
|
||||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
return vn_queue_bind_sparse_submit(&submit);
|
||||
}
|
||||
|
||||
for (uint32_t i = 0; i < submit.batch_count; i++) {
|
||||
|
Reference in New Issue
Block a user