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9 Commits

Author SHA1 Message Date
Eric Engestrom
1fbdd37d4c VERSION: bump for 23.3.0 2023-11-29 19:30:57 +00:00
Rhys Perry
421a8aaff1 ac/nir: fix partial mesh shader output writes on GFX11
Fixes dEQP-VK.mesh_shader.ext.smoke.monolithic.mesh_shader_triangle with
nir_opt_combine_stores disabled.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 240e16fc8e ("ac/nir/ngg: Use attribute ring for mesh shader params.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25530>
(cherry picked from commit 2d98236dd5)
2023-11-28 13:04:20 +00:00
Mary Guillemard
dced0dba02 venus: Do not submit batch manually when no feedback is required
This fixes hangs with Zink on piglit spec@arb_sparse_buffer tests caused by the double submission.

Fixes: a55d26b566 ("venus: add back sparse binding support")

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26375>
(cherry picked from commit f59665bb62)
2023-11-28 13:04:19 +00:00
Jesse Natalie
3ff4768692 d3d12: Fix multidimensional array ordering
Apparently my C multimensional array syntax was rusty.

Fixes: a6740ee7 ("d3d12: Fix indexing of local_reference_state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26362>
(cherry picked from commit 1924cdc289)
2023-11-28 13:04:17 +00:00
Eric Engestrom
54f93b1788 intel/ci: fix .hasvk-manual-rules
Fixes: 570acf5655 ("ci: Add a manual full and 1/10th hasvk CTS runs.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26259>
(cherry picked from commit cf510e38a5)
2023-11-28 13:03:57 +00:00
Eric Engestrom
2525258917 intel/perf: fix regex escaping
`\$` is interpreted before being passed to `re.search()`, but luckily
for us the escape is also invalid and because of that, python 3.12+
warns us about it.

Use a raw string instead, so that the `\` is passed untouched to
`re.search()`.

Fixes: aa04b47c6e ("intel/perf: add support for GtSlice/GtSliceXDualsubsliceY variables")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26355>
(cherry picked from commit 1942073112)
2023-11-28 13:03:56 +00:00
Marek Olšák
94ad18d1e7 nir: fix gathering TESS_LEVEL_INNER/OUTER usage with lowered IO
Those varyings shouldn't flag patch_inputs_read/patch_outputs_written.

Fixes: 10be706778 - nir: gather indirect info from lowered IO intrinsics

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26275>
(cherry picked from commit 7a9b73fcb8)
2023-11-28 13:03:52 +00:00
Pierre-Eric Pelloux-Prayer
3ed7b95a55 radeonsi: check sctx->tess_rings is valid before using it
Fixes: c89ca3b47f ("radeonsi: change si_emit_derived_tess_state into a state atom")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10015

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26190>
(cherry picked from commit 945288ffae)
2023-11-28 13:03:48 +00:00
Eric Engestrom
dd56f591e5 .pick_status.json: Update to f843b14c17 2023-11-28 11:22:43 +00:00
10 changed files with 270 additions and 14 deletions

View File

@@ -1,4 +1,244 @@
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View File

@@ -1 +1 @@
23.3.0-rc5
23.3.0

View File

@@ -3903,6 +3903,7 @@ ms_store_arrayed_output_intrin(nir_builder *b,
nir_def *soffset = nir_load_ring_attr_offset_amd(b);
nir_store_buffer_amd(b, store_val, ring, base_addr_off, soffset, arr_index,
.base = const_off + param_offset * 16,
.write_mask = write_mask,
.memory_modes = nir_var_shader_out,
.access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD);
} else if (out_mode == ms_out_mode_var) {

View File

@@ -410,10 +410,16 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
{
uint64_t slot_mask = 0;
uint16_t slot_mask_16bit = 0;
bool is_patch_special = false;
if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
is_patch_special = semantics.location == VARYING_SLOT_TESS_LEVEL_INNER ||
semantics.location == VARYING_SLOT_TESS_LEVEL_OUTER ||
semantics.location == VARYING_SLOT_BOUNDING_BOX0 ||
semantics.location == VARYING_SLOT_BOUNDING_BOX1;
if (semantics.location >= VARYING_SLOT_PATCH0 &&
semantics.location <= VARYING_SLOT_PATCH31) {
/* Generic per-patch I/O. */
@@ -516,7 +522,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_load_input_vertex:
case nir_intrinsic_load_interpolated_input:
if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
instr->intrinsic == nir_intrinsic_load_input) {
instr->intrinsic == nir_intrinsic_load_input &&
!is_patch_special) {
shader->info.patch_inputs_read |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_inputs_read_indirectly |= slot_mask;
@@ -541,7 +548,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_load_per_vertex_output:
case nir_intrinsic_load_per_primitive_output:
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_load_output) {
instr->intrinsic == nir_intrinsic_load_output &&
!is_patch_special) {
shader->info.patch_outputs_read |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask;
@@ -575,7 +583,8 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_store_per_vertex_output:
case nir_intrinsic_store_per_primitive_output:
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_store_output) {
instr->intrinsic == nir_intrinsic_store_output &&
!is_patch_special) {
shader->info.patch_outputs_written |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask;

View File

@@ -71,7 +71,7 @@ struct d3d12_bo {
uint8_t local_reference_mask[16];
d3d12_context_state_table_entry local_context_states[16];
uint8_t local_reference_state[8][16];
uint8_t local_reference_state[16][8];
};
struct d3d12_buffer {

View File

@@ -617,7 +617,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
}
/* tess factors are loaded as input instead of system value */
info->reads_tess_factors = nir->info.patch_inputs_read &
info->reads_tess_factors = nir->info.inputs_read &
(BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_INNER) |
BITFIELD64_BIT(VARYING_SLOT_TESS_LEVEL_OUTER));

View File

@@ -4274,8 +4274,16 @@ static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertic
if (sctx->patch_vertices != patch_vertices) {
sctx->patch_vertices = patch_vertices;
si_update_tess_in_out_patch_vertices(sctx);
if (sctx->shader.tcs.current)
si_update_tess_io_layout_state(sctx);
if (sctx->shader.tcs.current) {
/* Update the io layout now if possible,
* otherwise make sure it's done by si_update_shaders.
*/
if (sctx->tess_rings)
si_update_tess_io_layout_state(sctx);
else
sctx->do_update_shaders = true;
}
}
}

View File

@@ -118,7 +118,7 @@
- !reference [.vulkan-manual-rules, rules]
- changes:
- src/intel/**/*
when: on_success
when: manual
# ruleset to trigger on changes affecting either anv or iris, for jobs using both (piglit, skqp)
.intel-rules:

View File

@@ -251,10 +251,10 @@ hw_vars["$QueryMode"] = "perf->sys_vars.query_mode"
def resolve_variable(name, set, allow_counters):
if name in hw_vars:
return hw_vars[name]
m = re.search('\$GtSlice([0-9]+)$', name)
m = re.search(r'\$GtSlice([0-9]+)$', name)
if m:
return 'intel_device_info_slice_available(&perf->devinfo, {0})'.format(m.group(1))
m = re.search('\$GtSlice([0-9]+)XeCore([0-9]+)$', name)
m = re.search(r'\$GtSlice([0-9]+)XeCore([0-9]+)$', name)
if m:
return 'intel_device_info_subslice_available(&perf->devinfo, {0}, {1})'.format(m.group(1), m.group(2))
if allow_counters and name in set.counter_vars:

View File

@@ -1405,9 +1405,7 @@ vn_QueueBindSparse(VkQueue queue,
/* if feedback isn't used in the batch, can directly submit */
if (!submit.has_feedback_fence && !submit.has_feedback_semaphore &&
!submit.has_feedback_query) {
result = vn_queue_bind_sparse_submit(&submit);
if (result != VK_SUCCESS)
return result;
return vn_queue_bind_sparse_submit(&submit);
}
for (uint32_t i = 0; i < submit.batch_count; i++) {