VERSION: bump for 24.2.0-rc3

Cc: mesa-stable

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30399>
(cherry picked from commit 6da7bd842c)

.gitlab-ci/bare-metal/poe_run.py

@@ -64,7 +64,7 @@ class PoERun:
         if not boot_detected:
             self.print_error(
                 "Something wrong; couldn't detect the boot start up sequence")
-            return 1
+            return 2
 
         self.logger.create_job_phase("test")
         for line in self.ser.lines(timeout=self.test_timeout, phase="test"):

.gitlab-ci/build/gitlab-ci.yml

@@ -433,7 +433,7 @@ debian-android:
     - debian/arm64_build
   variables:
     VULKAN_DRIVERS: freedreno,broadcom
-    GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,softpipe,tegra,v3d,vc4,zink"
+    GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,llvmpipe,softpipe,tegra,v3d,vc4,zink"
     BUILDTYPE: "debugoptimized"
   tags:
     - aarch64
@@ -446,6 +446,8 @@ debian-arm32:
     CROSS: armhf
     DRI_LOADERS:
       -D glvnd=disabled
+    # remove llvmpipe from the .meson-arm list because here we have llvm=disabled
+    GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,softpipe,tegra,v3d,vc4,zink"
     EXTRA_OPTION: >
       -D llvm=disabled
       -D valgrind=disabled
@@ -480,7 +482,6 @@ debian-arm64:
     C_ARGS: >
       -Wno-error=array-bounds
       -Wno-error=stringop-truncation
-    GALLIUM_DRIVERS: "etnaviv,freedreno,kmsro,lima,nouveau,panfrost,llvmpipe,softpipe,tegra,v3d,vc4,zink"
     VULKAN_DRIVERS: "freedreno,broadcom,panfrost,imagination-experimental"
     DRI_LOADERS:
       -D glvnd=disabled

VERSION

@@ -1 +1 @@
-24.2.0-rc2
+24.2.0-rc3

include/pci_ids/iris_pci_ids.h

@@ -257,9 +257,9 @@ CHIPSET(0x56c0, atsm_g10, "ATS-M", "Intel(R) Data Center GPU Flex 170")
 CHIPSET(0x56c1, atsm_g11, "ATS-M", "Intel(R) Data Center GPU Flex 140")
 CHIPSET(0x56c2, atsm_g10, "ATS-M", "Intel(R) Data Center GPU Flex 170V")
 
-CHIPSET(0x6420, lnl, "LNL", "Intel(R) Graphics")
-CHIPSET(0x64a0, lnl, "LNL", "Intel(R) Graphics")
-CHIPSET(0x64b0, lnl, "LNL", "Intel(R) Graphics")
+CHIPSET(0x6420, lnl, "LNL", "Intel(R) Graphics", FORCE_PROBE)
+CHIPSET(0x64a0, lnl, "LNL", "Intel(R) Graphics", FORCE_PROBE)
+CHIPSET(0x64b0, lnl, "LNL", "Intel(R) Graphics", FORCE_PROBE)
 
 CHIPSET(0x7d40, mtl_u, "MTL", "Intel(R) Graphics")
 CHIPSET(0x7d45, mtl_u, "MTL", "Intel(R) Graphics")

meson.build

@@ -126,31 +126,31 @@ if gallium_drivers.contains('auto')
     # TODO: Sparc
     if ['x86', 'x86_64'].contains(host_machine.cpu_family())
       gallium_drivers = [
-        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'swrast',
+        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'llvmpipe', 'softpipe',
         'iris', 'crocus', 'i915', 'zink'
       ]
     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
       gallium_drivers = [
         'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau', 'svga',
-        'tegra', 'virgl', 'lima', 'panfrost', 'swrast', 'iris',
+        'tegra', 'virgl', 'lima', 'panfrost', 'llvmpipe', 'softpipe', 'iris',
         'zink'
       ]
     elif ['mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family())
       gallium_drivers = [
-        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast', 'zink'
+        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'llvmpipe', 'softpipe', 'zink'
       ]
     elif ['loongarch64'].contains(host_machine.cpu_family())
       gallium_drivers = [
-        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'etnaviv', 'swrast', 'zink'
+        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'etnaviv', 'llvmpipe', 'softpipe', 'zink'
       ]
     else
       error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
             host_machine.cpu_family()))
     endif
   elif ['windows'].contains(host_machine.system())
-    gallium_drivers = ['swrast', 'zink', 'd3d12']
+    gallium_drivers = ['llvmpipe', 'softpipe', 'zink', 'd3d12']
   elif ['darwin', 'cygwin', 'haiku'].contains(host_machine.system())
-    gallium_drivers = ['swrast']
+    gallium_drivers = ['llvmpipe', 'softpipe']
   else
     error('Unknown OS @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format(
           host_machine.system()))
@@ -160,7 +160,7 @@ elif gallium_drivers.contains('all')
    # is not available on non-Intel distros.
    gallium_drivers = [
      'r300', 'r600', 'radeonsi', 'crocus', 'v3d', 'vc4', 'freedreno', 'etnaviv',
-     'nouveau', 'svga', 'tegra', 'virgl', 'lima', 'panfrost', 'swrast', 'iris',
+     'nouveau', 'svga', 'tegra', 'virgl', 'lima', 'panfrost', 'llvmpipe', 'softpipe', 'iris',
      'zink', 'd3d12', 'asahi'
    ]
 endif
@@ -1835,9 +1835,9 @@ if with_llvm
 elif with_amd_vk and with_aco_tests
   error('ACO tests require LLVM, but LLVM is disabled.')
 elif with_swrast_vk
-  error('The following drivers require LLVM: Lavapipe. One of these is enabled, but LLVM is disabled.')
+  error('lavapipe requires LLVM and is enabled, but LLVM is disabled.')
 elif with_gallium_llvmpipe
-  error('The following drivers require LLVM: llvmpipe. It is enabled, but LLVM is disabled.')
+  error('llvmpipe requires LLVM and is enabled, but LLVM is disabled.')
 elif with_gallium_clover
   error('The OpenCL "Clover" state tracker requires LLVM, but LLVM is disabled.')
 elif with_clc
@@ -2291,12 +2291,6 @@ endif
 # as GCC LTO drops them. See: https://bugs.freedesktop.org/show_bug.cgi?id=109391
 gcc_lto_quirk = (cc.get_id() == 'gcc') ? ['-fno-lto'] : []
 
-# As of GCC 13.2.1, Venus build with optimization level plain/0 and LTO does not
-# compile properly: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11006
-if with_virtio_vk and cc.get_id() == 'gcc' and (get_option('optimization') == '0' or get_option('optimization') == 'plain') and get_option('b_lto') == true
-  error('Venus does not compile properly with GCC + optimization level plain/0 + LTO.')
-endif
-
 devenv = environment()
 
 dir_compiler_nir = join_paths(meson.current_source_dir(), 'src/compiler/nir/')

src/amd/compiler/aco_optimizer.cpp

@@ -4288,6 +4288,7 @@ to_uniform_bool_instr(opt_ctx& ctx, aco_ptr<Instruction>& instr)
    }
 
    instr->definitions[0].setTemp(Temp(instr->definitions[0].tempId(), s1));
+   ctx.program->temp_rc[instr->definitions[0].tempId()] = s1;
    assert(instr->operands[0].regClass() == s1);
    assert(instr->operands[1].regClass() == s1);
    return true;

src/compiler/clc/clc_helpers.cpp

@@ -1228,10 +1228,17 @@ clc_link_spirv_binaries(const struct clc_linker_args *args,
    context.SetMessageConsumer(msgconsumer);
    spvtools::LinkerOptions options;
    options.SetAllowPartialLinkage(args->create_library);
+   #if defined(HAS_SPIRV_LINK_LLVM_WORKAROUND) && LLVM_VERSION_MAJOR >= 17
+      options.SetAllowPtrTypeMismatch(true);
+   #endif
    options.SetCreateLibrary(args->create_library);
    std::vector<uint32_t> linkingResult;
    spv_result_t status = spvtools::Link(context, binaries, &linkingResult, options);
    if (status != SPV_SUCCESS) {
+      #if !defined(HAS_SPIRV_LINK_LLVM_WORKAROUND) && LLVM_VERSION_MAJOR >= 17
+        clc_warning(logger, "SPIRV-Tools doesn't contain https://github.com/KhronosGroup/SPIRV-Tools/pull/5534\n");
+        clc_warning(logger, "Please update in order to prevent spurious linking failures\n");
+      #endif
       return -1;
    }
 

src/compiler/clc/meson.build

@@ -82,6 +82,19 @@ else
   endif
 endif
 
+has_spirv_link_workaround = cpp.has_member(
+  'spvtools::LinkerOptions',
+  'SetAllowPtrTypeMismatch(true)',
+  prefix : [
+    '#include <spirv-tools/linker.hpp>',
+  ],
+  dependencies : dep_spirv_tools,
+)
+
+if has_spirv_link_workaround
+  _libmesaclc_c_args += ['-DHAS_SPIRV_LINK_LLVM_WORKAROUND=1']
+endif
+
 _libmesaclc = static_library(
   'libmesaclc',
   files_libmesaclc,

src/compiler/spirv/vtn_cfg.c

@@ -123,7 +123,12 @@ function_parameter_decoration_cb(struct vtn_builder *b, struct vtn_value *val,
       break;
 
    /* ignore for now */
+   case SpvDecorationAliased:
+   case SpvDecorationAliasedPointer:
    case SpvDecorationAlignment:
+   case SpvDecorationRelaxedPrecision:
+   case SpvDecorationRestrict:
+   case SpvDecorationRestrictPointer:
       break;
 
    default:

src/egl/drivers/haiku/egl_haiku.cpp

@@ -49,6 +49,8 @@
 #include "hgl/hgl_sw_winsys.h"
 #include "hgl_context.h"
 
+#include <Bitmap.h>
+
 extern "C" {
 #include "target-helpers/inline_sw_helper.h"
 }
@@ -115,6 +117,9 @@ haiku_create_window_surface(_EGLDisplay *disp, _EGLConfig *conf,
       return NULL;
    }
 
+   // Unset and delete previously set bitmap if any.
+   delete ((BitmapHook *)native_window)->SetBitmap(NULL);
+
    return &wgl_surf->base;
 }
 
@@ -168,6 +173,13 @@ haiku_destroy_surface(_EGLDisplay *disp, _EGLSurface *surf)
       struct haiku_egl_surface *hgl_surf = haiku_egl_surface(surf);
       struct pipe_screen *screen = hgl_dpy->disp->fscreen->screen;
       screen->fence_reference(screen, &hgl_surf->throttle_fence, NULL);
+
+      // Unset bitmap to release ownership. Bitmap will be deleted later
+      // when destroying framebuffer.
+      BitmapHook *bitmapHook = (BitmapHook*)hgl_surf->fb->winsysContext;
+      if (bitmapHook != NULL)
+         bitmapHook->SetBitmap(NULL);
+
       hgl_destroy_st_framebuffer(hgl_surf->fb);
       free(surf);
    }
@@ -229,6 +241,8 @@ haiku_swap_buffers(_EGLDisplay *disp, _EGLSurface *surf)
 
    update_size(buffer);
 
+   st_context_invalidate_state(st, ST_INVALIDATE_FB_STATE);
+
    return EGL_TRUE;
 }
 

src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c

@@ -3468,7 +3468,7 @@ lp_build_sample_soa_code(struct gallivm_state *gallivm,
 
    const enum pipe_texture_target target = static_texture_state->target;
    const unsigned dims = texture_dims(target);
-   const unsigned num_quads = type.length / 4;
+   const unsigned num_quads = type.length == 1 ? 1 : type.length / 4;
    struct lp_build_sample_context bld;
    struct lp_static_sampler_state derived_sampler_state = *static_sampler_state;
    LLVMTypeRef i32t = LLVMInt32TypeInContext(gallivm->context);

src/gallium/auxiliary/meson.build

@@ -431,7 +431,6 @@ files_libgalliumvl = files(
 )
 
 vlwinsys_deps = []
-vlwinsys_links = []
 files_libgalliumvlwinsys = files('vl/vl_winsys.h')
 if host_machine.system() == 'windows'
   files_libgalliumvlwinsys += files('vl/vl_winsys_win32.c')
@@ -445,7 +444,6 @@ if with_dri2 and with_platform_x11
       dep_xcb_sync, dep_xcb_present, dep_xshmfence, dep_xcb_xfixes,
       dep_xcb_dri3,
     ]
-    vlwinsys_links += libloader_dri3_helper
     files_libgalliumvlwinsys += files('vl/vl_winsys_dri3.c')
   endif
 endif
@@ -577,6 +575,5 @@ libgalliumvlwinsys = static_library(
   files_libgalliumvlwinsys,
   include_directories : [inc_gallium, inc_include, inc_loader, inc_src],
   dependencies : [dep_libdrm, vlwinsys_deps, idep_mesautil],
-  link_with : vlwinsys_links,
   build_by_default : false,
 )

src/gallium/auxiliary/vl/vl_winsys_dri3.c

@@ -34,7 +34,6 @@
 #include <xcb/xfixes.h>
 
 #include "loader.h"
-#include "loader_dri3_helper.h"
 
 #include "pipe/p_screen.h"
 #include "pipe/p_state.h"
@@ -762,10 +761,15 @@ struct vl_screen *
 vl_dri3_screen_create(Display *display, int screen)
 {
    struct vl_dri3_screen *scrn;
+   const xcb_query_extension_reply_t *extension;
+   xcb_dri3_open_cookie_t open_cookie;
+   xcb_dri3_open_reply_t *open_reply;
    xcb_get_geometry_cookie_t geom_cookie;
    xcb_get_geometry_reply_t *geom_reply;
+   xcb_xfixes_query_version_cookie_t xfixes_cookie;
+   xcb_xfixes_query_version_reply_t *xfixes_reply;
+   xcb_generic_error_t *error;
    int fd;
-   bool err = false;
 
    assert(display);
 
@@ -777,10 +781,45 @@ vl_dri3_screen_create(Display *display, int screen)
    if (!scrn->conn)
       goto free_screen;
 
-   fd = loader_dri3_open(scrn->conn, RootWindow(display, screen), 0);
-   if (fd < 0 || !loader_dri3_check_multibuffer(scrn->conn, &err) || err) {
+   xcb_prefetch_extension_data(scrn->conn , &xcb_dri3_id);
+   xcb_prefetch_extension_data(scrn->conn, &xcb_present_id);
+   xcb_prefetch_extension_data (scrn->conn, &xcb_xfixes_id);
+   extension = xcb_get_extension_data(scrn->conn, &xcb_dri3_id);
+   if (!(extension && extension->present))
+      goto free_screen;
+   extension = xcb_get_extension_data(scrn->conn, &xcb_present_id);
+   if (!(extension && extension->present))
+      goto free_screen;
+   extension = xcb_get_extension_data(scrn->conn, &xcb_xfixes_id);
+   if (!(extension && extension->present))
+      goto free_screen;
+
+   xfixes_cookie = xcb_xfixes_query_version(scrn->conn, XCB_XFIXES_MAJOR_VERSION,
+                                            XCB_XFIXES_MINOR_VERSION);
+   xfixes_reply = xcb_xfixes_query_version_reply(scrn->conn, xfixes_cookie, &error);
+   if (!xfixes_reply || error || xfixes_reply->major_version < 2) {
+      free(error);
+      free(xfixes_reply);
       goto free_screen;
    }
+   free(xfixes_reply);
+
+   open_cookie = xcb_dri3_open(scrn->conn, RootWindow(display, screen), None);
+   open_reply = xcb_dri3_open_reply(scrn->conn, open_cookie, NULL);
+   if (!open_reply)
+      goto free_screen;
+   if (open_reply->nfd != 1) {
+      free(open_reply);
+      goto free_screen;
+   }
+
+   fd = xcb_dri3_open_reply_fds(scrn->conn, open_reply)[0];
+   if (fd < 0) {
+      free(open_reply);
+      goto free_screen;
+   }
+   fcntl(fd, F_SETFD, FD_CLOEXEC);
+   free(open_reply);
 
    scrn->is_different_gpu = loader_get_user_preferred_fd(&fd, NULL);
 

src/gallium/drivers/i915/i915_context.h

@@ -174,6 +174,7 @@ struct i915_state {
    unsigned dst_buf_vars;
    uint32_t draw_offset;
    uint32_t draw_size;
+   unsigned cbuf_offset;
 
    /* Reswizzle for OC writes in PIXEL_SHADER_PROGRAM, or 0 if unnecessary. */
    uint32_t fixup_swizzle;

src/gallium/drivers/i915/i915_resource_texture.c

@@ -359,15 +359,16 @@ i915_texture_layout_2d(struct i915_texture *tex)
 {
    struct pipe_resource *pt = &tex->b;
    unsigned level;
-   unsigned width = util_next_power_of_two(pt->width0);
-   unsigned height = util_next_power_of_two(pt->height0);
-   unsigned nblocksy = util_format_get_nblocksy(pt->format, width);
+   unsigned width = pt->width0;
+   unsigned height = pt->height0;
+   unsigned nblocksy = 0;
    unsigned align_y = 2;
 
    if (util_format_is_compressed(pt->format))
       align_y = 1;
 
    tex->stride = align(util_format_get_stride(pt->format, width), 4);
+   nblocksy = align_nblocksy(pt->format, height, align_y);
    tex->total_nblocksy = 0;
 
    for (level = 0; level <= pt->last_level; level++) {
@@ -463,10 +464,10 @@ i945_texture_layout_2d(struct i915_texture *tex)
    unsigned level;
    unsigned x = 0;
    unsigned y = 0;
-   unsigned width = util_next_power_of_two(pt->width0);
-   unsigned height = util_next_power_of_two(pt->height0);
-   unsigned nblocksx = util_format_get_nblocksx(pt->format, width);
-   unsigned nblocksy = util_format_get_nblocksy(pt->format, height);
+   unsigned width = pt->width0;
+   unsigned height = pt->height0;
+   unsigned nblocksx = 0;
+   unsigned nblocksy = 0;
 
    if (util_format_is_compressed(pt->format)) {
       align_x = 1;
@@ -474,20 +475,8 @@ i945_texture_layout_2d(struct i915_texture *tex)
    }
 
    tex->stride = align(util_format_get_stride(pt->format, width), 4);
-
-   /* May need to adjust pitch to accommodate the placement of
-    * the 2nd mipmap level.  This occurs when the alignment
-    * constraints of mipmap placement push the right edge of the
-    * 2nd mipmap level out past the width of its parent.
-    */
-   if (pt->last_level > 0) {
-      unsigned mip1_nblocksx =
-         align_nblocksx(pt->format, u_minify(width, 1), align_x) +
-         util_format_get_nblocksx(pt->format, u_minify(width, 2));
-
-      if (mip1_nblocksx > nblocksx)
-         tex->stride = mip1_nblocksx * util_format_get_blocksize(pt->format);
-   }
+   nblocksx = align_nblocksx(pt->format, width, align_x);
+   nblocksy = align_nblocksy(pt->format, height, align_y);
 
    /* Pitch must be a whole number of dwords
     */

src/gallium/drivers/i915/i915_state_emit.c

@@ -214,7 +214,7 @@ emit_static(struct i915_context *i915)
    if (i915->current.cbuf_bo && (i915->static_dirty & I915_DST_BUF_COLOR)) {
       OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
       OUT_BATCH(i915->current.cbuf_flags);
-      OUT_RELOC(i915->current.cbuf_bo, I915_USAGE_RENDER, 0);
+      OUT_RELOC(i915->current.cbuf_bo, I915_USAGE_RENDER, i915->current.cbuf_offset);
    }
 
    /* What happens if no zbuf??

src/gallium/drivers/i915/i915_state_sampler.c

@@ -289,20 +289,8 @@ update_map(struct i915_context *i915, uint32_t unit,
    int first_level = view->u.tex.first_level;
    const uint32_t num_levels = pt->last_level - first_level;
    unsigned max_lod = num_levels * 4;
-   bool is_npot = (!util_is_power_of_two_or_zero(pt->width0) ||
-                   !util_is_power_of_two_or_zero(pt->height0));
    uint32_t format, pitch;
 
-   /*
-    * This is a bit messy. i915 doesn't support NPOT with mipmaps, but we can
-    * still texture from a single level. This is useful to make u_blitter work.
-    */
-   if (is_npot) {
-      width = u_minify(width, first_level);
-      height = u_minify(height, first_level);
-      max_lod = 1;
-   }
-
    assert(tex);
    assert(width);
    assert(height);
@@ -323,6 +311,8 @@ update_map(struct i915_context *i915, uint32_t unit,
     * XXX When min_filter != mag_filter and there's just one mipmap level,
     * set max_lod = 1 to make sure i915 chooses between min/mag filtering.
     */
+   if (max_lod == 0)
+      max_lod = 1;
 
    /* See note at the top of file */
    if (max_lod > (sampler->maxlod >> 2))
@@ -333,10 +323,7 @@ update_map(struct i915_context *i915, uint32_t unit,
                ((max_lod) << MS4_MAX_LOD_SHIFT) |
                ((depth - 1) << MS4_VOLUME_DEPTH_SHIFT));
 
-   if (is_npot)
-      state[2] = i915_texture_offset(tex, first_level, 0);
-   else
-      state[2] = 0;
+   state[2] = 0;
 }
 
 static void

src/gallium/drivers/i915/i915_state_static.c

@@ -81,6 +81,7 @@ update_framebuffer(struct i915_context *i915)
    struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
    struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
    unsigned x, y;
+   unsigned y1;
    int layer;
    uint32_t draw_offset, draw_size;
 
@@ -91,11 +92,19 @@ update_framebuffer(struct i915_context *i915)
 
       i915->current.cbuf_bo = tex->buffer;
       i915->current.cbuf_flags = surf->buf_info;
+      i915->current.cbuf_offset = 0;
 
       layer = cbuf_surface->u.tex.first_layer;
 
       x = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksx;
       y = tex->image_offset[cbuf_surface->u.tex.level][layer].nblocksy;
+      // Use offset if buffer not within max texture size 2048
+      if (y + i915->framebuffer.height >= (1 << (I915_MAX_TEXTURE_2D_LEVELS - 1))) {
+         // offset should be multiple of 8 to support TILE_X 
+         y1 = (y / 8) * 8;
+         y -= y1;
+         i915->current.cbuf_offset = y1 * tex->stride;
+      }
    } else {
       i915->current.cbuf_bo = NULL;
       x = y = 0;

src/gallium/drivers/iris/iris_state.c

@@ -3135,11 +3135,11 @@ iris_create_surface(struct pipe_context *ctx,
        * have a renderable view format.  We must be attempting to upload
        * blocks of compressed data via an uncompressed view.
        *
-       * In this case, we can assume there are no auxiliary buffers, a single
+       * In this case, we can assume there are no auxiliary surfaces, a single
        * miplevel, and that the resource is single-sampled.  Gallium may try
        * and create an uncompressed view with multiple layers, however.
        */
-      assert(res->aux.usage == ISL_AUX_USAGE_NONE);
+      assert(res->aux.surf.size_B == 0);
       assert(res->surf.samples == 1);
       assert(view->levels == 1);
 

src/gallium/drivers/llvmpipe/lp_screen.c

@@ -930,10 +930,12 @@ llvmpipe_destroy_screen(struct pipe_screen *_screen)
    close(screen->udmabuf_fd);
 #endif
 
+#if DETECT_OS_LINUX
    util_vma_heap_finish(&screen->mem_heap);
 
    close(screen->fd_mem_alloc);
    mtx_destroy(&screen->mem_mutex);
+#endif
    mtx_destroy(&screen->rast_mutex);
    mtx_destroy(&screen->cs_mutex);
    FREE(screen);
@@ -1175,15 +1177,17 @@ llvmpipe_create_screen(struct sw_winsys *winsys)
    screen->udmabuf_fd = open("/dev/udmabuf", O_RDWR);
 #endif
 
-   screen->fd_mem_alloc = os_create_anonymous_file(0, "allocation fd");
-   (void) mtx_init(&screen->mem_mutex, mtx_plain);
-
    uint64_t alignment;
    if (!os_get_page_size(&alignment))
       alignment = 256;
 
+#if DETECT_OS_LINUX
+   (void) mtx_init(&screen->mem_mutex, mtx_plain);
+
    util_vma_heap_init(&screen->mem_heap, alignment, UINT64_MAX - alignment);
    screen->mem_heap.alloc_high = false;
+   screen->fd_mem_alloc = os_create_anonymous_file(0, "allocation fd");
+#endif
 
    snprintf(screen->renderer_string, sizeof(screen->renderer_string),
             "llvmpipe (LLVM " MESA_LLVM_VERSION_STRING ", %u bits)",

src/gallium/drivers/llvmpipe/lp_screen.h

@@ -79,10 +79,12 @@ struct llvmpipe_screen
    int udmabuf_fd;
 #endif
 
+#if DETECT_OS_LINUX
    int fd_mem_alloc;
    mtx_t mem_mutex;
    uint64_t mem_file_size;
    struct util_vma_heap mem_heap;
+#endif
 };
 
 

src/gallium/drivers/llvmpipe/lp_texture.c

@@ -1290,21 +1290,27 @@ llvmpipe_memory_barrier(struct pipe_context *pipe,
 static struct pipe_memory_allocation *
 llvmpipe_allocate_memory(struct pipe_screen *_screen, uint64_t size)
 {
-   struct llvmpipe_screen *screen = llvmpipe_screen(_screen);
    struct llvmpipe_memory_allocation *mem = CALLOC_STRUCT(llvmpipe_memory_allocation);
    uint64_t alignment;
    if (!os_get_page_size(&alignment))
       alignment = 256;
 
-   mem->fd = screen->fd_mem_alloc;
    mem->size = align64(size, alignment);
 
 #if DETECT_OS_LINUX
+   struct llvmpipe_screen *screen = llvmpipe_screen(_screen);
+
    mem->cpu_addr = MAP_FAILED;
+   mem->fd = screen->fd_mem_alloc;
 
    mtx_lock(&screen->mem_mutex);
 
    mem->offset = util_vma_heap_alloc(&screen->mem_heap, mem->size, alignment);
+   if (!mem->offset) {
+      mtx_unlock(&screen->mem_mutex);
+      FREE(mem);
+      return NULL;
+   }
 
    if (mem->offset + mem->size > screen->mem_file_size) {
       /* expand the anonymous file */
@@ -1325,16 +1331,17 @@ static void
 llvmpipe_free_memory(struct pipe_screen *pscreen,
                      struct pipe_memory_allocation *pmem)
 {
-   struct llvmpipe_screen *screen = llvmpipe_screen(pscreen);
    struct llvmpipe_memory_allocation *mem = (struct llvmpipe_memory_allocation *)pmem;
 
+#if DETECT_OS_LINUX
+   struct llvmpipe_screen *screen = llvmpipe_screen(pscreen);
+
    if (mem->fd) {
       mtx_lock(&screen->mem_mutex);
       util_vma_heap_free(&screen->mem_heap, mem->offset, mem->size);
       mtx_unlock(&screen->mem_mutex);
    }
 
-#if DETECT_OS_LINUX
    if (mem->cpu_addr != MAP_FAILED)
       munmap(mem->cpu_addr, mem->size);
 #else

src/gallium/frontends/dri/dri2.c

@@ -1170,15 +1170,29 @@ dri2_create_image(__DRIscreen *_screen,
    if (count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID) {
       count = 0;
       modifiers = NULL;
-   } else if (count == 1 && modifiers[0] == DRM_FORMAT_MOD_LINEAR &&
-              !pscreen->resource_create_with_modifiers) {
-      count = 0;
-      modifiers = NULL;
-      use |= __DRI_IMAGE_USE_LINEAR;
    }
-   else if ((count > 1 || modifiers) &&
-            !pscreen->resource_create_with_modifiers) {
-      return NULL;
+
+   if (!pscreen->resource_create_with_modifiers && count > 0) {
+      bool invalid_ok = false;
+      bool linear_ok = false;
+
+      for (unsigned i = 0; i < _count; i++) {
+         if (modifiers[i] == DRM_FORMAT_MOD_LINEAR)
+            linear_ok = true;
+         else if (modifiers[i] == DRM_FORMAT_MOD_INVALID)
+            invalid_ok = true;
+      }
+
+      if (invalid_ok) {
+         count = 0;
+         modifiers = NULL;
+      } else if (linear_ok) {
+         count = 0;
+         modifiers = NULL;
+         use |= __DRI_IMAGE_USE_LINEAR;
+      } else {
+         return NULL;
+      }
    }
 
    if (pscreen->is_format_supported(pscreen, map->pipe_format, screen->target,

src/gallium/frontends/rusticl/api/program.rs

@@ -183,14 +183,16 @@ fn create_program_with_binary(
 ) -> CLResult<cl_program> {
     let c = Context::arc_from_raw(context)?;
     let devs = Device::refs_from_arr(device_list, num_devices)?;
-    let mut binary_status =
-        unsafe { cl_slice::from_raw_parts_mut(binary_status, num_devices as usize) }.ok();
 
     // CL_INVALID_VALUE if device_list is NULL or num_devices is zero.
     if devs.is_empty() {
         return Err(CL_INVALID_VALUE);
     }
 
+    // needs to happen after `devs.is_empty` check to protect against num_devices being 0
+    let mut binary_status =
+        unsafe { cl_slice::from_raw_parts_mut(binary_status, num_devices as usize) }.ok();
+
     // CL_INVALID_VALUE if lengths or binaries is NULL
     if lengths.is_null() || binaries.is_null() {
         return Err(CL_INVALID_VALUE);

src/gallium/frontends/rusticl/api/util.rs

@@ -26,7 +26,7 @@ pub trait CLInfo<I> {
         param_value: *mut ::std::os::raw::c_void,
         param_value_size_ret: *mut usize,
     ) -> CLResult<()> {
-        let arr = if !param_value.is_null() {
+        let arr = if !param_value.is_null() && param_value_size != 0 {
             unsafe { slice::from_raw_parts(param_value.cast(), param_value_size) }
         } else {
             &[]
@@ -224,9 +224,9 @@ where
     }
 }
 
-pub fn cl_prop<T: CLProp>(v: T) -> Vec<MaybeUninit<u8>>
+pub fn cl_prop<T>(v: T) -> Vec<MaybeUninit<u8>>
 where
-    T: Sized,
+    T: CLProp + Sized,
 {
     v.cl_vec()
 }

src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs

@@ -224,8 +224,10 @@ impl SPIRVBin {
 
     fn kernel_infos(&self) -> &[clc_kernel_info] {
         match self.info {
-            None => &[],
-            Some(info) => unsafe { slice::from_raw_parts(info.kernels, info.num_kernels as usize) },
+            Some(info) if info.num_kernels > 0 => unsafe {
+                slice::from_raw_parts(info.kernels, info.num_kernels as usize)
+            },
+            _ => &[],
         }
     }
 
@@ -447,6 +449,10 @@ impl SPIRVBin {
 
     pub fn spec_constant(&self, spec_id: u32) -> Option<clc_spec_constant_type> {
         let info = self.info?;
+        if info.num_spec_constants == 0 {
+            return None;
+        }
+
         let spec_constants =
             unsafe { slice::from_raw_parts(info.spec_constants, info.num_spec_constants as usize) };
 

src/gallium/targets/dri/dri_target.c

@@ -249,7 +249,7 @@ dri_loader_get_extensions(const char *driver_name)
       return __driDriverGetExtensions_tegra();
 #endif
 
-#if defined(HAVE_KMSRO)
+#if defined(GALLIUM_KMSRO)
    if (!strcmp(driver_name, "armada-drm"))
       return __driDriverGetExtensions_armada_drm();
    if (!strcmp(driver_name, "exynos"))

src/intel/blorp/blorp.h

@@ -148,14 +148,22 @@ void blorp_batch_init(struct blorp_context *blorp, struct blorp_batch *batch,
 void blorp_batch_finish(struct blorp_batch *batch);
 
 static inline isl_surf_usage_flags_t
-blorp_batch_isl_copy_usage(const struct blorp_batch *batch, bool is_dest)
+blorp_batch_isl_copy_usage(const struct blorp_batch *batch, bool is_dest,
+                           bool _protected)
 {
+   isl_surf_usage_flags_t usage;
+
    if (batch->flags & BLORP_BATCH_USE_COMPUTE)
-      return is_dest ? ISL_SURF_USAGE_STORAGE_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
+      usage = is_dest ? ISL_SURF_USAGE_STORAGE_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
    else if (batch->flags & BLORP_BATCH_USE_BLITTER)
-      return is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT : ISL_SURF_USAGE_BLITTER_SRC_BIT;
+      usage = is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT : ISL_SURF_USAGE_BLITTER_SRC_BIT;
    else
-      return is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
+      usage = is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
+
+   if (_protected)
+      usage |= ISL_SURF_USAGE_PROTECTED_BIT;
+
+   return usage;
 }
 
 struct blorp_address {

src/intel/common/intel_genX_state_brw.h

@@ -51,8 +51,22 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
    bool enable_8  = prog_data->dispatch_8;
    bool enable_16 = prog_data->dispatch_16;
    bool enable_32 = prog_data->dispatch_32;
+   uint8_t dispatch_multi = prog_data->dispatch_multi;
 
-#if GFX_VER >= 9 && GFX_VER < 20
+#if GFX_VER >= 20
+   if (ps->RenderTargetFastClearEnable) {
+      /* Bspec 57340 (r59562):
+       *
+       *   Clearing shader must use SIMD16 dispatch mode.
+       *
+       * The spec doesn't state if a fast-clear shader can be multi-poly. We
+       * just assume it can't.
+       */
+      assert(enable_16);
+      enable_32 = enable_8 = false;
+      dispatch_multi = 0;
+   }
+#elif GFX_VER >= 9
    /* SKL PRMs, Volume 2a: Command Reference: Instructions:
     *    3DSTATE_PS_BODY::8 Pixel Dispatch Enable:
     *
@@ -118,19 +132,16 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
    }
 
    assert(enable_8 || enable_16 || enable_32 ||
-          (GFX_VER >= 12 && prog_data->dispatch_multi));
-   assert(!prog_data->dispatch_multi ||
-          (GFX_VER >= 12 && !enable_8));
+          (GFX_VER >= 12 && dispatch_multi));
+   assert(!dispatch_multi || (GFX_VER >= 12 && !enable_8));
 
 #if GFX_VER >= 20
-   if (prog_data->dispatch_multi) {
+   if (dispatch_multi) {
       ps->Kernel0Enable = true;
-      ps->Kernel0SIMDWidth = (prog_data->dispatch_multi == 32 ?
-                              PS_SIMD32 : PS_SIMD16);
+      ps->Kernel0SIMDWidth = (dispatch_multi == 32 ? PS_SIMD32 : PS_SIMD16);
       ps->Kernel0MaximumPolysperThread =
          prog_data->max_polygons - 1;
-      switch (prog_data->dispatch_multi /
-              prog_data->max_polygons) {
+      switch (dispatch_multi / prog_data->max_polygons) {
       case 8:
          ps->Kernel0PolyPackingPolicy = POLY_PACK8_FIXED;
          break;
@@ -140,7 +151,6 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
       default:
          unreachable("Invalid polygon width");
       }
-
    } else if (enable_16) {
       ps->Kernel0Enable = true;
       ps->Kernel0SIMDWidth = PS_SIMD16;
@@ -150,14 +160,12 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
    if (enable_32) {
       ps->Kernel1Enable = true;
       ps->Kernel1SIMDWidth = PS_SIMD32;
-
-   } else if (enable_16 && prog_data->dispatch_multi == 16) {
+   } else if (enable_16 && dispatch_multi == 16) {
       ps->Kernel1Enable = true;
       ps->Kernel1SIMDWidth = PS_SIMD16;
    }
 #else
-   ps->_8PixelDispatchEnable = enable_8 ||
-      (GFX_VER == 12 && prog_data->dispatch_multi);
+   ps->_8PixelDispatchEnable = enable_8 || (GFX_VER == 12 && dispatch_multi);
    ps->_16PixelDispatchEnable = enable_16;
    ps->_32PixelDispatchEnable = enable_32;
 #endif

src/intel/compiler/brw_compiler.h

@@ -48,6 +48,8 @@ struct shader_info;
 struct nir_shader_compiler_options;
 typedef struct nir_shader nir_shader;
 
+#define REG_CLASS_COUNT 20
+
 struct brw_compiler {
    const struct intel_device_info *devinfo;
 
@@ -65,7 +67,7 @@ struct brw_compiler {
        * Array of the ra classes for the unaligned contiguous register
        * block sizes used, indexed by register size.
        */
-      struct ra_class *classes[16];
+      struct ra_class *classes[REG_CLASS_COUNT];
    } fs_reg_set;
 
    void (*shader_debug_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);

src/intel/compiler/brw_fs_reg_allocate.cpp

@@ -34,8 +34,6 @@
 
 using namespace brw;
 
-#define REG_CLASS_COUNT 20
-
 static void
 assign_reg(const struct intel_device_info *devinfo,
            unsigned *reg_hw_locations, brw_reg *reg)

src/intel/compiler/elk/elk_compiler.h

@@ -47,6 +47,8 @@ struct shader_info;
 struct nir_shader_compiler_options;
 typedef struct nir_shader nir_shader;
 
+#define REG_CLASS_COUNT 20
+
 struct elk_compiler {
    const struct intel_device_info *devinfo;
 
@@ -74,7 +76,7 @@ struct elk_compiler {
        * Array of the ra classes for the unaligned contiguous register
        * block sizes used, indexed by register size.
        */
-      struct ra_class *classes[16];
+      struct ra_class *classes[REG_CLASS_COUNT];
 
       /**
        * ra class for the aligned barycentrics we use for PLN, which doesn't

src/intel/compiler/elk/elk_fs_reg_allocate.cpp

@@ -34,8 +34,6 @@
 
 using namespace elk;
 
-#define REG_CLASS_COUNT 20
-
 static void
 assign_reg(const struct intel_device_info *devinfo,
            unsigned *reg_hw_locations, elk_fs_reg *reg)

src/intel/isl/isl.c

@@ -114,7 +114,7 @@ isl_device_setup_mocs(struct isl_device *dev)
       /* L3+L4=WB; BSpec: 71582 */
       dev->mocs.internal = 1 << 1;
       dev->mocs.external = 1 << 1;
-      dev->mocs.protected_mask = 3 << 0;
+      dev->mocs.protected_mask = 1 << 0;
       /* TODO: Setting to uncached
        * WA 14018443005:
        *  Ensure that any compression-enabled resource from gfx memory subject

src/intel/isl/isl_surface_state.c

@@ -242,7 +242,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
    /* They may only specify one of the above bits at a time */
    assert(__builtin_popcount(_base_usage) == 1);
    /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
-   assert((info->view->usage & ~ISL_SURF_USAGE_CUBE_BIT) == _base_usage);
+   assert((info->view->usage & ~(ISL_SURF_USAGE_CUBE_BIT |
+                                 ISL_SURF_USAGE_PROTECTED_BIT)) ==
+          _base_usage);
 #endif
 
    if (info->surf->dim == ISL_SURF_DIM_3D) {

src/intel/vulkan/anv_blorp.c

@@ -170,7 +170,7 @@ anv_blorp_batch_finish(struct blorp_batch *batch)
 
 static isl_surf_usage_flags_t
 get_usage_flag_for_cmd_buffer(const struct anv_cmd_buffer *cmd_buffer,
-                              bool is_dest)
+                              bool is_dest, bool protected)
 {
    isl_surf_usage_flags_t usage;
 
@@ -191,6 +191,9 @@ get_usage_flag_for_cmd_buffer(const struct anv_cmd_buffer *cmd_buffer,
       unreachable("Unhandled engine class");
    }
 
+   if (protected)
+      usage |= ISL_SURF_USAGE_PROTECTED_BIT;
+
    return usage;
 }
 
@@ -199,13 +202,13 @@ get_blorp_surf_for_anv_address(struct anv_cmd_buffer *cmd_buffer,
                                struct anv_address address,
                                uint32_t width, uint32_t height,
                                uint32_t row_pitch, enum isl_format format,
-                               bool is_dest,
+                               bool is_dest, bool protected,
                                struct blorp_surf *blorp_surf,
                                struct isl_surf *isl_surf)
 {
    bool ok UNUSED;
    isl_surf_usage_flags_t usage =
-      get_usage_flag_for_cmd_buffer(cmd_buffer, is_dest);
+      get_usage_flag_for_cmd_buffer(cmd_buffer, is_dest, protected);
 
    *blorp_surf = (struct blorp_surf) {
       .surf = isl_surf,
@@ -243,7 +246,8 @@ get_blorp_surf_for_anv_buffer(struct anv_cmd_buffer *cmd_buffer,
    get_blorp_surf_for_anv_address(cmd_buffer,
                                   anv_address_add(buffer->address, offset),
                                   width, height, row_pitch, format,
-                                  is_dest, blorp_surf, isl_surf);
+                                  is_dest, anv_buffer_is_protected(buffer),
+                                  blorp_surf, isl_surf);
 }
 
 /* Pick something high enough that it won't be used in core and low enough it
@@ -281,7 +285,8 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
 
    isl_surf_usage_flags_t isl_usage =
       get_usage_flag_for_cmd_buffer(cmd_buffer,
-                                    usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT);
+                                    usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT,
+                                    anv_image_is_protected(image));
    const struct anv_surface *surface = &image->planes[plane].primary_surface;
    const struct anv_address address =
       anv_image_address(image, &surface->memory_range);
@@ -1038,13 +1043,15 @@ copy_buffer(struct anv_device *device,
       .buffer = src_buffer->address.bo,
       .offset = src_buffer->address.offset + region->srcOffset,
       .mocs = anv_mocs(device, src_buffer->address.bo,
-                       blorp_batch_isl_copy_usage(batch, false /* is_dest */)),
+                       blorp_batch_isl_copy_usage(batch, false /* is_dest */,
+                                                  anv_buffer_is_protected(src_buffer))),
    };
    struct blorp_address dst = {
       .buffer = dst_buffer->address.bo,
       .offset = dst_buffer->address.offset + region->dstOffset,
       .mocs = anv_mocs(device, dst_buffer->address.bo,
-                       blorp_batch_isl_copy_usage(batch, true /* is_dest */)),
+                       blorp_batch_isl_copy_usage(batch, true /* is_dest */,
+                                                  anv_buffer_is_protected(dst_buffer))),
    };
 
    blorp_buffer_copy(batch, src, dst, region->size);
@@ -1121,14 +1128,17 @@ void anv_CmdUpdateBuffer(
          .offset = tmp_addr.offset,
          .mocs = anv_mocs(cmd_buffer->device, NULL,
                           get_usage_flag_for_cmd_buffer(cmd_buffer,
-                                                        false /* is_dest */)),
+                                                        false /* is_dest */,
+                                                        false /* protected */)),
       };
       struct blorp_address dst = {
          .buffer = dst_buffer->address.bo,
          .offset = dst_buffer->address.offset + dstOffset,
          .mocs = anv_mocs(cmd_buffer->device, dst_buffer->address.bo,
-                          get_usage_flag_for_cmd_buffer(cmd_buffer,
-                                                        true /* is_dest */)),
+                          get_usage_flag_for_cmd_buffer(
+                             cmd_buffer,
+                             true /* is_dest */,
+                             anv_buffer_is_protected(dst_buffer))),
       };
 
       blorp_buffer_copy(&batch, src, dst, copy_size);
@@ -1147,7 +1157,8 @@ void
 anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
                          struct anv_address address,
                          VkDeviceSize size,
-                         uint32_t data)
+                         uint32_t data,
+                         bool protected)
 {
    struct blorp_surf surf;
    struct isl_surf isl_surf;
@@ -1179,7 +1190,7 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
                                      },
                                      MAX_SURFACE_DIM, MAX_SURFACE_DIM,
                                      MAX_SURFACE_DIM * bs, isl_format,
-                                     true /* is_dest */,
+                                     true /* is_dest */, protected,
                                      &surf, &isl_surf);
 
       blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
@@ -1199,7 +1210,7 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
                                      },
                                      MAX_SURFACE_DIM, height,
                                      MAX_SURFACE_DIM * bs, isl_format,
-                                     true /* is_dest */,
+                                     true /* is_dest */, protected,
                                      &surf, &isl_surf);
 
       blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
@@ -1217,7 +1228,7 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
                                      },
                                      width, 1,
                                      width * bs, isl_format,
-                                     true /* is_dest */,
+                                     true /* is_dest */, protected,
                                      &surf, &isl_surf);
 
       blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
@@ -1252,7 +1263,8 @@ void anv_CmdFillBuffer(
 
    anv_cmd_buffer_fill_area(cmd_buffer,
                             anv_address_add(dst_buffer->address, dstOffset),
-                            fillSize, data);
+                            fillSize, data,
+                            anv_buffer_is_protected(dst_buffer));
 
    anv_add_buffer_write_pending_bits(cmd_buffer, "after fill buffer");
 }

src/intel/vulkan/anv_image.c

@@ -252,6 +252,9 @@ anv_image_choose_isl_surf_usage(struct anv_physical_device *device,
                           VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT))
       isl_usage |= ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT;
 
+   if (vk_create_flags & VK_IMAGE_CREATE_PROTECTED_BIT)
+      isl_usage |= ISL_SURF_USAGE_PROTECTED_BIT;
+
    /* Even if we're only using it for transfer operations, clears to depth and
     * stencil images happen as depth and stencil so they need the right ISL
     * usage bits or else things will fall apart.
@@ -1581,6 +1584,19 @@ anv_image_init(struct anv_device *device, struct anv_image *image,
 
       if (isl_drm_modifier_needs_display_layout(image->vk.drm_format_mod))
          isl_extra_usage_flags |= ISL_SURF_USAGE_DISPLAY_BIT;
+
+      if (device->info->ver >= 20 &&
+          !isl_drm_modifier_has_aux(image->vk.drm_format_mod)) {
+         /* TODO: On Xe2+, we cannot support modifiers that don't support
+          * compression because such support requires an explicit resolve
+          * that hasn't been implemented.
+          *
+          * We disable this in anv_AllocateMemory() as well.
+          *
+          * https://gitlab.freedesktop.org/mesa/mesa/-/issues/11537
+          */
+         isl_extra_usage_flags |= ISL_SURF_USAGE_DISABLE_AUX_BIT;
+      }
    }
 
    for (int i = 0; i < ANV_IMAGE_MEMORY_BINDING_END; ++i) {
@@ -2552,8 +2568,8 @@ anv_bind_image_memory(struct anv_device *device,
       if (device->info->has_aux_map && anv_image_map_aux_tt(device, image, p))
          continue;
 
-      /* Do nothing prior to gfx12. There are no special requirements. */
-      if (device->info->ver < 12)
+      /* Do nothing except for gfx12. There are no special requirements. */
+      if (device->info->ver != 12)
          continue;
 
       /* The plane's BO cannot support CCS, disable compression on it. */
@@ -3298,6 +3314,9 @@ anv_image_fill_surface_state(struct anv_device *device,
    struct isl_view view = *view_in;
    view.usage |= view_usage;
 
+   /* Propagate the protection flag of the image to the view. */
+   view_usage |= surface->isl.usage & ISL_SURF_USAGE_PROTECTED_BIT;
+
    if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
       view.swizzle = anv_swizzle_for_render(view.swizzle);
 

src/intel/vulkan/anv_private.h

@@ -3255,6 +3255,12 @@ struct anv_buffer {
    struct anv_sparse_binding_data sparse_data;
 };
 
+static inline bool
+anv_buffer_is_protected(const struct anv_buffer *buffer)
+{
+   return buffer->vk.create_flags & VK_BUFFER_CREATE_PROTECTED_BIT;
+}
+
 static inline bool
 anv_buffer_is_sparse(const struct anv_buffer *buffer)
 {
@@ -5317,6 +5323,12 @@ struct anv_image {
    struct list_head link;
 };
 
+static inline bool
+anv_image_is_protected(const struct anv_image *image)
+{
+   return image->vk.create_flags & VK_IMAGE_CREATE_PROTECTED_BIT;
+}
+
 static inline bool
 anv_image_is_sparse(const struct anv_image *image)
 {
@@ -5685,7 +5697,8 @@ void
 anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
                          struct anv_address address,
                          VkDeviceSize size,
-                         uint32_t data);
+                         uint32_t data,
+                         bool protected);
 
 VkResult
 anv_cmd_buffer_ensure_rcs_companion(struct anv_cmd_buffer *cmd_buffer);

src/intel/vulkan/genX_cmd_buffer.c

@@ -823,6 +823,7 @@ genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
                                     uint32_t base_layer,
                                     uint32_t layer_count)
 {
+#if GFX_VER < 20
    /* The aspect must be exactly one of the image aspects. */
    assert(util_bitcount(aspect) == 1 && (aspect & image->vk.aspects));
 
@@ -836,6 +837,7 @@ genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
 
    set_image_compressed_bit(cmd_buffer, image, aspect,
                             level, base_layer, layer_count, true);
+#endif
 }
 
 static void
@@ -3945,8 +3947,6 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
       return;
    }
 
-   struct anv_device *device = cmd_buffer->device;
-
    /* XXX: Right now, we're really dumb and just flush whatever categories
     * the app asks for. One of these days we may make this a bit better but
     * right now that's all the hardware allows for in most areas.
@@ -3956,6 +3956,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
 
 #if GFX_VER < 20
    bool apply_sparse_flushes = false;
+   struct anv_device *device = cmd_buffer->device;
 #endif
    bool flush_query_copies = false;
 
@@ -4093,7 +4094,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
                                        false /* will_full_fast_clear */);
             }
          }
-
+#if GFX_VER < 20
          /* Mark image as compressed if the destination layout has untracked
           * writes to the aux surface.
           */
@@ -4125,7 +4126,6 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
             }
          }
 
-#if GFX_VER < 20
          if (anv_image_is_sparse(image) && mask_is_write(src_flags))
             apply_sparse_flushes = true;
 #endif
@@ -5351,6 +5351,7 @@ cmd_buffer_mark_attachment_written(struct anv_cmd_buffer *cmd_buffer,
                                    struct anv_attachment *att,
                                    VkImageAspectFlagBits aspect)
 {
+#if GFX_VER < 20
    struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
    const struct anv_image_view *iview = att->iview;
 
@@ -5376,6 +5377,7 @@ cmd_buffer_mark_attachment_written(struct anv_cmd_buffer *cmd_buffer,
                                              level, layer, 1);
       }
    }
+#endif
 }
 
 void genX(CmdEndRendering)(

src/intel/vulkan/genX_query.c

@@ -799,15 +799,18 @@ void genX(CmdResetQueryPool)(
    ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
    struct anv_physical_device *pdevice = cmd_buffer->device->physical;
 
-   /* Shader clearing is only possible on render/compute */
+   /* Shader clearing is only possible on render/compute when not in protected
+    * mode.
+    */
    if (anv_cmd_buffer_is_render_or_compute_queue(cmd_buffer) &&
+       (cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT) != 0 &&
        queryCount >= pdevice->instance->query_clear_with_blorp_threshold) {
       trace_intel_begin_query_clear_blorp(&cmd_buffer->trace);
 
       anv_cmd_buffer_fill_area(cmd_buffer,
                                anv_query_address(pool, firstQuery),
                                queryCount * pool->stride,
-                               0);
+                               0, false);
 
       /* The pending clearing writes are in compute if we're in gpgpu mode on
        * the render engine or on the compute engine.

src/panfrost/vulkan/bifrost/panvk_vX_meta_desc_copy.c

@@ -312,8 +312,7 @@ panvk_per_arch(meta_get_copy_desc_job)(
       .img_attrib_table = shader_desc_state->img_attrib_table,
       .desc_copy = {
          .table = copy_table,
-         .attrib_buf_idx_offset =
-            shader->info.stage == MESA_SHADER_VERTEX ? MAX_VS_ATTRIBS : 0,
+         .attrib_buf_idx_offset = attrib_buf_idx_offset,
       },
    };
 

src/virtio/vulkan/vn_renderer_virtgpu.c

@@ -1111,10 +1111,15 @@ virtgpu_bo_destroy(struct vn_renderer *renderer, struct vn_renderer_bo *_bo)
 
    if (bo->base.mmap_ptr)
       munmap(bo->base.mmap_ptr, bo->base.mmap_size);
-   virtgpu_ioctl_gem_close(gpu, bo->gem_handle);
 
-   /* set gem_handle to 0 to indicate that the bo is invalid */
+   /* Set gem_handle to 0 to indicate that the bo is invalid. Must be set
+    * before closing gem handle. Otherwise the same gem handle can be reused
+    * by another newly created bo and unexpectedly gotten zero'ed out the
+    * tracked gem handle.
+    */
+   const uint32_t gem_handle = bo->gem_handle;
    bo->gem_handle = 0;
+   virtgpu_ioctl_gem_close(gpu, gem_handle);
 
    mtx_unlock(&gpu->dma_buf_import_mutex);