docs: Add release notes for the 10.2.3 release.

Which is imminent.

VERSION

@@ -1 +1 @@
-10.2.0-devel
+10.2.3

bin/.cherry-ignore

@@ -0,0 +1,7 @@
+# The first is the change, and the second is the revert of that change.
+e6967270c75a5b669152127bb7a746d55f4407a6 i965: Fix depth (array slices) computation for 1D_ARRAY render targets.
+155f98d49fdc2f46c760f8214327b3804ee60079 Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."
+
+# This patch didn't have enough in the commit message to convince me it
+# is a bug fix, (email sent to author asking for more information).
+41d759d076737f94976f5294b734dbc437a12bae

configure.ac

@@ -331,6 +331,19 @@ LDFLAGS=$save_LDFLAGS
 
 AC_SUBST([GC_SECTIONS])
 
+dnl
+dnl OpenBSD does not have DT_NEEDED entries for libc by design
+dnl so when these flags are passed to ld via libtool the checks will fail
+dnl
+case "$host_os" in
+openbsd*)
+    LD_NO_UNDEFINED="" ;;
+*)
+    LD_NO_UNDEFINED="-Wl,--no-undefined" ;;
+esac
+
+AC_SUBST([LD_NO_UNDEFINED])
+
 dnl
 dnl compatibility symlinks
 dnl
@@ -1179,6 +1192,13 @@ if test "x$enable_gbm" = xyes; then
         if test "x$enable_shared_glapi" = xno; then
             AC_MSG_ERROR([gbm_dri requires --enable-shared-glapi])
         fi
+    else
+        # Strictly speaking libgbm does not require --enable-dri, although
+        # both of its backends do. Thus one can build libgbm without any
+        # backends if --disable-dri is set.
+        # To avoid unnecessary complexity of checking if at least one backend
+        # is available when building, just mandate --enable-dri.
+        AC_MSG_ERROR([gbm requires --enable-dri])
     fi
 fi
 AM_CONDITIONAL(HAVE_GBM, test "x$enable_gbm" = xyes)
@@ -1273,6 +1293,7 @@ if test "x$enable_xa" = xyes; then
     fi
     GALLIUM_STATE_TRACKERS_DIRS="xa $GALLIUM_STATE_TRACKERS_DIRS"
     enable_gallium_loader=yes
+    enable_gallium_drm_loader=yes
 fi
 AM_CONDITIONAL(HAVE_ST_XA, test "x$enable_xa" = xyes)
 
@@ -1303,7 +1324,7 @@ AM_CONDITIONAL(HAVE_OPENVG, test "x$enable_openvg" = xyes)
 dnl
 dnl Gallium G3DVL configuration
 dnl
-if test -n "$with_gallium_drivers" && ! echo "$with_gallium_drivers" | grep -q 'swrast'; then
+if test -n "$with_gallium_drivers" -a "x$with_gallium_drivers" != xswrast; then
     if test "x$enable_xvmc" = xauto; then
 	PKG_CHECK_EXISTS([xvmc], [enable_xvmc=yes], [enable_xvmc=no])
     fi
@@ -1605,6 +1626,12 @@ if test "x$enable_gallium_llvm" = xyes; then
         AC_COMPUTE_INT([LLVM_VERSION_MINOR], [LLVM_VERSION_MINOR],
             [#include "${LLVM_INCLUDEDIR}/llvm/Config/llvm-config.h"])
 
+        dnl In LLVM 3.4.1 patch level was defined in config.h and not
+        dnl llvm-config.h
+        AC_COMPUTE_INT([LLVM_VERSION_PATCH], [LLVM_VERSION_PATCH],
+            [#include "${LLVM_INCLUDEDIR}/llvm/Config/config.h"],
+            LLVM_VERSION_PATCH=0) dnl Default if LLVM_VERSION_PATCH not found
+
         if test -n "${LLVM_VERSION_MAJOR}"; then
             LLVM_VERSION_INT="${LLVM_VERSION_MAJOR}0${LLVM_VERSION_MINOR}"
         else
@@ -1627,7 +1654,7 @@ if test "x$enable_gallium_llvm" = xyes; then
                 LLVM_COMPONENTS="${LLVM_COMPONENTS} option"
             fi
         fi
-        DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT"
+        DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT -DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH"
         MESA_LLVM=1
 
         dnl Check for Clang internal headers
@@ -1646,6 +1673,10 @@ if test "x$enable_gallium_llvm" = xyes; then
 else
     MESA_LLVM=0
     LLVM_VERSION_INT=0
+
+    if test "x$enable_opencl" = xyes; then
+        AC_MSG_ERROR([cannot enable OpenCL without LLVM])
+    fi
 fi
 
 dnl Directory for XVMC libs

docs/index.html

@@ -16,6 +16,20 @@
 
 <h1>News</h1>
 
+<h2>June 6, 2014</h2>
+<p>
+<a href="relnotes/10.2.1.html">Mesa 10.2.1</a> is released.  This release
+only fixes a build error in the radeonsi driver that was introduced between
+10.2-rc5 and the 10.2 final release.
+</p>
+
+<h2>June 6, 2014</h2>
+<p>
+<a href="relnotes/10.2.html">Mesa 10.2</a> is released.  This is a new
+development release.  See the release notes for more information about
+the release.
+</p>
+
 <h2>April 18, 2014</h2>
 <p>
 <a href="relnotes/10.1.1.html">Mesa 10.1.1</a> is released.

docs/relnotes.html

@@ -21,6 +21,8 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>
 
 <ul>
+<li><a href="relnotes/10.2.1.html">10.2.1 release notes</a>
+<li><a href="relnotes/10.2.html">10.2 release notes</a>
 <li><a href="relnotes/10.1.1.html">10.1.1 release notes</a>
 <li><a href="relnotes/10.1.html">10.1 release notes</a>
 <li><a href="relnotes/10.0.5.html">10.0.5 release notes</a>

docs/relnotes/10.2.1.html

@@ -0,0 +1,61 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.1 Release Notes / June 6, 2014</h1>
+
+<p>
+Mesa 10.2.1 is a bug fix release which fixes bugs found since the 10.1 release.
+</p>
+<p>
+Mesa 10.2.1 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+96f892dae2d0bb14ac9c2113f586c909  MesaLib-10.2.1.tar.gz
+093f9b5d077e5f6061dcd7b01b7aa51a  MesaLib-10.2.1.tar.bz2
+6ab76c1608e5deed1eb8b54c62d7a48a  MesaLib-10.2.1.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>
+Mesa 10.2 had a build problem in the radeonsi driver due to an error resolving
+conflicts in a patch cherry-pick from master.  The build error is fixed.
+</p>
+
+<h2>Changes</h2>
+
+<p>Ian Romanick (3):</p>
+<ul>
+  <li>docs: Add MD5 checksum, etc. for 10.1 release</li>
+  <li>radeonsi: Fix build error introduced in 5ab9a9c</li>
+  <li>Bump version to 10.2.1</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.2.html

@@ -0,0 +1,181 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.2 Release Notes / June 24, 2014</h1>
+
+<p>
+Mesa 10.2.2 is a bug fix release which fixes bugs found since the 10.2.1 release.
+</p>
+<p>
+Mesa 10.2.2 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+38c4a40364000f89cddaa1694f6f3cfb444981d1110238ce603093585477399c  MesaLib-10.2.2.tar.bz2
+2af2ec8b4db624c352e961eefbcce6c8d1f86d44c5542f6f378c50e1b958d453  MesaLib-10.2.2.tar.gz
+d4c0372da59367a344d62ebcdf5cf61039c9cae6925f40f2dab8f8d95cf22da9  MesaLib-10.2.2.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54372">Bug 54372</a> - GLX_INTEL_swap_event crashes driver when swapping window buffers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66452">Bug 66452</a> - JUNIPER UVD accelerated playback of WMV3 streams does not work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=74005">Bug 74005</a> - [i965 Bisected]Piglit/glx_glx-make-glxdrawable-current fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=77865">Bug 77865</a> - [BDW] Many Ogles3conform framebuffer_blit cases fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78581">Bug 78581</a> - OpenCL: clBuildProgram prints error messages directly rather than storing them</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79029">Bug 79029</a> - INTEL_DEBUG=shader_time is full of lies</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79729">Bug 79729</a> - [i965] glClear on a multisample texture doesn't work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79907">Bug 79907</a> - Mesa 10.2.1 --enable-vdpau default=auto broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80115">Bug 80115</a> - MESA_META_DRAW_BUFFERS induced GL_INVALID_VALUE errors</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Adrian Negreanu (8):</p>
+<ul>
+  <li>add megadriver_stub_FILES</li>
+  <li>android: adapt to the megadriver mechanism</li>
+  <li>android: add libloader to libGLES_mesa and libmesa_egl_dri2</li>
+  <li>android: add src/gallium/auxiliary as include path for libmesa_dricore</li>
+  <li>android, egl: add correct drm include for libmesa_egl_dri2</li>
+  <li>android, egl: typo dri2_fallback_pixmap_surface -&gt; dri2_fallback_create_pixmap_surface</li>
+  <li>android, mesa_gen_matypes: pull in timespec POSIX definition</li>
+  <li>android, dricore: undefined reference to _mesa_streaming_load_memcpy</li>
+</ul>
+
+<p>Carl Worth (1):</p>
+<ul>
+  <li>Update VERSION to 10.2.2</li>
+</ul>
+
+<p>Daniel Manjarres (1):</p>
+<ul>
+  <li>glx: Don't crash on swap event for a Window (non-GLXWindow)</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>targets/xa: limit the amount of exported symbols</li>
+  <li>configure: error out when building opencl without LLVM</li>
+  <li>configure: correctly autodetect xvmc/vdpau/omx</li>
+</ul>
+
+<p>Grigori Goronzy (1):</p>
+<ul>
+  <li>radeon/uvd: disable VC-1 simple/main on UVD 2.x</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>mesa: Copy Geom.UsesEndPrimitive when cloning a geometry program.</li>
+</ul>
+
+<p>Ian Romanick (3):</p>
+<ul>
+  <li>docs: Add initial 10.2.1 release notes</li>
+  <li>docs: Add MD5 checksum, etc. for 10.2.1 release</li>
+  <li>meta: Respect the driver's maximum number of draw buffers</li>
+</ul>
+
+<p>Ilia Mirkin (7):</p>
+<ul>
+  <li>gk110/ir: emit saturate flag on fadd when needed</li>
+  <li>gk110/ir: fix emitting constbuf file index</li>
+  <li>gk110/ir: fix bfind emission</li>
+  <li>nv50: make sure to mark first scissor dirty after blit</li>
+  <li>nv30: plug some memory leaks on screen destroy and shader compile</li>
+  <li>nv30: avoid dangling references to deleted contexts</li>
+  <li>nv30: hack to avoid errors on unexpected color/zeta combinations</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>meta_blit: properly compute texture width for the CopyTexSubImage fallback</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>mesa/main: Prevent sefgault on glGetIntegerv(GL_ATOMIC_COUNTER_BUFFER_BINDING).</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+  <li>i965: Don't use the head sentinel as an fs_inst in Gen4 workaround code.</li>
+  <li>i965: Invalidate live intervals when inserting Gen4 SEND workarounds.</li>
+  <li>i965/vec4: Fix dead code elimination for VGRFs of size &gt; 1.</li>
+  <li>i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.</li>
+  <li>i965: Drop Broadwell perf_debugs about missing MOCS that aren't missing.</li>
+  <li>i965: Add missing newlines to a few perf_debug messages.</li>
+  <li>i965/vec4: Use the sampler for pull constant loads on Broadwell.</li>
+  <li>i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.</li>
+  <li>i965: Save meta stencil blit programs in the context.</li>
+</ul>
+
+<p>Kristian Høgsberg (1):</p>
+<ul>
+  <li>mesa: Remove glClear optimization based on drawable size</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>configure: Only check for OpenCL without LLVM when the latter is certain</li>
+</ul>
+
+<p>Neil Roberts (1):</p>
+<ul>
+  <li>i965: Set the fast clear color value for texture surfaces</li>
+</ul>
+
+<p>Tom Stellard (2):</p>
+<ul>
+  <li>clover: Prevent Clang from printing number of errors and warnings to stderr.</li>
+  <li>clover: Don't use llvm's global context</li>
+</ul>
+
+<p>Ville Syrjälä (1):</p>
+<ul>
+  <li>i915: Fix gen2 texblend setup</li>
+</ul>
+
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.3.html

@@ -0,0 +1,127 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.3 Release Notes / July 7, 2014</h1>
+
+<p>
+Mesa 10.2.3 is a bug fix release which fixes bugs found since the 10.2.2 release.
+</p>
+<p>
+Mesa 10.2.3 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=76223">Bug 76223</a> - </li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79823">Bug 79823</a> - </li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80015">Bug 80015</a> - </li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Aaron Watry (1):</p>
+<ul>
+  <li>radeon/llvm: Allocate space for kernel metadata operands</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.2.2 release</li>
+  <li>cherry-ignore: Add a patch that's been rejected</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+  <li>nouveau: dup fd before passing it to device</li>
+  <li>nv50: disable dedicated ubo upload method</li>
+  <li>nv50: do an explicit flush on draw when there are persistent buffers</li>
+  <li>nvc0: add a memory barrier when there are persistent UBOs</li>
+</ul>
+
+<p>Jasper St. Pierre (1):</p>
+<ul>
+  <li>glxext: Send the Drawable's ID in the GLX_BufferSwapComplete event</li>
+</ul>
+
+<p>Kenneth Graunke (3):</p>
+<ul>
+  <li>i965: Don't emit SURFACE_STATEs for gather workarounds on Broadwell.</li>
+  <li>i965: Include marketing names for Broadwell GPUs.</li>
+  <li>i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeon/llvm: Use the llvm.rsq.clamped intrinsic for RSQ</li>
+</ul>
+
+<p>Rob Clark (9):</p>
+<ul>
+  <li>xa: fix segfault</li>
+  <li>freedreno: use OUT_RELOCW when buffer is written</li>
+  <li>freedreno/a3xx: fix depth/stencil GMEM positioning</li>
+  <li>freedreno/a3xx: fix depth/stencil gmem restore</li>
+  <li>freedreno/a3xx: fix blend opcode</li>
+  <li>freedreno: few caps fixes</li>
+  <li>freedreno/a3xx: texture fixes</li>
+  <li>freedreno: fix for null textures</li>
+  <li>freedreno/a3xx: vtx formats</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>draw: (trivial) fix clamping of viewport index</li>
+</ul>
+
+<p>Takashi Iwai (1):</p>
+<ul>
+  <li>llvmpipe: Fix zero-division in llvmpipe_texture_layout()</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+  <li>st/xa: Don't close the drm fd on failure v2</li>
+</ul>
+
+<p>Tobias Klausmann (1):</p>
+<ul>
+  <li>nv50/ir: allow gl_ViewportIndex to work on non-provoking vertices</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/10.2.html

@@ -14,7 +14,7 @@
 <iframe src="../contents.html"></iframe>
 <div class="content">
 
-<h1>Mesa 10.2 Release Notes / TBD</h1>
+<h1>Mesa 10.2 Release Notes / June 6, 2014</h1>
 
 <p>
 Mesa 10.2 is a new development release.
@@ -33,7 +33,9 @@ because compatibility contexts are not supported.
 
 <h2>MD5 checksums</h2>
 <pre>
-TBD.
+c87bfb6dd5cbcf1fdef42e5ccd972581  MesaLib-10.2.0.tar.gz
+7aaba90bd7169a94ae2fe83febdec963  MesaLib-10.2.0.tar.bz2
+58b203aca15dadc25ab4d1126db1052b  MesaLib-10.2.0.zip
 </pre>
 
 
@@ -67,6 +69,25 @@ TBD.
 <h2>Changes</h2>
 
 <ul>
+<li>Renamed <i>--with-llvm-shared-libs</i> to <i>--enable-llvm-shared-libs</i></li>
+<p>
+The option is used to control how mesa is linked against LLVM, and now
+defaults to enabled (shared linking).
+</p>
+
+<li>Split <i>libxatracker.so</i> into a standalone library which can be used
+with any gallium driver.</li>
+<p>
+Previously the library was linked statically against vmware's virtual gpu
+driver(svga), whereas now it loads a shared pipe_*.so driver. Provide the
+following options during configure, if you would like support for svga driver
+<i>--enable-xa --with-gallium-drivers=svga</i>
+</p>
+
+<p>
+Note: The files are installed in $(libdir)/gallium-pipe/ and the interface
+between them and libxatracker.so is <strong>not</strong> stable.
+</p>
 </ul>
 
 </div>

include/GL/glx.h

@@ -518,7 +518,7 @@ typedef struct {
     unsigned long serial;	/* # of last request processed by server */
     Bool send_event;		/* true if this came from a SendEvent request */
     Display *display;		/* Display the event was read from */
-    GLXDrawable drawable;	/* drawable on which event was requested in event mask */
+    Drawable drawable;	/* drawable on which event was requested in event mask */
     int event_type;
     int64_t ust;
     int64_t msc;

include/pci_ids/i965_pci_ids.h

@@ -91,24 +91,24 @@ CHIPSET(0x0F32, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0F33, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0157, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0155, byt,     "Intel(R) Bay Trail")
-CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell")
+CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell GT1")
-CHIPSET(0x1612, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x1612, bdw_gt2, "Intel(R) HD Graphics 5600 (Broadwell GT2)")
-CHIPSET(0x1616, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x1616, bdw_gt2, "Intel(R) HD Graphics 5500 (Broadwell GT2)")
-CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell GT2")
-CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell GT2")
-CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell GT2")
-CHIPSET(0x161E, bdw_gt2, "Intel(R) Broadwell")
+CHIPSET(0x161E, bdw_gt2, "Intel(R) HD Graphics 5300 (Broadwell GT2)")
-CHIPSET(0x1622, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x1622, bdw_gt3, "Intel(R) Iris Pro 6200 (Broadwell GT3e)")
-CHIPSET(0x1626, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x1626, bdw_gt3, "Intel(R) HD Graphics 6000 (Broadwell GT3)")
-CHIPSET(0x162A, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)")
-CHIPSET(0x162B, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)")
-CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3")
-CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3")
 CHIPSET(0x22B0, chv,     "Intel(R) Cherryview")
 CHIPSET(0x22B1, chv,     "Intel(R) Cherryview")
 CHIPSET(0x22B2, chv,     "Intel(R) Cherryview")

src/egl/drivers/dri2/Android.mk

@@ -40,8 +40,12 @@ LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/egl/main \
 	$(MESA_TOP)/src/loader \
+	$(DRM_TOP)/include/drm \
 	$(DRM_GRALLOC_TOP)
 
+LOCAL_STATIC_LIBRARIES := \
+	libloader
+
 LOCAL_MODULE := libmesa_egl_dri2
 
 include $(MESA_COMMON_MK)

src/egl/drivers/dri2/platform_android.c

@@ -638,7 +638,7 @@ droid_log(EGLint level, const char *msg)
 static struct dri2_egl_display_vtbl droid_display_vtbl = {
    .authenticate = NULL,
    .create_window_surface = droid_create_window_surface,
-   .create_pixmap_surface = dri2_fallback_pixmap_surface,
+   .create_pixmap_surface = dri2_fallback_create_pixmap_surface,
    .create_pbuffer_surface = droid_create_pbuffer_surface,
    .destroy_surface = droid_destroy_surface,
    .create_image = droid_create_image_khr,

src/egl/main/Android.mk

@@ -154,11 +154,14 @@ LOCAL_STATIC_LIBRARIES := \
 	libmesa_glsl \
 	libmesa_glsl_utils \
 	libmesa_gallium \
-	libloader \
 	$(LOCAL_STATIC_LIBRARIES)
 
 endif # MESA_BUILD_GALLIUM
 
+LOCAL_STATIC_LIBRARIES := \
+	$(LOCAL_STATIC_LIBRARIES) \
+	libloader
+
 LOCAL_MODULE := libGLES_mesa
 LOCAL_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/egl
 

src/egl/main/eglapi.c

@@ -524,8 +524,12 @@ eglMakeCurrent(EGLDisplay dpy, EGLSurface draw, EGLSurface read,
    if (!context && ctx != EGL_NO_CONTEXT)
       RETURN_EGL_ERROR(disp, EGL_BAD_CONTEXT, EGL_FALSE);
    if (!draw_surf || !read_surf) {
-      /* surfaces may be NULL if surfaceless */
+      /* From the EGL 1.4 (20130211) spec:
-      if (!disp->Extensions.KHR_surfaceless_context)
+       *
+       *    To release the current context without assigning a new one, set ctx
+       *    to EGL_NO_CONTEXT and set draw and read to EGL_NO_SURFACE.
+       */
+      if (!disp->Extensions.KHR_surfaceless_context && ctx != EGL_NO_CONTEXT)
          RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
 
       if ((!draw_surf && draw != EGL_NO_SURFACE) ||
@@ -567,6 +571,10 @@ _eglCreateWindowSurfaceCommon(_EGLDisplay *disp, EGLConfig config,
    EGLSurface ret;
 
    _EGL_CHECK_CONFIG(disp, conf, EGL_NO_SURFACE, drv);
+
+   if (native_window == NULL)
+      RETURN_EGL_ERROR(disp, EGL_BAD_NATIVE_WINDOW, EGL_NO_SURFACE);
+
    surf = drv->API.CreateWindowSurface(drv, disp, conf, native_window,
                                        attrib_list);
    ret = (surf) ? _eglLinkSurface(surf) : EGL_NO_SURFACE;

src/egl/wayland/wayland-drm/wayland-drm.xml

@@ -135,22 +135,6 @@
       <arg name="stride2" type="int"/>
     </request>
 
-    <!-- Create a wayland buffer for the prime fd.  Use for regular and planar
-         buffers.  Pass 0 for offset and stride for unused planes. -->
-    <request name="create_prime_buffer" since="2">
-      <arg name="id" type="new_id" interface="wl_buffer"/>
-      <arg name="name" type="fd"/>
-      <arg name="width" type="int"/>
-      <arg name="height" type="int"/>
-      <arg name="format" type="uint"/>
-      <arg name="offset0" type="int"/>
-      <arg name="stride0" type="int"/>
-      <arg name="offset1" type="int"/>
-      <arg name="stride1" type="int"/>
-      <arg name="offset2" type="int"/>
-      <arg name="stride2" type="int"/>
-    </request>
-
     <!-- Notification of the path of the drm device which is used by
          the server.  The client should use this device for creating
          local buffers.  Only buffers created from this device should
@@ -177,6 +161,25 @@
     <event name="capabilities">
       <arg name="value" type="uint"/>
     </event>
+
+    <!-- Version 2 additions -->
+
+    <!-- Create a wayland buffer for the prime fd.  Use for regular and planar
+         buffers.  Pass 0 for offset and stride for unused planes. -->
+    <request name="create_prime_buffer" since="2">
+      <arg name="id" type="new_id" interface="wl_buffer"/>
+      <arg name="name" type="fd"/>
+      <arg name="width" type="int"/>
+      <arg name="height" type="int"/>
+      <arg name="format" type="uint"/>
+      <arg name="offset0" type="int"/>
+      <arg name="stride0" type="int"/>
+      <arg name="offset1" type="int"/>
+      <arg name="stride1" type="int"/>
+      <arg name="offset2" type="int"/>
+      <arg name="stride2" type="int"/>
+    </request>
+
   </interface>
 
 </protocol>

src/gallium/auxiliary/draw/draw_context.c

@@ -1000,6 +1000,8 @@ draw_get_shader_param_no_llvm(unsigned shader, enum pipe_shader_cap param)
 /**
  * XXX: Results for PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS because there are two
  * different ways of setting textures, and drivers typically only support one.
+ * Drivers requesting a draw context explicitly without llvm must call
+ * draw_get_shader_param_no_llvm instead.
  */
 int
 draw_get_shader_param(unsigned shader, enum pipe_shader_cap param)

src/gallium/auxiliary/draw/draw_gs.c

@@ -597,7 +597,7 @@ int draw_geometry_shader_run(struct draw_geometry_shader *shader,
 
 
 #ifdef HAVE_LLVM
-   if (draw_get_option_use_llvm()) {
+   if (shader->draw->llvm) {
       shader->gs_output = output_verts->verts;
       if (max_out_prims > shader->max_out_prims) {
          unsigned i;
@@ -674,7 +674,7 @@ int draw_geometry_shader_run(struct draw_geometry_shader *shader,
 void draw_geometry_shader_prepare(struct draw_geometry_shader *shader,
                                   struct draw_context *draw)
 {
-   boolean use_llvm = draw_get_option_use_llvm();
+   boolean use_llvm = draw->llvm != NULL;
    if (!use_llvm && shader && shader->machine->Tokens != shader->state.tokens) {
       tgsi_exec_machine_bind_shader(shader->machine,
                                     shader->state.tokens,
@@ -686,7 +686,7 @@ void draw_geometry_shader_prepare(struct draw_geometry_shader *shader,
 boolean
 draw_gs_init( struct draw_context *draw )
 {
-   if (!draw_get_option_use_llvm()) {
+   if (!draw->llvm) {
       draw->gs.tgsi.machine = tgsi_exec_machine_create();
       if (!draw->gs.tgsi.machine)
          return FALSE;
@@ -715,7 +715,7 @@ draw_create_geometry_shader(struct draw_context *draw,
                             const struct pipe_shader_state *state)
 {
 #ifdef HAVE_LLVM
-   boolean use_llvm = draw_get_option_use_llvm();
+   boolean use_llvm = draw->llvm != NULL;
    struct llvm_geometry_shader *llvm_gs;
 #endif
    struct draw_geometry_shader *gs;
@@ -870,7 +870,7 @@ void draw_delete_geometry_shader(struct draw_context *draw,
       return;
    }
 #ifdef HAVE_LLVM
-   if (draw_get_option_use_llvm()) {
+   if (draw->llvm) {
       struct llvm_geometry_shader *shader = llvm_geometry_shader(dgs);
       struct draw_gs_llvm_variant_list_item *li;
 

src/gallium/auxiliary/draw/draw_private.h

@@ -47,7 +47,6 @@
 #include "tgsi/tgsi_scan.h"
 
 #ifdef HAVE_LLVM
-struct draw_llvm;
 struct gallivm_state;
 #endif
 
@@ -69,6 +68,7 @@ struct tgsi_exec_machine;
 struct tgsi_sampler;
 struct draw_pt_front_end;
 struct draw_assembler;
+struct draw_llvm;
 
 
 /**
@@ -318,9 +318,7 @@ struct draw_context
    unsigned start_instance;
    unsigned start_index;
 
-#ifdef HAVE_LLVM
    struct draw_llvm *llvm;
-#endif
 
    /** Texture sampler and sampler view state.
     * Note that we have arrays indexed by shader type.  At this time
@@ -495,7 +493,7 @@ draw_stats_clipper_primitives(struct draw_context *draw,
 static INLINE unsigned
 draw_clamp_viewport_idx(int idx)
 {
-   return ((PIPE_MAX_VIEWPORTS > idx || idx < 0) ? idx : 0);
+   return ((PIPE_MAX_VIEWPORTS > idx && idx >= 0) ? idx : 0);
 }
 
 /**

src/gallium/auxiliary/draw/draw_vs.c

@@ -149,7 +149,7 @@ draw_vs_init( struct draw_context *draw )
 {
    draw->dump_vs = debug_get_option_gallium_dump_vs();
 
-   if (!draw_get_option_use_llvm()) {
+   if (!draw->llvm) {
       draw->vs.tgsi.machine = tgsi_exec_machine_create();
       if (!draw->vs.tgsi.machine)
          return FALSE;
@@ -175,7 +175,7 @@ draw_vs_destroy( struct draw_context *draw )
    if (draw->vs.emit_cache)
       translate_cache_destroy(draw->vs.emit_cache);
 
-   if (!draw_get_option_use_llvm())
+   if (!draw->llvm)
       tgsi_exec_machine_destroy(draw->vs.tgsi.machine);
 }
 

src/gallium/auxiliary/draw/draw_vs_exec.c

@@ -63,7 +63,7 @@ vs_exec_prepare( struct draw_vertex_shader *shader,
 {
    struct exec_vertex_shader *evs = exec_vertex_shader(shader);
 
-   debug_assert(!draw_get_option_use_llvm());
+   debug_assert(!draw->llvm);
    /* Specify the vertex program to interpret/execute.
     * Avoid rebinding when possible.
     */
@@ -97,7 +97,7 @@ vs_exec_run_linear( struct draw_vertex_shader *shader,
    unsigned slot;
    boolean clamp_vertex_color = shader->draw->rasterizer->clamp_vertex_color;
 
-   debug_assert(!draw_get_option_use_llvm());
+   debug_assert(!shader->draw->llvm);
    tgsi_exec_set_constant_buffers(machine, PIPE_MAX_CONSTANT_BUFFERS,
                                   constants, const_size);
 

src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c

@@ -145,9 +145,6 @@ pipe_loader_sw_release(struct pipe_loader_device **dev)
 {
    struct pipe_loader_sw_device *sdev = pipe_loader_sw_device(*dev);
 
-   if (sdev->ws && sdev->ws->destroy)
-      sdev->ws->destroy(sdev->ws);
-
    if (sdev->lib)
       util_dl_close(sdev->lib);
 

src/gallium/auxiliary/tgsi/tgsi_strings.c

@@ -120,7 +120,8 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
    "FS_COORD_PIXEL_CENTER",
    "FS_COLOR0_WRITES_ALL_CBUFS",
    "FS_DEPTH_LAYOUT",
-   "VS_PROHIBIT_UCPS"
+   "VS_PROHIBIT_UCPS",
+   "GS_INVOCATIONS",
 };
 
 const char *tgsi_type_names[5] =

src/gallium/drivers/freedreno/Makefile.sources

@@ -3,6 +3,8 @@ C_SOURCES := \
 	freedreno_lowering.c \
 	freedreno_program.c \
 	freedreno_query.c \
+	freedreno_query_hw.c \
+	freedreno_query_sw.c \
 	freedreno_fence.c \
 	freedreno_resource.c \
 	freedreno_surface.c \
@@ -38,6 +40,7 @@ a3xx_SOURCES := \
 	a3xx/fd3_emit.c \
 	a3xx/fd3_gmem.c \
 	a3xx/fd3_program.c \
+	a3xx/fd3_query.c \
 	a3xx/fd3_rasterizer.c \
 	a3xx/fd3_screen.c \
 	a3xx/fd3_texture.c \

src/gallium/drivers/freedreno/a2xx/a2xx.xml.h

@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32840 bytes, from 2014-01-05 14:44:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9009 bytes, from 2014-01-11 16:56:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  12362 bytes, from 2014-01-07 14:47:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  56545 bytes, from 2014-02-26 16:32:11)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select {
 	SAMPLE_0123 = 6,
 };
 
+enum a2xx_rb_blend_opcode {
+	BLEND_DST_PLUS_SRC = 0,
+	BLEND_SRC_MINUS_DST = 1,
+	BLEND_MIN_DST_SRC = 2,
+	BLEND_MAX_DST_SRC = 3,
+	BLEND_DST_MINUS_SRC = 4,
+	BLEND_DST_PLUS_SRC_BIAS = 5,
+};
+
 enum adreno_mmu_clnt_beh {
 	BEH_NEVR = 0,
 	BEH_TRAN_RNG = 1,
@@ -996,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend
 }
 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0
 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)
+static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
 {
 	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
 }
@@ -1014,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend
 }
 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000
 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)
+static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
 {
 	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
 }

src/gallium/drivers/freedreno/a2xx/fd2_blend.c

@@ -34,6 +34,27 @@
 #include "fd2_context.h"
 #include "fd2_util.h"
 
+
+static enum a2xx_rb_blend_opcode
+blend_func(unsigned func)
+{
+	switch (func) {
+	case PIPE_BLEND_ADD:
+		return BLEND_DST_PLUS_SRC;
+	case PIPE_BLEND_MIN:
+		return BLEND_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return BLEND_MAX_DST_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return BLEND_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return BLEND_DST_MINUS_SRC;
+	default:
+		DBG("invalid blend func: %x", func);
+		return 0;
+	}
+}
+
 void *
 fd2_blend_state_create(struct pipe_context *pctx,
 		const struct pipe_blend_state *cso)
@@ -61,10 +82,10 @@ fd2_blend_state_create(struct pipe_context *pctx,
 
 	so->rb_blendcontrol =
 		A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(fd_blend_factor(rt->rgb_src_factor)) |
-		A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(fd_blend_func(rt->rgb_func)) |
+		A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) |
 		A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(fd_blend_factor(rt->rgb_dst_factor)) |
 		A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(fd_blend_factor(rt->alpha_src_factor)) |
-		A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(fd_blend_func(rt->alpha_func)) |
+		A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) |
 		A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(fd_blend_factor(rt->alpha_dst_factor));
 
 	if (rt->colormask & PIPE_MASK_R)

src/gallium/drivers/freedreno/a2xx/fd2_emit.c

@@ -125,7 +125,7 @@ emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
 {
 	unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id);
 	static const struct fd2_sampler_stateobj dummy_sampler = {};
-	struct fd2_sampler_stateobj *sampler;
+	const struct fd2_sampler_stateobj *sampler;
 	struct fd2_pipe_sampler_view *view;
 
 	if (emitted & (1 << const_idx))

src/gallium/drivers/freedreno/a3xx/a3xx.xml.h

@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32840 bytes, from 2014-01-05 14:44:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9009 bytes, from 2014-01-11 16:56:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  12362 bytes, from 2014-01-07 14:47:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  56545 bytes, from 2014-02-26 16:32:11)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -41,31 +41,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
 
-enum a3xx_render_mode {
-	RB_RENDERING_PASS = 0,
-	RB_TILING_PASS = 1,
-	RB_RESOLVE_PASS = 2,
-};
-
 enum a3xx_tile_mode {
 	LINEAR = 0,
 	TILE_32X32 = 2,
 };
 
-enum a3xx_threadmode {
-	MULTI = 0,
-	SINGLE = 1,
-};
-
-enum a3xx_instrbuffermode {
-	BUFFER = 1,
-};
-
-enum a3xx_threadsize {
-	TWO_QUADS = 0,
-	FOUR_QUADS = 1,
-};
-
 enum a3xx_state_block_id {
 	HLSQ_BLOCK_ID_TP_TEX = 2,
 	HLSQ_BLOCK_ID_TP_MIPMAP = 3,
@@ -180,12 +160,6 @@ enum a3xx_color_swap {
 	XYZW = 3,
 };
 
-enum a3xx_msaa_samples {
-	MSAA_ONE = 0,
-	MSAA_TWO = 1,
-	MSAA_FOUR = 2,
-};
-
 enum a3xx_sp_perfcounter_select {
 	SP_FS_CFLOW_INSTRUCTIONS = 12,
 	SP_FS_FULL_ALU_INSTRUCTIONS = 14,
@@ -212,21 +186,26 @@ enum a3xx_rop_code {
 	ROP_SET = 15,
 };
 
-enum adreno_rb_copy_control_mode {
+enum a3xx_rb_blend_opcode {
-	RB_COPY_RESOLVE = 1,
+	BLEND_DST_PLUS_SRC = 0,
-	RB_COPY_DEPTH_STENCIL = 5,
+	BLEND_SRC_MINUS_DST = 1,
+	BLEND_DST_MINUS_SRC = 2,
+	BLEND_MIN_DST_SRC = 3,
+	BLEND_MAX_DST_SRC = 4,
 };
 
 enum a3xx_tex_filter {
 	A3XX_TEX_NEAREST = 0,
 	A3XX_TEX_LINEAR = 1,
+	A3XX_TEX_ANISO = 2,
 };
 
 enum a3xx_tex_clamp {
 	A3XX_TEX_REPEAT = 0,
 	A3XX_TEX_CLAMP_TO_EDGE = 1,
 	A3XX_TEX_MIRROR_REPEAT = 2,
-	A3XX_TEX_CLAMP_NONE = 3,
+	A3XX_TEX_CLAMP_TO_BORDER = 3,
+	A3XX_TEX_MIRROR_CLAMP = 4,
 };
 
 enum a3xx_tex_swiz {
@@ -337,6 +316,7 @@ enum a3xx_tex_type {
 #define REG_A3XX_RBBM_INT_0_STATUS				0x00000064
 
 #define REG_A3XX_RBBM_PERFCTR_CTL				0x00000080
+#define A3XX_RBBM_PERFCTR_CTL_ENABLE				0x00000001
 
 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0				0x00000081
 
@@ -570,6 +550,10 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
 
 #define REG_A3XX_CP_AHB_FAULT					0x0000054d
 
+#define REG_A3XX_SP_GLOBAL_MEM_SIZE				0x00000e22
+
+#define REG_A3XX_SP_GLOBAL_MEM_ADDR				0x00000e23
+
 #define REG_A3XX_GRAS_CL_CLIP_CNTL				0x00002040
 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER			0x00001000
 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
@@ -644,8 +628,26 @@ static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
 }
 
 #define REG_A3XX_GRAS_SU_POINT_MINMAX				0x00002068
+#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
+#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
+static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
+{
+	return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
+}
+#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
+#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT			16
+static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
+{
+	return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
+}
 
 #define REG_A3XX_GRAS_SU_POINT_SIZE				0x00002069
+#define A3XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
+#define A3XX_GRAS_SU_POINT_SIZE__SHIFT				0
+static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
+{
+	return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
+}
 
 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE			0x0000206c
 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK		0x00ffffff
@@ -885,7 +887,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b
 }
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
 {
 	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
 }
@@ -903,7 +905,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb
 }
 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
 {
 	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
 }
@@ -986,12 +988,19 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples
 {
 	return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
 }
+#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR				0x00000008
 #define A3XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT			4
 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
 {
 	return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
 }
+#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00
+#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8
+static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
+{
+	return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
+}
 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000
 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14
 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
@@ -1034,6 +1043,12 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
 {
 	return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
 }
+#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
+#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT		10
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+	return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
+}
 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK		0x0003c000
 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT		14
 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
@@ -1074,7 +1089,7 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form
 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			11
 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 {
-	return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+	return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 }
 
 #define REG_A3XX_RB_DEPTH_PITCH					0x00002103
@@ -1202,6 +1217,8 @@ static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
 }
 
 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL			0x00002110
+#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET			0x00000001
+#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
 
 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR				0x00002111
 
@@ -1366,10 +1383,36 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
 }
 
 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG				0x0000220a
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK		0x00000003
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT		0
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
+{
+	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK		0x00000ffc
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT		2
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
+{
+	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK		0x003ff000
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT		12
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
+{
+	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
+}
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK		0xffc00000
+#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT		22
+static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
+{
+	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
+}
 
-#define REG_A3XX_HLSQ_CL_NDRANGE_1_REG				0x0000220b
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
 
-#define REG_A3XX_HLSQ_CL_NDRANGE_2_REG				0x0000220c
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
+
+static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
 
 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG				0x00002211
 
@@ -1377,7 +1420,9 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
 
 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG			0x00002214
 
-#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG			0x00002215
+static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
 
 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG			0x00002216
 
@@ -1492,6 +1537,12 @@ static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
 {
 	return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
 }
+#define A3XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
+#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT			22
+static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
+{
+	return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
+}
 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT			24
 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
@@ -1624,6 +1675,7 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
 }
 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE			0x00200000
 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x00400000
+#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE			0x00800000
 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK			0xff000000
 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT			24
 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
@@ -1797,6 +1849,7 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
 }
 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE			0x00200000
 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00400000
+#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE			0x00800000
 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK			0xff000000
 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT			24
 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
@@ -1976,6 +2029,42 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
 
 #define REG_A3XX_VBIF_OUT_AXI_AOOO				0x0000305f
 
+#define REG_A3XX_VBIF_PERF_CNT_EN				0x00003070
+#define A3XX_VBIF_PERF_CNT_EN_CNT0				0x00000001
+#define A3XX_VBIF_PERF_CNT_EN_CNT1				0x00000002
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0				0x00000004
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1				0x00000008
+#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2				0x00000010
+
+#define REG_A3XX_VBIF_PERF_CNT_CLR				0x00003071
+#define A3XX_VBIF_PERF_CNT_CLR_CNT0				0x00000001
+#define A3XX_VBIF_PERF_CNT_CLR_CNT1				0x00000002
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0				0x00000004
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1				0x00000008
+#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2				0x00000010
+
+#define REG_A3XX_VBIF_PERF_CNT_SEL				0x00003072
+
+#define REG_A3XX_VBIF_PERF_CNT0_LO				0x00003073
+
+#define REG_A3XX_VBIF_PERF_CNT0_HI				0x00003074
+
+#define REG_A3XX_VBIF_PERF_CNT1_LO				0x00003075
+
+#define REG_A3XX_VBIF_PERF_CNT1_HI				0x00003076
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO				0x00003077
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI				0x00003078
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO				0x00003079
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI				0x0000307a
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO				0x0000307b
+
+#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI				0x0000307c
+
 #define REG_A3XX_VSC_BIN_SIZE					0x00000c01
 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK				0x0000001f
 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
@@ -2249,6 +2338,12 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
 {
 	return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
 }
+#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK			0x00700000
+#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT			20
+static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
+{
+	return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
+}
 #define A3XX_TEX_SAMP_0_UNNORM_COORDS				0x80000000
 
 #define REG_A3XX_TEX_SAMP_1					0x00000001
@@ -2267,6 +2362,7 @@ static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
 
 #define REG_A3XX_TEX_CONST_0					0x00000000
 #define A3XX_TEX_CONST_0_TILED					0x00000001
+#define A3XX_TEX_CONST_0_SRGB					0x00000004
 #define A3XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT				4
 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
@@ -2303,6 +2399,7 @@ static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
 {
 	return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
 }
+#define A3XX_TEX_CONST_0_NOCONVERT				0x20000000
 #define A3XX_TEX_CONST_0_TYPE__MASK				0xc0000000
 #define A3XX_TEX_CONST_0_TYPE__SHIFT				30
 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)

src/gallium/drivers/freedreno/a3xx/fd3_blend.c

@@ -34,6 +34,27 @@
 #include "fd3_context.h"
 #include "fd3_util.h"
 
+
+static enum a3xx_rb_blend_opcode
+blend_func(unsigned func)
+{
+	switch (func) {
+	case PIPE_BLEND_ADD:
+		return BLEND_DST_PLUS_SRC;
+	case PIPE_BLEND_MIN:
+		return BLEND_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return BLEND_MAX_DST_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return BLEND_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return BLEND_DST_MINUS_SRC;
+	default:
+		DBG("invalid blend func: %x", func);
+		return 0;
+	}
+}
+
 void *
 fd3_blend_state_create(struct pipe_context *pctx,
 		const struct pipe_blend_state *cso)
@@ -80,10 +101,10 @@ fd3_blend_state_create(struct pipe_context *pctx,
 
 		so->rb_mrt[i].blend_control =
 				A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(fd_blend_factor(rt->rgb_src_factor)) |
-				A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(fd_blend_func(rt->rgb_func)) |
+				A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(blend_func(rt->rgb_func)) |
 				A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(fd_blend_factor(rt->rgb_dst_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(fd_blend_factor(rt->alpha_src_factor)) |
-				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(fd_blend_func(rt->alpha_func)) |
+				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(blend_func(rt->alpha_func)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(fd_blend_factor(rt->alpha_dst_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE;
 

src/gallium/drivers/freedreno/a3xx/fd3_compiler.c

@@ -1074,77 +1074,154 @@ trans_arl(const struct instr_translater *t,
 	add_src_reg(ctx, instr, tmp_src, chan)->flags |= IR3_REG_HALF;
 }
 
-/* texture fetch/sample instructions: */
+/*
-static void
+ * texture fetch/sample instructions:
-trans_samp(const struct instr_translater *t,
+ */
-		struct fd3_compile_context *ctx,
+
+struct tex_info {
+	int8_t order[4];
+	unsigned src_wrmask, flags;
+};
+
+static const struct tex_info *
+get_tex_info(struct fd3_compile_context *ctx,
 		struct tgsi_full_instruction *inst)
 {
-	struct ir3_instruction *instr;
+	static const struct tex_info tex1d = {
-	struct tgsi_src_register *coord = &inst->Src[0].Register;
+		.order = { 0, -1, -1, -1 },  /* coord.x */
-	struct tgsi_src_register *samp  = &inst->Src[1].Register;
+		.src_wrmask = TGSI_WRITEMASK_XY,
-	unsigned tex = inst->Texture.Texture;
+		.flags = 0,
-	int8_t *order;
+	};
-	unsigned i, flags = 0, src_wrmask;
+	static const struct tex_info tex1ds = {
-	bool needs_mov = false;
+		.order = { 0, -1,  2, -1 },  /* coord.xz */
+		.src_wrmask = TGSI_WRITEMASK_XYZ,
+		.flags = IR3_INSTR_S,
+	};
+	static const struct tex_info tex2d = {
+		.order = { 0,  1, -1, -1 },  /* coord.xy */
+		.src_wrmask = TGSI_WRITEMASK_XY,
+		.flags = 0,
+	};
+	static const struct tex_info tex2ds = {
+		.order = { 0,  1,  2, -1 },  /* coord.xyz */
+		.src_wrmask = TGSI_WRITEMASK_XYZ,
+		.flags = IR3_INSTR_S,
+	};
+	static const struct tex_info tex3d = {
+		.order = { 0,  1,  2, -1 },  /* coord.xyz */
+		.src_wrmask = TGSI_WRITEMASK_XYZ,
+		.flags = IR3_INSTR_3D,
+	};
+	static const struct tex_info tex3ds = {
+		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_S | IR3_INSTR_3D,
+	};
+	static const struct tex_info txp1d = {
+		.order = { 0, -1,  3, -1 },  /* coord.xw */
+		.src_wrmask = TGSI_WRITEMASK_XYZ,
+		.flags = IR3_INSTR_P,
+	};
+	static const struct tex_info txp1ds = {
+		.order = { 0, -1,  2,  3 },  /* coord.xzw */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_P | IR3_INSTR_S,
+	};
+	static const struct tex_info txp2d = {
+		.order = { 0,  1,  3, -1 },  /* coord.xyw */
+		.src_wrmask = TGSI_WRITEMASK_XYZ,
+		.flags = IR3_INSTR_P,
+	};
+	static const struct tex_info txp2ds = {
+		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_P | IR3_INSTR_S,
+	};
+	static const struct tex_info txp3d = {
+		.order = { 0,  1,  2,  3 },  /* coord.xyzw */
+		.src_wrmask = TGSI_WRITEMASK_XYZW,
+		.flags = IR3_INSTR_P | IR3_INSTR_3D,
+	};
 
-	switch (t->arg) {
+	unsigned tex = inst->Texture.Texture;
+
+	switch (inst->Instruction.Opcode) {
 	case TGSI_OPCODE_TEX:
 		switch (tex) {
+		case TGSI_TEXTURE_1D:
+			return &tex1d;
+		case TGSI_TEXTURE_SHADOW1D:
+			return &tex1ds;
 		case TGSI_TEXTURE_2D:
 		case TGSI_TEXTURE_RECT:
-			order = (int8_t[4]){ 0,  1, -1, -1 };
+			return &tex2d;
-			src_wrmask = TGSI_WRITEMASK_XY;
+		case TGSI_TEXTURE_SHADOW2D:
-			break;
+		case TGSI_TEXTURE_SHADOWRECT:
+			return &tex2ds;
 		case TGSI_TEXTURE_3D:
 		case TGSI_TEXTURE_CUBE:
-			order = (int8_t[4]){ 0,  1,  2, -1 };
+			return &tex3d;
-			src_wrmask = TGSI_WRITEMASK_XYZ;
+		case TGSI_TEXTURE_SHADOWCUBE:
-			flags |= IR3_INSTR_3D;
+			return &tex3ds;
-			break;
 		default:
 			compile_error(ctx, "unknown texture type: %s\n",
 					tgsi_texture_names[tex]);
-			break;
+			return NULL;
 		}
 		break;
 	case TGSI_OPCODE_TXP:
 		switch (tex) {
+		case TGSI_TEXTURE_1D:
+			return &txp1d;
+		case TGSI_TEXTURE_SHADOW1D:
+			return &txp1ds;
 		case TGSI_TEXTURE_2D:
 		case TGSI_TEXTURE_RECT:
-			order = (int8_t[4]){ 0,  1,  3, -1 };
+			return &txp2d;
-			src_wrmask = TGSI_WRITEMASK_XYZ;
+		case TGSI_TEXTURE_SHADOW2D:
-			break;
+		case TGSI_TEXTURE_SHADOWRECT:
+			return &txp2ds;
 		case TGSI_TEXTURE_3D:
 		case TGSI_TEXTURE_CUBE:
-			order = (int8_t[4]){ 0,  1,  2,  3 };
+			return &txp3d;
-			src_wrmask = TGSI_WRITEMASK_XYZW;
-			flags |= IR3_INSTR_3D;
-			break;
 		default:
 			compile_error(ctx, "unknown texture type: %s\n",
 					tgsi_texture_names[tex]);
 			break;
 		}
-		flags |= IR3_INSTR_P;
-		break;
-	default:
-		compile_assert(ctx, 0);
 		break;
 	}
+	compile_assert(ctx, 0);
+	return NULL;
+}
+
+static struct tgsi_src_register *
+get_tex_coord(struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst,
+		const struct tex_info *tinf)
+{
+	struct tgsi_src_register *coord = &inst->Src[0].Register;
+	struct ir3_instruction *instr;
+	unsigned tex = inst->Texture.Texture;
+	bool needs_mov = false;
+	unsigned i;
 
 	/* cat5 instruction cannot seem to handle const or relative: */
 	if (is_rel_or_const(coord))
 		needs_mov = true;
 
+	/* 1D textures we fix up w/ 0.0 as 2nd coord: */
+	if ((tex == TGSI_TEXTURE_1D) || (tex == TGSI_TEXTURE_SHADOW1D))
+		needs_mov = true;
+
 	/* The texture sample instructions need to coord in successive
 	 * registers/components (ie. src.xy but not src.yx).  And TXP
 	 * needs the .w component in .z for 2D..  so in some cases we
 	 * might need to emit some mov instructions to shuffle things
 	 * around:
 	 */
-	for (i = 1; (i < 4) && (order[i] >= 0) && !needs_mov; i++)
+	for (i = 1; (i < 4) && (tinf->order[i] >= 0) && !needs_mov; i++)
-		if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i]))
+		if (src_swiz(coord, i) != (src_swiz(coord, 0) + tinf->order[i]))
 			needs_mov = true;
 
 	if (needs_mov) {
@@ -1157,28 +1234,55 @@ trans_samp(const struct instr_translater *t,
 		/* need to move things around: */
 		tmp_src = get_internal_temp(ctx, &tmp_dst);
 
-		for (j = 0; (j < 4) && (order[j] >= 0); j++) {
+		for (j = 0; j < 4; j++) {
-			instr = instr_create(ctx, 1, 0);
+			if (tinf->order[j] < 0)
+				continue;
+			instr = instr_create(ctx, 1, 0);  /* mov */
 			instr->cat1.src_type = type_mov;
 			instr->cat1.dst_type = type_mov;
 			add_dst_reg(ctx, instr, &tmp_dst, j);
 			add_src_reg(ctx, instr, coord,
-					src_swiz(coord, order[j]));
+					src_swiz(coord, tinf->order[j]));
+		}
+
+		/* fix up .y coord: */
+		if ((tex == TGSI_TEXTURE_1D) ||
+				(tex == TGSI_TEXTURE_SHADOW1D)) {
+			instr = instr_create(ctx, 1, 0);  /* mov */
+			instr->cat1.src_type = type_mov;
+			instr->cat1.dst_type = type_mov;
+			add_dst_reg(ctx, instr, &tmp_dst, 1);  /* .y */
+			ir3_reg_create(instr, 0, IR3_REG_IMMED)->fim_val = 0.5;
 		}
 
 		coord = tmp_src;
 	}
 
+	return coord;
+}
+
+static void
+trans_samp(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_dst_register *dst = &inst->Dst[0].Register;
+	struct tgsi_src_register *coord;
+	struct tgsi_src_register *samp  = &inst->Src[1].Register;
+	const struct tex_info *tinf;
+
+	tinf = get_tex_info(ctx, inst);
+	coord = get_tex_coord(ctx, inst, tinf);
+
 	instr = instr_create(ctx, 5, t->opc);
 	instr->cat5.type = get_ftype(ctx);
 	instr->cat5.samp = samp->Index;
 	instr->cat5.tex  = samp->Index;
-	instr->flags |= flags;
+	instr->flags |= tinf->flags;
 
-	add_dst_reg_wrmask(ctx, instr, &inst->Dst[0].Register, 0,
+	add_dst_reg_wrmask(ctx, instr, dst, 0, dst->WriteMask);
-			inst->Dst[0].Register.WriteMask);
+	add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleX, tinf->src_wrmask);
-
-	add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleX, src_wrmask);
 }
 
 /*
@@ -1231,15 +1335,19 @@ trans_cmp(const struct instr_translater *t,
 
 	switch (t->tgsi_opc) {
 	case TGSI_OPCODE_SEQ:
+	case TGSI_OPCODE_FSEQ:
 		condition = IR3_COND_EQ;
 		break;
 	case TGSI_OPCODE_SNE:
+	case TGSI_OPCODE_FSNE:
 		condition = IR3_COND_NE;
 		break;
 	case TGSI_OPCODE_SGE:
+	case TGSI_OPCODE_FSGE:
 		condition = IR3_COND_GE;
 		break;
 	case TGSI_OPCODE_SLT:
+	case TGSI_OPCODE_FSLT:
 		condition = IR3_COND_LT;
 		break;
 	case TGSI_OPCODE_SLE:
@@ -1269,11 +1377,15 @@ trans_cmp(const struct instr_translater *t,
 
 	switch (t->tgsi_opc) {
 	case TGSI_OPCODE_SEQ:
+	case TGSI_OPCODE_FSEQ:
 	case TGSI_OPCODE_SGE:
+	case TGSI_OPCODE_FSGE:
 	case TGSI_OPCODE_SLE:
 	case TGSI_OPCODE_SNE:
+	case TGSI_OPCODE_FSNE:
 	case TGSI_OPCODE_SGT:
 	case TGSI_OPCODE_SLT:
+	case TGSI_OPCODE_FSLT:
 		/* cov.u16f16 dst, tmp0 */
 		instr = instr_create(ctx, 1, 0);
 		instr->cat1.src_type = get_utype(ctx);
@@ -1293,6 +1405,96 @@ trans_cmp(const struct instr_translater *t,
 	put_dst(ctx, inst, dst);
 }
 
+/*
+ * USNE(a,b) = (a != b) ? 1 : 0
+ *   cmps.u32.ne dst, a, b
+ *
+ * USEQ(a,b) = (a == b) ? 1 : 0
+ *   cmps.u32.eq dst, a, b
+ *
+ * ISGE(a,b) = (a > b) ? 1 : 0
+ *   cmps.s32.ge dst, a, b
+ *
+ * USGE(a,b) = (a > b) ? 1 : 0
+ *   cmps.u32.ge dst, a, b
+ *
+ * ISLT(a,b) = (a < b) ? 1 : 0
+ *   cmps.s32.lt dst, a, b
+ *
+ * USLT(a,b) = (a < b) ? 1 : 0
+ *   cmps.u32.lt dst, a, b
+ *
+ * UCMP(a,b,c) = (a < 0) ? b : c
+ *   cmps.u32.lt tmp0, a, {0}
+ *   sel.b16 dst, b, tmp0, c
+ */
+static void
+trans_icmp(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register constval0;
+	struct tgsi_src_register *a0, *a1, *a2;
+	unsigned condition;
+
+	a0 = &inst->Src[0].Register;  /* a */
+	a1 = &inst->Src[1].Register;  /* b */
+
+	switch (t->tgsi_opc) {
+	case TGSI_OPCODE_USNE:
+		condition = IR3_COND_NE;
+		break;
+	case TGSI_OPCODE_USEQ:
+		condition = IR3_COND_EQ;
+		break;
+	case TGSI_OPCODE_ISGE:
+	case TGSI_OPCODE_USGE:
+		condition = IR3_COND_GE;
+		break;
+	case TGSI_OPCODE_ISLT:
+	case TGSI_OPCODE_USLT:
+		condition = IR3_COND_LT;
+		break;
+	case TGSI_OPCODE_UCMP:
+		get_immediate(ctx, &constval0, 0);
+		a0 = &inst->Src[0].Register;  /* a */
+		a1 = &constval0;              /* {0} */
+		condition = IR3_COND_LT;
+		break;
+
+	default:
+		compile_assert(ctx, 0);
+		return;
+	}
+
+	if (is_const(a0) && is_const(a1))
+		a0 = get_unconst(ctx, a0);
+
+	if (t->tgsi_opc == TGSI_OPCODE_UCMP) {
+		struct tgsi_dst_register tmp_dst;
+		struct tgsi_src_register *tmp_src;
+		tmp_src = get_internal_temp(ctx, &tmp_dst);
+		/* cmps.u32.lt tmp, a0, a1 */
+		instr = instr_create(ctx, 2, t->opc);
+		instr->cat2.condition = condition;
+		vectorize(ctx, instr, &tmp_dst, 2, a0, 0, a1, 0);
+
+		a1 = &inst->Src[1].Register;
+		a2 = &inst->Src[2].Register;
+		/* sel.{b32,b16} dst, src2, tmp, src1 */
+		instr = instr_create(ctx, 3, OPC_SEL_B32);
+		vectorize(ctx, instr, dst, 3, a1, 0, tmp_src, 0, a2, 0);
+	} else {
+		/* cmps.{u32,s32}.<cond> dst, a0, a1 */
+		instr = instr_create(ctx, 2, t->opc);
+		instr->cat2.condition = condition;
+		vectorize(ctx, instr, dst, 2, a0, 0, a1, 0);
+	}
+	put_dst(ctx, inst, dst);
+}
+
 /*
  * Conditional / Flow control
  */
@@ -1533,7 +1735,7 @@ trans_endif(const struct instr_translater *t,
 }
 
 /*
- * Kill / Kill-if
+ * Kill
  */
 
 static void
@@ -1579,6 +1781,76 @@ trans_kill(const struct instr_translater *t,
 	ctx->kill[ctx->kill_count++] = instr;
 }
 
+/*
+ * Kill-If
+ */
+
+static void
+trans_killif(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct tgsi_src_register *src = &inst->Src[0].Register;
+	struct ir3_instruction *instr, *immed, *cond = NULL;
+	bool inv = false;
+
+	immed = create_immed(ctx, 0.0);
+
+	/* cmps.f.ne p0.x, cond, {0.0} */
+	instr = instr_create(ctx, 2, OPC_CMPS_F);
+	instr->cat2.condition = IR3_COND_NE;
+	ir3_reg_create(instr, regid(REG_P0, 0), 0);
+	ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = immed;
+	add_src_reg(ctx, instr, src, src->SwizzleX);
+
+	cond = instr;
+
+	/* kill p0.x */
+	instr = instr_create(ctx, 0, OPC_KILL);
+	instr->cat0.inv = inv;
+	ir3_reg_create(instr, 0, 0);  /* dummy dst */
+	ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = cond;
+
+	ctx->kill[ctx->kill_count++] = instr;
+
+}
+/*
+ * I2F / U2F / F2I / F2U
+ */
+
+static void
+trans_cov(const struct instr_translater *t,
+		struct fd3_compile_context *ctx,
+		struct tgsi_full_instruction *inst)
+{
+	struct ir3_instruction *instr;
+	struct tgsi_dst_register *dst = get_dst(ctx, inst);
+	struct tgsi_src_register *src = &inst->Src[0].Register;
+
+	// cov.f32s32 dst, tmp0 /
+	instr = instr_create(ctx, 1, 0);
+	switch (t->tgsi_opc) {
+	case TGSI_OPCODE_U2F:
+		instr->cat1.src_type = TYPE_U32;
+		instr->cat1.dst_type = TYPE_F32;
+		break;
+	case TGSI_OPCODE_I2F:
+		instr->cat1.src_type = TYPE_S32;
+		instr->cat1.dst_type = TYPE_F32;
+		break;
+	case TGSI_OPCODE_F2U:
+		instr->cat1.src_type = TYPE_F32;
+		instr->cat1.dst_type = TYPE_U32;
+		break;
+	case TGSI_OPCODE_F2I:
+		instr->cat1.src_type = TYPE_F32;
+		instr->cat1.dst_type = TYPE_S32;
+		break;
+
+	}
+	vectorize(ctx, instr, dst, 1, src, 0);
+}
+
 /*
  * Handlers for TGSI instructions which do have 1:1 mapping to native
  * instructions:
@@ -1616,9 +1888,11 @@ instr_cat2(const struct instr_translater *t,
 
 	switch (t->tgsi_opc) {
 	case TGSI_OPCODE_ABS:
+	case TGSI_OPCODE_IABS:
 		src0_flags = IR3_REG_ABS;
 		break;
 	case TGSI_OPCODE_SUB:
+	case TGSI_OPCODE_INEG:
 		src1_flags = IR3_REG_NEGATE;
 		break;
 	}
@@ -1724,6 +1998,22 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
 	INSTR(SUB,          instr_cat2, .opc = OPC_ADD_F),
 	INSTR(MIN,          instr_cat2, .opc = OPC_MIN_F),
 	INSTR(MAX,          instr_cat2, .opc = OPC_MAX_F),
+	INSTR(UADD,         instr_cat2, .opc = OPC_ADD_U),
+	INSTR(IMIN,         instr_cat2, .opc = OPC_MIN_S),
+	INSTR(UMIN,         instr_cat2, .opc = OPC_MIN_U),
+	INSTR(IMAX,         instr_cat2, .opc = OPC_MAX_S),
+	INSTR(UMAX,         instr_cat2, .opc = OPC_MAX_U),
+	INSTR(AND,          instr_cat2, .opc = OPC_AND_B),
+	INSTR(OR,           instr_cat2, .opc = OPC_OR_B),
+	INSTR(NOT,          instr_cat2, .opc = OPC_NOT_B),
+	INSTR(XOR,          instr_cat2, .opc = OPC_XOR_B),
+	INSTR(UMUL,         instr_cat2, .opc = OPC_MUL_U),
+	INSTR(SHL,          instr_cat2, .opc = OPC_SHL_B),
+	INSTR(USHR,         instr_cat2, .opc = OPC_SHR_B),
+	INSTR(ISHR,         instr_cat2, .opc = OPC_ASHR_B),
+	INSTR(IABS,         instr_cat2, .opc = OPC_ABSNEG_S),
+	INSTR(INEG,         instr_cat2, .opc = OPC_ABSNEG_S),
+	INSTR(AND,          instr_cat2, .opc = OPC_AND_B),
 	INSTR(MAD,          instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
 	INSTR(TRUNC,        instr_cat2, .opc = OPC_TRUNC_F),
 	INSTR(CLAMP,        trans_clamp),
@@ -1741,16 +2031,33 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
 	INSTR(TXP,          trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP),
 	INSTR(SGT,          trans_cmp),
 	INSTR(SLT,          trans_cmp),
+	INSTR(FSLT,         trans_cmp),
 	INSTR(SGE,          trans_cmp),
+	INSTR(FSGE,         trans_cmp),
 	INSTR(SLE,          trans_cmp),
 	INSTR(SNE,          trans_cmp),
+	INSTR(FSNE,         trans_cmp),
 	INSTR(SEQ,          trans_cmp),
+	INSTR(FSEQ,         trans_cmp),
 	INSTR(CMP,          trans_cmp),
+	INSTR(USNE,         trans_icmp, .opc = OPC_CMPS_U),
+	INSTR(USEQ,         trans_icmp, .opc = OPC_CMPS_U),
+	INSTR(ISGE,         trans_icmp, .opc = OPC_CMPS_S),
+	INSTR(USGE,         trans_icmp, .opc = OPC_CMPS_U),
+	INSTR(ISLT,         trans_icmp, .opc = OPC_CMPS_S),
+	INSTR(USLT,         trans_icmp, .opc = OPC_CMPS_U),
+	INSTR(UCMP,         trans_icmp, .opc = OPC_CMPS_U),
 	INSTR(IF,           trans_if),
+	INSTR(UIF,          trans_if),
 	INSTR(ELSE,         trans_else),
 	INSTR(ENDIF,        trans_endif),
 	INSTR(END,          instr_cat0, .opc = OPC_END),
 	INSTR(KILL,         trans_kill, .opc = OPC_KILL),
+	INSTR(KILL_IF,      trans_killif, .opc = OPC_KILL),
+	INSTR(I2F,          trans_cov),
+	INSTR(U2F,          trans_cov),
+	INSTR(F2I,          trans_cov),
+	INSTR(F2U,          trans_cov),
 };
 
 static fd3_semantic
@@ -1935,6 +2242,8 @@ decl_in(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 
 		DBG("decl in -> r%d", i);
 
+		compile_assert(ctx, n < ARRAY_SIZE(so->inputs));
+
 		so->inputs[n].semantic = decl_semantic(&decl->Semantic);
 		so->inputs[n].compmask = (1 << ncomp) - 1;
 		so->inputs[n].regid = r;
@@ -2024,6 +2333,8 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 
 		ncomp = 4;
 
+		compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
+
 		so->outputs[n].semantic = decl_semantic(&decl->Semantic);
 		so->outputs[n].regid = regid(i, comp);
 
@@ -2147,6 +2458,7 @@ compile_instructions(struct fd3_compile_context *ctx)
 			struct tgsi_full_immediate *imm =
 					&ctx->parser.FullToken.FullImmediate;
 			unsigned n = ctx->so->immediates_count++;
+			compile_assert(ctx, n < ARRAY_SIZE(ctx->so->immediates));
 			memcpy(ctx->so->immediates[n].val, imm->u, 16);
 			break;
 		}

src/gallium/drivers/freedreno/a3xx/fd3_compiler_old.c

@@ -1324,6 +1324,8 @@ decl_in(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 
 		DBG("decl in -> r%d", i + base);   // XXX
 
+		compile_assert(ctx, n < ARRAY_SIZE(so->inputs));
+
 		so->inputs[n].semantic = decl_semantic(&decl->Semantic);
 		so->inputs[n].compmask = (1 << ncomp) - 1;
 		so->inputs[n].ncomp = ncomp;
@@ -1410,6 +1412,7 @@ decl_out(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
 
 	for (i = decl->Range.First; i <= decl->Range.Last; i++) {
 		unsigned n = so->outputs_count++;
+		compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
 		so->outputs[n].semantic = decl_semantic(&decl->Semantic);
 		so->outputs[n].regid = regid(i + base, comp);
 	}

src/gallium/drivers/freedreno/a3xx/fd3_context.c

@@ -33,6 +33,7 @@
 #include "fd3_emit.h"
 #include "fd3_gmem.h"
 #include "fd3_program.h"
+#include "fd3_query.h"
 #include "fd3_rasterizer.h"
 #include "fd3_texture.h"
 #include "fd3_zsa.h"
@@ -134,5 +135,7 @@ fd3_context_create(struct pipe_screen *pscreen, void *priv)
 	fd3_ctx->solid_vbuf = create_solid_vertexbuf(pctx);
 	fd3_ctx->blit_texcoord_vbuf = create_blit_texcoord_vertexbuf(pctx);
 
+	fd3_query_context_init(pctx);
+
 	return pctx;
 }

src/gallium/drivers/freedreno/a3xx/fd3_emit.c

@@ -195,8 +195,10 @@ emit_textures(struct fd_ringbuffer *ring,
 		OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 				CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 		for (i = 0; i < tex->num_textures; i++) {
-			struct fd3_pipe_sampler_view *view =
+			static const struct fd3_pipe_sampler_view dummy_view = {};
-					fd3_pipe_sampler_view(tex->textures[i]);
+			const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+					fd3_pipe_sampler_view(tex->textures[i]) :
+					&dummy_view;
 			OUT_RING(ring, view->texconst0);
 			OUT_RING(ring, view->texconst1);
 			OUT_RING(ring, view->texconst2 |
@@ -213,8 +215,10 @@ emit_textures(struct fd_ringbuffer *ring,
 		OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 				CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 		for (i = 0; i < tex->num_textures; i++) {
-			struct fd3_pipe_sampler_view *view =
+			static const struct fd3_pipe_sampler_view dummy_view = {};
-					fd3_pipe_sampler_view(tex->textures[i]);
+			const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+					fd3_pipe_sampler_view(tex->textures[i]) :
+					&dummy_view;
 			struct fd_resource *rsc = view->tex_resource;
 
 			for (j = 0; j < view->mipaddrs; j++) {
@@ -323,9 +327,12 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 		if (vp->inputs[i].compmask) {
 			struct pipe_resource *prsc = vbufs[i].prsc;
 			struct fd_resource *rsc = fd_resource(prsc);
-			enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(vbufs[i].format);
+			enum pipe_format pfmt = vbufs[i].format;
+			enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
 			bool switchnext = (i != last);
-			uint32_t fs = util_format_get_blocksize(vbufs[i].format);
+			uint32_t fs = util_format_get_blocksize(pfmt);
+
+			debug_assert(fmt != ~0);
 
 			OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
 			OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
@@ -339,6 +346,7 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 			OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
 					A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
 					A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
+					A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
 					A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
 					A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
 					A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |

src/gallium/drivers/freedreno/a3xx/fd3_gmem.c

@@ -82,7 +82,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 				stride = bin_w * rsc->cpp;
 
 				if (bases) {
-					base = bases[i] * rsc->cpp;
+					base = bases[i];
 				}
 			} else {
 				stride = slice->pitch * rsc->cpp;
@@ -106,9 +106,17 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 }
 
 static uint32_t
-depth_base(struct fd_gmem_stateobj *gmem)
+depth_base(struct fd_context *ctx)
 {
-	return align(gmem->bin_w * gmem->bin_h, 0x4000);
+	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	uint32_t cpp = 4;
+	if (pfb->cbufs[0]) {
+		struct fd_resource *rsc =
+				fd_resource(pfb->cbufs[0]->texture);
+		cpp = rsc->cpp;
+	}
+	return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 }
 
 static bool
@@ -156,7 +164,7 @@ emit_binning_workaround(struct fd_context *ctx)
 	OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 			A3XX_RB_COPY_CONTROL_MODE(0) |
 			A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
-	OUT_RELOC(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
+	OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
 	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
 	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 			A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
@@ -399,12 +407,7 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 			}}, 1);
 
 	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
-		uint32_t base = 0;
+		uint32_t base = depth_base(ctx);
-		if (pfb->cbufs[0]) {
-			struct fd_resource *rsc =
-					fd_resource(pfb->cbufs[0]->texture);
-			base = depth_base(&ctx->gmem) * rsc->cpp;
-		}
 		emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 	}
 
@@ -458,7 +461,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 
 	OUT_PKT3(ring, CP_MEM_WRITE, 5);
-	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
+	OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 	OUT_RING(ring, fui(x0));
 	OUT_RING(ring, fui(y0));
 	OUT_RING(ring, fui(x1));
@@ -558,7 +561,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	bin_h = gmem->bin_h;
 
 	if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
-		emit_mem2gmem_surf(ctx, depth_base(gmem), pfb->zsbuf, bin_w);
+		emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);
 
 	if (ctx->restore & FD_BUFFER_COLOR)
 		emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
@@ -639,7 +642,7 @@ update_vsc_pipe(struct fd_context *ctx)
 	int i;
 
 	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
-	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
+	OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 
 	for (i = 0; i < 8; i++) {
 		struct fd_vsc_pipe *pipe = &ctx->pipe[i];
@@ -654,7 +657,7 @@ update_vsc_pipe(struct fd_context *ctx)
 				A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 				A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 				A3XX_VSC_PIPE_CONFIG_H(pipe->h));
-		OUT_RELOC(ring, pipe->bo, 0, 0, 0);        /* VSC_PIPE[i].DATA_ADDRESS */
+		OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
 		OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 	}
 }
@@ -789,6 +792,7 @@ fd3_emit_tile_init(struct fd_context *ctx)
 {
 	struct fd_ringbuffer *ring = ctx->ring;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	uint32_t rb_render_control;
 
 	fd3_emit_restore(ctx);
 
@@ -813,8 +817,10 @@ fd3_emit_tile_init(struct fd_context *ctx)
 		patch_draws(ctx, IGNORE_VISIBILITY);
 	}
 
-	patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
+	rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
-			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
+			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
+
+	patch_rbrc(ctx, rb_render_control);
 }
 
 /* before mem2gmem */
@@ -827,7 +833,7 @@ fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 	uint32_t reg;
 
 	OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
-	reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(gmem));
+	reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 	if (pfb->zsbuf) {
 		reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 	}

src/gallium/drivers/freedreno/a3xx/fd3_program.c

@@ -406,7 +406,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
 			A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 			A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
 
-	for (i = 0, j = -1; j < (int)fp->inputs_count; i++) {
+	for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
 		uint32_t reg = 0;
 
 		OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
@@ -428,7 +428,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
 		OUT_RING(ring, reg);
 	}
 
-	for (i = 0, j = -1; j < (int)fp->inputs_count; i++) {
+	for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
 		uint32_t reg = 0;
 
 		OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);

src/gallium/drivers/freedreno/a3xx/fd3_program.h

@@ -91,7 +91,7 @@ struct fd3_shader_variant {
 	struct {
 		fd3_semantic semantic;
 		uint8_t regid;
-	} outputs[16];
+	} outputs[16 + 2];  /* +POSITION +PSIZE */
 	bool writes_pos, writes_psize;
 
 	/* vertices/inputs: */
@@ -104,7 +104,7 @@ struct fd3_shader_variant {
 		/* in theory inloc of fs should match outloc of vs: */
 		uint8_t inloc;
 		uint8_t bary;
-	} inputs[16];
+	} inputs[16 + 2];  /* +POSITION +FACE */
 
 	unsigned total_in;       /* sum of inputs (scalar) */
 

src/gallium/drivers/freedreno/a3xx/fd3_query.c

@@ -0,0 +1,139 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#include "freedreno_query_hw.h"
+#include "freedreno_context.h"
+#include "freedreno_util.h"
+
+#include "fd3_query.h"
+#include "fd3_util.h"
+
+
+struct fd_rb_samp_ctrs {
+	uint64_t ctr[16];
+};
+
+/*
+ * Occlusion Query:
+ *
+ * OCCLUSION_COUNTER and OCCLUSION_PREDICATE differ only in how they
+ * interpret results
+ */
+
+static struct fd_hw_sample *
+occlusion_get_sample(struct fd_context *ctx, struct fd_ringbuffer *ring)
+{
+	struct fd_hw_sample *samp =
+			fd_hw_sample_init(ctx, sizeof(struct fd_rb_samp_ctrs));
+
+	/* Set RB_SAMPLE_COUNT_ADDR to samp->offset plus value of
+	 * HW_QUERY_BASE_REG register:
+	 */
+	OUT_PKT3(ring, CP_SET_CONSTANT, 3);
+	OUT_RING(ring, CP_REG(REG_A3XX_RB_SAMPLE_COUNT_ADDR) | 0x80000000);
+	OUT_RING(ring, HW_QUERY_BASE_REG);
+	OUT_RING(ring, samp->offset);
+
+	OUT_PKT0(ring, REG_A3XX_RB_SAMPLE_COUNT_CONTROL, 1);
+	OUT_RING(ring, A3XX_RB_SAMPLE_COUNT_CONTROL_COPY);
+
+	OUT_PKT3(ring, CP_DRAW_INDX, 3);
+	OUT_RING(ring, 0x00000000);
+	OUT_RING(ring, DRAW(DI_PT_POINTLIST_A2XX, DI_SRC_SEL_AUTO_INDEX,
+			INDEX_SIZE_IGN, USE_VISIBILITY));
+	OUT_RING(ring, 0);             /* NumIndices */
+
+	OUT_PKT3(ring, CP_EVENT_WRITE, 1);
+	OUT_RING(ring, ZPASS_DONE);
+
+	OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1);
+	OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);
+
+	OUT_PKT0(ring, REG_A3XX_VBIF_PERF_CNT_EN, 1);
+	OUT_RING(ring, A3XX_VBIF_PERF_CNT_EN_CNT0 |
+			A3XX_VBIF_PERF_CNT_EN_CNT1 |
+			A3XX_VBIF_PERF_CNT_EN_PWRCNT0 |
+			A3XX_VBIF_PERF_CNT_EN_PWRCNT1 |
+			A3XX_VBIF_PERF_CNT_EN_PWRCNT2);
+
+	return samp;
+}
+
+static uint64_t
+count_samples(const struct fd_rb_samp_ctrs *start,
+		const struct fd_rb_samp_ctrs *end)
+{
+	uint64_t n = 0;
+	unsigned i;
+
+	/* not quite sure what all of these are, possibly different
+	 * counters for each MRT render target:
+	 */
+	for (i = 0; i < 16; i += 4)
+		n += end->ctr[i] - start->ctr[i];
+
+	return n;
+}
+
+static void
+occlusion_counter_accumulate_result(struct fd_context *ctx,
+		const void *start, const void *end,
+		union pipe_query_result *result)
+{
+	uint64_t n = count_samples(start, end);
+	result->u64 += n;
+}
+
+static void
+occlusion_predicate_accumulate_result(struct fd_context *ctx,
+		const void *start, const void *end,
+		union pipe_query_result *result)
+{
+	uint64_t n = count_samples(start, end);
+	result->b |= (n > 0);
+}
+
+static const struct fd_hw_sample_provider occlusion_counter = {
+		.query_type = PIPE_QUERY_OCCLUSION_COUNTER,
+		.active = FD_STAGE_DRAW, /* | FD_STAGE_CLEAR ??? */
+		.get_sample = occlusion_get_sample,
+		.accumulate_result = occlusion_counter_accumulate_result,
+};
+
+static const struct fd_hw_sample_provider occlusion_predicate = {
+		.query_type = PIPE_QUERY_OCCLUSION_PREDICATE,
+		.active = FD_STAGE_DRAW, /* | FD_STAGE_CLEAR ??? */
+		.get_sample = occlusion_get_sample,
+		.accumulate_result = occlusion_predicate_accumulate_result,
+};
+
+void fd3_query_context_init(struct pipe_context *pctx)
+{
+	fd_hw_query_register_provider(pctx, &occlusion_counter);
+	fd_hw_query_register_provider(pctx, &occlusion_predicate);
+}

src/gallium/drivers/freedreno/a3xx/fd3_query.h

@@ -0,0 +1,36 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#ifndef FD3_QUERY_H_
+#define FD3_QUERY_H_
+
+#include "pipe/p_context.h"
+
+void fd3_query_context_init(struct pipe_context *pctx);
+
+#endif /* FD3_QUERY_H_ */

src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c

@@ -40,6 +40,7 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
 		const struct pipe_rasterizer_state *cso)
 {
 	struct fd3_rasterizer_stateobj *so;
+	float psize_min, psize_max;
 
 	so = CALLOC_STRUCT(fd3_rasterizer_stateobj);
 	if (!so)
@@ -47,19 +48,28 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
 
 	so->base = *cso;
 
+	if (cso->point_size_per_vertex) {
+		psize_min = util_get_min_point_size(cso);
+		psize_max = 8192;
+	} else {
+		/* Force the point size to be as if the vertex output was disabled. */
+		psize_min = cso->point_size;
+		psize_max = cso->point_size;
+	}
+
 /*
 	if (cso->line_stipple_enable) {
 		??? TODO line stipple
 	}
 	TODO cso->half_pixel_center
-	TODO cso->point_size
-	TODO psize_min/psize_max
 	if (cso->multisample)
 		TODO
 */
 	so->gras_cl_clip_cntl = A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER; /* ??? */
-	so->gras_su_point_minmax = 0xffc00010;  /* ??? */
+	so->gras_su_point_minmax =
-	so->gras_su_point_size   = 0x00000008;  /* ??? */
+			A3XX_GRAS_SU_POINT_MINMAX_MIN(psize_min/2) |
+			A3XX_GRAS_SU_POINT_MINMAX_MAX(psize_max/2);
+	so->gras_su_point_size   = A3XX_GRAS_SU_POINT_SIZE(cso->point_size/2);
 	so->gras_su_poly_offset_scale =
 			A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(cso->offset_scale);
 	so->gras_su_poly_offset_offset =

src/gallium/drivers/freedreno/a3xx/fd3_texture.c

@@ -30,6 +30,7 @@
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
+#include "util/u_format.h"
 
 #include "fd3_texture.h"
 #include "fd3_util.h"
@@ -47,12 +48,14 @@ tex_clamp(unsigned wrap)
 	case PIPE_TEX_WRAP_REPEAT:
 		return A3XX_TEX_REPEAT;
 	case PIPE_TEX_WRAP_CLAMP:
-	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 		return A3XX_TEX_CLAMP_TO_EDGE;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return A3XX_TEX_CLAMP_TO_BORDER;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP:
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return A3XX_TEX_MIRROR_CLAMP;
 	case PIPE_TEX_WRAP_MIRROR_REPEAT:
 		return A3XX_TEX_MIRROR_REPEAT;
 	default:
@@ -99,6 +102,9 @@ fd3_sampler_state_create(struct pipe_context *pctx,
 			A3XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t)) |
 			A3XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r));
 
+	if (cso->compare_mode)
+		so->texsamp0 |= A3XX_TEX_SAMP_0_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
+
 	if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 		so->texsamp1 =
 				A3XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
@@ -158,6 +164,10 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 			A3XX_TEX_CONST_0_MIPLVLS(miplevels) |
 			fd3_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
 						cso->swizzle_b, cso->swizzle_a);
+
+	if (util_format_is_srgb(cso->format))
+		so->texconst0 |= A3XX_TEX_CONST_0_SRGB;
+
 	so->texconst1 =
 			A3XX_TEX_CONST_1_FETCHSIZE(fd3_pipe2fetchsize(cso->format)) |
 			A3XX_TEX_CONST_1_WIDTH(prsc->width0) |

src/gallium/drivers/freedreno/a3xx/fd3_util.c

@@ -37,70 +37,44 @@ fd3_pipe2vtx(enum pipe_format format)
 {
 	switch (format) {
 	/* 8-bit buffers. */
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
 	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
 		return VFMT_NORM_UBYTE_8;
 
-	case PIPE_FORMAT_A8_SNORM:
-	case PIPE_FORMAT_I8_SNORM:
-	case PIPE_FORMAT_L8_SNORM:
 	case PIPE_FORMAT_R8_SNORM:
 		return VFMT_NORM_BYTE_8;
 
-	case PIPE_FORMAT_A8_UINT:
-	case PIPE_FORMAT_I8_UINT:
-	case PIPE_FORMAT_L8_UINT:
 	case PIPE_FORMAT_R8_UINT:
 		return VFMT_UBYTE_8;
 
-	case PIPE_FORMAT_A8_SINT:
-	case PIPE_FORMAT_I8_SINT:
-	case PIPE_FORMAT_L8_SINT:
 	case PIPE_FORMAT_R8_SINT:
 		return VFMT_BYTE_8;
 
 	/* 16-bit buffers. */
 	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_A16_UNORM:
-	case PIPE_FORMAT_L16_UNORM:
-	case PIPE_FORMAT_I16_UNORM:
 	case PIPE_FORMAT_Z16_UNORM:
 		return VFMT_NORM_USHORT_16;
 
 	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_A16_SNORM:
-	case PIPE_FORMAT_L16_SNORM:
-	case PIPE_FORMAT_I16_SNORM:
 		return VFMT_NORM_SHORT_16;
 
 	case PIPE_FORMAT_R16_UINT:
-	case PIPE_FORMAT_A16_UINT:
-	case PIPE_FORMAT_L16_UINT:
-	case PIPE_FORMAT_I16_UINT:
 		return VFMT_USHORT_16;
 
 	case PIPE_FORMAT_R16_SINT:
-	case PIPE_FORMAT_A16_SINT:
-	case PIPE_FORMAT_L16_SINT:
-	case PIPE_FORMAT_I16_SINT:
 		return VFMT_SHORT_16;
 
-	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_R16_FLOAT:
+		return VFMT_FLOAT_16;
+
 	case PIPE_FORMAT_R8G8_UNORM:
 		return VFMT_NORM_UBYTE_8_8;
 
-	case PIPE_FORMAT_L8A8_SNORM:
 	case PIPE_FORMAT_R8G8_SNORM:
 		return VFMT_NORM_BYTE_8_8;
 
-	case PIPE_FORMAT_L8A8_UINT:
 	case PIPE_FORMAT_R8G8_UINT:
 		return VFMT_UBYTE_8_8;
 
-	case PIPE_FORMAT_L8A8_SINT:
 	case PIPE_FORMAT_R8G8_SINT:
 		return VFMT_BYTE_8_8;
 
@@ -121,42 +95,62 @@ fd3_pipe2vtx(enum pipe_format format)
 	case PIPE_FORMAT_A8B8G8R8_UNORM:
 	case PIPE_FORMAT_A8R8G8B8_UNORM:
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
 	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
 		return VFMT_NORM_UBYTE_8_8_8_8;
 
 	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8X8_SNORM:
 		return VFMT_NORM_BYTE_8_8_8_8;
 
 	case PIPE_FORMAT_R8G8B8A8_UINT:
-	case PIPE_FORMAT_R8G8B8X8_UINT:
 		return VFMT_UBYTE_8_8_8_8;
 
 	case PIPE_FORMAT_R8G8B8A8_SINT:
-	case PIPE_FORMAT_R8G8B8X8_SINT:
 		return VFMT_BYTE_8_8_8_8;
 
-/* TODO probably need gles3 blob drivers to find the 32bit int formats:
+	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R32_UINT:
+		return VFMT_SHORT_16_16;
-	case PIPE_FORMAT_R32_SINT:
+
-	case PIPE_FORMAT_A32_UINT:
+	case PIPE_FORMAT_R16G16_FLOAT:
-	case PIPE_FORMAT_A32_SINT:
+		return VFMT_FLOAT_16_16;
-	case PIPE_FORMAT_L32_UINT:
+
-	case PIPE_FORMAT_L32_SINT:
+	case PIPE_FORMAT_R16G16_UINT:
-	case PIPE_FORMAT_I32_UINT:
+		return VFMT_USHORT_16_16;
-	case PIPE_FORMAT_I32_SINT:
+
-*/
+	case PIPE_FORMAT_R16G16_UNORM:
+		return VFMT_NORM_USHORT_16_16;
+
+	case PIPE_FORMAT_R16G16_SNORM:
+		return VFMT_NORM_SHORT_16_16;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+		return VFMT_NORM_UINT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_SNORM:
+		return VFMT_NORM_INT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_USCALED:
+		return VFMT_UINT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_SSCALED:
+		return VFMT_INT_10_10_10_2;
+
+	/* 48-bit buffers. */
+	case PIPE_FORMAT_R16G16B16_FLOAT:
+		return VFMT_FLOAT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_SSCALED:
+		return VFMT_SHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_UINT:
+		return VFMT_USHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_SNORM:
+		return VFMT_NORM_SHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_UNORM:
+		return VFMT_NORM_USHORT_16_16_16;
 
 	case PIPE_FORMAT_R32_FLOAT:
-	case PIPE_FORMAT_A32_FLOAT:
-	case PIPE_FORMAT_L32_FLOAT:
-	case PIPE_FORMAT_I32_FLOAT:
 	case PIPE_FORMAT_Z32_FLOAT:
 		return VFMT_FLOAT_32;
 
@@ -177,23 +171,14 @@ fd3_pipe2vtx(enum pipe_format format)
 		return VFMT_SHORT_16_16_16_16;
 
 	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_L32A32_FLOAT:
 		return VFMT_FLOAT_32_32;
 
 	case PIPE_FORMAT_R32G32_FIXED:
 		return VFMT_FIXED_32_32;
 
 	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-	case PIPE_FORMAT_R16G16B16X16_FLOAT:
 		return VFMT_FLOAT_16_16_16_16;
 
-/* TODO probably need gles3 blob drivers to find the 32bit int formats:
-	case PIPE_FORMAT_R32G32_SINT:
-	case PIPE_FORMAT_R32G32_UINT:
-	case PIPE_FORMAT_L32A32_UINT:
-	case PIPE_FORMAT_L32A32_SINT:
-*/
-
 	/* 96-bit buffers. */
 	case PIPE_FORMAT_R32G32B32_FLOAT:
 		return VFMT_FLOAT_32_32_32;
@@ -203,7 +188,6 @@ fd3_pipe2vtx(enum pipe_format format)
 
 	/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-	case PIPE_FORMAT_R32G32B32X32_FLOAT:
 		return VFMT_FLOAT_32_32_32_32;
 
 	case PIPE_FORMAT_R32G32B32A32_FIXED:
@@ -214,6 +198,20 @@ fd3_pipe2vtx(enum pipe_format format)
 	case PIPE_FORMAT_R32G32B32A32_UNORM:
 	case PIPE_FORMAT_R32G32B32A32_SINT:
 	case PIPE_FORMAT_R32G32B32A32_UINT:
+
+	case PIPE_FORMAT_R32_UINT:
+	case PIPE_FORMAT_R32_SINT:
+	case PIPE_FORMAT_A32_UINT:
+	case PIPE_FORMAT_A32_SINT:
+	case PIPE_FORMAT_L32_UINT:
+	case PIPE_FORMAT_L32_SINT:
+	case PIPE_FORMAT_I32_UINT:
+	case PIPE_FORMAT_I32_SINT:
+
+	case PIPE_FORMAT_R32G32_SINT:
+	case PIPE_FORMAT_R32G32_UINT:
+	case PIPE_FORMAT_L32A32_UINT:
+	case PIPE_FORMAT_L32A32_SINT:
 */
 
 	default:
@@ -235,6 +233,10 @@ fd3_pipe2tex(enum pipe_format format)
 	case PIPE_FORMAT_B8G8R8X8_UNORM:
 	case PIPE_FORMAT_R8G8B8A8_UNORM:
 	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8X8_SRGB:
+	case PIPE_FORMAT_R8G8B8A8_SRGB:
+	case PIPE_FORMAT_R8G8B8X8_SRGB:
 		return TFMT_NORM_UINT_8_8_8_8;
 
 	case PIPE_FORMAT_Z24X8_UNORM:
@@ -275,6 +277,12 @@ fd3_pipe2fetchsize(enum pipe_format format)
 
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
 	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8X8_SRGB:
+	case PIPE_FORMAT_R8G8B8A8_SRGB:
+	case PIPE_FORMAT_R8G8B8X8_SRGB:
 	case PIPE_FORMAT_Z24X8_UNORM:
 	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 		return TFETCH_4_BYTE;
@@ -348,8 +356,22 @@ fd3_pipe2swap(enum pipe_format format)
 	switch (format) {
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
 	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8X8_SRGB:
 		return WXYZ;
 
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_SRGB:
+	case PIPE_FORMAT_X8R8G8B8_SRGB:
+		return ZYXW;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_X8B8G8R8_SRGB:
+		return XYZW;
+
 	case PIPE_FORMAT_R8G8B8A8_UNORM:
 	case PIPE_FORMAT_R8G8B8X8_UNORM:
 	case PIPE_FORMAT_Z24X8_UNORM:
@@ -379,14 +401,14 @@ fd3_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
 {
 	const struct util_format_description *desc =
 			util_format_description(format);
-	uint8_t swiz[] = {
+	unsigned char swiz[4] = {
 			swizzle_r, swizzle_g, swizzle_b, swizzle_a,
-			PIPE_SWIZZLE_ZERO, PIPE_SWIZZLE_ONE,
+	}, rswiz[4];
-			PIPE_SWIZZLE_ONE, PIPE_SWIZZLE_ONE,
-	};
 
-	return A3XX_TEX_CONST_0_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) |
+	util_format_compose_swizzles(desc->swizzle, swiz, rswiz);
-			A3XX_TEX_CONST_0_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) |
+
-			A3XX_TEX_CONST_0_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) |
+	return A3XX_TEX_CONST_0_SWIZ_X(tex_swiz(rswiz[0])) |
-			A3XX_TEX_CONST_0_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]]));
+			A3XX_TEX_CONST_0_SWIZ_Y(tex_swiz(rswiz[1])) |
+			A3XX_TEX_CONST_0_SWIZ_Z(tex_swiz(rswiz[2])) |
+			A3XX_TEX_CONST_0_SWIZ_W(tex_swiz(rswiz[3]));
 }

src/gallium/drivers/freedreno/adreno_common.xml.h

@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32840 bytes, from 2014-01-05 14:44:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9009 bytes, from 2014-01-11 16:56:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  12362 bytes, from 2014-01-07 14:47:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  56545 bytes, from 2014-02-26 16:32:11)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -87,15 +87,6 @@ enum adreno_rb_blend_factor {
 	FACTOR_SRC_ALPHA_SATURATE = 16,
 };
 
-enum adreno_rb_blend_opcode {
-	BLEND_DST_PLUS_SRC = 0,
-	BLEND_SRC_MINUS_DST = 1,
-	BLEND_MIN_DST_SRC = 2,
-	BLEND_MAX_DST_SRC = 3,
-	BLEND_DST_MINUS_SRC = 4,
-	BLEND_DST_PLUS_SRC_BIAS = 5,
-};
-
 enum adreno_rb_surface_endian {
 	ENDIAN_NONE = 0,
 	ENDIAN_8IN16 = 1,
@@ -116,6 +107,39 @@ enum adreno_rb_depth_format {
 	DEPTHX_24_8 = 1,
 };
 
+enum adreno_rb_copy_control_mode {
+	RB_COPY_RESOLVE = 1,
+	RB_COPY_CLEAR = 2,
+	RB_COPY_DEPTH_STENCIL = 5,
+};
+
+enum a3xx_render_mode {
+	RB_RENDERING_PASS = 0,
+	RB_TILING_PASS = 1,
+	RB_RESOLVE_PASS = 2,
+	RB_COMPUTE_PASS = 3,
+};
+
+enum a3xx_msaa_samples {
+	MSAA_ONE = 0,
+	MSAA_TWO = 1,
+	MSAA_FOUR = 2,
+};
+
+enum a3xx_threadmode {
+	MULTI = 0,
+	SINGLE = 1,
+};
+
+enum a3xx_instrbuffermode {
+	BUFFER = 1,
+};
+
+enum a3xx_threadsize {
+	TWO_QUADS = 0,
+	FOUR_QUADS = 1,
+};
+
 #define REG_AXXX_CP_RB_BASE					0x000001c0
 
 #define REG_AXXX_CP_RB_CNTL					0x000001c1

src/gallium/drivers/freedreno/adreno_pm4.xml.h

@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32840 bytes, from 2014-01-05 14:44:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9009 bytes, from 2014-01-11 16:56:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  12362 bytes, from 2014-01-07 14:47:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  56545 bytes, from 2014-02-26 16:32:11)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -164,6 +164,11 @@ enum adreno_pm4_type3_packets {
 	CP_SET_BIN = 76,
 	CP_TEST_TWO_MEMS = 113,
 	CP_WAIT_FOR_ME = 19,
+	CP_SET_DRAW_STATE = 67,
+	CP_DRAW_INDX_OFFSET = 56,
+	CP_DRAW_INDIRECT = 40,
+	CP_DRAW_INDX_INDIRECT = 41,
+	CP_DRAW_AUTO = 36,
 	IN_IB_PREFETCH_END = 23,
 	IN_SUBBLK_PREFETCH = 31,
 	IN_INSTR_PREFETCH = 32,
@@ -351,6 +356,93 @@ static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 }
 
+#define REG_CP_DRAW_INDX_OFFSET_0				0x00000000
+#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f
+#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
+}
+#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0
+#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
+}
+#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK			0x00000700
+#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT			8
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
+}
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000800
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			11
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
+}
+#define CP_DRAW_INDX_OFFSET_0_NOT_EOP				0x00001000
+#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX			0x00002000
+#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE		0x00004000
+#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK			0xffff0000
+#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT		16
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
+}
+
+#define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
+
+#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
+#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff
+#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0
+static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
+}
+
+#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
+#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK			0xffffffff
+#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT			0
+static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
+}
+
+#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
+#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK			0xffffffff
+#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT			0
+static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
+{
+	return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
+}
+
+#define REG_CP_SET_DRAW_STATE_0					0x00000000
+#define CP_SET_DRAW_STATE_0_COUNT__MASK				0x0000ffff
+#define CP_SET_DRAW_STATE_0_COUNT__SHIFT			0
+static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
+{
+	return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
+}
+#define CP_SET_DRAW_STATE_0_DIRTY				0x00010000
+#define CP_SET_DRAW_STATE_0_DISABLE				0x00020000
+#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS			0x00040000
+#define CP_SET_DRAW_STATE_0_LOAD_IMMED				0x00080000
+#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK			0x1f000000
+#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT			24
+static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
+{
+	return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
+}
+
+#define REG_CP_SET_DRAW_STATE_1					0x00000001
+#define CP_SET_DRAW_STATE_1_ADDR__MASK				0xffffffff
+#define CP_SET_DRAW_STATE_1_ADDR__SHIFT				0
+static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
+{
+	return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
+}
+
 #define REG_CP_SET_BIN_0					0x00000000
 
 #define REG_CP_SET_BIN_1					0x00000001

src/gallium/drivers/freedreno/freedreno_context.c

@@ -34,6 +34,7 @@
 #include "freedreno_state.h"
 #include "freedreno_gmem.h"
 #include "freedreno_query.h"
+#include "freedreno_query_hw.h"
 #include "freedreno_util.h"
 
 static struct fd_ringbuffer *next_rb(struct fd_context *ctx)
@@ -145,6 +146,7 @@ fd_context_destroy(struct pipe_context *pctx)
 	DBG("");
 
 	fd_prog_fini(pctx);
+	fd_hw_query_fini(pctx);
 
 	util_slab_destroy(&ctx->transfer_pool);
 
@@ -221,6 +223,7 @@ fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen,
 	fd_query_context_init(pctx);
 	fd_texture_init(pctx);
 	fd_state_init(pctx);
+	fd_hw_query_init(pctx);
 
 	ctx->blitter = util_blitter_create(pctx);
 	if (!ctx->blitter)

src/gallium/drivers/freedreno/freedreno_context.h

@@ -33,6 +33,7 @@
 #include "pipe/p_context.h"
 #include "indices/u_primconvert.h"
 #include "util/u_blitter.h"
+#include "util/u_double_list.h"
 #include "util/u_slab.h"
 #include "util/u_string.h"
 
@@ -82,16 +83,80 @@ struct fd_vertex_stateobj {
 	unsigned num_elements;
 };
 
+/* Bitmask of stages in rendering that a particular query query is
+ * active.  Queries will be automatically started/stopped (generating
+ * additional fd_hw_sample_period's) on entrance/exit from stages that
+ * are applicable to the query.
+ *
+ * NOTE: set the stage to NULL at end of IB to ensure no query is still
+ * active.  Things aren't going to work out the way you want if a query
+ * is active across IB's (or between tile IB and draw IB)
+ */
+enum fd_render_stage {
+	FD_STAGE_NULL     = 0x00,
+	FD_STAGE_DRAW     = 0x01,
+	FD_STAGE_CLEAR    = 0x02,
+	/* TODO before queries which include MEM2GMEM or GMEM2MEM will
+	 * work we will need to call fd_hw_query_prepare() from somewhere
+	 * appropriate so that queries in the tiling IB get backed with
+	 * memory to write results to.
+	 */
+	FD_STAGE_MEM2GMEM = 0x04,
+	FD_STAGE_GMEM2MEM = 0x08,
+	/* used for driver internal draws (ie. util_blitter_blit()): */
+	FD_STAGE_BLIT     = 0x10,
+};
+
+#define MAX_HW_SAMPLE_PROVIDERS 4
+struct fd_hw_sample_provider;
+struct fd_hw_sample;
+
 struct fd_context {
 	struct pipe_context base;
 
 	struct fd_device *dev;
 	struct fd_screen *screen;
+
 	struct blitter_context *blitter;
 	struct primconvert_context *primconvert;
 
+	/* slab for pipe_transfer allocations: */
 	struct util_slab_mempool transfer_pool;
 
+	/* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
+	struct util_slab_mempool sample_pool;
+	struct util_slab_mempool sample_period_pool;
+
+	/* next sample offset.. incremented for each sample in the batch/
+	 * submit, reset to zero on next submit.
+	 */
+	uint32_t next_sample_offset;
+
+	/* sample-providers for hw queries: */
+	const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
+
+	/* cached samples (in case multiple queries need to reference
+	 * the same sample snapshot)
+	 */
+	struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
+
+	/* tracking for current stage, to know when to start/stop
+	 * any active queries:
+	 */
+	enum fd_render_stage stage;
+
+	/* list of active queries: */
+	struct list_head active_queries;
+
+	/* list of queries that are not active, but were active in the
+	 * current submit:
+	 */
+	struct list_head current_queries;
+
+	/* current query result bo and tile stride: */
+	struct fd_bo *query_bo;
+	uint32_t query_tile_stride;
+
 	/* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
 	 * DI_PT_x value to use for draw initiator.  There are some
 	 * slight differences between generation:

src/gallium/drivers/freedreno/freedreno_draw.c

@@ -36,6 +36,7 @@
 #include "freedreno_context.h"
 #include "freedreno_state.h"
 #include "freedreno_resource.h"
+#include "freedreno_query_hw.h"
 #include "freedreno_util.h"
 
 
@@ -70,7 +71,7 @@ fd_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		idx_bo = fd_resource(idx->buffer)->bo;
 		idx_type = size2indextype(idx->index_size);
 		idx_size = idx->index_size * info->count;
-		idx_offset = idx->offset;
+		idx_offset = idx->offset + (info->start * idx->index_size);
 		src_sel = DI_SRC_SEL_DMA;
 	} else {
 		idx_bo = NULL;
@@ -156,6 +157,7 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 	/* and any buffers used, need to be resolved: */
 	ctx->resolve |= buffers;
 
+	fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_DRAW);
 	ctx->draw(ctx, info);
 }
 
@@ -188,6 +190,8 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
 		util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 		util_format_short_name(pipe_surface_format(pfb->zsbuf)));
 
+	fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_CLEAR);
+
 	ctx->clear(ctx, buffers, color, depth, stencil);
 
 	ctx->dirty |= FD_DIRTY_ZSA |

src/gallium/drivers/freedreno/freedreno_gmem.c

@@ -35,6 +35,7 @@
 #include "freedreno_gmem.h"
 #include "freedreno_context.h"
 #include "freedreno_resource.h"
+#include "freedreno_query_hw.h"
 #include "freedreno_util.h"
 
 /*
@@ -273,17 +274,24 @@ render_tiles(struct fd_context *ctx)
 
 		ctx->emit_tile_prep(ctx, tile);
 
-		if (ctx->restore)
+		if (ctx->restore) {
+			fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_MEM2GMEM);
 			ctx->emit_tile_mem2gmem(ctx, tile);
+			fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
+		}
 
 		ctx->emit_tile_renderprep(ctx, tile);
 
+		fd_hw_query_prepare_tile(ctx, i, ctx->ring);
+
 		/* emit IB to drawcmds: */
 		OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 		fd_reset_wfi(ctx);
 
 		/* emit gmem2mem to transfer tile back to system memory: */
+		fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_GMEM2MEM);
 		ctx->emit_tile_gmem2mem(ctx, tile);
+		fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 	}
 }
 
@@ -292,6 +300,8 @@ render_sysmem(struct fd_context *ctx)
 {
 	ctx->emit_sysmem_prep(ctx);
 
+	fd_hw_query_prepare_tile(ctx, 0, ctx->ring);
+
 	/* emit IB to drawcmds: */
 	OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
 	fd_reset_wfi(ctx);
@@ -314,6 +324,11 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 		}
 	}
 
+	/* close out the draw cmds by making sure any active queries are
+	 * paused:
+	 */
+	fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
+
 	/* mark the end of the clear/draw cmds before emitting per-tile cmds: */
 	fd_ringmarker_mark(ctx->draw_end);
 	fd_ringmarker_mark(ctx->binning_end);
@@ -326,6 +341,7 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 		DBG("rendering sysmem (%s/%s)",
 			util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 			util_format_short_name(pipe_surface_format(pfb->zsbuf)));
+		fd_hw_query_prepare(ctx, 1);
 		render_sysmem(ctx);
 		ctx->stats.batch_sysmem++;
 	} else {
@@ -334,6 +350,7 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
 		DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
 			util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
 			util_format_short_name(pipe_surface_format(pfb->zsbuf)));
+		fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
 		render_tiles(ctx);
 		ctx->stats.batch_gmem++;
 	}

src/gallium/drivers/freedreno/freedreno_query.c

@@ -1,7 +1,7 @@
 /* -*- mode: C; c-file-style: "k&r"; ttxab-width 4; indent-tabs-mode: t; -*- */
 
 /*
- * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,63 +27,27 @@
  */
 
 #include "pipe/p_state.h"
-#include "util/u_string.h"
 #include "util/u_memory.h"
-#include "util/u_inlines.h"
-#include "os/os_time.h"
 
 #include "freedreno_query.h"
+#include "freedreno_query_sw.h"
+#include "freedreno_query_hw.h"
 #include "freedreno_context.h"
 #include "freedreno_util.h"
 
-#define FD_QUERY_DRAW_CALLS      (PIPE_QUERY_DRIVER_SPECIFIC + 0)
+/*
-#define FD_QUERY_BATCH_TOTAL     (PIPE_QUERY_DRIVER_SPECIFIC + 1)  /* total # of batches (submits) */
+ * Pipe Query interface:
-#define FD_QUERY_BATCH_SYSMEM    (PIPE_QUERY_DRIVER_SPECIFIC + 2)  /* batches using system memory (GMEM bypass) */
-#define FD_QUERY_BATCH_GMEM      (PIPE_QUERY_DRIVER_SPECIFIC + 3)  /* batches using GMEM */
-#define FD_QUERY_BATCH_RESTORE   (PIPE_QUERY_DRIVER_SPECIFIC + 4)  /* batches requiring GMEM restore */
-
-/* Currently just simple cpu query's supported.. probably need
- * to refactor this a bit when I'm eventually ready to add gpu
- * queries:
  */
-struct fd_query {
-	int type;
-	/* storage for the collected data */
-	union pipe_query_result data;
-	bool active;
-	uint64_t begin_value, end_value;
-	uint64_t begin_time, end_time;
-};
-
-static inline struct fd_query *
-fd_query(struct pipe_query *pq)
-{
-	return (struct fd_query *)pq;
-}
 
 static struct pipe_query *
 fd_create_query(struct pipe_context *pctx, unsigned query_type)
 {
+	struct fd_context *ctx = fd_context(pctx);
 	struct fd_query *q;
 
-	switch (query_type) {
+	q = fd_sw_create_query(ctx, query_type);
-	case PIPE_QUERY_PRIMITIVES_GENERATED:
-	case PIPE_QUERY_PRIMITIVES_EMITTED:
-	case FD_QUERY_DRAW_CALLS:
-	case FD_QUERY_BATCH_TOTAL:
-	case FD_QUERY_BATCH_SYSMEM:
-	case FD_QUERY_BATCH_GMEM:
-	case FD_QUERY_BATCH_RESTORE:
-		break;
-	default:
-		return NULL;
-	}
-
-	q = CALLOC_STRUCT(fd_query);
 	if (!q)
-		return NULL;
+		q = fd_hw_create_query(ctx, query_type);
-
-	q->type = query_type;
 
 	return (struct pipe_query *) q;
 }
@@ -92,64 +56,21 @@ static void
 fd_destroy_query(struct pipe_context *pctx, struct pipe_query *pq)
 {
 	struct fd_query *q = fd_query(pq);
-	free(q);
+	q->funcs->destroy_query(fd_context(pctx), q);
-}
-
-static uint64_t
-read_counter(struct pipe_context *pctx, int type)
-{
-	struct fd_context *ctx = fd_context(pctx);
-	switch (type) {
-	case PIPE_QUERY_PRIMITIVES_GENERATED:
-		/* for now same thing as _PRIMITIVES_EMITTED */
-	case PIPE_QUERY_PRIMITIVES_EMITTED:
-		return ctx->stats.prims_emitted;
-	case FD_QUERY_DRAW_CALLS:
-		return ctx->stats.draw_calls;
-	case FD_QUERY_BATCH_TOTAL:
-		return ctx->stats.batch_total;
-	case FD_QUERY_BATCH_SYSMEM:
-		return ctx->stats.batch_sysmem;
-	case FD_QUERY_BATCH_GMEM:
-		return ctx->stats.batch_gmem;
-	case FD_QUERY_BATCH_RESTORE:
-		return ctx->stats.batch_restore;
-	}
-	return 0;
-}
-
-static bool
-is_rate_query(struct fd_query *q)
-{
-	switch (q->type) {
-	case FD_QUERY_BATCH_TOTAL:
-	case FD_QUERY_BATCH_SYSMEM:
-	case FD_QUERY_BATCH_GMEM:
-	case FD_QUERY_BATCH_RESTORE:
-		return true;
-	default:
-		return false;
-	}
 }
 
 static void
 fd_begin_query(struct pipe_context *pctx, struct pipe_query *pq)
 {
 	struct fd_query *q = fd_query(pq);
-	q->active = true;
+	q->funcs->begin_query(fd_context(pctx), q);
-	q->begin_value = read_counter(pctx, q->type);
-	if (is_rate_query(q))
-		q->begin_time = os_time_get();
 }
 
 static void
 fd_end_query(struct pipe_context *pctx, struct pipe_query *pq)
 {
 	struct fd_query *q = fd_query(pq);
-	q->active = false;
+	q->funcs->end_query(fd_context(pctx), q);
-	q->end_value = read_counter(pctx, q->type);
-	if (is_rate_query(q))
-		q->end_time = os_time_get();
 }
 
 static boolean
@@ -157,21 +78,7 @@ fd_get_query_result(struct pipe_context *pctx, struct pipe_query *pq,
 		boolean wait, union pipe_query_result *result)
 {
 	struct fd_query *q = fd_query(pq);
-
+	return q->funcs->get_query_result(fd_context(pctx), q, wait, result);
-	if (q->active)
-		return false;
-
-	util_query_clear_result(result, q->type);
-
-	result->u64 = q->end_value - q->begin_value;
-
-	if (is_rate_query(q)) {
-		double fps = (result->u64 * 1000000) /
-				(double)(q->end_time - q->begin_time);
-		result->u64 = (uint64_t)fps;
-	}
-
-	return true;
 }
 
 static int

src/gallium/drivers/freedreno/freedreno_query.h

@@ -1,7 +1,7 @@
 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
 
 /*
- * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
+ * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -31,6 +31,37 @@
 
 #include "pipe/p_context.h"
 
+struct fd_context;
+struct fd_query;
+
+struct fd_query_funcs {
+	void (*destroy_query)(struct fd_context *ctx,
+			struct fd_query *q);
+	void (*begin_query)(struct fd_context *ctx, struct fd_query *q);
+	void (*end_query)(struct fd_context *ctx, struct fd_query *q);
+	boolean (*get_query_result)(struct fd_context *ctx,
+			struct fd_query *q, boolean wait,
+			union pipe_query_result *result);
+};
+
+struct fd_query {
+	const struct fd_query_funcs *funcs;
+	bool active;
+	int type;
+};
+
+static inline struct fd_query *
+fd_query(struct pipe_query *pq)
+{
+	return (struct fd_query *)pq;
+}
+
+#define FD_QUERY_DRAW_CALLS      (PIPE_QUERY_DRIVER_SPECIFIC + 0)
+#define FD_QUERY_BATCH_TOTAL     (PIPE_QUERY_DRIVER_SPECIFIC + 1)  /* total # of batches (submits) */
+#define FD_QUERY_BATCH_SYSMEM    (PIPE_QUERY_DRIVER_SPECIFIC + 2)  /* batches using system memory (GMEM bypass) */
+#define FD_QUERY_BATCH_GMEM      (PIPE_QUERY_DRIVER_SPECIFIC + 3)  /* batches using GMEM */
+#define FD_QUERY_BATCH_RESTORE   (PIPE_QUERY_DRIVER_SPECIFIC + 4)  /* batches requiring GMEM restore */
+
 void fd_query_screen_init(struct pipe_screen *pscreen);
 void fd_query_context_init(struct pipe_context *pctx);
 

src/gallium/drivers/freedreno/freedreno_query_hw.c

@@ -0,0 +1,465 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#include "pipe/p_state.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+
+#include "freedreno_query_hw.h"
+#include "freedreno_context.h"
+#include "freedreno_util.h"
+
+struct fd_hw_sample_period {
+	struct fd_hw_sample *start, *end;
+	struct list_head list;
+};
+
+/* maps query_type to sample provider idx: */
+static int pidx(unsigned query_type)
+{
+	switch (query_type) {
+	case PIPE_QUERY_OCCLUSION_COUNTER:
+		return 0;
+	case PIPE_QUERY_OCCLUSION_PREDICATE:
+		return 1;
+	default:
+		return -1;
+	}
+}
+
+static struct fd_hw_sample *
+get_sample(struct fd_context *ctx, struct fd_ringbuffer *ring,
+		unsigned query_type)
+{
+	struct fd_hw_sample *samp = NULL;
+	int idx = pidx(query_type);
+
+	if (!ctx->sample_cache[idx]) {
+		ctx->sample_cache[idx] =
+			ctx->sample_providers[idx]->get_sample(ctx, ring);
+	}
+
+	fd_hw_sample_reference(ctx, &samp, ctx->sample_cache[idx]);
+
+	return samp;
+}
+
+static void
+clear_sample_cache(struct fd_context *ctx)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ctx->sample_cache); i++)
+		fd_hw_sample_reference(ctx, &ctx->sample_cache[i], NULL);
+}
+
+static bool
+is_active(struct fd_hw_query *hq, enum fd_render_stage stage)
+{
+	return !!(hq->provider->active & stage);
+}
+
+
+static void
+resume_query(struct fd_context *ctx, struct fd_hw_query *hq,
+		struct fd_ringbuffer *ring)
+{
+	assert(!hq->period);
+	hq->period = util_slab_alloc(&ctx->sample_period_pool);
+	list_inithead(&hq->period->list);
+	hq->period->start = get_sample(ctx, ring, hq->base.type);
+	/* NOTE: util_slab_alloc() does not zero out the buffer: */
+	hq->period->end = NULL;
+}
+
+static void
+pause_query(struct fd_context *ctx, struct fd_hw_query *hq,
+		struct fd_ringbuffer *ring)
+{
+	assert(hq->period && !hq->period->end);
+	hq->period->end = get_sample(ctx, ring, hq->base.type);
+	list_addtail(&hq->period->list, &hq->current_periods);
+	hq->period = NULL;
+}
+
+static void
+destroy_periods(struct fd_context *ctx, struct list_head *list)
+{
+	struct fd_hw_sample_period *period, *s;
+	LIST_FOR_EACH_ENTRY_SAFE(period, s, list, list) {
+		fd_hw_sample_reference(ctx, &period->start, NULL);
+		fd_hw_sample_reference(ctx, &period->end, NULL);
+		list_del(&period->list);
+		util_slab_free(&ctx->sample_period_pool, period);
+	}
+}
+
+static void
+fd_hw_destroy_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_hw_query *hq = fd_hw_query(q);
+
+	destroy_periods(ctx, &hq->periods);
+	destroy_periods(ctx, &hq->current_periods);
+	list_del(&hq->list);
+
+	free(hq);
+}
+
+static void
+fd_hw_begin_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_hw_query *hq = fd_hw_query(q);
+	if (q->active)
+		return;
+
+	/* begin_query() should clear previous results: */
+	destroy_periods(ctx, &hq->periods);
+
+	if (is_active(hq, ctx->stage))
+		resume_query(ctx, hq, ctx->ring);
+
+	q->active = true;
+
+	/* add to active list: */
+	list_del(&hq->list);
+	list_addtail(&hq->list, &ctx->active_queries);
+}
+
+static void
+fd_hw_end_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_hw_query *hq = fd_hw_query(q);
+	if (!q->active)
+		return;
+	if (is_active(hq, ctx->stage))
+		pause_query(ctx, hq, ctx->ring);
+	q->active = false;
+	/* move to current list: */
+	list_del(&hq->list);
+	list_addtail(&hq->list, &ctx->current_queries);
+}
+
+/* helper to get ptr to specified sample: */
+static void * sampptr(struct fd_hw_sample *samp, uint32_t n, void *ptr)
+{
+	return ((char *)ptr) + (samp->tile_stride * n) + samp->offset;
+}
+
+static boolean
+fd_hw_get_query_result(struct fd_context *ctx, struct fd_query *q,
+		boolean wait, union pipe_query_result *result)
+{
+	struct fd_hw_query *hq = fd_hw_query(q);
+	const struct fd_hw_sample_provider *p = hq->provider;
+	struct fd_hw_sample_period *period;
+
+	if (q->active)
+		return false;
+
+	/* if the app tries to read back the query result before the
+	 * back is submitted, that forces us to flush so that there
+	 * are actually results to wait for:
+	 */
+	if (!LIST_IS_EMPTY(&hq->list)) {
+		DBG("reading query result forces flush!");
+		ctx->needs_flush = true;
+		fd_context_render(&ctx->base);
+	}
+
+	util_query_clear_result(result, q->type);
+
+	if (LIST_IS_EMPTY(&hq->periods))
+		return true;
+
+	assert(LIST_IS_EMPTY(&hq->list));
+	assert(LIST_IS_EMPTY(&hq->current_periods));
+	assert(!hq->period);
+
+	if (LIST_IS_EMPTY(&hq->periods))
+		return true;
+
+	/* if !wait, then check the last sample (the one most likely to
+	 * not be ready yet) and bail if it is not ready:
+	 */
+	if (!wait) {
+		int ret;
+
+		period = LIST_ENTRY(struct fd_hw_sample_period,
+				hq->periods.prev, list);
+
+		ret = fd_bo_cpu_prep(period->end->bo, ctx->screen->pipe,
+				DRM_FREEDRENO_PREP_READ | DRM_FREEDRENO_PREP_NOSYNC);
+		if (ret)
+			return false;
+
+		fd_bo_cpu_fini(period->end->bo);
+	}
+
+	/* sum the result across all sample periods: */
+	LIST_FOR_EACH_ENTRY(period, &hq->periods, list) {
+		struct fd_hw_sample *start = period->start;
+		struct fd_hw_sample *end = period->end;
+		unsigned i;
+
+		/* start and end samples should be from same batch: */
+		assert(start->bo == end->bo);
+		assert(start->num_tiles == end->num_tiles);
+
+		for (i = 0; i < start->num_tiles; i++) {
+			void *ptr;
+
+			fd_bo_cpu_prep(start->bo, ctx->screen->pipe,
+					DRM_FREEDRENO_PREP_READ);
+
+			ptr = fd_bo_map(start->bo);
+
+			p->accumulate_result(ctx, sampptr(period->start, i, ptr),
+					sampptr(period->end, i, ptr), result);
+
+			fd_bo_cpu_fini(start->bo);
+		}
+	}
+
+	return true;
+}
+
+static const struct fd_query_funcs hw_query_funcs = {
+		.destroy_query    = fd_hw_destroy_query,
+		.begin_query      = fd_hw_begin_query,
+		.end_query        = fd_hw_end_query,
+		.get_query_result = fd_hw_get_query_result,
+};
+
+struct fd_query *
+fd_hw_create_query(struct fd_context *ctx, unsigned query_type)
+{
+	struct fd_hw_query *hq;
+	struct fd_query *q;
+	int idx = pidx(query_type);
+
+	if ((idx < 0) || !ctx->sample_providers[idx])
+		return NULL;
+
+	hq = CALLOC_STRUCT(fd_hw_query);
+	if (!hq)
+		return NULL;
+
+	hq->provider = ctx->sample_providers[idx];
+
+	list_inithead(&hq->periods);
+	list_inithead(&hq->current_periods);
+	list_inithead(&hq->list);
+
+	q = &hq->base;
+	q->funcs = &hw_query_funcs;
+	q->type = query_type;
+
+	return q;
+}
+
+struct fd_hw_sample *
+fd_hw_sample_init(struct fd_context *ctx, uint32_t size)
+{
+	struct fd_hw_sample *samp = util_slab_alloc(&ctx->sample_pool);
+	pipe_reference_init(&samp->reference, 1);
+	samp->size = size;
+	samp->offset = ctx->next_sample_offset;
+	/* NOTE: util_slab_alloc() does not zero out the buffer: */
+	samp->bo = NULL;
+	samp->num_tiles = 0;
+	samp->tile_stride = 0;
+	ctx->next_sample_offset += size;
+	return samp;
+}
+
+void
+__fd_hw_sample_destroy(struct fd_context *ctx, struct fd_hw_sample *samp)
+{
+	if (samp->bo)
+		fd_bo_del(samp->bo);
+	util_slab_free(&ctx->sample_pool, samp);
+}
+
+static void
+prepare_sample(struct fd_hw_sample *samp, struct fd_bo *bo,
+		uint32_t num_tiles, uint32_t tile_stride)
+{
+	if (samp->bo) {
+		assert(samp->bo == bo);
+		assert(samp->num_tiles == num_tiles);
+		assert(samp->tile_stride == tile_stride);
+		return;
+	}
+	samp->bo = bo;
+	samp->num_tiles = num_tiles;
+	samp->tile_stride = tile_stride;
+}
+
+static void
+prepare_query(struct fd_hw_query *hq, struct fd_bo *bo,
+		uint32_t num_tiles, uint32_t tile_stride)
+{
+	struct fd_hw_sample_period *period, *s;
+
+	/* prepare all the samples in the query: */
+	LIST_FOR_EACH_ENTRY_SAFE(period, s, &hq->current_periods, list) {
+		prepare_sample(period->start, bo, num_tiles, tile_stride);
+		prepare_sample(period->end, bo, num_tiles, tile_stride);
+
+		/* move from current_periods list to periods list: */
+		list_del(&period->list);
+		list_addtail(&period->list, &hq->periods);
+	}
+}
+
+static void
+prepare_queries(struct fd_context *ctx, struct fd_bo *bo,
+		uint32_t num_tiles, uint32_t tile_stride,
+		struct list_head *list, bool remove)
+{
+	struct fd_hw_query *hq, *s;
+	LIST_FOR_EACH_ENTRY_SAFE(hq, s, list, list) {
+		prepare_query(hq, bo, num_tiles, tile_stride);
+		if (remove)
+			list_delinit(&hq->list);
+	}
+}
+
+/* called from gmem code once total storage requirements are known (ie.
+ * number of samples times number of tiles)
+ */
+void
+fd_hw_query_prepare(struct fd_context *ctx, uint32_t num_tiles)
+{
+	uint32_t tile_stride = ctx->next_sample_offset;
+	struct fd_bo *bo;
+
+	if (ctx->query_bo)
+		fd_bo_del(ctx->query_bo);
+
+	if (tile_stride > 0) {
+		bo = fd_bo_new(ctx->dev, tile_stride * num_tiles,
+				DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
+				DRM_FREEDRENO_GEM_TYPE_KMEM);
+	} else {
+		bo = NULL;
+	}
+
+	ctx->query_bo = bo;
+	ctx->query_tile_stride = tile_stride;
+
+	prepare_queries(ctx, bo, num_tiles, tile_stride,
+			&ctx->active_queries, false);
+	prepare_queries(ctx, bo, num_tiles, tile_stride,
+			&ctx->current_queries, true);
+
+	/* reset things for next batch: */
+	ctx->next_sample_offset = 0;
+}
+
+void
+fd_hw_query_prepare_tile(struct fd_context *ctx, uint32_t n,
+		struct fd_ringbuffer *ring)
+{
+	uint32_t tile_stride = ctx->query_tile_stride;
+	uint32_t offset = tile_stride * n;
+
+	/* bail if no queries: */
+	if (tile_stride == 0)
+		return;
+
+	fd_wfi(ctx, ring);
+	OUT_PKT0 (ring, HW_QUERY_BASE_REG, 1);
+	OUT_RELOCW(ring, ctx->query_bo, offset, 0, 0);
+}
+
+void
+fd_hw_query_set_stage(struct fd_context *ctx, struct fd_ringbuffer *ring,
+		enum fd_render_stage stage)
+{
+	/* special case: internal blits (like mipmap level generation)
+	 * go through normal draw path (via util_blitter_blit()).. but
+	 * we need to ignore the FD_STAGE_DRAW which will be set, so we
+	 * don't enable queries which should be paused during internal
+	 * blits:
+	 */
+	if ((ctx->stage == FD_STAGE_BLIT) &&
+			(stage != FD_STAGE_NULL))
+		return;
+
+	if (stage != ctx->stage) {
+		struct fd_hw_query *hq;
+		LIST_FOR_EACH_ENTRY(hq, &ctx->active_queries, list) {
+			bool was_active = is_active(hq, ctx->stage);
+			bool now_active = is_active(hq, stage);
+
+			if (now_active && !was_active)
+				resume_query(ctx, hq, ring);
+			else if (was_active && !now_active)
+				pause_query(ctx, hq, ring);
+		}
+	}
+	clear_sample_cache(ctx);
+	ctx->stage = stage;
+}
+
+void
+fd_hw_query_register_provider(struct pipe_context *pctx,
+		const struct fd_hw_sample_provider *provider)
+{
+	struct fd_context *ctx = fd_context(pctx);
+	int idx = pidx(provider->query_type);
+
+	assert((0 <= idx) && (idx < MAX_HW_SAMPLE_PROVIDERS));
+	assert(!ctx->sample_providers[idx]);
+
+	ctx->sample_providers[idx] = provider;
+}
+
+void
+fd_hw_query_init(struct pipe_context *pctx)
+{
+	struct fd_context *ctx = fd_context(pctx);
+
+	util_slab_create(&ctx->sample_pool, sizeof(struct fd_hw_sample),
+			16, UTIL_SLAB_SINGLETHREADED);
+	util_slab_create(&ctx->sample_period_pool, sizeof(struct fd_hw_sample_period),
+			16, UTIL_SLAB_SINGLETHREADED);
+	list_inithead(&ctx->active_queries);
+	list_inithead(&ctx->current_queries);
+}
+
+void
+fd_hw_query_fini(struct pipe_context *pctx)
+{
+	struct fd_context *ctx = fd_context(pctx);
+
+	util_slab_destroy(&ctx->sample_pool);
+	util_slab_destroy(&ctx->sample_period_pool);
+}

src/gallium/drivers/freedreno/freedreno_query_hw.h

@@ -0,0 +1,164 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#ifndef FREEDRENO_QUERY_HW_H_
+#define FREEDRENO_QUERY_HW_H_
+
+#include "util/u_double_list.h"
+
+#include "freedreno_query.h"
+#include "freedreno_context.h"
+
+
+/*
+ * HW Queries:
+ *
+ * See: https://github.com/freedreno/freedreno/wiki/Queries#hardware-queries
+ *
+ * Hardware queries will be specific to gpu generation, but they need
+ * some common infrastructure for triggering start/stop samples at
+ * various points (for example, to exclude mem2gmem/gmem2mem or clear)
+ * as well as per tile tracking.
+ *
+ * NOTE: in at least some cases hw writes sample values to memory addr
+ * specified in some register.  So we don't really have the option to
+ * just sample the same counter multiple times for multiple different
+ * queries with the same query_type.  So we cache per sample provider
+ * the most recent sample since the last draw.  This way multiple
+ * sample periods for multiple queries can reference the same sample.
+ *
+ * fd_hw_sample_provider:
+ *   - one per query type, registered/implemented by gpu generation
+ *     specific code
+ *   - can construct fd_hw_samples on demand
+ *   - most recent sample (since last draw) cached so multiple
+ *     different queries can ref the same sample
+ *
+ * fd_hw_sample:
+ *   - abstracts one snapshot of counter value(s) across N tiles
+ *   - backing object not allocated until submit time when number
+ *     of samples and number of tiles is known
+ *
+ * fd_hw_sample_period:
+ *   - consists of start and stop sample
+ *   - a query accumulates a list of sample periods
+ *   - the query result is the sum of the sample periods
+ */
+
+struct fd_hw_sample_provider {
+	unsigned query_type;
+
+	/* stages applicable to the query type: */
+	enum fd_render_stage active;
+
+	/* when a new sample is required, emit appropriate cmdstream
+	 * and return a sample object:
+	 */
+	struct fd_hw_sample *(*get_sample)(struct fd_context *ctx,
+			struct fd_ringbuffer *ring);
+
+	/* accumulate the results from specified sample period: */
+	void (*accumulate_result)(struct fd_context *ctx,
+			const void *start, const void *end,
+			union pipe_query_result *result);
+};
+
+struct fd_hw_sample {
+	struct pipe_reference reference;  /* keep this first */
+
+	/* offset and size of the sample are know at the time the
+	 * sample is constructed.
+	 */
+	uint32_t size;
+	uint32_t offset;
+
+	/* backing object, offset/stride/etc are determined not when
+	 * the sample is constructed, but when the batch is submitted.
+	 * This way we can defer allocation until total # of requested
+	 * samples, and total # of tiles, is known.
+	 */
+	struct fd_bo *bo;
+	uint32_t num_tiles;
+	uint32_t tile_stride;
+};
+
+struct fd_hw_sample_period;
+
+struct fd_hw_query {
+	struct fd_query base;
+
+	const struct fd_hw_sample_provider *provider;
+
+	/* list of fd_hw_sample_period in previous submits: */
+	struct list_head periods;
+
+	/* list of fd_hw_sample_period's in current submit: */
+	struct list_head current_periods;
+
+	/* if active and not paused, the current sample period (not
+	 * yet added to current_periods):
+	 */
+	struct fd_hw_sample_period *period;
+
+	struct list_head list;  /* list-node in ctx->active_queries */
+};
+
+static inline struct fd_hw_query *
+fd_hw_query(struct fd_query *q)
+{
+	return (struct fd_hw_query *)q;
+}
+
+struct fd_query * fd_hw_create_query(struct fd_context *ctx, unsigned query_type);
+/* helper for sample providers: */
+struct fd_hw_sample * fd_hw_sample_init(struct fd_context *ctx, uint32_t size);
+/* don't call directly, use fd_hw_sample_reference() */
+void __fd_hw_sample_destroy(struct fd_context *ctx, struct fd_hw_sample *samp);
+void fd_hw_query_prepare(struct fd_context *ctx, uint32_t num_tiles);
+void fd_hw_query_prepare_tile(struct fd_context *ctx, uint32_t n,
+		struct fd_ringbuffer *ring);
+void fd_hw_query_set_stage(struct fd_context *ctx,
+		struct fd_ringbuffer *ring, enum fd_render_stage stage);
+void fd_hw_query_register_provider(struct pipe_context *pctx,
+		const struct fd_hw_sample_provider *provider);
+void fd_hw_query_init(struct pipe_context *pctx);
+void fd_hw_query_fini(struct pipe_context *pctx);
+
+static inline void
+fd_hw_sample_reference(struct fd_context *ctx,
+		struct fd_hw_sample **ptr, struct fd_hw_sample *samp)
+{
+	struct fd_hw_sample *old_samp = *ptr;
+
+	if (pipe_reference(&(*ptr)->reference, &samp->reference))
+		__fd_hw_sample_destroy(ctx, old_samp);
+	if (ptr)
+		*ptr = samp;
+}
+
+#endif /* FREEDRENO_QUERY_HW_H_ */

src/gallium/drivers/freedreno/freedreno_query_sw.c

@@ -0,0 +1,165 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#include "pipe/p_state.h"
+#include "util/u_string.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "os/os_time.h"
+
+#include "freedreno_query_sw.h"
+#include "freedreno_context.h"
+#include "freedreno_util.h"
+
+/*
+ * SW Queries:
+ *
+ * In the core, we have some support for basic sw counters
+ */
+
+static void
+fd_sw_destroy_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_sw_query *sq = fd_sw_query(q);
+	free(sq);
+}
+
+static uint64_t
+read_counter(struct fd_context *ctx, int type)
+{
+	switch (type) {
+	case PIPE_QUERY_PRIMITIVES_GENERATED:
+		/* for now same thing as _PRIMITIVES_EMITTED */
+	case PIPE_QUERY_PRIMITIVES_EMITTED:
+		return ctx->stats.prims_emitted;
+	case FD_QUERY_DRAW_CALLS:
+		return ctx->stats.draw_calls;
+	case FD_QUERY_BATCH_TOTAL:
+		return ctx->stats.batch_total;
+	case FD_QUERY_BATCH_SYSMEM:
+		return ctx->stats.batch_sysmem;
+	case FD_QUERY_BATCH_GMEM:
+		return ctx->stats.batch_gmem;
+	case FD_QUERY_BATCH_RESTORE:
+		return ctx->stats.batch_restore;
+	}
+	return 0;
+}
+
+static bool
+is_rate_query(struct fd_query *q)
+{
+	switch (q->type) {
+	case FD_QUERY_BATCH_TOTAL:
+	case FD_QUERY_BATCH_SYSMEM:
+	case FD_QUERY_BATCH_GMEM:
+	case FD_QUERY_BATCH_RESTORE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void
+fd_sw_begin_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_sw_query *sq = fd_sw_query(q);
+	q->active = true;
+	sq->begin_value = read_counter(ctx, q->type);
+	if (is_rate_query(q))
+		sq->begin_time = os_time_get();
+}
+
+static void
+fd_sw_end_query(struct fd_context *ctx, struct fd_query *q)
+{
+	struct fd_sw_query *sq = fd_sw_query(q);
+	q->active = false;
+	sq->end_value = read_counter(ctx, q->type);
+	if (is_rate_query(q))
+		sq->end_time = os_time_get();
+}
+
+static boolean
+fd_sw_get_query_result(struct fd_context *ctx, struct fd_query *q,
+		boolean wait, union pipe_query_result *result)
+{
+	struct fd_sw_query *sq = fd_sw_query(q);
+
+	if (q->active)
+		return false;
+
+	util_query_clear_result(result, q->type);
+
+	result->u64 = sq->end_value - sq->begin_value;
+
+	if (is_rate_query(q)) {
+		double fps = (result->u64 * 1000000) /
+				(double)(sq->end_time - sq->begin_time);
+		result->u64 = (uint64_t)fps;
+	}
+
+	return true;
+}
+
+static const struct fd_query_funcs sw_query_funcs = {
+		.destroy_query    = fd_sw_destroy_query,
+		.begin_query      = fd_sw_begin_query,
+		.end_query        = fd_sw_end_query,
+		.get_query_result = fd_sw_get_query_result,
+};
+
+struct fd_query *
+fd_sw_create_query(struct fd_context *ctx, unsigned query_type)
+{
+	struct fd_sw_query *sq;
+	struct fd_query *q;
+
+	switch (query_type) {
+	case PIPE_QUERY_PRIMITIVES_GENERATED:
+	case PIPE_QUERY_PRIMITIVES_EMITTED:
+	case FD_QUERY_DRAW_CALLS:
+	case FD_QUERY_BATCH_TOTAL:
+	case FD_QUERY_BATCH_SYSMEM:
+	case FD_QUERY_BATCH_GMEM:
+	case FD_QUERY_BATCH_RESTORE:
+		break;
+	default:
+		return NULL;
+	}
+
+	sq = CALLOC_STRUCT(fd_sw_query);
+	if (!sq)
+		return NULL;
+
+	q = &sq->base;
+	q->funcs = &sw_query_funcs;
+	q->type = query_type;
+
+	return q;
+}

src/gallium/drivers/freedreno/freedreno_query_sw.h

@@ -0,0 +1,55 @@
+/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
+
+/*
+ * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#ifndef FREEDRENO_QUERY_SW_H_
+#define FREEDRENO_QUERY_SW_H_
+
+#include "freedreno_query.h"
+
+/*
+ * SW Queries:
+ *
+ * In the core, we have some support for basic sw counters
+ */
+
+struct fd_sw_query {
+	struct fd_query base;
+	uint64_t begin_value, end_value;
+	uint64_t begin_time, end_time;
+};
+
+static inline struct fd_sw_query *
+fd_sw_query(struct fd_query *q)
+{
+	return (struct fd_sw_query *)q;
+}
+
+struct fd_query * fd_sw_create_query(struct fd_context *ctx,
+		unsigned query_type);
+
+#endif /* FREEDRENO_QUERY_SW_H_ */

src/gallium/drivers/freedreno/freedreno_resource.c

@@ -36,6 +36,7 @@
 #include "freedreno_screen.h"
 #include "freedreno_surface.h"
 #include "freedreno_context.h"
+#include "freedreno_query_hw.h"
 #include "freedreno_util.h"
 
 #include <errno.h>
@@ -47,6 +48,10 @@ realloc_bo(struct fd_resource *rsc, uint32_t size)
 	uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 			DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
 
+	/* if we start using things other than write-combine,
+	 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
+	 */
+
 	if (rsc->bo)
 		fd_bo_del(rsc->bo);
 
@@ -401,7 +406,9 @@ render_blit(struct pipe_context *pctx, struct pipe_blit_info *info)
 	util_blitter_save_fragment_sampler_views(ctx->blitter,
 			ctx->fragtex.num_textures, ctx->fragtex.textures);
 
+	fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_BLIT);
 	util_blitter_blit(ctx->blitter, info);
+	fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
 
 	return true;
 }

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -143,6 +143,8 @@ tables for things that differ if the delta is not too much..
 static int
 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 {
+	struct fd_screen *screen = fd_screen(pscreen);
+
 	/* this is probably not totally correct.. but it's a start: */
 	switch (param) {
 	/* Supported features (boolean caps). */
@@ -159,11 +161,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
-	case PIPE_CAP_SM3:
 	case PIPE_CAP_SEAMLESS_CUBE_MAP:
-	case PIPE_CAP_PRIMITIVE_RESTART:
-	case PIPE_CAP_CONDITIONAL_RENDER:
-	case PIPE_CAP_TEXTURE_BARRIER:
 	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 	case PIPE_CAP_TGSI_INSTANCEID:
@@ -173,13 +171,18 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_COMPUTE:
 	case PIPE_CAP_START_INSTANCE:
 	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
-	case PIPE_CAP_TEXTURE_MULTISAMPLE:
 	case PIPE_CAP_USER_CONSTANT_BUFFERS:
+	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 		return 1;
 
 	case PIPE_CAP_SHADER_STENCIL_EXPORT:
 	case PIPE_CAP_TGSI_TEXCOORD:
 	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+	case PIPE_CAP_CONDITIONAL_RENDER:
+	case PIPE_CAP_PRIMITIVE_RESTART:
+	case PIPE_CAP_TEXTURE_MULTISAMPLE:
+	case PIPE_CAP_TEXTURE_BARRIER:
+	case PIPE_CAP_SM3:
 		return 0;
 
 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
@@ -205,7 +208,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_VS_LAYER:
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 	case PIPE_CAP_TEXTURE_GATHER_SM5:
-        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
         case PIPE_CAP_FAKE_SW_MSAA:
 	case PIPE_CAP_TEXTURE_QUERY_LOD:
         case PIPE_CAP_SAMPLE_SHADING:
@@ -229,17 +231,18 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 		return MAX_MIP_LEVELS;
 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-		return 9192;
+		return 0;  /* TODO: a3xx+ should support (required in gles3) */
 
 	/* Render targets. */
 	case PIPE_CAP_MAX_RENDER_TARGETS:
 		return 1;
 
-	/* Timer queries. */
+	/* Queries. */
 	case PIPE_CAP_QUERY_TIME_ELAPSED:
-	case PIPE_CAP_OCCLUSION_QUERY:
 	case PIPE_CAP_QUERY_TIMESTAMP:
 		return 0;
+	case PIPE_CAP_OCCLUSION_QUERY:
+		return (screen->gpu_id >= 300) ? 1: 0;
 
 	case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 	case PIPE_CAP_MIN_TEXEL_OFFSET:
@@ -252,7 +255,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_ENDIANNESS:
 		return PIPE_ENDIAN_LITTLE;
 
-        case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+	case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 		return 64;
 
 	default:
@@ -315,7 +318,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 		return 8; /* XXX */
 	case PIPE_SHADER_CAP_MAX_INPUTS:
-		return 32;
+		return 16;
 	case PIPE_SHADER_CAP_MAX_TEMPS:
 		return 64; /* Max native temporaries. */
 	case PIPE_SHADER_CAP_MAX_ADDRS:

src/gallium/drivers/freedreno/freedreno_texture.c

@@ -57,7 +57,7 @@ static void bind_sampler_states(struct fd_texture_stateobj *prog,
 
 	for (i = 0; i < nr; i++) {
 		if (hwcso[i])
-			new_nr++;
+			new_nr = i + 1;
 		prog->samplers[i] = hwcso[i];
 		prog->dirty_samplers |= (1 << i);
 	}
@@ -78,7 +78,7 @@ static void set_sampler_views(struct fd_texture_stateobj *prog,
 
 	for (i = 0; i < nr; i++) {
 		if (views[i])
-			new_nr++;
+			new_nr = i + 1;
 		pipe_sampler_view_reference(&prog->textures[i], views[i]);
 		prog->dirty_samplers |= (1 << i);
 	}

src/gallium/drivers/freedreno/freedreno_util.c

@@ -111,26 +111,6 @@ fd_blend_factor(unsigned factor)
 	}
 }
 
-enum adreno_rb_blend_opcode
-fd_blend_func(unsigned func)
-{
-	switch (func) {
-	case PIPE_BLEND_ADD:
-		return BLEND_DST_PLUS_SRC;
-	case PIPE_BLEND_MIN:
-		return BLEND_MIN_DST_SRC;
-	case PIPE_BLEND_MAX:
-		return BLEND_MAX_DST_SRC;
-	case PIPE_BLEND_SUBTRACT:
-		return BLEND_SRC_MINUS_DST;
-	case PIPE_BLEND_REVERSE_SUBTRACT:
-		return BLEND_DST_MINUS_SRC;
-	default:
-		DBG("invalid blend func: %x", func);
-		return 0;
-	}
-}
-
 enum adreno_pa_su_sc_draw
 fd_polygon_mode(unsigned mode)
 {

src/gallium/drivers/freedreno/freedreno_util.h

@@ -45,7 +45,6 @@
 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
-enum adreno_rb_blend_opcode fd_blend_func(unsigned func);
 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
 enum adreno_stencil_op fd_stencil_op(unsigned op);
 
@@ -223,11 +222,18 @@ OUT_IB(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
 	emit_marker(ring, 6);
 }
 
+/* CP_SCRATCH_REG4 is used to hold base address for query results: */
+#define HW_QUERY_BASE_REG REG_AXXX_CP_SCRATCH_REG4
+
 static inline void
 emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
 {
 	extern unsigned marker_cnt;
-	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG0 + scratch_idx, 1);
+	unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx;
+	assert(reg != HW_QUERY_BASE_REG);
+	if (reg == HW_QUERY_BASE_REG)
+		return;
+	OUT_PKT0(ring, reg, 1);
 	OUT_RING(ring, ++marker_cnt);
 }
 

src/gallium/drivers/llvmpipe/lp_rast.c

@@ -312,9 +312,15 @@ lp_rast_shade_tile(struct lp_rasterizer_task *task,
 
          /* color buffer */
          for (i = 0; i < scene->fb.nr_cbufs; i++){
-            stride[i] = scene->cbufs[i].stride;
+            if (scene->fb.cbufs[i]) {
-            color[i] = lp_rast_get_unswizzled_color_block_pointer(task, i, tile_x + x,
+               stride[i] = scene->cbufs[i].stride;
-                                                                  tile_y + y, inputs->layer);
+               color[i] = lp_rast_get_unswizzled_color_block_pointer(task, i, tile_x + x,
+                                                                     tile_y + y, inputs->layer);
+            }
+            else {
+               stride[i] = 0;
+               color[i] = NULL;
+            }
          }
 
          /* depth buffer */

src/gallium/drivers/llvmpipe/lp_texture.c

@@ -115,7 +115,7 @@ llvmpipe_texture_layout(struct llvmpipe_screen *screen,
             lpr->row_stride[level] = align(nblocksx * block_size, util_cpu_caps.cacheline);
 
          /* if row_stride * height > LP_MAX_TEXTURE_SIZE */
-         if (lpr->row_stride[level] > LP_MAX_TEXTURE_SIZE / nblocksy) {
+         if ((uint64_t)lpr->row_stride[level] * nblocksy > LP_MAX_TEXTURE_SIZE) {
             /* image too large */
             goto fail;
          }

src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h

@@ -177,6 +177,7 @@ struct nv50_ir_prog_info
       uint8_t vertexId;          /* system value index of VertexID */
       uint8_t edgeFlagIn;
       uint8_t edgeFlagOut;
+      int8_t viewportId;         /* output index of ViewportIndex */
       uint8_t fragDepth;         /* output index of FragDepth */
       uint8_t sampleMask;        /* output index of SampleMask */
       boolean sampleInterp;      /* perform sample interp on all fp inputs */

src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp

@@ -287,10 +287,12 @@ CodeEmitterGK110::emitPredicate(const Instruction *i)
 void
 CodeEmitterGK110::setCAddress14(const ValueRef& src)
 {
-   const int32_t addr = src.get()->asSym()->reg.data.offset / 4;
+   const Storage& res = src.get()->asSym()->reg;
+   const int32_t addr = res.data.offset / 4;
 
    code[0] |= (addr & 0x01ff) << 23;
    code[1] |= (addr & 0x3e00) >> 9;
+   code[1] |= res.fileIndex << 5;
 }
 
 void
@@ -413,7 +415,6 @@ CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2,
       case FILE_MEMORY_CONST:
          code[1] &= (s == 2) ? ~(0x4 << 28) : ~(0x8 << 28);
          setCAddress14(i->src(s));
-         code[1] |= i->getSrc(s)->reg.fileIndex << 5;
          break;
       case FILE_IMMEDIATE:
          setShortImmediate(i, s);
@@ -555,6 +556,7 @@ CodeEmitterGK110::emitFADD(const Instruction *i)
       RND_(2a, F);
       ABS_(31, 0);
       NEG_(33, 0);
+      SAT_(35);
 
       if (code[0] & 0x1) {
          modNegAbsF32_3b(i, 1);
@@ -633,7 +635,7 @@ CodeEmitterGK110::emitISAD(const Instruction *i)
 {
    assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
 
-   emitForm_21(i, 0x1fc, 0xb74);
+   emitForm_21(i, 0x1f4, 0xb74);
 
    if (i->dType == TYPE_S32)
       code[1] |= 1 << 19;
@@ -711,7 +713,7 @@ CodeEmitterGK110::emitEXTBF(const Instruction *i)
 void
 CodeEmitterGK110::emitBFIND(const Instruction *i)
 {
-   emitForm_21(i, 0x618, 0xc18);
+   emitForm_C(i, 0x218, 0x2);
 
    if (i->dType == TYPE_S32)
       code[1] |= 0x80000;
@@ -915,6 +917,9 @@ CodeEmitterGK110::emitSET(const CmpInstruction *i)
          modNegAbsF32_3b(i, 1);
       }
       FTZ_(3a);
+
+      if (i->dType == TYPE_F32)
+         code[1] |= 1 << 23;
    }
    if (i->sType == TYPE_S32)
       code[1] |= 1 << 19;
@@ -949,7 +954,7 @@ CodeEmitterGK110::emitSLCT(const CmpInstruction *i)
       FTZ_(32);
       emitCondCode(cc, 0x33, 0xf);
    } else {
-      emitForm_21(i, 0x1a4, 0xb20);
+      emitForm_21(i, 0x1a0, 0xb20);
       emitCondCode(cc, 0x34, 0x7);
    }
 }
@@ -964,7 +969,7 @@ void CodeEmitterGK110::emitSELP(const Instruction *i)
 
 void CodeEmitterGK110::emitTEXBAR(const Instruction *i)
 {
-   code[0] = 0x00000002 | (i->subOp << 23);
+   code[0] = 0x0000003e | (i->subOp << 23);
    code[1] = 0x77000000;
 
    emitPredicate(i);
@@ -1201,7 +1206,7 @@ CodeEmitterGK110::emitFlow(const Instruction *i)
    case OP_PRECONT:  code[1] = 0x15800000; mask = 2; break;
    case OP_PRERET:   code[1] = 0x13800000; mask = 2; break;
 
-   case OP_QUADON:  code[1] = 0x1b000000; mask = 0; break;
+   case OP_QUADON:  code[1] = 0x1b800000; mask = 0; break;
    case OP_QUADPOP: code[1] = 0x1c000000; mask = 0; break;
    case OP_BRKPT:   code[1] = 0x00000000; mask = 0; break;
    default:
@@ -1323,7 +1328,8 @@ CodeEmitterGK110::emitOUT(const Instruction *i)
 void
 CodeEmitterGK110::emitInterpMode(const Instruction *i)
 {
-   code[1] |= i->ipa << 21; // TODO: INTERP_SAMPLEID
+   code[1] |= (i->ipa & 0x3) << 21; // TODO: INTERP_SAMPLEID
+   code[1] |= (i->ipa & 0xc) << (19 - 2);
 }
 
 void

src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

@@ -790,6 +790,8 @@ bool Source::scanSource()
       info->prop.gp.instanceCount = 1; // default value
    }
 
+   info->io.viewportId = -1;
+
    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 
@@ -982,6 +984,9 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
          case TGSI_SEMANTIC_SAMPLEMASK:
             info->io.sampleMask = i;
             break;
+         case TGSI_SEMANTIC_VIEWPORT_INDEX:
+            info->io.viewportId = i;
+            break;
          default:
             break;
          }
@@ -1258,6 +1263,8 @@ private:
    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
    Stack loopBBs;  // loop headers
    Stack breakBBs; // end of / after loop
+
+   Value *viewport;
 };
 
 Symbol *
@@ -1555,8 +1562,16 @@ Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
    } else
    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
-      if (ptr || (info->out[idx].mask & (1 << c)))
+
-         mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+      if (ptr || (info->out[idx].mask & (1 << c))) {
+         /* Save the viewport index into a scratch register so that it can be
+            exported at EMIT time */
+         if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
+             viewport != NULL)
+            mkOp1(OP_MOV, TYPE_U32, viewport, val);
+         else
+            mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+      }
    } else
    if (f == TGSI_FILE_TEMPORARY ||
        f == TGSI_FILE_PREDICATE ||
@@ -2199,7 +2214,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
    case TGSI_OPCODE_IMUL_HI:
    case TGSI_OPCODE_UMUL_HI:
    case TGSI_OPCODE_OR:
-   case TGSI_OPCODE_POW:
    case TGSI_OPCODE_SHL:
    case TGSI_OPCODE_ISHR:
    case TGSI_OPCODE_USHR:
@@ -2254,6 +2268,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
       break;
+   case TGSI_OPCODE_POW:
+      val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
+      FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
+         mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
+      break;
    case TGSI_OPCODE_EX2:
    case TGSI_OPCODE_LG2:
       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
@@ -2453,7 +2472,12 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
       break;
    case TGSI_OPCODE_KILL_IF:
       val0 = new_LValue(func, FILE_PREDICATE);
+      mask = 0;
       for (c = 0; c < 4; ++c) {
+         const int s = tgsi.getSrc(0).getSwizzle(c);
+         if (mask & (1 << s))
+            continue;
+         mask |= 1 << s;
          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
       }
@@ -2514,6 +2538,13 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
       break;
    case TGSI_OPCODE_EMIT:
+      /* export the saved viewport index */
+      if (viewport != NULL) {
+         Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
+                                  info->out[info->io.viewportId].slot[0] * 4);
+         mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
+      }
+      /* fallthrough */
    case TGSI_OPCODE_ENDPRIM:
       // get vertex stream if specified (must be immediate)
       src0 = tgsi.srcCount() ?
@@ -2943,6 +2974,11 @@ Converter::run()
       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
    }
 
+   if (info->io.viewportId >= 0)
+      viewport = getScratch();
+   else
+      viewport = NULL;
+
    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
       if (!handleInstruction(&code->insns[ip]))
          return false;

src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp

@@ -37,18 +37,25 @@ namespace nv50_ir {
 //    ah*bl 00
 //
 // fffe0001 + fffe0001
+//
+// Note that this sort of splitting doesn't work for signed values, so we
+// compute the sign on those manually and then perform an unsigned multiply.
 static bool
 expandIntegerMUL(BuildUtil *bld, Instruction *mul)
 {
    const bool highResult = mul->subOp == NV50_IR_SUBOP_MUL_HIGH;
 
-   DataType fTy = mul->sType; // full type
+   DataType fTy; // full type
-   DataType hTy;
+   switch (mul->sType) {
+   case TYPE_S32: fTy = TYPE_U32; break;
+   case TYPE_S64: fTy = TYPE_U64; break;
+   default: fTy = mul->sType; break;
+   }
+
+   DataType hTy; // half type
    switch (fTy) {
-   case TYPE_S32: hTy = TYPE_S16; break;
    case TYPE_U32: hTy = TYPE_U16; break;
    case TYPE_U64: hTy = TYPE_U32; break;
-   case TYPE_S64: hTy = TYPE_S32; break;
    default:
       return false;
    }
@@ -59,15 +66,25 @@ expandIntegerMUL(BuildUtil *bld, Instruction *mul)
 
    bld->setPosition(mul, true);
 
+   Value *s[2];
    Value *a[2], *b[2];
-   Value *c[2];
    Value *t[4];
    for (int j = 0; j < 4; ++j)
       t[j] = bld->getSSA(fullSize);
 
+   s[0] = mul->getSrc(0);
+   s[1] = mul->getSrc(1);
+
+   if (isSignedType(mul->sType)) {
+      s[0] = bld->getSSA(fullSize);
+      s[1] = bld->getSSA(fullSize);
+      bld->mkOp1(OP_ABS, mul->sType, s[0], mul->getSrc(0));
+      bld->mkOp1(OP_ABS, mul->sType, s[1], mul->getSrc(1));
+   }
+
    // split sources into halves
-   i[0] = bld->mkSplit(a, halfSize, mul->getSrc(0));
+   i[0] = bld->mkSplit(a, halfSize, s[0]);
-   i[1] = bld->mkSplit(b, halfSize, mul->getSrc(1));
+   i[1] = bld->mkSplit(b, halfSize, s[1]);
 
    i[2] = bld->mkOp2(OP_MUL, fTy, t[0], a[0], b[1]);
    i[3] = bld->mkOp3(OP_MAD, fTy, t[1], a[1], b[0], t[0]);
@@ -75,23 +92,76 @@ expandIntegerMUL(BuildUtil *bld, Instruction *mul)
    i[4] = bld->mkOp3(OP_MAD, fTy, t[3], a[0], b[0], t[2]);
 
    if (highResult) {
-      Value *r[3];
+      Value *c[2];
+      Value *r[5];
       Value *imm = bld->loadImm(NULL, 1 << (halfSize * 8));
       c[0] = bld->getSSA(1, FILE_FLAGS);
       c[1] = bld->getSSA(1, FILE_FLAGS);
-      for (int j = 0; j < 3; ++j)
+      for (int j = 0; j < 5; ++j)
          r[j] = bld->getSSA(fullSize);
 
       i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8));
       i[6] = bld->mkOp2(OP_ADD, fTy, r[1], r[0], imm);
-      bld->mkOp2(OP_UNION, TYPE_U32, r[2], r[1], r[0]);
+      bld->mkMov(r[3], r[0])->setPredicate(CC_NC, c[0]);
-      i[5] = bld->mkOp3(OP_MAD, fTy, mul->getDef(0), a[1], b[1], r[2]);
+      bld->mkOp2(OP_UNION, TYPE_U32, r[2], r[1], r[3]);
+      i[5] = bld->mkOp3(OP_MAD, fTy, r[4], a[1], b[1], r[2]);
 
       // set carry defs / sources
       i[3]->setFlagsDef(1, c[0]);
-      i[4]->setFlagsDef(0, c[1]); // actual result not required, just the carry
+      // actual result required in negative case, but ignored for
+      // unsigned. for some reason the compiler ends up dropping the whole
+      // instruction if the destination is unused but the flags are.
+      if (isSignedType(mul->sType))
+         i[4]->setFlagsDef(1, c[1]);
+      else
+         i[4]->setFlagsDef(0, c[1]);
       i[6]->setPredicate(CC_C, c[0]);
       i[5]->setFlagsSrc(3, c[1]);
+
+      if (isSignedType(mul->sType)) {
+         Value *cc[2];
+         Value *rr[7];
+         Value *one = bld->getSSA(fullSize);
+         bld->loadImm(one, 1);
+         for (int j = 0; j < 7; j++)
+            rr[j] = bld->getSSA(fullSize);
+
+         // NOTE: this logic uses predicates because splitting basic blocks is
+         // ~impossible during the SSA phase. The RA relies on a correlation
+         // between edge order and phi node sources.
+
+         // Set the sign of the result based on the inputs
+         bld->mkOp2(OP_XOR, fTy, NULL, mul->getSrc(0), mul->getSrc(1))
+            ->setFlagsDef(0, (cc[0] = bld->getSSA(1, FILE_FLAGS)));
+
+         // 1s complement of 64-bit value
+         bld->mkOp1(OP_NOT, fTy, rr[0], r[4])
+            ->setPredicate(CC_S, cc[0]);
+         bld->mkOp1(OP_NOT, fTy, rr[1], t[3])
+            ->setPredicate(CC_S, cc[0]);
+
+         // add to low 32-bits, keep track of the carry
+         Instruction *n = bld->mkOp2(OP_ADD, fTy, NULL, rr[1], one);
+         n->setPredicate(CC_S, cc[0]);
+         n->setFlagsDef(0, (cc[1] = bld->getSSA(1, FILE_FLAGS)));
+
+         // If there was a carry, add 1 to the upper 32 bits
+         // XXX: These get executed even if they shouldn't be
+         bld->mkOp2(OP_ADD, fTy, rr[2], rr[0], one)
+            ->setPredicate(CC_C, cc[1]);
+         bld->mkMov(rr[3], rr[0])
+            ->setPredicate(CC_NC, cc[1]);
+         bld->mkOp2(OP_UNION, fTy, rr[4], rr[2], rr[3]);
+
+         // Merge the results from the negative and non-negative paths
+         bld->mkMov(rr[5], rr[4])
+            ->setPredicate(CC_S, cc[0]);
+         bld->mkMov(rr[6], r[4])
+            ->setPredicate(CC_NS, cc[0]);
+         bld->mkOp2(OP_UNION, mul->sType, mul->getDef(0), rr[5], rr[6]);
+      } else {
+         bld->mkMov(mul->getDef(0), r[4]);
+      }
    } else {
       bld->mkMov(mul->getDef(0), t[3]);
    }
@@ -591,6 +661,10 @@ void NV50LoweringPreSSA::loadTexMsInfo(uint32_t off, Value **ms,
    Value *tmp = new_LValue(func, FILE_GPR);
    uint8_t b = prog->driver->io.resInfoCBSlot;
    off += prog->driver->io.suInfoBase;
+   if (prog->getType() > Program::TYPE_VERTEX)
+      off += 16 * 2 * 4;
+   if (prog->getType() > Program::TYPE_GEOMETRY)
+      off += 16 * 2 * 4;
    *ms_x = bld.mkLoadv(TYPE_U32, bld.mkSymbol(
                              FILE_MEMORY_CONST, b, TYPE_U32, off + 0), NULL);
    *ms_y = bld.mkLoadv(TYPE_U32, bld.mkSymbol(
@@ -1205,8 +1279,11 @@ NV50LoweringPreSSA::checkPredicate(Instruction *insn)
    Value *pred = insn->getPredicate();
    Value *cdst;
 
-   if (!pred || pred->reg.file == FILE_FLAGS)
+   // FILE_PREDICATE will simply be changed to FLAGS on conversion to SSA
+   if (!pred ||
+       pred->reg.file == FILE_FLAGS || pred->reg.file == FILE_PREDICATE)
       return;
+
    cdst = bld.getSSA(1, FILE_FLAGS);
 
    bld.mkCmp(OP_SET, CC_NEU, insn->dType, cdst, insn->dType, bld.loadImm(NULL, 0), pred);

src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

@@ -187,7 +187,8 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
       return;
    }
 
-   if (insn->op == OP_SET)
+   if (insn->op == OP_SET || insn->op == OP_SET_AND ||
+       insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
       insn->asCmp()->setCond = reverseCondCode(insn->asCmp()->setCond);
    else
    if (insn->op == OP_SLCT)
@@ -424,7 +425,17 @@ ConstantFolding::expr(Instruction *i,
       case TYPE_F32: res.data.f32 = a->data.f32 * b->data.f32; break;
       case TYPE_F64: res.data.f64 = a->data.f64 * b->data.f64; break;
       case TYPE_S32:
-      case TYPE_U32: res.data.u32 = a->data.u32 * b->data.u32; break;
+         if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
+            res.data.s32 = ((int64_t)a->data.s32 * b->data.s32) >> 32;
+            break;
+         }
+         /* fallthrough */
+      case TYPE_U32:
+         if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
+            res.data.u32 = ((uint64_t)a->data.u32 * b->data.u32) >> 32;
+            break;
+         }
+         res.data.u32 = a->data.u32 * b->data.u32; break;
       default:
          return;
       }
@@ -550,8 +561,9 @@ ConstantFolding::expr(Instruction *i,
       if (i->src(0).getImmediate(src0))
          expr(i, src0, *i->getSrc(1)->asImm());
    } else {
-      i->op = OP_MOV;
+      i->op = i->saturate ? OP_SAT : OP_MOV; /* SAT handled by unary() */
    }
+   i->subOp = 0;
 }
 
 void
@@ -601,6 +613,7 @@ ConstantFolding::unary(Instruction *i, const ImmediateValue &imm)
    switch (i->op) {
    case OP_NEG: res.data.f32 = -imm.reg.data.f32; break;
    case OP_ABS: res.data.f32 = fabsf(imm.reg.data.f32); break;
+   case OP_SAT: res.data.f32 = CLAMP(imm.reg.data.f32, 0.0f, 1.0f); break;
    case OP_RCP: res.data.f32 = 1.0f / imm.reg.data.f32; break;
    case OP_RSQ: res.data.f32 = 1.0f / sqrtf(imm.reg.data.f32); break;
    case OP_LG2: res.data.f32 = log2f(imm.reg.data.f32); break;
@@ -690,12 +703,41 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
 {
    const int t = !s;
    const operation op = i->op;
+   Instruction *newi = i;
 
    switch (i->op) {
    case OP_MUL:
       if (i->dType == TYPE_F32)
          tryCollapseChainedMULs(i, s, imm0);
 
+      if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
+         assert(!isFloatType(i->sType));
+         if (imm0.isInteger(1) && i->dType == TYPE_S32) {
+            bld.setPosition(i, false);
+            // Need to set to the sign value, which is a compare.
+            newi = bld.mkCmp(OP_SET, CC_LT, TYPE_S32, i->getDef(0),
+                             TYPE_S32, i->getSrc(t), bld.mkImm(0));
+            delete_Instruction(prog, i);
+         } else if (imm0.isInteger(0) || imm0.isInteger(1)) {
+            // The high bits can't be set in this case (either mul by 0 or
+            // unsigned by 1)
+            i->op = OP_MOV;
+            i->subOp = 0;
+            i->setSrc(0, new_ImmediateValue(prog, 0u));
+            i->src(0).mod = Modifier(0);
+            i->setSrc(1, NULL);
+         } else if (!imm0.isNegative() && imm0.isPow2()) {
+            // Translate into a shift
+            imm0.applyLog2();
+            i->op = OP_SHR;
+            i->subOp = 0;
+            imm0.reg.data.u32 = 32 - imm0.reg.data.u32;
+            i->setSrc(0, i->getSrc(t));
+            i->src(0).mod = i->src(t).mod;
+            i->setSrc(1, new_ImmediateValue(prog, imm0.reg.data.u32));
+            i->src(1).mod = 0;
+         }
+      } else
       if (imm0.isInteger(0)) {
          i->op = OP_MOV;
          i->setSrc(0, new_ImmediateValue(prog, 0u));
@@ -786,7 +828,7 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
          else
             tA = tB;
          tB = s ? bld.getSSA() : i->getDef(0);
-         bld.mkOp2(OP_ADD, TYPE_U32, tB, mul->getDef(0), tA);
+         newi = bld.mkOp2(OP_ADD, TYPE_U32, tB, mul->getDef(0), tA);
          if (s)
             bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), tB, bld.mkImm(s));
 
@@ -818,7 +860,7 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
          tA = bld.getSSA();
          bld.mkCmp(OP_SET, CC_LT, TYPE_S32, tA, TYPE_S32, i->getSrc(0), bld.mkImm(0));
          tD = (d < 0) ? bld.getSSA() : i->getDef(0)->asLValue();
-         bld.mkOp2(OP_SUB, TYPE_U32, tD, tB, tA);
+         newi = bld.mkOp2(OP_SUB, TYPE_U32, tD, tB, tA);
          if (d < 0)
             bld.mkOp1(OP_NEG, TYPE_S32, i->getDef(0), tB);
 
@@ -882,6 +924,7 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
 
    case OP_ABS:
    case OP_NEG:
+   case OP_SAT:
    case OP_LG2:
    case OP_RCP:
    case OP_SQRT:
@@ -896,7 +939,7 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
    default:
       return;
    }
-   if (i->op != op)
+   if (newi->op != op)
       foldCount++;
 }
 

src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp

@@ -998,7 +998,9 @@ GCRA::doCoalesce(ArrayList& insns, unsigned int mask)
       case OP_TXQ:
       case OP_TXD:
       case OP_TXG:
+      case OP_TXLQ:
       case OP_TEXCSAA:
+      case OP_TEXPREP:
          if (!(mask & JOIN_MASK_TEX))
             break;
          for (c = 0; insn->srcExists(c) && c != insn->predSrc; ++c)

src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp

@@ -331,6 +331,8 @@ TargetNV50::insnCanLoad(const Instruction *i, int s,
          return false;
       if (sf == FILE_IMMEDIATE)
          return false;
+      if (i->subOp == NV50_IR_SUBOP_MUL_HIGH && sf == FILE_MEMORY_CONST)
+         return false;
       ldSize = 2;
    } else {
       ldSize = typeSizeof(ld->dType);

src/gallium/drivers/nouveau/nv30/nv30_context.c

@@ -165,6 +165,9 @@ nv30_context_destroy(struct pipe_context *pipe)
    if (nv30->draw)
       draw_destroy(nv30->draw);
 
+   if (nv30->screen->base.pushbuf->user_priv == &nv30->bufctx)
+      nv30->screen->base.pushbuf->user_priv = NULL;
+
    nouveau_bufctx_del(&nv30->bufctx);
 
    if (nv30->screen->cur_ctx == nv30)

src/gallium/drivers/nouveau/nv30/nv30_screen.c

@@ -325,6 +325,12 @@ nv30_screen_destroy(struct pipe_screen *pscreen)
       nouveau_fence_ref(NULL, &screen->base.fence.current);
    }
 
+   nouveau_bo_ref(NULL, &screen->notify);
+
+   nouveau_heap_destroy(&screen->query_heap);
+   nouveau_heap_destroy(&screen->vp_exec_heap);
+   nouveau_heap_destroy(&screen->vp_data_heap);
+
    nouveau_object_del(&screen->query);
    nouveau_object_del(&screen->fence);
    nouveau_object_del(&screen->ntfy);

src/gallium/drivers/nouveau/nv30/nv30_state.c

@@ -23,6 +23,7 @@
  *
  */
 
+#include "util/u_format.h"
 #include "util/u_helpers.h"
 #include "util/u_inlines.h"
 
@@ -360,6 +361,22 @@ nv30_set_framebuffer_state(struct pipe_context *pipe,
 
     nv30->framebuffer = *fb;
     nv30->dirty |= NV30_NEW_FRAMEBUFFER;
+
+   /* Hardware can't handle different swizzled-ness or different blocksizes
+    * for zs and cbufs. If both are supplied and something doesn't match,
+    * blank out the zs for now so that at least *some* rendering can occur.
+    */
+    if (fb->nr_cbufs > 0 && fb->zsbuf) {
+       struct nv30_miptree *color_mt = nv30_miptree(fb->cbufs[0]->texture);
+       struct nv30_miptree *zeta_mt = nv30_miptree(fb->zsbuf->texture);
+
+       if (color_mt->swizzled != zeta_mt->swizzled ||
+           (util_format_get_blocksize(fb->zsbuf->format) > 2) !=
+           (util_format_get_blocksize(fb->cbufs[0]->format) > 2)) {
+          nv30->framebuffer.zsbuf = NULL;
+          debug_printf("Mismatched color and zeta formats, ignoring zeta.\n");
+       }
+    }
 }
 
 static void

src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c

@@ -1225,6 +1225,7 @@ out:
    if(fpc)
    {
       FREE(fpc->r_temp);
+      FREE(fpc->r_imm);
       util_dynarray_fini(&fpc->if_stack);
       util_dynarray_fini(&fpc->label_relocs);
       util_dynarray_fini(&fpc->imm_data);

src/gallium/drivers/nouveau/nv50/nv50_context.c

@@ -61,7 +61,7 @@ static void
 nv50_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
    struct nv50_context *nv50 = nv50_context(pipe);
-   int i;
+   int i, s;
 
    if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
       for (i = 0; i < nv50->num_vtxbufs; ++i) {
@@ -74,6 +74,26 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned flags)
       if (nv50->idxbuf.buffer &&
           nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
          nv50->base.vbo_dirty = TRUE;
+
+      for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+         uint32_t valid = nv50->constbuf_valid[s];
+
+         while (valid && !nv50->cb_dirty) {
+            const unsigned i = ffs(valid) - 1;
+            struct pipe_resource *res;
+
+            valid &= ~(1 << i);
+            if (nv50->constbuf[s][i].user)
+               continue;
+
+            res = nv50->constbuf[s][i].u.buf;
+            if (!res)
+               continue;
+
+            if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+               nv50->cb_dirty = TRUE;
+         }
+      }
    }
 }
 
@@ -122,12 +142,9 @@ nv50_destroy(struct pipe_context *pipe)
 {
    struct nv50_context *nv50 = nv50_context(pipe);
 
-   if (nv50_context_screen(nv50)->cur_ctx == nv50) {
+   if (nv50_context_screen(nv50)->cur_ctx == nv50)
-      nv50->base.pushbuf->kick_notify = NULL;
       nv50_context_screen(nv50)->cur_ctx = NULL;
-      nouveau_pushbuf_bufctx(nv50->base.pushbuf, NULL);
+   nouveau_pushbuf_bufctx(nv50->base.pushbuf, NULL);
-   }
-   /* need to flush before destroying the bufctx */
    nouveau_pushbuf_kick(nv50->base.pushbuf, nv50->base.pushbuf->channel);
 
    nv50_context_unreference_resources(nv50);
@@ -256,7 +273,14 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
    nv50->base.screen    = &screen->base;
    nv50->base.copy_data = nv50_m2mf_copy_linear;
    nv50->base.push_data = nv50_sifc_linear_u8;
+   /* FIXME: Make it possible to use this again. The problem is that there is
+    * some clever logic in the card that allows for multiple renders to happen
+    * when there are only constbuf changes. However that relies on the
+    * constbuf updates happening to the right constbuf slots. Currently
+    * implementation just makes it go through a separate slot which doesn't
+    * properly update the right constbuf data.
    nv50->base.push_cb   = nv50_cb_push;
+    */
 
    nv50->screen = screen;
    pipe->screen = pscreen;

src/gallium/drivers/nouveau/nv50/nv50_context.h

@@ -78,16 +78,16 @@
 /* 8 user clip planes, at 4 32-bit floats each */
 #define NV50_CB_AUX_UCP_OFFSET    0x0000
 #define NV50_CB_AUX_UCP_SIZE      (8 * 4 * 4)
-/* 256 textures, each with ms_x, ms_y u32 pairs */
+/* 16 textures * 3 shaders, each with ms_x, ms_y u32 pairs */
 #define NV50_CB_AUX_TEX_MS_OFFSET 0x0080
-#define NV50_CB_AUX_TEX_MS_SIZE   (256 * 2 * 4)
+#define NV50_CB_AUX_TEX_MS_SIZE   (16 * 3 * 2 * 4)
 /* For each MS level (4), 8 sets of 32-bit integer pairs sample offsets */
-#define NV50_CB_AUX_MS_OFFSET     0x880
+#define NV50_CB_AUX_MS_OFFSET     0x200
 #define NV50_CB_AUX_MS_SIZE       (4 * 8 * 4 * 2)
 /* Sample position pairs for the current output MS level */
-#define NV50_CB_AUX_SAMPLE_OFFSET 0x980
+#define NV50_CB_AUX_SAMPLE_OFFSET 0x300
 #define NV50_CB_AUX_SAMPLE_OFFSET_SIZE (4 * 8 * 2)
-/* next spot: 0x9c0 */
+/* next spot: 0x340 */
 /* 4 32-bit floats for the vertex runout, put at the end */
 #define NV50_CB_AUX_RUNOUT_OFFSET (NV50_CB_AUX_SIZE - 0x10)
 
@@ -106,6 +106,7 @@ struct nv50_context {
    struct nouveau_bufctx *bufctx;
 
    uint32_t dirty;
+   boolean cb_dirty;
 
    struct {
       uint32_t instance_elts; /* bitmask of per-instance elements */

src/gallium/drivers/nouveau/nv50/nv50_query.c

@@ -332,7 +332,7 @@ nv50_render_condition(struct pipe_context *pipe,
    nv50->cond_cond = condition;
    nv50->cond_mode = mode;
 
-   PUSH_SPACE(push, 6);
+   PUSH_SPACE(push, 9);
 
    if (!pq) {
       BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
@@ -351,6 +351,10 @@ nv50_render_condition(struct pipe_context *pipe,
    PUSH_DATAh(push, q->bo->offset + q->offset);
    PUSH_DATA (push, q->bo->offset + q->offset);
    PUSH_DATA (push, NV50_3D_COND_MODE_RES_NON_ZERO);
+
+   BEGIN_NV04(push, NV50_2D(COND_ADDRESS_HIGH), 2);
+   PUSH_DATAh(push, q->bo->offset + q->offset);
+   PUSH_DATA (push, q->bo->offset + q->offset);
 }
 
 void

src/gallium/drivers/nouveau/nv50/nv50_screen.c

@@ -397,6 +397,8 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
    PUSH_DATA (push, 0);
    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
    PUSH_DATA (push, 1);
+   BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
+   PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 
    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
    PUSH_DATA (push, screen->tesla->handle);

src/gallium/drivers/nouveau/nv50/nv50_state_validate.c

@@ -400,6 +400,10 @@ nv50_switch_pipe_context(struct nv50_context *ctx_to)
    ctx_to->viewports_dirty = ~0;
    ctx_to->scissors_dirty = ~0;
 
+   ctx_to->constbuf_dirty[0] =
+   ctx_to->constbuf_dirty[1] =
+   ctx_to->constbuf_dirty[2] = (1 << NV50_MAX_PIPE_CONSTBUFS) - 1;
+
    if (!ctx_to->vertex)
       ctx_to->dirty &= ~(NV50_NEW_VERTEX | NV50_NEW_ARRAYS);
 

src/gallium/drivers/nouveau/nv50/nv50_surface.c

@@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
 
    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 
+   BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
+   PUSH_DATA (push, ( width << 16) | dstx);
+   PUSH_DATA (push, (height << 16) | dsty);
+   BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
+   PUSH_DATA (push, 8192 << 16);
+   PUSH_DATA (push, 8192 << 16);
+   nv50->scissors_dirty |= 1;
+
    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
    PUSH_DATA (push, 1);
    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
@@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
    }
 
-   nv50->dirty |= NV50_NEW_FRAMEBUFFER;
+   nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
 }
 
 static void
@@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
 
    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 
+   BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
+   PUSH_DATA (push, ( width << 16) | dstx);
+   PUSH_DATA (push, (height << 16) | dsty);
+   BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
+   PUSH_DATA (push, 8192 << 16);
+   PUSH_DATA (push, 8192 << 16);
+   nv50->scissors_dirty |= 1;
+
    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
    PUSH_DATAh(push, bo->offset + sf->offset);
    PUSH_DATA (push, bo->offset + sf->offset);
@@ -390,7 +406,7 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
    }
 
-   nv50->dirty |= NV50_NEW_FRAMEBUFFER;
+   nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
 }
 
 void
@@ -611,6 +627,7 @@ struct nv50_blitctx
    uint8_t mode;
    uint16_t color_mask;
    uint8_t filter;
+   uint8_t render_condition_enable;
    enum pipe_texture_target target;
    struct {
       struct pipe_framebuffer_state fb;
@@ -697,6 +714,12 @@ nv50_blitter_make_fp(struct pipe_context *pipe,
    tc = ureg_DECL_fs_input(
       ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
 
+   if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
+      /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
+      tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
+                        TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
+   }
+
    data = ureg_DECL_temporary(ureg);
 
    if (tex_s) {
@@ -933,7 +956,7 @@ nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
 {
    struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
 
-   if (blit->nv50->cond_query) {
+   if (blit->nv50->cond_query && !blit->render_condition_enable) {
       BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
       PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
    }
@@ -1071,7 +1094,7 @@ nv50_blitctx_post_blit(struct nv50_blitctx *blit)
    nv50->samplers[2][0] = blit->saved.sampler[0];
    nv50->samplers[2][1] = blit->saved.sampler[1];
 
-   if (nv50->cond_query)
+   if (nv50->cond_query && !blit->render_condition_enable)
       nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
                                        nv50->cond_cond, nv50->cond_mode);
 
@@ -1083,6 +1106,7 @@ nv50_blitctx_post_blit(struct nv50_blitctx *blit)
        NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
        NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
        NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
+   nv50->scissors_dirty |= 1;
 
    nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
 }
@@ -1105,6 +1129,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
    blit->mode = nv50_blit_select_mode(info);
    blit->color_mask = nv50_blit_derive_color_mask(info);
    blit->filter = nv50_blit_get_filter(info);
+   blit->render_condition_enable = info->render_condition_enable;
 
    nv50_blit_select_fp(blit, info);
    nv50_blitctx_pre_blit(blit);
@@ -1134,6 +1159,12 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
    y0 *= (float)(1 << nv50_miptree(src)->ms_y);
    y1 *= (float)(1 << nv50_miptree(src)->ms_y);
 
+   /* XXX: multiply by 6 for cube arrays ? */
+   dz = (float)info->src.box.depth / (float)info->dst.box.depth;
+   z = (float)info->src.box.z;
+   if (nv50_miptree(src)->layout_3d)
+      z += 0.5f * dz;
+
    if (src->last_level > 0) {
       /* If there are mip maps, GPU always assumes normalized coordinates. */
       const unsigned l = info->src.level;
@@ -1143,14 +1174,12 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
       x1 /= fh;
       y0 /= fv;
       y1 /= fv;
+      if (nv50_miptree(src)->layout_3d) {
+         z /= u_minify(src->depth0, l);
+         dz /= u_minify(src->depth0, l);
+      }
    }
 
-   /* XXX: multiply by 6 for cube arrays ? */
-   dz = (float)info->src.box.depth / (float)info->dst.box.depth;
-   z = (float)info->src.box.z;
-   if (nv50_miptree(src)->layout_3d)
-      z += 0.5f * dz;
-
    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
    PUSH_DATA (push, 0);
    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
@@ -1262,6 +1291,11 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
       PUSH_DATA (push, 1); /* enable */
    }
 
+   if (nv50->cond_query && info->render_condition_enable) {
+      BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
+      PUSH_DATA (push, NV50_2D_COND_MODE_RES_NON_ZERO);
+   }
+
    if (mask != 0xffffffff) {
       BEGIN_NV04(push, NV50_2D(ROP), 1);
       PUSH_DATA (push, 0xca); /* DPSDxax */
@@ -1384,6 +1418,10 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
       PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
    }
+   if (nv50->cond_query && info->render_condition_enable) {
+      BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
+      PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
+   }
 }
 
 static void

src/gallium/drivers/nouveau/nv50/nv50_tex.c

@@ -286,7 +286,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
    }
    if (nv50->num_textures[s]) {
       BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
-      PUSH_DATA (push, (NV50_CB_AUX_TEX_MS_OFFSET << (8 - 2)) | NV50_CB_AUX);
+      PUSH_DATA (push, ((NV50_CB_AUX_TEX_MS_OFFSET + 16 * s * 2 * 4) << (8 - 2)) | NV50_CB_AUX);
       BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
       for (i = 0; i < nv50->num_textures[s]; i++) {
          struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]);

src/gallium/drivers/nouveau/nv50/nv50_vbo.c

@@ -747,7 +747,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct nv50_context *nv50 = nv50_context(pipe);
    struct nouveau_pushbuf *push = nv50->base.pushbuf;
-   int i;
+   int i, s;
 
    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
    nv50->vb_elt_first = info->min_index + info->index_bias;
@@ -776,6 +776,33 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 
    push->kick_notify = nv50_draw_vbo_kick_notify;
 
+   for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+      uint32_t valid = nv50->constbuf_valid[s];
+
+      while (valid && !nv50->cb_dirty) {
+         const unsigned i = ffs(valid) - 1;
+         struct pipe_resource *res;
+
+         valid &= ~(1 << i);
+         if (nv50->constbuf[s][i].user)
+            continue;
+
+         res = nv50->constbuf[s][i].u.buf;
+         if (!res)
+            continue;
+
+         if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+            nv50->cb_dirty = TRUE;
+      }
+   }
+
+   /* If there are any coherent constbufs, flush the cache */
+   if (nv50->cb_dirty) {
+      BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
+      PUSH_DATA (push, 0);
+      nv50->cb_dirty = FALSE;
+   }
+
    if (nv50->vbo_fifo) {
       nv50_push_vbo(nv50, info);
       push->kick_notify = nv50_default_kick_notify;

src/gallium/drivers/nouveau/nvc0/nvc0_context.c

@@ -60,7 +60,7 @@ static void
 nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
    struct nvc0_context *nvc0 = nvc0_context(pipe);
-   int i;
+   int i, s;
 
    if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
       for (i = 0; i < nvc0->num_vtxbufs; ++i) {
@@ -73,6 +73,26 @@ nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags)
       if (nvc0->idxbuf.buffer &&
           nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
          nvc0->base.vbo_dirty = TRUE;
+
+      for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+         uint32_t valid = nvc0->constbuf_valid[s];
+
+         while (valid && !nvc0->cb_dirty) {
+            const unsigned i = ffs(valid) - 1;
+            struct pipe_resource *res;
+
+            valid &= ~(1 << i);
+            if (nvc0->constbuf[s][i].user)
+               continue;
+
+            res = nvc0->constbuf[s][i].u.buf;
+            if (!res)
+               continue;
+
+            if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+               nvc0->cb_dirty = TRUE;
+         }
+      }
    }
 }
 
@@ -123,11 +143,12 @@ nvc0_destroy(struct pipe_context *pipe)
 {
    struct nvc0_context *nvc0 = nvc0_context(pipe);
 
-   if (nvc0->screen->cur_ctx == nvc0) {
+   if (nvc0->screen->cur_ctx == nvc0)
-      nvc0->base.pushbuf->kick_notify = NULL;
       nvc0->screen->cur_ctx = NULL;
-      nouveau_pushbuf_bufctx(nvc0->base.pushbuf, NULL);
+   /* Unset bufctx, we don't want to revalidate any resources after the flush.
-   }
+    * Other contexts will always set their bufctx again on action calls.
+    */
+   nouveau_pushbuf_bufctx(nvc0->base.pushbuf, NULL);
    nouveau_pushbuf_kick(nvc0->base.pushbuf, nvc0->base.pushbuf->channel);
 
    nvc0_context_unreference_resources(nvc0);

src/gallium/drivers/nouveau/nvc0/nvc0_context.h

@@ -154,6 +154,8 @@ struct nvc0_context {
 
    struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS];
    uint16_t constbuf_dirty[6];
+   uint16_t constbuf_valid[6];
+   boolean cb_dirty;
 
    struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
    unsigned num_vtxbufs;

src/gallium/drivers/nouveau/nvc0/nvc0_program.c

@@ -133,17 +133,12 @@ static int
 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
 {
    unsigned count = info->prop.fp.numColourResults * 4;
-   unsigned i, c, ci;
+   unsigned i, c;
 
-   for (i = 0, ci = 0; i < info->numOutputs; ++i) {
+   for (i = 0; i < info->numOutputs; ++i)
-      if (info->out[i].sn == TGSI_SEMANTIC_COLOR) {
+      if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
          for (c = 0; c < 4; ++c)
-            info->out[i].slot[c] = ci * 4 + c;
+            info->out[i].slot[c] = info->out[i].si * 4 + c;
-         ci++;
-      }
-   }
-
-   assert(ci == info->prop.fp.numColourResults);
 
    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
       info->out[info->io.sampleMask].slot[0] = count++;

src/gallium/drivers/nouveau/nvc0/nvc0_query.c

@@ -585,12 +585,15 @@ nvc0_render_condition(struct pipe_context *pipe,
    if (wait)
       nvc0_query_fifo_wait(push, pq);
 
-   PUSH_SPACE(push, 4);
+   PUSH_SPACE(push, 7);
    PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
    BEGIN_NVC0(push, NVC0_3D(COND_ADDRESS_HIGH), 3);
    PUSH_DATAh(push, q->bo->offset + q->offset);
    PUSH_DATA (push, q->bo->offset + q->offset);
    PUSH_DATA (push, cond);
+   BEGIN_NVC0(push, NVC0_2D(COND_ADDRESS_HIGH), 2);
+   PUSH_DATAh(push, q->bo->offset + q->offset);
+   PUSH_DATA (push, q->bo->offset + q->offset);
 }
 
 void

src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

@@ -171,7 +171,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
       return 0;
    case PIPE_CAP_COMPUTE:
-      return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
+      return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
       return 1;
    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
@@ -211,7 +211,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
    case PIPE_SHADER_FRAGMENT:
       break;
    case PIPE_SHADER_COMPUTE:
-      if (class_3d < NVE4_3D_CLASS)
+      if (class_3d != NVE4_3D_CLASS)
          return 0;
       break;
    default:
@@ -514,9 +514,10 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
       return 0;
    case 0xe0:
+      return nve4_screen_compute_setup(screen, screen->base.pushbuf);
    case 0xf0:
    case 0x100:
-      return nve4_screen_compute_setup(screen, screen->base.pushbuf);
+      return 0;
    default:
       return -1;
    }
@@ -676,6 +677,8 @@ nvc0_screen_create(struct nouveau_device *dev)
    PUSH_DATA (push, 0x3f);
    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
    PUSH_DATA (push, 1);
+   BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
+   PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
 
    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->fence.bo->offset + 16);

src/gallium/drivers/nouveau/nvc0/nvc0_state.c

@@ -808,10 +808,15 @@ nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
    if (nvc0->constbuf[s][i].user) {
       nvc0->constbuf[s][i].u.data = cb->user_buffer;
       nvc0->constbuf[s][i].size = cb->buffer_size;
+      nvc0->constbuf_valid[s] |= 1 << i;
    } else
    if (cb) {
       nvc0->constbuf[s][i].offset = cb->buffer_offset;
       nvc0->constbuf[s][i].size = align(cb->buffer_size, 0x100);
+      nvc0->constbuf_valid[s] |= 1 << i;
+   }
+   else {
+      nvc0->constbuf_valid[s] &= ~(1 << i);
    }
 }
 

src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c

@@ -531,6 +531,7 @@ nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
    for (s = 0; s < 5; ++s) {
       ctx_to->samplers_dirty[s] = ~0;
       ctx_to->textures_dirty[s] = ~0;
+      ctx_to->constbuf_dirty[s] = (1 << NVC0_MAX_PIPE_CONSTBUFS) - 1;
    }
 
    if (!ctx_to->vertex)

src/gallium/drivers/nouveau/nvc0/nvc0_surface.c

@@ -503,6 +503,7 @@ struct nvc0_blitctx
    uint8_t mode;
    uint16_t color_mask;
    uint8_t filter;
+   uint8_t render_condition_enable;
    enum pipe_texture_target target;
    struct {
       struct pipe_framebuffer_state fb;
@@ -542,9 +543,22 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
       0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
       0x00001de7, 0x80000000, /* exit */
    };
+   static const uint32_t code_gk110[] =
+   {
+      0x00000000, 0x08000000, /* sched */
+      0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
+      0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
+      0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
+      0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
+      0x001c003c, 0x18000000, /* exit */
+   };
 
    blit->vp.type = PIPE_SHADER_VERTEX;
    blit->vp.translated = TRUE;
+   if (blit->screen->base.class_3d >= NVF0_3D_CLASS) {
+      blit->vp.code = (uint32_t *)code_gk110; /* const_cast */
+      blit->vp.code_size = sizeof(code_gk110);
+   } else
    if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
       blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
       blit->vp.code_size = sizeof(code_nve4);
@@ -691,7 +705,7 @@ nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
 
    /* TODO: maybe make this a MACRO (if we need more logic) ? */
 
-   if (blit->nvc0->cond_query)
+   if (blit->nvc0->cond_query && !blit->render_condition_enable)
       IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
 
    /* blend state */
@@ -833,7 +847,7 @@ nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
    nvc0->textures_dirty[4] |= 3;
    nvc0->samplers_dirty[4] |= 3;
 
-   if (nvc0->cond_query)
+   if (nvc0->cond_query && !blit->render_condition_enable)
       nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
                                        nvc0->cond_cond, nvc0->cond_mode);
 
@@ -868,6 +882,7 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    blit->mode = nv50_blit_select_mode(info);
    blit->color_mask = nv50_blit_derive_color_mask(info);
    blit->filter = nv50_blit_get_filter(info);
+   blit->render_condition_enable = info->render_condition_enable;
 
    nvc0_blit_select_fp(blit, info);
    nvc0_blitctx_pre_blit(blit);
@@ -894,6 +909,11 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
    y0 *= (float)(1 << nv50_miptree(src)->ms_y);
    y1 *= (float)(1 << nv50_miptree(src)->ms_y);
 
+   dz = (float)info->src.box.depth / (float)info->dst.box.depth;
+   z = (float)info->src.box.z;
+   if (nv50_miptree(src)->layout_3d)
+      z += 0.5f * dz;
+
    if (src->last_level > 0) {
       /* If there are mip maps, GPU always assumes normalized coordinates. */
       const unsigned l = info->src.level;
@@ -903,13 +923,12 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
       x1 /= fh;
       y0 /= fv;
       y1 /= fv;
+      if (nv50_miptree(src)->layout_3d) {
+         z /= u_minify(src->depth0, l);
+         dz /= u_minify(src->depth0, l);
+      }
    }
 
-   dz = (float)info->src.box.depth / (float)info->dst.box.depth;
-   z = (float)info->src.box.z;
-   if (nv50_miptree(src)->layout_3d)
-      z += 0.5f * dz;
-
    IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
    IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
               NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
@@ -1030,6 +1049,9 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
       PUSH_DATA (push, 1); /* enable */
    }
 
+   if (nvc0->cond_query && info->render_condition_enable)
+      IMMED_NVC0(push, NVC0_2D(COND_MODE), NVC0_2D_COND_MODE_RES_NON_ZERO);
+
    if (mask != 0xffffffff) {
       IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
       IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
@@ -1154,6 +1176,8 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
       IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
    if (mask != 0xffffffff)
       IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_SRCCOPY);
+   if (nvc0->cond_query && info->render_condition_enable)
+      IMMED_NVC0(push, NVC0_2D(COND_MODE), NVC0_2D_COND_MODE_ALWAYS);
 }
 
 static void

src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c

@@ -797,7 +797,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct nvc0_context *nvc0 = nvc0_context(pipe);
    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
-   int i;
+   int i, s;
 
    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
    nvc0->vb_elt_first = info->min_index + info->index_bias;
@@ -830,6 +830,31 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 
    push->kick_notify = nvc0_draw_vbo_kick_notify;
 
+   for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+      uint32_t valid = nvc0->constbuf_valid[s];
+
+      while (valid && !nvc0->cb_dirty) {
+         const unsigned i = ffs(valid) - 1;
+         struct pipe_resource *res;
+
+         valid &= ~(1 << i);
+         if (nvc0->constbuf[s][i].user)
+            continue;
+
+         res = nvc0->constbuf[s][i].u.buf;
+         if (!res)
+            continue;
+
+         if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+            nvc0->cb_dirty = TRUE;
+      }
+   }
+
+   if (nvc0->cb_dirty) {
+      IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
+      nvc0->cb_dirty = FALSE;
+   }
+
    if (nvc0->state.vbo_mode) {
       nvc0_push_vbo(nvc0, info);
       push->kick_notify = nvc0_default_kick_notify;

src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h

@@ -80,8 +80,9 @@ NVC0_FIFO_PKHDR_NI(int subc, int mthd, unsigned size)
 }
 
 static INLINE uint32_t
-NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint8_t data)
+NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint16_t data)
 {
+   assert(data < 0x2000);
    return 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2);
 }
 
@@ -133,7 +134,7 @@ BEGIN_1IC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size)
 }
 
 static INLINE void
-IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, uint8_t data)
+IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, uint16_t data)
 {
 #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING
    PUSH_SPACE(push, 1);

src/gallium/drivers/r600/r600_blit.c

@@ -789,7 +789,8 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 	    info->src.box.width == dst_width &&
 	    info->src.box.height == dst_height &&
 	    info->src.box.depth == 1 &&
-	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D) {
+	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
+	    (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
 		r600_blitter_begin(ctx, R600_COLOR_RESOLVE);
 		util_blitter_custom_resolve_color(rctx->blitter,
 						  info->dst.resource, info->dst.level,

src/gallium/drivers/r600/r600_pipe.h

@@ -829,15 +829,6 @@ static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 }
 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 
-static inline unsigned r600_tex_aniso_filter(unsigned filter)
-{
-	if (filter <= 1)   return 0;
-	if (filter <= 2)   return 1;
-	if (filter <= 4)   return 2;
-	if (filter <= 8)   return 3;
-	 /* else */        return 4;
-}
-
 /* 12.4 fixed-point */
 static INLINE unsigned r600_pack_float_12p4(float x)
 {

src/gallium/drivers/radeon/r600_pipe_common.h

@@ -489,6 +489,15 @@ r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 				(struct pipe_resource *)res);
 }
 
+static inline unsigned r600_tex_aniso_filter(unsigned filter)
+{
+	if (filter <= 1)   return 0;
+	if (filter <= 2)   return 1;
+	if (filter <= 4)   return 2;
+	if (filter <= 8)   return 3;
+	 /* else */        return 4;
+}
+
 #define R600_ERR(fmt, args...) \
 	fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 

src/gallium/drivers/radeon/r600_texture.c

@@ -1235,6 +1235,9 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 {
 	int i;
 
+	if (rctx->current_render_cond)
+		return;
+
 	for (i = 0; i < fb->nr_cbufs; i++) {
 		struct r600_texture *tex;
 		unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;

src/gallium/drivers/radeon/radeon_llvm_util.c

@@ -100,13 +100,17 @@ LLVMModuleRef radeon_llvm_get_kernel_module(LLVMContextRef ctx, unsigned index,
 	kernel_metadata = MALLOC(num_kernels * sizeof(LLVMValueRef));
 	LLVMGetNamedMetadataOperands(mod, "opencl.kernels", kernel_metadata);
 	for (i = 0; i < num_kernels; i++) {
-		LLVMValueRef kernel_signature, kernel_function;
+		LLVMValueRef kernel_signature, *kernel_function;
+		unsigned num_kernel_md_operands;
 		if (i == index) {
 			continue;
 		}
 		kernel_signature = kernel_metadata[i];
-		LLVMGetMDNodeOperands(kernel_signature, &kernel_function);
+		num_kernel_md_operands = LLVMGetMDNodeNumOperands(kernel_signature);
-		LLVMDeleteFunction(kernel_function);
+		kernel_function = MALLOC(num_kernel_md_operands * sizeof (LLVMValueRef));
+		LLVMGetMDNodeOperands(kernel_signature, kernel_function);
+		LLVMDeleteFunction(*kernel_function);
+		FREE(kernel_function);
 	}
 	FREE(kernel_metadata);
 	radeon_llvm_optimize(mod);

src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c

@@ -1378,7 +1378,11 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 	bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
 
 	bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
+#if HAVE_LLVM >= 0x0305
+	bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq.clamped.f32";
+#else
 	bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
+#endif
 }
 
 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,

src/gallium/drivers/radeon/radeon_video.c

@@ -242,7 +242,10 @@ int rvid_get_video_param(struct pipe_screen *screen,
 		switch (param) {
 		case PIPE_VIDEO_CAP_SUPPORTED:
 			/* no support for MPEG4 */
-			return codec != PIPE_VIDEO_FORMAT_MPEG4;
+			return codec != PIPE_VIDEO_FORMAT_MPEG4 &&
+			       /* FIXME: VC-1 simple/main profile is broken */
+			       profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE &&
+			       profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
 		case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 		case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 			/* and MPEG2 only with shaders */

src/gallium/drivers/radeonsi/si_blit.c

@@ -689,7 +689,8 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 	    info->src.box.height == dst_height &&
 	    info->src.box.depth == 1 &&
 	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
-	    !(dst->surface.flags & RADEON_SURF_SCANOUT)) {
+	    !(dst->surface.flags & RADEON_SURF_SCANOUT) &&
+	    (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
 		si_blitter_begin(ctx, SI_COLOR_RESOLVE);
 		util_blitter_custom_resolve_color(sctx->blitter,
 						  info->dst.resource, info->dst.level,

src/gallium/drivers/radeonsi/si_descriptors.c

@@ -152,7 +152,7 @@ static void si_update_descriptors(struct si_context *sctx,
 			7 + /* copy */
 			(4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
 			4; /* pointer update */
-#if HAVE_LLVM >= 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
 		if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
 		    desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0)
 			desc->atom.num_dw += 4; /* second pointer update */
@@ -177,7 +177,7 @@ static void si_emit_shader_pointer(struct si_context *sctx,
 	radeon_emit(cs, va);
 	radeon_emit(cs, va >> 32);
 
-#if HAVE_LLVM >= 0x0305
+#if LLVM_SUPPORTS_GEOM_SHADERS
 	if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
 	    desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) {
 		radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));

src/gallium/drivers/radeonsi/si_pipe.c

@@ -224,7 +224,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 		return 4;
 
 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
-		return HAVE_LLVM >= 0x0305 ? 330 : 140;
+		return (LLVM_SUPPORTS_GEOM_SHADERS) ? 330 : 140;
 
 	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 		return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
@@ -308,7 +308,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
 	case PIPE_SHADER_VERTEX:
 		break;
 	case PIPE_SHADER_GEOMETRY:
-#if HAVE_LLVM < 0x0305
+#if !(LLVM_SUPPORTS_GEOM_SHADERS)
 		return 0;
 #endif
 		break;

src/gallium/drivers/radeonsi/si_pipe.h

@@ -39,6 +39,10 @@
 
 #define SI_MAX_DRAW_CS_DWORDS 18
 
+#define LLVM_SUPPORTS_GEOM_SHADERS \
+	((HAVE_LLVM >= 0x0305) || \
+	(HAVE_LLVM == 0x0304 && LLVM_VERSION_PATCH >= 1))
+
 struct si_pipe_compute;
 
 struct si_screen {