docs: Add release notes for 10.2.5

Update version to 10.2.5
In preparation for the 10.2.5 release, of course.
2014-08-02 19:06:05 -07:00 · 2014-08-02 19:03:34 -07:00 · 2014-07-31 15:23:14 -07:00 · 2014-07-31 15:22:49 -07:00 · 2014-07-31 15:22:21 -07:00 · 2014-07-30 22:09:46 -07:00
131 changed files with 1716 additions and 382 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-10.2.0
+10.2.5
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,3 +1,18 @@
 # The first is the change, and the second is the revert of that change.
 e6967270c75a5b669152127bb7a746d55f4407a6 i965: Fix depth (array slices) computation for 1D_ARRAY render targets.
 155f98d49fdc2f46c760f8214327b3804ee60079 Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."
+
+# This patch didn't have enough in the commit message to convince me it
+# is a bug fix, (email sent to author asking for more information).
+41d759d076737f94976f5294b734dbc437a12bae
+
+# These patch were already cherry-picked before the 10.2.4 release.
+#
+# But get-pick-list.sh doesn't realize that because the commit messages for
+# these on the stable branch reference commit IDs that don't actually appear
+# on master. I'm not sure what happened, (perhaps master was force-pushed at
+# some point?).
+2eaf3f670fea4ce4466340141244e41a45542c13
+e5adc560cc8544200faa3e04504202839626ab37
+cf1b5eee7f36af29d1d5caba3538ad4985e51f81
+
--- a/configure.ac
+++ b/configure.ac
@@ -1324,7 +1324,7 @@ AM_CONDITIONAL(HAVE_OPENVG, test "x$enable_openvg" = xyes)
 dnl
 dnl Gallium G3DVL configuration
 dnl
-if test -n "$with_gallium_drivers" && ! echo "$with_gallium_drivers" | grep -q 'swrast'; then
+if test -n "$with_gallium_drivers" -a "x$with_gallium_drivers" != xswrast; then
    if test "x$enable_xvmc" = xauto; then
 	PKG_CHECK_EXISTS([xvmc], [enable_xvmc=yes], [enable_xvmc=no])
    fi
@@ -1673,6 +1673,10 @@ if test "x$enable_gallium_llvm" = xyes; then
 else
    MESA_LLVM=0
    LLVM_VERSION_INT=0
+
+    if test "x$enable_opencl" = xyes; then
+        AC_MSG_ERROR([cannot enable OpenCL without LLVM])
+    fi
 fi

 dnl Directory for XVMC libs
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,20 @@

 <h1>News</h1>

+<h2>June 6, 2014</h2>
+<p>
+<a href="relnotes/10.2.1.html">Mesa 10.2.1</a> is released.  This release
+only fixes a build error in the radeonsi driver that was introduced between
+10.2-rc5 and the 10.2 final release.
+</p>
+
+<h2>June 6, 2014</h2>
+<p>
+<a href="relnotes/10.2.html">Mesa 10.2</a> is released.  This is a new
+development release.  See the release notes for more information about
+the release.
+</p>
+
 <h2>April 18, 2014</h2>
 <p>
 <a href="relnotes/10.1.1.html">Mesa 10.1.1</a> is released.
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,8 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>

 <ul>
+<li><a href="relnotes/10.2.1.html">10.2.1 release notes</a>
+<li><a href="relnotes/10.2.html">10.2 release notes</a>
 <li><a href="relnotes/10.1.1.html">10.1.1 release notes</a>
 <li><a href="relnotes/10.1.html">10.1 release notes</a>
 <li><a href="relnotes/10.0.5.html">10.0.5 release notes</a>
--- a/docs/relnotes/10.2.1.html
+++ b/docs/relnotes/10.2.1.html
@@ -0,0 +1,61 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.1 Release Notes / June 6, 2014</h1>
+
+<p>
+Mesa 10.2.1 is a bug fix release which fixes bugs found since the 10.1 release.
+</p>
+<p>
+Mesa 10.2.1 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+96f892dae2d0bb14ac9c2113f586c909  MesaLib-10.2.1.tar.gz
+093f9b5d077e5f6061dcd7b01b7aa51a  MesaLib-10.2.1.tar.bz2
+6ab76c1608e5deed1eb8b54c62d7a48a  MesaLib-10.2.1.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>
+Mesa 10.2 had a build problem in the radeonsi driver due to an error resolving
+conflicts in a patch cherry-pick from master.  The build error is fixed.
+</p>
+
+<h2>Changes</h2>
+
+<p>Ian Romanick (3):</p>
+<ul>
+  <li>docs: Add MD5 checksum, etc. for 10.1 release</li>
+  <li>radeonsi: Fix build error introduced in 5ab9a9c</li>
+  <li>Bump version to 10.2.1</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.2.2.html
+++ b/docs/relnotes/10.2.2.html
@@ -0,0 +1,181 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.2 Release Notes / June 24, 2014</h1>
+
+<p>
+Mesa 10.2.2 is a bug fix release which fixes bugs found since the 10.2.1 release.
+</p>
+<p>
+Mesa 10.2.2 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+38c4a40364000f89cddaa1694f6f3cfb444981d1110238ce603093585477399c  MesaLib-10.2.2.tar.bz2
+2af2ec8b4db624c352e961eefbcce6c8d1f86d44c5542f6f378c50e1b958d453  MesaLib-10.2.2.tar.gz
+d4c0372da59367a344d62ebcdf5cf61039c9cae6925f40f2dab8f8d95cf22da9  MesaLib-10.2.2.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54372">Bug 54372</a> - GLX_INTEL_swap_event crashes driver when swapping window buffers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=66452">Bug 66452</a> - JUNIPER UVD accelerated playback of WMV3 streams does not work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=74005">Bug 74005</a> - [i965 Bisected]Piglit/glx_glx-make-glxdrawable-current fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=77865">Bug 77865</a> - [BDW] Many Ogles3conform framebuffer_blit cases fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78581">Bug 78581</a> - OpenCL: clBuildProgram prints error messages directly rather than storing them</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79029">Bug 79029</a> - INTEL_DEBUG=shader_time is full of lies</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79729">Bug 79729</a> - [i965] glClear on a multisample texture doesn't work</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79907">Bug 79907</a> - Mesa 10.2.1 --enable-vdpau default=auto broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80115">Bug 80115</a> - MESA_META_DRAW_BUFFERS induced GL_INVALID_VALUE errors</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Adrian Negreanu (8):</p>
+<ul>
+  <li>add megadriver_stub_FILES</li>
+  <li>android: adapt to the megadriver mechanism</li>
+  <li>android: add libloader to libGLES_mesa and libmesa_egl_dri2</li>
+  <li>android: add src/gallium/auxiliary as include path for libmesa_dricore</li>
+  <li>android, egl: add correct drm include for libmesa_egl_dri2</li>
+  <li>android, egl: typo dri2_fallback_pixmap_surface -&gt; dri2_fallback_create_pixmap_surface</li>
+  <li>android, mesa_gen_matypes: pull in timespec POSIX definition</li>
+  <li>android, dricore: undefined reference to _mesa_streaming_load_memcpy</li>
+</ul>
+
+<p>Carl Worth (1):</p>
+<ul>
+  <li>Update VERSION to 10.2.2</li>
+</ul>
+
+<p>Daniel Manjarres (1):</p>
+<ul>
+  <li>glx: Don't crash on swap event for a Window (non-GLXWindow)</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>targets/xa: limit the amount of exported symbols</li>
+  <li>configure: error out when building opencl without LLVM</li>
+  <li>configure: correctly autodetect xvmc/vdpau/omx</li>
+</ul>
+
+<p>Grigori Goronzy (1):</p>
+<ul>
+  <li>radeon/uvd: disable VC-1 simple/main on UVD 2.x</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+  <li>mesa: Copy Geom.UsesEndPrimitive when cloning a geometry program.</li>
+</ul>
+
+<p>Ian Romanick (3):</p>
+<ul>
+  <li>docs: Add initial 10.2.1 release notes</li>
+  <li>docs: Add MD5 checksum, etc. for 10.2.1 release</li>
+  <li>meta: Respect the driver's maximum number of draw buffers</li>
+</ul>
+
+<p>Ilia Mirkin (7):</p>
+<ul>
+  <li>gk110/ir: emit saturate flag on fadd when needed</li>
+  <li>gk110/ir: fix emitting constbuf file index</li>
+  <li>gk110/ir: fix bfind emission</li>
+  <li>nv50: make sure to mark first scissor dirty after blit</li>
+  <li>nv30: plug some memory leaks on screen destroy and shader compile</li>
+  <li>nv30: avoid dangling references to deleted contexts</li>
+  <li>nv30: hack to avoid errors on unexpected color/zeta combinations</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>meta_blit: properly compute texture width for the CopyTexSubImage fallback</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>mesa/main: Prevent sefgault on glGetIntegerv(GL_ATOMIC_COUNTER_BUFFER_BINDING).</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+  <li>i965: Don't use the head sentinel as an fs_inst in Gen4 workaround code.</li>
+  <li>i965: Invalidate live intervals when inserting Gen4 SEND workarounds.</li>
+  <li>i965/vec4: Fix dead code elimination for VGRFs of size &gt; 1.</li>
+  <li>i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.</li>
+  <li>i965: Drop Broadwell perf_debugs about missing MOCS that aren't missing.</li>
+  <li>i965: Add missing newlines to a few perf_debug messages.</li>
+  <li>i965/vec4: Use the sampler for pull constant loads on Broadwell.</li>
+  <li>i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.</li>
+  <li>i965: Save meta stencil blit programs in the context.</li>
+</ul>
+
+<p>Kristian Høgsberg (1):</p>
+<ul>
+  <li>mesa: Remove glClear optimization based on drawable size</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>configure: Only check for OpenCL without LLVM when the latter is certain</li>
+</ul>
+
+<p>Neil Roberts (1):</p>
+<ul>
+  <li>i965: Set the fast clear color value for texture surfaces</li>
+</ul>
+
+<p>Tom Stellard (2):</p>
+<ul>
+  <li>clover: Prevent Clang from printing number of errors and warnings to stderr.</li>
+  <li>clover: Don't use llvm's global context</li>
+</ul>
+
+<p>Ville Syrjälä (1):</p>
+<ul>
+  <li>i915: Fix gen2 texblend setup</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.2.3.html
+++ b/docs/relnotes/10.2.3.html
@@ -0,0 +1,130 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.3 Release Notes / July 7, 2014</h1>
+
+<p>
+Mesa 10.2.3 is a bug fix release which fixes bugs found since the 10.2.2 release.
+</p>
+<p>
+Mesa 10.2.3 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+e482a96170c98b17d6aba0d6e4dda4b9a2e61c39587bb64ac38cadfa4aba4aeb  MesaLib-10.2.3.tar.bz2
+96cffacaa1c52ae659b3b0f91be2eebf5528b748934256751261fb79ea3d6636  MesaLib-10.2.3.tar.gz
+82cab6ff14c8038ee39842dbdea0d447a78d119efd8d702d1497bc7c246434e9  MesaLib-10.2.3.zip
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=76223">Bug 76223</a> - </li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=79823">Bug 79823</a> - </li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80015">Bug 80015</a> - </li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Aaron Watry (1):</p>
+<ul>
+  <li>radeon/llvm: Allocate space for kernel metadata operands</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.2.2 release</li>
+  <li>cherry-ignore: Add a patch that's been rejected</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+  <li>nouveau: dup fd before passing it to device</li>
+  <li>nv50: disable dedicated ubo upload method</li>
+  <li>nv50: do an explicit flush on draw when there are persistent buffers</li>
+  <li>nvc0: add a memory barrier when there are persistent UBOs</li>
+</ul>
+
+<p>Jasper St. Pierre (1):</p>
+<ul>
+  <li>glxext: Send the Drawable's ID in the GLX_BufferSwapComplete event</li>
+</ul>
+
+<p>Kenneth Graunke (3):</p>
+<ul>
+  <li>i965: Don't emit SURFACE_STATEs for gather workarounds on Broadwell.</li>
+  <li>i965: Include marketing names for Broadwell GPUs.</li>
+  <li>i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeon/llvm: Use the llvm.rsq.clamped intrinsic for RSQ</li>
+</ul>
+
+<p>Rob Clark (9):</p>
+<ul>
+  <li>xa: fix segfault</li>
+  <li>freedreno: use OUT_RELOCW when buffer is written</li>
+  <li>freedreno/a3xx: fix depth/stencil GMEM positioning</li>
+  <li>freedreno/a3xx: fix depth/stencil gmem restore</li>
+  <li>freedreno/a3xx: fix blend opcode</li>
+  <li>freedreno: few caps fixes</li>
+  <li>freedreno/a3xx: texture fixes</li>
+  <li>freedreno: fix for null textures</li>
+  <li>freedreno/a3xx: vtx formats</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+  <li>draw: (trivial) fix clamping of viewport index</li>
+</ul>
+
+<p>Takashi Iwai (1):</p>
+<ul>
+  <li>llvmpipe: Fix zero-division in llvmpipe_texture_layout()</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+  <li>st/xa: Don't close the drm fd on failure v2</li>
+</ul>
+
+<p>Tobias Klausmann (1):</p>
+<ul>
+  <li>nv50/ir: allow gl_ViewportIndex to work on non-provoking vertices</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.2.4.html
+++ b/docs/relnotes/10.2.4.html
@@ -0,0 +1,127 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.4 Release Notes / July 18, 2014</h1>
+
+<p>
+Mesa 10.2.4 is a bug fix release which fixes bugs found since the 10.2.3 release.
+</p>
+<p>
+Mesa 10.2.4 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+06a2341244eb85c283f59f70161e06ded106f835ed9b6be1ef0243bd9344811a  MesaLib-10.2.4.tar.bz2
+33e3c8b4343503e7d7d17416c670438860a2fd99ec93ea3327f73c3abe33b5e4  MesaLib-10.2.4.tar.gz
+e26791a4a62a61b82e506e6ba031812d09697d1a831e8239af67e5722a8ee538  MesaLib-10.2.4.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=81157">Bug 81157</a> - [BDW]Piglit some spec_glsl-1.50_execution_built-in-functions* cases fail</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Abdiel Janulgue (3):</p>
+<ul>
+  <li>i965/fs: Refactor check for potential copy propagated instructions.</li>
+  <li>i965/fs: skip copy-propate for logical instructions with negated src entries</li>
+  <li>i965/vec4: skip copy-propate for logical instructions with negated src entries</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+  <li>mesa: fix geometry shader memory leaks</li>
+  <li>st/mesa: fix geometry shader memory leak</li>
+  <li>gallium/u_blitter: fix some shader memory leaks</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+  <li>docs: Add sha256 checksums for the 10.2.3 release</li>
+  <li>Update VERSION to 10.2.4</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>i965: Generalize the pixel_x/y workaround for all UW types.</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+  <li>nv50/ir: retrieve shadow compare from first arg</li>
+  <li>nv50/ir: ignore bias for samplerCubeShadow on nv50</li>
+  <li>nvc0/ir: do quadops on the right texture coordinates for TXD</li>
+  <li>nvc0/ir: use manual TXD when offsets are involved</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+  <li>i965: Add auxiliary surface field #defines for Broadwell.</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+  <li>i965: Don't copy propagate abs into Broadwell logic instructions.</li>
+  <li>i965: Set execution size to 8 for instructions with force_sechalf set.</li>
+  <li>i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.</li>
+  <li>i965/fs: Use WE_all for gl_SampleID header register munging.</li>
+  <li>i965: Add plumbing for Broadwell's auxiliary surface support.</li>
+  <li>i965: Drop SINT workaround for CMS layout on Broadwell.</li>
+  <li>i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.</li>
+  <li>i965: Add 2x MSAA support to the MCS allocation function.</li>
+  <li>i965: Enable compressed multisample support (CMS) on Broadwell.</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>gallium: fix u_default_transfer_inline_write for textures</li>
+  <li>st/mesa: fix samplerCubeShadow with bias</li>
+  <li>radeonsi: fix samplerCubeShadow with bias</li>
+  <li>radeonsi: add support for TXB2</li>
+</ul>
+
+<p>Matt Turner (8):</p>
+<ul>
+  <li>i965/vec4: Don't return void from a void function.</li>
+  <li>i965/vec4: Don't fix_math_operand() on Gen &gt;= 8.</li>
+  <li>i965/fs: Don't fix_math_operand() on Gen &gt;= 8.</li>
+  <li>i965/fs: Make try_constant_propagate() static.</li>
+  <li>i965/fs: Constant propagate into 2-src math instructions on Gen8.</li>
+  <li>i965/vec4: Constant propagate into 2-src math instructions on Gen8.</li>
+  <li>i965/fs: Don't use brw_imm_* unnecessarily.</li>
+  <li>i965/fs: Set correct number of regs_written for MCS fetches.</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.2.5.html
+++ b/docs/relnotes/10.2.5.html
@@ -0,0 +1,185 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.5 Release Notes / August 2, 2014</h1>
+
+<p>
+Mesa 10.2.5 is a bug fix release which fixes bugs found since the 10.2.4 release.
+</p>
+<p>
+Mesa 10.2.5 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80991">Bug 80991</a> - [BDW]Piglit spec_ARB_sample_shading_builtin-gl-sample-mask_2 fails</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Abdiel Janulgue (3):</p>
+<ul>
+  <li>i965/fs: Refactor check for potential copy propagated instructions.</li>
+  <li>i965/fs: skip copy-propate for logical instructions with negated src entries</li>
+  <li>i965/vec4: skip copy-propate for logical instructions with negated src entries</li>
+</ul>
+
+<p>Adel Gadllah (1):</p>
+<ul>
+  <li>i915: Fix up intelInitScreen2 for DRI3</li>
+</ul>
+
+<p>Anuj Phogat (2):</p>
+<ul>
+  <li>i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()</li>
+  <li>mesa: Don't use memcpy() in _mesa_texstore() for float depth texture data</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+  <li>mesa: fix geometry shader memory leaks</li>
+  <li>st/mesa: fix geometry shader memory leak</li>
+  <li>gallium/u_blitter: fix some shader memory leaks</li>
+</ul>
+
+<p>Carl Worth (6):</p>
+<ul>
+  <li>docs: Add sha256 checksums for the 10.2.3 release</li>
+  <li>Update VERSION to 10.2.4</li>
+  <li>Add release notes for 10.2.4</li>
+  <li>docs: Add SHA256 checksums for the 10.2.4 release</li>
+  <li>cherry-ignore: Ignore a few patches picked in the previous stable release</li>
+  <li>Update version to 10.2.5</li>
+</ul>
+
+<p>Christian König (1):</p>
+<ul>
+  <li>radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>i965: Generalize the pixel_x/y workaround for all UW types.</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>mesa: Don't allow GL_TEXTURE_BORDER queries outside compat profile</li>
+  <li>mesa: Don't allow GL_TEXTURE_{LUMINANCE,INTENSITY}_* queries outside compat profile</li>
+</ul>
+
+<p>Ilia Mirkin (5):</p>
+<ul>
+  <li>nv50/ir: retrieve shadow compare from first arg</li>
+  <li>nv50/ir: ignore bias for samplerCubeShadow on nv50</li>
+  <li>nvc0/ir: do quadops on the right texture coordinates for TXD</li>
+  <li>nvc0/ir: use manual TXD when offsets are involved</li>
+  <li>nvc0: make sure that the local memory allocation is aligned to 0x10</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>main/format_pack: Fix a wrong datatype in pack_ubyte_R8G8_UNORM</li>
+  <li>main/get_hash_params: Add GL_SAMPLE_SHADING_ARB</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+  <li>i965: Add auxiliary surface field #defines for Broadwell.</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>st/wgl: Clamp wglChoosePixelFormatARB's output nNumFormats to nMaxFormats.</li>
+</ul>
+
+<p>Kenneth Graunke (13):</p>
+<ul>
+  <li>i965: Don't copy propagate abs into Broadwell logic instructions.</li>
+  <li>i965: Set execution size to 8 for instructions with force_sechalf set.</li>
+  <li>i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.</li>
+  <li>i965/fs: Use WE_all for gl_SampleID header register munging.</li>
+  <li>i965: Add plumbing for Broadwell's auxiliary surface support.</li>
+  <li>i965: Drop SINT workaround for CMS layout on Broadwell.</li>
+  <li>i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.</li>
+  <li>i965: Add 2x MSAA support to the MCS allocation function.</li>
+  <li>i965: Enable compressed multisample support (CMS) on Broadwell.</li>
+  <li>i965: Add missing persample_shading field to brw_wm_debug_recompile.</li>
+  <li>i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.</li>
+  <li>i965/fs: Fix gl_SampleMask handling for SIMD16 on Gen8+.</li>
+  <li>i965/fs: Set LastRT on the final FB write on Broadwell.</li>
+</ul>
+
+<p>Marek Olšák (14):</p>
+<ul>
+  <li>gallium: fix u_default_transfer_inline_write for textures</li>
+  <li>st/mesa: fix samplerCubeShadow with bias</li>
+  <li>radeonsi: fix samplerCubeShadow with bias</li>
+  <li>radeonsi: add support for TXB2</li>
+  <li>r600g: switch SNORM conversion to DX and GLES behavior</li>
+  <li>radeonsi: fix CMASK and HTILE calculations for Hawaii</li>
+  <li>gallium/util: add a helper for calculating primitive count from vertex count</li>
+  <li>radeonsi: fix a hang with instancing on Hawaii</li>
+  <li>radeonsi: fix a hang with streamout on Hawaii</li>
+  <li>winsys/radeon: fix vram_size overflow with Hawaii</li>
+  <li>radeonsi: fix occlusion queries on Hawaii</li>
+  <li>r600g,radeonsi: switch all occurences of array_size to util_max_layer</li>
+  <li>radeonsi: fix build because of lack of draw_indirect infrastructure in 10.2</li>
+  <li>radeonsi: use DRAW_PREAMBLE on CIK</li>
+</ul>
+
+<p>Matt Turner (8):</p>
+<ul>
+  <li>i965/vec4: Don't return void from a void function.</li>
+  <li>i965/vec4: Don't fix_math_operand() on Gen &gt;= 8.</li>
+  <li>i965/fs: Don't fix_math_operand() on Gen &gt;= 8.</li>
+  <li>i965/fs: Make try_constant_propagate() static.</li>
+  <li>i965/fs: Constant propagate into 2-src math instructions on Gen8.</li>
+  <li>i965/vec4: Constant propagate into 2-src math instructions on Gen8.</li>
+  <li>i965/fs: Don't use brw_imm_* unnecessarily.</li>
+  <li>i965/fs: Set correct number of regs_written for MCS fetches.</li>
+</ul>
+
+<p>Thorsten Glaser (1):</p>
+<ul>
+  <li>nv50: fix build failure on m68k due to invalid struct alignment assumptions</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>clover: Call end_query before getting timestamp result v2</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.2.html
+++ b/docs/relnotes/10.2.html
@@ -14,7 +14,7 @@
 <iframe src="../contents.html"></iframe>
 <div class="content">

-<h1>Mesa 10.2 Release Notes / TBD</h1>
+<h1>Mesa 10.2 Release Notes / June 6, 2014</h1>

 <p>
 Mesa 10.2 is a new development release.
@@ -33,7 +33,9 @@ because compatibility contexts are not supported.

 <h2>MD5 checksums</h2>
 <pre>
-TBD.
+c87bfb6dd5cbcf1fdef42e5ccd972581  MesaLib-10.2.0.tar.gz
+7aaba90bd7169a94ae2fe83febdec963  MesaLib-10.2.0.tar.bz2
+58b203aca15dadc25ab4d1126db1052b  MesaLib-10.2.0.zip
 </pre>


--- a/include/GL/glx.h
+++ b/include/GL/glx.h
@@ -518,7 +518,7 @@ typedef struct {
    unsigned long serial;	/* # of last request processed by server */
    Bool send_event;		/* true if this came from a SendEvent request */
    Display *display;		/* Display the event was read from */
-    GLXDrawable drawable;	/* drawable on which event was requested in event mask */
+    Drawable drawable;	/* drawable on which event was requested in event mask */
    int event_type;
    int64_t ust;
    int64_t msc;
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -91,24 +91,24 @@ CHIPSET(0x0F32, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0F33, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0157, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0155, byt,     "Intel(R) Bay Trail")
-CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell")
-CHIPSET(0x1612, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x1616, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x161E, bdw_gt2, "Intel(R) Broadwell")
-CHIPSET(0x1622, bdw_gt3, "Intel(R) Broadwell")
-CHIPSET(0x1626, bdw_gt3, "Intel(R) Broadwell")
-CHIPSET(0x162A, bdw_gt3, "Intel(R) Broadwell")
-CHIPSET(0x162B, bdw_gt3, "Intel(R) Broadwell")
-CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell")
-CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell GT1")
+CHIPSET(0x1612, bdw_gt2, "Intel(R) HD Graphics 5600 (Broadwell GT2)")
+CHIPSET(0x1616, bdw_gt2, "Intel(R) HD Graphics 5500 (Broadwell GT2)")
+CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell GT2")
+CHIPSET(0x161E, bdw_gt2, "Intel(R) HD Graphics 5300 (Broadwell GT2)")
+CHIPSET(0x1622, bdw_gt3, "Intel(R) Iris Pro 6200 (Broadwell GT3e)")
+CHIPSET(0x1626, bdw_gt3, "Intel(R) HD Graphics 6000 (Broadwell GT3)")
+CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)")
+CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)")
+CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3")
+CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3")
 CHIPSET(0x22B0, chv,     "Intel(R) Cherryview")
 CHIPSET(0x22B1, chv,     "Intel(R) Cherryview")
 CHIPSET(0x22B2, chv,     "Intel(R) Cherryview")
--- a/src/egl/drivers/dri2/Android.mk
+++ b/src/egl/drivers/dri2/Android.mk
@@ -40,8 +40,12 @@ LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
 	$(MESA_TOP)/src/egl/main \
 	$(MESA_TOP)/src/loader \
+	$(DRM_TOP)/include/drm \
 	$(DRM_GRALLOC_TOP)

+LOCAL_STATIC_LIBRARIES := \
+	libloader
+
 LOCAL_MODULE := libmesa_egl_dri2

 include $(MESA_COMMON_MK)
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -638,7 +638,7 @@ droid_log(EGLint level, const char *msg)
 static struct dri2_egl_display_vtbl droid_display_vtbl = {
   .authenticate = NULL,
   .create_window_surface = droid_create_window_surface,
-   .create_pixmap_surface = dri2_fallback_pixmap_surface,
+   .create_pixmap_surface = dri2_fallback_create_pixmap_surface,
   .create_pbuffer_surface = droid_create_pbuffer_surface,
   .destroy_surface = droid_destroy_surface,
   .create_image = droid_create_image_khr,
--- a/src/egl/main/Android.mk
+++ b/src/egl/main/Android.mk
@@ -154,11 +154,14 @@ LOCAL_STATIC_LIBRARIES := \
 	libmesa_glsl \
 	libmesa_glsl_utils \
 	libmesa_gallium \
-	libloader \
 	$(LOCAL_STATIC_LIBRARIES)

 endif # MESA_BUILD_GALLIUM

+LOCAL_STATIC_LIBRARIES := \
+	$(LOCAL_STATIC_LIBRARIES) \
+	libloader
+
 LOCAL_MODULE := libGLES_mesa
 LOCAL_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/egl

--- a/src/gallium/auxiliary/draw/draw_private.h
+++ b/src/gallium/auxiliary/draw/draw_private.h
@@ -493,7 +493,7 @@ draw_stats_clipper_primitives(struct draw_context *draw,
 static INLINE unsigned
 draw_clamp_viewport_idx(int idx)
 {
-   return ((PIPE_MAX_VIEWPORTS > idx || idx < 0) ? idx : 0);
+   return ((PIPE_MAX_VIEWPORTS > idx && idx >= 0) ? idx : 0);
 }

 /**
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -383,6 +383,15 @@ void util_blitter_destroy(struct blitter_context *blitter)
      if (ctx->fs_texfetch_stencil[i])
         ctx->delete_fs_state(pipe, ctx->fs_texfetch_stencil[i]);

+      if (ctx->fs_texfetch_col_msaa[i])
+         ctx->delete_fs_state(pipe, ctx->fs_texfetch_col_msaa[i]);
+      if (ctx->fs_texfetch_depth_msaa[i])
+         ctx->delete_fs_state(pipe, ctx->fs_texfetch_depth_msaa[i]);
+      if (ctx->fs_texfetch_depthstencil_msaa[i])
+         ctx->delete_fs_state(pipe, ctx->fs_texfetch_depthstencil_msaa[i]);
+      if (ctx->fs_texfetch_stencil_msaa[i])
+         ctx->delete_fs_state(pipe, ctx->fs_texfetch_stencil_msaa[i]);
+
      for (j = 0; j< Elements(ctx->fs_resolve[i]); j++)
         for (f = 0; f < 2; f++)
            if (ctx->fs_resolve[i][j][f])
--- a/src/gallium/auxiliary/util/u_prim.h
+++ b/src/gallium/auxiliary/util/u_prim.h
@@ -136,6 +136,21 @@ u_prim_vertex_count(unsigned prim)
   return (likely(prim < PIPE_PRIM_MAX)) ? &prim_table[prim] : NULL;
 }

+/**
+ * Given a vertex count, return the number of primitives.
+ * For polygons, return the number of triangles.
+ */
+static INLINE unsigned
+u_prims_for_vertices(unsigned prim, unsigned num)
+{
+   const struct u_prim_vertex_count *info = u_prim_vertex_count(prim);
+
+   if (num < info->min)
+      return 0;
+
+   return 1 + ((num - info->min) / info->incr);
+}
+
 static INLINE boolean u_validate_pipe_prim( unsigned pipe_prim, unsigned nr )
 {
   const struct u_prim_vertex_count *count = u_prim_vertex_count(pipe_prim);
--- a/src/gallium/auxiliary/util/u_transfer.c
+++ b/src/gallium/auxiliary/util/u_transfer.c
@@ -25,8 +25,8 @@ void u_default_transfer_inline_write( struct pipe_context *pipe,
   usage |= PIPE_TRANSFER_WRITE;

   /* transfer_inline_write implicitly discards the rewritten buffer range */
-   /* XXX this looks very broken for non-buffer resources having more than one dim. */
-   if (box->x == 0 && box->width == resource->width0) {
+   if (resource->target == PIPE_BUFFER &&
+       box->x == 0 && box->width == resource->width0) {
      usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
   } else {
      usage |= PIPE_TRANSFER_DISCARD_RANGE;
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32580 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10186 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  57831 bytes, from 2014-05-19 21:02:34)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26293 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)

 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select {
 	SAMPLE_0123 = 6,
 };

+enum a2xx_rb_blend_opcode {
+	BLEND_DST_PLUS_SRC = 0,
+	BLEND_SRC_MINUS_DST = 1,
+	BLEND_MIN_DST_SRC = 2,
+	BLEND_MAX_DST_SRC = 3,
+	BLEND_DST_MINUS_SRC = 4,
+	BLEND_DST_PLUS_SRC_BIAS = 5,
+};
+
 enum adreno_mmu_clnt_beh {
 	BEH_NEVR = 0,
 	BEH_TRAN_RNG = 1,
@@ -996,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend
 }
 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0
 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)
+static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
 {
 	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
 }
@@ -1014,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend
 }
 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000
 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)
+static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
 {
 	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
 }
--- a/src/gallium/drivers/freedreno/a2xx/fd2_blend.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_blend.c
@@ -34,6 +34,27 @@
 #include "fd2_context.h"
 #include "fd2_util.h"

+
+static enum a2xx_rb_blend_opcode
+blend_func(unsigned func)
+{
+	switch (func) {
+	case PIPE_BLEND_ADD:
+		return BLEND_DST_PLUS_SRC;
+	case PIPE_BLEND_MIN:
+		return BLEND_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return BLEND_MAX_DST_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return BLEND_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return BLEND_DST_MINUS_SRC;
+	default:
+		DBG("invalid blend func: %x", func);
+		return 0;
+	}
+}
+
 void *
 fd2_blend_state_create(struct pipe_context *pctx,
 		const struct pipe_blend_state *cso)
@@ -61,10 +82,10 @@ fd2_blend_state_create(struct pipe_context *pctx,

 	so->rb_blendcontrol =
 		A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(fd_blend_factor(rt->rgb_src_factor)) |
-		A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(fd_blend_func(rt->rgb_func)) |
+		A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) |
 		A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(fd_blend_factor(rt->rgb_dst_factor)) |
 		A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(fd_blend_factor(rt->alpha_src_factor)) |
-		A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(fd_blend_func(rt->alpha_func)) |
+		A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) |
 		A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(fd_blend_factor(rt->alpha_dst_factor));

 	if (rt->colormask & PIPE_MASK_R)
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32580 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10186 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  57831 bytes, from 2014-05-19 21:02:34)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26293 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)

 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -186,16 +186,26 @@ enum a3xx_rop_code {
 	ROP_SET = 15,
 };

+enum a3xx_rb_blend_opcode {
+	BLEND_DST_PLUS_SRC = 0,
+	BLEND_SRC_MINUS_DST = 1,
+	BLEND_DST_MINUS_SRC = 2,
+	BLEND_MIN_DST_SRC = 3,
+	BLEND_MAX_DST_SRC = 4,
+};
+
 enum a3xx_tex_filter {
 	A3XX_TEX_NEAREST = 0,
 	A3XX_TEX_LINEAR = 1,
+	A3XX_TEX_ANISO = 2,
 };

 enum a3xx_tex_clamp {
 	A3XX_TEX_REPEAT = 0,
 	A3XX_TEX_CLAMP_TO_EDGE = 1,
 	A3XX_TEX_MIRROR_REPEAT = 2,
-	A3XX_TEX_CLAMP_NONE = 3,
+	A3XX_TEX_CLAMP_TO_BORDER = 3,
+	A3XX_TEX_MIRROR_CLAMP = 4,
 };

 enum a3xx_tex_swiz {
@@ -877,7 +887,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b
 }
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
 {
 	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
 }
@@ -895,7 +905,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb
 }
 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
 {
 	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
 }
@@ -978,6 +988,7 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples
 {
 	return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
 }
+#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR				0x00000008
 #define A3XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT			4
 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
@@ -1078,7 +1089,7 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form
 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			11
 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 {
-	return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+	return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 }

 #define REG_A3XX_RB_DEPTH_PITCH					0x00002103
@@ -1526,6 +1537,12 @@ static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
 {
 	return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
 }
+#define A3XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
+#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT			22
+static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
+{
+	return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
+}
 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT			24
 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_blend.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_blend.c
@@ -34,6 +34,27 @@
 #include "fd3_context.h"
 #include "fd3_util.h"

+
+static enum a3xx_rb_blend_opcode
+blend_func(unsigned func)
+{
+	switch (func) {
+	case PIPE_BLEND_ADD:
+		return BLEND_DST_PLUS_SRC;
+	case PIPE_BLEND_MIN:
+		return BLEND_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return BLEND_MAX_DST_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return BLEND_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return BLEND_DST_MINUS_SRC;
+	default:
+		DBG("invalid blend func: %x", func);
+		return 0;
+	}
+}
+
 void *
 fd3_blend_state_create(struct pipe_context *pctx,
 		const struct pipe_blend_state *cso)
@@ -80,10 +101,10 @@ fd3_blend_state_create(struct pipe_context *pctx,

 		so->rb_mrt[i].blend_control =
 				A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(fd_blend_factor(rt->rgb_src_factor)) |
-				A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(fd_blend_func(rt->rgb_func)) |
+				A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(blend_func(rt->rgb_func)) |
 				A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(fd_blend_factor(rt->rgb_dst_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(fd_blend_factor(rt->alpha_src_factor)) |
-				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(fd_blend_func(rt->alpha_func)) |
+				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(blend_func(rt->alpha_func)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(fd_blend_factor(rt->alpha_dst_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE;

--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -195,8 +195,10 @@ emit_textures(struct fd_ringbuffer *ring,
 		OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 				CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 		for (i = 0; i < tex->num_textures; i++) {
-			struct fd3_pipe_sampler_view *view =
-					fd3_pipe_sampler_view(tex->textures[i]);
+			static const struct fd3_pipe_sampler_view dummy_view = {};
+			const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+					fd3_pipe_sampler_view(tex->textures[i]) :
+					&dummy_view;
 			OUT_RING(ring, view->texconst0);
 			OUT_RING(ring, view->texconst1);
 			OUT_RING(ring, view->texconst2 |
@@ -213,8 +215,10 @@ emit_textures(struct fd_ringbuffer *ring,
 		OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
 				CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
 		for (i = 0; i < tex->num_textures; i++) {
-			struct fd3_pipe_sampler_view *view =
-					fd3_pipe_sampler_view(tex->textures[i]);
+			static const struct fd3_pipe_sampler_view dummy_view = {};
+			const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
+					fd3_pipe_sampler_view(tex->textures[i]) :
+					&dummy_view;
 			struct fd_resource *rsc = view->tex_resource;

 			for (j = 0; j < view->mipaddrs; j++) {
@@ -323,9 +327,12 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 		if (vp->inputs[i].compmask) {
 			struct pipe_resource *prsc = vbufs[i].prsc;
 			struct fd_resource *rsc = fd_resource(prsc);
-			enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(vbufs[i].format);
+			enum pipe_format pfmt = vbufs[i].format;
+			enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
 			bool switchnext = (i != last);
-			uint32_t fs = util_format_get_blocksize(vbufs[i].format);
+			uint32_t fs = util_format_get_blocksize(pfmt);
+
+			debug_assert(fmt != ~0);

 			OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
 			OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
@@ -339,6 +346,7 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
 			OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
 					A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
 					A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
+					A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
 					A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
 					A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
 					A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -82,7 +82,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 				stride = bin_w * rsc->cpp;

 				if (bases) {
-					base = bases[i] * rsc->cpp;
+					base = bases[i];
 				}
 			} else {
 				stride = slice->pitch * rsc->cpp;
@@ -106,9 +106,17 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 }

 static uint32_t
-depth_base(struct fd_gmem_stateobj *gmem)
+depth_base(struct fd_context *ctx)
 {
-	return align(gmem->bin_w * gmem->bin_h, 0x4000);
+	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	uint32_t cpp = 4;
+	if (pfb->cbufs[0]) {
+		struct fd_resource *rsc =
+				fd_resource(pfb->cbufs[0]->texture);
+		cpp = rsc->cpp;
+	}
+	return align(gmem->bin_w * gmem->bin_h * cpp, 0x4000);
 }

 static bool
@@ -156,7 +164,7 @@ emit_binning_workaround(struct fd_context *ctx)
 	OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 			A3XX_RB_COPY_CONTROL_MODE(0) |
 			A3XX_RB_COPY_CONTROL_GMEM_BASE(0));
-	OUT_RELOC(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
+	OUT_RELOCW(ring, fd_resource(fd3_ctx->solid_vbuf)->bo, 0x20, 0, -1);  /* RB_COPY_DEST_BASE */
 	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
 	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
 			A3XX_RB_COPY_DEST_INFO_FORMAT(RB_R8G8B8A8_UNORM) |
@@ -399,12 +407,7 @@ fd3_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 			}}, 1);

 	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
-		uint32_t base = 0;
-		if (pfb->cbufs[0]) {
-			struct fd_resource *rsc =
-					fd_resource(pfb->cbufs[0]->texture);
-			base = depth_base(&ctx->gmem) * rsc->cpp;
-		}
+		uint32_t base = depth_base(ctx);
 		emit_gmem2mem_surf(ctx, RB_COPY_DEPTH_STENCIL, base, pfb->zsbuf);
 	}

@@ -458,7 +461,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);

 	OUT_PKT3(ring, CP_MEM_WRITE, 5);
-	OUT_RELOC(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
+	OUT_RELOCW(ring, fd_resource(fd3_ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 	OUT_RING(ring, fui(x0));
 	OUT_RING(ring, fui(y0));
 	OUT_RING(ring, fui(x1));
@@ -558,7 +561,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	bin_h = gmem->bin_h;

 	if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
-		emit_mem2gmem_surf(ctx, depth_base(gmem), pfb->zsbuf, bin_w);
+		emit_mem2gmem_surf(ctx, depth_base(ctx), pfb->zsbuf, bin_w);

 	if (ctx->restore & FD_BUFFER_COLOR)
 		emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0], bin_w);
@@ -639,7 +642,7 @@ update_vsc_pipe(struct fd_context *ctx)
 	int i;

 	OUT_PKT0(ring, REG_A3XX_VSC_SIZE_ADDRESS, 1);
-	OUT_RELOC(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
+	OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */

 	for (i = 0; i < 8; i++) {
 		struct fd_vsc_pipe *pipe = &ctx->pipe[i];
@@ -654,7 +657,7 @@ update_vsc_pipe(struct fd_context *ctx)
 				A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 				A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 				A3XX_VSC_PIPE_CONFIG_H(pipe->h));
-		OUT_RELOC(ring, pipe->bo, 0, 0, 0);        /* VSC_PIPE[i].DATA_ADDRESS */
+		OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
 		OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 	}
 }
@@ -789,6 +792,7 @@ fd3_emit_tile_init(struct fd_context *ctx)
 {
 	struct fd_ringbuffer *ring = ctx->ring;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	uint32_t rb_render_control;

 	fd3_emit_restore(ctx);

@@ -813,8 +817,10 @@ fd3_emit_tile_init(struct fd_context *ctx)
 		patch_draws(ctx, IGNORE_VISIBILITY);
 	}

-	patch_rbrc(ctx, A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
-			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
+	rb_render_control = A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
+			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w);
+
+	patch_rbrc(ctx, rb_render_control);
 }

 /* before mem2gmem */
@@ -827,7 +833,7 @@ fd3_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 	uint32_t reg;

 	OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
-	reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(gmem));
+	reg = A3XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx));
 	if (pfb->zsbuf) {
 		reg |= A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 	}
--- a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
@@ -48,12 +48,14 @@ tex_clamp(unsigned wrap)
 	case PIPE_TEX_WRAP_REPEAT:
 		return A3XX_TEX_REPEAT;
 	case PIPE_TEX_WRAP_CLAMP:
-	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 		return A3XX_TEX_CLAMP_TO_EDGE;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return A3XX_TEX_CLAMP_TO_BORDER;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP:
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return A3XX_TEX_MIRROR_CLAMP;
 	case PIPE_TEX_WRAP_MIRROR_REPEAT:
 		return A3XX_TEX_MIRROR_REPEAT;
 	default:
--- a/src/gallium/drivers/freedreno/a3xx/fd3_util.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_util.c
@@ -37,70 +37,44 @@ fd3_pipe2vtx(enum pipe_format format)
 {
 	switch (format) {
 	/* 8-bit buffers. */
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
 	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
 		return VFMT_NORM_UBYTE_8;

-	case PIPE_FORMAT_A8_SNORM:
-	case PIPE_FORMAT_I8_SNORM:
-	case PIPE_FORMAT_L8_SNORM:
 	case PIPE_FORMAT_R8_SNORM:
 		return VFMT_NORM_BYTE_8;

-	case PIPE_FORMAT_A8_UINT:
-	case PIPE_FORMAT_I8_UINT:
-	case PIPE_FORMAT_L8_UINT:
 	case PIPE_FORMAT_R8_UINT:
 		return VFMT_UBYTE_8;

-	case PIPE_FORMAT_A8_SINT:
-	case PIPE_FORMAT_I8_SINT:
-	case PIPE_FORMAT_L8_SINT:
 	case PIPE_FORMAT_R8_SINT:
 		return VFMT_BYTE_8;

 	/* 16-bit buffers. */
 	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_A16_UNORM:
-	case PIPE_FORMAT_L16_UNORM:
-	case PIPE_FORMAT_I16_UNORM:
 	case PIPE_FORMAT_Z16_UNORM:
 		return VFMT_NORM_USHORT_16;

 	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_A16_SNORM:
-	case PIPE_FORMAT_L16_SNORM:
-	case PIPE_FORMAT_I16_SNORM:
 		return VFMT_NORM_SHORT_16;

 	case PIPE_FORMAT_R16_UINT:
-	case PIPE_FORMAT_A16_UINT:
-	case PIPE_FORMAT_L16_UINT:
-	case PIPE_FORMAT_I16_UINT:
 		return VFMT_USHORT_16;

 	case PIPE_FORMAT_R16_SINT:
-	case PIPE_FORMAT_A16_SINT:
-	case PIPE_FORMAT_L16_SINT:
-	case PIPE_FORMAT_I16_SINT:
 		return VFMT_SHORT_16;

-	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_R16_FLOAT:
+		return VFMT_FLOAT_16;
+
 	case PIPE_FORMAT_R8G8_UNORM:
 		return VFMT_NORM_UBYTE_8_8;

-	case PIPE_FORMAT_L8A8_SNORM:
 	case PIPE_FORMAT_R8G8_SNORM:
 		return VFMT_NORM_BYTE_8_8;

-	case PIPE_FORMAT_L8A8_UINT:
 	case PIPE_FORMAT_R8G8_UINT:
 		return VFMT_UBYTE_8_8;

-	case PIPE_FORMAT_L8A8_SINT:
 	case PIPE_FORMAT_R8G8_SINT:
 		return VFMT_BYTE_8_8;

@@ -121,42 +95,62 @@ fd3_pipe2vtx(enum pipe_format format)
 	case PIPE_FORMAT_A8B8G8R8_UNORM:
 	case PIPE_FORMAT_A8R8G8B8_UNORM:
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
 	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
 		return VFMT_NORM_UBYTE_8_8_8_8;

 	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8X8_SNORM:
 		return VFMT_NORM_BYTE_8_8_8_8;

 	case PIPE_FORMAT_R8G8B8A8_UINT:
-	case PIPE_FORMAT_R8G8B8X8_UINT:
 		return VFMT_UBYTE_8_8_8_8;

 	case PIPE_FORMAT_R8G8B8A8_SINT:
-	case PIPE_FORMAT_R8G8B8X8_SINT:
 		return VFMT_BYTE_8_8_8_8;

-/* TODO probably need gles3 blob drivers to find the 32bit int formats:
-	case PIPE_FORMAT_R32_UINT:
-	case PIPE_FORMAT_R32_SINT:
-	case PIPE_FORMAT_A32_UINT:
-	case PIPE_FORMAT_A32_SINT:
-	case PIPE_FORMAT_L32_UINT:
-	case PIPE_FORMAT_L32_SINT:
-	case PIPE_FORMAT_I32_UINT:
-	case PIPE_FORMAT_I32_SINT:
-*/
+	case PIPE_FORMAT_R16G16_SSCALED:
+		return VFMT_SHORT_16_16;
+
+	case PIPE_FORMAT_R16G16_FLOAT:
+		return VFMT_FLOAT_16_16;
+
+	case PIPE_FORMAT_R16G16_UINT:
+		return VFMT_USHORT_16_16;
+
+	case PIPE_FORMAT_R16G16_UNORM:
+		return VFMT_NORM_USHORT_16_16;
+
+	case PIPE_FORMAT_R16G16_SNORM:
+		return VFMT_NORM_SHORT_16_16;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+		return VFMT_NORM_UINT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_SNORM:
+		return VFMT_NORM_INT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_USCALED:
+		return VFMT_UINT_10_10_10_2;
+
+	case PIPE_FORMAT_R10G10B10A2_SSCALED:
+		return VFMT_INT_10_10_10_2;
+
+	/* 48-bit buffers. */
+	case PIPE_FORMAT_R16G16B16_FLOAT:
+		return VFMT_FLOAT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_SSCALED:
+		return VFMT_SHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_UINT:
+		return VFMT_USHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_SNORM:
+		return VFMT_NORM_SHORT_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_UNORM:
+		return VFMT_NORM_USHORT_16_16_16;

 	case PIPE_FORMAT_R32_FLOAT:
-	case PIPE_FORMAT_A32_FLOAT:
-	case PIPE_FORMAT_L32_FLOAT:
-	case PIPE_FORMAT_I32_FLOAT:
 	case PIPE_FORMAT_Z32_FLOAT:
 		return VFMT_FLOAT_32;

@@ -177,23 +171,14 @@ fd3_pipe2vtx(enum pipe_format format)
 		return VFMT_SHORT_16_16_16_16;

 	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_L32A32_FLOAT:
 		return VFMT_FLOAT_32_32;

 	case PIPE_FORMAT_R32G32_FIXED:
 		return VFMT_FIXED_32_32;

 	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-	case PIPE_FORMAT_R16G16B16X16_FLOAT:
 		return VFMT_FLOAT_16_16_16_16;

-/* TODO probably need gles3 blob drivers to find the 32bit int formats:
-	case PIPE_FORMAT_R32G32_SINT:
-	case PIPE_FORMAT_R32G32_UINT:
-	case PIPE_FORMAT_L32A32_UINT:
-	case PIPE_FORMAT_L32A32_SINT:
-*/
-
 	/* 96-bit buffers. */
 	case PIPE_FORMAT_R32G32B32_FLOAT:
 		return VFMT_FLOAT_32_32_32;
@@ -203,7 +188,6 @@ fd3_pipe2vtx(enum pipe_format format)

 	/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-	case PIPE_FORMAT_R32G32B32X32_FLOAT:
 		return VFMT_FLOAT_32_32_32_32;

 	case PIPE_FORMAT_R32G32B32A32_FIXED:
@@ -214,6 +198,20 @@ fd3_pipe2vtx(enum pipe_format format)
 	case PIPE_FORMAT_R32G32B32A32_UNORM:
 	case PIPE_FORMAT_R32G32B32A32_SINT:
 	case PIPE_FORMAT_R32G32B32A32_UINT:
+
+	case PIPE_FORMAT_R32_UINT:
+	case PIPE_FORMAT_R32_SINT:
+	case PIPE_FORMAT_A32_UINT:
+	case PIPE_FORMAT_A32_SINT:
+	case PIPE_FORMAT_L32_UINT:
+	case PIPE_FORMAT_L32_SINT:
+	case PIPE_FORMAT_I32_UINT:
+	case PIPE_FORMAT_I32_SINT:
+
+	case PIPE_FORMAT_R32G32_SINT:
+	case PIPE_FORMAT_R32G32_UINT:
+	case PIPE_FORMAT_L32A32_UINT:
+	case PIPE_FORMAT_L32A32_SINT:
 */

 	default:
@@ -358,8 +356,22 @@ fd3_pipe2swap(enum pipe_format format)
 	switch (format) {
 	case PIPE_FORMAT_B8G8R8A8_UNORM:
 	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8X8_SRGB:
 		return WXYZ;

+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_SRGB:
+	case PIPE_FORMAT_X8R8G8B8_SRGB:
+		return ZYXW;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_X8B8G8R8_SRGB:
+		return XYZW;
+
 	case PIPE_FORMAT_R8G8B8A8_UNORM:
 	case PIPE_FORMAT_R8G8B8X8_UNORM:
 	case PIPE_FORMAT_Z24X8_UNORM:
--- a/src/gallium/drivers/freedreno/adreno_common.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_common.xml.h
@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32580 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10186 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  57831 bytes, from 2014-05-19 21:02:34)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26293 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)

 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -87,15 +87,6 @@ enum adreno_rb_blend_factor {
 	FACTOR_SRC_ALPHA_SATURATE = 16,
 };

-enum adreno_rb_blend_opcode {
-	BLEND_DST_PLUS_SRC = 0,
-	BLEND_SRC_MINUS_DST = 1,
-	BLEND_MIN_DST_SRC = 2,
-	BLEND_MAX_DST_SRC = 3,
-	BLEND_DST_MINUS_SRC = 4,
-	BLEND_DST_PLUS_SRC_BIAS = 5,
-};
-
 enum adreno_rb_surface_endian {
 	ENDIAN_NONE = 0,
 	ENDIAN_8IN16 = 1,
--- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
@@ -10,11 +10,11 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32580 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10186 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  57831 bytes, from 2014-05-19 21:02:34)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26293 bytes, from 2014-05-16 11:51:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-13 17:29:47)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-13 17:28:10)

 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -48,6 +48,10 @@ realloc_bo(struct fd_resource *rsc, uint32_t size)
 	uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 			DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */

+	/* if we start using things other than write-combine,
+	 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
+	 */
+
 	if (rsc->bo)
 		fd_bo_del(rsc->bo);

--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -161,9 +161,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
-	case PIPE_CAP_SM3:
 	case PIPE_CAP_SEAMLESS_CUBE_MAP:
-	case PIPE_CAP_TEXTURE_BARRIER:
 	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 	case PIPE_CAP_TGSI_INSTANCEID:
@@ -173,8 +171,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_COMPUTE:
 	case PIPE_CAP_START_INSTANCE:
 	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
-	case PIPE_CAP_TEXTURE_MULTISAMPLE:
 	case PIPE_CAP_USER_CONSTANT_BUFFERS:
+	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 		return 1;

 	case PIPE_CAP_SHADER_STENCIL_EXPORT:
@@ -182,6 +180,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 	case PIPE_CAP_CONDITIONAL_RENDER:
 	case PIPE_CAP_PRIMITIVE_RESTART:
+	case PIPE_CAP_TEXTURE_MULTISAMPLE:
+	case PIPE_CAP_TEXTURE_BARRIER:
+	case PIPE_CAP_SM3:
 		return 0;

 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
@@ -207,7 +208,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_VS_LAYER:
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 	case PIPE_CAP_TEXTURE_GATHER_SM5:
-        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
        case PIPE_CAP_FAKE_SW_MSAA:
 	case PIPE_CAP_TEXTURE_QUERY_LOD:
        case PIPE_CAP_SAMPLE_SHADING:
--- a/src/gallium/drivers/freedreno/freedreno_texture.c
+++ b/src/gallium/drivers/freedreno/freedreno_texture.c
@@ -57,7 +57,7 @@ static void bind_sampler_states(struct fd_texture_stateobj *prog,

 	for (i = 0; i < nr; i++) {
 		if (hwcso[i])
-			new_nr++;
+			new_nr = i + 1;
 		prog->samplers[i] = hwcso[i];
 		prog->dirty_samplers |= (1 << i);
 	}
@@ -78,7 +78,7 @@ static void set_sampler_views(struct fd_texture_stateobj *prog,

 	for (i = 0; i < nr; i++) {
 		if (views[i])
-			new_nr++;
+			new_nr = i + 1;
 		pipe_sampler_view_reference(&prog->textures[i], views[i]);
 		prog->dirty_samplers |= (1 << i);
 	}
--- a/src/gallium/drivers/freedreno/freedreno_util.c
+++ b/src/gallium/drivers/freedreno/freedreno_util.c
@@ -111,26 +111,6 @@ fd_blend_factor(unsigned factor)
 	}
 }

-enum adreno_rb_blend_opcode
-fd_blend_func(unsigned func)
-{
-	switch (func) {
-	case PIPE_BLEND_ADD:
-		return BLEND_DST_PLUS_SRC;
-	case PIPE_BLEND_MIN:
-		return BLEND_MIN_DST_SRC;
-	case PIPE_BLEND_MAX:
-		return BLEND_MAX_DST_SRC;
-	case PIPE_BLEND_SUBTRACT:
-		return BLEND_SRC_MINUS_DST;
-	case PIPE_BLEND_REVERSE_SUBTRACT:
-		return BLEND_DST_MINUS_SRC;
-	default:
-		DBG("invalid blend func: %x", func);
-		return 0;
-	}
-}
-
 enum adreno_pa_su_sc_draw
 fd_polygon_mode(unsigned mode)
 {
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -45,7 +45,6 @@
 enum adreno_rb_depth_format fd_pipe2depth(enum pipe_format format);
 enum pc_di_index_size fd_pipe2index(enum pipe_format format);
 enum adreno_rb_blend_factor fd_blend_factor(unsigned factor);
-enum adreno_rb_blend_opcode fd_blend_func(unsigned func);
 enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
 enum adreno_stencil_op fd_stencil_op(unsigned op);

--- a/src/gallium/drivers/llvmpipe/lp_texture.c
+++ b/src/gallium/drivers/llvmpipe/lp_texture.c
@@ -115,7 +115,7 @@ llvmpipe_texture_layout(struct llvmpipe_screen *screen,
            lpr->row_stride[level] = align(nblocksx * block_size, util_cpu_caps.cacheline);

         /* if row_stride * height > LP_MAX_TEXTURE_SIZE */
-         if (lpr->row_stride[level] > LP_MAX_TEXTURE_SIZE / nblocksy) {
+         if ((uint64_t)lpr->row_stride[level] * nblocksy > LP_MAX_TEXTURE_SIZE) {
            /* image too large */
            goto fail;
         }
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -177,6 +177,7 @@ struct nv50_ir_prog_info
      uint8_t vertexId;          /* system value index of VertexID */
      uint8_t edgeFlagIn;
      uint8_t edgeFlagOut;
+      int8_t viewportId;         /* output index of ViewportIndex */
      uint8_t fragDepth;         /* output index of FragDepth */
      uint8_t sampleMask;        /* output index of SampleMask */
      boolean sampleInterp;      /* perform sample interp on all fp inputs */
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -287,10 +287,12 @@ CodeEmitterGK110::emitPredicate(const Instruction *i)
 void
 CodeEmitterGK110::setCAddress14(const ValueRef& src)
 {
-   const int32_t addr = src.get()->asSym()->reg.data.offset / 4;
+   const Storage& res = src.get()->asSym()->reg;
+   const int32_t addr = res.data.offset / 4;

   code[0] |= (addr & 0x01ff) << 23;
   code[1] |= (addr & 0x3e00) >> 9;
+   code[1] |= res.fileIndex << 5;
 }

 void
@@ -413,7 +415,6 @@ CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2,
      case FILE_MEMORY_CONST:
         code[1] &= (s == 2) ? ~(0x4 << 28) : ~(0x8 << 28);
         setCAddress14(i->src(s));
-         code[1] |= i->getSrc(s)->reg.fileIndex << 5;
         break;
      case FILE_IMMEDIATE:
         setShortImmediate(i, s);
@@ -555,6 +556,7 @@ CodeEmitterGK110::emitFADD(const Instruction *i)
      RND_(2a, F);
      ABS_(31, 0);
      NEG_(33, 0);
+      SAT_(35);

      if (code[0] & 0x1) {
         modNegAbsF32_3b(i, 1);
@@ -711,7 +713,7 @@ CodeEmitterGK110::emitEXTBF(const Instruction *i)
 void
 CodeEmitterGK110::emitBFIND(const Instruction *i)
 {
-   emitForm_21(i, 0x618, 0xc18);
+   emitForm_C(i, 0x218, 0x2);

   if (i->dType == TYPE_S32)
      code[1] |= 0x80000;
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -790,6 +790,8 @@ bool Source::scanSource()
      info->prop.gp.instanceCount = 1; // default value
   }

+   info->io.viewportId = -1;
+
   info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
   info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));

@@ -982,6 +984,9 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
         case TGSI_SEMANTIC_SAMPLEMASK:
            info->io.sampleMask = i;
            break;
+         case TGSI_SEMANTIC_VIEWPORT_INDEX:
+            info->io.viewportId = i;
+            break;
         default:
            break;
         }
@@ -1258,6 +1263,8 @@ private:
   Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
   Stack loopBBs;  // loop headers
   Stack breakBBs; // end of / after loop
+
+   Value *viewport;
 };

 Symbol *
@@ -1555,8 +1562,16 @@ Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
      mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
   } else
   if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
-      if (ptr || (info->out[idx].mask & (1 << c)))
-         mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+
+      if (ptr || (info->out[idx].mask & (1 << c))) {
+         /* Save the viewport index into a scratch register so that it can be
+            exported at EMIT time */
+         if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
+             viewport != NULL)
+            mkOp1(OP_MOV, TYPE_U32, viewport, val);
+         else
+            mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+      }
   } else
   if (f == TGSI_FILE_TEMPORARY ||
       f == TGSI_FILE_PREDICATE ||
@@ -2489,7 +2504,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
      break;
   case TGSI_OPCODE_TXB2:
   case TGSI_OPCODE_TXL2:
-      handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
+      handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
      break;
   case TGSI_OPCODE_SAMPLE:
   case TGSI_OPCODE_SAMPLE_B:
@@ -2523,6 +2538,13 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
         mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
      break;
   case TGSI_OPCODE_EMIT:
+      /* export the saved viewport index */
+      if (viewport != NULL) {
+         Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
+                                  info->out[info->io.viewportId].slot[0] * 4);
+         mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
+      }
+      /* fallthrough */
   case TGSI_OPCODE_ENDPRIM:
      // get vertex stream if specified (must be immediate)
      src0 = tgsi.srcCount() ?
@@ -2952,6 +2974,11 @@ Converter::run()
      mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
   }

+   if (info->io.viewportId >= 0)
+      viewport = getScratch();
+   else
+      viewport = NULL;
+
   for (ip = 0; ip < code->scan.num_instructions; ++ip) {
      if (!handleInstruction(&code->insns[ip]))
         return false;
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -797,6 +797,16 @@ NV50LoweringPreSSA::handleTXB(TexInstruction *i)
   const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
   int l, d;

+   // We can't actually apply bias *and* do a compare for a cube
+   // texture. Since the compare has to be done before the filtering, just
+   // drop the bias on the floor.
+   if (i->tex.target == TEX_TARGET_CUBE_SHADOW) {
+      i->op = OP_TEX;
+      i->setSrc(3, i->getSrc(4));
+      i->setSrc(4, NULL);
+      return handleTEX(i);
+   }
+
   handleTEX(i);
   Value *bias = i->getSrc(i->tex.target.getArgCount());
   if (bias->isUniform())
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -814,6 +814,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
   Value *zero = bld.loadImm(bld.getSSA(), 0);
   int l, c;
   const int dim = i->tex.target.getDim();
+   const int array = i->tex.target.isArray();

   i->op = OP_TEX; // no need to clone dPdx/dPdy later

@@ -824,7 +825,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
   for (l = 0; l < 4; ++l) {
      // mov coordinates from lane l to all lanes
      for (c = 0; c < dim; ++c)
-         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c), zero);
+         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c + array), zero);
      // add dPdx from lane l to lanes dx
      for (c = 0; c < dim; ++c)
         bld.mkQuadop(qOps[l][0], crd[c], l, i->dPdx[c].get(), crd[c]);
@@ -834,7 +835,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
      // texture
      bld.insert(tex = cloneForward(func, i));
      for (c = 0; c < dim; ++c)
-         tex->setSrc(c, crd[c]);
+         tex->setSrc(c + array, crd[c]);
      // save results
      for (c = 0; i->defExists(c); ++c) {
         Instruction *mov;
@@ -870,7 +871,8 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
   if (dim > 2 ||
       txd->tex.target.isCube() ||
       arg > 4 ||
-       txd->tex.target.isShadow())
+       txd->tex.target.isShadow() ||
+       txd->tex.useOffsets)
      return handleManualTXD(txd);

   for (int c = 0; c < dim; ++c) {
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c
@@ -165,6 +165,9 @@ nv30_context_destroy(struct pipe_context *pipe)
   if (nv30->draw)
      draw_destroy(nv30->draw);

+   if (nv30->screen->base.pushbuf->user_priv == &nv30->bufctx)
+      nv30->screen->base.pushbuf->user_priv = NULL;
+
   nouveau_bufctx_del(&nv30->bufctx);

   if (nv30->screen->cur_ctx == nv30)
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -325,6 +325,12 @@ nv30_screen_destroy(struct pipe_screen *pscreen)
      nouveau_fence_ref(NULL, &screen->base.fence.current);
   }

+   nouveau_bo_ref(NULL, &screen->notify);
+
+   nouveau_heap_destroy(&screen->query_heap);
+   nouveau_heap_destroy(&screen->vp_exec_heap);
+   nouveau_heap_destroy(&screen->vp_data_heap);
+
   nouveau_object_del(&screen->query);
   nouveau_object_del(&screen->fence);
   nouveau_object_del(&screen->ntfy);
--- a/src/gallium/drivers/nouveau/nv30/nv30_state.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_state.c
@@ -23,6 +23,7 @@
 *
 */

+#include "util/u_format.h"
 #include "util/u_helpers.h"
 #include "util/u_inlines.h"

@@ -360,6 +361,22 @@ nv30_set_framebuffer_state(struct pipe_context *pipe,

    nv30->framebuffer = *fb;
    nv30->dirty |= NV30_NEW_FRAMEBUFFER;
+
+   /* Hardware can't handle different swizzled-ness or different blocksizes
+    * for zs and cbufs. If both are supplied and something doesn't match,
+    * blank out the zs for now so that at least *some* rendering can occur.
+    */
+    if (fb->nr_cbufs > 0 && fb->zsbuf) {
+       struct nv30_miptree *color_mt = nv30_miptree(fb->cbufs[0]->texture);
+       struct nv30_miptree *zeta_mt = nv30_miptree(fb->zsbuf->texture);
+
+       if (color_mt->swizzled != zeta_mt->swizzled ||
+           (util_format_get_blocksize(fb->zsbuf->format) > 2) !=
+           (util_format_get_blocksize(fb->cbufs[0]->format) > 2)) {
+          nv30->framebuffer.zsbuf = NULL;
+          debug_printf("Mismatched color and zeta formats, ignoring zeta.\n");
+       }
+    }
 }

 static void
--- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
@@ -1225,6 +1225,7 @@ out:
   if(fpc)
   {
      FREE(fpc->r_temp);
+      FREE(fpc->r_imm);
      util_dynarray_fini(&fpc->if_stack);
      util_dynarray_fini(&fpc->label_relocs);
      util_dynarray_fini(&fpc->imm_data);
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -61,7 +61,7 @@ static void
 nv50_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
   struct nv50_context *nv50 = nv50_context(pipe);
-   int i;
+   int i, s;

   if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
      for (i = 0; i < nv50->num_vtxbufs; ++i) {
@@ -74,6 +74,26 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned flags)
      if (nv50->idxbuf.buffer &&
          nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
         nv50->base.vbo_dirty = TRUE;
+
+      for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+         uint32_t valid = nv50->constbuf_valid[s];
+
+         while (valid && !nv50->cb_dirty) {
+            const unsigned i = ffs(valid) - 1;
+            struct pipe_resource *res;
+
+            valid &= ~(1 << i);
+            if (nv50->constbuf[s][i].user)
+               continue;
+
+            res = nv50->constbuf[s][i].u.buf;
+            if (!res)
+               continue;
+
+            if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+               nv50->cb_dirty = TRUE;
+         }
+      }
   }
 }

@@ -253,7 +273,14 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
   nv50->base.screen    = &screen->base;
   nv50->base.copy_data = nv50_m2mf_copy_linear;
   nv50->base.push_data = nv50_sifc_linear_u8;
+   /* FIXME: Make it possible to use this again. The problem is that there is
+    * some clever logic in the card that allows for multiple renders to happen
+    * when there are only constbuf changes. However that relies on the
+    * constbuf updates happening to the right constbuf slots. Currently
+    * implementation just makes it go through a separate slot which doesn't
+    * properly update the right constbuf data.
   nv50->base.push_cb   = nv50_cb_push;
+    */

   nv50->screen = screen;
   pipe->screen = pscreen;
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.h
@@ -106,6 +106,7 @@ struct nv50_context {
   struct nouveau_bufctx *bufctx;

   uint32_t dirty;
+   boolean cb_dirty;

   struct {
      uint32_t instance_elts; /* bitmask of per-instance elements */
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -1106,6 +1106,7 @@ nv50_blitctx_post_blit(struct nv50_blitctx *blit)
       NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
       NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
       NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
+   nv50->scissors_dirty |= 1;

   nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
 }
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -747,7 +747,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
   struct nv50_context *nv50 = nv50_context(pipe);
   struct nouveau_pushbuf *push = nv50->base.pushbuf;
-   int i;
+   int i, s;

   /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
   nv50->vb_elt_first = info->min_index + info->index_bias;
@@ -776,6 +776,33 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)

   push->kick_notify = nv50_draw_vbo_kick_notify;

+   for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+      uint32_t valid = nv50->constbuf_valid[s];
+
+      while (valid && !nv50->cb_dirty) {
+         const unsigned i = ffs(valid) - 1;
+         struct pipe_resource *res;
+
+         valid &= ~(1 << i);
+         if (nv50->constbuf[s][i].user)
+            continue;
+
+         res = nv50->constbuf[s][i].u.buf;
+         if (!res)
+            continue;
+
+         if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+            nv50->cb_dirty = TRUE;
+      }
+   }
+
+   /* If there are any coherent constbufs, flush the cache */
+   if (nv50->cb_dirty) {
+      BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
+      PUSH_DATA (push, 0);
+      nv50->cb_dirty = FALSE;
+   }
+
   if (nv50->vbo_fifo) {
      nv50_push_vbo(nv50, info);
      push->kick_notify = nv50_default_kick_notify;
--- a/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
+++ b/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
@@ -67,10 +67,15 @@ struct iparm {
         uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom
         uint8_t is_long_term; // 08
         uint8_t non_existing; // 09
+         uint8_t u0a; // 0a
+         uint8_t u0b; // 0b
         uint32_t frame_idx; // 0c
         uint32_t field_order_cnt[2]; // 10
         uint32_t mvidx; // 18
         uint8_t field_pic_flag; // 1c
+         uint8_t u1d; // 1d
+         uint8_t u1e; // 1e
+         uint8_t u1f; // 1f
         // 20
      } refs[0x10]; // 1e0
   } ipicparm; // 150
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -60,7 +60,7 @@ static void
 nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
   struct nvc0_context *nvc0 = nvc0_context(pipe);
-   int i;
+   int i, s;

   if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
      for (i = 0; i < nvc0->num_vtxbufs; ++i) {
@@ -73,6 +73,26 @@ nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags)
      if (nvc0->idxbuf.buffer &&
          nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
         nvc0->base.vbo_dirty = TRUE;
+
+      for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+         uint32_t valid = nvc0->constbuf_valid[s];
+
+         while (valid && !nvc0->cb_dirty) {
+            const unsigned i = ffs(valid) - 1;
+            struct pipe_resource *res;
+
+            valid &= ~(1 << i);
+            if (nvc0->constbuf[s][i].user)
+               continue;
+
+            res = nvc0->constbuf[s][i].u.buf;
+            if (!res)
+               continue;
+
+            if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+               nvc0->cb_dirty = TRUE;
+         }
+      }
   }
 }

--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -154,6 +154,8 @@ struct nvc0_context {

   struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS];
   uint16_t constbuf_dirty[6];
+   uint16_t constbuf_valid[6];
+   boolean cb_dirty;

   struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
   unsigned num_vtxbufs;
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -626,7 +626,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
   if (info->bin.tlsSpace) {
      assert(info->bin.tlsSpace < (1 << 24));
      prog->hdr[0] |= 1 << 26;
-      prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
+      prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
      prog->need_tls = TRUE;
   }
   /* TODO: factor 2 only needed where joinat/precont is used,
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -808,10 +808,15 @@ nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
   if (nvc0->constbuf[s][i].user) {
      nvc0->constbuf[s][i].u.data = cb->user_buffer;
      nvc0->constbuf[s][i].size = cb->buffer_size;
+      nvc0->constbuf_valid[s] |= 1 << i;
   } else
   if (cb) {
      nvc0->constbuf[s][i].offset = cb->buffer_offset;
      nvc0->constbuf[s][i].size = align(cb->buffer_size, 0x100);
+      nvc0->constbuf_valid[s] |= 1 << i;
+   }
+   else {
+      nvc0->constbuf_valid[s] &= ~(1 << i);
   }
 }

--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -797,7 +797,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
   struct nvc0_context *nvc0 = nvc0_context(pipe);
   struct nouveau_pushbuf *push = nvc0->base.pushbuf;
-   int i;
+   int i, s;

   /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
   nvc0->vb_elt_first = info->min_index + info->index_bias;
@@ -830,6 +830,31 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)

   push->kick_notify = nvc0_draw_vbo_kick_notify;

+   for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+      uint32_t valid = nvc0->constbuf_valid[s];
+
+      while (valid && !nvc0->cb_dirty) {
+         const unsigned i = ffs(valid) - 1;
+         struct pipe_resource *res;
+
+         valid &= ~(1 << i);
+         if (nvc0->constbuf[s][i].user)
+            continue;
+
+         res = nvc0->constbuf[s][i].u.buf;
+         if (!res)
+            continue;
+
+         if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+            nvc0->cb_dirty = TRUE;
+      }
+   }
+
+   if (nvc0->cb_dirty) {
+      IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
+      nvc0->cb_dirty = FALSE;
+   }
+
   if (nvc0->state.vbo_mode) {
      nvc0_push_vbo(nvc0, info);
      push->kick_notify = nvc0_default_kick_notify;
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
@@ -80,8 +80,9 @@ NVC0_FIFO_PKHDR_NI(int subc, int mthd, unsigned size)
 }

 static INLINE uint32_t
-NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint8_t data)
+NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint16_t data)
 {
+   assert(data < 0x2000);
   return 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2);
 }

@@ -133,7 +134,7 @@ BEGIN_1IC0(struct nouveau_pushbuf *push, int subc, int mthd, unsigned size)
 }

 static INLINE void
-IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, uint8_t data)
+IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, uint16_t data)
 {
 #ifndef NVC0_PUSH_EXPLICIT_SPACE_CHECKING
   PUSH_SPACE(push, 1);
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -37,6 +37,8 @@
 #include "r300_screen_buffer.h"
 #include "compiler/radeon_regalloc.h"

+#include <inttypes.h>
+
 static void r300_release_referenced_objects(struct r300_context *r300)
 {
    struct pipe_framebuffer_state *fb =
@@ -482,7 +484,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 #endif
        fprintf(stderr,
                "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
-                "r300: GART size: %d MB, VRAM size: %d MB\n"
+                "r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
                "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
                r300->screen->info.drm_major,
                r300->screen->info.drm_minor,
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -626,7 +626,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
 		S_030008_DATA_FORMAT(format) |
 		S_030008_NUM_FORMAT_ALL(num_format) |
 		S_030008_FORMAT_COMP_ALL(format_comp) |
-		S_030008_SRF_MODE_ALL(1) |
 		S_030008_ENDIAN_SWAP(endian);
 	view->tex_resource_words[3] = swizzle_res;
 	/*
@@ -805,7 +804,6 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 	}

 	view->tex_resource_words[4] = (word4 |
-				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
 				       S_030010_ENDIAN_SWAP(endian));
 	view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
 				      S_030014_LAST_ARRAY(state->u.tex.last_layer);
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2374,7 +2374,6 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
 		vtx.data_format = format;
 		vtx.num_format_all = num_format;
 		vtx.format_comp_all = format_comp;
-		vtx.srf_mode_all = 1;
 		vtx.offset = elements[i].src_offset;
 		vtx.endian = endian;

--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -430,7 +430,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 		 * disable fast clear for texture array.
 		 */
 		/* Only use htile for first level */
-		if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) {
+		if (rtex->htile_buffer && !level &&
+		    util_max_layer(&rtex->resource.b.b, level) == 0) {
 			if (rtex->depth_clear_value != depth) {
 				rtex->depth_clear_value = depth;
 				rctx->db_state.atom.dirty = true;
@@ -837,7 +838,7 @@ static void r600_flush_resource(struct pipe_context *ctx,

 	if (!rtex->is_depth && rtex->cmask.size) {
 		r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
-					   0, res->array_size - 1);
+					   0, util_max_layer(res, 0));
 	}
 }

--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -851,7 +851,6 @@ static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx
 	vtx.data_format = FMT_32_32_32_32_FLOAT;
 	vtx.num_format_all = 2;		/* NUM_FORMAT_SCALED */
 	vtx.format_comp_all = 1;	/* FORMAT_COMP_SIGNED */
-	vtx.srf_mode_all = 1;		/* SRF_MODE_NO_ZERO */
 	vtx.endian = r600_endian_swap(32);

 	if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
@@ -4309,7 +4308,6 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
 	vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;		/* SEL_Z */
 	vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;		/* SEL_W */
 	vtx.use_const_fields = 1;
-	vtx.srf_mode_all = 1;		/* SRF_MODE_NO_ZERO */

 	if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
 		return r;
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -609,7 +609,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
 		S_038008_DATA_FORMAT(format) |
 		S_038008_NUM_FORMAT_ALL(num_format) |
 		S_038008_FORMAT_COMP_ALL(format_comp) |
-		S_038008_SRF_MODE_ALL(1) |
 		S_038008_ENDIAN_SWAP(endian);
 	view->tex_resource_words[3] = 0;
 	/*
@@ -720,7 +719,6 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
 		view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
 	}
 	view->tex_resource_words[4] = (word4 |
-				       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
 				       S_038010_REQUEST_SIZE(1) |
 				       S_038010_ENDIAN_SWAP(endian) |
 				       S_038010_BASE_LEVEL(0));
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -142,7 +142,13 @@ bool r600_common_context_init(struct r600_common_context *rctx,
 	rctx->ws = rscreen->ws;
 	rctx->family = rscreen->family;
 	rctx->chip_class = rscreen->chip_class;
-	rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
+
+	if (rscreen->family == CHIP_HAWAII)
+		rctx->max_db = 16;
+	else if (rscreen->chip_class >= EVERGREEN)
+		rctx->max_db = 8;
+	else
+		rctx->max_db = 4;

 	rctx->b.transfer_map = u_transfer_map_vtbl;
 	rctx->b.transfer_flush_region = u_default_transfer_flush_region;
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -72,6 +72,7 @@
 #define R600_CONTEXT_WAIT_3D_IDLE		(1 << 17)
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(1 << 18)
 #define R600_CONTEXT_VGT_FLUSH			(1 << 19)
+#define R600_CONTEXT_VGT_STREAMOUT_SYNC		(1 << 20)

 /* Debug flags. */
 /* logging */
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,

 	out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
 	out->alignment = MAX2(256, base_align);
-	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		    align(slice_bytes, base_align);
 }

 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
@@ -388,7 +389,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 				      struct r600_cmask_info *out)
 {
 	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
-	unsigned num_pipes = rscreen->tiling_info.num_channels;
+	unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
 	unsigned cl_width, cl_height;

 	switch (num_pipes) {
@@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 		out->slice_tile_max -= 1;

 	out->alignment = MAX2(256, base_align);
-	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		    align(slice_bytes, base_align);
 }

 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -485,7 +487,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 {
 	unsigned cl_width, cl_height, width, height;
 	unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
-	unsigned num_pipes = rscreen->tiling_info.num_channels;
+	unsigned num_pipes = rscreen->info.r600_num_tile_pipes;

 	/* HTILE is broken with 1D tiling on old kernels and CIK. */
 	if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
@@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 	pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
 	base_align = num_pipes * pipe_interleave_bytes;

-	return rtex->surface.array_size * align(slice_bytes, base_align);
+	return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+		align(slice_bytes, base_align);
 }

 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
--- a/src/gallium/drivers/radeon/radeon_llvm_util.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_util.c
@@ -100,13 +100,17 @@ LLVMModuleRef radeon_llvm_get_kernel_module(LLVMContextRef ctx, unsigned index,
 	kernel_metadata = MALLOC(num_kernels * sizeof(LLVMValueRef));
 	LLVMGetNamedMetadataOperands(mod, "opencl.kernels", kernel_metadata);
 	for (i = 0; i < num_kernels; i++) {
-		LLVMValueRef kernel_signature, kernel_function;
+		LLVMValueRef kernel_signature, *kernel_function;
+		unsigned num_kernel_md_operands;
 		if (i == index) {
 			continue;
 		}
 		kernel_signature = kernel_metadata[i];
-		LLVMGetMDNodeOperands(kernel_signature, &kernel_function);
-		LLVMDeleteFunction(kernel_function);
+		num_kernel_md_operands = LLVMGetMDNodeNumOperands(kernel_signature);
+		kernel_function = MALLOC(num_kernel_md_operands * sizeof (LLVMValueRef));
+		LLVMGetMDNodeOperands(kernel_signature, kernel_function);
+		LLVMDeleteFunction(*kernel_function);
+		FREE(kernel_function);
 	}
 	FREE(kernel_metadata);
 	radeon_llvm_optimize(mod);
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1378,7 +1378,11 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 	bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;

 	bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
+#if HAVE_LLVM >= 0x0305
+	bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq.clamped.f32";
+#else
 	bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
+#endif
 }

 void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -242,7 +242,10 @@ int rvid_get_video_param(struct pipe_screen *screen,
 		switch (param) {
 		case PIPE_VIDEO_CAP_SUPPORTED:
 			/* no support for MPEG4 */
-			return codec != PIPE_VIDEO_FORMAT_MPEG4;
+			return codec != PIPE_VIDEO_FORMAT_MPEG4 &&
+			       /* FIXME: VC-1 simple/main profile is broken */
+			       profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE &&
+			       profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
 		case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 		case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 			/* and MPEG2 only with shaders */
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -692,7 +692,6 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 	    !(dst->surface.flags & RADEON_SURF_SCANOUT) &&
 	    (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
 		si_blitter_begin(ctx, SI_COLOR_RESOLVE);
-t-cleared
 		util_blitter_custom_resolve_color(sctx->blitter,
 						  info->dst.resource, info->dst.level,
 						  info->dst.box.z,
@@ -736,7 +735,7 @@ static void si_flush_resource(struct pipe_context *ctx,

 	if (!rtex->is_depth && rtex->cmask.size) {
 		si_blit_decompress_color(ctx, rtex, 0, res->last_level,
-					 0, res->array_size - 1);
+					 0, util_max_layer(res, 0));
 	}
 }

--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -91,12 +91,13 @@ static void si_dma_copy_buffer(struct si_context *ctx,
 	}
 	ncopy = (size / max_csize) + !!(size % max_csize);

+	r600_need_dma_space(&ctx->b, ncopy * 5);
+
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
 			      RADEON_PRIO_MIN);
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
 			      RADEON_PRIO_MIN);

-	r600_need_dma_space(&ctx->b, ncopy * 5);
 	for (i = 0; i < ncopy; i++) {
 		csize = size < max_csize ? size : max_csize;
 		cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1539,9 +1539,8 @@ static void tex_fetch_args(
 	/* Pack LOD bias value */
 	if (opcode == TGSI_OPCODE_TXB)
 		address[count++] = coords[3];
-
-	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
-		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+	if (opcode == TGSI_OPCODE_TXB2)
+		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);

 	/* Pack depth comparison value */
 	switch (target) {
@@ -1558,6 +1557,9 @@ static void tex_fetch_args(
 		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
 	}

+	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
+		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+
 	/* Pack user derivatives */
 	if (opcode == TGSI_OPCODE_TXD) {
 		for (chan = 0; chan < 2; chan++) {
@@ -2497,6 +2499,7 @@ int si_pipe_shader_create(

 	bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
 	bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
+	bld_base->op_actions[TGSI_OPCODE_TXB2] = txb_action;
 #if HAVE_LLVM >= 0x0304
 	bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
 #endif
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -33,6 +33,7 @@
 #include "util/u_format.h"
 #include "util/u_index_modify.h"
 #include "util/u_memory.h"
+#include "util/u_prim.h"
 #include "util/u_upload_mgr.h"

 /*
@@ -425,16 +426,31 @@ static bool si_update_draw_info_state(struct si_context *sctx,
 					(rs ? rs->line_stipple_enable : false);
 		/* If the WD switch is false, the IA switch must be false too. */
 		bool ia_switch_on_eop = wd_switch_on_eop;
+		unsigned primgroup_size = 64;
+
+		/* Hawaii hangs if instancing is enabled and each instance
+		 * is smaller than a prim group and WD_SWITCH_ON_EOP is 0.
+		 * We don't know that for indirect drawing, so treat it as
+		 * always problematic. */
+		if (sctx->b.family == CHIP_HAWAII &&
+		    ((info->instance_count > 1 &&
+		      u_prims_for_vertices(info->mode, info->count) < primgroup_size))) {
+			wd_switch_on_eop = true;
+			ia_switch_on_eop = true;
+		}

-		si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
-			       S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
-			       S_028AA8_PARTIAL_VS_WAVE_ON(1) |
-			       S_028AA8_PRIMGROUP_SIZE(63) |
-			       S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
 		si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
 			       ib->index_size == 4 ? 0xFC000000 : 0xFC00);

-		si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+		si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+		si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+		si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
+			       S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+			       S_028AA8_PARTIAL_VS_WAVE_ON(1) |
+			       S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
+			       S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
+		si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+		si_pm4_cmd_end(pm4, false);
 	} else {
 		si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
 	}
@@ -902,11 +918,15 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 		radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
 	}
+	if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
+		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+		radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
+	}

 	sctx->flags = 0;
 }

-const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
+const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 17 }; /* number of CS dwords */

 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
@@ -985,6 +1005,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	}
 #endif

+	/* Workaround for a VGT hang when streamout is enabled.
+	 * It must be done after drawing. */
+	if (sctx->b.family == CHIP_HAWAII &&
+	    (sctx->b.streamout.streamout_enabled ||
+	     sctx->b.streamout.prims_gen_query_enabled)) {
+		sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
+	}
+
 	/* Set the depth buffer as dirty. */
 	if (sctx->framebuffer.state.zsbuf) {
 		struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -83,6 +83,8 @@
 #define PKT3_DRAW_INDEX_IMMD                   0x2E /* not on CIK */
 #define PKT3_NUM_INSTANCES                     0x2F
 #define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_DRAW_INDEX_OFFSET_2               0x35
+#define PKT3_DRAW_PREAMBLE                     0x36 /* new on CIK, required on GFX7.2 and later */
 #define PKT3_WRITE_DATA                        0x37
 #define     PKT3_WRITE_DATA_DST_SEL(x)             ((x) << 8)
 #define     PKT3_WRITE_DATA_DST_SEL_REG            0
--- a/src/gallium/state_trackers/clover/core/timestamp.cpp
+++ b/src/gallium/state_trackers/clover/core/timestamp.cpp
@@ -30,6 +30,7 @@ using namespace clover;
 timestamp::query::query(command_queue &q) :
   q(q),
   _query(q.pipe->create_query(q.pipe, PIPE_QUERY_TIMESTAMP)) {
+   q.pipe->end_query(q.pipe, _query);
 }

 timestamp::query::query(query &&other) :
--- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
+++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
@@ -117,12 +117,13 @@ namespace {
 #endif

   llvm::Module *
-   compile(const std::string &source, const std::string &name,
-           const std::string &triple, const std::string &processor,
-           const std::string &opts, clang::LangAS::Map& address_spaces) {
+   compile(llvm::LLVMContext &llvm_ctx, const std::string &source,
+           const std::string &name, const std::string &triple,
+           const std::string &processor, const std::string &opts,
+           clang::LangAS::Map& address_spaces) {

      clang::CompilerInstance c;
-      clang::EmitLLVMOnlyAction act(&llvm::getGlobalContext());
+      clang::EmitLLVMOnlyAction act(&llvm_ctx);
      std::string log;
      llvm::raw_string_ostream s_log(log);
      std::string libclc_path = LIBCLC_LIBEXECDIR + processor + "-"
@@ -187,6 +188,11 @@ namespace {
      c.getLangOpts().NoBuiltin = true;
      c.getTargetOpts().Triple = triple;
      c.getTargetOpts().CPU = processor;
+
+      // This is a workaround for a Clang bug which causes the number
+      // of warnings and errors to be printed to stderr.
+      // http://www.llvm.org/bugs/show_bug.cgi?id=19735
+      c.getDiagnosticOpts().ShowCarets = false;
 #if HAVE_LLVM <= 0x0301
      c.getInvocation().setLangDefaults(clang::IK_OpenCL);
 #else
@@ -394,10 +400,12 @@ clover::compile_program_llvm(const compat::string &source,
                      target.size() - processor_str_len - 1);
   clang::LangAS::Map address_spaces;

+   llvm::LLVMContext llvm_ctx;
+
   // The input file name must have the .cl extension in order for the
   // CompilerInvocation class to recognize it as an OpenCL source file.
-   llvm::Module *mod = compile(source, "input.cl", triple, processor, opts,
-                                                                address_spaces);
+   llvm::Module *mod = compile(llvm_ctx, source, "input.cl", triple, processor,
+                               opts, address_spaces);

   find_kernels(mod, kernels);

--- a/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
+++ b/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
@@ -448,9 +448,11 @@ wglChoosePixelFormatARB(
    */
   for (i = 0; i < count; i++) {
      if (scores[i].points > 0) {
-         if (*nNumFormats < nMaxFormats)
-            piFormats[*nNumFormats] = scores[i].index + 1;
+	 piFormats[*nNumFormats] = scores[i].index + 1;
         (*nNumFormats)++;
+	 if (*nNumFormats >= nMaxFormats) {
+	    break;
+	 }
      }
   }

--- a/src/gallium/state_trackers/xa/xa_composite.c
+++ b/src/gallium/state_trackers/xa/xa_composite.c
@@ -472,6 +472,9 @@ xa_composite_prepare(struct xa_context *ctx,
    struct xa_surface *dst_srf = comp->dst->srf;
    int ret;

+    if (comp->mask && !comp->mask->srf)
+	return -XA_ERR_INVAL;
+
    ret = xa_ctx_srf_create(ctx, dst_srf);
    if (ret != XA_ERR_NONE)
 	return ret;
--- a/src/gallium/state_trackers/xa/xa_tracker.c
+++ b/src/gallium/state_trackers/xa/xa_tracker.c
@@ -26,6 +26,7 @@
 * Thomas Hellstrom <thellstrom-at-vmware-dot-com>
 */

+#include <unistd.h>
 #include "xa_tracker.h"
 #include "xa_priv.h"
 #include "pipe/p_state.h"
@@ -140,11 +141,15 @@ xa_tracker_create(int drm_fd)
    struct xa_tracker *xa = calloc(1, sizeof(struct xa_tracker));
    enum xa_surface_type stype;
    unsigned int num_formats;
+    int loader_fd;

    if (!xa)
 	return NULL;

-    if (pipe_loader_drm_probe_fd(&xa->dev, drm_fd, false))
+    loader_fd = dup(drm_fd);
+    if (loader_fd == -1)
+        return NULL;
+    if (pipe_loader_drm_probe_fd(&xa->dev, loader_fd, false))
 	xa->screen = pipe_loader_create_screen(xa->dev, PIPE_SEARCH_DIR);
    if (!xa->screen)
 	goto out_no_screen;
--- a/src/gallium/targets/xa/Makefile.am
+++ b/src/gallium/targets/xa/Makefile.am
@@ -66,6 +66,9 @@ libxatracker_la_LDFLAGS = \
 	$(GC_SECTIONS) \
 	$(LD_NO_UNDEFINED)

+libxatracker_la_LDFLAGS += \
+	-Wl,--version-script=$(top_srcdir)/src/gallium/targets/xa/xa.sym
+
 if HAVE_MESA_LLVM
 libxatracker_la_LIBADD += $(LLVM_LIBS)
 libxatracker_la_LDFLAGS += $(LLVM_LDFLAGS)
--- a/src/gallium/targets/xa/xa.sym
+++ b/src/gallium/targets/xa/xa.sym
@@ -0,0 +1,38 @@
+{
+	global:
+		xa_composite_allocation;
+		xa_composite_check_accelerated;
+		xa_composite_done;
+		xa_composite_prepare;
+		xa_composite_rect;
+		xa_context_create;
+		xa_context_default;
+		xa_context_destroy;
+		xa_context_flush;
+		xa_copy;
+		xa_copy_done;
+		xa_copy_prepare;
+		xa_fence_get;
+		xa_fence_wait;
+		xa_fence_destroy;
+		xa_format_check_supported;
+		xa_solid;
+		xa_solid_done;
+		xa_solid_prepare;
+		xa_surface_create;
+		xa_surface_dma;
+		xa_surface_format;
+		xa_surface_from_handle;
+		xa_surface_handle;
+		xa_surface_map;
+		xa_surface_redefine;
+		xa_surface_ref;
+		xa_surface_unmap;
+		xa_surface_unref;
+		xa_tracker_create;
+		xa_tracker_destroy;
+		xa_tracker_version;
+		xa_yuv_planar_blit;
+	local:
+		*;
+};
--- a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
+++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
@@ -1,4 +1,5 @@
 #include <sys/stat.h>
+#include <unistd.h>
 #include "pipe/p_context.h"
 #include "pipe/p_state.h"
 #include "util/u_format.h"
@@ -59,7 +60,7 @@ nouveau_drm_screen_create(int fd)
 	struct nouveau_device *dev = NULL;
 	struct pipe_screen *(*init)(struct nouveau_device *);
 	struct nouveau_screen *screen;
-	int ret;
+	int ret, dupfd = -1;

 	pipe_mutex_lock(nouveau_screen_mutex);
 	if (!fd_tab) {
@@ -75,7 +76,17 @@ nouveau_drm_screen_create(int fd)
 		return &screen->base;
 	}

-	ret = nouveau_device_wrap(fd, 0, &dev);
+	/* Since the screen re-use is based on the device node and not the fd,
+	 * create a copy of the fd to be owned by the device. Otherwise a
+	 * scenario could occur where two screens are created, and the first
+	 * one is shut down, along with the fd being closed. The second
+	 * (identical) screen would now have a reference to the closed fd. We
+	 * avoid this by duplicating the original fd. Note that
+	 * nouveau_device_wrap does not close the fd in case of a device
+	 * creation error.
+	 */
+	dupfd = dup(fd);
+	ret = nouveau_device_wrap(dupfd, 1, &dev);
 	if (ret)
 		goto err;

@@ -114,6 +125,10 @@ nouveau_drm_screen_create(int fd)
 	return &screen->base;

 err:
+	if (dev)
+		nouveau_device_del(&dev);
+	else if (dupfd >= 0)
+		close(dupfd);
 	pipe_mutex_unlock(nouveau_screen_mutex);
 	return NULL;
 }
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -50,8 +50,8 @@ struct radeon_cs_context {

    int                         reloc_indices_hashlist[512];

-    unsigned                    used_vram;
-    unsigned                    used_gart;
+    uint64_t                    used_vram;
+    uint64_t                    used_gart;
 };

 struct radeon_drm_cs {
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -195,8 +195,8 @@ struct radeon_info {
    uint32_t                    pci_id;
    enum radeon_family          family;
    enum chip_class             chip_class;
-    uint32_t                    gart_size;
-    uint32_t                    vram_size;
+    uint64_t                    gart_size;
+    uint64_t                    vram_size;
    uint32_t                    max_sclk;

    uint32_t                    drm_major; /* version */
--- a/src/glx/dri2.c
+++ b/src/glx/dri2.c
@@ -131,10 +131,14 @@ DRI2WireToEvent(Display *dpy, XEvent *event, xEvent *wire)
      aevent->msc = ((CARD64)awire->msc_hi << 32) | awire->msc_lo;

      glxDraw = GetGLXDrawable(dpy, pdraw->drawable);
-      if (awire->sbc < glxDraw->lastEventSbc)
-	 glxDraw->eventSbcWrap += 0x100000000;
-      glxDraw->lastEventSbc = awire->sbc;
-      aevent->sbc = awire->sbc + glxDraw->eventSbcWrap;
+      if (glxDraw != NULL) {
+         if (awire->sbc < glxDraw->lastEventSbc)
+            glxDraw->eventSbcWrap += 0x100000000;
+         glxDraw->lastEventSbc = awire->sbc;
+         aevent->sbc = awire->sbc + glxDraw->eventSbcWrap;
+      } else {
+         aevent->sbc = awire->sbc;
+      }

      return True;
   }
--- a/src/glx/glxext.c
+++ b/src/glx/glxext.c
@@ -134,14 +134,15 @@ __glXWireToEvent(Display *dpy, XEvent *event, xEvent *wire)
      GLXBufferSwapComplete *aevent = (GLXBufferSwapComplete *)event;
      xGLXBufferSwapComplete2 *awire = (xGLXBufferSwapComplete2 *)wire;
      struct glx_drawable *glxDraw = GetGLXDrawable(dpy, awire->drawable);
-      aevent->event_type = awire->event_type;
-      aevent->drawable = awire->drawable;
-      aevent->ust = ((CARD64)awire->ust_hi << 32) | awire->ust_lo;
-      aevent->msc = ((CARD64)awire->msc_hi << 32) | awire->msc_lo;

      if (!glxDraw)
 	 return False;

+      aevent->event_type = awire->event_type;
+      aevent->drawable = glxDraw->xDrawable;
+      aevent->ust = ((CARD64)awire->ust_hi << 32) | awire->ust_lo;
+      aevent->msc = ((CARD64)awire->msc_hi << 32) | awire->msc_lo;
+
      if (awire->sbc < glxDraw->lastEventSbc)
 	 glxDraw->eventSbcWrap += 0x100000000;
      glxDraw->lastEventSbc = awire->sbc;
--- a/src/mesa/Android.libmesa_dricore.mk
+++ b/src/mesa/Android.libmesa_dricore.mk
@@ -47,10 +47,16 @@ ifeq ($(TARGET_ARCH),x86)
 endif # x86
 endif # MESA_ENABLE_ASM

+ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
+LOCAL_SRC_FILES += \
+	$(SRCDIR)main/streaming-load-memcpy.c
+endif
+
 LOCAL_C_INCLUDES := \
 	$(call intermediates-dir-for STATIC_LIBRARIES,libmesa_program,,) \
 	$(MESA_TOP)/src/mapi \
-	$(MESA_TOP)/src/glsl
+	$(MESA_TOP)/src/glsl \
+	$(MESA_TOP)/src/gallium/auxiliary

 LOCAL_WHOLE_STATIC_LIBRARIES := \
 	libmesa_program
--- a/src/mesa/Android.libmesa_glsl_utils.mk
+++ b/src/mesa/Android.libmesa_glsl_utils.mk
@@ -56,6 +56,7 @@ include $(CLEAR_VARS)

 LOCAL_MODULE := libmesa_glsl_utils
 LOCAL_IS_HOST_MODULE := true
+LOCAL_CFLAGS := -D_POSIX_C_SOURCE=199309L

 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/glsl \
--- a/src/mesa/Android.mesa_gen_matypes.mk
+++ b/src/mesa/Android.mesa_gen_matypes.mk
@@ -33,6 +33,7 @@ include $(CLEAR_VARS)

 LOCAL_MODULE := mesa_gen_matypes
 LOCAL_IS_HOST_MODULE := true
+LOCAL_CFLAGS := -D_POSIX_C_SOURCE=199309L

 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -801,7 +801,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
      int buf, real_color_buffers = 0;
      memset(save->ColorDrawBuffers, 0, sizeof(save->ColorDrawBuffers));

-      for (buf = 0; buf < MAX_DRAW_BUFFERS; buf++) {
+      for (buf = 0; buf < ctx->Const.MaxDrawBuffers; buf++) {
         int buf_index = ctx->DrawBuffer->_ColorDrawBufferIndexes[buf];
         if (buf_index == -1)
            continue;
@@ -1213,7 +1213,7 @@ _mesa_meta_end(struct gl_context *ctx)
      _mesa_BindRenderbuffer(GL_RENDERBUFFER, save->RenderbufferName);

   if (state & MESA_META_DRAW_BUFFERS) {
-      _mesa_DrawBuffers(MAX_DRAW_BUFFERS, save->ColorDrawBuffers);
+      _mesa_DrawBuffers(ctx->Const.MaxDrawBuffers, save->ColorDrawBuffers);
   }

   ctx->Meta->SaveStackDepth--;
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -405,7 +405,7 @@ blitframebuffer_texture(struct gl_context *ctx,
      }
   } else {
      GLenum tex_base_format;
-      int srcW = abs(srcY1 - srcY0);
+      int srcW = abs(srcX1 - srcX0);
      int srcH = abs(srcY1 - srcY0);
      /* Fall back to doing a CopyTexSubImage to get the destination
       * renderbuffer into a texture.
--- a/src/mesa/drivers/dri/Android.mk
+++ b/src/mesa/drivers/dri/Android.mk
@@ -43,6 +43,7 @@ MESA_DRI_C_INCLUDES := \

 MESA_DRI_WHOLE_STATIC_LIBRARIES := \
 	libmesa_glsl \
+	libmegadriver_stub \
 	libmesa_dri_common \
 	libmesa_dricore

--- a/src/mesa/drivers/dri/common/Android.mk
+++ b/src/mesa/drivers/dri/common/Android.mk
@@ -86,3 +86,20 @@ $(intermediates)/xmlpool/options.h: $$(PRIVATE_SCRIPT) $$(PRIVATE_TEMPLATE_HEADE

 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
+
+#
+# Build libmegadriver_stub
+#
+
+include $(CLEAR_VARS)
+include $(LOCAL_PATH)/Makefile.sources
+
+LOCAL_MODULE := libmegadriver_stub
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+LOCAL_C_INCLUDES := \
+    $(MESA_DRI_C_INCLUDES)
+
+LOCAL_SRC_FILES := $(megadriver_stub_FILES)
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
--- a/src/mesa/drivers/dri/common/Makefile.am
+++ b/src/mesa/drivers/dri/common/Makefile.am
@@ -42,7 +42,7 @@ libdricommon_la_SOURCES = $(DRI_COMMON_FILES)
 libdri_test_stubs_la_SOURCES = $(test_stubs_FILES)
 libdri_test_stubs_la_CFLAGS = $(AM_CFLAGS) -DNO_MAIN

-libmegadriver_stub_la_SOURCES = megadriver_stub.c
+libmegadriver_stub_la_SOURCES = $(megadriver_stub_FILES)

 sysconf_DATA = drirc

--- a/src/mesa/drivers/dri/common/Makefile.sources
+++ b/src/mesa/drivers/dri/common/Makefile.sources
@@ -14,3 +14,6 @@ mesa_dri_common_INCLUDES := \

 test_stubs_FILES := \
 	dri_test.c
+
+megadriver_stub_FILES := \
+	megadriver_stub.c
--- a/src/mesa/drivers/dri/i915/i830_texblend.c
+++ b/src/mesa/drivers/dri/i915/i830_texblend.c
@@ -445,7 +445,7 @@ i830EmitTextureBlend(struct i830_context *i830)
   I830_ACTIVESTATE(i830, I830_UPLOAD_TEXBLEND_ALL, false);

   if (ctx->Texture._MaxEnabledTexImageUnit != -1) {
-      for (unit = 0; unit < ctx->Texture._MaxEnabledTexImageUnit; unit++)
+      for (unit = 0; unit <= ctx->Texture._MaxEnabledTexImageUnit; unit++)
         if (ctx->Texture.Unit[unit]._Current)
            emit_texblend(i830, unit, blendunit++,
                          unit == ctx->Texture._MaxEnabledTexImageUnit);
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -1152,7 +1152,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
 {
   struct intel_screen *intelScreen;

-   if (psp->dri2.loader->base.version <= 2 ||
+   if (psp->image.loader) {
+   } else if (psp->dri2.loader->base.version <= 2 ||
       psp->dri2.loader->getBuffersWithFormat == NULL) {
      fprintf(stderr,
 	      "\nERROR!  DRI2 loader with getBuffersWithFormat() "
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1115,6 +1115,9 @@ struct brw_context

   struct brw_cache cache;

+   /** IDs for meta stencil blit shader programs. */
+   unsigned meta_stencil_blit_programs[2];
+
   /* Whether a meta-operation is in progress. */
   bool meta_in_progress;

--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -580,6 +580,16 @@
 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
 #define GEN7_SURFACE_MCS_PITCH_SHIFT            3
 #define GEN7_SURFACE_MCS_PITCH_MASK             INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_QPITCH_SHIFT           16
+#define GEN8_SURFACE_AUX_QPITCH_MASK            INTEL_MASK(30, 16)
+#define GEN8_SURFACE_AUX_PITCH_SHIFT            3
+#define GEN8_SURFACE_AUX_PITCH_MASK             INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_MODE_MASK              INTEL_MASK(2, 0)
+
+#define GEN8_SURFACE_AUX_MODE_NONE              0
+#define GEN8_SURFACE_AUX_MODE_MCS               1
+#define GEN8_SURFACE_AUX_MODE_APPEND            2
+#define GEN8_SURFACE_AUX_MODE_HIZ               3

 /* Surface state DW7 */
 #define GEN7_SURFACE_CLEAR_COLOR_SHIFT		28
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1263,19 +1263,21 @@ fs_visitor::emit_samplepos_setup(ir_variable *ir)
      stride(retype(brw_vec1_grf(c->sample_pos_reg, 0),
                    BRW_REGISTER_TYPE_B), 16, 8, 2);

-   emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
+   fs_inst *inst = emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
   if (dispatch_width == 16) {
-      fs_inst *inst = emit(MOV(half(int_sample_x, 1),
-                               fs_reg(suboffset(sample_pos_reg, 16))));
+      inst->force_uncompressed = true;
+      inst = emit(MOV(half(int_sample_x, 1),
+                      fs_reg(suboffset(sample_pos_reg, 16))));
      inst->force_sechalf = true;
   }
   /* Compute gl_SamplePosition.x */
   compute_sample_position(pos, int_sample_x);
   pos.reg_offset++;
-   emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
+   inst = emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
   if (dispatch_width == 16) {
-      fs_inst *inst = emit(MOV(half(int_sample_y, 1),
-                               fs_reg(suboffset(sample_pos_reg, 17))));
+      inst->force_uncompressed = true;
+      inst = emit(MOV(half(int_sample_y, 1),
+                      fs_reg(suboffset(sample_pos_reg, 17))));
      inst->force_sechalf = true;
   }
   /* Compute gl_SamplePosition.y */
@@ -1309,13 +1311,22 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
       * populating a temporary variable with the sequence (0, 1, 2, 3),
       * and then reading from it using vstride=1, width=4, hstride=0.
       * These computations hold good for 4x multisampling as well.
+       *
+       * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
+       * the first four slots are sample 0 of subspan 0; the next four
+       * are sample 1 of subspan 0; the third group is sample 0 of
+       * subspan 1, and finally sample 1 of subspan 1.
       */
-      emit(BRW_OPCODE_AND, t1,
-           fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
-           fs_reg(brw_imm_d(0xc0)));
-      emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
+      fs_inst *inst;
+      inst = emit(BRW_OPCODE_AND, t1,
+                  fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
+                  fs_reg(0xc0));
+      inst->force_writemask_all = true;
+      inst = emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
+      inst->force_writemask_all = true;
      /* This works for both SIMD8 and SIMD16 */
-      emit(MOV(t2, brw_imm_v(0x3210)));
+      inst = emit(MOV(t2, brw_imm_v(c->key.persample_2x ? 0x1010 : 0x3210)));
+      inst->force_writemask_all = true;
      /* This special instruction takes care of setting vstride=1,
       * width=4, hstride=0 of t2 during an ADD instruction.
       */
@@ -1393,7 +1404,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
    * Gen 6 hardware ignores source modifiers (negate and abs) on math
    * instructions, so we also move to a temp to set those up.
    */
-   if (brw->gen >= 6)
+   if (brw->gen == 6 || brw->gen == 7)
      src = fix_math_operand(src);

   fs_inst *inst = emit(opcode, dst, src);
@@ -1425,7 +1436,9 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
      return NULL;
   }

-   if (brw->gen >= 6) {
+   if (brw->gen >= 8) {
+      inst = emit(opcode, dst, src0, src1);
+   } else if (brw->gen >= 6) {
      src0 = fix_math_operand(src0);
      src1 = fix_math_operand(src1);

@@ -2406,7 +2419,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
    * program.
    */
   for (fs_inst *scan_inst = (fs_inst *)inst->prev;
-        scan_inst != NULL;
+        !scan_inst->is_head_sentinel();
        scan_inst = (fs_inst *)scan_inst->prev) {

      /* If we hit control flow, assume that there *are* outstanding
@@ -2533,6 +2546,8 @@ fs_visitor::insert_gen4_send_dependency_workarounds()
   if (brw->gen != 4 || brw->is_g4x)
      return;

+   bool progress = false;
+
   /* Note that we're done with register allocation, so GRF fs_regs always
    * have a .reg_offset of 0.
    */
@@ -2543,8 +2558,12 @@ fs_visitor::insert_gen4_send_dependency_workarounds()
      if (inst->mlen != 0 && inst->dst.file == GRF) {
         insert_gen4_pre_send_dependency_workarounds(inst);
         insert_gen4_post_send_dependency_workarounds(inst);
+         progress = true;
      }
   }
+
+   if (progress)
+      invalidate_live_intervals();
 }

 /**
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -368,7 +368,6 @@ public:
   bool opt_cse_local(bblock_t *block, exec_list *aeb);
   bool opt_copy_propagate();
   bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
-   bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
   bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
                                 exec_list *acp);
   void opt_drop_redundant_mov_to_flags();
--- a/Show More
+++ b/Show More
@@ -1 +1 @@
 .2.0
 .2.5