Compare commits
30 Commits
mesa-10.2.
...
mesa-10.2.
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816d37e5c5 |
@@ -5,3 +5,14 @@ e6967270c75a5b669152127bb7a746d55f4407a6 i965: Fix depth (array slices) computat
|
||||
# This patch didn't have enough in the commit message to convince me it
|
||||
# is a bug fix, (email sent to author asking for more information).
|
||||
41d759d076737f94976f5294b734dbc437a12bae
|
||||
|
||||
# These patch were already cherry-picked before the 10.2.4 release.
|
||||
#
|
||||
# But get-pick-list.sh doesn't realize that because the commit messages for
|
||||
# these on the stable branch reference commit IDs that don't actually appear
|
||||
# on master. I'm not sure what happened, (perhaps master was force-pushed at
|
||||
# some point?).
|
||||
2eaf3f670fea4ce4466340141244e41a45542c13
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||||
e5adc560cc8544200faa3e04504202839626ab37
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||||
cf1b5eee7f36af29d1d5caba3538ad4985e51f81
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||||
|
||||
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||||
@@ -31,9 +31,11 @@ because compatibility contexts are not supported.
|
||||
|
||||
<h2>SHA256 checksums</h2>
|
||||
<pre>
|
||||
06a2341244eb85c283f59f70161e06ded106f835ed9b6be1ef0243bd9344811a MesaLib-10.2.4.tar.bz2
|
||||
33e3c8b4343503e7d7d17416c670438860a2fd99ec93ea3327f73c3abe33b5e4 MesaLib-10.2.4.tar.gz
|
||||
e26791a4a62a61b82e506e6ba031812d09697d1a831e8239af67e5722a8ee538 MesaLib-10.2.4.zip
|
||||
</pre>
|
||||
|
||||
|
||||
<h2>New features</h2>
|
||||
<p>None</p>
|
||||
|
||||
|
||||
185
docs/relnotes/10.2.5.html
Normal file
185
docs/relnotes/10.2.5.html
Normal file
@@ -0,0 +1,185 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta http-equiv="content-type" content="text/html; charset=utf-8">
|
||||
<title>Mesa Release Notes</title>
|
||||
<link rel="stylesheet" type="text/css" href="../mesa.css">
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<div class="header">
|
||||
<h1>The Mesa 3D Graphics Library</h1>
|
||||
</div>
|
||||
|
||||
<iframe src="../contents.html"></iframe>
|
||||
<div class="content">
|
||||
|
||||
<h1>Mesa 10.2.5 Release Notes / August 2, 2014</h1>
|
||||
|
||||
<p>
|
||||
Mesa 10.2.5 is a bug fix release which fixes bugs found since the 10.2.4 release.
|
||||
</p>
|
||||
<p>
|
||||
Mesa 10.2.5 implements the OpenGL 3.3 API, but the version reported by
|
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glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
|
||||
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
|
||||
Some drivers don't support all the features required in OpenGL 3.3. OpenGL
|
||||
3.3 is <strong>only</strong> available if requested at context creation
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||||
because compatibility contexts are not supported.
|
||||
</p>
|
||||
|
||||
<h2>SHA256 checksums</h2>
|
||||
<pre>
|
||||
</pre>
|
||||
|
||||
<h2>New features</h2>
|
||||
<p>None</p>
|
||||
|
||||
<h2>Bug fixes</h2>
|
||||
|
||||
<p>This list is likely incomplete.</p>
|
||||
|
||||
<ul>
|
||||
|
||||
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80991">Bug 80991</a> - [BDW]Piglit spec_ARB_sample_shading_builtin-gl-sample-mask_2 fails</li>
|
||||
|
||||
</ul>
|
||||
|
||||
<h2>Changes</h2>
|
||||
|
||||
<p>Abdiel Janulgue (3):</p>
|
||||
<ul>
|
||||
<li>i965/fs: Refactor check for potential copy propagated instructions.</li>
|
||||
<li>i965/fs: skip copy-propate for logical instructions with negated src entries</li>
|
||||
<li>i965/vec4: skip copy-propate for logical instructions with negated src entries</li>
|
||||
</ul>
|
||||
|
||||
<p>Adel Gadllah (1):</p>
|
||||
<ul>
|
||||
<li>i915: Fix up intelInitScreen2 for DRI3</li>
|
||||
</ul>
|
||||
|
||||
<p>Anuj Phogat (2):</p>
|
||||
<ul>
|
||||
<li>i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()</li>
|
||||
<li>mesa: Don't use memcpy() in _mesa_texstore() for float depth texture data</li>
|
||||
</ul>
|
||||
|
||||
<p>Brian Paul (3):</p>
|
||||
<ul>
|
||||
<li>mesa: fix geometry shader memory leaks</li>
|
||||
<li>st/mesa: fix geometry shader memory leak</li>
|
||||
<li>gallium/u_blitter: fix some shader memory leaks</li>
|
||||
</ul>
|
||||
|
||||
<p>Carl Worth (6):</p>
|
||||
<ul>
|
||||
<li>docs: Add sha256 checksums for the 10.2.3 release</li>
|
||||
<li>Update VERSION to 10.2.4</li>
|
||||
<li>Add release notes for 10.2.4</li>
|
||||
<li>docs: Add SHA256 checksums for the 10.2.4 release</li>
|
||||
<li>cherry-ignore: Ignore a few patches picked in the previous stable release</li>
|
||||
<li>Update version to 10.2.5</li>
|
||||
</ul>
|
||||
|
||||
<p>Christian König (1):</p>
|
||||
<ul>
|
||||
<li>radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc</li>
|
||||
</ul>
|
||||
|
||||
<p>Eric Anholt (1):</p>
|
||||
<ul>
|
||||
<li>i965: Generalize the pixel_x/y workaround for all UW types.</li>
|
||||
</ul>
|
||||
|
||||
<p>Ian Romanick (2):</p>
|
||||
<ul>
|
||||
<li>mesa: Don't allow GL_TEXTURE_BORDER queries outside compat profile</li>
|
||||
<li>mesa: Don't allow GL_TEXTURE_{LUMINANCE,INTENSITY}_* queries outside compat profile</li>
|
||||
</ul>
|
||||
|
||||
<p>Ilia Mirkin (5):</p>
|
||||
<ul>
|
||||
<li>nv50/ir: retrieve shadow compare from first arg</li>
|
||||
<li>nv50/ir: ignore bias for samplerCubeShadow on nv50</li>
|
||||
<li>nvc0/ir: do quadops on the right texture coordinates for TXD</li>
|
||||
<li>nvc0/ir: use manual TXD when offsets are involved</li>
|
||||
<li>nvc0: make sure that the local memory allocation is aligned to 0x10</li>
|
||||
</ul>
|
||||
|
||||
<p>Jason Ekstrand (2):</p>
|
||||
<ul>
|
||||
<li>main/format_pack: Fix a wrong datatype in pack_ubyte_R8G8_UNORM</li>
|
||||
<li>main/get_hash_params: Add GL_SAMPLE_SHADING_ARB</li>
|
||||
</ul>
|
||||
|
||||
<p>Jordan Justen (1):</p>
|
||||
<ul>
|
||||
<li>i965: Add auxiliary surface field #defines for Broadwell.</li>
|
||||
</ul>
|
||||
|
||||
<p>José Fonseca (1):</p>
|
||||
<ul>
|
||||
<li>st/wgl: Clamp wglChoosePixelFormatARB's output nNumFormats to nMaxFormats.</li>
|
||||
</ul>
|
||||
|
||||
<p>Kenneth Graunke (13):</p>
|
||||
<ul>
|
||||
<li>i965: Don't copy propagate abs into Broadwell logic instructions.</li>
|
||||
<li>i965: Set execution size to 8 for instructions with force_sechalf set.</li>
|
||||
<li>i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.</li>
|
||||
<li>i965/fs: Use WE_all for gl_SampleID header register munging.</li>
|
||||
<li>i965: Add plumbing for Broadwell's auxiliary surface support.</li>
|
||||
<li>i965: Drop SINT workaround for CMS layout on Broadwell.</li>
|
||||
<li>i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.</li>
|
||||
<li>i965: Add 2x MSAA support to the MCS allocation function.</li>
|
||||
<li>i965: Enable compressed multisample support (CMS) on Broadwell.</li>
|
||||
<li>i965: Add missing persample_shading field to brw_wm_debug_recompile.</li>
|
||||
<li>i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.</li>
|
||||
<li>i965/fs: Fix gl_SampleMask handling for SIMD16 on Gen8+.</li>
|
||||
<li>i965/fs: Set LastRT on the final FB write on Broadwell.</li>
|
||||
</ul>
|
||||
|
||||
<p>Marek Olšák (14):</p>
|
||||
<ul>
|
||||
<li>gallium: fix u_default_transfer_inline_write for textures</li>
|
||||
<li>st/mesa: fix samplerCubeShadow with bias</li>
|
||||
<li>radeonsi: fix samplerCubeShadow with bias</li>
|
||||
<li>radeonsi: add support for TXB2</li>
|
||||
<li>r600g: switch SNORM conversion to DX and GLES behavior</li>
|
||||
<li>radeonsi: fix CMASK and HTILE calculations for Hawaii</li>
|
||||
<li>gallium/util: add a helper for calculating primitive count from vertex count</li>
|
||||
<li>radeonsi: fix a hang with instancing on Hawaii</li>
|
||||
<li>radeonsi: fix a hang with streamout on Hawaii</li>
|
||||
<li>winsys/radeon: fix vram_size overflow with Hawaii</li>
|
||||
<li>radeonsi: fix occlusion queries on Hawaii</li>
|
||||
<li>r600g,radeonsi: switch all occurences of array_size to util_max_layer</li>
|
||||
<li>radeonsi: fix build because of lack of draw_indirect infrastructure in 10.2</li>
|
||||
<li>radeonsi: use DRAW_PREAMBLE on CIK</li>
|
||||
</ul>
|
||||
|
||||
<p>Matt Turner (8):</p>
|
||||
<ul>
|
||||
<li>i965/vec4: Don't return void from a void function.</li>
|
||||
<li>i965/vec4: Don't fix_math_operand() on Gen >= 8.</li>
|
||||
<li>i965/fs: Don't fix_math_operand() on Gen >= 8.</li>
|
||||
<li>i965/fs: Make try_constant_propagate() static.</li>
|
||||
<li>i965/fs: Constant propagate into 2-src math instructions on Gen8.</li>
|
||||
<li>i965/vec4: Constant propagate into 2-src math instructions on Gen8.</li>
|
||||
<li>i965/fs: Don't use brw_imm_* unnecessarily.</li>
|
||||
<li>i965/fs: Set correct number of regs_written for MCS fetches.</li>
|
||||
</ul>
|
||||
|
||||
<p>Thorsten Glaser (1):</p>
|
||||
<ul>
|
||||
<li>nv50: fix build failure on m68k due to invalid struct alignment assumptions</li>
|
||||
</ul>
|
||||
|
||||
<p>Tom Stellard (1):</p>
|
||||
<ul>
|
||||
<li>clover: Call end_query before getting timestamp result v2</li>
|
||||
</ul>
|
||||
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
@@ -136,6 +136,21 @@ u_prim_vertex_count(unsigned prim)
|
||||
return (likely(prim < PIPE_PRIM_MAX)) ? &prim_table[prim] : NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Given a vertex count, return the number of primitives.
|
||||
* For polygons, return the number of triangles.
|
||||
*/
|
||||
static INLINE unsigned
|
||||
u_prims_for_vertices(unsigned prim, unsigned num)
|
||||
{
|
||||
const struct u_prim_vertex_count *info = u_prim_vertex_count(prim);
|
||||
|
||||
if (num < info->min)
|
||||
return 0;
|
||||
|
||||
return 1 + ((num - info->min) / info->incr);
|
||||
}
|
||||
|
||||
static INLINE boolean u_validate_pipe_prim( unsigned pipe_prim, unsigned nr )
|
||||
{
|
||||
const struct u_prim_vertex_count *count = u_prim_vertex_count(pipe_prim);
|
||||
|
||||
@@ -67,10 +67,15 @@ struct iparm {
|
||||
uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom
|
||||
uint8_t is_long_term; // 08
|
||||
uint8_t non_existing; // 09
|
||||
uint8_t u0a; // 0a
|
||||
uint8_t u0b; // 0b
|
||||
uint32_t frame_idx; // 0c
|
||||
uint32_t field_order_cnt[2]; // 10
|
||||
uint32_t mvidx; // 18
|
||||
uint8_t field_pic_flag; // 1c
|
||||
uint8_t u1d; // 1d
|
||||
uint8_t u1e; // 1e
|
||||
uint8_t u1f; // 1f
|
||||
// 20
|
||||
} refs[0x10]; // 1e0
|
||||
} ipicparm; // 150
|
||||
|
||||
@@ -626,7 +626,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
|
||||
if (info->bin.tlsSpace) {
|
||||
assert(info->bin.tlsSpace < (1 << 24));
|
||||
prog->hdr[0] |= 1 << 26;
|
||||
prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
|
||||
prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
|
||||
prog->need_tls = TRUE;
|
||||
}
|
||||
/* TODO: factor 2 only needed where joinat/precont is used,
|
||||
|
||||
@@ -37,6 +37,8 @@
|
||||
#include "r300_screen_buffer.h"
|
||||
#include "compiler/radeon_regalloc.h"
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
static void r300_release_referenced_objects(struct r300_context *r300)
|
||||
{
|
||||
struct pipe_framebuffer_state *fb =
|
||||
@@ -482,7 +484,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
|
||||
#endif
|
||||
fprintf(stderr,
|
||||
"r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
|
||||
"r300: GART size: %d MB, VRAM size: %d MB\n"
|
||||
"r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
|
||||
"r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
|
||||
r300->screen->info.drm_major,
|
||||
r300->screen->info.drm_minor,
|
||||
|
||||
@@ -626,7 +626,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
|
||||
S_030008_DATA_FORMAT(format) |
|
||||
S_030008_NUM_FORMAT_ALL(num_format) |
|
||||
S_030008_FORMAT_COMP_ALL(format_comp) |
|
||||
S_030008_SRF_MODE_ALL(1) |
|
||||
S_030008_ENDIAN_SWAP(endian);
|
||||
view->tex_resource_words[3] = swizzle_res;
|
||||
/*
|
||||
@@ -805,7 +804,6 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
|
||||
}
|
||||
|
||||
view->tex_resource_words[4] = (word4 |
|
||||
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
|
||||
S_030010_ENDIAN_SWAP(endian));
|
||||
view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
|
||||
S_030014_LAST_ARRAY(state->u.tex.last_layer);
|
||||
|
||||
@@ -2374,7 +2374,6 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
|
||||
vtx.data_format = format;
|
||||
vtx.num_format_all = num_format;
|
||||
vtx.format_comp_all = format_comp;
|
||||
vtx.srf_mode_all = 1;
|
||||
vtx.offset = elements[i].src_offset;
|
||||
vtx.endian = endian;
|
||||
|
||||
|
||||
@@ -430,7 +430,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
|
||||
* disable fast clear for texture array.
|
||||
*/
|
||||
/* Only use htile for first level */
|
||||
if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) {
|
||||
if (rtex->htile_buffer && !level &&
|
||||
util_max_layer(&rtex->resource.b.b, level) == 0) {
|
||||
if (rtex->depth_clear_value != depth) {
|
||||
rtex->depth_clear_value = depth;
|
||||
rctx->db_state.atom.dirty = true;
|
||||
@@ -837,7 +838,7 @@ static void r600_flush_resource(struct pipe_context *ctx,
|
||||
|
||||
if (!rtex->is_depth && rtex->cmask.size) {
|
||||
r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
|
||||
0, res->array_size - 1);
|
||||
0, util_max_layer(res, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -851,7 +851,6 @@ static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx
|
||||
vtx.data_format = FMT_32_32_32_32_FLOAT;
|
||||
vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
|
||||
vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
|
||||
vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
|
||||
vtx.endian = r600_endian_swap(32);
|
||||
|
||||
if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
|
||||
@@ -4309,7 +4308,6 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
|
||||
vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
|
||||
vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
|
||||
vtx.use_const_fields = 1;
|
||||
vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
|
||||
|
||||
if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
|
||||
return r;
|
||||
|
||||
@@ -609,7 +609,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
|
||||
S_038008_DATA_FORMAT(format) |
|
||||
S_038008_NUM_FORMAT_ALL(num_format) |
|
||||
S_038008_FORMAT_COMP_ALL(format_comp) |
|
||||
S_038008_SRF_MODE_ALL(1) |
|
||||
S_038008_ENDIAN_SWAP(endian);
|
||||
view->tex_resource_words[3] = 0;
|
||||
/*
|
||||
@@ -720,7 +719,6 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
|
||||
view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
|
||||
}
|
||||
view->tex_resource_words[4] = (word4 |
|
||||
S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
|
||||
S_038010_REQUEST_SIZE(1) |
|
||||
S_038010_ENDIAN_SWAP(endian) |
|
||||
S_038010_BASE_LEVEL(0));
|
||||
|
||||
@@ -142,7 +142,13 @@ bool r600_common_context_init(struct r600_common_context *rctx,
|
||||
rctx->ws = rscreen->ws;
|
||||
rctx->family = rscreen->family;
|
||||
rctx->chip_class = rscreen->chip_class;
|
||||
rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
|
||||
|
||||
if (rscreen->family == CHIP_HAWAII)
|
||||
rctx->max_db = 16;
|
||||
else if (rscreen->chip_class >= EVERGREEN)
|
||||
rctx->max_db = 8;
|
||||
else
|
||||
rctx->max_db = 4;
|
||||
|
||||
rctx->b.transfer_map = u_transfer_map_vtbl;
|
||||
rctx->b.transfer_flush_region = u_default_transfer_flush_region;
|
||||
|
||||
@@ -72,6 +72,7 @@
|
||||
#define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
|
||||
#define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
|
||||
#define R600_CONTEXT_VGT_FLUSH (1 << 19)
|
||||
#define R600_CONTEXT_VGT_STREAMOUT_SYNC (1 << 20)
|
||||
|
||||
/* Debug flags. */
|
||||
/* logging */
|
||||
|
||||
@@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
|
||||
|
||||
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
|
||||
out->alignment = MAX2(256, base_align);
|
||||
out->size = rtex->surface.array_size * align(slice_bytes, base_align);
|
||||
out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
|
||||
align(slice_bytes, base_align);
|
||||
}
|
||||
|
||||
static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
|
||||
@@ -388,7 +389,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
|
||||
struct r600_cmask_info *out)
|
||||
{
|
||||
unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
|
||||
unsigned num_pipes = rscreen->tiling_info.num_channels;
|
||||
unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
|
||||
unsigned cl_width, cl_height;
|
||||
|
||||
switch (num_pipes) {
|
||||
@@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
|
||||
out->slice_tile_max -= 1;
|
||||
|
||||
out->alignment = MAX2(256, base_align);
|
||||
out->size = rtex->surface.array_size * align(slice_bytes, base_align);
|
||||
out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
|
||||
align(slice_bytes, base_align);
|
||||
}
|
||||
|
||||
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
|
||||
@@ -485,7 +487,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
|
||||
{
|
||||
unsigned cl_width, cl_height, width, height;
|
||||
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
|
||||
unsigned num_pipes = rscreen->tiling_info.num_channels;
|
||||
unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
|
||||
|
||||
/* HTILE is broken with 1D tiling on old kernels and CIK. */
|
||||
if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
|
||||
@@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
|
||||
pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
|
||||
base_align = num_pipes * pipe_interleave_bytes;
|
||||
|
||||
return rtex->surface.array_size * align(slice_bytes, base_align);
|
||||
return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
|
||||
align(slice_bytes, base_align);
|
||||
}
|
||||
|
||||
static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
|
||||
|
||||
@@ -735,7 +735,7 @@ static void si_flush_resource(struct pipe_context *ctx,
|
||||
|
||||
if (!rtex->is_depth && rtex->cmask.size) {
|
||||
si_blit_decompress_color(ctx, rtex, 0, res->last_level,
|
||||
0, res->array_size - 1);
|
||||
0, util_max_layer(res, 0));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -91,12 +91,13 @@ static void si_dma_copy_buffer(struct si_context *ctx,
|
||||
}
|
||||
ncopy = (size / max_csize) + !!(size % max_csize);
|
||||
|
||||
r600_need_dma_space(&ctx->b, ncopy * 5);
|
||||
|
||||
r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
|
||||
RADEON_PRIO_MIN);
|
||||
r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
|
||||
RADEON_PRIO_MIN);
|
||||
|
||||
r600_need_dma_space(&ctx->b, ncopy * 5);
|
||||
for (i = 0; i < ncopy; i++) {
|
||||
csize = size < max_csize ? size : max_csize;
|
||||
cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
|
||||
|
||||
@@ -33,6 +33,7 @@
|
||||
#include "util/u_format.h"
|
||||
#include "util/u_index_modify.h"
|
||||
#include "util/u_memory.h"
|
||||
#include "util/u_prim.h"
|
||||
#include "util/u_upload_mgr.h"
|
||||
|
||||
/*
|
||||
@@ -425,16 +426,31 @@ static bool si_update_draw_info_state(struct si_context *sctx,
|
||||
(rs ? rs->line_stipple_enable : false);
|
||||
/* If the WD switch is false, the IA switch must be false too. */
|
||||
bool ia_switch_on_eop = wd_switch_on_eop;
|
||||
unsigned primgroup_size = 64;
|
||||
|
||||
/* Hawaii hangs if instancing is enabled and each instance
|
||||
* is smaller than a prim group and WD_SWITCH_ON_EOP is 0.
|
||||
* We don't know that for indirect drawing, so treat it as
|
||||
* always problematic. */
|
||||
if (sctx->b.family == CHIP_HAWAII &&
|
||||
((info->instance_count > 1 &&
|
||||
u_prims_for_vertices(info->mode, info->count) < primgroup_size))) {
|
||||
wd_switch_on_eop = true;
|
||||
ia_switch_on_eop = true;
|
||||
}
|
||||
|
||||
si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
|
||||
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
|
||||
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
|
||||
S_028AA8_PRIMGROUP_SIZE(63) |
|
||||
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
|
||||
si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
|
||||
ib->index_size == 4 ? 0xFC000000 : 0xFC00);
|
||||
|
||||
si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
|
||||
si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
|
||||
si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
|
||||
si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
|
||||
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
|
||||
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
|
||||
S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
|
||||
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
|
||||
si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
|
||||
si_pm4_cmd_end(pm4, false);
|
||||
} else {
|
||||
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
|
||||
}
|
||||
@@ -902,11 +918,15 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
|
||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
||||
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
|
||||
}
|
||||
if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
|
||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
||||
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
|
||||
}
|
||||
|
||||
sctx->flags = 0;
|
||||
}
|
||||
|
||||
const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
|
||||
const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 17 }; /* number of CS dwords */
|
||||
|
||||
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
|
||||
{
|
||||
@@ -985,6 +1005,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Workaround for a VGT hang when streamout is enabled.
|
||||
* It must be done after drawing. */
|
||||
if (sctx->b.family == CHIP_HAWAII &&
|
||||
(sctx->b.streamout.streamout_enabled ||
|
||||
sctx->b.streamout.prims_gen_query_enabled)) {
|
||||
sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
|
||||
}
|
||||
|
||||
/* Set the depth buffer as dirty. */
|
||||
if (sctx->framebuffer.state.zsbuf) {
|
||||
struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
|
||||
|
||||
@@ -83,6 +83,8 @@
|
||||
#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
|
||||
#define PKT3_NUM_INSTANCES 0x2F
|
||||
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
|
||||
#define PKT3_DRAW_INDEX_OFFSET_2 0x35
|
||||
#define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */
|
||||
#define PKT3_WRITE_DATA 0x37
|
||||
#define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8)
|
||||
#define PKT3_WRITE_DATA_DST_SEL_REG 0
|
||||
|
||||
@@ -30,6 +30,7 @@ using namespace clover;
|
||||
timestamp::query::query(command_queue &q) :
|
||||
q(q),
|
||||
_query(q.pipe->create_query(q.pipe, PIPE_QUERY_TIMESTAMP)) {
|
||||
q.pipe->end_query(q.pipe, _query);
|
||||
}
|
||||
|
||||
timestamp::query::query(query &&other) :
|
||||
|
||||
@@ -448,9 +448,11 @@ wglChoosePixelFormatARB(
|
||||
*/
|
||||
for (i = 0; i < count; i++) {
|
||||
if (scores[i].points > 0) {
|
||||
if (*nNumFormats < nMaxFormats)
|
||||
piFormats[*nNumFormats] = scores[i].index + 1;
|
||||
piFormats[*nNumFormats] = scores[i].index + 1;
|
||||
(*nNumFormats)++;
|
||||
if (*nNumFormats >= nMaxFormats) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -50,8 +50,8 @@ struct radeon_cs_context {
|
||||
|
||||
int reloc_indices_hashlist[512];
|
||||
|
||||
unsigned used_vram;
|
||||
unsigned used_gart;
|
||||
uint64_t used_vram;
|
||||
uint64_t used_gart;
|
||||
};
|
||||
|
||||
struct radeon_drm_cs {
|
||||
|
||||
@@ -195,8 +195,8 @@ struct radeon_info {
|
||||
uint32_t pci_id;
|
||||
enum radeon_family family;
|
||||
enum chip_class chip_class;
|
||||
uint32_t gart_size;
|
||||
uint32_t vram_size;
|
||||
uint64_t gart_size;
|
||||
uint64_t vram_size;
|
||||
uint32_t max_sclk;
|
||||
|
||||
uint32_t drm_major; /* version */
|
||||
|
||||
@@ -1152,7 +1152,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
|
||||
{
|
||||
struct intel_screen *intelScreen;
|
||||
|
||||
if (psp->dri2.loader->base.version <= 2 ||
|
||||
if (psp->image.loader) {
|
||||
} else if (psp->dri2.loader->base.version <= 2 ||
|
||||
psp->dri2.loader->getBuffersWithFormat == NULL) {
|
||||
fprintf(stderr,
|
||||
"\nERROR! DRI2 loader with getBuffersWithFormat() "
|
||||
|
||||
@@ -1311,6 +1311,11 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
|
||||
* populating a temporary variable with the sequence (0, 1, 2, 3),
|
||||
* and then reading from it using vstride=1, width=4, hstride=0.
|
||||
* These computations hold good for 4x multisampling as well.
|
||||
*
|
||||
* For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
|
||||
* the first four slots are sample 0 of subspan 0; the next four
|
||||
* are sample 1 of subspan 0; the third group is sample 0 of
|
||||
* subspan 1, and finally sample 1 of subspan 1.
|
||||
*/
|
||||
fs_inst *inst;
|
||||
inst = emit(BRW_OPCODE_AND, t1,
|
||||
@@ -1320,7 +1325,7 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
|
||||
inst = emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
|
||||
inst->force_writemask_all = true;
|
||||
/* This works for both SIMD8 and SIMD16 */
|
||||
inst = emit(MOV(t2, brw_imm_v(0x3210)));
|
||||
inst = emit(MOV(t2, brw_imm_v(c->key.persample_2x ? 0x1010 : 0x3210)));
|
||||
inst->force_writemask_all = true;
|
||||
/* This special instruction takes care of setting vstride=1,
|
||||
* width=4, hstride=0 of t2 during an ADD instruction.
|
||||
|
||||
@@ -280,6 +280,10 @@ brw_wm_debug_recompile(struct brw_context *brw,
|
||||
old_key->stats_wm, key->stats_wm);
|
||||
found |= key_debug(brw, "flat shading",
|
||||
old_key->flat_shade, key->flat_shade);
|
||||
found |= key_debug(brw, "per-sample shading",
|
||||
old_key->persample_shading, key->persample_shading);
|
||||
found |= key_debug(brw, "per-sample shading and 2x MSAA",
|
||||
old_key->persample_2x, key->persample_2x);
|
||||
found |= key_debug(brw, "number of color buffers",
|
||||
old_key->nr_color_regions, key->nr_color_regions);
|
||||
found |= key_debug(brw, "MRT alpha test or alpha-to-coverage",
|
||||
@@ -525,6 +529,8 @@ static void brw_wm_populate_key( struct brw_context *brw,
|
||||
/* Ignore sample qualifier while computing this flag. */
|
||||
key->persample_shading =
|
||||
_mesa_get_min_invocations_per_fragment(ctx, &fp->program, true) > 1;
|
||||
if (key->persample_shading)
|
||||
key->persample_2x = ctx->DrawBuffer->Visual.samples == 2;
|
||||
|
||||
key->compute_pos_offset =
|
||||
_mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1 &&
|
||||
|
||||
@@ -62,6 +62,7 @@ struct brw_wm_prog_key {
|
||||
GLuint stats_wm:1;
|
||||
GLuint flat_shade:1;
|
||||
GLuint persample_shading:1;
|
||||
GLuint persample_2x:1;
|
||||
GLuint nr_color_regions:5;
|
||||
GLuint replicate_alpha:1;
|
||||
GLuint render_to_fbo:1;
|
||||
|
||||
@@ -113,10 +113,8 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir)
|
||||
|
||||
uint32_t msg_control = msg_type;
|
||||
|
||||
/* "Last Render Target Select" must be set on all writes to the last of
|
||||
* the render targets (if using MRT), or always for a single RT scenario.
|
||||
*/
|
||||
if ((ir->target == c->key.nr_color_regions - 1) || !c->key.nr_color_regions)
|
||||
/* Set "Last Render Target Select" on the final FB write. */
|
||||
if (ir->eot)
|
||||
msg_control |= (1 << 4); /* Last Render Target Select */
|
||||
|
||||
uint32_t surf_index =
|
||||
@@ -713,13 +711,8 @@ gen8_fs_generator::generate_set_omask(fs_inst *inst,
|
||||
mask.hstride == BRW_HORIZONTAL_STRIDE_0);
|
||||
}
|
||||
|
||||
unsigned save_exec_size = default_state.exec_size;
|
||||
default_state.exec_size = BRW_EXECUTE_8;
|
||||
|
||||
gen8_instruction *mov = MOV(dst, retype(mask, dst.type));
|
||||
gen8_set_mask_control(mov, BRW_MASK_DISABLE);
|
||||
|
||||
default_state.exec_size = save_exec_size;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -2135,9 +2135,9 @@ intel_miptree_unmap_depthstencil(struct brw_context *brw,
|
||||
x + s_image_x + map->x,
|
||||
y + s_image_y + map->y,
|
||||
brw->has_swizzling);
|
||||
ptrdiff_t z_offset = ((y + z_image_y) *
|
||||
ptrdiff_t z_offset = ((y + z_image_y + map->y) *
|
||||
(z_mt->pitch / 4) +
|
||||
(x + z_image_x));
|
||||
(x + z_image_x + map->x));
|
||||
|
||||
if (map_z32f_x24s8) {
|
||||
z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0];
|
||||
|
||||
@@ -888,7 +888,7 @@ pack_float_R_UNORM8(const GLfloat src[4], void *dst)
|
||||
static void
|
||||
pack_ubyte_R8G8_UNORM(const GLubyte src[4], void *dst)
|
||||
{
|
||||
GLubyte *d = ((GLubyte *) dst);
|
||||
GLushort *d = ((GLushort *) dst);
|
||||
*d = PACK_COLOR_88(src[GCOMP], src[RCOMP]);
|
||||
}
|
||||
|
||||
|
||||
@@ -84,6 +84,7 @@ descriptor=[
|
||||
[ "SAMPLES_ARB", "BUFFER_INT(Visual.samples), extra_new_buffers" ],
|
||||
|
||||
# GL_ARB_sample_shading
|
||||
[ "SAMPLE_SHADING_ARB", "CONTEXT_BOOL(Multisample.SampleShading), extra_gl40_ARB_sample_shading" ],
|
||||
[ "MIN_SAMPLE_SHADING_VALUE_ARB", "CONTEXT_FLOAT(Multisample.MinSampleShadingValue), extra_gl40_ARB_sample_shading" ],
|
||||
|
||||
# GL_SGIS_generate_mipmap
|
||||
|
||||
@@ -1107,6 +1107,8 @@ get_tex_level_parameter_image(struct gl_context *ctx,
|
||||
}
|
||||
break;
|
||||
case GL_TEXTURE_BORDER:
|
||||
if (ctx->API != API_OPENGL_COMPAT)
|
||||
goto invalid_pname;
|
||||
*params = img->Border;
|
||||
break;
|
||||
case GL_TEXTURE_RED_SIZE:
|
||||
@@ -1120,6 +1122,8 @@ get_tex_level_parameter_image(struct gl_context *ctx,
|
||||
break;
|
||||
case GL_TEXTURE_INTENSITY_SIZE:
|
||||
case GL_TEXTURE_LUMINANCE_SIZE:
|
||||
if (ctx->API != API_OPENGL_COMPAT)
|
||||
goto invalid_pname;
|
||||
if (_mesa_base_format_has_channel(img->_BaseFormat, pname)) {
|
||||
*params = _mesa_get_format_bits(texFormat, pname);
|
||||
if (*params == 0) {
|
||||
@@ -1166,12 +1170,15 @@ get_tex_level_parameter_image(struct gl_context *ctx,
|
||||
break;
|
||||
|
||||
/* GL_ARB_texture_float */
|
||||
case GL_TEXTURE_LUMINANCE_TYPE_ARB:
|
||||
case GL_TEXTURE_INTENSITY_TYPE_ARB:
|
||||
if (ctx->API != API_OPENGL_COMPAT)
|
||||
goto invalid_pname;
|
||||
/* FALLTHROUGH */
|
||||
case GL_TEXTURE_RED_TYPE_ARB:
|
||||
case GL_TEXTURE_GREEN_TYPE_ARB:
|
||||
case GL_TEXTURE_BLUE_TYPE_ARB:
|
||||
case GL_TEXTURE_ALPHA_TYPE_ARB:
|
||||
case GL_TEXTURE_LUMINANCE_TYPE_ARB:
|
||||
case GL_TEXTURE_INTENSITY_TYPE_ARB:
|
||||
case GL_TEXTURE_DEPTH_TYPE_ARB:
|
||||
if (!ctx->Extensions.ARB_texture_float)
|
||||
goto invalid_pname;
|
||||
|
||||
@@ -3908,6 +3908,21 @@ _mesa_texstore_can_use_memcpy(struct gl_context *ctx,
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
/* Depth texture data needs clamping in following cases:
|
||||
* - Floating point dstFormat with signed srcType: clamp to [0.0, 1.0].
|
||||
* - Fixed point dstFormat with signed srcType: clamp to [0, 2^n -1].
|
||||
*
|
||||
* All the cases except one (float dstFormat with float srcType) are ruled
|
||||
* out by _mesa_format_matches_format_and_type() check above. Handle the
|
||||
* remaining case here.
|
||||
*/
|
||||
if ((baseInternalFormat == GL_DEPTH_COMPONENT ||
|
||||
baseInternalFormat == GL_DEPTH_STENCIL) &&
|
||||
(srcType == GL_FLOAT ||
|
||||
srcType == GL_FLOAT_32_UNSIGNED_INT_24_8_REV)) {
|
||||
return GL_FALSE;
|
||||
}
|
||||
|
||||
return GL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user