docs: Add sha256 sums for the 10.3.7 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Add release notes for the 10.3.7 release
2015-01-12 10:17:08 +00:00 · 2015-01-12 10:06:40 +00:00 · 2015-01-12 10:02:08 +00:00 · 2015-01-07 16:34:27 +00:00 · 2015-01-07 16:12:31 +00:00 · 2015-01-06 15:31:33 +00:00
63 changed files with 1020 additions and 160 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-10.3.3
+10.3.7
--- a/bin/get-pick-list.sh
+++ b/bin/get-pick-list.sh
@@ -14,7 +14,7 @@ git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
 	sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked

 # Grep for commits that were marked as a candidate for the stable tree.
-git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*mesa-stable\)' HEAD..origin/master |\
+git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*10\.3.*mesa-stable\)' HEAD..origin/master |\
 while read sha
 do
 	# Check to see whether the patch is on the ignore list.
--- a/configure.ac
+++ b/configure.ac
@@ -32,7 +32,7 @@ LIBDRM_RADEON_REQUIRED=2.4.56
 LIBDRM_INTEL_REQUIRED=2.4.52
 LIBDRM_NVVIEUX_REQUIRED=2.4.33
 LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41"
-LIBDRM_FREEDRENO_REQUIRED=2.4.55
+LIBDRM_FREEDRENO_REQUIRED=2.4.57
 DRI2PROTO_REQUIRED=2.6
 DRI3PROTO_REQUIRED=1.0
 PRESENTPROTO_REQUIRED=1.0
@@ -237,7 +237,16 @@ AC_SUBST([VISIBILITY_CXXFLAGS])
 dnl
 dnl Optional flags, check for compiler support
 dnl
-AX_CHECK_COMPILE_FLAG([-msse4.1], [SSE41_SUPPORTED=1], [SSE41_SUPPORTED=0])
+save_CFLAGS="$CFLAGS"
+CFLAGS="-msse4.1 $CFLAGS"
+AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
+#include <smmintrin.h>
+int main () {
+    __m128i a = _mm_set1_epi32 (0), b = _mm_set1_epi32 (0), c;
+    c = _mm_max_epu32(a, b);
+    return 0;
+}]])], SSE41_SUPPORTED=1)
+CFLAGS="$save_CFLAGS"
 if test "x$SSE41_SUPPORTED" = x1; then
    DEFINES="$DEFINES -DUSE_SSE41"
 fi
--- a/docs/relnotes/10.2.html
+++ b/docs/relnotes/10.2.html
@@ -88,6 +88,8 @@ following options during configure, if you would like support for svga driver
 Note: The files are installed in $(libdir)/gallium-pipe/ and the interface
 between them and libxatracker.so is <strong>not</strong> stable.
 </p>
+
+<li>The environment variable GALLIUM_MSAA that forced a multisample GLX visual was removed.</li>
 </ul>

 </div>
--- a/docs/relnotes/10.3.3.html
+++ b/docs/relnotes/10.3.3.html
@@ -30,7 +30,9 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+23a0c36d88cd5d8968ae6454160de2878192fd1d37b5d606adca1f1b7e788b79  MesaLib-10.3.3.tar.gz
+0e4eee4a2ddf86456eed2fc44da367f95471f74249636710491e85cc256c4753  MesaLib-10.3.3.tar.bz2
+a83648f17d776b7cf6c813fbb15782d2644b937dc6a7c53d8c0d1b35411f4840  MesaLib-10.3.3.zip
 </pre>

 <h2>New features</h2>
--- a/docs/relnotes/10.3.4.html
+++ b/docs/relnotes/10.3.4.html
@@ -0,0 +1,106 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.3.4 Release Notes / November 21, 2014</h1>
+
+<p>
+Mesa 10.3.4 is a bug fix release which fixes bugs found since the 10.3.3 release.
+</p>
+<p>
+Mesa 10.3.4 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+26482495ef6177f889dbd87c7edcccfedd995598785bbbd7e3e066352574c8e0  MesaLib-10.3.4.tar.gz
+e6373913142338d10515daf619d659433bfd2989988198930c13b0945a15e98a  MesaLib-10.3.4.tar.bz2
+8c3ebbb6535daf3414305860ebca6ac67dbb6e3d35058c7a6ce18b84b5945b7f  MesaLib-10.3.4.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=76252">Bug 76252</a> - Dynamic loading/unloading of opengl32.dll results in a deadlock</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78770">Bug 78770</a> - [SNB bisected]Webglc conformance/textures/texture-size-limit.html fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=83500">Bug 83500</a> - si_dma_copy_tile causes GPU hangs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85647">Bug 85647</a> - Random radeonsi crashes with mesa 10.3.x</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Brian Paul (1):</p>
+<ul>
+  <li>st/mesa: copy sampler_array_size field when copying instructions</li>
+</ul>
+
+<p>Chad Versace (1):</p>
+<ul>
+  <li>i965: Fix segfault in WebGL Conformance on Ivybridge</li>
+</ul>
+
+<p>Dave Airlie (5):</p>
+<ul>
+  <li>r600g/cayman: fix integer multiplication output overwrite (v2)</li>
+  <li>r600g/cayman: fix texture gather tests</li>
+  <li>r600g/cayman: handle empty vertex shaders</li>
+  <li>r600g: geom shaders: always load texture src regs from inputs</li>
+  <li>r600g: limit texture offset application to specific types (v2)</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.3.3 release</li>
+  <li>configure.ac: roll up a program for the sse4.1 check</li>
+  <li>get-pick-list.sh: Require explicit "10.3" for nominating stable patches</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+  <li>st/mesa: add a fallback for clear_with_quad when no vs_layer</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>llvmpipe: Avoid deadlock when unloading opengl32.dll</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>i915g: we also have more than 0 viewports!</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeonsi: Disable asynchronous DMA except for PIPE_BUFFER</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.3.5.html
+++ b/docs/relnotes/10.3.5.html
@@ -0,0 +1,88 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.3.5 Release Notes / December 5, 2014</h1>
+
+<p>
+Mesa 10.3.5 is a bug fix release which fixes bugs found since the 10.3.4 release.
+</p>
+<p>
+Mesa 10.3.5 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+7ea71c3cce89114df3dc050376afa1c6f6bf235d77a68f9703273603d6a90621  MesaLib-10.3.5.tar.gz
+eb75d2790f1606d59d50a6acaa637b6c75f2155b3e0eca3d5099165c0d9556ae  MesaLib-10.3.5.tar.bz2
+164bc64ba63fb07ff255ff8de6ed3c95ff545dfe8f864c44c33abe94788da910  MesaLib-10.3.5.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=86618">Bug 86618</a> - [NV96] neg modifiers not working in MIN and MAX operations</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Brian Paul (2):</p>
+<ul>
+  <li>mesa: fix arithmetic error in _mesa_compute_compressed_pixelstore()</li>
+  <li>mesa: fix height error check for 1D array textures</li>
+</ul>
+
+<p>Chris Forbes (2):</p>
+<ul>
+  <li>i965: Handle nested uniform array indexing</li>
+  <li>mesa: Fix Get(GL_TRANSPOSE_CURRENT_MATRIX_ARB) to transpose</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.3.5 release</li>
+  <li>Update version to 10.3.5</li>
+</ul>
+
+<p>Ilia Mirkin (6):</p>
+<ul>
+  <li>nv50/ir: set neg modifiers on min/max args</li>
+  <li>nv50,nvc0: actually check constbufs for invalidation</li>
+  <li>nv50,nvc0: buffer resources can be bound as other things down the line</li>
+  <li>freedreno/ir3: don't pass consts to madsh.m16 in MOD logic</li>
+  <li>freedreno/a3xx: only enable blend clamp for non-float formats</li>
+  <li>freedreno/ir3: fix UMAD</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+  <li>configure.ac: bump libdrm_freedreno requirement</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.3.6.html
+++ b/docs/relnotes/10.3.6.html
@@ -0,0 +1,124 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.3.6 Release Notes / December 29, 2014</h1>
+
+<p>
+Mesa 10.3.6 is a bug fix release which fixes bugs found since the 10.3.5 release.
+</p>
+<p>
+Mesa 10.3.6 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+c4d053d6bc6604cb5c93c99e0ef2e815c539f26dc5a03737eb3809bc1767d12f  MesaLib-10.3.6.tar.gz
+8d43673c6788fbf85f9c36c3a95c61ccf46f8835fc9c0d85d34474490d80572b  MesaLib-10.3.6.tar.bz2
+6b5b1e9a13949cfdb76fe51e8dcc3ea71e464a5ca73d11fdc29c20c4ba3f411a  MesaLib-10.3.6.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60879">Bug 60879</a> - [radeonsi] X11 can't start with acceleration enabled</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82585">Bug 82585</a> - geometry shader with optional out variable segfaults</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=82991">Bug 82991</a> - Inverted bumpmap in webgl applications</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=84777">Bug 84777</a> - [BSW]Piglit spec_glsl-1.50_execution_geometry-basic fails</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Andres Gomez (1):</p>
+<ul>
+  <li>i965/brw_reg: struct constructor now needs explicit negate and abs values.</li>
+</ul>
+
+<p>Ben Widawsky (1):</p>
+<ul>
+  <li>i965/gs: Avoid DW * DW mul</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>r600g: only init GS_VERT_ITEMSIZE on r600</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.3.5 release</li>
+  <li>Revert "glx/dri3: Request non-vsynced Present for swapinterval zero. (v3)"</li>
+  <li>Update version to 10.3.6</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>linker: Wrap access of producer_var with a NULL check</li>
+  <li>linker: Assign varying locations geometry shader inputs for SSO</li>
+</ul>
+
+<p>Ilia Mirkin (3):</p>
+<ul>
+  <li>util/primconvert: pass index bias through</li>
+  <li>util/primconvert: support instanced rendering</li>
+  <li>util/primconvert: take ib offset into account</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>util/primconvert: Avoid point arithmetic; apply offset on all cases.</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>docs/relnotes: document the removal of GALLIUM_MSAA</li>
+</ul>
+
+<p>Mario Kleiner (4):</p>
+<ul>
+  <li>glx/dri3: Fix glXWaitForSbcOML() to handle targetSBC==0 correctly. (v2)</li>
+  <li>glx/dri3: Track separate (ust, msc) for PresentPixmap vs. PresentNotifyMsc (v2)</li>
+  <li>glx/dri3: Request non-vsynced Present for swapinterval zero. (v3)</li>
+  <li>glx/dri3: Don't fail on glXSwapBuffersMscOML(dpy, window, 0, 0, 0) (v2)</li>
+</ul>
+
+<p>Maxence Le Doré (1):</p>
+<ul>
+  <li>glsl: Add gl_MaxViewports to available builtin constants</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+  <li>radeonsi: Program RASTER_CONFIG for harvested GPUs v5</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.3.7.html
+++ b/docs/relnotes/10.3.7.html
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.3.7 Release Notes / January 12, 2015</h1>
+
+<p>
+Mesa 10.3.7 is a bug fix release which fixes bugs found since the 10.3.6 release.
+</p>
+<p>
+Mesa 10.3.7 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3.  OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+bc13f33c19bc9f44a0565fdd51a8f9d1c0153a3365c429ceaf4ef43b7022b052  MesaLib-10.3.7.tar.gz
+43c6ced15e237cbb21b3082d7c0b42777c50c1f731d0d4b5efb5231063fb6a5b  MesaLib-10.3.7.tar.bz2
+d821fd46baf804fecfcf403e901800a4b996c7dd1c83f20a354b46566a49026f  MesaLib-10.3.7.zip
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85529">Bug 85529</a> - Surfaces not drawn in Unvanquished</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=87619">Bug 87619</a> - Changes to state such as render targets change fragment shader without marking it dirty.</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Chad Versace (2):</p>
+<ul>
+  <li>i965: Use safer pointer arithmetic in intel_texsubimage_tiled_memcpy()</li>
+  <li>i965: Use safer pointer arithmetic in gather_oa_results()</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+  <li>docs: Add sha256 sums for the 10.3.6 release</li>
+  <li>Update version to 10.3.7</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+  <li>nv50,nvc0: set vertex id base to index_bias</li>
+  <li>nv50/ir: fix texture offsets in release builds</li>
+</ul>
+
+<p>Kenneth Graunke (2):</p>
+<ul>
+  <li>i965: Add missing BRW_NEW_*_PROG_DATA to texture/renderbuffer atoms.</li>
+  <li>i965: Fix start/base_vertex_location for &gt;1 prims but !BRW_NEW_VERTICES.</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>glsl_to_tgsi: fix a bug in copy propagation</li>
+  <li>vbo: ignore primitive restart if FixedIndex is enabled in DrawArrays</li>
+  <li>st/mesa: fix GL_PRIMITIVE_RESTART_FIXED_INDEX</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -327,6 +327,7 @@ DRM drivers that don't have a full-fledged GEM (such as qxl or simpledrm)</li>
 <li>Removed support for the GL_ATI_envmap_bumpmap extension</li>
 <li>The hacky --enable-32/64-bit is no longer available in configure. To build
 32/64 bit mesa refer to the default method recommended by your distribution</li>
+</li>The environment variable GALLIUM_MSAA that forced a multisample GLX visual was removed.</li>
 </ul>

 </div>
--- a/src/gallium/auxiliary/indices/u_primconvert.c
+++ b/src/gallium/auxiliary/indices/u_primconvert.c
@@ -123,6 +123,9 @@ util_primconvert_draw_vbo(struct primconvert_context *pc,
   new_info.indexed = true;
   new_info.min_index = info->min_index;
   new_info.max_index = info->max_index;
+   new_info.index_bias = info->index_bias;
+   new_info.start_instance = info->start_instance;
+   new_info.instance_count = info->instance_count;

   if (info->indexed) {
      u_index_translator(pc->primtypes_mask,
@@ -135,6 +138,7 @@ util_primconvert_draw_vbo(struct primconvert_context *pc,
         src = pipe_buffer_map(pc->pipe, ib->buffer,
                               PIPE_TRANSFER_READ, &src_transfer);
      }
+      src = (const uint8_t *)src + ib->offset;
   }
   else {
      u_index_generator(pc->primtypes_mask,
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -124,6 +124,76 @@ void *util_make_layered_clear_vertex_shader(struct pipe_context *pipe)
   return pipe->create_vs_state(pipe, &state);
 }

+/**
+ * Takes position and color, and outputs position, color, and instance id.
+ */
+void *util_make_layered_clear_helper_vertex_shader(struct pipe_context *pipe)
+{
+   static const char text[] =
+         "VERT\n"
+         "DCL IN[0]\n"
+         "DCL IN[1]\n"
+         "DCL SV[0], INSTANCEID\n"
+         "DCL OUT[0], POSITION\n"
+         "DCL OUT[1], GENERIC[0]\n"
+         "DCL OUT[2], GENERIC[1]\n"
+
+         "MOV OUT[0], IN[0]\n"
+         "MOV OUT[1], IN[1]\n"
+         "MOV OUT[2].x, SV[0].xxxx\n"
+         "END\n";
+   struct tgsi_token tokens[1000];
+   struct pipe_shader_state state = {tokens};
+
+   if (!tgsi_text_translate(text, tokens, Elements(tokens))) {
+      assert(0);
+      return NULL;
+   }
+   return pipe->create_vs_state(pipe, &state);
+}
+
+/**
+ * Takes position, color, and target layer, and emits vertices on that target
+ * layer, with the specified color.
+ */
+void *util_make_layered_clear_geometry_shader(struct pipe_context *pipe)
+{
+   static const char text[] =
+      "GEOM\n"
+      "PROPERTY GS_INPUT_PRIMITIVE TRIANGLES\n"
+      "PROPERTY GS_OUTPUT_PRIMITIVE TRIANGLE_STRIP\n"
+      "PROPERTY GS_MAX_OUTPUT_VERTICES 3\n"
+      "PROPERTY GS_INVOCATIONS 1\n"
+      "DCL IN[][0], POSITION\n" /* position */
+      "DCL IN[][1], GENERIC[0]\n" /* color */
+      "DCL IN[][2], GENERIC[1]\n" /* vs invocation */
+      "DCL OUT[0], POSITION\n"
+      "DCL OUT[1], GENERIC[0]\n"
+      "DCL OUT[2], LAYER\n"
+      "IMM[0] INT32 {0, 0, 0, 0}\n"
+
+      "MOV OUT[0], IN[0][0]\n"
+      "MOV OUT[1], IN[0][1]\n"
+      "MOV OUT[2].x, IN[0][2].xxxx\n"
+      "EMIT IMM[0].xxxx\n"
+      "MOV OUT[0], IN[1][0]\n"
+      "MOV OUT[1], IN[1][1]\n"
+      "MOV OUT[2].x, IN[1][2].xxxx\n"
+      "EMIT IMM[0].xxxx\n"
+      "MOV OUT[0], IN[2][0]\n"
+      "MOV OUT[1], IN[2][1]\n"
+      "MOV OUT[2].x, IN[2][2].xxxx\n"
+      "EMIT IMM[0].xxxx\n"
+      "END\n";
+   struct tgsi_token tokens[1000];
+   struct pipe_shader_state state = {tokens};
+
+   if (!tgsi_text_translate(text, tokens, Elements(tokens))) {
+      assert(0);
+      return NULL;
+   }
+   return pipe->create_gs_state(pipe, &state);
+}

 /**
 * Make simple fragment texture shader:
--- a/src/gallium/auxiliary/util/u_simple_shaders.h
+++ b/src/gallium/auxiliary/util/u_simple_shaders.h
@@ -59,6 +59,12 @@ util_make_vertex_passthrough_shader_with_so(struct pipe_context *pipe,
 extern void *
 util_make_layered_clear_vertex_shader(struct pipe_context *pipe);

+extern void *
+util_make_layered_clear_helper_vertex_shader(struct pipe_context *pipe);
+
+extern void *
+util_make_layered_clear_geometry_shader(struct pipe_context *pipe);
+
 extern void *
 util_make_fragment_tex_shader_writemask(struct pipe_context *pipe, 
                                        unsigned tex_target,
--- a/src/gallium/drivers/freedreno/a3xx/fd3_blend.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_blend.c
@@ -105,8 +105,7 @@ fd3_blend_state_create(struct pipe_context *pctx,
 				A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(fd_blend_factor(rt->rgb_dst_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(fd_blend_factor(rt->alpha_src_factor)) |
 				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(blend_func(rt->alpha_func)) |
-				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(fd_blend_factor(rt->alpha_dst_factor)) |
-				A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE;
+				A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(fd_blend_factor(rt->alpha_dst_factor));

 		so->rb_mrt[i].control =
 				A3XX_RB_MRT_CONTROL_ROP_CODE(rop) |
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -566,16 +566,20 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		}
 	}

-	if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
+	if ((dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) && ctx->blend) {
 		struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
 		uint32_t i;

 		for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
+			bool is_float = util_format_is_float(
+					pipe_surface_format(ctx->framebuffer.cbufs[i]));
+
 			OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 			OUT_RING(ring, blend->rb_mrt[i].control);

 			OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
-			OUT_RING(ring, blend->rb_mrt[i].blend_control);
+			OUT_RING(ring, blend->rb_mrt[i].blend_control |
+					COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
 		}
 	}

--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -2136,7 +2136,7 @@ trans_cov(const struct instr_translater *t,
 *  madsh.m16 tmp1, a, b, tmp0 (mul-add shift high mix, i.e. ah * bl << 16)
 *  madsh.m16 dst, b, a, tmp1 (i.e. al * bh << 16)
 *
- * For UMAD, replace first mull.u with mad.u16.
+ * For UMAD, add in the extra argument after mull.u.
 */
 static void
 trans_umul(const struct instr_translater *t,
@@ -2159,16 +2159,16 @@ trans_umul(const struct instr_translater *t,
 	if (is_rel_or_const(b))
 		b = get_unconst(ctx, b);

-	if (t->tgsi_opc == TGSI_OPCODE_UMUL) {
-		/* mull.u tmp0, a, b */
-		instr = instr_create(ctx, 2, OPC_MULL_U);
-		vectorize(ctx, instr, &tmp0_dst, 2, a, 0, b, 0);
-	} else {
+	/* mull.u tmp0, a, b */
+	instr = instr_create(ctx, 2, OPC_MULL_U);
+	vectorize(ctx, instr, &tmp0_dst, 2, a, 0, b, 0);
+
+	if (t->tgsi_opc == TGSI_OPCODE_UMAD) {
 		struct tgsi_src_register *c = &inst->Src[2].Register;

-		/* mad.u16 tmp0, a, b, c */
-		instr = instr_create(ctx, 3, OPC_MAD_U16);
-		vectorize(ctx, instr, &tmp0_dst, 3, a, 0, b, 0, c, 0);
+		/* add.u tmp0, tmp0, c */
+		instr = instr_create(ctx, 2, OPC_ADD_U);
+		vectorize(ctx, instr, &tmp0_dst, 2, tmp0_src, 0, c, 0);
 	}

 	/* madsh.m16 tmp1, a, b, tmp0 */
@@ -2374,6 +2374,9 @@ trans_idiv(const struct instr_translater *t,
 	if (t->tgsi_opc == TGSI_OPCODE_MOD || t->tgsi_opc == TGSI_OPCODE_UMOD) {
 		/* The division result will have ended up in q. */

+		if (is_rel_or_const(b))
+			b = get_unconst(ctx, b);
+
 		/* mull.u r, q, b */
 		instr = instr_create(ctx, 2, OPC_MULL_U);
 		vectorize(ctx, instr, &r_dst, 2, q_src, 0, b, 0);
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -236,6 +236,9 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
   case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
      return 0;

+   case PIPE_CAP_MAX_VIEWPORTS:
+      return 1;
+
   case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
      return 64;

--- a/src/gallium/drivers/llvmpipe/lp_rast.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast.c
@@ -800,6 +800,10 @@ static PIPE_THREAD_ROUTINE( thread_function, init_data )
      pipe_semaphore_signal(&task->work_done);
   }

+#ifdef _WIN32
+   pipe_semaphore_signal(&task->work_done);
+#endif
+
   return 0;
 }

@@ -885,9 +889,15 @@ void lp_rast_destroy( struct lp_rasterizer *rast )
      pipe_semaphore_signal(&rast->tasks[i].work_ready);
   }

-   /* Wait for threads to terminate before cleaning up per-thread data */
+   /* Wait for threads to terminate before cleaning up per-thread data.
+    * We don't actually call pipe_thread_wait to avoid dead lock on Windows
+    * per https://bugs.freedesktop.org/show_bug.cgi?id=76252 */
   for (i = 0; i < rast->num_threads; i++) {
+#ifdef _WIN32
+      pipe_semaphore_wait(&rast->tasks[i].work_done);
+#else
      pipe_thread_wait(rast->threads[i]);
+#endif
   }

   /* Clean up per-thread data */
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -924,7 +924,9 @@ CodeEmitterNV50::emitMINMAX(const Instruction *i)
         break;
      }
      code[1] |= i->src(0).mod.abs() << 20;
+      code[1] |= i->src(0).mod.neg() << 26;
      code[1] |= i->src(1).mod.abs() << 19;
+      code[1] |= i->src(1).mod.neg() << 27;
   }
   emitForm_MAD(i);
 }
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -772,7 +772,8 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
   if (i->tex.useOffsets) {
      for (int c = 0; c < 3; ++c) {
         ImmediateValue val;
-         assert(i->offset[0][c].getImmediate(val));
+         if (!i->offset[0][c].getImmediate(val))
+            assert(!"non-immediate offset");
         i->tex.offset[c] = val.reg.data.u32;
         i->offset[0][c].set(NULL);
      }
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -760,7 +760,8 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
         assert(i->tex.useOffsets == 1);
         for (c = 0; c < 3; ++c) {
            ImmediateValue val;
-            assert(i->offset[0][c].getImmediate(val));
+            if (!i->offset[0][c].getImmediate(val))
+               assert(!"non-immediate offset passed to non-TXG");
            imm |= (val.reg.data.u32 & 0xf) << (c * 4);
         }
         if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -188,7 +188,12 @@ nv50_invalidate_resource_storage(struct nouveau_context *ctx,
      }
   }

-   if (res->bind & PIPE_BIND_VERTEX_BUFFER) {
+   if (res->bind & (PIPE_BIND_VERTEX_BUFFER |
+                    PIPE_BIND_INDEX_BUFFER |
+                    PIPE_BIND_CONSTANT_BUFFER |
+                    PIPE_BIND_STREAM_OUTPUT |
+                    PIPE_BIND_SAMPLER_VIEW)) {
+
      assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
      for (i = 0; i < nv50->num_vtxbufs; ++i) {
         if (nv50->vtxbuf[i].buffer == res) {
@@ -198,14 +203,11 @@ nv50_invalidate_resource_storage(struct nouveau_context *ctx,
               return ref;
         }
      }
-   }
-   if (res->bind & PIPE_BIND_INDEX_BUFFER) {
+
      if (nv50->idxbuf.buffer == res)
         if (!--ref)
            return ref;
-   }

-   if (res->bind & PIPE_BIND_SAMPLER_VIEW) {
      for (s = 0; s < 3; ++s) {
      assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
      for (i = 0; i < nv50->num_textures[s]; ++i) {
@@ -218,12 +220,11 @@ nv50_invalidate_resource_storage(struct nouveau_context *ctx,
         }
      }
      }
-   }

-   if (res->bind & PIPE_BIND_CONSTANT_BUFFER) {
      for (s = 0; s < 3; ++s) {
-      assert(nv50->num_vtxbufs <= NV50_MAX_PIPE_CONSTBUFS);
-      for (i = 0; i < nv50->num_vtxbufs; ++i) {
+      for (i = 0; i < NV50_MAX_PIPE_CONSTBUFS; ++i) {
+         if (!(nv50->constbuf_valid[s] & (1 << i)))
+            continue;
         if (!nv50->constbuf[s][i].user &&
             nv50->constbuf[s][i].u.buf == res) {
            nv50->dirty |= NV50_NEW_CONSTBUF;
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -603,6 +603,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
   BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
   PUSH_DATA (push, 1);

+   BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
+   PUSH_DATA (push, 0);
+   if (screen->base.class_3d >= NV84_3D_CLASS) {
+      BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+      PUSH_DATA (push, 0);
+   }
+
   PUSH_KICK (push);
 }

--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -472,6 +472,10 @@ nv50_draw_arrays(struct nv50_context *nv50,
   if (nv50->state.index_bias) {
      BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
      PUSH_DATA (push, 0);
+      if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
+         BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+         PUSH_DATA (push, 0);
+      }
      nv50->state.index_bias = 0;
   }

@@ -594,6 +598,10 @@ nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
   if (index_bias != nv50->state.index_bias) {
      BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
      PUSH_DATA (push, index_bias);
+      if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
+         BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+         PUSH_DATA (push, index_bias);
+      }
      nv50->state.index_bias = index_bias;
   }

--- a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
+++ b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
@@ -227,6 +227,7 @@ locn_0f_ts:
 /* NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT
 *
 * NOTE: Saves and restores VB_ELEMENT,INSTANCE_BASE.
+ * Forcefully sets VERTEX_ID_BASE to the value of VB_ELEMENT_BASE.
 *
 * arg     = mode
 * parm[0] = count
@@ -247,6 +248,8 @@ locn_0f_ts:
   maddr 0x150d /* VB_ELEMENT,INSTANCE_BASE */
   send $r4
   send $r5
+   maddr 0x446
+   send $r4
   mov $r4 0x1
 dei_again:
   maddr 0x586 /* VERTEX_BEGIN_GL */
@@ -258,8 +261,10 @@ dei_again:
   branz $r2 #dei_again
   mov $r1 (extrinsrt $r1 $r4 0 1 26) /* set INSTANCE_NEXT */
   maddr 0x150d /* VB_ELEMENT,INSTANCE_BASE */
-   exit send $r6
+   send $r6
   send $r7
+   exit maddr 0x446
+   send $r6
 dei_end:
   exit
   nop
--- a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
+++ b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
@@ -128,16 +128,18 @@ uint32_t mme9097_draw_elts_indirect[] = {
 	0x00000301,
 	0x00000201,
 	0x017dc451,
-/* 0x000c: dei_again */
+/* 0x000e: dei_again */
 	0x00002431,
-	0x0004d007,
-/* 0x0017: dei_end */
+	0x0005d007,
 	0x00000501,
+/* 0x001b: dei_end */
 	0x01434615,
 	0x01438715,
 	0x05434021,
 	0x00002041,
 	0x00002841,
+	0x01118021,
+	0x00002041,
 	0x00004411,
 	0x01618021,
 	0x00000841,
@@ -148,8 +150,10 @@ uint32_t mme9097_draw_elts_indirect[] = {
 	0xfffe9017,
 	0xd0410912,
 	0x05434021,
-	0x000030c1,
+	0x00003041,
 	0x00003841,
+	0x011180a1,
+	0x00003041,
 	0x00000091,
 	0x00000011,
 };
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -204,7 +204,12 @@ nvc0_invalidate_resource_storage(struct nouveau_context *ctx,
      }
   }

-   if (res->bind & PIPE_BIND_VERTEX_BUFFER) {
+   if (res->bind & (PIPE_BIND_VERTEX_BUFFER |
+                    PIPE_BIND_INDEX_BUFFER |
+                    PIPE_BIND_CONSTANT_BUFFER |
+                    PIPE_BIND_STREAM_OUTPUT |
+                    PIPE_BIND_COMMAND_ARGS_BUFFER |
+                    PIPE_BIND_SAMPLER_VIEW)) {
      for (i = 0; i < nvc0->num_vtxbufs; ++i) {
         if (nvc0->vtxbuf[i].buffer == res) {
            nvc0->dirty |= NVC0_NEW_ARRAYS;
@@ -213,17 +218,14 @@ nvc0_invalidate_resource_storage(struct nouveau_context *ctx,
               return ref;
         }
      }
-   }
-   if (res->bind & PIPE_BIND_INDEX_BUFFER) {
+
      if (nvc0->idxbuf.buffer == res) {
         nvc0->dirty |= NVC0_NEW_IDXBUF;
         nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
         if (!--ref)
            return ref;
      }
-   }

-   if (res->bind & PIPE_BIND_SAMPLER_VIEW) {
      for (s = 0; s < 5; ++s) {
      for (i = 0; i < nvc0->num_textures[s]; ++i) {
         if (nvc0->textures[s][i] &&
@@ -236,11 +238,11 @@ nvc0_invalidate_resource_storage(struct nouveau_context *ctx,
         }
      }
      }
-   }

-   if (res->bind & PIPE_BIND_CONSTANT_BUFFER) {
      for (s = 0; s < 5; ++s) {
-      for (i = 0; i < nvc0->num_vtxbufs; ++i) {
+      for (i = 0; i < NVC0_MAX_PIPE_CONSTBUFS; ++i) {
+         if (!(nvc0->constbuf_valid[s] & (1 << i)))
+            continue;
         if (!nvc0->constbuf[s][i].user &&
             nvc0->constbuf[s][i].u.buf == res) {
            nvc0->dirty |= NVC0_NEW_CONSTBUF;
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -575,8 +575,9 @@ nvc0_draw_arrays(struct nvc0_context *nvc0,
   if (nvc0->state.index_bias) {
      /* index_bias is implied 0 if !info->indexed (really ?) */
      /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
-      PUSH_SPACE(push, 1);
+      PUSH_SPACE(push, 2);
      IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
+      IMMED_NVC0(push, NVC0_3D(VERTEX_ID), 0);
      nvc0->state.index_bias = 0;
   }

@@ -705,9 +706,11 @@ nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
   prim = nvc0_prim_gl(mode);

   if (index_bias != nvc0->state.index_bias) {
-      PUSH_SPACE(push, 2);
+      PUSH_SPACE(push, 4);
      BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
      PUSH_DATA (push, index_bias);
+      BEGIN_NVC0(push, NVC0_3D(VERTEX_ID), 1);
+      PUSH_DATA (push, index_bias);
      nvc0->state.index_bias = index_bias;
   }

@@ -818,6 +821,7 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
      if (nvc0->state.index_bias) {
         /* index_bias is implied 0 if !info->indexed (really ?) */
         IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
+         IMMED_NVC0(push, NVC0_3D(VERTEX_ID), 0);
         nvc0->state.index_bias = 0;
      }
      size = 4 * 4;
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2493,8 +2493,10 @@ static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	int i, j, k, r;
 	struct r600_bytecode_alu alu;
-	int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
-	for (k = 0; k < last_slot; k++) {
+	int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+	int t1 = ctx->temp_reg;
+
+	for (k = 0; k <= lasti; k++) {
 		if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
 			continue;

@@ -2504,7 +2506,8 @@ static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 				r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
 			}
-			tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+			alu.dst.sel = t1;
+			alu.dst.chan = i;
 			alu.dst.write = (i == k);
 			if (i == 3)
 				alu.last = 1;
@@ -2513,6 +2516,23 @@ static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
 				return r;
 		}
 	}
+
+	for (i = 0 ; i <= lasti; i++) {
+		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+			continue;
+		memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+		alu.op = ALU_OP1_MOV;
+		alu.src[0].sel = t1;
+		alu.src[0].chan = i;
+		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		alu.dst.write = 1;
+		if (i == lasti)
+			alu.last = 1;
+		r = r600_bytecode_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+
 	return 0;
 }

@@ -4499,7 +4519,8 @@ static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
 	return 	(inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
 		inst->Src[index].Register.File != TGSI_FILE_INPUT &&
 		inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
-		ctx->src[index].neg || ctx->src[index].abs;
+		ctx->src[index].neg || ctx->src[index].abs ||
+		(inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
 }

 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
@@ -5105,9 +5126,24 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 				/* texture offsets do not apply to other texture targets */
 			}
 		} else {
-			offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
-			offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
-			offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
+			switch (inst->Texture.Texture) {
+			case TGSI_TEXTURE_3D:
+				offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
+				/* fallthrough */
+			case TGSI_TEXTURE_2D:
+			case TGSI_TEXTURE_SHADOW2D:
+			case TGSI_TEXTURE_RECT:
+			case TGSI_TEXTURE_SHADOWRECT:
+			case TGSI_TEXTURE_2D_ARRAY:
+			case TGSI_TEXTURE_SHADOW2D_ARRAY:
+				offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
+				/* fallthrough */
+			case TGSI_TEXTURE_1D:
+			case TGSI_TEXTURE_SHADOW1D:
+			case TGSI_TEXTURE_1D_ARRAY:
+			case TGSI_TEXTURE_SHADOW1D_ARRAY:
+				offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
+			}
 		}
 	}

@@ -5328,11 +5364,18 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
 		tex.inst_mod = texture_component_select;

+		if (ctx->bc->chip_class == CAYMAN) {
 		/* GATHER4 result order is different from TGSI TG4 */
-		tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
-		tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
-		tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
-		tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
+			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
+			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
+			tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+		} else {
+			tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+			tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
+			tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+			tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+		}
 	}
 	else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
 		tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2615,11 +2615,8 @@ void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
 	r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
 			       r600_conv_prim_to_gs_out(rshader->gs_output_prim));

-	r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
-	r600_store_value(cb, cp_shader->ring_item_size >> 2);
-	r600_store_value(cb, 0);
-	r600_store_value(cb, 0);
-	r600_store_value(cb, 0);
+	r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
+	                       cp_shader->ring_item_size >> 2);

 	r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
 			       (rshader->ring_item_size) >> 2);
--- a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
@@ -83,14 +83,18 @@ int bc_finalizer::run() {
 		last_cf = c;
 	}

-	if (last_cf->bc.op_ptr->flags & CF_ALU) {
+	if (!ctx.is_cayman() && last_cf->bc.op_ptr->flags & CF_ALU) {
 		last_cf = sh.create_cf(CF_OP_NOP);
 		sh.root->push_back(last_cf);
 	}

-	if (ctx.is_cayman())
-		last_cf->insert_after(sh.create_cf(CF_OP_CF_END));
-	else
+	if (ctx.is_cayman()) {
+		if (!last_cf) {
+			cf_node *c = sh.create_cf(CF_OP_CF_END);
+			sh.root->push_back(c);
+		} else
+			last_cf->insert_after(sh.create_cf(CF_OP_CF_END));
+	} else
 		last_cf->bc.end_of_program = 1;

 	for (unsigned t = EXP_PIXEL; t < EXP_TYPE_COUNT; ++t) {
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -270,6 +270,21 @@ void si_dma_copy(struct pipe_context *ctx,
 		return;
 	}

+	/* XXX: Using the asynchronous DMA engine for multi-dimensional
+	 * operations seems to cause random GPU lockups for various people.
+	 * While the root cause for this might need to be fixed in the kernel,
+	 * let's disable it for now.
+	 *
+	 * Before re-enabling this, please make sure you can hit all newly
+	 * enabled paths in your testing, preferably with both piglit and real
+	 * world apps, and get in touch with people on the bug reports below
+	 * for stability testing.
+	 *
+	 * https://bugs.freedesktop.org/show_bug.cgi?id=85647
+	 * https://bugs.freedesktop.org/show_bug.cgi?id=83500
+	 */
+	goto fallback;
+
 	if (src->format != dst->format || src_box->depth > 1 ||
 	    rdst->dirty_level_mask != 0) {
 		goto fallback;
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3007,6 +3007,110 @@ void si_init_state_functions(struct si_context *sctx)
 	sctx->b.b.draw_vbo = si_draw_vbo;
 }

+static void
+si_write_harvested_raster_configs(struct si_context *sctx,
+				  struct si_pm4_state *pm4,
+				  unsigned raster_config)
+{
+	unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
+	unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
+	unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
+	unsigned num_rb = sctx->screen->b.info.r600_num_backends;
+	unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
+	unsigned rb_per_se = num_rb / num_se;
+	unsigned se0_mask = (1 << rb_per_se) - 1;
+	unsigned se1_mask = se0_mask << rb_per_se;
+	unsigned se;
+
+	assert(num_se == 1 || num_se == 2);
+	assert(sh_per_se == 1 || sh_per_se == 2);
+	assert(rb_per_pkr == 1 || rb_per_pkr == 2);
+
+	/* XXX: I can't figure out what the *_XSEL and *_YSEL
+	 * fields are for, so I'm leaving them as their default
+	 * values. */
+
+	se0_mask &= rb_mask;
+	se1_mask &= rb_mask;
+	if (num_se == 2 && (!se0_mask || !se1_mask)) {
+		raster_config &= C_028350_SE_MAP;
+
+		if (!se0_mask) {
+			raster_config |=
+				S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
+		} else {
+			raster_config |=
+				S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
+		}
+	}
+
+	for (se = 0; se < num_se; se++) {
+		unsigned raster_config_se = raster_config;
+		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
+		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+
+		pkr0_mask &= rb_mask;
+		pkr1_mask &= rb_mask;
+		if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
+			raster_config_se &= C_028350_PKR_MAP;
+
+			if (!pkr0_mask) {
+				raster_config_se |=
+					S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
+			} else {
+				raster_config_se |=
+					S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
+			}
+		}
+
+		if (rb_per_pkr == 2) {
+			unsigned rb0_mask = 1 << (se * rb_per_se);
+			unsigned rb1_mask = rb0_mask << 1;
+
+			rb0_mask &= rb_mask;
+			rb1_mask &= rb_mask;
+			if (!rb0_mask || !rb1_mask) {
+				raster_config_se &= C_028350_RB_MAP_PKR0;
+
+				if (!rb0_mask) {
+					raster_config_se |=
+						S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
+				} else {
+					raster_config_se |=
+						S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
+				}
+			}
+
+			if (sh_per_se == 2) {
+				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
+				rb1_mask = rb0_mask << 1;
+				rb0_mask &= rb_mask;
+				rb1_mask &= rb_mask;
+				if (!rb0_mask || !rb1_mask) {
+					raster_config_se &= C_028350_RB_MAP_PKR1;
+
+					if (!rb0_mask) {
+						raster_config_se |=
+							S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
+					} else {
+						raster_config_se |=
+							S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
+					}
+				}
+			}
+		}
+
+		si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
+			       SE_INDEX(se) | SH_BROADCAST_WRITES |
+			       INSTANCE_BROADCAST_WRITES);
+		si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
+	}
+
+	si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
+		       SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
+		       INSTANCE_BROADCAST_WRITES);
+}
+
 void si_init_config(struct si_context *sctx)
 {
 	struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
@@ -3078,24 +3182,40 @@ void si_init_config(struct si_context *sctx)
 			break;
 		}
 	} else {
+		unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
+		unsigned num_rb = sctx->screen->b.info.r600_num_backends;
+		unsigned raster_config;
+
 		switch (sctx->screen->b.family) {
 		case CHIP_TAHITI:
 		case CHIP_PITCAIRN:
-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
+			raster_config = 0x2a00126a;
 			break;
 		case CHIP_VERDE:
-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
+			raster_config = 0x0000124a;
 			break;
 		case CHIP_OLAND:
-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
+			raster_config = 0x00000082;
 			break;
 		case CHIP_HAINAN:
-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+			raster_config = 0x00000000;
 			break;
 		default:
-			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+			fprintf(stderr,
+				"radeonsi: Unknown GPU, using 0 for raster_config\n");
+			raster_config = 0x00000000;
 			break;
 		}
+
+		/* Always use the default config when all backends are enabled
+		 * (or when we failed to determine the enabled backends).
+		 */
+		if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
+			si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
+				       raster_config);
+		} else {
+			si_write_harvested_raster_configs(sctx, pm4, raster_config);
+		}
 	}

 	si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -204,7 +204,13 @@
 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
 */

-
+#define GRBM_GFX_INDEX                                                  0x802C
+#define         INSTANCE_INDEX(x)                                     ((x) << 0)
+#define         SH_INDEX(x)                                           ((x) << 8)
+#define         SE_INDEX(x)                                           ((x) << 16)
+#define         SH_BROADCAST_WRITES                                   (1 << 29)
+#define         INSTANCE_BROADCAST_WRITES                             (1 << 30)
+#define         SE_BROADCAST_WRITES                                   (1 << 31)
 #define R_0084FC_CP_STRMOUT_CNTL		                        0x0084FC
 #define   S_0084FC_OFFSET_UPDATE_DONE(x)		              (((x) & 0x1) << 0)
 #define R_0085F0_CP_COHER_CNTL                                          0x0085F0
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -325,6 +325,9 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
                         &ws->info.max_sclk);
    ws->info.max_sclk /= 1000;

+    radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
+                         &ws->info.si_backend_enabled_mask);
+
    ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);

    /* Generation-specific queries. */
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -229,6 +229,7 @@ struct radeon_info {

    boolean                     si_tile_mode_array_valid;
    uint32_t                    si_tile_mode_array[32];
+    uint32_t                    si_backend_enabled_mask;

    boolean                     cik_macrotile_mode_array_valid;
    uint32_t                    cik_macrotile_mode_array[16];
--- a/src/glsl/builtin_variables.cpp
+++ b/src/glsl/builtin_variables.cpp
@@ -727,6 +727,10 @@ builtin_variable_generator::generate_constants()
      add_const("gl_MaxCombinedImageUniforms",
                state->Const.MaxCombinedImageUniforms);
   }
+
+   if (state->is_version(410, 0) ||
+       state->ARB_viewport_array_enable)
+      add_const("gl_MaxViewports", state->Const.MaxViewports);
 }


--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -134,6 +134,9 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context *_ctx,
   this->Const.MaxFragmentImageUniforms = ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxImageUniforms;
   this->Const.MaxCombinedImageUniforms = ctx->Const.MaxCombinedImageUniforms;

+   /* ARB_viewport_array */
+   this->Const.MaxViewports = ctx->Const.MaxViewports;
+
   this->current_function = NULL;
   this->toplevel_ir = NULL;
   this->found_return = false;
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -341,6 +341,9 @@ struct _mesa_glsl_parse_state {
      unsigned MaxGeometryImageUniforms;
      unsigned MaxFragmentImageUniforms;
      unsigned MaxCombinedImageUniforms;
+
+      /* ARB_viewport_array */
+      unsigned MaxViewports;
   } Const;

   /**
--- a/src/glsl/link_varyings.cpp
+++ b/src/glsl/link_varyings.cpp
@@ -830,9 +830,11 @@ varying_matches::record(ir_variable *producer_var, ir_variable *consumer_var)
       * regardless of where they appear.  We can trivially satisfy that
       * requirement by changing the interpolation type to flat here.
       */
-      producer_var->data.centroid = false;
-      producer_var->data.sample = false;
-      producer_var->data.interpolation = INTERP_QUALIFIER_FLAT;
+      if (producer_var) {
+         producer_var->data.centroid = false;
+         producer_var->data.sample = false;
+         producer_var->data.interpolation = INTERP_QUALIFIER_FLAT;
+      }

      if (consumer_var) {
         consumer_var->data.centroid = false;
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -2738,6 +2738,21 @@ link_shaders(struct gl_context *ctx, struct gl_shader_program *prog)
   if (last >= 0 && last < MESA_SHADER_FRAGMENT) {
      gl_shader *const sh = prog->_LinkedShaders[last];

+      if (first == MESA_SHADER_GEOMETRY) {
+         /* There was no vertex shader, but we still have to assign varying
+          * locations for use by geometry shader inputs in SSO.
+          *
+          * If the shader is not separable (i.e., prog->SeparateShader is
+          * false), linking will have already failed when first is
+          * MESA_SHADER_GEOMETRY.
+          */
+         if (!assign_varying_locations(ctx, mem_ctx, prog,
+                                       NULL, sh,
+                                       num_tfeedback_decls, tfeedback_decls,
+                                       prog->Geom.VerticesIn))
+            goto done;
+      }
+
      if (num_tfeedback_decls != 0 || prog->SeparateShader) {
         /* There was no fragment shader, but we still have to assign varying
          * locations for use by transform feedback.
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -392,11 +392,14 @@ dri3_handle_present_event(struct dri3_drawable *priv, xcb_present_generic_event_
            break;
         }
         dri3_update_num_back(priv);
+
+         priv->ust = ce->ust;
+         priv->msc = ce->msc;
      } else {
         priv->recv_msc_serial = ce->serial;
+         priv->notify_ust = ce->ust;
+         priv->notify_msc = ce->msc;
      }
-      priv->ust = ce->ust;
-      priv->msc = ce->msc;
      break;
   }
   case XCB_PRESENT_EVENT_IDLE_NOTIFY: {
@@ -470,8 +473,8 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t target_msc, int64_t divisor,
      }
   }

-   *ust = priv->ust;
-   *msc = priv->msc;
+   *ust = priv->notify_ust;
+   *msc = priv->notify_msc;
   *sbc = priv->recv_sbc;

   return 1;
@@ -501,6 +504,15 @@ dri3_wait_for_sbc(__GLXDRIdrawable *pdraw, int64_t target_sbc, int64_t *ust,
 {
   struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;

+   /* From the GLX_OML_sync_control spec:
+    *
+    *     "If <target_sbc> = 0, the function will block until all previous
+    *      swaps requested with glXSwapBuffersMscOML for that window have
+    *      completed."
+    */
+   if (!target_sbc)
+      target_sbc = priv->send_sbc;
+
   while (priv->recv_sbc < target_sbc) {
      if (!dri3_wait_for_event(pdraw))
         return 0;
@@ -1504,11 +1516,24 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t target_msc, int64_t divisor,
      dri3_fence_reset(c, back);

      /* Compute when we want the frame shown by taking the last known successful
-       * MSC and adding in a swap interval for each outstanding swap request
+       * MSC and adding in a swap interval for each outstanding swap request.
+       * target_msc=divisor=remainder=0 means "Use glXSwapBuffers() semantic"
       */
      ++priv->send_sbc;
-      if (target_msc == 0)
+      if (target_msc == 0 && divisor == 0 && remainder == 0)
         target_msc = priv->msc + priv->swap_interval * (priv->send_sbc - priv->recv_sbc);
+      else if (divisor == 0 && remainder > 0) {
+         /* From the GLX_OML_sync_control spec:
+          *
+          *     "If <divisor> = 0, the swap will occur when MSC becomes
+          *      greater than or equal to <target_msc>."
+          *
+          * Note that there's no mention of the remainder.  The Present extension
+          * throws BadValue for remainder != 0 with divisor == 0, so just drop
+          * the passed in value.
+          */
+         remainder = 0;
+      }

      back->busy = 1;
      back->last_swap = priv->send_sbc;
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -178,9 +178,12 @@ struct dri3_drawable {
   uint64_t send_sbc;
   uint64_t recv_sbc;

-   /* Last received UST/MSC values */
+   /* Last received UST/MSC values for pixmap present complete */
   uint64_t ust, msc;

+   /* Last received UST/MSC values from present notify msc event */
+   uint64_t notify_ust, notify_msc;
+
   /* Serial numbers for tracking wait_for_msc events */
   uint32_t send_msc_serial;
   uint32_t recv_msc_serial;
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1063,11 +1063,8 @@ struct brw_context
   bool no_depth_or_stencil;

   struct {
-      /** Does the current draw use the index buffer? */
-      bool indexed;
-
-      int start_vertex_location;
-      int base_vertex_location;
+      /** The value of gl_BaseVertex for the current _mesa_prim. */
+      int gl_basevertex;

      /**
       * Buffer and offset used for GL_ARB_shader_draw_parameters
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -181,14 +181,20 @@ static void brw_emit_prim(struct brw_context *brw,
   DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
       prim->start, prim->count);

+   int start_vertex_location = prim->start;
+   int base_vertex_location = prim->basevertex;
+
   if (prim->indexed) {
      vertex_access_type = brw->gen >= 7 ?
         GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
         GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
+      start_vertex_location += brw->ib.start_vertex_offset;
+      base_vertex_location += brw->vb.start_vertex_bias;
   } else {
      vertex_access_type = brw->gen >= 7 ?
         GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL :
         GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
+      start_vertex_location += brw->vb.start_vertex_bias;
   }

   /* We only need to trim the primitive count on pre-Gen6. */
@@ -263,10 +269,10 @@ static void brw_emit_prim(struct brw_context *brw,
                vertex_access_type);
   }
   OUT_BATCH(verts_per_instance);
-   OUT_BATCH(brw->draw.start_vertex_location);
+   OUT_BATCH(start_vertex_location);
   OUT_BATCH(prim->num_instances);
   OUT_BATCH(prim->base_instance);
-   OUT_BATCH(brw->draw.base_vertex_location);
+   OUT_BATCH(base_vertex_location);
   ADVANCE_BATCH();

   /* Only used on Sandybridge; harmless to set elsewhere. */
@@ -430,9 +436,8 @@ static bool brw_try_draw_prims( struct gl_context *ctx,
         }
      }

-      brw->draw.indexed = prims[i].indexed;
-      brw->draw.start_vertex_location = prims[i].start;
-      brw->draw.base_vertex_location = prims[i].basevertex;
+      brw->draw.gl_basevertex =
+         prims[i].indexed ? prims[i].basevertex : prims[i].start;

      drm_intel_bo_unreference(brw->draw.draw_params_bo);

--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -607,19 +607,9 @@ brw_prepare_vertices(struct brw_context *brw)
 void
 brw_prepare_shader_draw_parameters(struct brw_context *brw)
 {
-   int *gl_basevertex_value;
-   if (brw->draw.indexed) {
-      brw->draw.start_vertex_location += brw->ib.start_vertex_offset;
-      brw->draw.base_vertex_location += brw->vb.start_vertex_bias;
-      gl_basevertex_value = &brw->draw.base_vertex_location;
-   } else {
-      brw->draw.start_vertex_location += brw->vb.start_vertex_bias;
-      gl_basevertex_value = &brw->draw.start_vertex_location;
-   }
-
   /* For non-indirect draws, upload gl_BaseVertex. */
   if (brw->vs.prog_data->uses_vertexid && brw->draw.draw_params_bo == NULL) {
-      intel_upload_data(brw, gl_basevertex_value, 4, 4,
+      intel_upload_data(brw, &brw->draw.gl_basevertex, 4, 4,
 			&brw->draw.draw_params_bo,
                        &brw->draw.draw_params_offset);
   }
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -706,12 +706,14 @@ fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src
   }

   struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
+                                 src.negate, src.abs,
 				 BRW_REGISTER_TYPE_F,
 				 vstride,
 				 width,
 				 BRW_HORIZONTAL_STRIDE_0,
 				 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
   struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
+                                 src.negate, src.abs,
 				 BRW_REGISTER_TYPE_F,
 				 vstride,
 				 width,
@@ -761,12 +763,14 @@ fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src

      /* produce accurate derivatives */
      struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
+                                    src.negate, src.abs,
                                    BRW_REGISTER_TYPE_F,
                                    BRW_VERTICAL_STRIDE_4,
                                    BRW_WIDTH_4,
                                    BRW_HORIZONTAL_STRIDE_1,
                                    BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
      struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
+                                    src.negate, src.abs,
                                    BRW_REGISTER_TYPE_F,
                                    BRW_VERTICAL_STRIDE_4,
                                    BRW_WIDTH_4,
@@ -794,12 +798,14 @@ fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src
   } else {
      /* replicate the derivative at the top-left pixel to other pixels */
      struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
+                                    src.negate, src.abs,
                                    BRW_REGISTER_TYPE_F,
                                    BRW_VERTICAL_STRIDE_4,
                                    BRW_WIDTH_4,
                                    BRW_HORIZONTAL_STRIDE_0,
                                    BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
      struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
+                                    src.negate, src.abs,
                                    BRW_REGISTER_TYPE_F,
                                    BRW_VERTICAL_STRIDE_4,
                                    BRW_WIDTH_4,
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -907,7 +907,7 @@ gather_oa_results(struct brw_context *brw,
      return;
   }

-   const int snapshot_size = brw->perfmon.entries_per_oa_snapshot;
+   const ptrdiff_t snapshot_size = brw->perfmon.entries_per_oa_snapshot;

   /* First, add the contributions from the "head" interval:
    * (snapshot taken at BeginPerfMonitor time,
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -218,6 +218,8 @@ type_is_signed(unsigned type)
 * \param file      one of the BRW_x_REGISTER_FILE values
 * \param nr        register number/index
 * \param subnr     register sub number
+ * \param negate    register negate modifier
+ * \param abs       register abs modifier
 * \param type      one of BRW_REGISTER_TYPE_x
 * \param vstride   one of BRW_VERTICAL_STRIDE_x
 * \param width     one of BRW_WIDTH_x
@@ -229,6 +231,8 @@ static inline struct brw_reg
 brw_reg(unsigned file,
        unsigned nr,
        unsigned subnr,
+        unsigned negate,
+        unsigned abs,
        enum brw_reg_type type,
        unsigned vstride,
        unsigned width,
@@ -248,8 +252,8 @@ brw_reg(unsigned file,
   reg.file = file;
   reg.nr = nr;
   reg.subnr = subnr * type_sz(type);
-   reg.negate = 0;
-   reg.abs = 0;
+   reg.negate = negate;
+   reg.abs = abs;
   reg.vstride = vstride;
   reg.width = width;
   reg.hstride = hstride;
@@ -276,6 +280,8 @@ brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr)
   return brw_reg(file,
                  nr,
                  subnr,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_F,
                  BRW_VERTICAL_STRIDE_16,
                  BRW_WIDTH_16,
@@ -291,6 +297,8 @@ brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr)
   return brw_reg(file,
                  nr,
                  subnr,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_F,
                  BRW_VERTICAL_STRIDE_8,
                  BRW_WIDTH_8,
@@ -306,6 +314,8 @@ brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr)
   return brw_reg(file,
                  nr,
                  subnr,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_F,
                  BRW_VERTICAL_STRIDE_4,
                  BRW_WIDTH_4,
@@ -321,6 +331,8 @@ brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr)
   return brw_reg(file,
                  nr,
                  subnr,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_F,
                  BRW_VERTICAL_STRIDE_2,
                  BRW_WIDTH_2,
@@ -336,6 +348,8 @@ brw_vec1_reg(unsigned file, unsigned nr, unsigned subnr)
   return brw_reg(file,
                  nr,
                  subnr,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_F,
                  BRW_VERTICAL_STRIDE_0,
                  BRW_WIDTH_1,
@@ -429,6 +443,8 @@ static inline struct brw_reg
 brw_imm_reg(enum brw_reg_type type)
 {
   return brw_reg(BRW_IMMEDIATE_VALUE,
+                  0,
+                  0,
                  0,
                  0,
                  type,
@@ -618,6 +634,8 @@ brw_ip_reg(void)
   return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
                  BRW_ARF_IP,
                  0,
+                  0,
+                  0,
                  BRW_REGISTER_TYPE_UD,
                  BRW_VERTICAL_STRIDE_4, /* ? */
                  BRW_WIDTH_1,
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1651,6 +1651,8 @@ vec4_visitor::get_timestamp()
   src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
                                BRW_ARF_TIMESTAMP,
                                0,
+                                0,
+                                0,
                                BRW_REGISTER_TYPE_UD,
                                BRW_VERTICAL_STRIDE_0,
                                BRW_WIDTH_4,
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -502,13 +502,17 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
    *
    * We can do this with the following EU instruction:
    *
-    *     mul(2) dst.3<1>UD src0<8;2,4>UD src1   { Align1 WE_all }
+    *     mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW   { Align1 WE_all }
    */
   brw_push_insn_state(p);
   brw_set_default_access_mode(p, BRW_ALIGN_1);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+   assert(brw->gen >= 7 &&
+          src1.file == BRW_IMMEDIATE_VALUE &&
+          src1.type == BRW_REGISTER_TYPE_UD &&
+          src1.dw1.ud <= USHRT_MAX);
   brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
-           src1);
+           retype(src1, BRW_REGISTER_TYPE_UW));
   brw_set_default_access_mode(p, BRW_ALIGN_16);
   brw_pop_insn_state(p);
 }
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3427,10 +3427,8 @@ void
 vec4_visitor::move_uniform_array_access_to_pull_constants()
 {
   int pull_constant_loc[this->uniforms];
-
-   for (int i = 0; i < this->uniforms; i++) {
-      pull_constant_loc[i] = -1;
-   }
+   memset(pull_constant_loc, -1, sizeof(pull_constant_loc));
+   bool nested_reladdr;

   /* Walk through and find array access of uniforms.  Put a copy of that
    * uniform in the pull constant buffer.
@@ -3438,44 +3436,51 @@ vec4_visitor::move_uniform_array_access_to_pull_constants()
    * Note that we don't move constant-indexed accesses to arrays.  No
    * testing has been done of the performance impact of this choice.
    */
-   foreach_in_list_safe(vec4_instruction, inst, &instructions) {
-      for (int i = 0 ; i < 3; i++) {
-	 if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
-	    continue;
+   do {
+      nested_reladdr = false;

-	 int uniform = inst->src[i].reg;
+      foreach_in_list_safe(vec4_instruction, inst, &instructions) {
+         for (int i = 0 ; i < 3; i++) {
+            if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
+               continue;

-	 /* If this array isn't already present in the pull constant buffer,
-	  * add it.
-	  */
-	 if (pull_constant_loc[uniform] == -1) {
-	    const gl_constant_value **values =
-               &stage_prog_data->param[uniform * 4];
+            int uniform = inst->src[i].reg;

-	    pull_constant_loc[uniform] = stage_prog_data->nr_pull_params / 4;
+            if (inst->src[i].reladdr->reladdr)
+               nested_reladdr = true;  /* will need another pass */

-	    assert(uniform < uniform_array_size);
-	    for (int j = 0; j < uniform_size[uniform] * 4; j++) {
-	       stage_prog_data->pull_param[stage_prog_data->nr_pull_params++]
-                  = values[j];
-	    }
-	 }
+            /* If this array isn't already present in the pull constant buffer,
+             * add it.
+             */
+            if (pull_constant_loc[uniform] == -1) {
+               const gl_constant_value **values =
+                  &stage_prog_data->param[uniform * 4];

-	 /* Set up the annotation tracking for new generated instructions. */
-	 base_ir = inst->ir;
-	 current_annotation = inst->annotation;
+               pull_constant_loc[uniform] = stage_prog_data->nr_pull_params / 4;

-	 dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+               assert(uniform < uniform_array_size);
+               for (int j = 0; j < uniform_size[uniform] * 4; j++) {
+                  stage_prog_data->pull_param[stage_prog_data->nr_pull_params++]
+                     = values[j];
+               }
+            }

-	 emit_pull_constant_load(inst, temp, inst->src[i],
-				 pull_constant_loc[uniform]);
+            /* Set up the annotation tracking for new generated instructions. */
+            base_ir = inst->ir;
+            current_annotation = inst->annotation;

-	 inst->src[i].file = temp.file;
-	 inst->src[i].reg = temp.reg;
-	 inst->src[i].reg_offset = temp.reg_offset;
-	 inst->src[i].reladdr = NULL;
+            dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+
+            emit_pull_constant_load(inst, temp, inst->src[i],
+                                    pull_constant_loc[uniform]);
+
+            inst->src[i].file = temp.file;
+            inst->src[i].reg = temp.reg;
+            inst->src[i].reg_offset = temp.reg_offset;
+            inst->src[i].reladdr = NULL;
+         }
      }
-   }
+   } while (nested_reladdr);

   /* Now there are no accesses of the UNIFORM file with a reladdr, so
    * no need to track them as larger-than-vec4 objects.  This will be
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -535,6 +535,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
   drm_intel_bo *bo = NULL;
   unsigned pitch_minus_1 = 0;
   uint32_t multisampling_state = 0;
+   /* CACHE_NEW_WM_PROG */
   uint32_t surf_index =
      brw->wm.prog_data->binding_table.render_target_start + unit;

@@ -620,6 +621,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
   uint32_t format = 0;
   /* _NEW_BUFFERS */
   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+   /* CACHE_NEW_WM_PROG */
   uint32_t surf_index =
      brw->wm.prog_data->binding_table.render_target_start + unit;

@@ -737,7 +739,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = {
      .mesa = (_NEW_COLOR |
               _NEW_BUFFERS),
      .brw = BRW_NEW_BATCH,
-      .cache = 0
+      .cache = CACHE_NEW_WM_PROG,
   },
   .emit = brw_update_renderbuffer_surfaces,
 };
@@ -764,6 +766,8 @@ update_stage_texture_surfaces(struct brw_context *brw,
   struct gl_context *ctx = &brw->ctx;

   uint32_t *surf_offset = stage_state->surf_offset;
+
+   /* CACHE_NEW_*_PROG */
   if (for_gather)
      surf_offset += stage_state->prog_data->binding_table.gather_texture_start;
   else
@@ -828,7 +832,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
             BRW_NEW_VERTEX_PROGRAM |
             BRW_NEW_GEOMETRY_PROGRAM |
             BRW_NEW_FRAGMENT_PROGRAM,
-      .cache = 0
+      .cache = CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG | CACHE_NEW_WM_PROG,
   },
   .emit = brw_update_texture_surfaces,
 };
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1746,8 +1746,8 @@ intel_miptree_map_gtt(struct brw_context *brw,
   unsigned int bw, bh;
   void *base;
   unsigned int image_x, image_y;
-   int x = map->x;
-   int y = map->y;
+   intptr_t x = map->x;
+   intptr_t y = map->y;

   /* For compressed formats, the stride is the number of bytes per
    * row of blocks.  intel_miptree_get_image_offset() already does
@@ -1773,7 +1773,8 @@ intel_miptree_map_gtt(struct brw_context *brw,
      map->ptr = base + y * map->stride + x * mt->cpp;
   }

-   DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__,
+   DBG("%s: %d,%d %dx%d from mt %p (%s) "
+       "%"PRIiPTR",%"PRIiPTR" = %p/%d\n", __FUNCTION__,
       map->x, map->y, map->w, map->h,
       mt, _mesa_get_format_name(mt->format),
       x, y, map->ptr, map->stride);
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -494,8 +494,8 @@ linear_to_tiled(uint32_t xt1, uint32_t xt2,
         /* Translate by (xt,yt) for single-tile copier. */
         tile_copy(x0-xt, x1-xt, x2-xt, x3-xt,
                   y0-yt, y1-yt,
-                   dst + xt * th + yt * dst_pitch,
-                   src + xt      + yt * src_pitch,
+                   dst + (ptrdiff_t) xt * th + (ptrdiff_t) yt * dst_pitch,
+                   src + (ptrdiff_t) xt      + (ptrdiff_t) yt * src_pitch,
                   src_pitch,
                   swizzle_bit,
                   mem_copy);
@@ -660,7 +660,8 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
   linear_to_tiled(
      xoffset * cpp, (xoffset + width) * cpp,
      yoffset, yoffset + height,
-      bo->virtual, pixels - yoffset * src_pitch - xoffset * cpp,
+      bo->virtual,
+      pixels - (ptrdiff_t) yoffset * src_pitch - (ptrdiff_t) xoffset * cpp,
      image->mt->pitch, src_pitch,
      brw->has_swizzling,
      image->mt->tiling,
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -622,7 +622,7 @@ descriptor=[
 # == GL_CURRENT_MATRIX_NV
  [ "CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX, 0, extra_ARB_vertex_program_ARB_fragment_program" ],
 # == GL_CURRENT_MATRIX_NV
-  [ "TRANSPOSE_CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX, 0, extra_ARB_vertex_program_ARB_fragment_program" ],
+  [ "TRANSPOSE_CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX_T, 0, extra_ARB_vertex_program_ARB_fragment_program" ],
 # == GL_PROGRAM_ERROR_POSITION_NV
  [ "PROGRAM_ERROR_POSITION_ARB", "CONTEXT_INT(Program.ErrorPos), extra_ARB_vertex_program_ARB_fragment_program" ],

--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1542,7 +1542,7 @@ _mesa_legal_texture_dimensions(struct gl_context *ctx, GLenum target,
      maxSize >>= level;
      if (width < 2 * border || width > 2 * border + maxSize)
         return GL_FALSE;
-      if (height < 1 || height > ctx->Const.MaxArrayTextureLayers)
+      if (height < 0 || height > ctx->Const.MaxArrayTextureLayers)
         return GL_FALSE;
      if (!ctx->Extensions.ARB_texture_non_power_of_two) {
         if (width > 0 && !_mesa_is_pow_two(width - 2 * border))
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -2225,7 +2225,7 @@ _mesa_compute_compressed_pixelstore(GLuint dims, mesa_format texFormat,

      if (packing->RowLength) {
         store->TotalBytesPerRow = packing->CompressedBlockSize *
-            (packing->RowLength + bw - 1) / bw;
+            ((packing->RowLength + bw - 1) / bw);
      }

      store->SkipBytes += packing->SkipPixels * packing->CompressedBlockSize / bw;
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -88,6 +88,14 @@ st_destroy_clear(struct st_context *st)
      cso_delete_vertex_shader(st->cso_context, st->clear.vs);
      st->clear.vs = NULL;
   }
+   if (st->clear.vs_layered) {
+      cso_delete_vertex_shader(st->cso_context, st->clear.vs_layered);
+      st->clear.vs_layered = NULL;
+   }
+   if (st->clear.gs_layered) {
+      cso_delete_geometry_shader(st->cso_context, st->clear.gs_layered);
+      st->clear.gs_layered = NULL;
+   }
 }


@@ -127,6 +135,7 @@ set_vertex_shader(struct st_context *st)
   }

   cso_set_vertex_shader_handle(st->cso_context, st->clear.vs);
+   cso_set_geometry_shader_handle(st->cso_context, NULL);
 }


@@ -135,18 +144,25 @@ set_vertex_shader_layered(struct st_context *st)
 {
   struct pipe_context *pipe = st->pipe;

-   if (!pipe->screen->get_param(pipe->screen, PIPE_CAP_TGSI_INSTANCEID) ||
-       !pipe->screen->get_param(pipe->screen, PIPE_CAP_TGSI_VS_LAYER_VIEWPORT)) {
-      assert(!"Got layered clear, but the VS layer output is unsupported");
+   if (!pipe->screen->get_param(pipe->screen, PIPE_CAP_TGSI_INSTANCEID)) {
+      assert(!"Got layered clear, but VS instancing is unsupported");
      set_vertex_shader(st);
      return;
   }

   if (!st->clear.vs_layered) {
-      st->clear.vs_layered = util_make_layered_clear_vertex_shader(pipe);
+      bool vs_layer =
+         pipe->screen->get_param(pipe->screen, PIPE_CAP_TGSI_VS_LAYER_VIEWPORT);
+      if (vs_layer) {
+         st->clear.vs_layered = util_make_layered_clear_vertex_shader(pipe);
+      } else {
+         st->clear.vs_layered = util_make_layered_clear_helper_vertex_shader(pipe);
+         st->clear.gs_layered = util_make_layered_clear_geometry_shader(pipe);
+      }
   }

   cso_set_vertex_shader_handle(st->cso_context, st->clear.vs_layered);
+   cso_set_geometry_shader_handle(st->cso_context, st->clear.gs_layered);
 }


@@ -332,7 +348,6 @@ clear_with_quad(struct gl_context *ctx, unsigned clear_buffers)
   }

   set_fragment_shader(st);
-   cso_set_geometry_shader_handle(st->cso_context, NULL);

   if (num_layers > 1)
      set_vertex_shader_layered(st);
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -181,6 +181,7 @@ struct st_context
      void *vs;
      void *fs;
      void *vs_layered;
+      void *gs_layered;
   } clear;

   /** used for anything using util_draw_vertex_buffer */
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.c
@@ -40,6 +40,7 @@
 #include "main/image.h"
 #include "main/bufferobj.h"
 #include "main/macros.h"
+#include "main/varray.h"

 #include "vbo/vbo.h"

@@ -234,7 +235,7 @@ st_draw_vbo(struct gl_context *ctx,
       * so we only set these fields for indexed drawing:
       */
      info.primitive_restart = ctx->Array._PrimitiveRestart;
-      info.restart_index = ctx->Array.RestartIndex;
+      info.restart_index = _mesa_primitive_restart_index(ctx, ib->type);
   }
   else {
      /* Transform feedback drawing is always non-indexed. */
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -3564,7 +3564,8 @@ glsl_to_tgsi_visitor::copy_propagate(void)
               first = copy_chan;
            } else {
               if (first->src[0].file != copy_chan->src[0].file ||
-        	   first->src[0].index != copy_chan->src[0].index) {
+                   first->src[0].index != copy_chan->src[0].index ||
+                   first->src[0].index2D != copy_chan->src[0].index2D) {
        	  good = false;
        	  break;
               }
@@ -4059,6 +4060,7 @@ get_pixel_transfer_visitor(struct st_fragment_program *fp,

      newinst = v->emit(NULL, inst->op, inst->dst, src_regs[0], src_regs[1], src_regs[2]);
      newinst->tex_target = inst->tex_target;
+      newinst->sampler_array_size = inst->sampler_array_size;
   }

   /* Make modifications to fragment program info. */
@@ -4138,6 +4140,7 @@ get_bitmap_visitor(struct st_fragment_program *fp,

      newinst = v->emit(NULL, inst->op, inst->dst, src_regs[0], src_regs[1], src_regs[2]);
      newinst->tex_target = inst->tex_target;
+      newinst->sampler_array_size = inst->sampler_array_size;
   }

   /* Make modifications to fragment program info. */
@@ -4561,8 +4564,10 @@ compile_tgsi_instruction(struct st_translate *t,
                             inst->saturate,
                             clamp_dst_color_output);

-   for (i = 0; i < num_src; i++) 
+   for (i = 0; i < num_src; i++) {
+      assert(inst->src[i].file != PROGRAM_UNDEFINED);
      src[i] = translate_src(t, &inst->src[i]);
+   }

   switch(inst->op) {
   case TGSI_OPCODE_BGNLOOP:
@@ -4592,6 +4597,7 @@ compile_tgsi_instruction(struct st_translate *t,
   case TGSI_OPCODE_TG4:
   case TGSI_OPCODE_LODQ:
      src[num_src] = t->samplers[inst->sampler.index];
+      assert(src[num_src].File != TGSI_FILE_NULL);
      if (inst->sampler.reladdr)
         src[num_src] =
            ureg_src_indirect(src[num_src], ureg_src(t->address[2]));
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -620,7 +620,8 @@ vbo_draw_arrays(struct gl_context *ctx, GLenum mode, GLint start,
   prim[0].is_indirect = 0;

   /* Implement the primitive restart index */
-   if (ctx->Array.PrimitiveRestart && ctx->Array.RestartIndex < count) {
+   if (ctx->Array.PrimitiveRestart && !ctx->Array.PrimitiveRestartFixedIndex &&
+       ctx->Array.RestartIndex < count) {
      GLuint primCount = 0;

      if (ctx->Array.RestartIndex == start) {
@@ -1 +1 @@
 .3.3
 .3.7