docs: add release notes for 17.1.3

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Update version to 17.1.3
2017-06-19 12:13:25 +01:00 · 2017-06-19 12:10:00 +01:00 · 2017-06-14 12:47:58 +01:00 · 2017-06-14 12:47:58 +01:00 · 2017-06-14 12:47:58 +01:00 · 2017-06-14 12:47:58 +01:00
38 changed files with 415 additions and 186 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-17.1.2
+17.1.3
--- a/configure.ac
+++ b/configure.ac
@@ -97,7 +97,7 @@ XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
 PYTHON_MAKO_REQUIRED=0.8.0
 LIBSENSORS_REQUIRED=4.0.0
-ZLIB_REQUIRED=1.2.8
+ZLIB_REQUIRED=1.2.3

 dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
@@ -2476,10 +2476,10 @@ if test -n "$with_gallium_drivers"; then
        xswr)
            llvm_require_version $LLVM_REQUIRED_SWR "swr"

-            swr_require_cxx_feature_flags "C++14" "__cplusplus >= 201402L" \
-                "-std=c++14" \
-                SWR_CXX14_CXXFLAGS
-            AC_SUBST([SWR_CXX14_CXXFLAGS])
+            swr_require_cxx_feature_flags "C++11" "__cplusplus >= 201103L" \
+                ",-std=c++11" \
+                SWR_CXX11_CXXFLAGS
+            AC_SUBST([SWR_CXX11_CXXFLAGS])

            swr_require_cxx_feature_flags "AVX" "defined(__AVX__)" \
                ",-mavx,-march=core-avx" \
--- a/docs/relnotes/17.1.2.html
+++ b/docs/relnotes/17.1.2.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+0d2020c2115db0d13a5be0075abf0da143290f69f5817a2f277861e89166a3e1  mesa-17.1.2.tar.gz
+0937804f43746339b1f9540d8f9c8b4a1bb3d3eec0e4020eac283b8799798239  mesa-17.1.2.tar.xz
 </pre>


--- a/docs/relnotes/17.1.3.html
+++ b/docs/relnotes/17.1.3.html
@@ -0,0 +1,155 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.3 Release Notes / June 19, 2017</h1>
+
+<p>
+Mesa 17.1.3 is a bug fix release which fixes bugs found since the 17.1.2 release.
+</p>
+<p>
+Mesa 17.1.3 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100988">Bug 100988</a> - glXGetCurrentDisplay() no longer works for FakeGLX contexts?</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+  <li>radv: Set both compute and graphics SGPRS on descriptor set flush.</li>
+  <li>radv: Dirty all descriptors sets when changing the pipeline.</li>
+  <li>radv: Remove SI num RB override for occlusion queries.</li>
+</ul>
+
+<p>Brian Paul (1):</p>
+<ul>
+  <li>xlib: fix glXGetCurrentDisplay() failure</li>
+</ul>
+
+<p>Chad Versace (1):</p>
+<ul>
+  <li>i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer()</li>
+</ul>
+
+<p>Chuck Atkins (1):</p>
+<ul>
+  <li>configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3.</li>
+</ul>
+
+<p>Dave Airlie (3):</p>
+<ul>
+  <li>radv: expose integrated device type for APUs.</li>
+  <li>radv: set fmask state to all 0s when no fmask. (v2)</li>
+  <li>glsl/lower_distance: only set max_array_access for 1D clip dist arrays</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>Update version to 17.1.3</li>
+</ul>
+
+<p>Grazvydas Ignotas (1):</p>
+<ul>
+  <li>radv: fix trace dumping for !use_ib_bos</li>
+</ul>
+
+<p>Jason Ekstrand (4):</p>
+<ul>
+  <li>i965/blorp: Take a layer range in intel_hiz_exec</li>
+  <li>i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec</li>
+  <li>i965: Perform HiZ flush/stall prior to HiZ resolves</li>
+  <li>i965: Mark depth surfaces as needing a HiZ resolve after blitting</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>automake: Link all libGL.so variants with -Bsymbolic.</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+  <li>docs: add sha256 checksums for 17.1.2</li>
+</ul>
+
+<p>Lucas Stach (1):</p>
+<ul>
+  <li>etnaviv: always do cpu_fini in transfer_unmap</li>
+</ul>
+
+<p>Lyude (1):</p>
+<ul>
+  <li>nvc0: disable BGRA8 images on Fermi</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+  <li>st/mesa: don't load cached TGSI shaders on demand</li>
+  <li>radeonsi: fix a GPU hang with tessellation on 2-CU configs</li>
+  <li>radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2)</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+  <li>radv: fewer than 8 RBs are possible</li>
+</ul>
+
+<p>Nicolas Dechesne (1):</p>
+<ul>
+  <li>util/rand_xor: add missing include statements</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>egl: fix _eglQuerySurface in EGL_BUFFER_AGE_EXT case</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+  <li>dri3/GLX: Fix drawable invalidation v2</li>
+</ul>
+
+<p>Tim Rowley (1):</p>
+<ul>
+  <li>swr: relax c++ requirement from c++14 to c++11</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1268,38 +1268,39 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,

 static void
 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
-				  struct radv_pipeline *pipeline,
 				  VkShaderStageFlags stages,
 				  struct radv_descriptor_set *set,
 				  unsigned idx)
 {
-	if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-						   idx, set->va,
-						   MESA_SHADER_FRAGMENT);
+	if (cmd_buffer->state.pipeline) {
+		if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
+			emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+							   idx, set->va,
+							   MESA_SHADER_FRAGMENT);

-	if (stages & VK_SHADER_STAGE_VERTEX_BIT)
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-						   idx, set->va,
-						   MESA_SHADER_VERTEX);
+		if (stages & VK_SHADER_STAGE_VERTEX_BIT)
+			emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+							   idx, set->va,
+							   MESA_SHADER_VERTEX);

-	if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-						   idx, set->va,
-						   MESA_SHADER_GEOMETRY);
+		if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(cmd_buffer->state.pipeline))
+			emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+							   idx, set->va,
+							   MESA_SHADER_GEOMETRY);

-	if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-						   idx, set->va,
-						   MESA_SHADER_TESS_CTRL);
+		if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+			emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+							   idx, set->va,
+							   MESA_SHADER_TESS_CTRL);

-	if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-						   idx, set->va,
-						   MESA_SHADER_TESS_EVAL);
+		if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+			emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+							   idx, set->va,
+							   MESA_SHADER_TESS_EVAL);
+	}

-	if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
-		emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
+	if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
+		emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
 						   idx, set->va,
 						   MESA_SHADER_COMPUTE);
 }
@@ -1324,7 +1325,6 @@ radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)

 static void
 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
-		       struct radv_pipeline *pipeline,
 		       VkShaderStageFlags stages)
 {
 	unsigned i;
@@ -1345,7 +1345,7 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
 		if (!set)
 			continue;

-		radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
+		radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
 	}
 	cmd_buffer->state.descriptors_dirty = 0;
 	cmd_buffer->state.push_descriptors_dirty = false;
@@ -1515,8 +1515,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,

 	radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);

-	radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
-			       VK_SHADER_STAGE_ALL_GRAPHICS);
+	radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
 	radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
 			     VK_SHADER_STAGE_ALL_GRAPHICS);

@@ -2153,6 +2152,13 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
 	assert(cmd_buffer->cs->cdw <= cdw_max);
 }

+static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
+{
+	for (unsigned i = 0; i < MAX_SETS; i++) {
+		if (cmd_buffer->state.descriptors[i])
+			cmd_buffer->state.descriptors_dirty |= (1u << i);
+	}
+}

 void radv_CmdBindPipeline(
 	VkCommandBuffer                             commandBuffer,
@@ -2162,10 +2168,7 @@ void radv_CmdBindPipeline(
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 	RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);

-	for (unsigned i = 0; i < MAX_SETS; i++) {
-		if (cmd_buffer->state.descriptors[i])
-			cmd_buffer->state.descriptors_dirty |= (1 << i);
-	}
+	radv_mark_descriptor_sets_dirty(cmd_buffer);

 	switch (pipelineBindPoint) {
 	case VK_PIPELINE_BIND_POINT_COMPUTE:
@@ -2174,6 +2177,9 @@ void radv_CmdBindPipeline(
 		break;
 	case VK_PIPELINE_BIND_POINT_GRAPHICS:
 		cmd_buffer->state.pipeline = pipeline;
+		if (!pipeline)
+			break;
+
 		cmd_buffer->state.vertex_descriptors_dirty = true;
 		cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
 		cmd_buffer->push_constant_stages |= pipeline->active_stages;
@@ -2336,7 +2342,6 @@ void radv_CmdSetStencilReference(
 	cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
 }

-
 void radv_CmdExecuteCommands(
 	VkCommandBuffer                             commandBuffer,
 	uint32_t                                    commandBufferCount,
@@ -2381,6 +2386,7 @@ void radv_CmdExecuteCommands(
 		primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
 		primary->state.last_primitive_reset_en = -1;
 		primary->state.last_primitive_reset_index = 0;
+		radv_mark_descriptor_sets_dirty(primary);
 	}
 }

@@ -2757,8 +2763,7 @@ static void
 radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
 {
 	radv_emit_compute_pipeline(cmd_buffer);
-	radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
-			       VK_SHADER_STAGE_COMPUTE_BIT);
+	radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
 	radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
 			     VK_SHADER_STAGE_COMPUTE_BIT);
 	si_emit_cache_flush(cmd_buffer);
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -676,7 +676,7 @@ void radv_GetPhysicalDeviceProperties(
 		.driverVersion = radv_get_driver_version(),
 		.vendorID = 0x1002,
 		.deviceID = pdevice->rad_info.pci_id,
-		.deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
+		.deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
 		.limits = limits,
 		.sparseProperties = {0},
 	};
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -382,7 +382,8 @@ si_make_texture_descriptor(struct radv_device *device,
 			S_008F24_LAST_ARRAY(last_layer);
 		fmask_state[6] = 0;
 		fmask_state[7] = 0;
-	}
+	} else if (fmask_state)
+		memset(fmask_state, 0, 8 * 4);
 }

 static void
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -51,10 +51,10 @@ void
 radv_meta_restore(const struct radv_meta_saved_state *state,
 		  struct radv_cmd_buffer *cmd_buffer)
 {
-	cmd_buffer->state.pipeline = state->old_pipeline;
+	radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
+			     radv_pipeline_to_handle(state->old_pipeline));

 	cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-	cmd_buffer->state.descriptors_dirty |= (1u << 0);
 	memcpy(cmd_buffer->state.vertex_bindings, state->old_vertex_bindings,
 	       sizeof(state->old_vertex_bindings));

@@ -114,7 +114,6 @@ radv_meta_restore_compute(const struct radv_meta_saved_compute_state *state,
 			     radv_pipeline_to_handle(state->old_pipeline));

 	cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-	cmd_buffer->state.descriptors_dirty |= (1u << 0);

 	if (push_constant_size) {
 		memcpy(cmd_buffer->push_constants, state->push_constants, push_constant_size);
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -44,11 +44,6 @@ static unsigned get_max_db(struct radv_device *device)
 	unsigned num_db = device->physical_device->rad_info.num_render_backends;
 	MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;

-	if (device->physical_device->rad_info.chip_class == SI)
-		num_db = 8;
-	else
-		num_db = MAX2(8, num_db);
-
 	/* Otherwise we need to change the query reset procedure */
 	assert(rb_mask == ((1ull << num_db) - 1));

--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -931,6 +931,9 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
 {
 	struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
 	void *ret = NULL;
+
+	if (!cs->ib_buffer)
+		return NULL;
 	for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
 		struct radv_amdgpu_winsys_bo *bo;

@@ -949,10 +952,15 @@ static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
                                       uint32_t trace_id)
 {
 	struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
+	void *ib = cs->base.buf;
+	int num_dw = cs->base.cdw;

-	ac_parse_ib(file,
-		    radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address),
-		    cs->ib.size, trace_id,  "main IB", cs->ws->info.chip_class,
+	if (cs->ws->use_ib_bos) {
+		ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
+		num_dw = cs->ib.size;
+	}
+	assert(ib);
+	ac_parse_ib(file, ib, num_dw, trace_id, "main IB", cs->ws->info.chip_class,
 		    radv_amdgpu_winsys_get_cpu_addr, cs);
 }

--- a/src/compiler/glsl/lower_distance.cpp
+++ b/src/compiler/glsl/lower_distance.cpp
@@ -167,7 +167,6 @@ lower_distance_visitor::visit(ir_variable *ir)
      /* Clone the old var so that we inherit all of its properties */
      *new_var = ir->clone(ralloc_parent(ir), NULL);
      (*new_var)->name = ralloc_strdup(*new_var, GLSL_CLIP_VAR_NAME);
-      (*new_var)->data.max_array_access = new_size - 1;
      (*new_var)->data.location = VARYING_SLOT_CLIP_DIST0;

      if (!ir->type->fields.array->is_array()) {
@@ -182,6 +181,7 @@ lower_distance_visitor::visit(ir_variable *ir)
                  this->shader_stage == MESA_SHADER_GEOMETRY)));

         assert (ir->type->fields.array == glsl_type::float_type);
+         (*new_var)->data.max_array_access = new_size - 1;

         /* And change the properties that we need to change */
         (*new_var)->type = glsl_type::get_array_instance(glsl_type::vec4_type,
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -609,10 +609,10 @@ droid_query_buffer_age(_EGLDriver *drv,

   if (update_buffers(dri2_surf) < 0) {
      _eglError(EGL_BAD_ALLOC, "droid_query_buffer_age");
-      return 0;
+      return -1;
   }

-   return dri2_surf->back->age;
+   return dri2_surf->back ? dri2_surf->back->age : 0;
 }

 static EGLBoolean
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -463,7 +463,7 @@ dri2_drm_query_buffer_age(_EGLDriver *drv,

   if (get_back_bo(dri2_surf) < 0) {
      _eglError(EGL_BAD_ALLOC, "dri2_query_buffer_age");
-      return 0;
+      return -1;
   }

   return dri2_surf->back->age;
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -808,7 +808,7 @@ dri2_wl_query_buffer_age(_EGLDriver *drv,

   if (get_back_bo(dri2_surf) < 0) {
      _eglError(EGL_BAD_ALLOC, "dri2_query_buffer_age");
-      return 0;
+      return -1;
   }

   return dri2_surf->back->age;
--- a/src/egl/main/eglsurface.c
+++ b/src/egl/main/eglsurface.c
@@ -409,7 +409,11 @@ _eglQuerySurface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surface,
         _eglError(EGL_BAD_ATTRIBUTE, "eglQuerySurface");
         return EGL_FALSE;
      }
-      *value = drv->API.QueryBufferAge(drv, dpy, surface);
+      EGLint result = drv->API.QueryBufferAge(drv, dpy, surface);
+      /* error happened */
+      if (result < 0)
+         return EGL_FALSE;
+      *value = result;
      break;
   default:
      _eglError(EGL_BAD_ATTRIBUTE, "eglQuerySurface");
--- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
@@ -70,6 +70,9 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans)
   if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture)))
      rsc = etna_resource(rsc->texture); /* switch to using the texture resource */

+   if (trans->rsc)
+      etna_bo_cpu_fini(etna_resource(trans->rsc)->bo);
+
   if (ptrans->usage & PIPE_TRANSFER_WRITE) {
      if (trans->rsc) {
         /* We have a temporary resource due to either tile status or
@@ -105,15 +108,15 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans)
      }

      rsc->seqno++;
-      etna_bo_cpu_fini(rsc->bo);

      if (rsc->base.bind & PIPE_BIND_SAMPLER_VIEW) {
-         /* XXX do we need to flush the CPU cache too or start a write barrier
-          * to make sure the GPU sees it? */
         ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
      }
   }

+   if (!trans->rsc)
+      etna_bo_cpu_fini(rsc->bo);
+
   pipe_resource_reference(&trans->rsc, NULL);
   pipe_resource_reference(&ptrans->resource, NULL);
   slab_free(&ctx->transfer_pool, trans);
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -90,11 +90,20 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
   bindings &= ~(PIPE_BIND_LINEAR |
                 PIPE_BIND_SHARED);

-   if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
-       nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
-      /* MS images are currently unsupported on Maxwell because they have to
-       * be handled explicitly. */
-      return false;
+   if (bindings & PIPE_BIND_SHADER_IMAGE) {
+      if (sample_count > 1 &&
+          nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
+         /* MS images are currently unsupported on Maxwell because they have to
+          * be handled explicitly. */
+         return false;
+      }
+
+      if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
+          nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
+         /* This should work on Fermi, but for currently unknown reasons it
+          * does not and results in breaking reads from pbos. */
+         return false;
+      }
   }

   return (( nvc0_format_table[format].usage |
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -366,6 +366,7 @@ struct si_context {
 	struct si_shader_selector *last_tcs;
 	int			last_num_tcs_input_cp;
 	int			last_tes_sh_base;
+	bool			last_tess_uses_primid;
 	unsigned		last_num_patches;

 	/* Debug state. */
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -101,6 +101,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	 * It would be wrong to think that TCS = TES. */
 	struct si_shader_selector *tcs =
 		sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
+	unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id;
+	bool has_primid_instancing_bug = sctx->b.chip_class == SI &&
+					 sctx->b.screen->info.max_se == 1;
 	unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
 	unsigned num_tcs_input_cp = info->vertices_per_patch;
 	unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
@@ -114,7 +117,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	if (sctx->last_ls == ls->current &&
 	    sctx->last_tcs == tcs &&
 	    sctx->last_tes_sh_base == tes_sh_base &&
-	    sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
+	    sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
+	    (!has_primid_instancing_bug ||
+	     (sctx->last_tess_uses_primid == tess_uses_primid))) {
 		*num_patches = sctx->last_num_patches;
 		return;
 	}
@@ -123,6 +128,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	sctx->last_tcs = tcs;
 	sctx->last_tes_sh_base = tes_sh_base;
 	sctx->last_num_tcs_input_cp = num_tcs_input_cp;
+	sctx->last_tess_uses_primid = tess_uses_primid;

 	/* This calculates how shader inputs and outputs among VS, TCS, and TES
 	 * are laid out in LDS. */
@@ -155,8 +161,12 @@ static void si_emit_derived_tess_state(struct si_context *sctx,

 	/* Make sure that the data fits in LDS. This assumes the shaders only
 	 * use LDS for the inputs and outputs.
+	 *
+	 * While CIK can use 64K per threadgroup, there is a hang on Stoney
+	 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
+	 * uses 32K at most on all GCN chips.
 	 */
-	hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
+	hardware_lds_size = 32768;
 	*num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
 	                                                       output_patch_size));

@@ -174,22 +184,21 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 	if (sctx->b.chip_class == SI) {
 		unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
 		*num_patches = MIN2(*num_patches, one_wave);
-
-		if (sctx->screen->b.info.max_se == 1) {
-			/* The VGT HS block increments the patch ID unconditionally
-			 * within a single threadgroup. This results in incorrect
-			 * patch IDs when instanced draws are used.
-			 *
-			 * The intended solution is to restrict threadgroups to
-			 * a single instance by setting SWITCH_ON_EOI, which
-			 * should cause IA to split instances up. However, this
-			 * doesn't work correctly on SI when there is no other
-			 * SE to switch to.
-			 */
-			*num_patches = 1;
-		}
 	}

+	/* The VGT HS block increments the patch ID unconditionally
+	 * within a single threadgroup. This results in incorrect
+	 * patch IDs when instanced draws are used.
+	 *
+	 * The intended solution is to restrict threadgroups to
+	 * a single instance by setting SWITCH_ON_EOI, which
+	 * should cause IA to split instances up. However, this
+	 * doesn't work correctly on SI when there is no other
+	 * SE to switch to.
+	 */
+	if (has_primid_instancing_bug)
+		*num_patches = 1;
+
 	sctx->last_num_patches = *num_patches;

 	output_patch0_offset = input_patch_size * *num_patches;
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -22,7 +22,7 @@
 include Makefile.sources
 include $(top_srcdir)/src/gallium/Automake.inc

-AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX14_CXXFLAGS)
+AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX11_CXXFLAGS)

 noinst_LTLIBRARIES = libmesaswr.la

@@ -32,7 +32,7 @@ COMMON_CXXFLAGS = \
 	-fno-strict-aliasing \
 	$(GALLIUM_DRIVER_CFLAGS) \
 	$(LLVM_CXXFLAGS) \
-	$(SWR_CXX14_CXXFLAGS) \
+	$(SWR_CXX11_CXXFLAGS) \
 	-I$(builddir)/rasterizer/codegen \
 	-I$(builddir)/rasterizer/jitter \
 	-I$(builddir)/rasterizer/archrast \
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -38,7 +38,7 @@ loadersource = env.ParseSourceList('Makefile.sources', [

 if not env['msvc'] :
    env.Append(CCFLAGS = [
-        '-std=c++14',
+        '-std=c++11',
    ])

 swrroot = '#src/gallium/drivers/swr/'
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -953,26 +953,27 @@ public:


 private:
+    template <typename MaskT>
+    INLINE __m128i expandThenBlend4(uint32_t* min, uint32_t* max) // @llvm_func_start
+    {
+        __m128i vMin = _mm_set1_epi32(*min);
+        __m128i vMax = _mm_set1_epi32(*max);
+        return _simd_blend4_epi32<MaskT::value>(vMin, vMax);
+    }  // @llvm_func_end
+
    INLINE void CalcTileSampleOffsets(int numSamples)   // @llvm_func_start
-    {                                                                      
-        auto expandThenBlend4 = [](uint32_t* min, uint32_t* max, auto mask)
-        {
-            __m128i vMin = _mm_set1_epi32(*min);
-            __m128i vMax = _mm_set1_epi32(*max);
-            return _simd_blend4_epi32<decltype(mask)::value>(vMin, vMax);
-        };
-                                                                           
+    {
        auto minXi = std::min_element(std::begin(_xi), &_xi[numSamples]);
        auto maxXi = std::max_element(std::begin(_xi), &_xi[numSamples]);
-        std::integral_constant<int, 0xA> xMask;
+        using xMask = std::integral_constant<int, 0xA>;
        // BR(max),    BL(min),    UR(max),    UL(min)
-        tileSampleOffsetsX = expandThenBlend4(minXi, maxXi, xMask);
-        
+        tileSampleOffsetsX = expandThenBlend4<xMask>(minXi, maxXi);
+
        auto minYi = std::min_element(std::begin(_yi), &_yi[numSamples]);
        auto maxYi = std::max_element(std::begin(_yi), &_yi[numSamples]);
-        std::integral_constant<int, 0xC> yMask;
+        using yMask = std::integral_constant<int, 0xC>;
        // BR(max),    BL(min),    UR(max),    UL(min)
-        tileSampleOffsetsY = expandThenBlend4(minYi, maxYi, yMask);
+        tileSampleOffsetsY = expandThenBlend4<yMask>(minYi, maxYi);
    };  // @llvm_func_end
    // scalar sample values
    uint32_t _xi[SWR_MAX_NUM_MULTISAMPLES];
--- a/src/gallium/targets/libgl-xlib/Makefile.am
+++ b/src/gallium/targets/libgl-xlib/Makefile.am
@@ -54,6 +54,7 @@ lib@GL_LIB@_la_SOURCES = xlib.c
 lib@GL_LIB@_la_LDFLAGS = \
 	-no-undefined \
 	-version-number $(GL_MAJOR):$(GL_MINOR):$(GL_TINY) \
+	$(BSYMBOLIC) \
 	$(GC_SECTIONS) \
 	$(LD_NO_UNDEFINED)

--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -235,6 +235,11 @@ dri3_bind_context(struct glx_context *context, struct glx_context *old,
   if (!(*psc->core->bindContext) (pcp->driContext, dri_draw, dri_read))
      return GLXBadContext;

+   if (dri_draw)
+      (*psc->f->invalidate)(dri_draw);
+   if (dri_read && dri_read != dri_draw)
+      (*psc->f->invalidate)(dri_read);
+
   return Success;
 }

@@ -493,6 +498,7 @@ dri3_flush_front_buffer(__DRIdrawable *driDrawable, void *loaderPrivate)

   loader_dri3_flush(draw, __DRI2_FLUSH_DRAWABLE, __DRI2_THROTTLE_FLUSHFRONT);

+   (*psc->f->invalidate)(driDrawable);
   loader_dri3_wait_gl(draw);
 }

--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1047,7 +1047,8 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 */
 void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
-	       unsigned int level, unsigned int layer, enum blorp_hiz_op op)
+               unsigned int level, unsigned int start_layer,
+               unsigned int num_layers, enum blorp_hiz_op op)
 {
   const char *opname = NULL;

@@ -1066,12 +1067,85 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
      break;
   }

-   DBG("%s %s to mt %p level %d layer %d\n",
-       __func__, opname, mt, level, layer);
+   DBG("%s %s to mt %p level %d layers %d-%d\n",
+       __func__, opname, mt, level, start_layer, start_layer + num_layers - 1);
+
+   /* The following stalls and flushes are only documented to be required for
+    * HiZ clear operations.  However, they also seem to be required for the
+    * HiZ resolve operation which is basically the same as a fast clear only a
+    * different value is written into the HiZ surface.
+    */
+   if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
+      if (brw->gen == 6) {
+         /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
+          *
+          *   "If other rendering operations have preceded this clear, a
+          *   PIPE_CONTROL with write cache flush enabled and Z-inhibit
+          *   disabled must be issued before the rectangle primitive used for
+          *   the depth buffer clear operation.
+          */
+          brw_emit_pipe_control_flush(brw,
+                                      PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                                      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                      PIPE_CONTROL_CS_STALL);
+      } else if (brw->gen >= 7) {
+         /*
+          * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
+          *
+          *   If other rendering operations have preceded this clear, a
+          *   PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
+          *   enabled must be issued before the rectangle primitive used for
+          *   the depth buffer clear operation.
+          *
+          * Same applies for Gen8 and Gen9.
+          *
+          * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
+          * PIPE_CONTROL, Depth Cache Flush Enable:
+          *
+          *   This bit must not be set when Depth Stall Enable bit is set in
+          *   this packet.
+          *
+          * This is confirmed to hold for real, HSW gets immediate gpu hangs.
+          *
+          * Therefore issue two pipe control flushes, one for cache flush and
+          * another for depth stall.
+          */
+          brw_emit_pipe_control_flush(brw,
+                                      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                      PIPE_CONTROL_CS_STALL);
+
+          brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+      }
+   }

   if (brw->gen >= 8) {
-      gen8_hiz_exec(brw, mt, level, layer, op);
+      for (unsigned a = 0; a < num_layers; a++)
+         gen8_hiz_exec(brw, mt, level, start_layer + a, op);
   } else {
-      gen6_blorp_hiz_exec(brw, mt, level, layer, op);
+      for (unsigned a = 0; a < num_layers; a++)
+         gen6_blorp_hiz_exec(brw, mt, level, start_layer + a, op);
+   }
+
+
+   /* The following stalls and flushes are only documented to be required for
+    * HiZ clear operations.  However, they also seem to be required for the
+    * HiZ resolve operation which is basically the same as a fast clear only a
+    * different value is written into the HiZ surface.
+    */
+   if (op == BLORP_HIZ_OP_DEPTH_CLEAR || op == BLORP_HIZ_OP_HIZ_RESOLVE) {
+      if (brw->gen == 6) {
+         /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+          *
+          *     "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be
+          *     followed by a PIPE_CONTROL command with DEPTH_STALL bit set
+          *     and Then followed by Depth FLUSH'
+         */
+         brw_emit_pipe_control_flush(brw,
+                                     PIPE_CONTROL_DEPTH_STALL);
+
+         brw_emit_pipe_control_flush(brw,
+                                     PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                     PIPE_CONTROL_CS_STALL);
+      }
   }
 }
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -70,7 +70,8 @@ brw_blorp_resolve_color(struct brw_context *brw,

 void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
-	       unsigned int level, unsigned int layer, enum blorp_hiz_op op);
+               unsigned int level, unsigned int start_layer,
+               unsigned int num_layers, enum blorp_hiz_op op);

 void gen6_blorp_exec(struct blorp_batch *batch,
                     const struct blorp_params *params);
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -175,71 +175,13 @@ brw_fast_clear_depth(struct gl_context *ctx)
      mt->depth_clear_value = depth_clear_value;
   }

-   if (brw->gen == 6) {
-      /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
-       *
-       *   "If other rendering operations have preceded this clear, a
-       *    PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
-       *    must be issued before the rectangle primitive used for the depth
-       *    buffer clear operation.
-       */
-       brw_emit_pipe_control_flush(brw,
-                                   PIPE_CONTROL_RENDER_TARGET_FLUSH |
-                                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                                   PIPE_CONTROL_CS_STALL);
-   } else if (brw->gen >= 7) {
-      /*
-       * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
-       *
-       *   If other rendering operations have preceded this clear, a
-       *   PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
-       *   enabled must be issued before the rectangle primitive used for the
-       *   depth buffer clear operation.
-       *
-       * Same applies for Gen8 and Gen9.
-       *
-       * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1 PIPE_CONTROL,
-       * Depth Cache Flush Enable:
-       *
-       *   This bit must not be set when Depth Stall Enable bit is set in
-       *   this packet.
-       *
-       * This is confirmed to hold for real, HSW gets immediate gpu hangs.
-       *
-       * Therefore issue two pipe control flushes, one for cache flush and
-       * another for depth stall.
-       */
-       brw_emit_pipe_control_flush(brw,
-                                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                                   PIPE_CONTROL_CS_STALL);
-
-       brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
-   }
-
   if (fb->MaxNumLayers > 0) {
-      for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
-         intel_hiz_exec(brw, mt, depth_irb->mt_level,
-                        depth_irb->mt_layer + layer,
-                        BLORP_HIZ_OP_DEPTH_CLEAR);
-      }
-   } else {
-      intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer,
+      intel_hiz_exec(brw, mt, depth_irb->mt_level,
+                     depth_irb->mt_layer, depth_irb->layer_count,
+                     BLORP_HIZ_OP_DEPTH_CLEAR);
+   } else {
+      intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, 1,
                     BLORP_HIZ_OP_DEPTH_CLEAR);
-   }
-
-   if (brw->gen == 6) {
-      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
-       *
-       *     "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
-       *      by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
-       *      followed by Depth FLUSH'
-      */
-      brw_emit_pipe_control_flush(brw,
-                                  PIPE_CONTROL_DEPTH_STALL);
-
-      brw_emit_pipe_control_flush(brw,
-                                  PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                                  PIPE_CONTROL_CS_STALL);
   }

   /* Now, the HiZ buffer contains data that needs to be resolved to the depth
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -329,6 +329,7 @@ intel_miptree_blit(struct brw_context *brw,
   intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
   intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
   intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
+   intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);

   if (src_flip)
      src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
@@ -387,6 +388,7 @@ intel_miptree_copy(struct brw_context *brw,
   intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
   intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
   intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
+   intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);

   uint32_t src_image_x, src_image_y;
   intel_miptree_get_image_offset(src_mt, src_level, src_slice,
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -442,13 +442,9 @@ intel_create_renderbuffer(mesa_format format, unsigned num_samples)
   struct intel_renderbuffer *irb;
   struct gl_renderbuffer *rb;

-   GET_CURRENT_CONTEXT(ctx);
-
   irb = CALLOC_STRUCT(intel_renderbuffer);
-   if (!irb) {
-      _mesa_error(ctx, GL_OUT_OF_MEMORY, "creating renderbuffer");
+   if (!irb)
      return NULL;
-   }

   rb = &irb->Base.Base;
   irb->layer_count = 1;
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1992,7 +1992,7 @@ intel_miptree_slice_resolve(struct brw_context *brw,
   if (!item || item->need != need)
      return false;

-   intel_hiz_exec(brw, mt, level, layer, need);
+   intel_hiz_exec(brw, mt, level, layer, 1, need);
   intel_resolve_map_remove(item);
   return true;
 }
@@ -2028,7 +2028,7 @@ intel_miptree_all_slices_resolve(struct brw_context *brw,
      if (map->need != need)
 	 continue;

-      intel_hiz_exec(brw, mt, map->level, map->layer, need);
+      intel_hiz_exec(brw, mt, map->level, map->layer, 1, need);
      intel_resolve_map_remove(map);
      did_resolve = true;
   }
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -1029,10 +1029,6 @@ intel_miptree_unmap(struct brw_context *brw,
 		    unsigned int level,
 		    unsigned int slice);

-void
-intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
-	       unsigned int level, unsigned int layer, enum blorp_hiz_op op);
-
 bool
 intel_miptree_sample_with_hiz(struct brw_context *brw,
                              struct intel_mipmap_tree *mt);
--- a/src/mesa/drivers/x11/Makefile.am
+++ b/src/mesa/drivers/x11/Makefile.am
@@ -76,6 +76,7 @@ lib@GL_LIB@_la_LIBADD = \
 lib@GL_LIB@_la_LDFLAGS = \
 	-no-undefined \
 	-version-number $(GL_MAJOR):$(GL_MINOR):$(GL_PATCH) \
+	$(BSYMBOLIC) \
 	$(GC_SECTIONS) \
 	$(LD_NO_UNDEFINED)

--- a/src/mesa/drivers/x11/glxapi.c
+++ b/src/mesa/drivers/x11/glxapi.c
@@ -379,13 +379,13 @@ glXQueryServerString(Display *dpy, int screen, int name)

 /*** GLX_VERSION_1_2 ***/

+/* declare here to avoid including xmesa.h */
+extern Display *XMesaGetCurrentDisplay(void);
+
 Display PUBLIC *
 glXGetCurrentDisplay(void)
 {
-   /* Same code as in libGL's glxext.c */
-   __GLXcontext *gc = (__GLXcontext *) glXGetCurrentContext();
-   if (NULL == gc) return NULL;
-   return gc->currentDpy;
+   return XMesaGetCurrentDisplay();
 }


--- a/src/mesa/drivers/x11/glxapi.h
+++ b/src/mesa/drivers/x11/glxapi.h
@@ -37,7 +37,6 @@
 * work properly.
 */
 typedef struct __GLXcontextRec {
-   Display *currentDpy;
   GLboolean isDirect;
   GLXDrawable currentDrawable;
   GLXDrawable currentReadable;
--- a/src/mesa/drivers/x11/xm_api.c
+++ b/src/mesa/drivers/x11/xm_api.c
@@ -1304,6 +1304,14 @@ XMesaBuffer XMesaGetCurrentReadBuffer( void )
 }


+Display *XMesaGetCurrentDisplay(void)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   XMesaContext xmctx = XMESA_CONTEXT(ctx);
+   return xmctx ? xmctx->display : NULL;
+}
+
+

 GLboolean XMesaSetFXmode( GLint mode )
 {
--- a/src/mesa/drivers/x11/xmesa.h
+++ b/src/mesa/drivers/x11/xmesa.h
@@ -240,6 +240,12 @@ extern XMesaBuffer XMesaGetCurrentBuffer( void );
 extern XMesaBuffer XMesaGetCurrentReadBuffer( void );


+/*
+ * Return display of current context.
+ */
+extern Display *XMesaGetCurrentDisplay( void );
+
+
 /*
 * Swap the front and back buffers for the given buffer.  No action is
 * taken if the buffer is not double buffered.
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -22,7 +22,7 @@
 */

 #include <stdio.h>
-
+#include "st_debug.h"
 #include "st_program.h"
 #include "st_shader_cache.h"
 #include "compiler/glsl/program.h"
@@ -383,6 +383,11 @@ st_load_tgsi_from_disk_cache(struct gl_context *ctx,
         _mesa_associate_uniform_storage(ctx, prog, glprog->Parameters,
                                         false);

+         /* Create Gallium shaders now instead of on demand. */
+         if (ST_DEBUG & DEBUG_PRECOMPILE ||
+             st->shader_has_one_variant[glprog->info.stage])
+            st_precompile_shader_variant(st, glprog);
+
         free(buffer);
      } else {
         /* Failed to find a matching cached shader so fallback to recompile.
--- a/src/util/rand_xor.c
+++ b/src/util/rand_xor.c
@@ -25,6 +25,7 @@
 #if defined(__linux__)
 #include <sys/file.h>
 #include <unistd.h>
+#include <fcntl.h>
 #else
 #include <time.h>
 #endif
Author	SHA1	Message	Date
Emil Velikov	f60875e211	docs: add release notes for 17.1.3 Signed-off-by: Emil Velikov <emil.velikov@collabora.com>	2017-06-19 12:13:25 +01:00
Emil Velikov	5ab872d64a	Update version to 17.1.3 Signed-off-by: Emil Velikov <emil.velikov@collabora.com>	2017-06-19 12:10:00 +01:00
Chuck Atkins	9bc4ee1c8e	configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3. Testing with zlib versions 1.2.{3,4,5,6,7,8} showed no difference in functionality, correctness, or zlib API usage and 1.2.3 is the oldest version available in still actively deployed production Linux distributions (RHEL/CentOS 6 and SuSE 11). Build 17.1.1 against the system supplied zlib-devel packages for 1.2.3 in EL6 and 1.2.7 on EL7. I then swapped out the zlib version at runtime via LD_LIBRARY_PATH with ones build from the release tarballs from zlib.net Testwise - I ran the piglit shader profile with --quick addded to the tests since I figured that would exercise the shader cache, which would in turn use zlib. Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com> Cc: 17.1 <mesa-stable@lists.freedesktop.org> Cc: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> [Emil Velikov: add hunk about version/piglit testing] Acked-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `ad69b037b1`)	2017-06-14 12:47:58 +01:00
Nicolas Dechesne	b708c2961e	util/rand_xor: add missing include statements Fixes for: src/util/rand_xor.c:60:13: error: implicit declaration of function 'open' [-Werror=implicit-function-declaration] int fd = open("/dev/urandom", O_RDONLY); ^~~~ src/util/rand_xor.c:60:34: error: 'O_RDONLY' undeclared (first use in this function) int fd = open("/dev/urandom", O_RDONLY); ^~~~~~~~ Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (cherry picked from commit `adadadc151`)	2017-06-14 12:47:58 +01:00
Dave Airlie	538975fdf8	glsl/lower_distance: only set max_array_access for 1D clip dist arrays The max_array_access field applies to the first dimension, which means we only want to set it for the 1D clip dist arrays. This fixes an ir_validate assert seen with KHR-GL44.cull_distance.functional on nouveau and radeon with debug builds. Fixes: `a08c4ebbe` (glsl: rewrite clip/cull distance lowering pass) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `53587b7105`)	2017-06-14 12:47:58 +01:00
Grazvydas Ignotas	3734a7de6c	radv: fix trace dumping for !use_ib_bos Fixes trace dumping crash for SI or when RADV_DEBUG=noibs is set. Fixes: `97dfff5410` "radv: Dump command buffer on hang." Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit `fae3b13905`)	2017-06-14 12:47:58 +01:00
Dave Airlie	423dab9d32	radv: set fmask state to all 0s when no fmask. (v2) The shader reads the descriptor to decide if it should take the fmask value, however we weren't initing it always, which meant random crap, esp with MSAA depth textures. Fixes random hangs with: dEQP-VK.glsl.builtin_var.fragdepth.* v2: check fmask_state is not NULL Fixes: `f4e499ec79` "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `51553c0bea`) [Emil Velikov: resolve trivial conflicts] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_image.c	2017-06-14 12:47:58 +01:00
Bas Nieuwenhuizen	18fd7249c5	radv: Remove SI num RB override for occlusion queries. radeonsi doesn't have it anymore either. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Fixes: `f4e499ec79` "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `59c2e2a061`)	2017-06-14 12:47:58 +01:00
Nicolai Hähnle	f66de22af4	radv: fewer than 8 RBs are possible This fixes the subsequent assertion on Bonaire. Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit `388d36dfd1`)	2017-06-14 12:47:58 +01:00
Dave Airlie	8bd7d8c042	radv: expose integrated device type for APUs. This just sets the vulkan device type depending on whether this is an APU or GPU. Signed-off-by: Dave Airlie <airlied@redhat.com> Fixes: `f4e499ec79` "radv: add initial non-conformant radv vulkan driver" (cherry picked from commit `2890a71158`)	2017-06-14 12:47:58 +01:00
Bas Nieuwenhuizen	ffb46c8826	radv: Dirty all descriptors sets when changing the pipeline. Sets could have been ignored during previous descriptor set flush due to the shader not using them and therefore no SGPR being assigned. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Fixes: `ae61ddabe8` "radv: move userdata sgpr ownership to compiler side." (cherry picked from commit `4415a46be2`) Conflicts: src/amd/vulkan/radv_cmd_buffer.c src/amd/vulkan/radv_meta.c	2017-06-14 12:47:58 +01:00
Bas Nieuwenhuizen	c8226d3782	radv: Set both compute and graphics SGPRS on descriptor set flush. We clear the descriptors_dirty array afterwards, so the SGPRs for the other pipeline don't get updated on the flush for that other draw/dispatch, so we have to make sure we do it immediately. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Fixes: `ae61ddabe8` "radv: move userdata sgpr ownership to compiler side." (cherry picked from commit `5fb8bb3065`) [Emil Velikov: drop radv_flush_indirect_descriptor_sets hunk - missing in branch] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/amd/vulkan/radv_cmd_buffer.c	2017-06-14 12:47:57 +01:00
Tapani Pälli	6f062ba893	egl: fix _eglQuerySurface in EGL_BUFFER_AGE_EXT case Specification states that in case of error, value should not be written, patch changes buffer age queries to return -1 in case of error so that we can skip changing the value. In addition, small change to droid_query_buffer_age to return 0 in case buffer does not have a back buffer available. Fixes: dEQP-EGL.functional.negative_partial_update.not_postable_surface Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Chad Versace <chadversary@chromium.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit `8fac894f9b`)	2017-06-14 12:47:57 +01:00
Tim Rowley	891dafc8e7	swr: relax c++ requirement from c++14 to c++11 Remove c++14 generic lambda to keep compiler requirement at c++11. No regressions on piglit or vtk test suites. Tested-by: Chuck Atkins <chuck.atkins@kitware.com> Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> CC: mesa-stable@lists.freedesktop.org (cherry picked from commit `0b80b02502`)	2017-06-14 12:47:57 +01:00
Marek Olšák	2a7279fa8f	radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2) The workaround causes a massive performance decrease on 1-SE parts. (Cape Verde, Hainan, Oland) The performance regression is already part of 17.0 and 17.1. v2: check tess_uses_prim_id Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (cherry picked from commit `391673af7a`) [Emil Velikov: s/tcs_tes_uses_prim_id/tess_uses_prim_id/] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>	2017-06-14 12:47:43 +01:00
Jason Ekstrand	ae960d7dee	i965: Mark depth surfaces as needing a HiZ resolve after blitting Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chadversary@chromium.org> (cherry picked from commit `5097fcbfdc`)	2017-06-14 10:40:22 +01:00
Jason Ekstrand	3a193c009b	i965: Perform HiZ flush/stall prior to HiZ resolves Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (cherry picked from commit `acbd02450b`)	2017-06-14 10:40:22 +01:00
Jason Ekstrand	4889bb6af3	i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (cherry picked from commit `acb9a2ef8f`)	2017-06-14 10:40:22 +01:00
Jason Ekstrand	845c238ce2	i965/blorp: Take a layer range in intel_hiz_exec Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (cherry picked from commit `252b004a51`)	2017-06-14 10:40:22 +01:00
Thomas Hellstrom	67acca073a	dri3/GLX: Fix drawable invalidation v2 A number of internal VMware apitrace traces image comparisons fail with dri3 because the viewport transformation becomes incorrect after an X drawable resize. The incorrect viewport transformation sometimes persist until the second draw-call after a swapBuffer. Comparing with the dri2 glx code there are a couple of places where dri2 invalidates the drawable in the absence of server-triggered invalidation, where dri3 doesn't do that. When these invalidation points are added to dri3, the image comparisons become correct. v2: Addressed review comment by Michel Dänzer. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit `1253d58983`)	2017-06-14 10:40:22 +01:00
Marek Olšák	7b10ed6a12	radeonsi: fix a GPU hang with tessellation on 2-CU configs Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced to 2 CUs. Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org> Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (cherry picked from commit `6c655cfeb4`)	2017-06-14 10:40:22 +01:00
Marek Olšák	5a8d7ef65a	st/mesa: don't load cached TGSI shaders on demand This fixes a performance issue with the shader cache that delayed Gallium shader create calls until draw calls. I'd like this in stable, but it's not a showstopper. Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit `2ec50f98a9`)	2017-06-14 10:40:22 +01:00
Lyude	98564569d0	nvc0: disable BGRA8 images on Fermi BGRA8 image stores on Fermi don't work, which results in breaking PBO downloads, such that they always return 0x0. Discovered this through a glamor bug, and confirmed it does indeed break a good number of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888 Fixes: `8e7893eb53` ("nvc0: add support for BGRA8 images") Signed-off-by: Lyude <lyude@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit `245912b684`)	2017-06-14 10:40:22 +01:00
Brian Paul	6348a02e27	xlib: fix glXGetCurrentDisplay() failure glXGetCurrentDisplay() has been broken for years and nobody noticed until recently. This change adds a new XMesaGetCurrentDisplay() that the GLX emulation API can call, just as we did for glXGetCurrentContext(). Tested by hacking glxgears to call glXGetCurrentContext() before and after glXMakeCurrent() to verify the return value is NULL beforehand and the same as the opened display afterward. Also tested by Tom Hudson with his tests programs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100988 Cc: mesa-stable@lists.freedesktop.org Tested-by: Tom Hudson <tom.hudson.phd@gmail.com> Signed-off-by: Brian Paul <brianp@vmware.com> (cherry picked from commit `c6ba85a8c0`)	2017-06-14 10:40:22 +01:00
Jose Fonseca	c24bdf046e	automake: Link all libGL.so variants with -Bsymbolic. We were linking src/glx with -Bsymbolic, but not the classic/gallium X11 libGL.so. But it's always a good idea to build all libGL.so and all DRI drivers with -Bsymbolic, otherwise they might resolve symbols from the 3rd party application executable or shared libraries, which is _never_ what we want. In particular, this can happen when intercepting OpenGL calls with apitrace, before `63194b2573` Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (cherry picked from commit `ce5e83b8a0`)	2017-06-14 10:40:22 +01:00
Chad Versace	15b5e5996a	i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer() This function never occurs in the callchain of a GL function. It occurs only in the callchain of eglCreate*Surface and the analogous paths for GLX. Therefore, even if a thread does have a bound GL context, emitting a GL error here is wrong. A misplaced GL error, when no GL call is made, can confuse clients. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit `9d996e94fb`) [Emil Velikov: resolve trivial conflicts] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/mesa/drivers/dri/i965/intel_fbo.c	2017-06-14 10:39:50 +01:00
Lucas Stach	8cfaa8ad66	etnaviv: always do cpu_fini in transfer_unmap The cpu_fini() call pushes the buffer back into the GPU domain, which needs to be done for all buffers, not just the ones with CPU written content. The etnaviv kernel driver currently doesn't validate this, but may start to do so at a later point in time. If there is a temporary resource the fini needs to happen before the RS uses this one as the source for the upload. Also remove an invalid comment about flushing CPU caches, cpu_fini takes care of everything involved in this. Fixes: `c9e8b49b88` ("etnaviv: gallium driver for Vivante GPUs") Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com> (cherry picked from commit `cab5996c26`)	2017-06-14 09:49:45 +01:00
Juan A. Suarez Romero	4908b1e909	docs: add sha256 checksums for 17.1.2 Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>	2017-06-05 21:15:43 +00:00
@@ -1 +1 @@
 .1.2
 .1.3