docs: Add 18.1.9 release notes

Bump version to 18.1.9
radv: Fix driver UUID SHA1 init.
2018-09-24 08:43:25 -07:00 · 2018-09-21 09:02:55 -07:00 · 2018-09-20 14:53:59 -07:00 · 2018-09-20 13:30:54 -07:00 · 2018-09-20 13:29:41 -07:00 · 2018-09-20 13:29:40 -07:00
46 changed files with 545 additions and 101 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-18.1.8
+18.1.9
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -70,6 +70,21 @@ a4a104fc81e93555899050efac23c3cd6ba762ab
 4ffb575da59fd3aece02734ca4fd3212d5002d55
 8c048af5890d43578ca41eb9dcfa60cb9cc3fc9c
 c92a463d2341dd7893dd8b54775930ed9be72ac0
+ea1e50cc166ae855f9fa91ca6a4f944123298e4e
+f73f748323ef5a421ffd8fa0f02afd9627e31023
+d4e52281aa9c1acc92619736da8b67d8c02ce380
+a5f35aa742c3f1e2fae6a6c2fb53f92822f0cb70
+f6e09db2e613c215257b80f40957d580165b5ddf
+d4bf954fe61ec231be2bfa5e059f0fb7f6150bd1
+abdf396cbeaec2bfe9da2fd773d42fa3022ca8b5
+b9f6521157ab55073eec528cacc1f3b567e49503
+aa3020592964344c7032396d159e4ab2df743587
+063264db5be2941746fa58f164cdc803362753a9
+748f4cce183007587a6688ef25ad5f9dbea5c33c
+9de062ef207c6062d1fabb70209f4bbc9dc4732d
+7d1d1208c2b38890fe065b6431ef2e3b7166bae4
+0796c3934ebfe3448acf2d63f478f51c08e33046
+864c780566b8782c4fc69b4337db768223717bd8

 # These have more than one fixes tag and generate a warning
 #
@@ -96,3 +111,19 @@ a72dbc461bdb7714656e62cd8f4b00a404c2e6e0
 # This requires a much more significant patch not present in 18.1
 #
 4dc244eb447b1fa4e39d67a58328ed774395c901
+
+# This patches were dropped since they only fix developer tools, which aren't
+# built by default and should be of no use to end users or distros
+#
+97fcccb25ed5f55139c03ebc1c71742f0f25f683
+4aec44c0d9c4c0649c362199fac97efe0a3b38a4
+
+# This patch was reverted on master shortly after merging.
+#
+90819abb56f6b1a0cd4946b13b6caf24fb46e500
+
+# These were supreceeded by patches backported to 18.1
+#
+3341429d74099b436c3824164837eebd47029ded
+9158e0bd82ffdad4baf46221bccbbb3fe4764c11
+cc3b99bb48769ccd018b781338b548306af5046b
--- a/docs/relnotes/18.1.8.html
+++ b/docs/relnotes/18.1.8.html
@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+8ec62f215dd1bb3910987f9941c6fc31632a0874e618815cf1e8e29445c86e0a  mesa-18.1.8.tar.gz
+bd1be67fe9c73b517765264ac28911c84144682d28dbff140e1c2deb2f44c21b  mesa-18.1.8.tar.xz
 </pre>


--- a/docs/relnotes/18.1.9.html
+++ b/docs/relnotes/18.1.9.html
@@ -0,0 +1,177 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.8 Release Notes / September 24 2018</h1>
+
+<p>
+Mesa 18.1.9 is a bug fix release which fixes bugs found since the 18.1.8 release.
+</p>
+<p>
+Mesa 18.1.9 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103241">Bug 103241</a> - Anv crashes when using 64-bit vertex inputs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104926">Bug 104926</a> - swrast: Mesa 17.3.3 produces:  HW cursor for format 875713089 not supported</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107280">Bug 107280</a> - [DXVK] Batman: Arkham City with tessellation enabled hangs on SKL GT4</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107772">Bug 107772</a> - Mesa preprocessor matches if(def)s &amp; endifs incorrectly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107779">Bug 107779</a> - Access violation with some games</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107810">Bug 107810</a> - The 'va_end' call is missed after 'va_copy' in 'util_vsnprintf' function under windows</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Andrii Simiklit (4):</p>
+<ul>
+  <li>apple/glx/log: added missing va_end() after va_copy()</li>
+  <li>mesa/util: don't use the same 'va_list' instance twice</li>
+  <li>mesa/util: don't ignore NULL returned from 'malloc'</li>
+  <li>mesa/util: add missing va_end() after va_copy()</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (4):</p>
+<ul>
+  <li>radv: Use build ID if available for cache UUID.</li>
+  <li>radv: Only allow 16 user SGPRs for compute on GFX9+.</li>
+  <li>radv: Set the user SGPR MSB for Vega.</li>
+  <li>radv: Fix driver UUID SHA1 init.</li>
+</ul>
+
+<p>Christopher Egert (1):</p>
+<ul>
+  <li>radeon: fix ColorMask</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>virgl: don't send a shader create with no data. (v2)</li>
+</ul>
+
+<p>Dylan Baker (10):</p>
+<ul>
+  <li>docs/relnotes: Add sha256 sums for mesa 18.1.8</li>
+  <li>cherry-ignore: Add additional 18.2 patch</li>
+  <li>meson: Print a message about why a libdrm version was selected</li>
+  <li>cherry-ignore: add another 18.2 patch</li>
+  <li>cherry-ignore: Add patches that don't apply cleanly and are for developer tools</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: add 18.2 patchs</li>
+  <li>cherry-ignore: add a patch that was reverted on master</li>
+  <li>cherry-ignore: one final update</li>
+  <li>Bump version to 18.1.9</li>
+</ul>
+
+<p>Erik Faye-Lund (2):</p>
+<ul>
+  <li>winsys/virgl: avoid unintended behavior</li>
+  <li>virgl: adjust strides when mapping temp-resources</li>
+</ul>
+
+<p>Gert Wollny (1):</p>
+<ul>
+  <li>winsys/virgl: correct resource and handle allocation (v2)</li>
+</ul>
+
+<p>Jason Ekstrand (6):</p>
+<ul>
+  <li>anv/pipeline: Only consider double elements which actually exist</li>
+  <li>i965: Workaround the gen9 hw astc5x5 sampler bug</li>
+  <li>anv: Re-emit vertex buffers when the pipeline changes</li>
+  <li>anv: Disable the vertex cache when tessellating on SKL GT4</li>
+  <li>anv: Clamp scissors to the framebuffer boundary</li>
+  <li>anv/query: Write both dwords in emit_zero_queries</li>
+</ul>
+
+<p>Josh Pieper (1):</p>
+<ul>
+  <li>st/mesa: Validate the result of pipe_transfer_map in make_texture (v2)</li>
+</ul>
+
+<p>Kenneth Feng (1):</p>
+<ul>
+  <li>amd: Add Picasso device id</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+  <li>st/mesa: help fix stencil border color for GL_DEPTH_STENCIL textures</li>
+  <li>radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI</li>
+  <li>r600: fix HTILE for NPOT textures with mipmapping</li>
+  <li>radeonsi: fix printing a BO list into ddebug reports</li>
+</ul>
+
+<p>Mathias Fröhlich (1):</p>
+<ul>
+  <li>tnl: Fix green gun regression in xonotic.</li>
+</ul>
+
+<p>Mauro Rossi (3):</p>
+<ul>
+  <li>android: broadcom/genxml: fix collision with intel/genxml header-gen macro</li>
+  <li>android: broadcom/cle: add gallium include path</li>
+  <li>android: broadcom/cle: export the broadcom top level path headers</li>
+</ul>
+
+<p>Michal Srb (1):</p>
+<ul>
+  <li>st/dri: don't set queryDmaBufFormats/queryDmaBufModifiers if the driver does not implement it</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+  <li>loader/dri3: Only wait for back buffer fences in dri3_get_buffer</li>
+</ul>
+
+<p>Pierre Moreau (1):</p>
+<ul>
+  <li>nvir: Always split 64-bit IMAD/IMUL operations</li>
+</ul>
+
+<p>Sergii Romantsov (1):</p>
+<ul>
+  <li>intel: compiler option msse2 and mstackrealign</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>glsl: fixer lexer for unreachable defines</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -236,3 +236,4 @@ CHIPSET(0x69A3, VEGA12)
 CHIPSET(0x69AF, VEGA12)

 CHIPSET(0x15DD, RAVEN)
+CHIPSET(0x15D8, RAVEN)
--- a/meson.build
+++ b/meson.build
@@ -1068,12 +1068,17 @@ _libdrm_checks = [

 # Loop over the enables versions and get the highest libdrm requirement for all
 # active drivers.
+_drm_blame = ''
 foreach d : _libdrm_checks
  ver = get_variable('_drm_@0@_ver'.format(d[0]))
  if d[1] and ver.version_compare('>' + _drm_ver)
    _drm_ver = ver
+    _drm_blame = d[0]
  endif
 endforeach
+if _drm_blame != ''
+  message('libdrm @0@ needed because @1@ has the highest requirement'.format(_drm_ver, _drm_blame))
+endif

 # Then get each libdrm module
 foreach d : _libdrm_checks
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -45,22 +45,51 @@
 #include "sid.h"
 #include "gfx9d.h"
 #include "addrlib/gfx9/chip/gfx9_enum.h"
+#include "util/build_id.h"
 #include "util/debug.h"
+#include "util/mesa-sha1.h"
+
+static bool
+radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
+{
+	uint32_t timestamp;
+
+#ifdef HAVE_DL_ITERATE_PHDR
+	const struct build_id_note *note = NULL;
+	if ((note = build_id_find_nhdr_for_addr(ptr))) {
+		_mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
+	} else
+#endif
+	if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
+		if (!timestamp) {
+			fprintf(stderr, "radv: The provided filesystem timestamp for the cache is bogus!\n");
+		}
+
+		_mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
+	} else
+		return false;
+	return true;
+}

 static int
 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
 {
-	uint32_t mesa_timestamp, llvm_timestamp;
-	uint16_t f = family;
+	struct mesa_sha1 ctx;
+	unsigned char sha1[20];
+	unsigned ptr_size = sizeof(void*);
+
 	memset(uuid, 0, VK_UUID_SIZE);
-	if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
-	    !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
+	_mesa_sha1_init(&ctx);
+
+	if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
+	    !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
 		return -1;

-	memcpy(uuid, &mesa_timestamp, 4);
-	memcpy((char*)uuid + 4, &llvm_timestamp, 4);
-	memcpy((char*)uuid + 8, &f, 2);
-	snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void *));
+	_mesa_sha1_update(&ctx, &family, sizeof(family));
+	_mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
+	_mesa_sha1_final(&ctx, sha1);
+
+	memcpy(uuid, sha1, VK_UUID_SIZE);
 	return 0;
 }

--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -583,7 +583,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
 	if (ctx->shader_info->info.loads_push_constants)
 		user_sgpr_info->sgpr_count += 2;

-	uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
+	uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
 	uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;

 	if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -379,7 +379,8 @@ radv_fill_shader_variant(struct radv_device *device,

 	variant->code_size = binary->code_size;
 	variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
-			S_00B12C_SCRATCH_EN(scratch_enabled);
+			 S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
+			 S_00B12C_SCRATCH_EN(scratch_enabled);

 	variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 		S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
--- a/src/broadcom/Android.cle.mk
+++ b/src/broadcom/Android.cle.mk
@@ -29,6 +29,10 @@ LOCAL_SRC_FILES := $(BROADCOM_DECODER_FILES)

 LOCAL_STATIC_LIBRARIES := libmesa_broadcom_genxml

+LOCAL_C_INCLUDES += $(MESA_TOP)/src/gallium/include
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_PATH)
+
 LOCAL_SHARED_LIBRARIES := libexpat libz

 include $(MESA_COMMON_MK)
--- a/src/broadcom/Android.genxml.mk
+++ b/src/broadcom/Android.genxml.mk
@@ -39,7 +39,7 @@ $(intermediates)/dummy.c:
 # This is the list of auto-generated files headers
 LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/broadcom/, $(BROADCOM_GENXML_GENERATED_FILES))

-define header-gen
+define pack-header-gen
 	@mkdir -p $(dir $@)
 	@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
 	$(hide) $(PRIVATE_SCRIPT) $(PRIVATE_SCRIPT_FLAGS) $(PRIVATE_XML) > $@
@@ -48,22 +48,22 @@ endef
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v21.xml
 $(intermediates)/broadcom/cle/v3d_packet_v21_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v21.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v33.xml
 $(intermediates)/broadcom/cle/v3d_packet_v33_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v33.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v41.xml
 $(intermediates)/broadcom/cle/v3d_packet_v41_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v41.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/cle/gen_pack_header.py
 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: PRIVATE_XML := $(LOCAL_PATH)/cle/v3d_packet_v42.xml
 $(intermediates)/broadcom/cle/v3d_packet_v42_pack.h: $(LOCAL_PATH)/cle/v3d_packet_v42.xml $(LOCAL_PATH)/cle/gen_pack_header.py
-	$(call header-gen)
+	$(call pack-header-gen)

 $(intermediates)/broadcom/cle/v3d_xml.h: $(addprefix $(MESA_TOP)/src/broadcom/,$(BROADCOM_GENXML_XML_FILES)) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
 	@mkdir -p $(dir $@)
--- a/src/compiler/glsl/glcpp/glcpp-lex.l
+++ b/src/compiler/glsl/glcpp/glcpp-lex.l
@@ -289,6 +289,7 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
         * token. */
 	if (parser->first_non_space_token_this_line) {
 		BEGIN HASH;
+		yyextra->in_define = false;
 	}

 	RETURN_TOKEN_NEVER_SKIP (HASH_TOKEN);
@@ -336,43 +337,55 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
 	/* For the pre-processor directives, we return these tokens
 	 * even when we are otherwise skipping. */
 <HASH>ifdef {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IFDEF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IFDEF);
+	}
 }

 <HASH>ifndef {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IFNDEF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IFNDEF);
+	}
 }

 <HASH>if/[^_a-zA-Z0-9] {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (IF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (IF);
+	}
 }

 <HASH>elif/[^_a-zA-Z0-9] {
-	BEGIN INITIAL;
-	yyextra->lexing_directive = 1;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ELIF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->lexing_directive = 1;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ELIF);
+	}
 }

 <HASH>else {
-	BEGIN INITIAL;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ELSE);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ELSE);
+	}
 }

 <HASH>endif {
-	BEGIN INITIAL;
-	yyextra->space_tokens = 0;
-	RETURN_TOKEN_NEVER_SKIP (ENDIF);
+	if (!yyextra->in_define) {
+		BEGIN INITIAL;
+		yyextra->space_tokens = 0;
+		RETURN_TOKEN_NEVER_SKIP (ENDIF);
+	}
 }

 <HASH>error[^\r\n]* {
@@ -399,7 +412,8 @@ HEXADECIMAL_INTEGER	0[xX][0-9a-fA-F]+[uU]?
 	 *	  and not whitespace). This will generate an error.
 	 */
 <HASH>define{HSPACE}* {
-	if (! parser->skipping) {
+	yyextra->in_define = true;
+	if (!parser->skipping) {
 		BEGIN DEFINE;
 		yyextra->space_tokens = 0;
 		RETURN_TOKEN (DEFINE_TOKEN);
--- a/src/compiler/glsl/glcpp/glcpp.h
+++ b/src/compiler/glsl/glcpp/glcpp.h
@@ -197,6 +197,7 @@ struct glcpp_parser {
 	int first_non_space_token_this_line;
 	int newline_as_space;
 	int in_control_line;
+	bool in_define;
 	int paren_count;
 	int commented_newlines;
 	skip_node_t *skip_stack;
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3797,7 +3797,7 @@ Program::optimizeSSA(int level)
   RUN_PASS(2, AlgebraicOpt, run);
   RUN_PASS(2, ModifierFolding, run); // before load propagation -> less checks
   RUN_PASS(1, ConstantFolding, foldAll);
-   RUN_PASS(1, Split64BitOpPreRA, run);
+   RUN_PASS(0, Split64BitOpPreRA, run);
   RUN_PASS(1, LoadPropagation, run);
   RUN_PASS(1, IndirectPropagation, run);
   RUN_PASS(2, MemoryOpt, run);
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -774,8 +774,8 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 		return;
 	}

-	width = align(rtex->resource.b.b.width0, cl_width * 8);
-	height = align(rtex->resource.b.b.height0, cl_height * 8);
+	width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+	height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);

 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -134,12 +134,13 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,

 	if (ctx->current_saved_cs) {
 		si_trace_emit(ctx);
-		si_log_hw_flush(ctx);

 		/* Save the IB for debug contexts. */
 		si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 		ctx->current_saved_cs->flushed = true;
 		ctx->current_saved_cs->time_flush = os_time_get_nano();
+
+		si_log_hw_flush(ctx);
 	}

 	/* Flush the CS. */
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1019,8 +1019,8 @@ static void si_texture_get_htile_size(struct si_screen *sscreen,
 		return;
 	}

-	width = align(rtex->resource.b.b.width0, cl_width * 8);
-	height = align(rtex->resource.b.b.height0, cl_height * 8);
+	width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+	height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);

 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -283,7 +283,7 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
   while (left_bytes) {
      uint32_t length, offlen;
      int hdr_len = base_hdr_size + (first_pass ? strm_hdr_size : 0);
-      if (ctx->cbuf->cdw + hdr_len + 1 > VIRGL_MAX_CMDBUF_DWORDS)
+      if (ctx->cbuf->cdw + hdr_len + 1 >= VIRGL_MAX_CMDBUF_DWORDS)
         ctx->base.flush(&ctx->base, NULL, 0);

      thispass = (VIRGL_MAX_CMDBUF_DWORDS - ctx->cbuf->cdw - hdr_len - 1) * 4;
--- a/src/gallium/drivers/virgl/virgl_texture.c
+++ b/src/gallium/drivers/virgl/virgl_texture.c
@@ -177,6 +177,8 @@ static void *virgl_texture_transfer_map(struct pipe_context *ctx,
      /* we want to do a resolve blit into the temporary */
      hw_res = trans->resolve_tmp->hw_res;
      offset = 0;
+      trans->base.stride = ((struct virgl_texture*)trans->resolve_tmp)->stride[level];
+      trans->base.layer_stride = trans->base.stride * nblocksy;
   } else {
      offset = vrend_get_tex_image_offset(vtex, level, box->z);

--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -2215,8 +2215,10 @@ dri_kms_init_screen(__DRIscreen * sPriv)
      dri2ImageExtension.createImageFromFds = dri2_from_fds;
      dri2ImageExtension.createImageFromDmaBufs = dri2_from_dma_bufs;
      dri2ImageExtension.createImageFromDmaBufs2 = dri2_from_dma_bufs2;
-      dri2ImageExtension.queryDmaBufFormats = dri2_query_dma_buf_formats;
-      dri2ImageExtension.queryDmaBufModifiers = dri2_query_dma_buf_modifiers;
+      if (pscreen->query_dmabuf_modifiers) {
+         dri2ImageExtension.queryDmaBufFormats = dri2_query_dma_buf_formats;
+         dri2ImageExtension.queryDmaBufModifiers = dri2_query_dma_buf_modifiers;
+      }
   }

   sPriv->extensions = dri_screen_extensions;
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -313,7 +313,7 @@ virgl_drm_winsys_resource_cache_create(struct virgl_winsys *qws,
   struct virgl_hw_res *res, *curr_res;
   struct list_head *curr, *next;
   int64_t now;
-   int ret;
+   int ret = 0;

   /* only store binds for vertex/index/const buffers */
   if (bind != VIRGL_BIND_CONSTANT_BUFFER && bind != VIRGL_BIND_INDEX_BUFFER &&
@@ -617,13 +617,26 @@ static void virgl_drm_add_res(struct virgl_drm_winsys *qdws,
 {
   unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);

-   if (cbuf->cres > cbuf->nres) {
-      cbuf->nres += 256;
-      cbuf->res_bo = realloc(cbuf->res_bo, cbuf->nres * sizeof(struct virgl_hw_buf*));
-      if (!cbuf->res_bo) {
-          fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, cbuf->nres);
+   if (cbuf->cres >= cbuf->nres) {
+      unsigned new_nres = cbuf->nres + 256;
+      void *new_ptr = REALLOC(cbuf->res_bo,
+                              cbuf->nres * sizeof(struct virgl_hw_buf*),
+                              new_nres * sizeof(struct virgl_hw_buf*));
+      if (!new_ptr) {
+          fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, new_nres);
          return;
      }
+      cbuf->res_bo = new_ptr;
+
+      new_ptr = REALLOC(cbuf->res_hlist,
+                        cbuf->nres * sizeof(uint32_t),
+                        new_nres * sizeof(uint32_t));
+      if (!new_ptr) {
+          fprintf(stderr,"failure to add hlist relocation %d, %d\n", cbuf->cres, cbuf->nres);
+          return;
+      }
+      cbuf->res_hlist = new_ptr;
+      cbuf->nres = new_nres;
   }

   cbuf->res_bo[cbuf->cres] = NULL;
--- a/src/glx/apple/apple_glx_log.c
+++ b/src/glx/apple/apple_glx_log.c
@@ -97,6 +97,7 @@ void _apple_glx_vlog(int level, const char *file, const char *function,
        fprintf(stderr, "%-9s %24s:%-4d %s(%"PRIu64"): ",
                _asl_level_string(level), file, line, function, thread);
        vfprintf(stderr, fmt, args2);
+        va_end(args2);
    }

    msg = asl_new(ASL_TYPE_MSG);
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -104,7 +104,7 @@ noinst_LTLIBRARIES += $(VULKAN_PER_GEN_LIBS)

 VULKAN_CFLAGS = \
 	$(AM_CFLAGS) \
-	-msse2
+	-msse2 -mstackrealign

 VULKAN_CPPFLAGS = \
 	-I$(top_srcdir)/src/compiler \
--- a/src/intel/meson.build
+++ b/src/intel/meson.build
@@ -18,6 +18,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.

+c_sse2_args = ['-msse2', '-mstackrealign']
 inc_intel = include_directories('.')

 subdir('blorp')
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -48,6 +48,7 @@ clamp_int64(int64_t x, int64_t min, int64_t max)
 void
 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 {
+   struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
   uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
   const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
   struct anv_state scissor_state =
@@ -73,8 +74,8 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
         /* Do this math using int64_t so overflow gets clamped correctly. */
         .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
         .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
-         .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
-         .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
+         .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, fb->height - 1),
+         .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, fb->width - 1)
      };

      if (s->extent.width <= 0 || s->extent.height <= 0) {
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2475,6 +2475,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
   uint32_t *p;

   uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
+   if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE)
+      vb_emit |= pipeline->vb_used;

   assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);

@@ -2599,7 +2601,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
                                          pipeline->depth_clamp_enable);
   }

-   if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
+   if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_SCISSOR |
+                                      ANV_CMD_DIRTY_RENDER_TARGETS))
      gen7_cmd_buffer_emit_scissor(cmd_buffer);

   genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -91,7 +91,8 @@ emit_vertex_input(struct anv_pipeline *pipeline,

   /* Pull inputs_read out of the VS prog data */
   const uint64_t inputs_read = vs_prog_data->inputs_read;
-   const uint64_t double_inputs_read = vs_prog_data->double_inputs_read;
+   const uint64_t double_inputs_read =
+      vs_prog_data->double_inputs_read & inputs_read;
   assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
   const uint32_t elements = inputs_read >> VERT_ATTRIB_GENERIC0;
   const uint32_t elements_double = double_inputs_read >> VERT_ATTRIB_GENERIC0;
@@ -1172,7 +1173,28 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
      vs.IllegalOpcodeExceptionEnable = false;
      vs.SoftwareExceptionEnable    = false;
      vs.MaximumNumberofThreads     = devinfo->max_vs_threads - 1;
-      vs.VertexCacheDisable         = false;
+
+      if (GEN_GEN == 9 && devinfo->gt == 4 &&
+          anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
+         /* On Sky Lake GT4, we have experienced some hangs related to the VS
+          * cache and tessellation.  It is unknown exactly what is happening
+          * but the Haswell docs for the "VS Reference Count Full Force Miss
+          * Enable" field of the "Thread Mode" register refer to a HSW bug in
+          * which the VUE handle reference count would overflow resulting in
+          * internal reference counting bugs.  My (Jason's) best guess is that
+          * this bug cropped back up on SKL GT4 when we suddenly had more
+          * threads in play than any previous gen9 hardware.
+          *
+          * What we do know for sure is that setting this bit when
+          * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
+          * City when playing with DXVK (https://bugs.freedesktop.org/107280).
+          * Disabling the vertex cache with tessellation shaders should only
+          * have a minor performance impact as the tessellation shaders are
+          * likely generating and processing far more geometry than the vertex
+          * stage.
+          */
+         vs.VertexCacheDisable = true;
+      }

      vs.VertexURBEntryReadLength      = vs_prog_data->base.urb_read_length;
      vs.VertexURBEntryReadOffset      = 0;
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -341,6 +341,11 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
            sdi.Address.offset = slot_offset + j * sizeof(uint64_t);
            sdi.ImmediateData = 0ull;
         }
+         anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+            sdi.Address.bo = &pool->bo;
+            sdi.Address.offset = slot_offset + j * sizeof(uint64_t) + 4;
+            sdi.ImmediateData = 0ull;
+         }
      }
      emit_query_availability(cmd_buffer, &pool->bo, slot_offset);
   }
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -111,7 +111,7 @@ foreach g : [['70', ['gen7_cmd_buffer.c']], ['75', ['gen7_cmd_buffer.c']],
      inc_vulkan_wsi,
    ],
    c_args : [
-      c_vis_args, no_override_init_args, '-msse2',
+      c_vis_args, no_override_init_args, c_sse2_args,
      '-DGEN_VERSIONx10=@0@'.format(_gen),
    ],
    dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers],
@@ -155,7 +155,7 @@ anv_deps = [
 anv_flags = [
  c_vis_args,
  no_override_init_args,
-  '-msse2',
+  c_sse2_args,
 ]

 if with_platform_x11
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1736,7 +1736,9 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
      buffer = new_buffer;
      draw->buffers[buf_id] = buffer;
   }
-   dri3_fence_await(draw->conn, draw, buffer);
+
+   if (buffer_type == loader_dri3_buffer_back)
+      dri3_fence_await(draw->conn, draw, buffer);

   /*
    * Do we need to preserve the content of a previous buffer?
--- a/src/mesa/Android.libmesa_dricore.mk
+++ b/src/mesa/Android.libmesa_dricore.mk
@@ -49,7 +49,7 @@ ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
 LOCAL_WHOLE_STATIC_LIBRARIES := \
 	libmesa_sse41
 LOCAL_CFLAGS := \
-	-msse4.1 \
+	-msse4.1 -mstackrealign \
       -DUSE_SSE41
 endif

--- a/src/mesa/Android.libmesa_sse41.mk
+++ b/src/mesa/Android.libmesa_sse41.mk
@@ -34,7 +34,7 @@ LOCAL_SRC_FILES += \
 	$(X86_SSE41_FILES)

 LOCAL_CFLAGS := \
-	-msse4.1
+	-msse4.1 -mstackrealign

 LOCAL_C_INCLUDES := \
 	$(MESA_TOP)/src/mapi \
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -44,7 +44,7 @@ AM_CFLAGS = \
 	$(WNO_OVERRIDE_INIT) \
 	$(LIBDRM_CFLAGS) \
 	$(VALGRIND_CFLAGS) \
-	-msse2
+	-msse2 -mstackrealign

 AM_CXXFLAGS = $(AM_CFLAGS)

--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -194,6 +194,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
   assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
          (surf->aux_addr.buffer == NULL));

+   if (!is_render_target && brw->screen->devinfo.gen == 9)
+      gen9_apply_single_tex_astc5x5_wa(brw, mt->format, surf->aux_usage);
+
   /* ISL wants real levels, not offset ones. */
   *level -= mt->first_level;
 }
@@ -305,7 +308,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   enum isl_format src_isl_format =
      brw_blorp_to_isl_format(brw, src_format, false);
   enum isl_aux_usage src_aux_usage =
-      intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format);
+      intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format,
+                                      0 /* The astc5x5 WA isn't needed */);
   /* We do format workarounds for some depth formats so we can't reliably
    * sample with HiZ.  One of these days, we should fix that.
    */
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -168,6 +168,11 @@ enum brw_cache_id {
   BRW_MAX_CACHE
 };

+enum gen9_astc5x5_wa_tex_type {
+   GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
+   GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
+};
+
 enum brw_state_id {
   /* brw_cache_ids must come first - see brw_program_cache.c */
   BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
@@ -1312,6 +1317,8 @@ struct brw_context
    */
   enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS];

+   enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask;
+
   __DRIcontext *driContext;
   struct intel_screen *screen;
 };
@@ -1336,6 +1343,10 @@ void intel_update_renderbuffers(__DRIcontext *context,
                                __DRIdrawable *drawable);
 void intel_prepare_render(struct brw_context *brw);

+void gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
+                                      mesa_format format,
+                                      enum isl_aux_usage aux_usage);
+
 void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
                                bool *draw_aux_buffer_disabled);

--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -376,6 +376,68 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
   return found;
 }

+/** Implement the ASTC 5x5 sampler workaround
+ *
+ * Gen9 sampling hardware has a bug where an ASTC 5x5 compressed surface
+ * cannot live in the sampler cache at the same time as an aux compressed
+ * surface.  In order to work around the bug we have to stall rendering with a
+ * CS and pixel scoreboard stall (implicit in the CS stall) and invalidate the
+ * texture cache whenever one of ASTC 5x5 or aux compressed may be in the
+ * sampler cache and we're about to render with something which samples from
+ * the other.
+ *
+ * In the case of a single shader which textures from both ASTC 5x5 and
+ * a texture which is CCS or HiZ compressed, we have to resolve the aux
+ * compressed texture prior to rendering.  This second part is handled in
+ * brw_predraw_resolve_inputs() below.
+ *
+ * We have observed this issue to affect CCS and HiZ sampling but whether or
+ * not it also affects MCS is unknown.  Because MCS has no concept of a
+ * resolve (and doing one would be stupid expensive), we choose to simply
+ * ignore the possibility and hope for the best.
+ */
+static void
+gen9_apply_astc5x5_wa_flush(struct brw_context *brw,
+                            enum gen9_astc5x5_wa_tex_type curr_mask)
+{
+   assert(brw->screen->devinfo.gen == 9);
+
+   if (((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+        (curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX)) ||
+       ((brw->gen9_astc5x5_wa_tex_mask & GEN9_ASTC5X5_WA_TEX_TYPE_AUX) &&
+        (curr_mask & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5))) {
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
+   }
+
+   brw->gen9_astc5x5_wa_tex_mask = curr_mask;
+}
+
+static enum gen9_astc5x5_wa_tex_type
+gen9_astc5x5_wa_bits(mesa_format format, enum isl_aux_usage aux_usage)
+{
+   if (aux_usage != ISL_AUX_USAGE_NONE &&
+       aux_usage != ISL_AUX_USAGE_MCS)
+      return GEN9_ASTC5X5_WA_TEX_TYPE_AUX;
+
+   if (format == MESA_FORMAT_RGBA_ASTC_5x5 ||
+       format == MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5)
+      return GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5;
+
+   return 0;
+}
+
+/* Helper for the gen9 ASTC 5x5 workaround.  This version exists for BLORP's
+ * use-cases where only a single texture is bound.
+ */
+void
+gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
+                                 mesa_format format,
+                                 enum isl_aux_usage aux_usage)
+{
+   gen9_apply_astc5x5_wa_flush(brw, gen9_astc5x5_wa_bits(format, aux_usage));
+}
+
 static void
 mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
                           const struct gl_program *prog)
@@ -415,8 +477,30 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
      mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
   }

-   /* Resolve depth buffer and render cache of each enabled texture. */
   int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
+
+   enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits = 0;
+   if (brw->screen->devinfo.gen == 9) {
+      /* In order to properly implement the ASTC 5x5 workaround for an
+       * arbitrary draw or dispatch call, we have to walk the entire list of
+       * textures looking for ASTC 5x5.  If there is any ASTC 5x5 in this draw
+       * call, all aux compressed textures must be resolved and have aux
+       * compression disabled while sampling.
+       */
+      for (int i = 0; i <= maxEnabledUnit; i++) {
+         if (!ctx->Texture.Unit[i]._Current)
+            continue;
+         tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
+         if (!tex_obj || !tex_obj->mt)
+            continue;
+
+         astc5x5_wa_bits |= gen9_astc5x5_wa_bits(tex_obj->_Format,
+                                                 tex_obj->mt->aux_usage);
+      }
+      gen9_apply_astc5x5_wa_flush(brw, astc5x5_wa_bits);
+   }
+
+   /* Resolve depth buffer and render cache of each enabled texture. */
   for (int i = 0; i <= maxEnabledUnit; i++) {
      if (!ctx->Texture.Unit[i]._Current)
 	 continue;
@@ -450,7 +534,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,

      intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
                                    min_level, num_levels,
-                                    min_layer, num_layers);
+                                    min_layer, num_layers,
+                                    astc5x5_wa_bits);

      /* If any programs are using it with texelFetch, we may need to also do
       * a prepare with an sRGB format to ensure texelFetch works "properly".
@@ -461,7 +546,8 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
         if (txf_format != view_format) {
            intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
                                          min_level, num_levels,
-                                          min_layer, num_layers);
+                                          min_layer, num_layers,
+                                          astc5x5_wa_bits);
         }
      }

@@ -533,7 +619,8 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
         if (irb) {
            intel_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
                                          irb->mt_level, 1,
-                                          irb->mt_layer, irb->layer_count);
+                                          irb->mt_layer, irb->layer_count,
+                                          brw->gen9_astc5x5_wa_tex_mask);
         }
      }
   }
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -601,7 +601,8 @@ static void brw_update_texture_surface(struct gl_context *ctx,
         view.usage |= ISL_SURF_USAGE_CUBE_BIT;

      enum isl_aux_usage aux_usage =
-         intel_miptree_texture_aux_usage(brw, mt, format);
+         intel_miptree_texture_aux_usage(brw, mt, format,
+                                         brw->gen9_astc5x5_wa_tex_mask);

      brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
                             surf_offset, surf_index,
@@ -1105,7 +1106,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
            };

            enum isl_aux_usage aux_usage =
-               intel_miptree_texture_aux_usage(brw, irb->mt, format);
+               intel_miptree_texture_aux_usage(brw, irb->mt, format,
+                                               brw->gen9_astc5x5_wa_tex_mask);
            if (brw->draw_aux_usage[i] == ISL_AUX_USAGE_NONE)
               aux_usage = ISL_AUX_USAGE_NONE;

--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2619,8 +2619,19 @@ can_texture_with_ccs(struct brw_context *brw,
 enum isl_aux_usage
 intel_miptree_texture_aux_usage(struct brw_context *brw,
                                struct intel_mipmap_tree *mt,
-                                enum isl_format view_format)
+                                enum isl_format view_format,
+                                enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
 {
+   assert(brw->screen->devinfo.gen == 9 || astc5x5_wa_bits == 0);
+
+   /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
+    * CCS or HiZ compressed textures.  See gen9_apply_astc5x5_wa_flush() for
+    * details.
+    */
+   if ((astc5x5_wa_bits & GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5) &&
+       mt->aux_usage != ISL_AUX_USAGE_MCS)
+      return ISL_AUX_USAGE_NONE;
+
   switch (mt->aux_usage) {
   case ISL_AUX_USAGE_HIZ:
      if (intel_miptree_sample_with_hiz(brw, mt))
@@ -2678,10 +2689,12 @@ intel_miptree_prepare_texture(struct brw_context *brw,
                              struct intel_mipmap_tree *mt,
                              enum isl_format view_format,
                              uint32_t start_level, uint32_t num_levels,
-                              uint32_t start_layer, uint32_t num_layers)
+                              uint32_t start_layer, uint32_t num_layers,
+                              enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits)
 {
   enum isl_aux_usage aux_usage =
-      intel_miptree_texture_aux_usage(brw, mt, view_format);
+      intel_miptree_texture_aux_usage(brw, mt, view_format, astc5x5_wa_bits);
+
   bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;

   /* Clear color is specified as ints or floats and the conversion is done by
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -652,13 +652,15 @@ intel_miptree_access_raw(struct brw_context *brw,
 enum isl_aux_usage
 intel_miptree_texture_aux_usage(struct brw_context *brw,
                                struct intel_mipmap_tree *mt,
-                                enum isl_format view_format);
+                                enum isl_format view_format,
+                                enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
                              struct intel_mipmap_tree *mt,
                              enum isl_format view_format,
                              uint32_t start_level, uint32_t num_levels,
-                              uint32_t start_layer, uint32_t num_layers);
+                              uint32_t start_layer, uint32_t num_layers,
+                              enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits);
 void
 intel_miptree_prepare_image(struct brw_context *brw,
                            struct intel_mipmap_tree *mt);
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -142,7 +142,7 @@ foreach v : ['40', '45', '50', '60', '70', '75', '80', '90', '100', '110']
    ['genX_blorp_exec.c', 'genX_state_upload.c', gen_xml_pack],
    include_directories : [inc_common, inc_intel, inc_dri_common],
    c_args : [
-      c_vis_args, no_override_init_args, '-msse2',
+      c_vis_args, no_override_init_args, c_sse2_args,
      '-DGEN_VERSIONx10=@0@'.format(v),
    ],
    dependencies : [dep_libdrm, idep_nir_headers],
@@ -183,8 +183,8 @@ libi965 = static_library(
  include_directories : [
    inc_common, inc_intel, inc_dri_common, inc_util, inc_drm_uapi,
  ],
-  c_args : [c_vis_args, no_override_init_args, '-msse2'],
-  cpp_args : [cpp_vis_args, '-msse2'],
+  c_args : [c_vis_args, no_override_init_args, c_sse2_args],
+  cpp_args : [cpp_vis_args, c_sse2_args],
  link_with : [
    i965_gen_libs, libintel_common, libintel_dev, libisl, libintel_compiler,
    libblorp,
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -688,10 +688,10 @@ static void r200ColorMask( struct gl_context *ctx,
   if (!rrb)
     return;
   mask = radeonPackColor( rrb->cpp,
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3) );
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3)*0xFF );


   if (!(r && g && b && a))
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -503,10 +503,10 @@ static void radeonColorMask( struct gl_context *ctx,
     return;

   mask = radeonPackColor( rrb->cpp,
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2),
-			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3) );
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2)*0xFF,
+			   GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3)*0xFF );

   if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
      RADEON_STATECHANGE( rmesa, msk );
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -163,6 +163,9 @@ st_convert_sampler(const struct st_context *st,
      const GLboolean is_integer = texobj->_IsIntegerFormat;
      GLenum texBaseFormat = _mesa_base_tex_image(texobj)->_BaseFormat;

+      if (texobj->StencilSampling)
+         texBaseFormat = GL_STENCIL_INDEX;
+
      if (st->apply_texture_swizzle_to_border_color) {
         const struct st_texture_object *stobj = st_texture_object_const(texobj);
         /* XXX: clean that up to not use the sampler view at all */
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -566,7 +566,11 @@ make_texture(struct st_context *st,
      dest = pipe_transfer_map(pipe, pt, 0, 0,
                               PIPE_TRANSFER_WRITE, 0, 0,
                               width, height, &transfer);
-
+      if (!dest) {
+         pipe_resource_reference(&pt, NULL);
+         _mesa_unmap_pbo_source(ctx, unpack);
+         return NULL;
+      }

      /* Put image into texture transfer.
       * Note that the image is actually going to be upside down in
@@ -1173,6 +1177,13 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
      return;
   }

+   /* Put glDrawPixels image into a texture */
+   pt = make_texture(st, width, height, format, type, unpack, pixels);
+   if (!pt) {
+      _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDrawPixels");
+      return;
+   }
+
   /*
    * Get vertex/fragment shaders
    */
@@ -1199,13 +1210,6 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
      st_upload_constants(st, &st->fp->Base);
   }

-   /* Put glDrawPixels image into a texture */
-   pt = make_texture(st, width, height, format, type, unpack, pixels);
-   if (!pt) {
-      _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDrawPixels");
-      return;
-   }
-
   /* create sampler view for the image */
   sv[0] = st_create_texture_sampler_view(st->pipe, pt);
   if (!sv[0]) {
--- a/src/mesa/tnl/t_split_copy.c
+++ b/src/mesa/tnl/t_split_copy.c
@@ -519,7 +519,7 @@ replay_init(struct copy_context *copy)
   for (offset = 0, i = 0; i < copy->nr_varying; i++) {
      const struct gl_vertex_array *src = copy->varying[i].array;
      const struct gl_array_attributes *srcattr = src->VertexAttrib;
-      struct gl_vertex_array *dst = &copy->dstarray[i];
+      struct gl_vertex_array *dst = &copy->dstarray[copy->varying[i].attr];
      struct gl_vertex_buffer_binding *dstbind = &copy->varying[i].dstbinding;
      struct gl_array_attributes *dstattr = &copy->varying[i].dstattribs;

--- a/src/util/u_string.h
+++ b/src/util/u_string.h
@@ -81,6 +81,7 @@ util_vsnprintf(char *str, size_t size, const char *format, va_list ap)
   if (ret < 0) {
      ret = _vscprintf(format, ap_copy);
   }
+   va_end(ap_copy);
   return ret;
 }

@@ -119,14 +120,14 @@ util_vasprintf(char **ret, const char *format, va_list ap)

   /* Compute length of output string first */
   va_copy(ap_copy, ap);
-   int r = util_vsnprintf(NULL, 0, format, ap);
+   int r = util_vsnprintf(NULL, 0, format, ap_copy);
   va_end(ap_copy);

   if (r < 0)
      return -1;

   *ret = (char *) malloc(r + 1);
-   if (!ret)
+   if (!*ret)
      return -1;

   /* Print to buffer */
@@ -1 +1 @@
 .1.8
 .1.9