docs: Add mesa 18.1.7 docs

With the current code, we didn't do the space checks prior
to atomic counter setup emission, but we also didn't add
atomic counters to the space check so we could get a flush
later as well.

These flushes would be bad, and lead to problems with
parallel tests. We have to ensure the atomic counter copy in,
draw emits and counter copy out are kept in the same command
submission unit.

This reworks the code to drop some useless masks, make the
counting separate to the emits, and make the space checker
handle atomic counter space.

[airlied: want this in 18.2]

Fixes: 06993e4ee (r600: add support for hw atomic counters. (v3))
(cherry picked from commit 32529e6084)

.travis.yml

@@ -18,13 +18,11 @@ env:
     - LIBPCIACCESS_VERSION=libpciaccess-0.13.4
     - LIBDRM_VERSION=libdrm-2.4.74
     - XCBPROTO_VERSION=xcb-proto-1.13
-    - RANDRPROTO_VERSION=randrproto-1.3.0
-    - LIBXRANDR_VERSION=libXrandr-1.3.0
     - LIBXCB_VERSION=libxcb-1.13
     - LIBXSHMFENCE_VERSION=libxshmfence-1.2
     - LIBVDPAU_VERSION=libvdpau-1.1
     - LIBVA_VERSION=libva-1.7.0
-    - LIBWAYLAND_VERSION=wayland-1.15.0
+    - LIBWAYLAND_VERSION=wayland-1.11.1
     - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
     - PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
     - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
@@ -35,18 +33,18 @@ matrix:
     - env:
         - LABEL="meson Vulkan"
         - BUILD=meson
-        - MESON_OPTIONS="-Ddri-drivers=[] -Dgallium-drivers=[]"
-        - LLVM_VERSION=5.0
+        - MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
+        - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-trusty-4.0
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-5.0-dev
+            - llvm-4.0-dev
             # Common
             - xz-utils
             - libexpat1-dev
@@ -55,7 +53,7 @@ matrix:
     - env:
         - LABEL="meson loaders/classic DRI"
         - BUILD=meson
-        - MESON_OPTIONS="-Dvulkan-drivers=[] -Dgallium-drivers=[]"
+        - MESON_OPTIONS="-Dvulkan-drivers= -Dgallium-drivers="
       addons:
         apt:
           packages:
@@ -94,7 +92,7 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=5.0
+        - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - OVERRIDE_CC="gcc-4.8"
         - OVERRIDE_CXX="g++-4.8"
@@ -107,12 +105,12 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-trusty-4.0
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-5.0-dev
+            - llvm-4.0-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -125,7 +123,7 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=5.0
+        - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
@@ -136,12 +134,12 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-trusty-4.0
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-5.0-dev
+            - llvm-4.0-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -161,7 +159,7 @@ matrix:
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv,imx"
+        - GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
@@ -233,7 +231,7 @@ matrix:
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
         - DRI_DRIVERS=""
         - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="r600"
+        - GALLIUM_DRIVERS="r600,radeonsi"
         - VULKAN_DRIVERS=""
         - LIBUNWIND_FLAGS="--enable-libunwind"
       addons:
@@ -292,39 +290,6 @@ matrix:
             - libx11-xcb-dev
             - libelf-dev
             - libunwind8-dev
-    - env:
-        # NOTE: Analogous to SWR above, building Clover is quite slow.
-        - LABEL="make Gallium ST Clover LLVM-6.0"
-        - BUILD=make
-        - MAKEFLAGS="-j4"
-        - MAKE_CHECK_COMMAND="true"
-        - LLVM_VERSION=6.0
-        - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-        - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
-        - DRI_DRIVERS=""
-        - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-        - GALLIUM_DRIVERS="r600,radeonsi"
-        - VULKAN_DRIVERS=""
-        - LIBUNWIND_FLAGS="--enable-libunwind"
-      addons:
-        apt:
-          sources:
-            - llvm-toolchain-trusty-6.0
-            # llvm-6 depends on gcc-4.9 which is not in main repo
-            - ubuntu-toolchain-r-test
-          packages:
-            - libclc-dev
-            # From sources above
-            - llvm-6.0-dev
-            - clang-6.0
-            - libclang-6.0-dev
-            # Common
-            - xz-utils
-            - x11proto-xf86vidmode-dev
-            - libexpat1-dev
-            - libx11-xcb-dev
-            - libelf-dev
-            - libunwind8-dev
     - env:
         - LABEL="make Gallium ST Other"
         - BUILD=make
@@ -366,7 +331,7 @@ matrix:
         - BUILD=make
         - MAKEFLAGS="-j4"
         - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel check"
-        - LLVM_VERSION=5.0
+        - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl --with-platforms=x11,wayland"
         - DRI_DRIVERS=""
@@ -377,12 +342,12 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-trusty-4.0
           packages:
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-5.0-dev
+            - llvm-4.0-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -400,6 +365,7 @@ matrix:
       addons:
         apt:
           packages:
+            - scons
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -418,6 +384,7 @@ matrix:
       addons:
         apt:
           packages:
+            - scons
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             - llvm-3.3-dev
@@ -432,7 +399,7 @@ matrix:
         - BUILD=scons
         - SCONSFLAGS="-j4"
         - SCONS_TARGET="swr=1"
-        - LLVM_VERSION=5.0
+        - LLVM_VERSION=4.0
         - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
         # Keep it symmetrical to the make build. There's no actual SWR, yet.
         - SCONS_CHECK_COMMAND="true"
@@ -441,12 +408,13 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-trusty-4.0
           packages:
+            - scons
             # LLVM packaging is broken and misses these dependencies
             - libedit-dev
             # From sources above
-            - llvm-5.0-dev
+            - llvm-4.0-dev
             # Common
             - xz-utils
             - x11proto-xf86vidmode-dev
@@ -499,11 +467,6 @@ install:
       pip3 install --user "meson<0.45.0";
     fi
 
-  # Install a more modern scons from pip.
-  - if test "x$BUILD" = xscons; then
-      pip2 install --user "scons>=2.4";
-    fi
-
   # Since libdrm gets updated in configure.ac regularly, try to pick up the
   # latest version from there.
   - for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
@@ -547,14 +510,6 @@ install:
       tar -jxvf $LIBDRM_VERSION.tar.bz2
       (cd $LIBDRM_VERSION && ./configure --prefix=$HOME/prefix --enable-vc4 --enable-freedreno --enable-etnaviv-experimental-api && make install)
 
-      wget $XORG_RELEASES/proto/$RANDRPROTO_VERSION.tar.bz2
-      tar -jxvf $RANDRPROTO_VERSION.tar.bz2
-      (cd $RANDRPROTO_VERSION && ./configure --prefix=$HOME/prefix && make install)
-
-      wget $XORG_RELEASES/lib/$LIBXRANDR_VERSION.tar.bz2
-      tar -jxvf $LIBXRANDR_VERSION.tar.bz2
-      (cd $LIBXRANDR_VERSION && ./configure --prefix=$HOME/prefix && make install)
-
       wget $XORG_RELEASES/lib/$LIBXSHMFENCE_VERSION.tar.bz2
       tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
       (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make install)
@@ -586,34 +541,13 @@ install:
            "#ifndef _LINUX_MEMFD_H" \
            "#define _LINUX_MEMFD_H" \
            "" \
+           "#define __NR_memfd_create 319" \
+           "#define SYS_memfd_create __NR_memfd_create" \
+           "" \
            "#define MFD_CLOEXEC             0x0001U" \
            "#define MFD_ALLOW_SEALING       0x0002U" \
            "" \
            "#endif /* _LINUX_MEMFD_H */" > linux/memfd.h
-
-      # Generate this header, including the missing SYS_memfd_create
-      # macro, which is not provided by the header in the Travis
-      # instance
-      mkdir -p sys
-      printf "%s\n" \
-           "#ifndef _SYSCALL_H" \
-           "#define _SYSCALL_H      1" \
-           "" \
-           "#include <asm/unistd.h>" \
-           "" \
-           "#ifndef _LIBC" \
-           "# include <bits/syscall.h>" \
-           "#endif" \
-           "" \
-           "#ifndef __NR_memfd_create" \
-           "# define __NR_memfd_create 319 /* Taken from <asm/unistd_64.h> */" \
-           "#endif" \
-           "" \
-           "#ifndef SYS_memfd_create" \
-           "# define SYS_memfd_create __NR_memfd_create" \
-           "#endif" \
-           "" \
-           "#endif" > sys/syscall.h
     fi
 
 script:
@@ -624,9 +558,7 @@ script:
 
       export CFLAGS="$CFLAGS -isystem`pwd`";
 
-      mkdir build &&
-      cd build &&
-      ../autogen.sh --enable-debug
+      ./autogen.sh --enable-debug
         $LIBUNWIND_FLAGS
         $DRI_LOADERS
         --with-dri-drivers=$DRI_DRIVERS

Android.common.mk

@@ -74,7 +74,6 @@ LOCAL_CFLAGS += \
 	-DHAVE_ENDIAN_H \
 	-DHAVE_ZLIB \
 	-DMAJOR_IN_SYSMACROS \
-	-DVK_USE_PLATFORM_ANDROID_KHR \
 	-fvisibility=hidden \
 	-Wno-sign-compare
 

Makefile.am

@@ -77,7 +77,6 @@ noinst_HEADERS = \
 	include/drm-uapi/drm_mode.h \
 	include/drm-uapi/i915_drm.h \
 	include/drm-uapi/tegra_drm.h \
-	include/drm-uapi/v3d_drm.h \
 	include/drm-uapi/vc4_drm.h \
 	include/D3D9 \
 	include/GL/wglext.h \

README.rst

@@ -1,79 +0,0 @@
-`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
-======================================================
-
-
-Source
-------
-
-This repository lives at https://gitlab.freedesktop.org/mesa/mesa.
-Other repositories are likely forks, and code found there is not supported.
-
-
-Build status
-------------
-
-Travis:
-
-.. image:: https://travis-ci.org/mesa3d/mesa.svg?branch=master
-    :target: https://travis-ci.org/mesa3d/mesa
-
-Appveyor:
-
-.. image:: https://img.shields.io/appveyor/ci/mesa3d/mesa.svg
-    :target: https://ci.appveyor.com/project/mesa3d/mesa
-
-Coverity:
-
-.. image:: https://scan.coverity.com/projects/139/badge.svg?flat=1
-    :target: https://scan.coverity.com/projects/mesa
-
-
-Build & install
----------------
-
-You can find more information in our documentation (`docs/install.html
-<https://mesa3d.org/install.html>`_), but the recommended way is to use
-Meson (`docs/meson.html <https://mesa3d.org/meson.html>`_):
-
-.. code-block:: sh
-
-  $ mkdir build
-  $ cd build
-  $ meson ..
-  $ sudo ninja install
-
-
-Support
--------
-
-Many Mesa devs hang on IRC; if you're not sure which channel is
-appropriate, you should ask your question on `Freenode's #dri-devel
-<irc://chat.freenode.net#dri-devel>`_, someone will redirect you if
-necessary.
-Remember that not everyone is in the same timezone as you, so it might
-take a while before someone qualified sees your question.
-To figure out who you're talking to, or which nick to ping for your
-question, check out `Who's Who on IRC
-<https://dri.freedesktop.org/wiki/WhosWho/>`_.
-
-The next best option is to ask your question in an email to the
-mailing lists: `mesa-dev\@lists.freedesktop.org
-<https://lists.freedesktop.org/mailman/listinfo/mesa-dev>`_
-
-
-Bug reports
------------
-
-If you think something isn't working properly, please file a bug report
-(`docs/bugs.html <https://mesa3d.org/bugs.html>`_).
-
-
-Contributing
-------------
-
-Contributions are welcome, and step-by-step instructions can be found in our
-documentation (`docs/submittingpatches.html
-<https://mesa3d.org/submittingpatches.html>`_).
-
-Note that Mesa uses email mailing-lists for patches submission, review and
-discussions.

REVIEWERS

@@ -116,7 +116,6 @@ MESON BUILD
 R: Dylan Baker <dylan@pnwbakers.com>
 R: Eric Engestrom <eric@engestrom.ch>
 F: */meson.build
-F: meson.build
 F: meson_options.txt
 
 ANDROID EGL SUPPORT

SConstruct

@@ -27,12 +27,6 @@ import SCons.Util
 
 import common
 
-#######################################################################
-# Minimal scons version
-
-EnsureSConsVersion(2, 4)
-
-
 #######################################################################
 # Configuration options
 

VERSION

@@ -1 +1 @@
-18.2.0-rc1
+18.1.7

appveyor.yml

@@ -35,13 +35,13 @@ clone_depth: 100
 
 cache:
 - win_flex_bison-2.5.9.zip
-- llvm-5.0.1-msvc2015-mtd.7z
+- llvm-3.3.1-msvc2015-mtd.7z
 
 os: Visual Studio 2015
 
 environment:
   WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip
-  LLVM_ARCHIVE: llvm-5.0.1-msvc2015-mtd.7z
+  LLVM_ARCHIVE: llvm-3.3.1-msvc2015-mtd.7z
 
 install:
 # Check pip

bin/.cherry-ignore

@@ -0,0 +1,73 @@
+d89f58a6b8436b59dcf3b896c0ccddabed3f78fd
+a7d0c53ab89ca86b705014925214101f5bc4187f
+
+# These patches are ignored becuase Jason provided a version rebased on the 18.1
+# branch that was pulled instead
+#
+778e2881a04817e8c10c7a400bf1e37414420194
+3b54dd87f707a0fa40a1555bee64aeb06a381c27
+eeae4851494c16d2a6591550bfa6ef77d887ebe3
+a26693493570a9d0f0fba1be617e01ee7bfff4db
+0e7f3febf7e739c075a139ae641d65a0618752f3
+
+# This has a warning that it fixes more than one commit, but isn't needed in
+# 18.1
+#
+a1220e73116bad74f39c1792a0b0cf0e4e5031db
+
+# This doesn't apply and isn't necessary since
+# 1cc2e0cc6b47bd5efbf2af266405060785085e6b isn't in the 18.1 branch
+#
+587e712eda95c31d88ea9d20e59ad0ae59afef4f
+
+# This requires too many previous patch, and Marek (the author) decided to
+# to drop it from stable
+# 
+cac7ab1192eefdd8d8b3f25053fb006b5c330eb8
+
+# This patch is excluded since it requires additional patches to be pulled,
+# and is mainly aimed at developers, who rarely (if ever) work in the
+# stable branch
+#
+a2f5292c82ad07731d633b36a663e46adc181db9
+
+# This patch required manual backport, which was provided as
+# 3953467ee7851792c1d4b1c9435499545a7da9fc
+#
+4a67ce886a7b3def5f66c1aedf9e5436d157a03c
+
+# This patch required manual backport, which was provided as
+# 31677c5aa867e457cd06ae25150be2155e8da3c6
+#
+1f616a840eac02241c585d28e9dac8f19a297f39
+
+# Jason de-nominated this because it "a) shouldn't be needed and b) is horribly
+# broken"
+#
+11712b9ca17e4e1a819dcb7d020e19c6da77bc90
+
+# None of these are tagged for 18.1, they're for 18.2, but get-pick-list
+# still finds them for some reason
+#
+1c7a2433b270afb65f044d0cf49cb67715f50b5b
+0f79b2015bc0c44a8ed470684b6789f0e2e6aa6c
+ccbe33af5b086f4b488ac7ca8a8a45ebc9ac189c
+3f9cb2eb05152f4f0269e97893a16f23261f095b
+f2c0d310d6efe560de8192ab468ba02d50c9ac1e
+50a8713d4f90a6c70a23f9f5871420371df283a7
+1561e4984eb03d6946d19b820b83a96bbbd83b98
+66e12451ac4e4e1c05a48b2cd2b0d3186f779f20
+73b342c7a52a93d283799800824311639f372de0
+71d5b2fbf83061a1319141d26942771e8c75ff2b
+011a811652c74dcc9f56506ebb6075e4bdfe6ef9
+f3a78a9da01218df0067b24b52204a4e5f01bc69
+f9e8456c39136aa41f85f82758a00e5aa2aab334
+0aacb5eab6120aa1410966d23101e16eea3fbcd7
+a4a104fc81e93555899050efac23c3cd6ba762ab
+24ee53231da84a1be5ec08abebe8a2ff6aa019ca
+4c43ec461de4f122d5d6566361d064c816e4ef69
+
+# These have more than one fixes tag and generate a warning
+#
+24839663a40257e0468406d72c48d431b5ae2bd4
+6ff1c479968819b93c46d24bd898e89ce14ac401

bin/bugzilla_mesa.sh

@@ -23,7 +23,7 @@ echo "<ul>"
 echo ""
 
 # extract fdo urls from commit log
-git log --pretty=medium $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before | sort -n -u | sed -e $use_after |\
+git log $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before | sort -n -u | sed -e $use_after |\
 while read url
 do
 	id=$(echo $url | cut -d'=' -f2)

bin/install_megadrivers.py

@@ -43,26 +43,28 @@ def main():
     master = os.path.join(to, os.path.basename(args.megadriver))
 
     if not os.path.exists(to):
+        if os.path.lexists(to):
+            os.unlink(to)
         os.makedirs(to)
     shutil.copy(args.megadriver, master)
 
-    for driver in args.drivers:
-        abs_driver = os.path.join(to, driver)
+    for each in args.drivers:
+        driver = os.path.join(to, each)
 
-        if os.path.exists(abs_driver):
-            os.unlink(abs_driver)
-        print('installing {} to {}'.format(args.megadriver, abs_driver))
-        os.link(master, abs_driver)
+        if os.path.lexists(driver):
+            os.unlink(driver)
+        print('installing {} to {}'.format(args.megadriver, driver))
+        os.link(master, driver)
 
         try:
             ret = os.getcwd()
             os.chdir(to)
 
-            name, ext = os.path.splitext(driver)
+            name, ext = os.path.splitext(each)
             while ext != '.so':
-                if os.path.exists(name):
+                if os.path.lexists(name):
                     os.unlink(name)
-                os.symlink(driver, name)
+                os.symlink(each, name)
                 name, ext = os.path.splitext(name)
         finally:
             os.chdir(ret)

configure.ac

@@ -78,9 +78,8 @@ LIBDRM_AMDGPU_REQUIRED=2.4.91
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
-LIBDRM_FREEDRENO_REQUIRED=2.4.92
+LIBDRM_FREEDRENO_REQUIRED=2.4.91
 LIBDRM_ETNAVIV_REQUIRED=2.4.89
-LIBDRM_VC4_REQUIRED=2.4.89
 
 dnl Versions for external dependencies
 DRI2PROTO_REQUIRED=2.8
@@ -90,7 +89,6 @@ LIBOMXIL_TIZONIA_REQUIRED=0.10.0
 LIBVA_REQUIRED=0.39.0
 VDPAU_REQUIRED=1.1
 WAYLAND_REQUIRED=1.11
-WAYLAND_EGL_BACKEND_REQUIRED=3
 WAYLAND_PROTOCOLS_REQUIRED=1.8
 XCB_REQUIRED=1.9.3
 XCBDRI2_REQUIRED=1.8
@@ -108,9 +106,9 @@ dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
 LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
-LLVM_REQUIRED_RADEONSI=5.0.0
-LLVM_REQUIRED_RADV=5.0.0
-LLVM_REQUIRED_SWR=5.0.0
+LLVM_REQUIRED_RADEONSI=4.0.0
+LLVM_REQUIRED_RADV=4.0.0
+LLVM_REQUIRED_SWR=4.0.0
 
 dnl Check for progs
 AC_PROG_CPP
@@ -121,7 +119,6 @@ dnl other CC/CXX flags related help
 AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only needed if not
                               enabled by default and different  from -std=c++11)])
 AM_PROG_CC_C_O
-AC_PROG_GREP
 AC_PROG_NM
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
@@ -302,10 +299,7 @@ AX_CHECK_COMPILE_FLAG([-Wall],                                 [CFLAGS="$CFLAGS
 AX_CHECK_COMPILE_FLAG([-Werror=implicit-function-declaration], [CFLAGS="$CFLAGS -Werror=implicit-function-declaration"])
 AX_CHECK_COMPILE_FLAG([-Werror=missing-prototypes],            [CFLAGS="$CFLAGS -Werror=missing-prototypes"])
 AX_CHECK_COMPILE_FLAG([-Wmissing-prototypes],                  [CFLAGS="$CFLAGS -Wmissing-prototypes"])
-dnl Dylan Baker: gcc and clang always accepr -Wno-*, hence check for the original warning, then set the no-* flag
-AX_CHECK_COMPILE_FLAG([-Wmissing-field-initializers],          [CFLAGS="$CFLAGS -Wno-missing-field-initializers"])
 AX_CHECK_COMPILE_FLAG([-fno-math-errno],                       [CFLAGS="$CFLAGS -fno-math-errno"])
-
 AX_CHECK_COMPILE_FLAG([-fno-trapping-math],                    [CFLAGS="$CFLAGS -fno-trapping-math"])
 AX_CHECK_COMPILE_FLAG([-fvisibility=hidden],                   [VISIBILITY_CFLAGS="-fvisibility=hidden"])
 
@@ -317,7 +311,6 @@ AX_CHECK_COMPILE_FLAG([-Wall],                                 [CXXFLAGS="$CXXFL
 AX_CHECK_COMPILE_FLAG([-fno-math-errno],                       [CXXFLAGS="$CXXFLAGS -fno-math-errno"])
 AX_CHECK_COMPILE_FLAG([-fno-trapping-math],                    [CXXFLAGS="$CXXFLAGS -fno-trapping-math"])
 AX_CHECK_COMPILE_FLAG([-fvisibility=hidden],                   [VISIBILITY_CXXFLAGS="-fvisibility=hidden"])
-AX_CHECK_COMPILE_FLAG([-Wmissing-field-initializers],          [CXXFLAGS="$CXXFLAGS -Wno-missing-field-initializers"])
 AC_LANG_POP([C++])
 
 # Flags to help ensure that certain portions of the code -- and only those
@@ -767,6 +760,21 @@ esac
 
 AC_SUBST([LIB_EXT])
 
+dnl
+dnl potentially-infringing-but-nobody-knows-for-sure stuff
+dnl
+AC_ARG_ENABLE([texture-float],
+    [AS_HELP_STRING([--enable-texture-float],
+        [enable floating-point textures and renderbuffers @<:@default=disabled@:>@])],
+    [enable_texture_float="$enableval"],
+    [enable_texture_float=no]
+)
+if test "x$enable_texture_float" = xyes; then
+    AC_MSG_WARN([Floating-point textures enabled.])
+    AC_MSG_WARN([Please consult docs/patents.txt with your lawyer before building Mesa.])
+    DEFINES="$DEFINES -DTEXTURE_FLOAT_ENABLED"
+fi
+
 dnl
 dnl Arch/platform-specific settings
 dnl
@@ -1366,7 +1374,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast"
 AC_ARG_WITH([gallium-drivers],
     [AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@],
         [comma delimited Gallium drivers list, e.g.
-        "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv,imx"
+        "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,vc4,vc5,virgl,etnaviv,imx"
         @<:@default=r300,r600,svga,swrast@:>@])],
     [with_gallium_drivers="$withval"],
     [with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"])
@@ -1503,15 +1511,15 @@ fi
 AC_ARG_WITH([gl-lib-name],
   [AS_HELP_STRING([--with-gl-lib-name@<:@=NAME@:>@],
     [specify GL library name @<:@default=GL@:>@])],
-  [GL_LIB=$withval],
-  [GL_LIB="$DEFAULT_GL_LIB_NAME"])
+  [AC_MSG_ERROR([--with-gl-lib-name is no longer supported. Rename the library manually if needed.])],
+  [])
 AC_ARG_WITH([osmesa-lib-name],
   [AS_HELP_STRING([--with-osmesa-lib-name@<:@=NAME@:>@],
     [specify OSMesa library name @<:@default=OSMesa@:>@])],
-  [OSMESA_LIB=$withval],
-  [OSMESA_LIB=OSMesa])
-AS_IF([test "x$GL_LIB" = xyes], [GL_LIB="$DEFAULT_GL_LIB_NAME"])
-AS_IF([test "x$OSMESA_LIB" = xyes], [OSMESA_LIB=OSMesa])
+  [AC_MSG_ERROR([--with-osmesa-lib-name is no longer supported. Rename the library manually if needed.])],
+  [])
+GL_LIB="$DEFAULT_GL_LIB_NAME"
+OSMESA_LIB=OSMesa
 
 dnl
 dnl Mangled Mesa support
@@ -1523,6 +1531,9 @@ AC_ARG_ENABLE([mangling],
   [enable_mangling=no]
 )
 if test "x${enable_mangling}" = "xyes" ; then
+  if test "x$enable_libglvnd" = xyes; then
+    AC_MSG_ERROR([Conflicting options --enable-mangling and --enable-libglvnd.])
+  fi
   DEFINES="${DEFINES} -DUSE_MGL_NAMESPACE"
   GL_LIB="Mangled${GL_LIB}"
   OSMESA_LIB="Mangled${OSMESA_LIB}"
@@ -1530,6 +1541,15 @@ fi
 AC_SUBST([GL_LIB])
 AC_SUBST([OSMESA_LIB])
 
+dnl HACK when building glx + glvnd we ship gl.pc, despite that glvnd should do it
+dnl Thus we need to use GL as a DSO name.
+if test "x$enable_libglvnd" = xyes -a "x$enable_glx" != xno; then
+  GL_PKGCONF_LIB="GL"
+else
+  GL_PKGCONF_LIB="$GL_LIB"
+fi
+AC_SUBST([GL_PKGCONF_LIB])
+
 # Check for libdrm
 PKG_CHECK_MODULES([LIBDRM], [libdrm >= $LIBDRM_REQUIRED],
                   [have_libdrm=yes], [have_libdrm=no])
@@ -1569,7 +1589,6 @@ AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes -a "x$dri_platform" = x
 AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
 AM_CONDITIONAL(HAVE_GALLIUM_EXTRA_HUD, test "x$enable_gallium_extra_hud" = xyes )
 AM_CONDITIONAL(HAVE_WINDOWSDRI, test "x$enable_dri" = xyes -a "x$dri_platform" = xwindows )
-AM_CONDITIONAL(HAVE_XLEASE, test "x$have_xlease" = xyes )
 
 AC_ARG_ENABLE([shared-glapi],
     [AS_HELP_STRING([--enable-shared-glapi],
@@ -1658,6 +1677,8 @@ xxlib | xgallium-xlib)
 xdri)
     # DRI-based GLX
 
+    require_dri_shared_libs_and_glapi "GLX"
+
     # find the DRI deps for libGL
     dri_modules="x11 xext xdamage >= $XDAMAGE_REQUIRED xfixes x11-xcb xcb xcb-glx >= $XCBGLX_REQUIRED"
 
@@ -1802,9 +1823,6 @@ for plat in $platforms; do
         PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >= $WAYLAND_REQUIRED])
         PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >= $WAYLAND_REQUIRED])
         PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED])
-        if test "x$enable_egl" = xyes; then
-          PKG_CHECK_MODULES([WAYLAND_EGL], [wayland-egl-backend >= $WAYLAND_EGL_BACKEND_REQUIRED])
-        fi
         WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir wayland-protocols`
 
         PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
@@ -1837,9 +1855,6 @@ for plat in $platforms; do
 
     android)
         PKG_CHECK_MODULES([ANDROID], [cutils hardware sync])
-        if test -n "$with_gallium_drivers"; then
-            PKG_CHECK_MODULES([BACKTRACE], [backtrace])
-        fi
         DEFINES="$DEFINES -DHAVE_ANDROID_PLATFORM"
         ;;
 
@@ -1875,45 +1890,12 @@ if test x"$enable_dri3" = xyes; then
     fi
 fi
 
-
-if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
-    have_xlease=yes
-else
-    have_xlease=no
-fi
-
-if test x"$have_xlease" = xyes; then
-    randr_modules="x11-xcb xcb-randr"
-    PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
-    xlib_randr_modules="xrandr"
-    PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
-fi
-
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
 AM_CONDITIONAL(HAVE_PLATFORM_SURFACELESS, echo "$platforms" | grep -q 'surfaceless')
 AM_CONDITIONAL(HAVE_PLATFORM_ANDROID, echo "$platforms" | grep -q 'android')
 
-AC_ARG_ENABLE(xlib-lease,
-    [AS_HELP_STRING([--enable-xlib-lease]
-                    [enable VK_acquire_xlib_display using X leases])],
-    [enable_xlib_lease=$enableval], [enable_xlib_lease=auto])
-case "x$enable_xlib_lease" in
-xyes)
-    ;;
-xno)
-    ;;
-*)
-    if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
-        enable_xlib_lease=yes
-    else
-        enable_xlib_lease=no
-    fi
-esac
-
-AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
-
 dnl
 dnl More DRI setup
 dnl
@@ -2764,20 +2746,20 @@ if test -n "$with_gallium_drivers"; then
             ;;
         xvc4)
             HAVE_GALLIUM_VC4=yes
-            PKG_CHECK_MODULES([VC4], [libdrm >= $LIBDRM_VC4_REQUIRED])
+            require_libdrm "vc4"
 
             PKG_CHECK_MODULES([SIMPENROSE], [simpenrose],
                               [USE_VC4_SIMULATOR=yes;
                                DEFINES="$DEFINES -DUSE_VC4_SIMULATOR"],
                               [USE_VC4_SIMULATOR=no])
             ;;
-        xv3d)
-            HAVE_GALLIUM_V3D=yes
+        xvc5)
+            HAVE_GALLIUM_VC5=yes
 
-            PKG_CHECK_MODULES([V3D_SIMULATOR], [v3dv3],
-                              [USE_V3D_SIMULATOR=yes;
-                               DEFINES="$DEFINES -DUSE_V3D_SIMULATOR"],
-                              [USE_V3D_SIMULATOR=no])
+            PKG_CHECK_MODULES([VC5_SIMULATOR], [v3dv3],
+                              [USE_VC5_SIMULATOR=yes;
+                               DEFINES="$DEFINES -DUSE_VC5_SIMULATOR"],
+                              [AC_MSG_ERROR([vc5 requires the simulator])])
             ;;
         xpl111)
             HAVE_GALLIUM_PL111=yes
@@ -2797,9 +2779,8 @@ if test -n "$with_gallium_drivers"; then
 fi
 
 # XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x5.0.0 -a \
-                                              "x$LLVM_VERSION" != x5.0.1 -a \
-                                              "x$LLVM_VERSION" != x5.0.2)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
+                                              "x$LLVM_VERSION" != x4.0.1)
 
 if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
     llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
@@ -2930,8 +2911,8 @@ AM_CONDITIONAL(HAVE_GALLIUM_SWR, test "x$HAVE_GALLIUM_SWR" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_SWRAST, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes -o \
                                          "x$HAVE_GALLIUM_LLVMPIPE" = xyes -o \
                                          "x$HAVE_GALLIUM_SWR" = xyes)
-AM_CONDITIONAL(HAVE_GALLIUM_V3D, test "x$HAVE_GALLIUM_V3D" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_VC4, test "x$HAVE_GALLIUM_VC4" = xyes)
+AM_CONDITIONAL(HAVE_GALLIUM_VC5, test "x$HAVE_GALLIUM_VC5" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_VIRGL, test "x$HAVE_GALLIUM_VIRGL" = xyes)
 
 AM_CONDITIONAL(HAVE_GALLIUM_STATIC_TARGETS, test "x$enable_shared_pipe_drivers" = xno)
@@ -2959,7 +2940,7 @@ AM_CONDITIONAL(HAVE_AMD_DRIVERS, test "x$HAVE_GALLIUM_RADEONSI" = xyes -o \
                                       "x$HAVE_RADEON_VULKAN" = xyes)
 
 AM_CONDITIONAL(HAVE_BROADCOM_DRIVERS, test "x$HAVE_GALLIUM_VC4" = xyes -o \
-                                      "x$HAVE_GALLIUM_V3D" = xyes)
+                                      "x$HAVE_GALLIUM_VC5" = xyes)
 
 AM_CONDITIONAL(HAVE_INTEL_DRIVERS, test "x$HAVE_INTEL_VULKAN" = xyes -o \
                                         "x$HAVE_I965_DRI" = xyes)
@@ -2970,8 +2951,8 @@ AM_CONDITIONAL(NEED_RADEON_DRM_WINSYS, test "x$HAVE_GALLIUM_R300" = xyes -o \
 AM_CONDITIONAL(NEED_WINSYS_XLIB, test "x$enable_glx" = xgallium-xlib)
 AM_CONDITIONAL(HAVE_GALLIUM_COMPUTE, test x$enable_opencl = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_LLVM, test "x$enable_llvm" = xyes)
-AM_CONDITIONAL(USE_V3D_SIMULATOR, test x$USE_V3D_SIMULATOR = xyes)
 AM_CONDITIONAL(USE_VC4_SIMULATOR, test x$USE_VC4_SIMULATOR = xyes)
+AM_CONDITIONAL(USE_VC5_SIMULATOR, test x$USE_VC5_SIMULATOR = xyes)
 
 AM_CONDITIONAL(HAVE_LIBDRM, test "x$have_libdrm" = xyes)
 AM_CONDITIONAL(HAVE_OSMESA, test "x$enable_osmesa" = xyes)
@@ -3007,7 +2988,7 @@ AC_SUBST([XVMC_MAJOR], 1)
 AC_SUBST([XVMC_MINOR], 0)
 
 AC_SUBST([XA_MAJOR], 2)
-AC_SUBST([XA_MINOR], 4)
+AC_SUBST([XA_MINOR], 3)
 AC_SUBST([XA_PATCH], 0)
 AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_PATCH")
 
@@ -3056,6 +3037,8 @@ AC_CONFIG_FILES([Makefile
                  src/egl/Makefile
                  src/egl/main/egl.pc
                  src/egl/wayland/wayland-drm/Makefile
+                 src/egl/wayland/wayland-egl/Makefile
+                 src/egl/wayland/wayland-egl/wayland-egl.pc
                  src/gallium/Makefile
                  src/gallium/auxiliary/Makefile
                  src/gallium/auxiliary/pipe-loader/Makefile
@@ -3073,8 +3056,8 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/drivers/tegra/Makefile
                  src/gallium/drivers/etnaviv/Makefile
                  src/gallium/drivers/imx/Makefile
-                 src/gallium/drivers/v3d/Makefile
                  src/gallium/drivers/vc4/Makefile
+                 src/gallium/drivers/vc5/Makefile
                  src/gallium/drivers/virgl/Makefile
                  src/gallium/state_trackers/clover/Makefile
                  src/gallium/state_trackers/dri/Makefile
@@ -3121,8 +3104,8 @@ AC_CONFIG_FILES([Makefile
                  src/gallium/winsys/sw/wrapper/Makefile
                  src/gallium/winsys/sw/xlib/Makefile
                  src/gallium/winsys/tegra/drm/Makefile
-                 src/gallium/winsys/v3d/drm/Makefile
                  src/gallium/winsys/vc4/drm/Makefile
+                 src/gallium/winsys/vc5/drm/Makefile
                  src/gallium/winsys/virgl/drm/Makefile
                  src/gallium/winsys/virgl/vtest/Makefile
                  src/gbm/Makefile
@@ -3157,9 +3140,7 @@ AC_CONFIG_FILES([Makefile
                  src/mesa/state_tracker/tests/Makefile
                  src/util/Makefile
                  src/util/tests/hash_table/Makefile
-                 src/util/tests/set/Makefile
                  src/util/tests/string_buffer/Makefile
-                 src/util/tests/vma/Makefile
                  src/util/xmlpool/Makefile
                  src/vulkan/Makefile])
 

docs/codingstyle.html

@@ -83,7 +83,7 @@ We try to quote the OpenGL specification where prudent:
     *     "An INVALID_OPERATION error is generated for any of the following
     *     conditions:
     *
-    *     * <length> is zero."
+    *     * <length> is zero."
     *
     * Additionally, page 94 of the PDF of the OpenGL 4.5 core spec
     * (30.10.2014) also says this, so it's no longer allowed for desktop GL,
@@ -94,7 +94,7 @@ Function comment example:
 <pre>
    /**
     * Create and initialize a new buffer object.  Called via the
-    * ctx-&gt;Driver.CreateObject() driver callback function.
+    * ctx->Driver.CreateObject() driver callback function.
     * \param  name  integer name of the object
     * \param  type  one of GL_FOO, GL_BAR, etc.
     * \return  pointer to new object or NULL if error

docs/egl.html

@@ -168,7 +168,6 @@ the X server directly using (XCB-)DRI2 protocol.</p>
 <p>This driver can share DRI drivers with <code>libGL</code>.</p>
 
 </dd>
-</dl>
 
 <h2>Packaging</h2>
 

docs/features.txt

@@ -36,7 +36,7 @@ context as extensions.
 Feature                                                 Status
 ------------------------------------------------------- ------------------------
 
-GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl
+GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
 
   glBindFragDataLocation, glGetFragDataLocation         DONE
   GL_NV_conditional_render (Conditional rendering)      DONE ()
@@ -63,12 +63,12 @@ GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llv
   glVertexAttribI commands                              DONE
   Depth format cube textures                            DONE ()
   GLX_ARB_create_context (GLX 1.4 is required)          DONE
-  Multisample anti-aliasing                             DONE (freedreno/a5xx, freedreno (*), llvmpipe (*), softpipe (*), swr (*))
+  Multisample anti-aliasing                             DONE (freedreno (*), llvmpipe (*), softpipe (*), swr (*))
 
-(*) freedreno (a2xx-a4xx), llvmpipe, softpipe, and swr have fake Multisample anti-aliasing support
+(*) freedreno, llvmpipe, softpipe, and swr have fake Multisample anti-aliasing support
 
 
-GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl
+GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
 
   Forward compatible context support/deprecations       DONE ()
   GL_ARB_draw_instanced (Instanced drawing)             DONE ()
@@ -81,7 +81,7 @@ GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llv
   GL_EXT_texture_snorm (Signed normalized textures)     DONE ()
 
 
-GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr, virgl
+GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
 
   Core/compatibility profiles                           DONE
   Geometry shaders                                      DONE ()
@@ -90,13 +90,13 @@ GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, soft
   GL_ARB_fragment_coord_conventions (Frag shader coord) DONE (freedreno)
   GL_ARB_provoking_vertex (Provoking vertex)            DONE (freedreno)
   GL_ARB_seamless_cube_map (Seamless cubemaps)          DONE (freedreno)
-  GL_ARB_texture_multisample (Multisample textures)     DONE (freedreno/a5xx)
+  GL_ARB_texture_multisample (Multisample textures)     DONE ()
   GL_ARB_depth_clamp (Frag depth clamp)                 DONE (freedreno)
   GL_ARB_sync (Fence objects)                           DONE (freedreno)
   GLX_ARB_create_context_profile                        DONE
 
 
-GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl
+GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe
 
   GL_ARB_blend_func_extended                            DONE (freedreno/a3xx, swr)
   GL_ARB_explicit_attrib_location                       DONE (all drivers that support GLSL)
@@ -110,18 +110,18 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, soft
   GL_ARB_vertex_type_2_10_10_10_rev                     DONE (freedreno, swr)
 
 
-GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
+GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
   GL_ARB_draw_buffers_blend                             DONE (freedreno, i965/gen6+, nv50, llvmpipe, softpipe, swr)
   GL_ARB_draw_indirect                                  DONE (freedreno, i965/gen7+, llvmpipe, softpipe, swr)
   GL_ARB_gpu_shader5                                    DONE (i965/gen7+)
   - 'precise' qualifier                                 DONE
   - Dynamically uniform sampler array indices           DONE (softpipe)
-  - Dynamically uniform UBO array indices               DONE (freedreno)
+  - Dynamically uniform UBO array indices               DONE ()
   - Implicit signed -> unsigned conversions             DONE
   - Fused multiply-add                                  DONE ()
-  - Packing/bitfield/conversion functions               DONE (freedreno, softpipe)
-  - Enhanced textureGather                              DONE (freedreno, softpipe)
+  - Packing/bitfield/conversion functions               DONE (softpipe)
+  - Enhanced textureGather                              DONE (softpipe)
   - Geometry shader instancing                          DONE (llvmpipe, softpipe)
   - Geometry shader multiple streams                    DONE ()
   - Enhanced per-sample shading                         DONE ()
@@ -139,7 +139,7 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
   GL_ARB_transform_feedback3                            DONE (i965/gen7+, llvmpipe, softpipe, swr)
 
 
-GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
+GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
   GL_ARB_ES2_compatibility                              DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
   GL_ARB_get_program_binary                             DONE (0 or 1 binary formats)
@@ -149,7 +149,7 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
   GL_ARB_viewport_array                                 DONE (i965, nv50, llvmpipe, softpipe)
 
 
-GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
+GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
   GL_ARB_texture_compression_bptc                       DONE (freedreno, i965)
   GL_ARB_compressed_texture_pixel_storage               DONE (all drivers)
@@ -165,7 +165,7 @@ GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi, virgl
   GL_ARB_map_buffer_alignment                           DONE (all drivers)
 
 
-GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi, virgl
+GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
 
   GL_ARB_arrays_of_arrays                               DONE (all drivers that support GLSL 1.30)
   GL_ARB_ES3_compatibility                              DONE (all drivers that support GLSL 3.30)
@@ -205,20 +205,20 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
   - input/output block locations                        DONE
   GL_ARB_multi_bind                                     DONE (all drivers)
   GL_ARB_query_buffer_object                            DONE (i965/hsw+)
-  GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, llvmpipe, softpipe, swr, virgl)
-  GL_ARB_texture_stencil8                               DONE (freedreno, i965/hsw+, nv50, llvmpipe, softpipe, swr, virgl)
-  GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, llvmpipe, softpipe, swr, virgl)
+  GL_ARB_texture_mirror_clamp_to_edge                   DONE (i965, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_texture_stencil8                               DONE (freedreno, i965/hsw+, nv50, llvmpipe, softpipe, swr)
+  GL_ARB_vertex_type_10f_11f_11f_rev                    DONE (i965, nv50, llvmpipe, softpipe, swr)
 
 GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
 
-  GL_ARB_ES3_1_compatibility                            DONE (i965/hsw+, r600, virgl)
+  GL_ARB_ES3_1_compatibility                            DONE (i965/hsw+, r600)
   GL_ARB_clip_control                                   DONE (freedreno, i965, nv50, r600, llvmpipe, softpipe, swr)
-  GL_ARB_conditional_render_inverted                    DONE (freedreno, i965, nv50, r600, llvmpipe, softpipe, swr, virgl)
-  GL_ARB_cull_distance                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr, virgl)
-  GL_ARB_derivative_control                             DONE (i965, nv50, r600, virgl)
+  GL_ARB_conditional_render_inverted                    DONE (freedreno, i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_cull_distance                                  DONE (i965, nv50, r600, llvmpipe, softpipe, swr)
+  GL_ARB_derivative_control                             DONE (i965, nv50, r600)
   GL_ARB_direct_state_access                            DONE (all drivers)
   GL_ARB_get_texture_sub_image                          DONE (all drivers)
-  GL_ARB_shader_texture_image_samples                   DONE (i965, nv50, r600, virgl)
+  GL_ARB_shader_texture_image_samples                   DONE (i965, nv50, r600)
   GL_ARB_texture_barrier                                DONE (freedreno, i965, nv50, r600)
   GL_KHR_context_flush_control                          DONE (all - but needs GLX/EGL extension to be useful)
   GL_KHR_robustness                                     DONE (i965)
@@ -229,19 +229,19 @@ GL 4.6, GLSL 4.60
   GL_ARB_gl_spirv                                       in progress (Nicolai Hähnle, Ian Romanick)
   GL_ARB_indirect_parameters                            DONE (i965/gen7+, nvc0, radeonsi)
   GL_ARB_pipeline_statistics_query                      DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
-  GL_ARB_polygon_offset_clamp                           DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr, virgl)
-  GL_ARB_shader_atomic_counter_ops                      DONE (freedreno/a5xx, i965/gen7+, nvc0, r600, radeonsi, softpipe, virgl)
+  GL_ARB_polygon_offset_clamp                           DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, swr)
+  GL_ARB_shader_atomic_counter_ops                      DONE (freedreno/a5xx, i965/gen7+, nvc0, r600, radeonsi, softpipe)
   GL_ARB_shader_draw_parameters                         DONE (i965, nvc0, radeonsi)
   GL_ARB_shader_group_vote                              DONE (i965, nvc0, radeonsi)
   GL_ARB_spirv_extensions                               in progress (Nicolai Hähnle, Ian Romanick)
   GL_ARB_texture_filter_anisotropic                     DONE (freedreno, i965, nv50, nvc0, r600, radeonsi, softpipe (*), llvmpipe (*))
-  GL_ARB_transform_feedback_overflow_query              DONE (i965/gen6+, nvc0, radeonsi, llvmpipe, softpipe, virgl)
+  GL_ARB_transform_feedback_overflow_query              DONE (i965/gen6+, nvc0, radeonsi, llvmpipe, softpipe)
   GL_KHR_no_error                                       DONE (all drivers)
 
 (*) softpipe and llvmpipe advertise 16x anisotropy but simply ignore the setting
 
 These are the extensions cherry-picked to make GLES 3.1
-GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi, virgl
+GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi
 
   GL_ARB_arrays_of_arrays                               DONE (all drivers that support GLSL 1.30)
   GL_ARB_compute_shader                                 DONE (freedreno/a5xx, i965/gen7+, softpipe)
@@ -256,11 +256,11 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi, virgl
   GL_ARB_shading_language_packing                       DONE (all drivers)
   GL_ARB_separate_shader_objects                        DONE (all drivers)
   GL_ARB_stencil_texturing                              DONE (freedreno, nv50, llvmpipe, softpipe, swr)
-  GL_ARB_texture_multisample (Multisample textures)     DONE (freedreno/a5xx, i965/gen7+, nv50, llvmpipe, softpipe)
+  GL_ARB_texture_multisample (Multisample textures)     DONE (i965/gen7+, nv50, llvmpipe, softpipe)
   GL_ARB_texture_storage_multisample                    DONE (all drivers that support GL_ARB_texture_multisample)
   GL_ARB_vertex_attrib_binding                          DONE (all drivers)
-  GS5 Enhanced textureGather                            DONE (freedreno, i965/gen7+)
-  GS5 Packing/bitfield/conversion functions             DONE (freedreno/a5xx, i965/gen6+)
+  GS5 Enhanced textureGather                            DONE (freedreno, i965/gen7+,)
+  GS5 Packing/bitfield/conversion functions             DONE (i965/gen6+)
   GL_EXT_shader_integer_mix                             DONE (all drivers that support GLSL)
 
   Additional functionality not covered above:
@@ -269,28 +269,28 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi, virgl
       glGetBooleani_v - restrict to GLES enums
       gl_HelperInvocation support                       DONE (i965, r600)
 
-GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+, radeonsi, virgl
+GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+
 
   GL_EXT_color_buffer_float                             DONE (all drivers)
-  GL_KHR_blend_equation_advanced                        DONE (i965, nvc0)
+  GL_KHR_blend_equation_advanced                        DONE (i965, nvc0, radeonsi)
   GL_KHR_debug                                          DONE (all drivers)
-  GL_KHR_robustness                                     DONE (i965, nvc0)
+  GL_KHR_robustness                                     DONE (i965, nvc0, radeonsi)
   GL_KHR_texture_compression_astc_ldr                   DONE (freedreno, i965/gen9+)
   GL_OES_copy_image                                     DONE (all drivers)
   GL_OES_draw_buffers_indexed                           DONE (all drivers that support GL_ARB_draw_buffers_blend)
   GL_OES_draw_elements_base_vertex                      DONE (all drivers)
-  GL_OES_geometry_shader                                DONE (i965/hsw+, nvc0)
+  GL_OES_geometry_shader                                DONE (i965/hsw+, nvc0, radeonsi)
   GL_OES_gpu_shader5                                    DONE (all drivers that support GL_ARB_gpu_shader5)
-  GL_OES_primitive_bounding_box                         DONE (i965/gen7+, nvc0)
-  GL_OES_sample_shading                                 DONE (i965, nvc0, r600)
-  GL_OES_sample_variables                               DONE (i965, nvc0, r600)
+  GL_OES_primitive_bounding_box                         DONE (i965/gen7+, nvc0, radeonsi)
+  GL_OES_sample_shading                                 DONE (i965, nvc0, r600, radeonsi)
+  GL_OES_sample_variables                               DONE (i965, nvc0, r600, radeonsi)
   GL_OES_shader_image_atomic                            DONE (all drivers that support GL_ARB_shader_image_load_store)
   GL_OES_shader_io_blocks                               DONE (All drivers that support GLES 3.1)
-  GL_OES_shader_multisample_interpolation               DONE (i965, nvc0, r600)
+  GL_OES_shader_multisample_interpolation               DONE (i965, nvc0, r600, radeonsi)
   GL_OES_tessellation_shader                            DONE (all drivers that support GL_ARB_tessellation_shader)
   GL_OES_texture_border_clamp                           DONE (all drivers)
-  GL_OES_texture_buffer                                 DONE (freedreno, i965, nvc0)
-  GL_OES_texture_cube_map_array                         DONE (i965/hsw+, nvc0)
+  GL_OES_texture_buffer                                 DONE (i965, nvc0, radeonsi)
+  GL_OES_texture_cube_map_array                         DONE (i965/hsw+, nvc0, radeonsi)
   GL_OES_texture_stencil8                               DONE (all drivers that support GL_ARB_texture_stencil8)
   GL_OES_texture_storage_multisample_2d_array           DONE (all drivers that support GL_ARB_texture_multisample)
 
@@ -299,17 +299,17 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_bindless_texture                               DONE (nvc0, radeonsi)
   GL_ARB_cl_event                                       not started
   GL_ARB_compute_variable_group_size                    DONE (nvc0, radeonsi)
-  GL_ARB_ES3_2_compatibility                            DONE (i965/gen8+, radeonsi, virgl)
-  GL_ARB_fragment_shader_interlock                      DONE (i965)
+  GL_ARB_ES3_2_compatibility                            DONE (i965/gen8+)
+  GL_ARB_fragment_shader_interlock                      not started
   GL_ARB_gpu_shader_int64                               DONE (i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe)
   GL_ARB_parallel_shader_compile                        not started, but Chia-I Wu did some related work in 2014
-  GL_ARB_post_depth_coverage                            DONE (i965, nvc0)
+  GL_ARB_post_depth_coverage                            DONE (i965)
   GL_ARB_robustness_isolation                           not started
-  GL_ARB_sample_locations                               DONE (nvc0)
-  GL_ARB_seamless_cubemap_per_texture                   DONE (freedreno, i965, nvc0, radeonsi, r600, softpipe, swr, virgl)
+  GL_ARB_sample_locations                               not started
+  GL_ARB_seamless_cubemap_per_texture                   DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
   GL_ARB_shader_ballot                                  DONE (i965/gen8+, nvc0, radeonsi)
   GL_ARB_shader_clock                                   DONE (i965/gen7+, nv50, nvc0, r600, radeonsi)
-  GL_ARB_shader_stencil_export                          DONE (i965/gen9+, r600, radeonsi, softpipe, llvmpipe, swr, virgl)
+  GL_ARB_shader_stencil_export                          DONE (i965/gen9+, r600, radeonsi, softpipe, llvmpipe, swr)
   GL_ARB_shader_viewport_layer_array                    DONE (i965/gen6+, nvc0, radeonsi)
   GL_ARB_sparse_buffer                                  DONE (radeonsi/CIK+)
   GL_ARB_sparse_texture                                 not started
@@ -322,14 +322,12 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_EXT_semaphore                                      DONE (radeonsi)
   GL_EXT_semaphore_fd                                   DONE (radeonsi)
   GL_EXT_semaphore_win32                                not started
-  GL_EXT_texture_norm16                                 DONE (i965, r600, radeonsi, nvc0)
   GL_KHR_blend_equation_advanced_coherent               DONE (i965/gen9+)
   GL_KHR_texture_compression_astc_hdr                   DONE (i965/bxt)
   GL_KHR_texture_compression_astc_sliced_3d             DONE (i965/gen9+)
   GL_OES_depth_texture_cube_map                         DONE (all drivers that support GLSL 1.30+)
   GL_OES_EGL_image                                      DONE (all drivers)
-  GL_OES_EGL_image_external                             DONE (all drivers)
-  GL_OES_EGL_image_external_essl3                       DONE (all drivers)
+  GL_OES_EGL_image_external_essl3                       not started
   GL_OES_required_internalformat                        DONE (all drivers)
   GL_OES_surfaceless_context                            DONE (all drivers)
   GL_OES_texture_compression_astc                       DONE (core only)
@@ -337,7 +335,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_OES_texture_float_linear                           DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
   GL_OES_texture_half_float                             DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
   GL_OES_texture_half_float_linear                      DONE (freedreno, i965, r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe)
-  GL_OES_texture_view                                   DONE (i965/gen8+)
+  GL_OES_texture_view                                   not started - based on GL_ARB_texture_view
   GL_OES_viewport_array                                 DONE (i965, nvc0, radeonsi)
   GLX_ARB_context_flush_control                         not started
   GLX_ARB_robustness_application_isolation              not started
@@ -354,55 +352,39 @@ we DO NOT WANT implementations of these extensions for Mesa.
 
 Vulkan 1.0 -- all DONE: anv, radv
 
-Vulkan 1.1 -- all DONE: anv, radv
-
+Khronos extensions that are not part of any Vulkan version:
   VK_KHR_16bit_storage                                  in progress (Alejandro)
-  VK_KHR_bind_memory2                                   DONE (anv, radv)
+  VK_KHR_android_surface                                not started
   VK_KHR_dedicated_allocation                           DONE (anv, radv)
   VK_KHR_descriptor_update_template                     DONE (anv, radv)
-  VK_KHR_device_group                                   not started
-  VK_KHR_device_group_creation                          not started
-  VK_KHR_external_fence                                 DONE (anv, radv)
-  VK_KHR_external_fence_capabilities                    DONE (anv, radv)
+  VK_KHR_display                                        not started
+  VK_KHR_display_swapchain                              not started
+  VK_KHR_external_fence                                 not started
+  VK_KHR_external_fence_capabilities                    not started
+  VK_KHR_external_fence_fd                              not started
+  VK_KHR_external_fence_win32                           not started
   VK_KHR_external_memory                                DONE (anv, radv)
   VK_KHR_external_memory_capabilities                   DONE (anv, radv)
-  VK_KHR_external_semaphore                             DONE (anv, radv)
-  VK_KHR_external_semaphore_capabilities                DONE (anv, radv)
-  VK_KHR_get_memory_requirements2                       DONE (anv, radv)
-  VK_KHR_get_physical_device_properties2                DONE (anv, radv)
-  VK_KHR_maintenance1                                   DONE (anv, radv)
-  VK_KHR_maintenance2                                   DONE (anv, radv)
-  VK_KHR_maintenance3                                   DONE (anv, radv)
-  VK_KHR_multiview                                      DONE (anv, radv)
-  VK_KHR_relaxed_block_layout                           DONE (anv, radv)
-  VK_KHR_sampler_ycbcr_conversion                       DONE (anv)
-  VK_KHR_shader_draw_parameters                         DONE (anv, radv)
-  VK_KHR_storage_buffer_storage_class                   DONE (anv, radv)
-  VK_KHR_variable_pointers                              DONE (anv, radv)
-
-Khronos extensions that are not part of any Vulkan version:
-  VK_KHR_8bit_storage                                   DONE (anv)
-  VK_KHR_android_surface                                not started
-  VK_KHR_create_renderpass2                             DONE (anv, radv)
-  VK_KHR_display                                        DONE (anv, radv)
-  VK_KHR_display_swapchain                              DONE (anv, radv)
-  VK_KHR_draw_indirect_count                            DONE (radv)
-  VK_KHR_external_fence_fd                              DONE (anv, radv)
-  VK_KHR_external_fence_win32                           not started
   VK_KHR_external_memory_fd                             DONE (anv, radv)
   VK_KHR_external_memory_win32                          not started
-  VK_KHR_external_semaphore_fd                          DONE (anv, radv)
+  VK_KHR_external_semaphore                             DONE (radv)
+  VK_KHR_external_semaphore_capabilities                DONE (radv)
+  VK_KHR_external_semaphore_fd                          DONE (radv)
   VK_KHR_external_semaphore_win32                       not started
-  VK_KHR_get_display_properties2                        DONE (anv, radv)
-  VK_KHR_get_surface_capabilities2                      DONE (anv, radv)
-  VK_KHR_image_format_list                              DONE (anv, radv)
+  VK_KHR_get_memory_requirements2                       DONE (anv, radv)
+  VK_KHR_get_physical_device_properties2                DONE (anv, radv)
+  VK_KHR_get_surface_capabilities2                      DONE (anv)
   VK_KHR_incremental_present                            DONE (anv, radv)
+  VK_KHR_maintenance1                                   DONE (anv, radv)
   VK_KHR_mir_surface                                    not started
   VK_KHR_push_descriptor                                DONE (anv, radv)
   VK_KHR_sampler_mirror_clamp_to_edge                   DONE (anv, radv)
+  VK_KHR_shader_draw_parameters                         DONE (anv, radv)
   VK_KHR_shared_presentable_image                       not started
+  VK_KHR_storage_buffer_storage_class                   DONE (anv, radv)
   VK_KHR_surface                                        DONE (anv, radv)
   VK_KHR_swapchain                                      DONE (anv, radv)
+  VK_KHR_variable_pointers                              DONE (anv, radv)
   VK_KHR_wayland_surface                                DONE (anv, radv)
   VK_KHR_win32_keyed_mutex                              not started
   VK_KHR_win32_surface                                  not started

docs/index.html

@@ -16,71 +16,6 @@
 
 <h1>News</h1>
 
-<h2>July 27, 2018</h2>
-<p>
-<a href="relnotes/18.1.5.html">Mesa 18.1.5</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>July 13, 2018</h2>
-<p>
-<a href="relnotes/18.1.4.html">Mesa 18.1.4</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>June 29, 2018</h2>
-<p>
-<a href="relnotes/18.1.3.html">Mesa 18.1.3</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>June 15, 2018</h2>
-<p>
-<a href="relnotes/18.1.2.html">Mesa 18.1.2</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>June 3, 2018</h2>
-<p>
-<a href="relnotes/18.0.5.html">Mesa 18.0.5</a> is released.
-This is a bug-fix release.
-<br>
-NOTE: It is anticipated that 18.0.5 will be the final release in the
-18.0 series. Users of 18.0 are encouraged to migrate to the 18.1
-series in order to obtain future fixes.
-</p>
-
-<h2>June 1, 2018</h2>
-<p>
-<a href="relnotes/18.1.1.html">Mesa 18.1.1</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>May 18, 2018</h2>
-<p>
-<a href="relnotes/18.1.0.html">Mesa 18.1.0</a> is released.  This is a
-new development release.  See the release notes for more information
-about the release.
-</p>
-
-<h2>May 17, 2018</h2>
-<p>
-<a href="relnotes/18.0.4.html">Mesa 18.0.4</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>May 7, 2018</h2>
-<p>
-<a href="relnotes/18.0.3.html">Mesa 18.0.3</a> is released.
-This is a bug-fix release.
-</p>
-
-<h2>April 28, 2018</h2>
-<p>
-<a href="relnotes/18.0.2.html">Mesa 18.0.2</a> is released.
-This is a bug-fix release.
-</p>
-
 <h2>April 18, 2018</h2>
 <p>
 <a href="relnotes/18.0.1.html">Mesa 18.0.1</a> is released.

docs/meson.html

@@ -24,7 +24,10 @@ for production</strong></p>
 <p>The meson build is tested on on Linux, macOS, Cygwin and Haiku, it should
 work on FreeBSD, DragonflyBSD, NetBSD, and OpenBSD.</p>
 
-<p><strong>Mesa requires Meson >= 0.44.1 to build.</strong>
+<p><strong>Mesa requires Meson >= 0.42.0 to build in general.</strong>
+
+Additionaly, to build the Clover OpenCL state tracker or the OpenSWR driver
+meson 0.44.0 or greater is required.
 
 Some older versions of meson do not check that they are too old and will error
 out in odd ways.
@@ -33,7 +36,7 @@ out in odd ways.
 <p>
 The meson program is used to configure the source directory and generates
 either a ninja build file or Visual Studio® build files. The latter must
-be enabled via the <code>--backend</code> switch, as ninja is the default backend on all
+be enabled via the --backend switch, as ninja is the default backend on all
 operating systems. Meson only supports out-of-tree builds, and must be passed a
 directory to put built and generated sources into. We'll call that directory
 "build" for examples.
@@ -49,7 +52,7 @@ along with a build directory to view the selected options for. This will show
 your meson global arguments and project arguments, along with their defaults
 and your local settings.
 
-Meson does not currently support listing options before configure a build
+Moes does not currently support listing options before configure a build
 directory, but this feature is being discussed upstream.
 </p>
 
@@ -60,21 +63,13 @@ directory, but this feature is being discussed upstream.
 <p>
 With additional arguments <code>meson configure</code> is used to change
 options on already configured build directory. All options passed to this
-command are in the form <code>-D "command"="value"</code>.
+command are in the form -D "command"="value".
 </p>
 
 <pre>
     meson configure build/ -Dprefix=/tmp/install -Dglx=true
 </pre>
 
-<p>
-Note that options taking lists (such as <code>platforms</code>) are
-<a href="http://mesonbuild.com/Build-options.html#using-build-options">a bit
-more complicated</a>, but the simplest form compatible with Mesa options
-is to use a comma to separate values (<code>-D platforms=drm,wayland</code>)
-and brackets to represent an empty list (<code>-D platforms=[]</code>).
-</p>
-
 <p>
 Once you've run the initial <code>meson</code> command successfully you can use
 your configured backend to build the project. With ninja, the -C option can be
@@ -90,14 +85,13 @@ Without arguments, it will produce libGL.so and/or several other libraries
 depending on the options you have chosen. Later, if you want to rebuild for a
 different configuration, you should run <code>ninja clean</code> before
 changing the configuration, or create a new out of tree build directory for
-each configuration you want to build
-<a href="http://mesonbuild.com/Using-multiple-build-directories.html">as
-recommended in the documentation</a>
+each configuration you want to build.
+
+http://mesonbuild.com/Using-multiple-build-directories.html
 </p>
 
-<dl>
 <dt><code>Environment Variables</code></dt>
-<dd><p>Meson supports the standard CC and CXX environment variables for
+<dd><p>Meson supports the standard CC and CXX envrionment variables for
 changing the default compiler, and CFLAGS, CXXFLAGS, and LDFLAGS for setting
 options to the compiler and linker.
 
@@ -108,9 +102,9 @@ the popular compilers, a complete list is available
 These arguments are consumed and stored by meson when it is initialized or
 re-initialized. Therefore passing them to meson configure will not do anything,
 and passing them to ninja will only do something if ninja decides to
-re-initialize meson, for example, if a meson.build file has been changed.
+re-initialze meson, for example, if a meson.build file has been changed.
 Changing these variables will not cause all targets to be rebuilt, so running
-ninja clean is recommended when changing CFLAGS or CXXFLAGS. Meson will never
+ninja clean is recomended when changing CFLAGS or CXXFLAGS. meson will never
 change compiler in a configured build directory.
 </p>
 
@@ -122,13 +116,14 @@ change compiler in a configured build directory.
     CFLAGS=-Wno-typedef-redefinition ninja -C build-clang
 </pre>
 
-<p>Meson also honors <code>DESTDIR</code> for installs</p>
+<p>Meson also honors DESTDIR for installs</p>
 </dd>
 
 
+<dl>
 <dt><code>LLVM</code></dt>
 <dd><p>Meson includes upstream logic to wrap llvm-config using it's standard
-dependency interface. It will search <code>$PATH</code> (or <code>%PATH%</code> on windows) for
+dependncy interface. It will search $PATH (or %PATH% on windows) for
 llvm-config, so using an LLVM from a non-standard path is as easy as
 <code>PATH=/path/with/llvm-config:$PATH meson build</code>.
 </p></dd>
@@ -151,7 +146,7 @@ One of the oddities of meson is that some options are different when passed to
 the <code>meson</code> than to <code>meson configure</code>. These options are
 passed as --option=foo to <code>meson</code>, but -Doption=foo to <code>meson
 configure</code>. Mesa defined options are always passed as -Doption=foo.
-</p>
+<p>
 
 <p>For those coming from autotools be aware of the following:</p>
 
@@ -160,13 +155,13 @@ configure</code>. Mesa defined options are always passed as -Doption=foo.
 <dd><p>This option will set the compiler debug/optimisation levels to aid
 debugging the Mesa libraries.</p>
 
-<p>Note that in meson this defaults to <code>debugoptimized</code>, and
-not setting it to <code>release</code> will yield non-optimal
-performance and binary size. Not using <code>debug</code> may interfere
-with debugging as some code and validation will be optimized away.
+<p>Note that in meson this defaults to "debugoptimized", and  not setting it to
+"release" will yield non-optimal performance and binary size. Not using "debug"
+may interfer with debbugging as some code and validation will be optimized
+away.
 </p>
 
-<p> For those wishing to pass their own optimization flags, use the <code>plain</code>
+<p> For those wishing to pass their own optimization flags, use the "plain"
 buildtype, which causes meson to inject no additional compiler arguments, only
 those in the C/CXXFLAGS and those that mesa itself defines.</p>
 </dd>
@@ -174,14 +169,10 @@ those in the C/CXXFLAGS and those that mesa itself defines.</p>
 
 <dl>
 <dt><code>-Db_ndebug</code></dt>
-<dd><p>This option controls assertions in meson projects. When set to <code>false</code>
+<dd><p>This option controls assertions in meson projects. When set to false
 (the default) assertions are enabled, when set to true they are disabled. This
 is unrelated to the <code>buildtype</code>; setting the latter to
 <code>release</code> will not turn off assertions.
 </p>
 </dd>
 </dl>
-
-</div>
-</body>
-</html>

docs/patents.txt

@@ -0,0 +1,31 @@
+ARB_texture_float:
+
+    Silicon Graphics, Inc. owns US Patent #6,650,327, issued November 18,
+    2003 [1].
+
+    SGI believes this patent contains necessary IP for graphics systems
+    implementing floating point rasterization and floating point
+    framebuffer capabilities described in ARB_texture_float extension, and
+    will discuss licensing on RAND terms, on an individual basis with
+    companies wishing to use this IP in the context of conformant OpenGL
+    implementations [2].
+
+    The source code to implement ARB_texture_float extension is included
+    and can be toggled on at compile time, for those who purchased a
+    license from SGI, or are in a country where the patent does not apply,
+    etc.
+
+    The software is provided "as is", without warranty of any kind, express
+    or implied, including but not limited to the warranties of
+    merchantability, fitness for a particular purpose and noninfringement.
+    In no event shall the authors or copyright holders be liable for any
+    claim, damages or other liability, whether in an action of contract,
+    tort or otherwise, arising from, out of or in connection with the
+    software or the use or other dealings in the software.
+
+    You should contact a lawyer or SGI's legal department if you want to
+    enable this extension.
+
+
+[1] https://patents.google.com/patent/US6650327B1
+[2] https://www.opengl.org/registry/specs/ARB/texture_float.txt

docs/precompiled.html

@@ -24,12 +24,10 @@ Some Linux distributions closely follow the latest Mesa releases. On others one
 has to use unofficial channels.
 <br>
 There are some general directions:
-<ul>
 <li>Debian/Ubuntu based distros - PPA: xorg-edgers, oibaf and padoka</li>
 <li>Fedora - Corp: erp and che</li>
 <li>OpenSuse/SLES - OBS: X11:XOrg and pontostroy:X11</li>
 <li>Gentoo/Archlinux - officially provided/supported</li>
-</ul>
 </p>
 
 </div>

docs/release-calendar.html

@@ -37,47 +37,95 @@ if you'd like to nominate a patch in the next stable release.
 <th>Release</th>
 <th>Release manager</th>
 <th>Notes</th>
+<tr>
+<td rowspan="3">18.0</td>
+<td>2018-04-20</td>
+<td>18.0.2</td>
+<td>Juan A. Suarez Romero</td>
+<td></td>
 </tr>
 <tr>
-<td rowspan="3">18.1</td>
-<td>2018-08-10</td>
-<td>18.1.6</td>
+<td>2018-05-04</td>
+<td>18.0.3</td>
+<td>Juan A. Suarez Romero</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-05-18</td>
+<td>18.0.4</td>
+<td>Juan A. Suarez Romero</td>
+<td>Last planned 18.0.x release</td>
+</tr>
+<tr>
+<td rowspan="8">18.1</td>
+<td>2018-04-20</td>
+<td>18.1.0rc1</td>
 <td>Dylan Baker</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-08-24</td>
-<td>18.1.7</td>
+<td>2018-04-27</td>
+<td>18.1.0rc2</td>
 <td>Dylan Baker</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-09-07</td>
-<td>18.1.8</td>
+<td>2018-05-04</td>
+<td>18.1.0rc3</td>
 <td>Dylan Baker</td>
-<td>Last planned 18.1.x release</td>
+<td></td>
+</tr>
+<tr>
+<td>2018-05-11</td>
+<td>18.1.0rc4</td>
+<td>Dylan Baker</td>
+<td>Last planned RC/Final release</td>
+</tr>
+<tr>
+<td>TBD</td>
+<td>18.1.1</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>TBD</td>
+<td>18.1.2</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>TBD</td>
+<td>18.1.3</td>
+<td>Emil Velikov</td>
+<td></td>
+</tr>
+<tr>
+<td>TBD</td>
+<td>18.1.4</td>
+<td>Emil Velikov</td>
+<td>Last planned RC/Final release</td>
 </tr>
 <tr>
 <td rowspan="4">18.2</td>
-<td>2018-08-01</td>
+<td>2018-07-20</td>
 <td>18.2.0rc1</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-08-08</td>
+<td>2018-07-27</td>
 <td>18.2.0rc2</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-08-15</td>
+<td>2018-08-03</td>
 <td>18.2.0rc3</td>
 <td>Andres Gomez</td>
 <td></td>
 </tr>
 <tr>
-<td>2018-08-22</td>
+<td>2018-08-10</td>
 <td>18.2.0rc4</td>
 <td>Andres Gomez</td>
 <td>Last planned RC/Final release</td>

docs/releasing.html

@@ -54,8 +54,8 @@ For example:
 <h1 id="schedule">Release schedule</h1>
 
 <p>
-Releases should happen on Wednesdays. Delays can occur although those
-should be keep to a minimum.
+Releases should happen on Fridays. Delays can occur although those should be keep
+to a minimum.
 <br>
 See our <a href="release-calendar.html" target="_parent">calendar</a> for the
 date and other details for individual releases.

docs/relnotes.html

@@ -21,16 +21,7 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>
 
 <ul>
-<li><a href="relnotes/18.1.5.html">18.1.5 release notes</a>
-<li><a href="relnotes/18.1.4.html">18.1.4 release notes</a>
-<li><a href="relnotes/18.1.3.html">18.1.3 release notes</a>
-<li><a href="relnotes/18.1.2.html">18.1.2 release notes</a>
-<li><a href="relnotes/18.0.5.html">18.0.5 release notes</a>
-<li><a href="relnotes/18.1.1.html">18.1.1 release notes</a>
 <li><a href="relnotes/18.1.0.html">18.1.0 release notes</a>
-<li><a href="relnotes/18.0.4.html">18.0.4 release notes</a>
-<li><a href="relnotes/18.0.3.html">18.0.3 release notes</a>
-<li><a href="relnotes/18.0.2.html">18.0.2 release notes</a>
 <li><a href="relnotes/18.0.1.html">18.0.1 release notes</a>
 <li><a href="relnotes/17.3.9.html">17.3.9 release notes</a>
 <li><a href="relnotes/17.3.8.html">17.3.8 release notes</a>

docs/relnotes/18.0.0.html

@@ -48,8 +48,8 @@ Note: some of the new features are only available with certain drivers.
 <li>Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE environment variable is set to "0" or "false"</li>
 <li>GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on r600/evergreen+</li>
 <li>GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on r600/evergreen+</li>
-<li>GL_ARB_shader_storage_buffer_object on r600/evergreen+</li>
-<li>GL_ARB_compute_shader on r600/evergreen+</li>
+<li>GL_ARB_shader_storage_buffer_object on r600/evergreen+<li>
+<li>GL_ARB_compute_shader on r600/evergreen+<li>
 <li>GL_ARB_cull_distance on r600/evergreen+</li>
 <li>GL_ARB_enhanced_layouts on r600/evergreen+</li>
 <li>GL_ARB_bindless_texture on nvc0/kepler</li>

docs/relnotes/18.0.2.html

@@ -1,144 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.2 Release Notes / April 28, 2018</h1>
-
-<p>
-Mesa 18.0.2 is a bug fix release which fixes bugs found since the 18.0.1 release.
-</p>
-<p>
-Mesa 18.0.2 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-SHA256: ffd8dfe3337b474a3baa085f0e7ef1a32c7cdc3bed1ad810b2633919a9324840  mesa-18.0.2.tar.gz
-SHA256: 98fa159768482dc568b9f8bf0f36c7acb823fa47428ffd650b40784f16b9e7b3  mesa-18.0.2.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=95009">Bug 95009</a> - [SNB] amd_shader_trinary_minmax.execution.built-in-functions.gs-mid3-ivec2-ivec2-ivec2 intermittent</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=95012">Bug 95012</a> - [SNB] glsl-1_50.execution.built-in-functions.gs-op tests intermittent</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98281">Bug 98281</a> - 'message's in ctx-&gt;Debug.LogMessages[] seem to leak.</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105320">Bug 105320</a> - Storage texel buffer access produces wrong results (RX Vega)</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105775">Bug 105775</a> - SI reaches the maximum IB size in dwords and fail to submit</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105994">Bug 105994</a> - surface state leak when creating and destroying image views with aspectMask depth and stencil</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106074">Bug 106074</a> - radv: si_scissor_from_viewport returns incorrect result when using half-pixel viewport offset</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106126">Bug 106126</a> - eglMakeCurrent does not always ensure dri_drawable-&gt;update_drawable_info has been called for a new EGLSurface if another has been created and destroyed first</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.</li>
-  <li>radv: Mark GTT memory as device local for APUs.</li>
-</ul>
-
-<p>Dylan Baker (2):</p>
-<ul>
-  <li>bin/install_megadrivers: fix DESTDIR and -D*-path</li>
-  <li>meson: don't build classic mesa tests without dri_drivers</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>intel/compiler: Add scheduler deps for instructions that implicitly read g0</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_*</li>
-</ul>
-
-<p>Johan Klokkhammer Helsing (1):</p>
-<ul>
-  <li>st/dri: Fix dangling pointer to a destroyed dri_drawable</li>
-</ul>
-
-<p>Juan A. Suarez Romero (4):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.1</li>
-  <li>travis: radv needs LLVM 4.0</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>Update version to 18.0.2</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Fix shadow batches to be the same size as the real BO.</li>
-</ul>
-
-<p>Lionel Landwerlin (1):</p>
-<ul>
-  <li>anv: fix number of planes for depth &amp; stencil</li>
-</ul>
-
-<p>Lucas Stach (1):</p>
-<ul>
-  <li>etnaviv: fix texture_format_needs_swiz</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>radeonsi/gfx9: fix a hang with an empty first IB</li>
-  <li>glsl_to_tgsi: try harder to lower unsupported ir_binop_vector_extract</li>
-  <li>Revert "st/dri: Fix dangling pointer to a destroyed dri_drawable"</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>radv: fix scissor computation when using half-pixel viewport offset</li>
-  <li>radv/winsys: allow to submit up to 4 IBs for chips without chaining</li>
-</ul>
-
-<p>Thomas Hellstrom (1):</p>
-<ul>
-  <li>svga: Fix incorrect advertizing of EGL_KHR_gl_colorspace</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>mesa: free debug messages when destroying the debug state</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.3.html

@@ -1,107 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.3 Release Notes / May 7, 2018</h1>
-
-<p>
-Mesa 18.0.3 is a bug fix release which fixes bugs found since the 18.0.2 release.
-</p>
-<p>
-Mesa 18.0.3 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-58cc5c5b1ab2a44e6e47f18ef6c29836ad06f95450adce635ce3c317507a171b  mesa-18.0.3.tar.gz
-099d9667327a76a61741a533f95067d76ea71a656e66b91507b3c0caf1d49e30  mesa-18.0.3.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105374">Bug 105374</a> - texture3d, a SaschaWillems demo, assert fails</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106147">Bug 106147</a> - SIGBUS in write_reloc() when Sacha Willems' &quot;texture3d&quot; Vulkan demo starts</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Andres Rodriguez (1):</p>
-<ul>
-  <li>radv/winsys: fix leaking resources from bo's imported by fd</li>
-</ul>
-
-<p>Boyuan Zhang (1):</p>
-<ul>
-  <li>radeon/vcn: fix mpeg4 msg buffer settings</li>
-</ul>
-
-<p>Eric Anholt (1):</p>
-<ul>
-  <li>gallium/util: Fix incorrect refcounting of separate stencil.</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>anv/allocator: Don't shrink either end of the block pool</li>
-</ul>
-
-<p>Juan A. Suarez Romero (3):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.2</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>Update version to 18.0.3</li>
-</ul>
-
-<p>Leo Liu (1):</p>
-<ul>
-  <li>st/omx/enc: fix blit setup for YUV LoadImage</li>
-</ul>
-
-<p>Marek Olšák (2):</p>
-<ul>
-  <li>util/u_queue: fix a deadlock in util_queue_finish</li>
-  <li>radeonsi/gfx9: workaround for INTERP with indirect indexing</li>
-</ul>
-
-<p>Nanley Chery (1):</p>
-<ul>
-  <li>i965/tex_image: Avoid the ASTC LDR workaround on gen9lp</li>
-</ul>
-
-<p>Samuel Pitoiset (1):</p>
-<ul>
-  <li>radv: compute the number of subpass attachments correctly</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.4.html

@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.4 Release Notes / May 17, 2018</h1>
-
-<p>
-Mesa 18.0.4 is a bug fix release which fixes bugs found since the 18.0.3 release.
-</p>
-<p>
-Mesa 18.0.4 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  mesa-18.0.4.tar.gz
-1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  mesa-18.0.4.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91808">Bug 91808</a> - trine1 misrender r600g</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100430">Bug 100430</a> - [radv] graphical glitches on dolphin emulator</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106243">Bug 106243</a> - [kbl] GPU HANG: 9:0:0x85dffffb, in Cinnamon</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106480">Bug 106480</a> - A2B10G10R10_SNORM vertex attribute doesn't work.</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Bas Nieuwenhuizen (3):</p>
-<ul>
-  <li>radv: Translate logic ops.</li>
-  <li>radv: Fix up 2_10_10_10 alpha sign.</li>
-  <li>radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.</li>
-</ul>
-
-<p>Dave Airlie (3):</p>
-<ul>
-  <li>r600: fix constant buffer bounds.</li>
-  <li>radv: resolve all layers in compute resolve path.</li>
-  <li>radv: use compute path for multi-layer images.</li>
-</ul>
-
-<p>Deepak Rawat (1):</p>
-<ul>
-  <li>egl/x11: Send invalidate to driver on copy_region path in swap_buffer</li>
-</ul>
-
-<p>Ian Romanick (1):</p>
-<ul>
-  <li>mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)</li>
-</ul>
-
-<p>Jan Vesely (8):</p>
-<ul>
-  <li>clover: Add explicit virtual destructor to argument class</li>
-  <li>eg/compute: Drop reference on code_bo in destructor.</li>
-  <li>r600: Cleanup constant buffers on context destruction</li>
-  <li>eg/compute: Drop reference to kernel_param bo in destructor</li>
-  <li>pipe-loader: Free driver_name in error path</li>
-  <li>gallium/auxiliary: Add helper function to count the number of entries in hash table</li>
-  <li>winsys/radeon: Destroy fd_hash table when the last winsys is removed.</li>
-  <li>winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.</li>
-</ul>
-
-<p>Jason Ekstrand (1):</p>
-<ul>
-  <li>i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL</li>
-</ul>
-
-<p>Jose Maria Casanova Crespo (2):</p>
-<ul>
-  <li>intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate</li>
-  <li>intel/compiler: fix brw_imm_w for negative 16-bit integers</li>
-</ul>
-
-<p>Juan A. Suarez Romero (7):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.3</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>cherry-ignore: glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug</li>
-  <li>cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs</li>
-  <li>cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT</li>
-  <li>cherry-ignore: radv/resolve: do fmask decompress on all layers.</li>
-  <li>Update version to 18.0.4</li>
-</ul>
-
-<p>Kai Wasserbäch (1):</p>
-<ul>
-  <li>opencl: autotools: Fix linking order for OpenCL target</li>
-</ul>
-
-<p>Kenneth Graunke (1):</p>
-<ul>
-  <li>i965: Don't leak blorp on Gen4-5.</li>
-</ul>
-
-<p>Lionel Landwerlin (2):</p>
-<ul>
-  <li>i965: require pixel scoreboard stall prior to ISP disable</li>
-  <li>anv: emit pixel scoreboard stall before ISP disable</li>
-</ul>
-
-<p>Matthew Nicholls (1):</p>
-<ul>
-  <li>radv: fix multisample image copies</li>
-</ul>
-
-<p>Neil Roberts (1):</p>
-<ul>
-  <li>spirv: Apply OriginUpperLeft to FragCoord</li>
-</ul>
-
-<p>Rhys Perry (1):</p>
-<ul>
-  <li>mesa: fix error handling in get_framebuffer_parameteriv</li>
-</ul>
-
-<p>Ross Burton (1):</p>
-<ul>
-  <li>src/intel/Makefile.vulkan.am: add missing MKDIR_GEN</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.0.5.html

@@ -1,162 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.0.5 Release Notes / June 3, 2018</h1>
-
-<p>
-Mesa 18.0.5 is a bug fix release which fixes bugs found since the 18.0.4 release.
-</p>
-<p>
-Mesa 18.0.5 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation
-because compatibility contexts are not supported.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-ea3e00329cea899b1e32db812fd2f426832be37e4baa2e2fd9288a3480f30531  mesa-18.0.5.tar.gz
-5187bba8d72aea78f2062d134ec6079a508e8216062dce9ec9048b5eb2c4fc6b  mesa-18.0.5.tar.xz
-</pre>
-
-
-<h2>New features</h2>
-<p>None</p>
-
-
-<h2>Bug fixes</h2>
-
-<ul>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=78097">Bug 78097</a> - glUniform1ui and friends not supported by display lists</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102390">Bug 102390</a> - centroid interpolation causes broken attribute values</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105351">Bug 105351</a> - [Gen6+] piglit's arb_shader_image_load_store-host-mem-barrier fails with a glGetTexSubImage fallback path</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106090">Bug 106090</a> - Compiling compute shader crashes RADV</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106315">Bug 106315</a> - The witness + dxvk suffers flickering garbage</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106465">Bug 106465</a> - No test for Image Load/Store on format-incompatible texture buffer</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106479">Bug 106479</a> - NDEBUG not defined for libamdgpu_addrlib</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106481">Bug 106481</a> - No test for Image Load/Store on texture buffer sized greater than MAX_TEXTURE_BUFFER_SIZE_ARB</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106504">Bug 106504</a> - vulkan SPIR-V parsing failed at ../src/compiler/spirv/vtn_cfg.c:381</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106587">Bug 106587</a> - Dota2 is very dark when using vulkan render on a Intel &lt;&lt; AMD prime setup</li>
-
-<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106629">Bug 106629</a> - [SNB,IVB,HSW,BDW] dEQP-EGL.functional.image.create.gles2_cubemap_negative_z_rgb_read_pixels</li>
-
-</ul>
-
-
-<h2>Changes</h2>
-
-<p>Anuj Phogat (1):</p>
-<ul>
-  <li>i965/glk: Add l3 banks count for 2x6 configuration</li>
-</ul>
-
-<p>Bas Nieuwenhuizen (2):</p>
-<ul>
-  <li>amd/addrlib: Use defines in autotools build.</li>
-  <li>radv: Fix SRGB compute copies.</li>
-</ul>
-
-<p>Dave Airlie (1):</p>
-<ul>
-  <li>tgsi/scan: add hw atomic to the list of memory accessing files</li>
-</ul>
-
-<p>Francisco Jerez (4):</p>
-<ul>
-  <li>Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"</li>
-  <li>i965: Move buffer texture size calculation into a common helper function.</li>
-  <li>i965: Handle non-zero texture buffer offsets in buffer object range calculation.</li>
-  <li>i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.</li>
-</ul>
-
-<p>Jan Vesely (1):</p>
-<ul>
-  <li>eg/compute: Use reference counting to handle compute memory pool.</li>
-</ul>
-
-<p>Jason Ekstrand (2):</p>
-<ul>
-  <li>intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0</li>
-  <li>intel/blorp: Support blits and clears on surfaces with offsets</li>
-</ul>
-
-<p>Jose Dapena Paz (1):</p>
-<ul>
-  <li>mesa: do not leak ctx-&gt;Shader.ReferencedProgram references</li>
-</ul>
-
-<p>Juan A. Suarez Romero (8):</p>
-<ul>
-  <li>docs: add sha256 checksums for 18.0.4</li>
-  <li>cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers</li>
-  <li>cherry-ignore: add explicit 18.1 only nominations</li>
-  <li>cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too</li>
-  <li>cherry-ignore: Tegra is not supported</li>
-  <li>cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)</li>
-  <li>cherry-ignore: nv30: ensure that displayable formats are marked accordingly</li>
-  <li>Update version to 18.0.5</li>
-</ul>
-
-<p>Marek Olšák (3):</p>
-<ul>
-  <li>st/mesa: simplify lastLevel determination in st_finalize_texture</li>
-  <li>radeonsi: fix incorrect parentheses around VS-PS varying elimination</li>
-  <li>mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)</li>
-</ul>
-
-<p>Michel Dänzer (1):</p>
-<ul>
-  <li>dri3: Stricter SBC wraparound handling</li>
-</ul>
-
-<p>Nanley Chery (1):</p>
-<ul>
-  <li>i965/miptree: Zero-initialize CCS_D buffers</li>
-</ul>
-
-<p>Samuel Pitoiset (2):</p>
-<ul>
-  <li>spirv: fix visiting inner loops with same break/continue block</li>
-  <li>radv: fix centroid interpolation</li>
-</ul>
-
-<p>Stuart Young (1):</p>
-<ul>
-  <li>etnaviv: Fix missing rnndb file in tarballs</li>
-</ul>
-
-<p>Timothy Arceri (1):</p>
-<ul>
-  <li>mesa: add glUniform*ui{v} support to display lists</li>
-</ul>
-
-
-</div>
-</body>
-</html>

docs/relnotes/18.1.6.html

@@ -0,0 +1,188 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.6 Release Notes / August 13 2018</h1>
+
+<p>
+Mesa 18.1.6 is a bug fix release which fixes bugs found since the 18.1.5 release.
+</p>
+<p>
+Mesa 18.1.6 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+580e03328ffefe1fd43b19ab7669f20d931601a1c0a4c0f8b9c65d6e81a06df3  mesa-18.1.6.tar.gz
+bb7ce759069801804fcfb8152da3457f76cd7b4e0096e4870ff5adcb5c894289  mesa-18.1.6.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=13728">Bug 13728</a> - [G965] Some objects in Neverwinter Nights Linux version not displayed correctly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98699">Bug 98699</a> - &quot;float[a+++4 ? 1:1] f;&quot; crashes glsl_compiler</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99730">Bug 99730</a> - Metro Redux game(s) needs override for midshader extension declaration</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106382">Bug 106382</a> - Shader cache breaks INTEL_DEBUG=shader_time</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107117">Bug 107117</a> - mesa-18.1: regression with TFP on intel with modesettings and glamor acceleration</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107212">Bug 107212</a> - Dual-Core CPU E5500 / G45: RetroArch with reicast core results in corrupted graphics</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>Adam Jackson (1):</p>
+<ul>
+  <li>glx: GLX_MESA_multithread_makecurrent is direct-only</li>
+</ul>
+
+<p>Andres Gomez (3):</p>
+<ul>
+  <li>ddebug: use util_snprintf() in dd_get_debug_filename_and_mkdir</li>
+  <li>gallium/aux/util: use util_snprintf() in test_texture_barrier</li>
+  <li>glsl: use util_snprintf()</li>
+</ul>
+
+<p>Christian Gmeiner (1):</p>
+<ul>
+  <li>etnaviv: fix typo in query names</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>r600: reduce num compute threads to 1024.</li>
+</ul>
+
+<p>Dylan Baker (6):</p>
+<ul>
+  <li>docs: Add sha-256 sums for 18.1.5</li>
+  <li>nir/meson: fix c vs cpp args for nir test</li>
+  <li>gallium: fix ddebug on windows</li>
+  <li>cherry-ignore: add patches that get-pick-list is finding in error</li>
+  <li>cherry-ignore: Add some additional patches that are for 18.2</li>
+  <li>bump version to 18.1.6</li>
+</ul>
+
+<p>Emil Velikov (5):</p>
+<ul>
+  <li>swr: don't export swr_create_screen_internal</li>
+  <li>automake: require shared glapi when using DRI based libGL</li>
+  <li>autotools: error out when using the broken --with-{gl, osmesa}-lib-name</li>
+  <li>autotools: error out when building with mangling and glvnd</li>
+  <li>autotools: use correct gl.pc LIBS when using glvnd</li>
+</ul>
+
+<p>Eric Anholt (4):</p>
+<ul>
+  <li>vc4: Fix a leak of the no-vertex-elements workaround BO.</li>
+  <li>vc4: Respect a sampler view's first_layer field.</li>
+  <li>vc4: Ignore samplers for finding uniform offsets.</li>
+  <li>egl: Fix leak of X11 pixmaps backing pbuffers in DRI3.</li>
+</ul>
+
+<p>Gert Wollny (1):</p>
+<ul>
+  <li>meson, install_megadrivers: Also remove stale symlinks</li>
+</ul>
+
+<p>Jan Vesely (2):</p>
+<ul>
+  <li>clover: Reduce wait_count in abort path.</li>
+  <li>clover: Don't extend illegal integer types.</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>nir: Take if uses into account in ssa_def_components_read</li>
+  <li>i965/fs: Flag all slots of a flat input as flat</li>
+</ul>
+
+<p>Jon Turney (1):</p>
+<ul>
+  <li>meson: use correct keyword to fix a meson warning</li>
+</ul>
+
+<p>Jordan Justen (2):</p>
+<ul>
+  <li>i965, anv: Use INTEL_DEBUG for disk_cache driver flags</li>
+  <li>i965: Disable shader cache with INTEL_DEBUG=shader_time</li>
+</ul>
+
+<p>Juan A. Suarez Romero (2):</p>
+<ul>
+  <li>wayland/egl: update surface size on window resize</li>
+  <li>wayland/egl: initialize window surface size to window size</li>
+</ul>
+
+<p>Karol Herbst (2):</p>
+<ul>
+  <li>nir/lower_int64: mark all metadata as dirty</li>
+  <li>nvc0/ir: return 0 in imageLoad on incomplete textures</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>ac/surface: fix MSAA corruption on Vega due to FMASK tile swizzle</li>
+</ul>
+
+<p>Mauro Rossi (2):</p>
+<ul>
+  <li>radv: generate entrypoints for VK_ANDROID_native_buffer</li>
+  <li>radv: move vk_format_table.c to generated sources</li>
+</ul>
+
+<p>Olivier Fourdan (1):</p>
+<ul>
+  <li>dri3: For 1.2, use root window instead of pixmap drawable</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>glsl: handle error case with ast_post_inc, ast_post_dec</li>
+</ul>
+
+<p>Vlad Golovkin (1):</p>
+<ul>
+  <li>swr: Remove unnecessary memset call</li>
+</ul>
+
+<p>vadym.shovkoplias (1):</p>
+<ul>
+  <li>drirc: Allow extension midshader for Metro Redux</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/18.1.7.html

@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 18.1.7 Release Notes / August 24 2018</h1>
+
+<p>
+Mesa 18.1.7 is a bug fix release which fixes bugs found since the 18.1.6 release.
+</p>
+<p>
+Mesa 18.1.7 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+
+<p>None</p>
+
+<h2>Bug fixes</h2>
+<ul>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105975">Bug 105975</a> - i965 always reports 0 viewport subpixel bits</li>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107098">Bug 107098</a> - Segfault after munmap(kms_sw_dt-&gt;ro_mapped)</li>
+</ul>
+
+<h2>Changes</h2>
+<p>Alexander Tsoy (1):</p>
+<ul>
+  <li>meson: fix build for egl platform_x11 without dri3 and gbm</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+  <li>radv: Fix missing Android platform define.</li>
+</ul>
+
+<p>Danylo Piliaiev (1):</p>
+<ul>
+  <li>i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>r600/eg: rework atomic counter emission with flushes</li>
+</ul>
+
+<p>Dylan Baker (7):</p>
+<ul>
+  <li>docs: Add sha256 sums for 18.1.6</li>
+  <li>cherry-ignore: Add additional 18.2 only patches</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: Add more 18.2 patches</li>
+  <li>cherry-ignore: Add a couple of patches with &gt; 1 fixes tags</li>
+  <li>cherry-ignore: more 18.2 patches</li>
+  <li>bump version for 18.1.7 release</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>intel: Switch the order of the 2x MSAA sample positions</li>
+  <li>anv/lower_ycbcr: Use the binding array size for bounds checks</li>
+</ul>
+
+<p>Ray Strode (1):</p>
+<ul>
+  <li>gallium/winsys/kms: don't unmap what wasn't mapped</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+  <li>radv/winsys: fix creating the BO list for virtual buffers</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+  <li>radv: add Doom workaround</li>
+</ul>
+
+</div>
+</body>
+</html>

docs/relnotes/18.2.0.html

@@ -1,75 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
-<html lang="en">
-<head>
-  <meta http-equiv="content-type" content="text/html; charset=utf-8">
-  <title>Mesa Release Notes</title>
-  <link rel="stylesheet" type="text/css" href="../mesa.css">
-</head>
-<body>
-
-<div class="header">
-  <h1>The Mesa 3D Graphics Library</h1>
-</div>
-
-<iframe src="../contents.html"></iframe>
-<div class="content">
-
-<h1>Mesa 18.2.0 Release Notes / TBD</h1>
-
-<p>
-Mesa 18.2.0 is a new development release. People who are concerned
-with stability and reliability should stick with a previous release or
-wait for Mesa 18.2.1.
-</p>
-<p>
-Mesa 18.2.0 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is <strong>only</strong> available if requested at context creation.
-Compatibility contexts may report a lower version depending on each driver.
-</p>
-
-<p>
-libwayland-egl is now distributed by Wayland (since 1.15,
-<a href="https://lists.freedesktop.org/archives/wayland-devel/2018-April/037767.html">see announcement</a>),
-and has been removed from Mesa in this release. Make sure you're using
-an up-to-date version of Wayland to keep the functionality.
-</p>
-
-
-<h2>SHA256 checksums</h2>
-<pre>
-TBD.
-</pre>
-
-
-<h2>New features</h2>
-
-<p>
-Note: some of the new features are only available with certain drivers.
-</p>
-
-<ul>
-<li>OpenGL 4.3 on virgl</li>
-<li>OpenGL 4.4 Compatibility profile on radeonsi</li>
-<li>OpenGL ES 3.2 on radeonsi and virgl</li>
-<li>GL_ARB_ES3_2_compatibility on radeonsi</li>
-<li>GL_ARB_fragment_shader_interlock on i965</li>
-<li>GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)</li>
-<li>GL_ANDROID_extension_pack_es31a on radeonsi.</li>
-<li>GL_KHR_texture_compression_astc_ldr on radeonsi</li>
-</ul>
-
-<h2>Bug fixes</h2>
-
-<h2>Changes</h2>
-
-<ul>
-<li>Removed GL_EXT_polygon_offset applications should use glPolygonOffset instead.</li>
-<li>Removed libwayland-egl, now part of Wayland</li>
-</ul>
-
-</div>
-</body>
-</html>

docs/specs/MESA_framebuffer_flip_y.txt

@@ -1,81 +0,0 @@
-Name
-
-    MESA_framebuffer_flip_y
-
-Name Strings
-
-    GL_MESA_framebuffer_flip_y
-
-Contact
-
-    Fritz Koenig <frkoenig@google.com>
-
-Contributors
-
-    Fritz Koenig, Google
-    Kristian Høgsberg, Google
-    Chad Versace, Google
-
-Status
-
-    Proposal
-
-Version
-
-    Version 1, June 7, 2018
-
-Number
-
-    302
-
-Dependencies
-
-    OpenGL ES 3.1 is required, for FramebufferParameteri.
-
-Overview
-
-    This extension defines a new framebuffer parameter,
-    GL_FRAMEBUFFER_FLIP_Y_MESA, that changes the behavior of the reads and
-    writes to the framebuffer attachment points. When GL_FRAMEBUFFER_FLIP_Y_MESA
-    is GL_TRUE, render commands and pixel transfer operations access the
-    backing store of each attachment point with an y-inverted coordinate
-    system. This y-inversion is relative to the coordinate system set when
-    GL_FRAMEBUFFER_FLIP_Y_MESA is GL_FALSE.
-
-    Access through TexSubImage2D and similar calls will notice the effect of
-    the flip when they are not attached to framebuffer objects because
-    GL_FRAMEBUFFER_FLIP_Y_MESA is associated with the framebuffer object and
-    not the attachment points.
-
-IP Status
-
-    None
-
-Issues
-
-    None
-
-New Procedures and Functions
-
-    None
-
-New Types
-
-    None
-
-New Tokens
-
-    Accepted by the <pname> argument of FramebufferParameteri and
-    GetFramebufferParameteriv:
-
-        GL_FRAMEBUFFER_FLIP_Y_MESA                      0x8BBB
-
-Errors
-
-    An INVALID_OPERATION error is generated by GetFramebufferParameteriv if the
-    default framebuffer is bound to <target> and <pname> is FRAMEBUFFER_FLIP_Y_MESA.
-
-Revision History
-
-    Version 1, June, 2018
-        Initial draft (Fritz Koenig)

docs/specs/enums.txt

@@ -71,9 +71,6 @@ GL_MESA_tile_raster_order
 	GL_TILE_RASTER_ORDER_INCREASING_X_MESA	0x8BB9
 	GL_TILE_RASTER_ORDER_INCREASING_Y_MESA	0x8BBA
 
-GL_MESA_framebuffer_flip_y
-	GL_FRAMEBUFFER_FLIP_Y_MESA           0x8BBB
-
 EGL_MESA_drm_image
         EGL_DRM_BUFFER_FORMAT_MESA		0x31D0
         EGL_DRM_BUFFER_USE_MESA			0x31D1

docs/submittingpatches.html

@@ -36,7 +36,7 @@
 perhaps, in very trivial cases.)
 <li>Code patches should follow Mesa
 <a href="codingstyle.html" target="_parent">coding conventions</a>.
-<li>Whenever possible, patches should only affect individual Mesa/Gallium
+<li>Whenever possible, patches should only effect individual Mesa/Gallium
 components.
 <li>Patches should never introduce build breaks and should be bisectable (see
 <code>git bisect</code>.)
@@ -122,9 +122,9 @@ Please use common sense and do <strong>not</strong> blindly add everyone.
 <pre>
     $ scripts/get_reviewer.pl --help # to get the help screen
     $ scripts/get_reviewer.pl -f src/egl/drivers/dri2/platform_android.c
-    Rob Herring &lt;robh@kernel.org&gt; (reviewer:ANDROID EGL SUPPORT,added_lines:188/700=27%,removed_lines:58/283=20%)
-    Tomasz Figa &lt;tfiga@chromium.org&gt; (reviewer:ANDROID EGL SUPPORT,authored:12/41=29%,added_lines:308/700=44%,removed_lines:115/283=41%)
-    Emil Velikov &lt;emil.l.velikov@gmail.com&gt; (authored:13/41=32%,removed_lines:76/283=27%)
+    Rob Herring <robh@kernel.org> (reviewer:ANDROID EGL SUPPORT,added_lines:188/700=27%,removed_lines:58/283=20%)
+    Tomasz Figa <tfiga@chromium.org> (reviewer:ANDROID EGL SUPPORT,authored:12/41=29%,added_lines:308/700=44%,removed_lines:115/283=41%)
+    Emil Velikov <emil.l.velikov@gmail.com> (authored:13/41=32%,removed_lines:76/283=27%)
 </pre>
 </ul>
 

docs/utilities.html

@@ -31,7 +31,7 @@
   <dd>is a very useful tool for tracking down
   memory-related problems in your code.</dd>
 
-  <dt><a href="https://scan.coverity.com/projects/mesa">Coverity</a></dt>
+  <dt><a href="https://scan.coverity.com/projects/mesa">Coverity</a><dt>
   <dd>provides static code analysis of Mesa.  If you create an account
   you can see the results and try to fix outstanding issues.</dd>
 </dl>

docs/viewperf.html

@@ -18,8 +18,8 @@
 
 <p>
 This page lists known issues with
-<a href="https://www.spec.org/gwpg/gpc.static/vp11info.html">SPEC Viewperf 11</a>
-and <a href="https://www.spec.org/gwpg/gpc.static/vp12info.html">SPEC Viewperf 12</a>
+<a href="https://www.spec.org/gwpg/gpc.static/vp11info.html" target="_main">SPEC Viewperf 11</a>
+and <a href="https://www.spec.org/gwpg/gpc.static/vp12info.html" target="_main">SPEC Viewperf 12</a>
 when running on Mesa-based drivers.
 </p>
 
@@ -66,10 +66,13 @@ either in Viewperf or the Mesa driver.
 
 <p>
 These tests use features of the
-<a href="https://www.opengl.org/registry/specs/NV/fragment_program2.txt">GL_NV_fragment_program2</a>
-and
-<a href="https://www.opengl.org/registry/specs/NV/vertex_program3.txt">GL_NV_vertex_program3</a>
-extensions without checking if the driver supports them.
+<a href="https://www.opengl.org/registry/specs/NV/fragment_program2.txt"
+target="_main">
+GL_NV_fragment_program2</a> and
+<a href="https://www.opengl.org/registry/specs/NV/vertex_program3.txt"
+target="_main">
+GL_NV_vertex_program3</a> extensions without checking if the driver supports
+them.
 </p>
 <p>
 When Mesa tries to compile the vertex/fragment programs it generates errors
@@ -83,8 +86,8 @@ Subsequent drawing calls become no-ops and the rendering is incorrect.
 
 <p>
 These tests depend on the
-<a href="https://www.opengl.org/registry/specs/NV/primitive_restart.txt">GL_NV_primitive_restart</a>
-extension.
+<a href="https://www.opengl.org/registry/specs/NV/primitive_restart.txt"
+target="_main">GL_NV_primitive_restart</a> extension.
 </p>
 
 <p>
@@ -121,7 +124,7 @@ never specified.
 
 <p>
 A trace captured with
-<a href="https://github.com/apitrace/apitrace">API trace</a>
+<a href="https://github.com/apitrace/apitrace" target="_main">API trace</a>
 shows this sequences of calls like this:
 
 <pre>

include/GL/internal/dri_interface.h

@@ -589,7 +589,7 @@ struct __DRIdamageExtensionRec {
  * SWRast Loader extension.
  */
 #define __DRI_SWRAST_LOADER "DRI_SWRastLoader"
-#define __DRI_SWRAST_LOADER_VERSION 4
+#define __DRI_SWRAST_LOADER_VERSION 3
 struct __DRIswrastLoaderExtensionRec {
     __DRIextension base;
 
@@ -631,24 +631,6 @@ struct __DRIswrastLoaderExtensionRec {
    void (*getImage2)(__DRIdrawable *readable,
 		     int x, int y, int width, int height, int stride,
 		     char *data, void *loaderPrivate);
-
-    /**
-     * Put shm image to drawable
-     *
-     * \since 4
-     */
-    void (*putImageShm)(__DRIdrawable *drawable, int op,
-                        int x, int y, int width, int height, int stride,
-                        int shmid, char *shmaddr, unsigned offset,
-                        void *loaderPrivate);
-    /**
-     * Get shm image from readable
-     *
-     * \since 4
-     */
-    void (*getImageShm)(__DRIdrawable *readable,
-                        int x, int y, int width, int height,
-                        int shmid, void *loaderPrivate);
 };
 
 /**
@@ -1271,7 +1253,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_YUYV         0x100f
 #define __DRI_IMAGE_FORMAT_XBGR2101010  0x1010
 #define __DRI_IMAGE_FORMAT_ABGR2101010  0x1011
-#define __DRI_IMAGE_FORMAT_SABGR8       0x1012
 
 #define __DRI_IMAGE_USE_SHARE		0x0001
 #define __DRI_IMAGE_USE_SCANOUT		0x0002
@@ -1308,7 +1289,6 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_ABGR8888	0x34324241
 #define __DRI_IMAGE_FOURCC_XBGR8888	0x34324258
 #define __DRI_IMAGE_FOURCC_SARGB8888	0x83324258
-#define __DRI_IMAGE_FOURCC_SABGR8888	0x84324258
 #define __DRI_IMAGE_FOURCC_ARGB2101010	0x30335241
 #define __DRI_IMAGE_FOURCC_XRGB2101010	0x30335258
 #define __DRI_IMAGE_FOURCC_ABGR2101010	0x30334241

include/GLES2/gl2ext.h

@@ -2334,11 +2334,6 @@ GL_APICALL void GL_APIENTRY glGetPerfQueryInfoINTEL (GLuint queryId, GLuint quer
 #endif
 #endif /* GL_INTEL_performance_query */
 
-#ifndef GL_MESA_framebuffer_flip_y
-#define GL_MESA_framebuffer_flip_y 1
-#define GL_FRAMEBUFFER_FLIP_Y_MESA        0x8BBB
-#endif /* GL_MESA_framebuffer_flip_y */
-
 #ifndef GL_MESA_program_binary_formats
 #define GL_MESA_program_binary_formats 1
 #define GL_PROGRAM_BINARY_FORMAT_MESA     0x875F

include/drm-uapi/drm_fourcc.h

@@ -384,23 +384,6 @@ extern "C" {
 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
 	fourcc_mod_code(NVIDIA, 0x15)
 
-/*
- * Some Broadcom modifiers take parameters, for example the number of
- * vertical lines in the image. Reserve the lower 32 bits for modifier
- * type, and the next 24 bits for parameters. Top 8 bits are the
- * vendor code.
- */
-#define __fourcc_mod_broadcom_param_shift 8
-#define __fourcc_mod_broadcom_param_bits 48
-#define fourcc_mod_broadcom_code(val, params) \
-	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
-#define fourcc_mod_broadcom_param(m) \
-	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
-	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
-#define fourcc_mod_broadcom_mod(m) \
-	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
-		 __fourcc_mod_broadcom_param_shift))
-
 /*
  * Broadcom VC4 "T" format
  *
@@ -422,69 +405,6 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
 
-/*
- * Broadcom SAND format
- *
- * This is the native format that the H.264 codec block uses.  For VC4
- * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
- *
- * The image can be considered to be split into columns, and the
- * columns are placed consecutively into memory.  The width of those
- * columns can be either 32, 64, 128, or 256 pixels, but in practice
- * only 128 pixel columns are used.
- *
- * The pitch between the start of each column is set to optimally
- * switch between SDRAM banks. This is passed as the number of lines
- * of column width in the modifier (we can't use the stride value due
- * to various core checks that look at it , so you should set the
- * stride to width*cpp).
- *
- * Note that the column height for this format modifier is the same
- * for all of the planes, assuming that each column contains both Y
- * and UV.  Some SAND-using hardware stores UV in a separate tiled
- * image from Y to reduce the column height, which is not supported
- * with these modifiers.
- */
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
-	fourcc_mod_broadcom_code(2, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
-	fourcc_mod_broadcom_code(3, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
-	fourcc_mod_broadcom_code(4, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
-	fourcc_mod_broadcom_code(5, v)
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
-	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
-	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
-	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
-	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
-
-/* Broadcom UIF format
- *
- * This is the common format for the current Broadcom multimedia
- * blocks, including V3D 3.x and newer, newer video codecs, and
- * displays.
- *
- * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
- * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
- * stored in columns, with padding between the columns to ensure that
- * moving from one column to the next doesn't hit the same SDRAM page
- * bank.
- *
- * To calculate the padding, it is assumed that each hardware block
- * and the software driving it knows the platform's SDRAM page size,
- * number of banks, and XOR address, and that it's identical between
- * all blocks using the format.  This tiling modifier will use XOR as
- * necessary to reduce the padding.  If a hardware block can't do XOR,
- * the assumption is that a no-XOR tiling modifier will be created.
- */
-#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
-
 #if defined(__cplusplus)
 }
 #endif

include/drm-uapi/vc4_drm.h

@@ -183,17 +183,10 @@ struct drm_vc4_submit_cl {
 	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
 	__u32 perfmonid;
 
-	/* Syncobj handle to wait on. If set, processing of this render job
-	 * will not start until the syncobj is signaled. 0 means ignore.
+	/* Unused field to align this struct on 64 bits. Must be set to 0.
+	 * If one ever needs to add an u32 field to this struct, this field
+	 * can be used.
 	 */
-	__u32 in_sync;
-
-	/* Syncobj handle to export fence to. If set, the fence in the syncobj
-	 * will be replaced with a fence that signals upon completion of this
-	 * render job. 0 means ignore.
-	 */
-	__u32 out_sync;
-
 	__u32 pad2;
 };
 

include/pci_ids/i965_pci_ids.h

@@ -156,7 +156,6 @@ CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
 CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)")
 CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
 CHIPSET(0x591B, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)")
-CHIPSET(0x591C, kbl_gt2, "Intel(R) Kaby Lake GT2")
 CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)")
 CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)")
 CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F")

include/pci_ids/radeonsi_pci_ids.h

@@ -235,11 +235,4 @@ CHIPSET(0x69A2, VEGA12)
 CHIPSET(0x69A3, VEGA12)
 CHIPSET(0x69AF, VEGA12)
 
-CHIPSET(0x66A0, VEGA20)
-CHIPSET(0x66A1, VEGA20)
-CHIPSET(0x66A2, VEGA20)
-CHIPSET(0x66A3, VEGA20)
-CHIPSET(0x66A7, VEGA20)
-CHIPSET(0x66AF, VEGA20)
-
 CHIPSET(0x15DD, RAVEN)

include/vulkan/vk_icd.h

@@ -24,34 +24,13 @@
 #define VKICD_H
 
 #include "vulkan.h"
-#include <stdbool.h>
 
-// Loader-ICD version negotiation API.  Versions add the following features:
-//   Version 0 - Initial.  Doesn't support vk_icdGetInstanceProcAddr
-//               or vk_icdNegotiateLoaderICDInterfaceVersion.
-//   Version 1 - Add support for vk_icdGetInstanceProcAddr.
-//   Version 2 - Add Loader/ICD Interface version negotiation
-//               via vk_icdNegotiateLoaderICDInterfaceVersion.
-//   Version 3 - Add ICD creation/destruction of KHR_surface objects.
-//   Version 4 - Add unknown physical device extension qyering via
-//               vk_icdGetPhysicalDeviceProcAddr.
-//   Version 5 - Tells ICDs that the loader is now paying attention to the
-//               application version of Vulkan passed into the ApplicationInfo
-//               structure during vkCreateInstance.  This will tell the ICD
-//               that if the loader is older, it should automatically fail a
-//               call for any API version > 1.0.  Otherwise, the loader will
-//               manually determine if it can support the expected version.
-#define CURRENT_LOADER_ICD_INTERFACE_VERSION 5
+/*
+ * Loader-ICD version negotiation API
+ */
+#define CURRENT_LOADER_ICD_INTERFACE_VERSION 3
 #define MIN_SUPPORTED_LOADER_ICD_INTERFACE_VERSION 0
-#define MIN_PHYS_DEV_EXTENSION_ICD_INTERFACE_VERSION 4
-typedef VkResult(VKAPI_PTR *PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t *pVersion);
-
-// This is defined in vk_layer.h which will be found by the loader, but if an ICD is building against this
-// file directly, it won't be found.
-#ifndef PFN_GetPhysicalDeviceProcAddr
-typedef PFN_vkVoidFunction(VKAPI_PTR *PFN_GetPhysicalDeviceProcAddr)(VkInstance instance, const char *pName);
-#endif
-
+typedef VkResult (VKAPI_PTR *PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t *pVersion);
 /*
  * The ICD must reserve space for a pointer for the loader's dispatch
  * table, at the start of <each object>.
@@ -85,9 +64,6 @@ typedef enum {
     VK_ICD_WSI_PLATFORM_WIN32,
     VK_ICD_WSI_PLATFORM_XCB,
     VK_ICD_WSI_PLATFORM_XLIB,
-    VK_ICD_WSI_PLATFORM_ANDROID,
-    VK_ICD_WSI_PLATFORM_MACOS,
-    VK_ICD_WSI_PLATFORM_IOS,
     VK_ICD_WSI_PLATFORM_DISPLAY
 } VkIcdWsiPlatform;
 
@@ -101,7 +77,7 @@ typedef struct {
     MirConnection *connection;
     MirSurface *mirSurface;
 } VkIcdSurfaceMir;
-#endif  // VK_USE_PLATFORM_MIR_KHR
+#endif // VK_USE_PLATFORM_MIR_KHR
 
 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
 typedef struct {
@@ -109,7 +85,7 @@ typedef struct {
     struct wl_display *display;
     struct wl_surface *surface;
 } VkIcdSurfaceWayland;
-#endif  // VK_USE_PLATFORM_WAYLAND_KHR
+#endif // VK_USE_PLATFORM_WAYLAND_KHR
 
 #ifdef VK_USE_PLATFORM_WIN32_KHR
 typedef struct {
@@ -117,7 +93,7 @@ typedef struct {
     HINSTANCE hinstance;
     HWND hwnd;
 } VkIcdSurfaceWin32;
-#endif  // VK_USE_PLATFORM_WIN32_KHR
+#endif // VK_USE_PLATFORM_WIN32_KHR
 
 #ifdef VK_USE_PLATFORM_XCB_KHR
 typedef struct {
@@ -125,7 +101,7 @@ typedef struct {
     xcb_connection_t *connection;
     xcb_window_t window;
 } VkIcdSurfaceXcb;
-#endif  // VK_USE_PLATFORM_XCB_KHR
+#endif // VK_USE_PLATFORM_XCB_KHR
 
 #ifdef VK_USE_PLATFORM_XLIB_KHR
 typedef struct {
@@ -133,28 +109,13 @@ typedef struct {
     Display *dpy;
     Window window;
 } VkIcdSurfaceXlib;
-#endif  // VK_USE_PLATFORM_XLIB_KHR
+#endif // VK_USE_PLATFORM_XLIB_KHR
 
 #ifdef VK_USE_PLATFORM_ANDROID_KHR
 typedef struct {
-    VkIcdSurfaceBase base;
-    struct ANativeWindow *window;
+    ANativeWindow* window;
 } VkIcdSurfaceAndroid;
-#endif  // VK_USE_PLATFORM_ANDROID_KHR
-
-#ifdef VK_USE_PLATFORM_MACOS_MVK
-typedef struct {
-    VkIcdSurfaceBase base;
-    const void *pView;
-} VkIcdSurfaceMacOS;
-#endif  // VK_USE_PLATFORM_MACOS_MVK
-
-#ifdef VK_USE_PLATFORM_IOS_MVK
-typedef struct {
-    VkIcdSurfaceBase base;
-    const void *pView;
-} VkIcdSurfaceIOS;
-#endif  // VK_USE_PLATFORM_IOS_MVK
+#endif //VK_USE_PLATFORM_ANDROID_KHR
 
 typedef struct {
     VkIcdSurfaceBase base;
@@ -167,4 +128,4 @@ typedef struct {
     VkExtent2D imageExtent;
 } VkIcdSurfaceDisplay;
 
-#endif  // VKICD_H
+#endif // VKICD_H

include/vulkan/vulkan_core.h

@@ -43,7 +43,7 @@ extern "C" {
 #define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
 #define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
 // Version of this file
-#define VK_HEADER_VERSION 80
+#define VK_HEADER_VERSION 73
 
 
 #define VK_NULL_HANDLE 0
@@ -320,9 +320,6 @@ typedef enum VkStructureType {
     VK_STRUCTURE_TYPE_IMPORT_SEMAPHORE_FD_INFO_KHR = 1000079000,
     VK_STRUCTURE_TYPE_SEMAPHORE_GET_FD_INFO_KHR = 1000079001,
     VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR = 1000080000,
-    VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT = 1000081000,
-    VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT = 1000081001,
-    VK_STRUCTURE_TYPE_CONDITIONAL_RENDERING_BEGIN_INFO_EXT = 1000081002,
     VK_STRUCTURE_TYPE_PRESENT_REGIONS_KHR = 1000084000,
     VK_STRUCTURE_TYPE_OBJECT_TABLE_CREATE_INFO_NVX = 1000086000,
     VK_STRUCTURE_TYPE_INDIRECT_COMMANDS_LAYOUT_CREATE_INFO_NVX = 1000086001,
@@ -344,13 +341,6 @@ typedef enum VkStructureType {
     VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT = 1000101000,
     VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT = 1000101001,
     VK_STRUCTURE_TYPE_HDR_METADATA_EXT = 1000105000,
-    VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2_KHR = 1000109000,
-    VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2_KHR = 1000109001,
-    VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_2_KHR = 1000109002,
-    VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2_KHR = 1000109003,
-    VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO_2_KHR = 1000109004,
-    VK_STRUCTURE_TYPE_SUBPASS_BEGIN_INFO_KHR = 1000109005,
-    VK_STRUCTURE_TYPE_SUBPASS_END_INFO_KHR = 1000109006,
     VK_STRUCTURE_TYPE_SHARED_PRESENT_SURFACE_CAPABILITIES_KHR = 1000111000,
     VK_STRUCTURE_TYPE_IMPORT_FENCE_WIN32_HANDLE_INFO_KHR = 1000114000,
     VK_STRUCTURE_TYPE_EXPORT_FENCE_WIN32_HANDLE_INFO_KHR = 1000114001,
@@ -360,11 +350,6 @@ typedef enum VkStructureType {
     VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SURFACE_INFO_2_KHR = 1000119000,
     VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_KHR = 1000119001,
     VK_STRUCTURE_TYPE_SURFACE_FORMAT_2_KHR = 1000119002,
-    VK_STRUCTURE_TYPE_DISPLAY_PROPERTIES_2_KHR = 1000121000,
-    VK_STRUCTURE_TYPE_DISPLAY_PLANE_PROPERTIES_2_KHR = 1000121001,
-    VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR = 1000121002,
-    VK_STRUCTURE_TYPE_DISPLAY_PLANE_INFO_2_KHR = 1000121003,
-    VK_STRUCTURE_TYPE_DISPLAY_PLANE_CAPABILITIES_2_KHR = 1000121004,
     VK_STRUCTURE_TYPE_IOS_SURFACE_CREATE_INFO_MVK = 1000122000,
     VK_STRUCTURE_TYPE_MACOS_SURFACE_CREATE_INFO_MVK = 1000123000,
     VK_STRUCTURE_TYPE_DEBUG_UTILS_OBJECT_NAME_INFO_EXT = 1000128000,
@@ -399,7 +384,6 @@ typedef enum VkStructureType {
     VK_STRUCTURE_TYPE_DESCRIPTOR_SET_VARIABLE_DESCRIPTOR_COUNT_ALLOCATE_INFO_EXT = 1000161003,
     VK_STRUCTURE_TYPE_DESCRIPTOR_SET_VARIABLE_DESCRIPTOR_COUNT_LAYOUT_SUPPORT_EXT = 1000161004,
     VK_STRUCTURE_TYPE_DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT = 1000174000,
-    VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR = 1000177000,
     VK_STRUCTURE_TYPE_IMPORT_MEMORY_HOST_POINTER_INFO_EXT = 1000178000,
     VK_STRUCTURE_TYPE_MEMORY_HOST_POINTER_PROPERTIES_EXT = 1000178001,
     VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT = 1000178002,
@@ -1225,16 +1209,6 @@ typedef enum VkObjectType {
     VK_OBJECT_TYPE_MAX_ENUM = 0x7FFFFFFF
 } VkObjectType;
 
-typedef enum VkVendorId {
-    VK_VENDOR_ID_VIV = 0x10001,
-    VK_VENDOR_ID_VSI = 0x10002,
-    VK_VENDOR_ID_KAZAN = 0x10003,
-    VK_VENDOR_ID_BEGIN_RANGE = VK_VENDOR_ID_VIV,
-    VK_VENDOR_ID_END_RANGE = VK_VENDOR_ID_KAZAN,
-    VK_VENDOR_ID_RANGE_SIZE = (VK_VENDOR_ID_KAZAN - VK_VENDOR_ID_VIV + 1),
-    VK_VENDOR_ID_MAX_ENUM = 0x7FFFFFFF
-} VkVendorId;
-
 typedef VkFlags VkInstanceCreateFlags;
 
 typedef enum VkFormatFeatureFlagBits {
@@ -1378,7 +1352,6 @@ typedef enum VkPipelineStageFlagBits {
     VK_PIPELINE_STAGE_HOST_BIT = 0x00004000,
     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT = 0x00008000,
     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT = 0x00010000,
-    VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT = 0x00040000,
     VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX = 0x00020000,
     VK_PIPELINE_STAGE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
 } VkPipelineStageFlagBits;
@@ -1467,7 +1440,6 @@ typedef enum VkBufferUsageFlagBits {
     VK_BUFFER_USAGE_INDEX_BUFFER_BIT = 0x00000040,
     VK_BUFFER_USAGE_VERTEX_BUFFER_BIT = 0x00000080,
     VK_BUFFER_USAGE_INDIRECT_BUFFER_BIT = 0x00000100,
-    VK_BUFFER_USAGE_CONDITIONAL_RENDERING_BIT_EXT = 0x00000200,
     VK_BUFFER_USAGE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
 } VkBufferUsageFlagBits;
 typedef VkFlags VkBufferUsageFlags;
@@ -1579,7 +1551,6 @@ typedef enum VkAccessFlagBits {
     VK_ACCESS_HOST_WRITE_BIT = 0x00004000,
     VK_ACCESS_MEMORY_READ_BIT = 0x00008000,
     VK_ACCESS_MEMORY_WRITE_BIT = 0x00010000,
-    VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT = 0x00100000,
     VK_ACCESS_COMMAND_PROCESS_READ_BIT_NVX = 0x00020000,
     VK_ACCESS_COMMAND_PROCESS_WRITE_BIT_NVX = 0x00040000,
     VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT = 0x00080000,
@@ -2744,16 +2715,6 @@ typedef struct VkDrawIndirectCommand {
     uint32_t    firstInstance;
 } VkDrawIndirectCommand;
 
-typedef struct VkBaseOutStructure {
-    VkStructureType               sType;
-    struct VkBaseOutStructure*    pNext;
-} VkBaseOutStructure;
-
-typedef struct VkBaseInStructure {
-    VkStructureType                    sType;
-    const struct VkBaseInStructure*    pNext;
-} VkBaseInStructure;
-
 
 typedef VkResult (VKAPI_PTR *PFN_vkCreateInstance)(const VkInstanceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkInstance* pInstance);
 typedef void (VKAPI_PTR *PFN_vkDestroyInstance)(VkInstance instance, const VkAllocationCallbacks* pAllocator);
@@ -5449,114 +5410,6 @@ VKAPI_ATTR void VKAPI_CALL vkUpdateDescriptorSetWithTemplateKHR(
     const void*                                 pData);
 #endif
 
-#define VK_KHR_create_renderpass2 1
-#define VK_KHR_CREATE_RENDERPASS_2_SPEC_VERSION 1
-#define VK_KHR_CREATE_RENDERPASS_2_EXTENSION_NAME "VK_KHR_create_renderpass2"
-
-typedef struct VkAttachmentDescription2KHR {
-    VkStructureType                 sType;
-    const void*                     pNext;
-    VkAttachmentDescriptionFlags    flags;
-    VkFormat                        format;
-    VkSampleCountFlagBits           samples;
-    VkAttachmentLoadOp              loadOp;
-    VkAttachmentStoreOp             storeOp;
-    VkAttachmentLoadOp              stencilLoadOp;
-    VkAttachmentStoreOp             stencilStoreOp;
-    VkImageLayout                   initialLayout;
-    VkImageLayout                   finalLayout;
-} VkAttachmentDescription2KHR;
-
-typedef struct VkAttachmentReference2KHR {
-    VkStructureType       sType;
-    const void*           pNext;
-    uint32_t              attachment;
-    VkImageLayout         layout;
-    VkImageAspectFlags    aspectMask;
-} VkAttachmentReference2KHR;
-
-typedef struct VkSubpassDescription2KHR {
-    VkStructureType                     sType;
-    const void*                         pNext;
-    VkSubpassDescriptionFlags           flags;
-    VkPipelineBindPoint                 pipelineBindPoint;
-    uint32_t                            viewMask;
-    uint32_t                            inputAttachmentCount;
-    const VkAttachmentReference2KHR*    pInputAttachments;
-    uint32_t                            colorAttachmentCount;
-    const VkAttachmentReference2KHR*    pColorAttachments;
-    const VkAttachmentReference2KHR*    pResolveAttachments;
-    const VkAttachmentReference2KHR*    pDepthStencilAttachment;
-    uint32_t                            preserveAttachmentCount;
-    const uint32_t*                     pPreserveAttachments;
-} VkSubpassDescription2KHR;
-
-typedef struct VkSubpassDependency2KHR {
-    VkStructureType         sType;
-    const void*             pNext;
-    uint32_t                srcSubpass;
-    uint32_t                dstSubpass;
-    VkPipelineStageFlags    srcStageMask;
-    VkPipelineStageFlags    dstStageMask;
-    VkAccessFlags           srcAccessMask;
-    VkAccessFlags           dstAccessMask;
-    VkDependencyFlags       dependencyFlags;
-    int32_t                 viewOffset;
-} VkSubpassDependency2KHR;
-
-typedef struct VkRenderPassCreateInfo2KHR {
-    VkStructureType                       sType;
-    const void*                           pNext;
-    VkRenderPassCreateFlags               flags;
-    uint32_t                              attachmentCount;
-    const VkAttachmentDescription2KHR*    pAttachments;
-    uint32_t                              subpassCount;
-    const VkSubpassDescription2KHR*       pSubpasses;
-    uint32_t                              dependencyCount;
-    const VkSubpassDependency2KHR*        pDependencies;
-    uint32_t                              correlatedViewMaskCount;
-    const uint32_t*                       pCorrelatedViewMasks;
-} VkRenderPassCreateInfo2KHR;
-
-typedef struct VkSubpassBeginInfoKHR {
-    VkStructureType      sType;
-    const void*          pNext;
-    VkSubpassContents    contents;
-} VkSubpassBeginInfoKHR;
-
-typedef struct VkSubpassEndInfoKHR {
-    VkStructureType    sType;
-    const void*        pNext;
-} VkSubpassEndInfoKHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkCreateRenderPass2KHR)(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass);
-typedef void (VKAPI_PTR *PFN_vkCmdBeginRenderPass2KHR)(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo*      pRenderPassBegin, const VkSubpassBeginInfoKHR*      pSubpassBeginInfo);
-typedef void (VKAPI_PTR *PFN_vkCmdNextSubpass2KHR)(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR*      pSubpassBeginInfo, const VkSubpassEndInfoKHR*        pSubpassEndInfo);
-typedef void (VKAPI_PTR *PFN_vkCmdEndRenderPass2KHR)(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR*        pSubpassEndInfo);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkCreateRenderPass2KHR(
-    VkDevice                                    device,
-    const VkRenderPassCreateInfo2KHR*           pCreateInfo,
-    const VkAllocationCallbacks*                pAllocator,
-    VkRenderPass*                               pRenderPass);
-
-VKAPI_ATTR void VKAPI_CALL vkCmdBeginRenderPass2KHR(
-    VkCommandBuffer                             commandBuffer,
-    const VkRenderPassBeginInfo*                pRenderPassBegin,
-    const VkSubpassBeginInfoKHR*                pSubpassBeginInfo);
-
-VKAPI_ATTR void VKAPI_CALL vkCmdNextSubpass2KHR(
-    VkCommandBuffer                             commandBuffer,
-    const VkSubpassBeginInfoKHR*                pSubpassBeginInfo,
-    const VkSubpassEndInfoKHR*                  pSubpassEndInfo);
-
-VKAPI_ATTR void VKAPI_CALL vkCmdEndRenderPass2KHR(
-    VkCommandBuffer                             commandBuffer,
-    const VkSubpassEndInfoKHR*                  pSubpassEndInfo);
-#endif
-
 #define VK_KHR_shared_presentable_image 1
 #define VK_KHR_SHARED_PRESENTABLE_IMAGE_SPEC_VERSION 1
 #define VK_KHR_SHARED_PRESENTABLE_IMAGE_EXTENSION_NAME "VK_KHR_shared_presentable_image"
@@ -5719,70 +5572,6 @@ typedef VkPhysicalDeviceVariablePointerFeatures VkPhysicalDeviceVariablePointerF
 
 
 
-#define VK_KHR_get_display_properties2 1
-#define VK_KHR_GET_DISPLAY_PROPERTIES_2_SPEC_VERSION 1
-#define VK_KHR_GET_DISPLAY_PROPERTIES_2_EXTENSION_NAME "VK_KHR_get_display_properties2"
-
-typedef struct VkDisplayProperties2KHR {
-    VkStructureType           sType;
-    void*                     pNext;
-    VkDisplayPropertiesKHR    displayProperties;
-} VkDisplayProperties2KHR;
-
-typedef struct VkDisplayPlaneProperties2KHR {
-    VkStructureType                sType;
-    void*                          pNext;
-    VkDisplayPlanePropertiesKHR    displayPlaneProperties;
-} VkDisplayPlaneProperties2KHR;
-
-typedef struct VkDisplayModeProperties2KHR {
-    VkStructureType               sType;
-    void*                         pNext;
-    VkDisplayModePropertiesKHR    displayModeProperties;
-} VkDisplayModeProperties2KHR;
-
-typedef struct VkDisplayPlaneInfo2KHR {
-    VkStructureType     sType;
-    const void*         pNext;
-    VkDisplayModeKHR    mode;
-    uint32_t            planeIndex;
-} VkDisplayPlaneInfo2KHR;
-
-typedef struct VkDisplayPlaneCapabilities2KHR {
-    VkStructureType                  sType;
-    void*                            pNext;
-    VkDisplayPlaneCapabilitiesKHR    capabilities;
-} VkDisplayPlaneCapabilities2KHR;
-
-
-typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDeviceDisplayProperties2KHR)(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayProperties2KHR* pProperties);
-typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDeviceDisplayPlaneProperties2KHR)(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPlaneProperties2KHR* pProperties);
-typedef VkResult (VKAPI_PTR *PFN_vkGetDisplayModeProperties2KHR)(VkPhysicalDevice physicalDevice, VkDisplayKHR display, uint32_t* pPropertyCount, VkDisplayModeProperties2KHR* pProperties);
-typedef VkResult (VKAPI_PTR *PFN_vkGetDisplayPlaneCapabilities2KHR)(VkPhysicalDevice physicalDevice, const VkDisplayPlaneInfo2KHR* pDisplayPlaneInfo, VkDisplayPlaneCapabilities2KHR* pCapabilities);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR VkResult VKAPI_CALL vkGetPhysicalDeviceDisplayProperties2KHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t*                                   pPropertyCount,
-    VkDisplayProperties2KHR*                    pProperties);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetPhysicalDeviceDisplayPlaneProperties2KHR(
-    VkPhysicalDevice                            physicalDevice,
-    uint32_t*                                   pPropertyCount,
-    VkDisplayPlaneProperties2KHR*               pProperties);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetDisplayModeProperties2KHR(
-    VkPhysicalDevice                            physicalDevice,
-    VkDisplayKHR                                display,
-    uint32_t*                                   pPropertyCount,
-    VkDisplayModeProperties2KHR*                pProperties);
-
-VKAPI_ATTR VkResult VKAPI_CALL vkGetDisplayPlaneCapabilities2KHR(
-    VkPhysicalDevice                            physicalDevice,
-    const VkDisplayPlaneInfo2KHR*               pDisplayPlaneInfo,
-    VkDisplayPlaneCapabilities2KHR*             pCapabilities);
-#endif
-
 #define VK_KHR_dedicated_allocation 1
 #define VK_KHR_DEDICATED_ALLOCATION_SPEC_VERSION 3
 #define VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME "VK_KHR_dedicated_allocation"
@@ -5938,47 +5727,6 @@ VKAPI_ATTR void VKAPI_CALL vkGetDescriptorSetLayoutSupportKHR(
     VkDescriptorSetLayoutSupport*               pSupport);
 #endif
 
-#define VK_KHR_draw_indirect_count 1
-#define VK_KHR_DRAW_INDIRECT_COUNT_SPEC_VERSION 1
-#define VK_KHR_DRAW_INDIRECT_COUNT_EXTENSION_NAME "VK_KHR_draw_indirect_count"
-
-typedef void (VKAPI_PTR *PFN_vkCmdDrawIndirectCountKHR)(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride);
-typedef void (VKAPI_PTR *PFN_vkCmdDrawIndexedIndirectCountKHR)(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR void VKAPI_CALL vkCmdDrawIndirectCountKHR(
-    VkCommandBuffer                             commandBuffer,
-    VkBuffer                                    buffer,
-    VkDeviceSize                                offset,
-    VkBuffer                                    countBuffer,
-    VkDeviceSize                                countBufferOffset,
-    uint32_t                                    maxDrawCount,
-    uint32_t                                    stride);
-
-VKAPI_ATTR void VKAPI_CALL vkCmdDrawIndexedIndirectCountKHR(
-    VkCommandBuffer                             commandBuffer,
-    VkBuffer                                    buffer,
-    VkDeviceSize                                offset,
-    VkBuffer                                    countBuffer,
-    VkDeviceSize                                countBufferOffset,
-    uint32_t                                    maxDrawCount,
-    uint32_t                                    stride);
-#endif
-
-#define VK_KHR_8bit_storage 1
-#define VK_KHR_8BIT_STORAGE_SPEC_VERSION  1
-#define VK_KHR_8BIT_STORAGE_EXTENSION_NAME "VK_KHR_8bit_storage"
-
-typedef struct VkPhysicalDevice8BitStorageFeaturesKHR {
-    VkStructureType    sType;
-    void*              pNext;
-    VkBool32           storageBuffer8BitAccess;
-    VkBool32           uniformAndStorageBuffer8BitAccess;
-    VkBool32           storagePushConstant8;
-} VkPhysicalDevice8BitStorageFeaturesKHR;
-
-
-
 #define VK_EXT_debug_report 1
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkDebugReportCallbackEXT)
 
@@ -6429,51 +6177,6 @@ typedef struct VkValidationFlagsEXT {
 #define VK_EXT_SHADER_SUBGROUP_VOTE_EXTENSION_NAME "VK_EXT_shader_subgroup_vote"
 
 
-#define VK_EXT_conditional_rendering 1
-#define VK_EXT_CONDITIONAL_RENDERING_SPEC_VERSION 1
-#define VK_EXT_CONDITIONAL_RENDERING_EXTENSION_NAME "VK_EXT_conditional_rendering"
-
-
-typedef enum VkConditionalRenderingFlagBitsEXT {
-    VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT = 0x00000001,
-    VK_CONDITIONAL_RENDERING_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
-} VkConditionalRenderingFlagBitsEXT;
-typedef VkFlags VkConditionalRenderingFlagsEXT;
-
-typedef struct VkConditionalRenderingBeginInfoEXT {
-    VkStructureType                   sType;
-    const void*                       pNext;
-    VkBuffer                          buffer;
-    VkDeviceSize                      offset;
-    VkConditionalRenderingFlagsEXT    flags;
-} VkConditionalRenderingBeginInfoEXT;
-
-typedef struct VkPhysicalDeviceConditionalRenderingFeaturesEXT {
-    VkStructureType    sType;
-    void*              pNext;
-    VkBool32           conditionalRendering;
-    VkBool32           inheritedConditionalRendering;
-} VkPhysicalDeviceConditionalRenderingFeaturesEXT;
-
-typedef struct VkCommandBufferInheritanceConditionalRenderingInfoEXT {
-    VkStructureType    sType;
-    const void*        pNext;
-    VkBool32           conditionalRenderingEnable;
-} VkCommandBufferInheritanceConditionalRenderingInfoEXT;
-
-
-typedef void (VKAPI_PTR *PFN_vkCmdBeginConditionalRenderingEXT)(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin);
-typedef void (VKAPI_PTR *PFN_vkCmdEndConditionalRenderingEXT)(VkCommandBuffer commandBuffer);
-
-#ifndef VK_NO_PROTOTYPES
-VKAPI_ATTR void VKAPI_CALL vkCmdBeginConditionalRenderingEXT(
-    VkCommandBuffer                             commandBuffer,
-    const VkConditionalRenderingBeginInfoEXT*   pConditionalRenderingBegin);
-
-VKAPI_ATTR void VKAPI_CALL vkCmdEndConditionalRenderingEXT(
-    VkCommandBuffer                             commandBuffer);
-#endif
-
 #define VK_NVX_device_generated_commands 1
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkObjectTableNVX)
 VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkIndirectCommandsLayoutNVX)

meson.build

@@ -25,13 +25,10 @@ project(
     [find_program('python', 'python2', 'python3'), 'bin/meson_get_version.py']
   ).stdout(),
   license : 'MIT',
-  meson_version : '>= 0.44.1',
+  meson_version : '>= 0.42',
   default_options : ['buildtype=debugoptimized', 'c_std=c99', 'cpp_std=c++11']
 )
 
-cc = meson.get_compiler('c')
-cpp = meson.get_compiler('cpp')
-
 null_dep = dependency('', required : false)
 
 system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
@@ -53,13 +50,16 @@ with_tests = get_option('build-tests')
 with_valgrind = get_option('valgrind')
 with_libunwind = get_option('libunwind')
 with_asm = get_option('asm')
-with_glx_read_only_text = get_option('glx-read-only-text')
 with_osmesa = get_option('osmesa')
-with_swr_arches = get_option('swr-arches')
-with_tools = get_option('tools')
+with_swr_arches = get_option('swr-arches').split(',')
+with_tools = get_option('tools').split(',')
 if with_tools.contains('all')
   with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
 endif
+if get_option('texture-float')
+  pre_args += '-DTEXTURE_FLOAT_ENABLED'
+  message('WARNING: Floating-point texture enabled. Please consult docs/patents.txt and your lawyer before building mesa.')
+endif
 
 dri_drivers_path = get_option('dri-drivers-path')
 if dri_drivers_path == ''
@@ -93,102 +93,128 @@ endif
 
 system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 'linux'].contains(host_machine.system())
 
+with_dri = false
+with_dri_i915 = false
+with_dri_i965 = false
+with_dri_r100 = false
+with_dri_r200 = false
+with_dri_nouveau = false
+with_dri_swrast = false
 _drivers = get_option('dri-drivers')
-if _drivers.contains('auto')
+if _drivers == 'auto'
   if system_has_kms_drm
     # TODO: PPC, Sparc
     if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-      _drivers = ['i915', 'i965', 'r100', 'r200', 'nouveau']
+      _drivers = 'i915,i965,r100,r200,nouveau'
     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-      _drivers = []
+      _drivers = ''
     else
       error('Unknown architecture. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
   elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
     # only swrast would make sense here, but gallium swrast is a much better default
-    _drivers = []
+    _drivers = ''
   else
     error('Unknown OS. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
 endif
+if _drivers != ''
+  _split = _drivers.split(',')
+  with_dri_i915 = _split.contains('i915')
+  with_dri_i965 = _split.contains('i965')
+  with_dri_r100 = _split.contains('r100')
+  with_dri_r200 = _split.contains('r200')
+  with_dri_nouveau = _split.contains('nouveau')
+  with_dri_swrast = _split.contains('swrast')
+  with_dri = true
+endif
 
-with_dri_i915 = _drivers.contains('i915')
-with_dri_i965 = _drivers.contains('i965')
-with_dri_r100 = _drivers.contains('r100')
-with_dri_r200 = _drivers.contains('r200')
-with_dri_nouveau = _drivers.contains('nouveau')
-with_dri_swrast = _drivers.contains('swrast')
-
-with_dri = _drivers.length() != 0 and _drivers != ['']
-
+with_gallium = false
+with_gallium_pl111 = false
+with_gallium_radeonsi = false
+with_gallium_r300 = false
+with_gallium_r600 = false
+with_gallium_nouveau = false
+with_gallium_freedreno = false
+with_gallium_softpipe = false
+with_gallium_vc4 = false
+with_gallium_vc5 = false
+with_gallium_etnaviv = false
+with_gallium_imx = false
+with_gallium_tegra = false
+with_gallium_i915 = false
+with_gallium_svga = false
+with_gallium_virgl = false
+with_gallium_swr = false
 _drivers = get_option('gallium-drivers')
-if _drivers.contains('auto')
+if _drivers == 'auto'
   if system_has_kms_drm
     # TODO: PPC, Sparc
     if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-      _drivers = [
-        'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'swrast'
-      ]
+      _drivers = 'r300,r600,radeonsi,nouveau,virgl,svga,swrast'
     elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-      _drivers = [
-        'pl111', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'imx', 'nouveau',
-        'tegra', 'virgl', 'swrast',
-      ]
+      _drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,nouveau,tegra,virgl,swrast'
     else
       error('Unknown architecture. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
   elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
-    _drivers = ['swrast']
+    _drivers = 'swrast'
   else
     error('Unknown OS. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
 endif
-with_gallium_pl111 = _drivers.contains('pl111')
-with_gallium_radeonsi = _drivers.contains('radeonsi')
-with_gallium_r300 = _drivers.contains('r300')
-with_gallium_r600 = _drivers.contains('r600')
-with_gallium_nouveau = _drivers.contains('nouveau')
-with_gallium_freedreno = _drivers.contains('freedreno')
-with_gallium_softpipe = _drivers.contains('swrast')
-with_gallium_vc4 = _drivers.contains('vc4')
-with_gallium_v3d = _drivers.contains('v3d')
-with_gallium_etnaviv = _drivers.contains('etnaviv')
-with_gallium_imx = _drivers.contains('imx')
-with_gallium_tegra = _drivers.contains('tegra')
-with_gallium_i915 = _drivers.contains('i915')
-with_gallium_svga = _drivers.contains('svga')
-with_gallium_virgl = _drivers.contains('virgl')
-with_gallium_swr = _drivers.contains('swr')
-
-with_gallium = _drivers.length() != 0 and _drivers != ['']
-
-if with_gallium and system_has_kms_drm
-  _glx = get_option('glx')
-  _egl = get_option('egl')
-  if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 'false')
-    with_dri = true
+if _drivers != ''
+  _split = _drivers.split(',')
+  with_gallium_pl111 = _split.contains('pl111')
+  with_gallium_radeonsi = _split.contains('radeonsi')
+  with_gallium_r300 = _split.contains('r300')
+  with_gallium_r600 = _split.contains('r600')
+  with_gallium_nouveau = _split.contains('nouveau')
+  with_gallium_freedreno = _split.contains('freedreno')
+  with_gallium_softpipe = _split.contains('swrast')
+  with_gallium_vc4 = _split.contains('vc4')
+  with_gallium_vc5 = _split.contains('vc5')
+  with_gallium_etnaviv = _split.contains('etnaviv')
+  with_gallium_imx = _split.contains('imx')
+  with_gallium_tegra = _split.contains('tegra')
+  with_gallium_i915 = _split.contains('i915')
+  with_gallium_svga = _split.contains('svga')
+  with_gallium_virgl = _split.contains('virgl')
+  with_gallium_swr = _split.contains('swr')
+  with_gallium = true
+  if system_has_kms_drm
+    _glx = get_option('glx')
+    _egl = get_option('egl')
+    if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 'false')
+      with_dri = true
+    endif
   endif
 endif
 
+with_intel_vk = false
+with_amd_vk = false
+with_any_vk = false
 _vulkan_drivers = get_option('vulkan-drivers')
-if _vulkan_drivers.contains('auto')
+if _vulkan_drivers == 'auto'
   if system_has_kms_drm
     if host_machine.cpu_family().startswith('x86')
-      _vulkan_drivers = ['amd', 'intel']
+      _vulkan_drivers = 'amd,intel'
     else
       error('Unknown architecture. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.')
     endif
   elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
     # No vulkan driver supports windows or macOS currently
-    _vulkan_drivers = []
+    _vulkan_drivers = ''
   else
     error('Unknown OS. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.')
   endif
 endif
-
-with_intel_vk = _vulkan_drivers.contains('intel')
-with_amd_vk = _vulkan_drivers.contains('amd')
-with_any_vk = _vulkan_drivers.length() != 0 and _vulkan_drivers != ['']
+if _vulkan_drivers != ''
+  _split = _vulkan_drivers.split(',')
+  with_intel_vk = _split.contains('intel')
+  with_amd_vk = _split.contains('amd')
+  with_any_vk = with_amd_vk or with_intel_vk
+endif
 
 if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
   error('Only one swrast provider can be built')
@@ -221,37 +247,33 @@ else
   with_dri_platform = 'none'
 endif
 
+with_platform_android = false
+with_platform_wayland = false
+with_platform_x11 = false
+with_platform_drm = false
+with_platform_surfaceless = false
+egl_native_platform = ''
 _platforms = get_option('platforms')
-if _platforms.contains('auto')
+if _platforms == 'auto'
   if system_has_kms_drm
-    _platforms = ['x11', 'wayland', 'drm', 'surfaceless']
+    _platforms = 'x11,wayland,drm,surfaceless'
   elif ['darwin', 'windows', 'cygwin'].contains(host_machine.system())
-    _platforms = ['x11', 'surfaceless']
+    _platforms = 'x11,surfaceless'
   elif ['haiku'].contains(host_machine.system())
-    _platforms = ['haiku']
+    _platforms = 'haiku'
   else
     error('Unknown OS. Please pass -Dplatforms to set platforms. Patches gladly accepted to fix this.')
   endif
 endif
-
-with_platform_android = _platforms.contains('android')
-with_platform_x11 = _platforms.contains('x11')
-with_platform_wayland = _platforms.contains('wayland')
-with_platform_drm = _platforms.contains('drm')
-with_platform_haiku = _platforms.contains('haiku')
-with_platform_surfaceless = _platforms.contains('surfaceless')
-
-with_platforms = false
-if _platforms.length() != 0 and _platforms != ['']
-  with_platforms = true
-  egl_native_platform = _platforms[0]
-endif
-
-_xlib_lease = get_option('xlib-lease')
-if _xlib_lease == 'auto'
-  with_xlib_lease = with_platform_x11 and with_platform_drm
-else
-  with_xlib_lease = _xlib_lease == 'true'
+if _platforms != ''
+  _split = _platforms.split(',')
+  with_platform_android = _split.contains('android')
+  with_platform_x11 = _split.contains('x11')
+  with_platform_wayland = _split.contains('wayland')
+  with_platform_drm = _split.contains('drm')
+  with_platform_haiku = _split.contains('haiku')
+  with_platform_surfaceless = _split.contains('surfaceless')
+  egl_native_platform = _split[0]
 endif
 
 with_glx = get_option('glx')
@@ -263,6 +285,7 @@ if with_glx == 'auto'
   elif with_gallium
     # Even when building just gallium drivers the user probably wants dri
     with_glx = 'dri'
+    with_dri = true
   elif with_platform_x11 and with_any_opengl and not with_any_vk
     # The automatic behavior should not be to turn on xlib based glx when
     # building only vulkan drivers
@@ -271,11 +294,6 @@ if with_glx == 'auto'
     with_glx = 'disabled'
   endif
 endif
-if with_glx == 'dri'
-   if with_gallium
-      with_dri = true
-   endif
-endif
 
 if not (with_dri or with_gallium or with_glx == 'xlib' or with_glx == 'gallium-xlib')
   with_gles1 = false
@@ -297,13 +315,13 @@ endif
 
 _egl = get_option('egl')
 if _egl == 'auto'
-  with_egl = with_dri and with_shared_glapi and with_platforms
+  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
 elif _egl == 'true'
   if not with_dri
     error('EGL requires dri')
   elif not with_shared_glapi
     error('EGL requires shared-glapi')
-  elif not with_platforms
+  elif egl_native_platform == ''
     error('No platforms specified, consider -Dplatforms=drm,x11 at least')
   elif not ['disabled', 'dri'].contains(with_glx)
     error('EGL requires dri, but a GLX is being built without dri')
@@ -325,7 +343,11 @@ endif
 pre_args += '-DGLX_USE_TLS'
 if with_glx != 'disabled'
   if not (with_platform_x11 and with_any_opengl)
-    error('Cannot build GLX support without X11 platform support and at least one OpenGL API')
+    if with_glx == 'auto'
+      with_glx = 'disabled'
+    else
+      error('Cannot build GLX support without X11 platform support and at least one OpenGL API')
+    endif
   elif with_glx == 'gallium-xlib' 
     if not with_gallium
       error('Gallium-xlib based GLX requires at least one gallium driver')
@@ -338,12 +360,8 @@ if with_glx != 'disabled'
     if with_dri
       error('xlib conflicts with any dri driver')
     endif
-  elif with_glx == 'dri'
-    if not with_dri
-      error('dri based GLX requires at least one DRI driver')
-    elif not with_shared_glapi
-      error('dri based GLX requires shared-glapi')
-    endif
+  elif with_glx == 'dri' and not with_dri
+    error('dri based GLX requires at least one DRI driver')
   endif
 endif
 
@@ -615,34 +633,13 @@ if with_gallium_st_nine
   endif
 endif
 
-if get_option('power8') != 'false'
-  if host_machine.cpu_family() == 'ppc64le'
-    if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.8')
-      error('Altivec is not supported with gcc version < 4.8.')
-    endif
-    if cc.compiles('''
-        #include <altivec.h>
-        int main() {
-          vector unsigned char r;
-          vector unsigned int v = vec_splat_u32 (1);
-          r = __builtin_vec_vgbbd ((vector unsigned char) v);
-          return 0;
-        }''',
-        args : '-mpower8-vector',
-        name : 'POWER8 intrinsics')
-      pre_args += ['-D_ARCH_PWR8', '-mpower8-vector']
-    elif get_option('power8') == 'true'
-      error('POWER8 intrinsic support required but not found.')
-    endif
-  endif
-endif
-
 _opencl = get_option('gallium-opencl')
 if _opencl != 'disabled'
   if not with_gallium
     error('OpenCL Clover implementation requires at least one gallium driver.')
   endif
 
+  # TODO: alitvec?
   dep_clc = dependency('libclc')
   with_gallium_opencl = true
   with_opencl_icd = _opencl == 'icd'
@@ -703,6 +700,7 @@ if has_mako.returncode() != 0
   error('Python (2.x) mako module required to build mesa.')
 endif
 
+cc = meson.get_compiler('c')
 if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
   error('When using GCC, version 4.4.6 or later is required.')
 endif
@@ -776,16 +774,13 @@ foreach a : ['-Wall', '-Werror=implicit-function-declaration',
     c_args += a
   endif
 endforeach
-if cc.has_argument('-Wmissing-field-initializers')
-  c_args += '-Wno-missing-field-initializers'
-endif
-
 c_vis_args = []
 if cc.has_argument('-fvisibility=hidden')
   c_vis_args += '-fvisibility=hidden'
 endif
 
 # Check for generic C++ arguments
+cpp = meson.get_compiler('cpp')
 cpp_args = []
 foreach a : ['-Wall', '-fno-math-errno', '-fno-trapping-math',
              '-Qunused-arguments']
@@ -796,12 +791,9 @@ endforeach
 
 # For some reason, the test for -Wno-foo always succeeds with gcc, even if the
 # option is not supported. Hence, check for -Wfoo instead.
-
-foreach a : ['non-virtual-dtor', 'missing-field-initializers']
-  if cpp.has_argument('-W' + a)
-    cpp_args += '-Wno-' + a
-  endif
-endforeach
+if cpp.has_argument('-Wnon-virtual-dtor')
+  cpp_args += '-Wno-non-virtual-dtor'
+endif
 
 no_override_init_args = []
 foreach a : ['override-init', 'initializer-overrides']
@@ -886,44 +878,30 @@ if not cc.links('''#include <stdint.h>
   pre_args += '-DMISSING_64_BIT_ATOMICS'
 endif
 
+# TODO: endian
+# TODO: powr8
 # TODO: shared/static? Is this even worth doing?
 
-# When cross compiling we generally need to turn off the use of assembly,
-# because mesa's assembly relies on building an executable for the host system,
-# and running it to get information about struct sizes. There is at least one
-# case of cross compiling where we can use asm, and that's x86_64 -> x86 when
-# host OS == build OS, since in that case the build machine can run the host's
-# binaries.
+# Building x86 assembly code requires running x86 binaries. It is possible for
+# x86_64 OSes to run x86 binaries, so don't disable asm in those cases
+# TODO: it should be possible to use an exe_wrapper to run the binary during
+# the build. 
 if meson.is_cross_build() 
-  if build_machine.system() != host_machine.system()
-    # TODO: It may be possible to do this with an exe_wrapper (like wine).
-    message('Cross compiling from one OS to another, disabling assembly.')
-    with_asm = false
-  elif not (build_machine.cpu_family().startswith('x86') and host_machine.cpu_family() == 'x86')
-    # FIXME: Gentoo always sets -m32 for x86_64 -> x86 builds, resulting in an
-    # x86 -> x86 cross compile. We use startswith rather than == to handle this
-    # case.
-    # TODO: There may be other cases where the 64 bit version of the
-    # architecture can run 32 bit binaries (aarch64 and armv7 for example)
-    message('''
-      Cross compiling to different architectures, and the host cannot run
-      the build machine's binaries. Disabling assembly.
-    ''')
+  if not (build_machine.cpu_family().startswith('x86') and host_machine.cpu_family() == 'x86'
+          and build_machine.system() == host_machine.system())
+    message('Cross compiling to x86 from non-x86, disabling asm')
     with_asm = false
   endif
 endif
 
 with_asm_arch = ''
 if with_asm
+  # TODO: SPARC and PPC
   if host_machine.cpu_family() == 'x86'
     if system_has_kms_drm
       with_asm_arch = 'x86'
       pre_args += ['-DUSE_X86_ASM', '-DUSE_MMX_ASM', '-DUSE_3DNOW_ASM',
                    '-DUSE_SSE_ASM']
-
-      if with_glx_read_only_text
-         pre_args += ['-DGLX_X86_READONLY_TEXT']
-      endif
     endif
   elif host_machine.cpu_family() == 'x86_64'
     if system_has_kms_drm
@@ -940,16 +918,6 @@ if with_asm
       with_asm_arch = 'aarch64'
       pre_args += ['-DUSE_AARCH64_ASM']
     endif
-  elif host_machine.cpu_family() == 'sparc64'
-    if system_has_kms_drm
-      with_asm_arch = 'sparc'
-      pre_args += ['-DUSE_SPARC_ASM']
-    endif
-  elif host_machine.cpu_family() == 'ppc64le'
-    if system_has_kms_drm
-      with_asm_arch = 'ppc64le'
-      pre_args += ['-DUSE_PPC64LE_ASM']
-    endif
   endif
 endif
 
@@ -989,7 +957,7 @@ if cc.links('''
       freelocale(loc);
       return 0;
     }''',
-    extra_args : pre_args,
+    args : pre_args,
     name : 'strtod has locale support')
   pre_args += '-DHAVE_STRTOD_L'
 endif
@@ -1084,7 +1052,7 @@ _drm_amdgpu_ver = '2.4.91'
 _drm_radeon_ver = '2.4.71'
 _drm_nouveau_ver = '2.4.66'
 _drm_etnaviv_ver = '2.4.89'
-_drm_freedreno_ver = '2.4.92'
+_drm_freedreno_ver = '2.4.91'
 _drm_intel_ver = '2.4.75'
 _drm_ver = '2.4.75'
 
@@ -1098,12 +1066,6 @@ _libdrm_checks = [
   ['freedreno', with_gallium_freedreno],
 ]
 
-# VC4 only needs core libdrm support of this version, not a libdrm_vc4
-# library.
-if with_gallium_vc4
-  _drm_ver = '2.4.89'
-endif
-
 # Loop over the enables versions and get the highest libdrm requirement for all
 # active drivers.
 foreach d : _libdrm_checks
@@ -1136,7 +1098,6 @@ if dep_libdrm.found()
 endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
-llvm_optional_modules = []
 if with_amd_vk or with_gallium_radeonsi or with_gallium_r600
   llvm_modules += ['amdgpu', 'bitreader', 'ipo']
   if with_gallium_r600
@@ -1148,11 +1109,11 @@ if with_gallium_opencl
     'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 'irreader',
     'lto', 'option', 'objcarcopts', 'profiledata',
   ]
-  llvm_optional_modules += ['coroutines', 'opencl']
+  # TODO: optional modules
 endif
 
 if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
-  _llvm_version = '>= 5.0.0'
+  _llvm_version = '>= 4.0.0'
 elif with_gallium_opencl or with_gallium_r600
   _llvm_version = '>= 3.9.0'
 else
@@ -1162,20 +1123,12 @@ endif
 _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
-    'llvm',
-    version : _llvm_version,
-    modules : llvm_modules,
-    optional_modules : llvm_optional_modules,
+    'llvm', version : _llvm_version, modules : llvm_modules,
     required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or with_gallium_opencl,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
-  dep_llvm = dependency(
-    'llvm',
-    version : _llvm_version,
-    modules : llvm_modules,
-    optional_modules : llvm_optional_modules,
-  )
+  dep_llvm = dependency('llvm', version : _llvm_version, modules : llvm_modules)
   with_llvm = true
 else
   dep_llvm = null_dep
@@ -1204,13 +1157,6 @@ if with_llvm
     '-DHAVE_LLVM=0x0@0@0@1@'.format(_llvm_version[0], _llvm_version[1]),
     '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
   ]
-
-  # LLVM can be built without rtti, turning off rtti changes the ABI of C++
-  # programs, so we need to build all C++ code in mesa without rtti as well to
-  # ensure that linking works.
-  if dep_llvm.get_configtool_variable('has-rtti') == 'NO'
-    cpp_args += '-fno-rtti'
-  endif
 elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
   error('The following drivers require LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
 endif
@@ -1241,6 +1187,8 @@ if get_option('selinux')
   pre_args += '-DMESA_SELINUX'
 endif
 
+# TODO: llvm-prefix and llvm-shared-libs
+
 if with_libunwind != 'false'
   dep_unwind = dependency('libunwind', required : with_libunwind == 'true')
   if dep_unwind.found()
@@ -1250,6 +1198,8 @@ else
   dep_unwind = null_dep
 endif
 
+# TODO: gallium-hud
+
 if with_osmesa != 'none'
   if with_osmesa == 'classic' and not with_dri_swrast
     error('OSMesa classic requires dri (classic) swrast.')
@@ -1277,11 +1227,6 @@ if with_platform_wayland
   dep_wl_protocols = dependency('wayland-protocols', version : '>= 1.8')
   dep_wayland_client = dependency('wayland-client', version : '>=1.11')
   dep_wayland_server = dependency('wayland-server', version : '>=1.11')
-  if with_egl
-    dep_wayland_egl = dependency('wayland-egl-backend', version : '>= 3')
-    dep_wayland_egl_headers = declare_dependency(
-      compile_args : run_command(prog_pkgconfig, ['wayland-egl-backend', '--cflags']).stdout().split())
-  endif
   wayland_dmabuf_xml = join_paths(
     dep_wl_protocols.get_pkgconfig_variable('pkgdatadir'), 'unstable',
     'linux-dmabuf', 'linux-dmabuf-unstable-v1.xml'
@@ -1312,8 +1257,6 @@ dep_xcb_present = null_dep
 dep_xcb_sync = null_dep
 dep_xcb_xfixes = null_dep
 dep_xshmfence = null_dep
-dep_xcb_xrandr = null_dep
-dep_xlib_xrandr = null_dep
 if with_platform_x11
   if with_glx == 'xlib' or with_glx == 'gallium-xlib'
     dep_x11 = dependency('x11')
@@ -1360,10 +1303,6 @@ if with_platform_x11
       with_gallium_omx != 'disabled'))
     dep_xcb_xfixes = dependency('xcb-xfixes')
   endif
-  if with_xlib_lease
-    dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
-    dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
-  endif
 endif
 
 if get_option('gallium-extra-hud')
@@ -1380,6 +1319,18 @@ else
   dep_lmsensors = null_dep
 endif
 
+# TODO: various libdirs
+
+# TODO: gallium driver dirs
+
+# FIXME: this is a workaround for #2326
+prog_touch = find_program('touch')
+dummy_cpp = custom_target(
+  'dummy_cpp',
+  output : 'dummy.cpp',
+  command : [prog_touch, '@OUTPUT@'],
+)
+
 foreach a : pre_args
   add_project_arguments(a, language : ['c', 'cpp'])
 endforeach

meson_options.txt

@@ -1,4 +1,4 @@
-# Copyright © 2017-2018 Intel Corporation
+# Copyright © 2017 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -20,11 +20,8 @@
 
 option(
   'platforms',
-  type : 'array',
-  value : ['auto'],
-  choices : [
-    '', 'auto', 'x11', 'wayland', 'drm', 'surfaceless', 'haiku', 'android',
-  ],
+  type : 'string',
+  value : 'auto',
   description : 'comma separated list of window systems to support. If this is set to auto all platforms applicable to the OS will be enabled.'
 )
 option(
@@ -36,10 +33,9 @@ option(
 )
 option(
   'dri-drivers',
-  type : 'array',
-  value : ['auto'],
-  choices : ['', 'auto', 'i915', 'i965', 'r100', 'r200', 'nouveau', 'swrast'],
-  description : 'List of dri drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  type : 'string',
+  value : 'auto',
+  description : 'comma separated list of dri drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
 )
 option(
   'dri-drivers-path',
@@ -55,14 +51,9 @@ option(
 )
 option(
   'gallium-drivers',
-  type : 'array',
-  value : ['auto'],
-  choices : [
-    '', 'auto', 'pl111', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
-    'swrast', 'v3d', 'vc4', 'etnaviv', 'imx', 'tegra', 'i915', 'svga', 'virgl',
-    'swr',
-  ],
-  description : 'List of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  type : 'string',
+  value : 'auto',
+  description : 'comma separated list of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
 )
 option(
   'gallium-extra-hud',
@@ -150,10 +141,9 @@ option(
 )
 option(
   'vulkan-drivers',
-  type : 'array',
-  value : ['auto'],
-  choices : ['', 'auto', 'amd', 'intel'],
-  description : 'List of vulkan drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
+  type : 'string',
+  value : 'auto',
+  description : 'comma separated list of vulkan drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
 )
 option(
   'shader-cache',
@@ -224,12 +214,6 @@ option(
   value : true,
   description : 'Build assembly code if possible'
 )
-option(
-   'glx-read-only-text',
-   type : 'boolean',
-   value : false,
-   description : 'Disable writable .text section on x86 (decreases performance)'
-)
 option(
   'llvm',
   type : 'combo',
@@ -264,6 +248,12 @@ option(
   value : false,
   description : 'Build unit tests. Currently this will build *all* unit tests, which may build more than expected.'
 )
+option(
+  'texture-float',
+  type : 'boolean',
+  value : false,
+  description : 'Enable floating point textures and renderbuffers. This option may be patent encumbered, please read docs/patents.txt and consult with your lawyer before turning this on.'
+)
 option(
   'selinux',
   type : 'boolean',
@@ -286,29 +276,13 @@ option(
 )
 option(
   'swr-arches',
-  type : 'array',
-  value : ['avx', 'avx2'],
-  choices : ['avx', 'avx2', 'knl', 'skx'],
-  description : 'Architectures to build SWR support for.',
+  type : 'string',
+  value : 'avx,avx2',
+  description : 'Comma delemited swr architectures. choices : avx,avx2,knl,skx'
 )
 option(
   'tools',
-  type : 'array',
-  value : [],
-  choices : ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc', 'all'],
-  description : 'List of tools to build.',
-)
-option(
-  'power8',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'Enable power8 optimizations.',
-)
-option(
-  'xlib-lease',
-  type : 'combo',
-  value : 'auto',
-  choices : ['auto', 'true', 'false'],
-  description : 'Enable VK_EXT_acquire_xlib_display.'
+  type : 'string',
+  value : '',
+  description : 'Comma delimited list of tools to build. choices : freedreno,glsl,intel,nir,nouveau,xvmc or all'
 )

scons/gallium.py

@@ -392,6 +392,10 @@ def generate(env):
         cppdefines += ['PIPE_SUBSYSTEM_WINDOWS_USER']
     if env['embedded']:
         cppdefines += ['PIPE_SUBSYSTEM_EMBEDDED']
+    if env['texture_float']:
+        print('warning: Floating-point textures enabled.')
+        print('warning: Please consult docs/patents.txt with your lawyer before building Mesa.')
+        cppdefines += ['TEXTURE_FLOAT_ENABLED']
     env.Append(CPPDEFINES = cppdefines)
 
     # C compiler options

scons/llvm.py

@@ -123,10 +123,6 @@ def generate(env):
                 'LLVMDemangle', 'LLVMGlobalISel', 'LLVMDebugInfoMSF',
                 'LLVMBinaryFormat',
             ])
-            if env['platform'] == 'windows' and env['crosscompile']:
-                # LLVM 5.0 requires MinGW w/ pthreads due to use of std::thread and friends.
-                assert env['gcc']
-                env['CXX'] = env['CXX'] + '-posix'
         elif llvm_version >= distutils.version.LooseVersion('4.0'):
             env.Prepend(LIBS = [
                 'LLVMX86Disassembler', 'LLVMX86AsmParser',
@@ -215,11 +211,8 @@ def generate(env):
             'imagehlp',
             'psapi',
             'shell32',
-            'advapi32',
-            'ole32',
-            'uuid',
+            'advapi32'
         ])
-
         if env['msvc']:
             # Some of the LLVM C headers use the inline keyword without
             # defining it.

src/Makefile.am

@@ -95,6 +95,11 @@ if HAVE_GBM
 SUBDIRS += gbm
 endif
 
+## Optionally required by EGL
+if HAVE_PLATFORM_WAYLAND
+SUBDIRS += egl/wayland/wayland-egl
+endif
+
 if HAVE_EGL
 SUBDIRS += egl
 endif

src/amd/Android.mk

@@ -27,4 +27,3 @@ include $(LOCAL_PATH)/Makefile.sources
 
 include $(LOCAL_PATH)/Android.addrlib.mk
 include $(LOCAL_PATH)/Android.common.mk
-include $(LOCAL_PATH)/vulkan/Android.mk

src/amd/addrlib/amdgpu_asic_addr.h

@@ -87,7 +87,6 @@
 
 #define AMDGPU_VEGA10_RANGE     0x01, 0x14
 #define AMDGPU_VEGA12_RANGE     0x14, 0x28
-#define AMDGPU_VEGA20_RANGE     0x28, 0xFF
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
 
@@ -129,7 +128,6 @@
 #define ASICREV_IS_VEGA10_P(r)         ASICREV_IS(r, VEGA10)
 #define ASICREV_IS_VEGA12_P(r)         ASICREV_IS(r, VEGA12)
 #define ASICREV_IS_VEGA12_p(r)         ASICREV_IS(r, VEGA12)
-#define ASICREV_IS_VEGA20_P(r)         ASICREV_IS(r, VEGA20)
 
 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
 

src/amd/addrlib/gfx9/gfx9addrlib.cpp

@@ -1230,7 +1230,6 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
         {
             ADDR_ASSERT(m_settings.isVega10 == FALSE);
             ADDR_ASSERT(m_settings.isRaven == FALSE);
-            ADDR_ASSERT(m_settings.isVega20 == FALSE);
 
             if (m_settings.isVega12)
             {
@@ -1274,7 +1273,7 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
             m_settings.isArcticIsland = 1;
             m_settings.isVega10    = ASICREV_IS_VEGA10_P(uChipRevision);
             m_settings.isVega12    = ASICREV_IS_VEGA12_P(uChipRevision);
-            m_settings.isVega20    = ASICREV_IS_VEGA20_P(uChipRevision);
+
             m_settings.isDce12 = 1;
 
             if (m_settings.isVega10 == 0)

src/amd/addrlib/gfx9/gfx9addrlib.h

@@ -56,7 +56,6 @@ struct Gfx9ChipSettings
         UINT_32 isVega10            : 1;
         UINT_32 isRaven             : 1;
         UINT_32 isVega12            : 1;
-        UINT_32 isVega20            : 1;
 
         // Display engine IP version name
         UINT_32 isDce12             : 1;

src/amd/common/ac_binary.h

@@ -27,10 +27,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 struct ac_shader_reloc {
 	char name[32];
 	uint64_t offset;
@@ -102,8 +98,4 @@ void ac_shader_binary_read_config(struct ac_shader_binary *binary,
 				  bool supports_spill);
 void ac_shader_binary_clean(struct ac_shader_binary *b);
 
-#ifdef __cplusplus
-}
-#endif
-
 #endif /* AC_BINARY_H */

src/amd/common/ac_gpu_info.c

@@ -96,7 +96,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		       struct radeon_info *info,
 		       struct amdgpu_gpu_info *amdinfo)
 {
-	struct drm_amdgpu_info_device device_info = {};
 	struct amdgpu_buffer_size_alignments alignment_info = {};
 	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
 	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
@@ -125,13 +124,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		return false;
 	}
 
-	r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
-			      &device_info);
-	if (r) {
-		fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
-		return false;
-	}
-
 	r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 	if (r) {
 		fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
@@ -243,7 +235,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	}
 
 	if (info->drm_minor >= 9) {
-		struct drm_amdgpu_memory_info meminfo = {};
+		struct drm_amdgpu_memory_info meminfo;
 
 		r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
 		if (r) {
@@ -332,7 +324,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
 	/* convert the shader clock from KHz to MHz */
 	info->max_shader_clock = amdinfo->max_engine_clk / 1000;
-	info->num_tcc_blocks = device_info.num_tcc_blocks;
 	info->max_se = amdinfo->num_shader_engines;
 	info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 	info->has_hw_decode =
@@ -352,34 +343,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_local_buffers = info->drm_minor >= 20 &&
 				  !info->has_dedicated_vram;
 	info->kernel_flushes_hdp_before_ib = true;
-	info->htile_cmask_support_1d_tiling = true;
-	info->si_TA_CS_BC_BASE_ADDR_allowed = true;
-	info->has_bo_metadata = true;
-	info->has_gpu_reset_status_query = true;
-	info->has_gpu_reset_counter_query = false;
-	info->has_eqaa_surface_allocator = true;
-	info->has_format_bc1_through_bc7 = true;
-	/* DRM 3.1.0 doesn't flush TC for VI correctly. */
-	info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
-					      info->drm_minor >= 2;
-	info->has_indirect_compute_dispatch = true;
-	/* SI doesn't support unaligned loads. */
-	info->has_unaligned_shader_loads = info->chip_class != SI;
-	/* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
-	 * these faults are mitigated in software.
-	 * Disable sparse mappings on GFX9 due to hangs.
-	 */
-	info->has_sparse_vm_mappings =
-		info->chip_class >= CIK && info->chip_class <= VI &&
-		info->drm_minor >= 13;
-	info->has_2d_tiling = true;
-	info->has_read_registers_query = true;
 
 	info->num_render_backends = amdinfo->rb_pipes;
-	/* The value returned by the kernel driver was wrong. */
-	if (info->family == CHIP_KAVERI)
-		info->num_render_backends = 2;
-
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
@@ -512,7 +477,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    vce_fw_version = %u\n", info->vce_fw_version);
 	printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
 
-	printf("Kernel & winsys capabilities:\n");
+	printf("Kernel info:\n");
 	printf("    drm = %i.%i.%i\n", info->drm_major,
 	       info->drm_minor, info->drm_patchlevel);
 	printf("    has_userptr = %i\n", info->has_userptr);
@@ -522,24 +487,10 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
 	printf("    has_local_buffers = %u\n", info->has_local_buffers);
 	printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
-	printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
-	printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
-	printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
-	printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
-	printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
-	printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
-	printf("    has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
-	printf("    kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
-	printf("    has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
-	printf("    has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
-	printf("    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
-	printf("    has_2d_tiling = %u\n", info->has_2d_tiling);
-	printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
 	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
-	printf("    num_tcc_blocks = %i\n", info->num_tcc_blocks);
 	printf("    max_se = %i\n", info->max_se);
 	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
@@ -599,235 +550,3 @@ void ac_print_gpu_info(struct radeon_info *info)
 		       G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
 	}
 }
-
-int
-ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
-{
-	if (chip_class >= GFX9)
-		return -1;
-
-	switch (family) {
-	case CHIP_OLAND:
-	case CHIP_HAINAN:
-	case CHIP_KAVERI:
-	case CHIP_KABINI:
-	case CHIP_MULLINS:
-	case CHIP_ICELAND:
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
-		return 16;
-	case CHIP_TAHITI:
-	case CHIP_PITCAIRN:
-	case CHIP_VERDE:
-	case CHIP_BONAIRE:
-	case CHIP_HAWAII:
-	case CHIP_TONGA:
-	case CHIP_FIJI:
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-		return 32;
-	default:
-		unreachable("Unknown GPU");
-	}
-}
-
-void
-ac_get_raster_config(struct radeon_info *info,
-		     uint32_t *raster_config_p,
-		     uint32_t *raster_config_1_p)
-{
-	unsigned raster_config, raster_config_1;
-
-	switch (info->family) {
-	/* 1 SE / 1 RB */
-	case CHIP_HAINAN:
-	case CHIP_KABINI:
-	case CHIP_MULLINS:
-	case CHIP_STONEY:
-		raster_config = 0x00000000;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 1 SE / 4 RBs */
-	case CHIP_VERDE:
-		raster_config = 0x0000124a;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 1 SE / 2 RBs (Oland is special) */
-	case CHIP_OLAND:
-		raster_config = 0x00000082;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 1 SE / 2 RBs */
-	case CHIP_KAVERI:
-	case CHIP_ICELAND:
-	case CHIP_CARRIZO:
-		raster_config = 0x00000002;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 2 SEs / 4 RBs */
-	case CHIP_BONAIRE:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-		raster_config = 0x16000012;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 2 SEs / 8 RBs */
-	case CHIP_TAHITI:
-	case CHIP_PITCAIRN:
-		raster_config = 0x2a00126a;
-		raster_config_1 = 0x00000000;
-		break;
-	/* 4 SEs / 8 RBs */
-	case CHIP_TONGA:
-	case CHIP_POLARIS10:
-		raster_config = 0x16000012;
-		raster_config_1 = 0x0000002a;
-		break;
-	/* 4 SEs / 16 RBs */
-	case CHIP_HAWAII:
-	case CHIP_FIJI:
-	case CHIP_VEGAM:
-		raster_config = 0x3a00161a;
-		raster_config_1 = 0x0000002e;
-		break;
-	default:
-		fprintf(stderr,
-			"ac: Unknown GPU, using 0 for raster_config\n");
-		raster_config = 0x00000000;
-		raster_config_1 = 0x00000000;
-		break;
-	}
-
-	/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
-	 * This decreases performance by up to 50% when the RB is the bottleneck.
-	 */
-	if (info->family == CHIP_KAVERI && info->drm_major == 2)
-		raster_config = 0x00000000;
-
-	/* Fiji: Old kernels have incorrect tiling config. This decreases
-	 * RB performance by 25%. (it disables 1 RB in the second packer)
-	 */
-	if (info->family == CHIP_FIJI &&
-	    info->cik_macrotile_mode_array[0] == 0x000000e8) {
-		raster_config = 0x16000012;
-		raster_config_1 = 0x0000002a;
-	}
-
-	*raster_config_p = raster_config;
-	*raster_config_1_p = raster_config_1;
-}
-
-void
-ac_get_harvested_configs(struct radeon_info *info,
-			 unsigned raster_config,
-			 unsigned *cik_raster_config_1_p,
-			 unsigned *raster_config_se)
-{
-	unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
-	unsigned num_se = MAX2(info->max_se, 1);
-	unsigned rb_mask = info->enabled_rb_mask;
-	unsigned num_rb = MIN2(info->num_render_backends, 16);
-	unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
-	unsigned rb_per_se = num_rb / num_se;
-	unsigned se_mask[4];
-	unsigned se;
-
-	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
-	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
-	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
-	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
-
-	assert(num_se == 1 || num_se == 2 || num_se == 4);
-	assert(sh_per_se == 1 || sh_per_se == 2);
-	assert(rb_per_pkr == 1 || rb_per_pkr == 2);
-
-
-	if (info->chip_class >= CIK) {
-		unsigned raster_config_1 = *cik_raster_config_1_p;
-		if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
-				     (!se_mask[2] && !se_mask[3]))) {
-			raster_config_1 &= C_028354_SE_PAIR_MAP;
-
-			if (!se_mask[0] && !se_mask[1]) {
-				raster_config_1 |=
-					S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
-			} else {
-				raster_config_1 |=
-					S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
-			}
-			*cik_raster_config_1_p = raster_config_1;
-		}
-	}
-
-	for (se = 0; se < num_se; se++) {
-		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
-		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
-		int idx = (se / 2) * 2;
-
-		raster_config_se[se] = raster_config;
-		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
-			raster_config_se[se] &= C_028350_SE_MAP;
-
-			if (!se_mask[idx]) {
-				raster_config_se[se] |=
-					S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
-			} else {
-				raster_config_se[se] |=
-					S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
-			}
-		}
-
-		pkr0_mask &= rb_mask;
-		pkr1_mask &= rb_mask;
-		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
-			raster_config_se[se] &= C_028350_PKR_MAP;
-
-			if (!pkr0_mask) {
-				raster_config_se[se] |=
-					S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
-			} else {
-				raster_config_se[se] |=
-					S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
-			}
-		}
-
-		if (rb_per_se >= 2) {
-			unsigned rb0_mask = 1 << (se * rb_per_se);
-			unsigned rb1_mask = rb0_mask << 1;
-
-			rb0_mask &= rb_mask;
-			rb1_mask &= rb_mask;
-			if (!rb0_mask || !rb1_mask) {
-				raster_config_se[se] &= C_028350_RB_MAP_PKR0;
-
-				if (!rb0_mask) {
-					raster_config_se[se] |=
-						S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
-				} else {
-					raster_config_se[se] |=
-						S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
-				}
-			}
-
-			if (rb_per_se > 2) {
-				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
-				rb1_mask = rb0_mask << 1;
-				rb0_mask &= rb_mask;
-				rb1_mask &= rb_mask;
-				if (!rb0_mask || !rb1_mask) {
-					raster_config_se[se] &= C_028350_RB_MAP_PKR1;
-
-					if (!rb0_mask) {
-						raster_config_se[se] |=
-							S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
-					} else {
-						raster_config_se[se] |=
-							S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
-					}
-				}
-			}
-		}
-	}
-}

src/amd/common/ac_gpu_info.h

@@ -86,7 +86,7 @@ struct radeon_info {
 	uint32_t                    vce_fw_version;
 	uint32_t                    vce_harvest_config;
 
-	/* Kernel & winsys capabilities. */
+	/* Kernel info. */
 	uint32_t                    drm_major; /* version */
 	uint32_t                    drm_minor;
 	uint32_t                    drm_patchlevel;
@@ -97,25 +97,11 @@ struct radeon_info {
 	bool                        has_ctx_priority;
 	bool                        has_local_buffers;
 	bool                        kernel_flushes_hdp_before_ib;
-	bool                        htile_cmask_support_1d_tiling;
-	bool                        si_TA_CS_BC_BASE_ADDR_allowed;
-	bool                        has_bo_metadata;
-	bool                        has_gpu_reset_status_query;
-	bool                        has_gpu_reset_counter_query;
-	bool                        has_eqaa_surface_allocator;
-	bool                        has_format_bc1_through_bc7;
-	bool                        kernel_flushes_tc_l2_after_ib;
-	bool                        has_indirect_compute_dispatch;
-	bool                        has_unaligned_shader_loads;
-	bool                        has_sparse_vm_mappings;
-	bool                        has_2d_tiling;
-	bool                        has_read_registers_query;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
-	uint32_t                    num_tcc_blocks;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
@@ -145,29 +131,6 @@ void ac_compute_driver_uuid(char *uuid, size_t size);
 
 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 void ac_print_gpu_info(struct radeon_info *info);
-int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
-void ac_get_raster_config(struct radeon_info *info,
-			  uint32_t *raster_config_p,
-			  uint32_t *raster_config_1_p);
-void ac_get_harvested_configs(struct radeon_info *info,
-			      unsigned raster_config,
-			      unsigned *cik_raster_config_1_p,
-			      unsigned *raster_config_se);
-
-static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
-{
-
-	switch (family) {
-	/* These always have 8 waves: */
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-		return 8;
-	default:
-		return 10;
-	}
-}
 
 #ifdef __cplusplus
 }

src/amd/common/ac_llvm_build.c

@@ -57,15 +57,15 @@ struct ac_llvm_flow {
  * The caller is responsible for initializing ctx::module and ctx::builder.
  */
 void
-ac_llvm_context_init(struct ac_llvm_context *ctx,
+ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 		     enum chip_class chip_class, enum radeon_family family)
 {
 	LLVMValueRef args[1];
 
-	ctx->context = LLVMContextCreate();
-
 	ctx->chip_class = chip_class;
 	ctx->family = family;
+
+	ctx->context = context;
 	ctx->module = NULL;
 	ctx->builder = NULL;
 
@@ -175,8 +175,6 @@ ac_get_type_size(LLVMTypeRef type)
 	switch (kind) {
 	case LLVMIntegerTypeKind:
 		return LLVMGetIntTypeWidth(type) / 8;
-	case LLVMHalfTypeKind:
-		return 2;
 	case LLVMFloatTypeKind:
 		return 4;
 	case LLVMDoubleTypeKind:
@@ -322,9 +320,6 @@ void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned bufsize)
 	case LLVMIntegerTypeKind:
 		snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
 		break;
-	case LLVMHalfTypeKind:
-		snprintf(buf, bufsize, "f16");
-		break;
 	case LLVMFloatTypeKind:
 		snprintf(buf, bufsize, "f32");
 		break;
@@ -893,35 +888,36 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
 			    bool writeonly_memory,
 			    bool swizzle_enable_hint)
 {
-	/* Split 3 channel stores, becase LLVM doesn't support 3-channel
-	 * intrinsics. */
-	if (num_channels == 3) {
-		LLVMValueRef v[3], v01;
-
-		for (int i = 0; i < 3; i++) {
-			v[i] = LLVMBuildExtractElement(ctx->builder, vdata,
-					LLVMConstInt(ctx->i32, i, 0), "");
-		}
-		v01 = ac_build_gather_values(ctx, v, 2);
-
-		ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,
-					    soffset, inst_offset, glc, slc,
-					    writeonly_memory, swizzle_enable_hint);
-		ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
-					    soffset, inst_offset + 8,
-					    glc, slc,
-					    writeonly_memory, swizzle_enable_hint);
-		return;
-	}
-
 	/* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
 	 * (voffset is swizzled, but soffset isn't swizzled).
 	 * llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
 	 */
 	if (!swizzle_enable_hint) {
-		LLVMValueRef offset = soffset;
+		/* Split 3 channel stores, becase LLVM doesn't support 3-channel
+		 * intrinsics. */
+		if (num_channels == 3) {
+			LLVMValueRef v[3], v01;
 
+			for (int i = 0; i < 3; i++) {
+				v[i] = LLVMBuildExtractElement(ctx->builder, vdata,
+						LLVMConstInt(ctx->i32, i, 0), "");
+			}
+			v01 = ac_build_gather_values(ctx, v, 2);
+
+			ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,
+						    soffset, inst_offset, glc, slc,
+						    writeonly_memory, swizzle_enable_hint);
+			ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
+						    soffset, inst_offset + 8,
+						    glc, slc,
+						    writeonly_memory, swizzle_enable_hint);
+			return;
+		}
+
+		unsigned func = CLAMP(num_channels, 1, 3) - 1;
 		static const char *types[] = {"f32", "v2f32", "v4f32"};
+		char name[256];
+		LLVMValueRef offset = soffset;
 
 		if (inst_offset)
 			offset = LLVMBuildAdd(ctx->builder, offset,
@@ -938,46 +934,53 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
 			LLVMConstInt(ctx->i1, slc, 0),
 		};
 
-		char name[256];
 		snprintf(name, sizeof(name), "llvm.amdgcn.buffer.store.%s",
-			 types[CLAMP(num_channels, 1, 3) - 1]);
+			 types[func]);
 
 		ac_build_intrinsic(ctx, name, ctx->voidt,
 				   args, ARRAY_SIZE(args),
 				   writeonly_memory ?
-				   AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
-				   AC_FUNC_ATTR_WRITEONLY);
+					   AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
+					   AC_FUNC_ATTR_WRITEONLY);
 		return;
 	}
 
-	static const unsigned dfmt[] = {
+	static unsigned dfmt[] = {
 		V_008F0C_BUF_DATA_FORMAT_32,
 		V_008F0C_BUF_DATA_FORMAT_32_32,
 		V_008F0C_BUF_DATA_FORMAT_32_32_32,
 		V_008F0C_BUF_DATA_FORMAT_32_32_32_32
 	};
-	static const char *types[] = {"i32", "v2i32", "v4i32"};
+	assert(num_channels >= 1 && num_channels <= 4);
+
 	LLVMValueRef args[] = {
+		rsrc,
 		vdata,
-		LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, ""),
-		LLVMConstInt(ctx->i32, 0, 0),
-		voffset ? voffset : LLVMConstInt(ctx->i32, 0, 0),
+		LLVMConstInt(ctx->i32, num_channels, 0),
+		voffset ? voffset : LLVMGetUndef(ctx->i32),
 		soffset,
 		LLVMConstInt(ctx->i32, inst_offset, 0),
 		LLVMConstInt(ctx->i32, dfmt[num_channels - 1], 0),
 		LLVMConstInt(ctx->i32, V_008F0C_BUF_NUM_FORMAT_UINT, 0),
-		LLVMConstInt(ctx->i1, glc, 0),
-		LLVMConstInt(ctx->i1, slc, 0),
+		LLVMConstInt(ctx->i32, voffset != NULL, 0),
+		LLVMConstInt(ctx->i32, 0, 0), /* idxen */
+		LLVMConstInt(ctx->i32, glc, 0),
+		LLVMConstInt(ctx->i32, slc, 0),
+		LLVMConstInt(ctx->i32, 0, 0), /* tfe*/
 	};
+
+	/* The instruction offset field has 12 bits */
+	assert(voffset || inst_offset < (1 << 12));
+
+	/* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
+	unsigned func = CLAMP(num_channels, 1, 3) - 1;
+	const char *types[] = {"i32", "v2i32", "v4i32"};
 	char name[256];
-	snprintf(name, sizeof(name), "llvm.amdgcn.tbuffer.store.%s",
-		 types[CLAMP(num_channels, 1, 3) - 1]);
+	snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
 
 	ac_build_intrinsic(ctx, name, ctx->voidt,
 			   args, ARRAY_SIZE(args),
-			   writeonly_memory ?
-				   AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
-				   AC_FUNC_ATTR_WRITEONLY);
+			   AC_FUNC_ATTR_LEGACY);
 }
 
 static LLVMValueRef
@@ -1103,31 +1106,6 @@ LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
 	                                   can_speculate, true);
 }
 
-LLVMValueRef
-ac_build_tbuffer_load_short(struct ac_llvm_context *ctx,
-			    LLVMValueRef rsrc,
-			    LLVMValueRef vindex,
-			    LLVMValueRef voffset,
-				LLVMValueRef soffset,
-				LLVMValueRef immoffset)
-{
-	const char *name = "llvm.amdgcn.tbuffer.load.i32";
-	LLVMTypeRef type = ctx->i32;
-	LLVMValueRef params[] = {
-				rsrc,
-				vindex,
-				voffset,
-				soffset,
-				immoffset,
-				LLVMConstInt(ctx->i32, V_008F0C_BUF_DATA_FORMAT_16, false),
-				LLVMConstInt(ctx->i32, V_008F0C_BUF_NUM_FORMAT_UINT, false),
-				ctx->i1false,
-				ctx->i1false,
-	};
-	LLVMValueRef res = ac_build_intrinsic(ctx, name, type, params, 9, 0);
-	return LLVMBuildTrunc(ctx->builder, res, ctx->i16, "");
-}
-
 /**
  * Set range metadata on an instruction.  This can only be used on load and
  * call instructions.  If you know an instruction can only produce the values
@@ -1200,21 +1178,7 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
 	LLVMValueRef tl, trbl, args[2];
 	LLVMValueRef result;
 
-	if (HAVE_LLVM >= 0x0700) {
-		unsigned tl_lanes[4], trbl_lanes[4];
-
-		for (unsigned i = 0; i < 4; ++i) {
-			tl_lanes[i] = i & mask;
-			trbl_lanes[i] = (i & mask) + idx;
-		}
-
-		tl = ac_build_quad_swizzle(ctx, val,
-		                           tl_lanes[0], tl_lanes[1],
-		                           tl_lanes[2], tl_lanes[3]);
-		trbl = ac_build_quad_swizzle(ctx, val,
-		                             trbl_lanes[0], trbl_lanes[1],
-		                             trbl_lanes[2], trbl_lanes[3]);
-	} else if (ctx->chip_class >= VI) {
+	if (ctx->chip_class >= VI) {
 		LLVMValueRef thread_id, tl_tid, trbl_tid;
 		thread_id = ac_get_thread_id(ctx);
 
@@ -1284,13 +1248,6 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
 	tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
 	trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
 	result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
-
-	if (HAVE_LLVM >= 0x0700) {
-		result = ac_build_intrinsic(ctx,
-			"llvm.amdgcn.wqm.f32", ctx->f32,
-			&result, 1, 0);
-	}
-
 	return result;
 }
 
@@ -1410,41 +1367,66 @@ LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
 
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
-	return ac_build_fmin(ctx, ac_build_fmax(ctx, value, ctx->f32_0),
-			     ctx->f32_1);
+	if (HAVE_LLVM >= 0x0500) {
+		return ac_build_fmin(ctx, ac_build_fmax(ctx, value, ctx->f32_0),
+				     ctx->f32_1);
+	}
+
+	LLVMValueRef args[3] = {
+		value,
+		LLVMConstReal(ctx->f32, 0),
+		LLVMConstReal(ctx->f32, 1),
+	};
+
+	return ac_build_intrinsic(ctx, "llvm.AMDGPU.clamp.", ctx->f32, args, 3,
+				  AC_FUNC_ATTR_READNONE |
+				  AC_FUNC_ATTR_LEGACY);
 }
 
 void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
 {
 	LLVMValueRef args[9];
 
-	args[0] = LLVMConstInt(ctx->i32, a->target, 0);
-	args[1] = LLVMConstInt(ctx->i32, a->enabled_channels, 0);
+	if (HAVE_LLVM >= 0x0500) {
+		args[0] = LLVMConstInt(ctx->i32, a->target, 0);
+		args[1] = LLVMConstInt(ctx->i32, a->enabled_channels, 0);
 
-	if (a->compr) {
-		LLVMTypeRef i16 = LLVMInt16TypeInContext(ctx->context);
-		LLVMTypeRef v2i16 = LLVMVectorType(i16, 2);
+		if (a->compr) {
+			LLVMTypeRef i16 = LLVMInt16TypeInContext(ctx->context);
+			LLVMTypeRef v2i16 = LLVMVectorType(i16, 2);
 
-		args[2] = LLVMBuildBitCast(ctx->builder, a->out[0],
-				v2i16, "");
-		args[3] = LLVMBuildBitCast(ctx->builder, a->out[1],
-				v2i16, "");
-		args[4] = LLVMConstInt(ctx->i1, a->done, 0);
-		args[5] = LLVMConstInt(ctx->i1, a->valid_mask, 0);
+			args[2] = LLVMBuildBitCast(ctx->builder, a->out[0],
+						   v2i16, "");
+			args[3] = LLVMBuildBitCast(ctx->builder, a->out[1],
+						   v2i16, "");
+			args[4] = LLVMConstInt(ctx->i1, a->done, 0);
+			args[5] = LLVMConstInt(ctx->i1, a->valid_mask, 0);
 
-		ac_build_intrinsic(ctx, "llvm.amdgcn.exp.compr.v2i16",
-				   ctx->voidt, args, 6, 0);
-	} else {
-		args[2] = a->out[0];
-		args[3] = a->out[1];
-		args[4] = a->out[2];
-		args[5] = a->out[3];
-		args[6] = LLVMConstInt(ctx->i1, a->done, 0);
-		args[7] = LLVMConstInt(ctx->i1, a->valid_mask, 0);
+			ac_build_intrinsic(ctx, "llvm.amdgcn.exp.compr.v2i16",
+					   ctx->voidt, args, 6, 0);
+		} else {
+			args[2] = a->out[0];
+			args[3] = a->out[1];
+			args[4] = a->out[2];
+			args[5] = a->out[3];
+			args[6] = LLVMConstInt(ctx->i1, a->done, 0);
+			args[7] = LLVMConstInt(ctx->i1, a->valid_mask, 0);
 
-		ac_build_intrinsic(ctx, "llvm.amdgcn.exp.f32",
-				   ctx->voidt, args, 8, 0);
+			ac_build_intrinsic(ctx, "llvm.amdgcn.exp.f32",
+					   ctx->voidt, args, 8, 0);
+		}
+		return;
 	}
+
+	args[0] = LLVMConstInt(ctx->i32, a->enabled_channels, 0);
+	args[1] = LLVMConstInt(ctx->i32, a->valid_mask, 0);
+	args[2] = LLVMConstInt(ctx->i32, a->done, 0);
+	args[3] = LLVMConstInt(ctx->i32, a->target, 0);
+	args[4] = LLVMConstInt(ctx->i32, a->compr, 0);
+	memcpy(args + 5, a->out, sizeof(a->out[0]) * 4);
+
+	ac_build_intrinsic(ctx, "llvm.SI.export", ctx->voidt, args, 9,
+			   AC_FUNC_ATTR_LEGACY);
 }
 
 void ac_build_export_null(struct ac_llvm_context *ctx)
@@ -1503,26 +1485,8 @@ static unsigned ac_num_derivs(enum ac_image_dim dim)
 	}
 }
 
-static const char *get_atomic_name(enum ac_atomic_op op)
-{
-	switch (op) {
-	case ac_atomic_swap: return "swap";
-	case ac_atomic_add: return "add";
-	case ac_atomic_sub: return "sub";
-	case ac_atomic_smin: return "smin";
-	case ac_atomic_umin: return "umin";
-	case ac_atomic_smax: return "smax";
-	case ac_atomic_umax: return "umax";
-	case ac_atomic_and: return "and";
-	case ac_atomic_or: return "or";
-	case ac_atomic_xor: return "xor";
-	}
-	unreachable("bad atomic op");
-}
-
-/* LLVM 6 and older */
-static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
-						struct ac_image_args *a)
+LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
+				   struct ac_image_args *a)
 {
 	LLVMValueRef args[16];
 	LLVMTypeRef retty = ctx->v4f32;
@@ -1530,6 +1494,16 @@ static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
 	const char *atomic_subop = "";
 	char intr_name[128], coords_type[64];
 
+	assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
+	       !a->level_zero);
+	assert((a->opcode != ac_image_get_resinfo && a->opcode != ac_image_load_mip &&
+		a->opcode != ac_image_store_mip) ||
+	       a->lod);
+	assert((a->bias ? 1 : 0) +
+	       (a->lod ? 1 : 0) +
+	       (a->level_zero ? 1 : 0) +
+	       (a->derivs[0] ? 1 : 0) <= 1);
+
 	bool sample = a->opcode == ac_image_sample ||
 		      a->opcode == ac_image_gather4 ||
 		      a->opcode == ac_image_get_lod;
@@ -1641,7 +1615,18 @@ static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
 		if (a->opcode == ac_image_atomic_cmpswap) {
 			atomic_subop = "cmpswap";
 		} else {
-			atomic_subop = get_atomic_name(a->atomic);
+			switch (a->atomic) {
+			case ac_atomic_swap: atomic_subop = "swap"; break;
+			case ac_atomic_add: atomic_subop = "add"; break;
+			case ac_atomic_sub: atomic_subop = "sub"; break;
+			case ac_atomic_smin: atomic_subop = "smin"; break;
+			case ac_atomic_umin: atomic_subop = "umin"; break;
+			case ac_atomic_smax: atomic_subop = "smax"; break;
+			case ac_atomic_umax: atomic_subop = "umax"; break;
+			case ac_atomic_and: atomic_subop = "and"; break;
+			case ac_atomic_or: atomic_subop = "or"; break;
+			case ac_atomic_xor: atomic_subop = "xor"; break;
+			}
 		}
 		break;
 	case ac_image_get_lod:
@@ -1685,173 +1670,22 @@ static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
 	return result;
 }
 
-LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
-				   struct ac_image_args *a)
-{
-	const char *overload[3] = { "", "", "" };
-	unsigned num_overloads = 0;
-	LLVMValueRef args[18];
-	unsigned num_args = 0;
-	enum ac_image_dim dim = a->dim;
-
-	assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
-	       !a->level_zero);
-	assert((a->opcode != ac_image_get_resinfo && a->opcode != ac_image_load_mip &&
-		a->opcode != ac_image_store_mip) ||
-	       a->lod);
-	assert(a->opcode == ac_image_sample || a->opcode == ac_image_gather4 ||
-	       (!a->compare && !a->offset));
-	assert((a->opcode == ac_image_sample || a->opcode == ac_image_gather4 ||
-		a->opcode == ac_image_get_lod) ||
-	       !a->bias);
-	assert((a->bias ? 1 : 0) +
-	       (a->lod ? 1 : 0) +
-	       (a->level_zero ? 1 : 0) +
-	       (a->derivs[0] ? 1 : 0) <= 1);
-
-	if (HAVE_LLVM < 0x0700)
-		return ac_build_image_opcode_llvm6(ctx, a);
-
-	if (a->opcode == ac_image_get_lod) {
-		switch (dim) {
-		case ac_image_1darray:
-			dim = ac_image_1d;
-			break;
-		case ac_image_2darray:
-		case ac_image_cube:
-			dim = ac_image_2d;
-			break;
-		default:
-			break;
-		}
-	}
-
-	bool sample = a->opcode == ac_image_sample ||
-		      a->opcode == ac_image_gather4 ||
-		      a->opcode == ac_image_get_lod;
-	bool atomic = a->opcode == ac_image_atomic ||
-		      a->opcode == ac_image_atomic_cmpswap;
-	LLVMTypeRef coord_type = sample ? ctx->f32 : ctx->i32;
-
-	if (atomic || a->opcode == ac_image_store || a->opcode == ac_image_store_mip) {
-		args[num_args++] = a->data[0];
-		if (a->opcode == ac_image_atomic_cmpswap)
-			args[num_args++] = a->data[1];
-	}
-
-	if (!atomic)
-		args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, false);
-
-	if (a->offset)
-		args[num_args++] = ac_to_integer(ctx, a->offset);
-	if (a->bias) {
-		args[num_args++] = ac_to_float(ctx, a->bias);
-		overload[num_overloads++] = ".f32";
-	}
-	if (a->compare)
-		args[num_args++] = ac_to_float(ctx, a->compare);
-	if (a->derivs[0]) {
-		unsigned count = ac_num_derivs(dim);
-		for (unsigned i = 0; i < count; ++i)
-			args[num_args++] = ac_to_float(ctx, a->derivs[i]);
-		overload[num_overloads++] = ".f32";
-	}
-	unsigned num_coords =
-		a->opcode != ac_image_get_resinfo ? ac_num_coords(dim) : 0;
-	for (unsigned i = 0; i < num_coords; ++i)
-		args[num_args++] = LLVMBuildBitCast(ctx->builder, a->coords[i], coord_type, "");
-	if (a->lod)
-		args[num_args++] = LLVMBuildBitCast(ctx->builder, a->lod, coord_type, "");
-	overload[num_overloads++] = sample ? ".f32" : ".i32";
-
-	args[num_args++] = a->resource;
-	if (sample) {
-		args[num_args++] = a->sampler;
-		args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, false);
-	}
-
-	args[num_args++] = ctx->i32_0; /* texfailctrl */
-	args[num_args++] = LLVMConstInt(ctx->i32, a->cache_policy, false);
-
-	const char *name;
-	const char *atomic_subop = "";
-	switch (a->opcode) {
-	case ac_image_sample: name = "sample"; break;
-	case ac_image_gather4: name = "gather4"; break;
-	case ac_image_load: name = "load"; break;
-	case ac_image_load_mip: name = "load.mip"; break;
-	case ac_image_store: name = "store"; break;
-	case ac_image_store_mip: name = "store.mip"; break;
-	case ac_image_atomic:
-		name = "atomic.";
-		atomic_subop = get_atomic_name(a->atomic);
-		break;
-	case ac_image_atomic_cmpswap:
-		name = "atomic.";
-		atomic_subop = "cmpswap";
-		break;
-	case ac_image_get_lod: name = "getlod"; break;
-	case ac_image_get_resinfo: name = "getresinfo"; break;
-	default: unreachable("invalid image opcode");
-	}
-
-	const char *dimname;
-	switch (dim) {
-	case ac_image_1d: dimname = "1d"; break;
-	case ac_image_2d: dimname = "2d"; break;
-	case ac_image_3d: dimname = "3d"; break;
-	case ac_image_cube: dimname = "cube"; break;
-	case ac_image_1darray: dimname = "1darray"; break;
-	case ac_image_2darray: dimname = "2darray"; break;
-	case ac_image_2dmsaa: dimname = "2dmsaa"; break;
-	case ac_image_2darraymsaa: dimname = "2darraymsaa"; break;
-	default: unreachable("invalid dim");
-	}
-
-	bool lod_suffix =
-		a->lod && (a->opcode == ac_image_sample || a->opcode == ac_image_gather4);
-	char intr_name[96];
-	snprintf(intr_name, sizeof(intr_name),
-		 "llvm.amdgcn.image.%s%s" /* base name */
-		 "%s%s%s" /* sample/gather modifiers */
-		 ".%s.%s%s%s%s", /* dimension and type overloads */
-		 name, atomic_subop,
-		 a->compare ? ".c" : "",
-		 a->bias ? ".b" :
-		 lod_suffix ? ".l" :
-		 a->derivs[0] ? ".d" :
-		 a->level_zero ? ".lz" : "",
-		 a->offset ? ".o" : "",
-		 dimname,
-		 atomic ? "i32" : "v4f32",
-		 overload[0], overload[1], overload[2]);
-
-	LLVMTypeRef retty;
-	if (atomic)
-		retty = ctx->i32;
-	else if (a->opcode == ac_image_store || a->opcode == ac_image_store_mip)
-		retty = ctx->voidt;
-	else
-		retty = ctx->v4f32;
-
-	LLVMValueRef result =
-		ac_build_intrinsic(ctx, intr_name, retty, args, num_args,
-				   a->attributes);
-	if (!sample && retty == ctx->v4f32) {
-		result = LLVMBuildBitCast(ctx->builder, result,
-					  ctx->v4i32, "");
-	}
-	return result;
-}
-
 LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
 				    LLVMValueRef args[2])
 {
-	LLVMTypeRef v2f16 =
-		LLVMVectorType(LLVMHalfTypeInContext(ctx->context), 2);
+	if (HAVE_LLVM >= 0x0500) {
+		LLVMTypeRef v2f16 =
+			LLVMVectorType(LLVMHalfTypeInContext(ctx->context), 2);
+		LLVMValueRef res =
+			ac_build_intrinsic(ctx, "llvm.amdgcn.cvt.pkrtz",
+					   v2f16, args, 2,
+					   AC_FUNC_ATTR_READNONE);
+		return LLVMBuildBitCast(ctx->builder, res, ctx->i32, "");
+	}
 
-	return ac_build_intrinsic(ctx, "llvm.amdgcn.cvt.pkrtz", v2f16,
-				  args, 2, AC_FUNC_ATTR_READNONE);
+	return ac_build_intrinsic(ctx, "llvm.SI.packf16", ctx->i32, args, 2,
+				  AC_FUNC_ATTR_READNONE |
+				  AC_FUNC_ATTR_LEGACY);
 }
 
 /* Upper 16 bits must be zero. */
@@ -2035,11 +1869,20 @@ LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
 		width,
 	};
 
+	if (HAVE_LLVM >= 0x0500) {
+		return ac_build_intrinsic(ctx,
+					  is_signed ? "llvm.amdgcn.sbfe.i32" :
+						      "llvm.amdgcn.ubfe.i32",
+					  ctx->i32, args, 3,
+					  AC_FUNC_ATTR_READNONE);
+	}
+
 	return ac_build_intrinsic(ctx,
-				  is_signed ? "llvm.amdgcn.sbfe.i32" :
-					      "llvm.amdgcn.ubfe.i32",
+				  is_signed ? "llvm.AMDGPU.bfe.i32" :
+					      "llvm.AMDGPU.bfe.u32",
 				  ctx->i32, args, 3,
-				  AC_FUNC_ATTR_READNONE);
+				  AC_FUNC_ATTR_READNONE |
+				  AC_FUNC_ATTR_LEGACY);
 }
 
 void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned simm16)
@@ -2119,9 +1962,9 @@ LLVMValueRef ac_build_fsign(struct ac_llvm_context *ctx, LLVMValueRef src0,
 	return val;
 }
 
-#define AC_EXP_TARGET		0
-#define AC_EXP_ENABLED_CHANNELS 1
-#define AC_EXP_OUT0		2
+#define AC_EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
+#define AC_EXP_ENABLED_CHANNELS (HAVE_LLVM >= 0x0500 ? 1 : 0)
+#define AC_EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
 
 enum ac_ir_type {
 	AC_IR_UNDEF,
@@ -2775,13 +2618,11 @@ void ac_apply_fmask_to_sample(struct ac_llvm_context *ac, LLVMValueRef fmask,
 	final_sample = LLVMBuildMul(ac->builder, addr[sample_chan],
 				    LLVMConstInt(ac->i32, 4, 0), "");
 	final_sample = LLVMBuildLShr(ac->builder, fmask_value, final_sample, "");
-	/* Mask the sample index by 0x7, because 0x8 means an unknown value
-	 * with EQAA, so those will map to 0. */
 	final_sample = LLVMBuildAnd(ac->builder, final_sample,
-				    LLVMConstInt(ac->i32, 0x7, 0), "");
+				    LLVMConstInt(ac->i32, 0xF, 0), "");
 
 	/* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
-	 * resource descriptor is 0 (invalid).
+	 * resource descriptor is 0 (invalid),
 	 */
 	LLVMValueRef tmp;
 	tmp = LLVMBuildBitCast(ac->builder, fmask, ac->v8i32, "");

src/amd/common/ac_llvm_build.h

@@ -97,7 +97,7 @@ struct ac_llvm_context {
 };
 
 void
-ac_llvm_context_init(struct ac_llvm_context *ctx,
+ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 		     enum chip_class chip_class, enum radeon_family family);
 
 void
@@ -252,14 +252,6 @@ LLVMValueRef ac_build_buffer_load_format_gfx9_safe(struct ac_llvm_context *ctx,
                                                   bool glc,
                                                   bool can_speculate);
 
-LLVMValueRef
-ac_build_tbuffer_load_short(struct ac_llvm_context *ctx,
-			    LLVMValueRef rsrc,
-			    LLVMValueRef vindex,
-			    LLVMValueRef voffset,
-				LLVMValueRef soffset,
-				LLVMValueRef immoffset);
-
 LLVMValueRef
 ac_get_thread_id(struct ac_llvm_context *ctx);
 

src/amd/common/ac_llvm_helper.cpp

@@ -29,24 +29,30 @@
 #pragma push_macro("DEBUG")
 #undef DEBUG
 
-#include "ac_binary.h"
 #include "ac_llvm_util.h"
-
 #include <llvm-c/Core.h>
-#include <llvm/Target/TargetMachine.h>
+#include <llvm/Target/TargetOptions.h>
+#include <llvm/ExecutionEngine/ExecutionEngine.h>
+#include <llvm/IR/Attributes.h>
+#include <llvm/IR/CallSite.h>
 #include <llvm/IR/IRBuilder.h>
-#include <llvm/Analysis/TargetLibraryInfo.h>
-#include <llvm/Transforms/IPO.h>
 
-#include <llvm/IR/LegacyPassManager.h>
-#if HAVE_LLVM < 0x0700
-#include "llvm/Support/raw_ostream.h"
+#if HAVE_LLVM < 0x0500
+namespace llvm {
+typedef AttributeSet AttributeList;
+}
 #endif
 
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)
 {
    llvm::Argument *A = llvm::unwrap<llvm::Argument>(val);
+#if HAVE_LLVM < 0x0500
+   llvm::AttrBuilder B;
+   B.addDereferenceableAttr(bytes);
+   A->addAttr(llvm::AttributeList::get(A->getContext(), A->getArgNo() + 1,  B));
+#else
    A->addAttr(llvm::Attribute::getWithDereferenceableBytes(A->getContext(), bytes));
+#endif
 }
 
 bool ac_is_sgpr_param(LLVMValueRef arg)
@@ -67,16 +73,6 @@ bool ac_llvm_is_function(LLVMValueRef v)
 	return LLVMGetValueKind(v) == LLVMFunctionValueKind;
 }
 
-LLVMModuleRef ac_create_module(LLVMTargetMachineRef tm, LLVMContextRef ctx)
-{
-   llvm::TargetMachine *TM = reinterpret_cast<llvm::TargetMachine*>(tm);
-   LLVMModuleRef module = LLVMModuleCreateWithNameInContext("mesa-shader", ctx);
-
-   llvm::unwrap(module)->setTargetTriple(TM->getTargetTriple().getTriple());
-   llvm::unwrap(module)->setDataLayout(TM->createDataLayout());
-   return module;
-}
-
 LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 				 enum ac_float_mode float_mode)
 {
@@ -103,78 +99,3 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 
 	return builder;
 }
-
-LLVMTargetLibraryInfoRef
-ac_create_target_library_info(const char *triple)
-{
-	return reinterpret_cast<LLVMTargetLibraryInfoRef>(new llvm::TargetLibraryInfoImpl(llvm::Triple(triple)));
-}
-
-void
-ac_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info)
-{
-	delete reinterpret_cast<llvm::TargetLibraryInfoImpl *>(library_info);
-}
-
-/* The LLVM compiler is represented as a pass manager containing passes for
- * optimizations, instruction selection, and code generation.
- */
-struct ac_compiler_passes {
-	ac_compiler_passes(): ostream(code_string) {}
-
-	llvm::SmallString<0> code_string;  /* ELF shader binary */
-	llvm::raw_svector_ostream ostream; /* stream for appending data to the binary */
-	llvm::legacy::PassManager passmgr; /* list of passes */
-};
-
-struct ac_compiler_passes *ac_create_llvm_passes(LLVMTargetMachineRef tm)
-{
-	struct ac_compiler_passes *p = new ac_compiler_passes();
-	if (!p)
-		return NULL;
-
-	llvm::TargetMachine *TM = reinterpret_cast<llvm::TargetMachine*>(tm);
-
-	if (TM->addPassesToEmitFile(p->passmgr, p->ostream,
-#if HAVE_LLVM >= 0x0700
-				    nullptr,
-#endif
-				    llvm::TargetMachine::CGFT_ObjectFile)) {
-		fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n");
-		delete p;
-		return NULL;
-	}
-	return p;
-}
-
-void ac_destroy_llvm_passes(struct ac_compiler_passes *p)
-{
-	delete p;
-}
-
-/* This returns false on failure. */
-bool ac_compile_module_to_binary(struct ac_compiler_passes *p, LLVMModuleRef module,
-				 struct ac_shader_binary *binary)
-{
-	p->passmgr.run(*llvm::unwrap(module));
-
-	llvm::StringRef data = p->ostream.str();
-	bool success = ac_elf_read(data.data(), data.size(), binary);
-	p->code_string = ""; /* release the ELF shader binary */
-
-	if (!success)
-		fprintf(stderr, "amd: cannot read an ELF shader binary\n");
-	return success;
-}
-
-void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr)
-{
-	llvm::unwrap(passmgr)->add(llvm::createBarrierNoopPass());
-}
-
-void ac_enable_global_isel(LLVMTargetMachineRef tm)
-{
-#if HAVE_LLVM >= 0x0700
-  reinterpret_cast<llvm::TargetMachine*>(tm)->setGlobalISel(true);
-#endif
-}

src/amd/common/ac_llvm_util.c

@@ -28,13 +28,7 @@
 #include "util/bitscan.h"
 #include <llvm-c/Core.h>
 #include <llvm-c/Support.h>
-#include <llvm-c/Transforms/IPO.h>
-#include <llvm-c/Transforms/Scalar.h>
-#if HAVE_LLVM >= 0x0700
-#include <llvm-c/Transforms/Utils.h>
-#endif
 #include "c11/threads.h"
-#include "gallivm/lp_bld_misc.h"
 #include "util/u_math.h"
 
 #include <assert.h>
@@ -56,27 +50,20 @@ static void ac_init_llvm_target()
 	 * https://reviews.llvm.org/D26348
 	 *
 	 * "mesa" is the prefix for error messages.
-	 *
-	 * -global-isel-abort=2 is a no-op unless global isel has been enabled.
-	 * This option tells the backend to fall-back to SelectionDAG and print
-	 * a diagnostic message if global isel fails.
 	 */
-	const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", "-global-isel-abort=2" };
-	LLVMParseCommandLineOptions(3, argv, NULL);
+	const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
+	LLVMParseCommandLineOptions(2, argv, NULL);
 }
 
 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 
-void ac_init_llvm_once(void)
-{
-	call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
-}
-
-static LLVMTargetRef ac_get_llvm_target(const char *triple)
+LLVMTargetRef ac_get_llvm_target(const char *triple)
 {
 	LLVMTargetRef target = NULL;
 	char *err_message = NULL;
 
+	call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
+
 	if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
 		fprintf(stderr, "Cannot find target for triple %s ", triple);
 		if (err_message) {
@@ -128,86 +115,40 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
 	case CHIP_VEGAM:
 		return "polaris11";
 	case CHIP_VEGA10:
-		return "gfx900";
-	case CHIP_RAVEN:
-		return "gfx902";
 	case CHIP_VEGA12:
-		return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
-	case CHIP_VEGA20:
-		return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
+	case CHIP_RAVEN:
+		return "gfx900";
 	default:
 		return "";
 	}
 }
 
-static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
-						     enum ac_target_machine_options tm_options,
-						     LLVMCodeGenOptLevel level,
-						     const char **out_triple)
+LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac_target_machine_options tm_options)
 {
 	assert(family >= CHIP_TAHITI);
 	char features[256];
 	const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
 	LLVMTargetRef target = ac_get_llvm_target(triple);
-	bool barrier_does_waitcnt = family != CHIP_VEGA20;
 
 	snprintf(features, sizeof(features),
-		 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
+		 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
 		 tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
 		 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 		 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
-		 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
-		 barrier_does_waitcnt ? ",+auto-waitcnt-before-barrier" : "");
+		 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "");
 	
 	LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 	                             target,
 	                             triple,
 	                             ac_get_llvm_processor_name(family),
 				     features,
-	                             level,
+	                             LLVMCodeGenLevelDefault,
 	                             LLVMRelocDefault,
 	                             LLVMCodeModelDefault);
 
-	if (out_triple)
-		*out_triple = triple;
-	if (tm_options & AC_TM_ENABLE_GLOBAL_ISEL)
-		ac_enable_global_isel(tm);
 	return tm;
 }
 
-static LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
-					    bool check_ir)
-{
-	LLVMPassManagerRef passmgr = LLVMCreatePassManager();
-	if (!passmgr)
-		return NULL;
-
-	if (target_library_info)
-		LLVMAddTargetLibraryInfo(target_library_info,
-					 passmgr);
-
-	if (check_ir)
-		LLVMAddVerifierPass(passmgr);
-	LLVMAddAlwaysInlinerPass(passmgr);
-	/* Normally, the pass manager runs all passes on one function before
-	 * moving onto another. Adding a barrier no-op pass forces the pass
-	 * manager to run the inliner on all functions first, which makes sure
-	 * that the following passes are only run on the remaining non-inline
-	 * function, so it removes useless work done on dead inline functions.
-	 */
-	ac_llvm_add_barrier_noop_pass(passmgr);
-	/* This pass should eliminate all the load and store instructions. */
-	LLVMAddPromoteMemoryToRegisterPass(passmgr);
-	LLVMAddScalarReplAggregatesPass(passmgr);
-	LLVMAddLICMPass(passmgr);
-	LLVMAddAggressiveDCEPass(passmgr);
-	LLVMAddCFGSimplificationPass(passmgr);
-	/* This is recommended by the instruction combining pass. */
-	LLVMAddEarlyCSEMemSSAPass(passmgr);
-	LLVMAddInstructionCombiningPass(passmgr);
-	return passmgr;
-}
-
 static const char *attr_to_str(enum ac_func_attr attr)
 {
    switch (attr) {
@@ -299,60 +240,3 @@ ac_count_scratch_private_memory(LLVMValueRef function)
 
 	return private_mem_vgprs;
 }
-
-bool
-ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
-		      bool okay_to_leak_target_library_info,
-		      enum radeon_family family,
-		      enum ac_target_machine_options tm_options)
-{
-	const char *triple;
-	memset(compiler, 0, sizeof(*compiler));
-
-	compiler->tm = ac_create_target_machine(family, tm_options,
-						LLVMCodeGenLevelDefault,
-						&triple);
-	if (!compiler->tm)
-		return false;
-
-	if (tm_options & AC_TM_CREATE_LOW_OPT) {
-		compiler->low_opt_tm =
-			ac_create_target_machine(family, tm_options,
-						 LLVMCodeGenLevelLess, NULL);
-		if (!compiler->low_opt_tm)
-			goto fail;
-	}
-
-	if (okay_to_leak_target_library_info || (HAVE_LLVM >= 0x0700)) {
-		compiler->target_library_info =
-			ac_create_target_library_info(triple);
-		if (!compiler->target_library_info)
-			goto fail;
-	}
-
-	compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
-					      tm_options & AC_TM_CHECK_IR);
-	if (!compiler->passmgr)
-		goto fail;
-
-	return true;
-fail:
-	ac_destroy_llvm_compiler(compiler);
-	return false;
-}
-
-void
-ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
-{
-	if (compiler->passmgr)
-		LLVMDisposePassManager(compiler->passmgr);
-#if HAVE_LLVM >= 0x0700
-	/* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
-	if (compiler->target_library_info)
-		ac_dispose_target_library_info(compiler->target_library_info);
-#endif
-	if (compiler->low_opt_tm)
-		LLVMDisposeTargetMachine(compiler->low_opt_tm);
-	if (compiler->tm)
-		LLVMDisposeTargetMachine(compiler->tm);
-}

src/amd/common/ac_llvm_util.h

@@ -35,9 +35,6 @@
 extern "C" {
 #endif
 
-struct ac_shader_binary;
-struct ac_compiler_passes;
-
 enum ac_func_attr {
 	AC_FUNC_ATTR_ALWAYSINLINE = (1 << 0),
 	AC_FUNC_ATTR_INREG        = (1 << 2),
@@ -62,9 +59,6 @@ enum ac_target_machine_options {
 	AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
 	AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
 	AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
-	AC_TM_CHECK_IR = (1 << 5),
-	AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
-	AC_TM_CREATE_LOW_OPT = (1 << 7),
 };
 
 enum ac_float_mode {
@@ -73,23 +67,10 @@ enum ac_float_mode {
 	AC_FLOAT_MODE_UNSAFE_FP_MATH,
 };
 
-/* Per-thread persistent LLVM objects. */
-struct ac_llvm_compiler {
-	LLVMTargetLibraryInfoRef	target_library_info;
-	LLVMPassManagerRef		passmgr;
-
-	/* Default compiler. */
-	LLVMTargetMachineRef		tm;
-	struct ac_compiler_passes	*passes;
-
-	/* Optional compiler for faster compilation with fewer optimizations.
-	 * LLVM modules can be created with "tm" too. There is no difference.
-	 */
-	LLVMTargetMachineRef		low_opt_tm; /* uses -O1 instead of -O2 */
-	struct ac_compiler_passes	*low_opt_passes;
-};
-
 const char *ac_get_llvm_processor_name(enum radeon_family family);
+LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac_target_machine_options tm_options);
+
+LLVMTargetRef ac_get_llvm_target(const char *triple);
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes);
 bool ac_is_sgpr_param(LLVMValueRef param);
 void ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
@@ -100,7 +81,6 @@ void ac_dump_module(LLVMModuleRef module);
 
 LLVMValueRef ac_llvm_get_called_value(LLVMValueRef call);
 bool ac_llvm_is_function(LLVMValueRef v);
-LLVMModuleRef ac_create_module(LLVMTargetMachineRef tm, LLVMContextRef ctx);
 
 LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
 				 enum ac_float_mode float_mode);
@@ -128,24 +108,6 @@ ac_get_store_intr_attribs(bool writeonly_memory)
 unsigned
 ac_count_scratch_private_memory(LLVMValueRef function);
 
-LLVMTargetLibraryInfoRef ac_create_target_library_info(const char *triple);
-void ac_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info);
-void ac_init_llvm_once(void);
-
-
-bool ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
-			   bool okay_to_leak_target_library_info,
-			   enum radeon_family family,
-			   enum ac_target_machine_options tm_options);
-void ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler);
-
-struct ac_compiler_passes *ac_create_llvm_passes(LLVMTargetMachineRef tm);
-void ac_destroy_llvm_passes(struct ac_compiler_passes *p);
-bool ac_compile_module_to_binary(struct ac_compiler_passes *p, LLVMModuleRef module,
-				 struct ac_shader_binary *binary);
-void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr);
-void ac_enable_global_isel(LLVMTargetMachineRef tm);
-
 #ifdef __cplusplus
 }
 #endif

src/amd/common/ac_surface.c

@@ -143,10 +143,6 @@ static void addrlib_family_rev_id(enum radeon_family family,
 		*addrlib_family = FAMILY_AI;
 		*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
 		break;
-	case CHIP_VEGA20:
-		*addrlib_family = FAMILY_AI;
-		*addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
-		break;
 	case CHIP_RAVEN:
 		*addrlib_family = FAMILY_RV;
 		*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
@@ -231,16 +227,8 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 	return addrCreateOutput.hLib;
 }
 
-static int surf_config_sanity(const struct ac_surf_config *config,
-			      unsigned flags)
+static int surf_config_sanity(const struct ac_surf_config *config)
 {
-	/* FMASK is allocated together with the color surface and can't be
-	 * allocated separately.
-	 */
-	assert(!(flags & RADEON_SURF_FMASK));
-	if (flags & RADEON_SURF_FMASK)
-		return -EINVAL;
-
 	/* all dimension must be at least 1 ! */
 	if (!config->info.width || !config->info.height || !config->info.depth ||
 	    !config->info.array_size || !config->info.levels)
@@ -253,27 +241,10 @@ static int surf_config_sanity(const struct ac_surf_config *config,
 	case 4:
 	case 8:
 		break;
-	case 16:
-		if (flags & RADEON_SURF_Z_OR_SBUFFER)
-			return -EINVAL;
-		break;
 	default:
 		return -EINVAL;
 	}
 
-	if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
-		switch (config->info.storage_samples) {
-		case 0:
-		case 1:
-		case 2:
-		case 4:
-		case 8:
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-
 	if (config->is_3d && config->info.array_size > 1)
 		return -EINVAL;
 	if (config->is_cube && config->info.depth > 1)
@@ -305,10 +276,10 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 	 */
 	if (config->info.levels == 1 &&
 	    AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
-	    AddrSurfInfoIn->bpp &&
-	    util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
+	    AddrSurfInfoIn->bpp) {
 		unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 
+		assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
 		AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 	}
 
@@ -372,9 +343,6 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 	/* The previous level's flag tells us if we can use DCC for this level. */
 	if (AddrSurfInfoIn->flags.dccCompatible &&
 	    (level == 0 || AddrDccOut->subLvlCompressible)) {
-		bool prev_level_clearable = level == 0 ||
-					    AddrDccOut->dccRamSizeAligned;
-
 		AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 		AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 		AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
@@ -387,26 +355,10 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 
 		if (ret == ADDR_OK) {
 			surf_level->dcc_offset = surf->dcc_size;
+			surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 			surf->num_dcc_levels = level + 1;
 			surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 			surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
-
-			/* If the DCC size of a subresource (1 mip level or 1 slice)
-			 * is not aligned, the DCC memory layout is not contiguous for
-			 * that subresource, which means we can't use fast clear.
-			 *
-			 * We only do fast clears for whole mipmap levels. If we did
-			 * per-slice fast clears, the same restriction would apply.
-			 * (i.e. only compute the slice size and see if it's aligned)
-			 *
-			 * The last level can be non-contiguous and still be clearable
-			 * if it's interleaved with the next level that doesn't exist.
-			 */
-			if (AddrDccOut->dccRamSizeAligned ||
-			    (prev_level_clearable && level == config->info.levels - 1))
-				surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
-			else
-				surf_level->dcc_fast_clear_size = 0;
 		}
 	}
 
@@ -440,7 +392,6 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
 }
 
 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
-#define     V_009910_ADDR_SURF_THICK_MICRO_TILING                   0x03
 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 
 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
@@ -475,6 +426,7 @@ static bool get_display_flag(const struct ac_surf_config *config,
 	unsigned bpe = surf->bpe;
 
 	if (surf->flags & RADEON_SURF_SCANOUT &&
+	    !(surf->flags & RADEON_SURF_FMASK) &&
 	    config->info.samples <= 1 &&
 	    surf->blk_w <= 2 && surf->blk_h == 1) {
 		/* subsampled */
@@ -551,66 +503,6 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 	return 0;
 }
 
-void ac_compute_cmask(const struct radeon_info *info,
-		      const struct ac_surf_config *config,
-		      struct radeon_surf *surf)
-{
-	unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
-	unsigned num_pipes = info->num_tile_pipes;
-	unsigned cl_width, cl_height;
-
-	if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
-		return;
-
-	assert(info->chip_class <= VI);
-
-	switch (num_pipes) {
-	case 2:
-		cl_width = 32;
-		cl_height = 16;
-		break;
-	case 4:
-		cl_width = 32;
-		cl_height = 32;
-		break;
-	case 8:
-		cl_width = 64;
-		cl_height = 32;
-		break;
-	case 16: /* Hawaii */
-		cl_width = 64;
-		cl_height = 64;
-		break;
-	default:
-		assert(0);
-		return;
-	}
-
-	unsigned base_align = num_pipes * pipe_interleave_bytes;
-
-	unsigned width = align(config->info.width, cl_width*8);
-	unsigned height = align(config->info.height, cl_height*8);
-	unsigned slice_elements = (width * height) / (8*8);
-
-	/* Each element of CMASK is a nibble. */
-	unsigned slice_bytes = slice_elements / 2;
-
-	surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
-	if (surf->u.legacy.cmask_slice_tile_max)
-		surf->u.legacy.cmask_slice_tile_max -= 1;
-
-	unsigned num_layers;
-	if (config->is_3d)
-		num_layers = config->info.depth;
-	else if (config->is_cube)
-		num_layers = 6;
-	else
-		num_layers = config->info.array_size;
-
-	surf->cmask_alignment = MAX2(256, base_align);
-	surf->cmask_size = align(slice_bytes, base_align) * num_layers;
-}
-
 /**
  * Fill in the tiling information in \p surf based on the given surface config.
  *
@@ -645,8 +537,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 
 	compressed = surf->blk_w == 4 && surf->blk_h == 4;
 
-	/* MSAA requires 2D tiling. */
-	if (config->info.samples > 1)
+	/* MSAA and FMASK require 2D tiling. */
+	if (config->info.samples > 1 ||
+	    (surf->flags & RADEON_SURF_FMASK))
 		mode = RADEON_SURF_MODE_2D;
 
 	/* DB doesn't support linear layouts. */
@@ -689,18 +582,13 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	}
 
 	AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
-		MAX2(1, config->info.samples);
+		config->info.samples ? config->info.samples : 1;
 	AddrSurfInfoIn.tileIndex = -1;
 
-	if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
-		AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
-			MAX2(1, config->info.storage_samples);
-	}
-
 	/* Set the micro tile type. */
 	if (surf->flags & RADEON_SURF_SCANOUT)
 		AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
-	else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+	else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 		AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 	else
 		AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
@@ -708,6 +596,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 	AddrSurfInfoIn.flags.cube = config->is_cube;
+	AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
 	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 	AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
@@ -772,6 +661,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 	    surf->u.legacy.bankw && surf->u.legacy.bankh &&
 	    surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
+		assert(!(surf->flags & RADEON_SURF_FMASK));
+
 		/* If any of these parameters are incorrect, the calculation
 		 * will fail. */
 		AddrTileInfoIn.banks = surf->u.legacy.num_banks;
@@ -918,67 +809,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 		}
 	}
 
-	/* Compute FMASK. */
-	if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
-		ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
-		ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
-		ADDR_TILEINFO fmask_tile_info = {};
-
-		fin.size = sizeof(fin);
-		fout.size = sizeof(fout);
-
-		fin.tileMode = AddrSurfInfoOut.tileMode;
-		fin.pitch = AddrSurfInfoOut.pitch;
-		fin.height = config->info.height;
-		fin.numSlices = AddrSurfInfoIn.numSlices;
-		fin.numSamples = AddrSurfInfoIn.numSamples;
-		fin.numFrags = AddrSurfInfoIn.numFrags;
-		fin.tileIndex = -1;
-		fout.pTileInfo = &fmask_tile_info;
-
-		r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
-		if (r)
-			return r;
-
-		surf->fmask_size = fout.fmaskBytes;
-		surf->fmask_alignment = fout.baseAlign;
-		surf->fmask_tile_swizzle = 0;
-
-		surf->u.legacy.fmask.slice_tile_max =
-			(fout.pitch * fout.height) / 64;
-		if (surf->u.legacy.fmask.slice_tile_max)
-		    surf->u.legacy.fmask.slice_tile_max -= 1;
-
-		surf->u.legacy.fmask.tiling_index = fout.tileIndex;
-		surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
-		surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
-
-		/* Compute tile swizzle for FMASK. */
-		if (config->info.fmask_surf_index &&
-		    !(surf->flags & RADEON_SURF_SHAREABLE)) {
-			ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
-			ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
-
-			xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
-			xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
-
-			/* This counter starts from 1 instead of 0. */
-			xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
-			xin.tileIndex = fout.tileIndex;
-			xin.macroModeIndex = fout.macroModeIndex;
-			xin.pTileInfo = fout.pTileInfo;
-			xin.tileMode = fin.tileMode;
-
-			int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
-			if (r != ADDR_OK)
-				return r;
-
-			assert(xout.tileSwizzle <=
-			       u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
-			surf->fmask_tile_swizzle = xout.tileSwizzle;
-		}
-	}
-
 	/* Recalculate the whole DCC miptree size including disabled levels.
 	 * This is what addrlib does, but calling addrlib would be a lot more
 	 * complicated.
@@ -999,34 +829,13 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	/* Make sure HTILE covers the whole miptree, because the shader reads
 	 * TC-compatible HTILE even for levels where it's disabled by DB.
 	 */
-	if (surf->htile_size && config->info.levels > 1 &&
-	    surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
-		/* MSAA can't occur with levels > 1, so ignore the sample count. */
-		const unsigned total_pixels = surf->surf_size / surf->bpe;
-		const unsigned htile_block_size = 8 * 8;
-		const unsigned htile_element_size = 4;
-
-		surf->htile_size = (total_pixels / htile_block_size) *
-				   htile_element_size;
-		surf->htile_size = align(surf->htile_size, surf->htile_alignment);
-	}
+	if (surf->htile_size && config->info.levels > 1)
+		surf->htile_size *= 2;
 
 	surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 	surf->is_displayable = surf->is_linear ||
 			       surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
 			       surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
-
-	/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
-	 * used at the same time. This case is not currently expected to occur
-	 * because we don't use rotated. Enforce this restriction on all chips
-	 * to facilitate testing.
-	 */
-	if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
-		assert(!"rotate micro tile mode is unsupported");
-		return ADDR_ERROR;
-	}
-
-	ac_compute_cmask(info, config, surf);
 	return 0;
 }
 
@@ -1286,8 +1095,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 
 			surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 			surf->u.gfx9.fmask.epitch = fout.pitch - 1;
-			surf->fmask_size = fout.fmaskBytes;
-			surf->fmask_alignment = fout.baseAlign;
+			surf->u.gfx9.fmask_size = fout.fmaskBytes;
+			surf->u.gfx9.fmask_alignment = fout.baseAlign;
 
 			/* Compute tile swizzle for the FMASK surface. */
 			if (config->info.fmask_surf_index &&
@@ -1313,8 +1122,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 					return ret;
 
 				assert(xout.pipeBankXor <=
-				       u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
-				surf->fmask_tile_swizzle = xout.pipeBankXor;
+				       u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
+				surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
 			}
 		}
 
@@ -1326,7 +1135,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 			cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 
-			if (in->numSamples > 1) {
+			if (in->numSamples) {
 				/* FMASK is always aligned. */
 				cin.cMaskFlags.pipeAligned = 1;
 				cin.cMaskFlags.rbAligned = 1;
@@ -1351,8 +1160,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 
 			surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
 			surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
-			surf->cmask_size = cout.cmaskBytes;
-			surf->cmask_alignment = cout.baseAlign;
+			surf->u.gfx9.cmask_size = cout.cmaskBytes;
+			surf->u.gfx9.cmask_alignment = cout.baseAlign;
 		}
 	}
 
@@ -1369,6 +1178,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 	int r;
 
+	assert(!(surf->flags & RADEON_SURF_FMASK));
+
 	AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
 
 	compressed = surf->blk_w == 4 && surf->blk_h == 4;
@@ -1406,10 +1217,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 			assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 			AddrSurfInfoIn.format = ADDR_FMT_32_32;
 			break;
-		case 12:
-			assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
-			AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
-			break;
 		case 16:
 			assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 			AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
@@ -1429,12 +1236,9 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.opt4space = 1;
 
 	AddrSurfInfoIn.numMipLevels = config->info.levels;
-	AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
+	AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
 	AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
 
-	if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
-		AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
-
 	/* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
 	 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
 	 * must sample 1D textures as 2D. */
@@ -1487,13 +1291,13 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	surf->num_dcc_levels = 0;
 	surf->surf_size = 0;
-	surf->fmask_size = 0;
 	surf->dcc_size = 0;
 	surf->htile_size = 0;
 	surf->htile_slice_size = 0;
 	surf->u.gfx9.surf_offset = 0;
 	surf->u.gfx9.stencil_offset = 0;
-	surf->cmask_size = 0;
+	surf->u.gfx9.fmask_size = 0;
+	surf->u.gfx9.cmask_size = 0;
 
 	/* Calculate texture layout information. */
 	r = gfx9_compute_miptree(addrlib, config, surf, compressed,
@@ -1567,13 +1371,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 		case ADDR_SW_4KB_R_X:
 		case ADDR_SW_64KB_R_X:
 		case ADDR_SW_VAR_R_X:
-			/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
-			 * used at the same time. This case is not currently expected to occur
-			 * because we don't use rotated. Enforce this restriction on all chips
-			 * to facilitate testing.
-			 */
-			assert(!"rotate micro tile mode is unsupported");
-			return ADDR_ERROR;
+			surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
+			break;
 
 		/* Z = depth. */
 		case ADDR_SW_4KB_Z:
@@ -1592,7 +1391,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	/* Temporary workaround to prevent VM faults and hangs. */
 	if (info->family == CHIP_VEGA12)
-		surf->fmask_size *= 8;
+		surf->u.gfx9.fmask_size *= 8;
 
 	return 0;
 }
@@ -1604,7 +1403,7 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 {
 	int r;
 
-	r = surf_config_sanity(config, surf->flags);
+	r = surf_config_sanity(config);
 	if (r)
 		return r;
 

src/amd/common/ac_surface.h

@@ -79,13 +79,6 @@ struct legacy_surf_level {
     enum radeon_surf_mode       mode:2;
 };
 
-struct legacy_surf_fmask {
-    unsigned slice_tile_max; /* max 4M */
-    uint8_t tiling_index;    /* max 31 */
-    uint8_t bankh;           /* max 8 */
-    uint16_t pitch_in_pixels;
-};
-
 struct legacy_surf_layout {
     unsigned                    bankw:4;  /* max 8 */
     unsigned                    bankh:4;  /* max 8 */
@@ -108,8 +101,6 @@ struct legacy_surf_layout {
     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
-    struct legacy_surf_fmask    fmask;
-    unsigned                    cmask_slice_tile_max;
 };
 
 /* Same as addrlib - AddrResourceType. */
@@ -151,6 +142,13 @@ struct gfx9_surf_layout {
     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 
     uint64_t                    stencil_offset; /* separate stencil */
+    uint64_t                    fmask_size;
+    uint64_t                    cmask_size;
+
+    uint32_t                    fmask_alignment;
+    uint32_t                    cmask_alignment;
+
+    uint8_t                     fmask_tile_swizzle;
 };
 
 struct radeon_surf {
@@ -190,23 +188,17 @@ struct radeon_surf {
      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
      */
     uint8_t                     tile_swizzle;
-    uint8_t                     fmask_tile_swizzle;
 
     uint64_t                    surf_size;
-    uint64_t                    fmask_size;
-    uint32_t                    surf_alignment;
-    uint32_t                    fmask_alignment;
-
     /* DCC and HTILE are very small. */
     uint32_t                    dcc_size;
-    uint32_t                    dcc_alignment;
-
     uint32_t                    htile_size;
-    uint32_t                    htile_slice_size;
-    uint32_t                    htile_alignment;
 
-    uint32_t                    cmask_size;
-    uint32_t                    cmask_alignment;
+    uint32_t                    htile_slice_size;
+
+    uint32_t                    surf_alignment;
+    uint32_t                    dcc_alignment;
+    uint32_t                    htile_alignment;
 
     union {
         /* R600-VI return values.
@@ -225,13 +217,12 @@ struct ac_surf_info {
 	uint32_t width;
 	uint32_t height;
 	uint32_t depth;
-	uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
-	uint8_t storage_samples; /* For color: allocated samples */
+	uint8_t samples;
 	uint8_t levels;
 	uint8_t num_channels; /* heuristic for displayability */
 	uint16_t array_size;
 	uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
-	uint32_t *fmask_surf_index;
+	uint32_t *fmask_surf_index; /* GFX9+ */
 };
 
 struct ac_surf_config {
@@ -249,10 +240,6 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 		       enum radeon_surf_mode mode,
 		       struct radeon_surf *surf);
 
-void ac_compute_cmask(const struct radeon_info *info,
-		      const struct ac_surf_config *config,
-		      struct radeon_surf *surf);
-
 #ifdef __cplusplus
 }
 #endif

src/amd/common/amd_family.h

@@ -95,7 +95,6 @@ enum radeon_family {
     CHIP_VEGAM,
     CHIP_VEGA10,
     CHIP_VEGA12,
-    CHIP_VEGA20,
     CHIP_RAVEN,
     CHIP_LAST,
 };

src/amd/common/gfx9d.h

@@ -1123,6 +1123,7 @@
 #define   S_030960_HW_USE_ONLY(x)                                     (((unsigned)(x) & 0x1) << 23)
 #define   G_030960_HW_USE_ONLY(x)                                     (((x) >> 23) & 0x1)
 #define   C_030960_HW_USE_ONLY                                        0xFF7FFFFF
+#define R_030964_VGT_OBJECT_ID                                          0x030964
 #define R_030968_VGT_INSTANCE_BASE_ID                                   0x030968
 #define R_030A00_PA_SU_LINE_STIPPLE_VALUE                               0x030A00
 #define   S_030A00_LINE_STIPPLE_VALUE(x)                              (((unsigned)(x) & 0xFFFFFF) << 0)
@@ -1194,6 +1195,19 @@
 #define   S_030E04_ADDRESS(x)                                         (((unsigned)(x) & 0xFF) << 0)
 #define   G_030E04_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
 #define   C_030E04_ADDRESS                                            0xFFFFFF00
+#define R_030E08_TA_GRAD_ADJ_UCONFIG                                    0x030E08
+#define   S_030E08_GRAD_ADJ_0(x)                                      (((unsigned)(x) & 0xFF) << 0)
+#define   G_030E08_GRAD_ADJ_0(x)                                      (((x) >> 0) & 0xFF)
+#define   C_030E08_GRAD_ADJ_0                                         0xFFFFFF00
+#define   S_030E08_GRAD_ADJ_1(x)                                      (((unsigned)(x) & 0xFF) << 8)
+#define   G_030E08_GRAD_ADJ_1(x)                                      (((x) >> 8) & 0xFF)
+#define   C_030E08_GRAD_ADJ_1                                         0xFFFF00FF
+#define   S_030E08_GRAD_ADJ_2(x)                                      (((unsigned)(x) & 0xFF) << 16)
+#define   G_030E08_GRAD_ADJ_2(x)                                      (((x) >> 16) & 0xFF)
+#define   C_030E08_GRAD_ADJ_2                                         0xFF00FFFF
+#define   S_030E08_GRAD_ADJ_3(x)                                      (((unsigned)(x) & 0xFF) << 24)
+#define   G_030E08_GRAD_ADJ_3(x)                                      (((x) >> 24) & 0xFF)
+#define   C_030E08_GRAD_ADJ_3                                         0x00FFFFFF
 #define R_030F00_DB_OCCLUSION_COUNT0_LOW                                0x030F00
 #define R_008F00_SQ_BUF_RSRC_WORD0                                      0x008F00
 #define R_030F04_DB_OCCLUSION_COUNT0_HI                                 0x030F04
@@ -4070,6 +4084,10 @@
 #define   S_028060_DISALLOW_OVERFLOW(x)                               (((unsigned)(x) & 0x1) << 3)
 #define   G_028060_DISALLOW_OVERFLOW(x)                               (((x) >> 3) & 0x1)
 #define   C_028060_DISALLOW_OVERFLOW                                  0xFFFFFFF7
+#define R_028064_DB_RENDER_FILTER                                       0x028064
+#define   S_028064_PS_INVOKE_MASK(x)                                  (((unsigned)(x) & 0xFFFF) << 0)
+#define   G_028064_PS_INVOKE_MASK(x)                                  (((x) >> 0) & 0xFFFF)
+#define   C_028064_PS_INVOKE_MASK                                     0xFFFF0000
 #define R_028068_DB_Z_INFO2                                             0x028068
 #define   S_028068_EPITCH(x)                                          (((unsigned)(x) & 0xFFFF) << 0)
 #define   G_028068_EPITCH(x)                                          (((x) >> 0) & 0xFFFF)
@@ -4399,6 +4417,9 @@
 #define   S_02835C_NUM_RB_PER_SE(x)                                   (((unsigned)(x) & 0x03) << 5)
 #define   G_02835C_NUM_RB_PER_SE(x)                                   (((x) >> 5) & 0x03)
 #define   C_02835C_NUM_RB_PER_SE                                      0xFFFFFF9F
+#define   S_02835C_DISABLE_SRBSL_DB_OPTIMIZED_PACKING(x)              (((unsigned)(x) & 0x1) << 8)
+#define   G_02835C_DISABLE_SRBSL_DB_OPTIMIZED_PACKING(x)              (((x) >> 8) & 0x1)
+#define   C_02835C_DISABLE_SRBSL_DB_OPTIMIZED_PACKING                 0xFFFFFEFF
 #define R_028360_CP_PERFMON_CNTX_CNTL                                   0x028360
 #define   S_028360_PERFMON_ENABLE(x)                                  (((unsigned)(x) & 0x1) << 31)
 #define   G_028360_PERFMON_ENABLE(x)                                  (((x) >> 31) & 0x1)
@@ -4442,6 +4463,26 @@
 #define   S_0283A8_BOT_QTR(x)                                         (((unsigned)(x) & 0xFF) << 24)
 #define   G_0283A8_BOT_QTR(x)                                         (((x) >> 24) & 0xFF)
 #define   C_0283A8_BOT_QTR                                            0x00FFFFFF
+#define R_0283AC_PA_SC_FOV_WINDOW_LR                                    0x0283AC
+#define   S_0283AC_LEFT_EYE_FOV_LEFT(x)                               (((unsigned)(x) & 0xFF) << 0)
+#define   G_0283AC_LEFT_EYE_FOV_LEFT(x)                               (((x) >> 0) & 0xFF)
+#define   C_0283AC_LEFT_EYE_FOV_LEFT                                  0xFFFFFF00
+#define   S_0283AC_LEFT_EYE_FOV_RIGHT(x)                              (((unsigned)(x) & 0xFF) << 8)
+#define   G_0283AC_LEFT_EYE_FOV_RIGHT(x)                              (((x) >> 8) & 0xFF)
+#define   C_0283AC_LEFT_EYE_FOV_RIGHT                                 0xFFFF00FF
+#define   S_0283AC_RIGHT_EYE_FOV_LEFT(x)                              (((unsigned)(x) & 0xFF) << 16)
+#define   G_0283AC_RIGHT_EYE_FOV_LEFT(x)                              (((x) >> 16) & 0xFF)
+#define   C_0283AC_RIGHT_EYE_FOV_LEFT                                 0xFF00FFFF
+#define   S_0283AC_RIGHT_EYE_FOV_RIGHT(x)                             (((unsigned)(x) & 0xFF) << 24)
+#define   G_0283AC_RIGHT_EYE_FOV_RIGHT(x)                             (((x) >> 24) & 0xFF)
+#define   C_0283AC_RIGHT_EYE_FOV_RIGHT                                0x00FFFFFF
+#define R_0283B0_PA_SC_FOV_WINDOW_TB                                    0x0283B0
+#define   S_0283B0_FOV_TOP(x)                                         (((unsigned)(x) & 0xFF) << 0)
+#define   G_0283B0_FOV_TOP(x)                                         (((x) >> 0) & 0xFF)
+#define   C_0283B0_FOV_TOP                                            0xFFFFFF00
+#define   S_0283B0_FOV_BOT(x)                                         (((unsigned)(x) & 0xFF) << 8)
+#define   G_0283B0_FOV_BOT(x)                                         (((x) >> 8) & 0xFF)
+#define   C_0283B0_FOV_BOT                                            0xFFFF00FF
 #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX                           0x02840C
 #define R_028414_CB_BLEND_RED                                           0x028414
 #define R_028418_CB_BLEND_GREEN                                         0x028418
@@ -5731,6 +5772,9 @@
 #define   S_028830_RECTANGLE_FILTER_DISABLE(x)                        (((unsigned)(x) & 0x1) << 4)
 #define   G_028830_RECTANGLE_FILTER_DISABLE(x)                        (((x) >> 4) & 0x1)
 #define   C_028830_RECTANGLE_FILTER_DISABLE                           0xFFFFFFEF
+#define   S_028830_SRBSL_ENABLE(x)                                    (((unsigned)(x) & 0x1) << 5)
+#define   G_028830_SRBSL_ENABLE(x)                                    (((x) >> 5) & 0x1)
+#define   C_028830_SRBSL_ENABLE                                       0xFFFFFFDF
 #define R_028834_PA_CL_OBJPRIM_ID_CNTL                                  0x028834
 #define   S_028834_OBJ_ID_SEL(x)                                      (((unsigned)(x) & 0x1) << 0)
 #define   G_028834_OBJ_ID_SEL(x)                                      (((x) >> 0) & 0x1)
@@ -5764,7 +5808,6 @@
 #define   S_02883C_USE_PROVOKING_ZW(x)                                (((unsigned)(x) & 0x1) << 4)
 #define   G_02883C_USE_PROVOKING_ZW(x)                                (((x) >> 4) & 0x1)
 #define   C_02883C_USE_PROVOKING_ZW                                   0xFFFFFFEF
-#define R_028840_PA_STEREO_CNTL                                         0x028840
 #define R_028A00_PA_SU_POINT_SIZE                                       0x028A00
 #define   S_028A00_HEIGHT(x)                                          (((unsigned)(x) & 0xFFFF) << 0)
 #define   G_028A00_HEIGHT(x)                                          (((x) >> 0) & 0xFFFF)
@@ -6230,6 +6273,10 @@
 #define   S_028A98_OBJECT_ID_INST_EN(x)                               (((unsigned)(x) & 0x1) << 3)
 #define   G_028A98_OBJECT_ID_INST_EN(x)                               (((x) >> 3) & 0x1)
 #define   C_028A98_OBJECT_ID_INST_EN                                  0xFFFFFFF7
+#define R_028A9C_VGT_INDEX_PAYLOAD_CNTL                                 0x028A9C
+#define   S_028A9C_COMPOUND_INDEX_EN(x)                               (((unsigned)(x) & 0x1) << 0)
+#define   G_028A9C_COMPOUND_INDEX_EN(x)                               (((x) >> 0) & 0x1)
+#define   C_028A9C_COMPOUND_INDEX_EN                                  0xFFFFFFFE
 #define R_028AA0_VGT_INSTANCE_STEP_RATE_0                               0x028AA0
 #define R_028AA4_VGT_INSTANCE_STEP_RATE_1                               0x028AA4
 #define R_028AAC_VGT_ESGS_RING_ITEMSIZE                                 0x028AAC

src/amd/common/sid.h

@@ -239,7 +239,7 @@
 #define     S_411_ENGINE(x)		(((unsigned)(x) & 0x1) << 27)
 #define       V_411_ME			0
 #define       V_411_PFP			1
-#define     S_411_DST_SEL(x)		(((unsigned)(x) & 0x3) << 20)
+#define     S_411_DSL_SEL(x)		(((unsigned)(x) & 0x3) << 20)
 #define       V_411_DST_ADDR		0
 #define       V_411_GDS			1 /* program DAS to 1 as well */
 #define       V_411_NOWHERE		2 /* new for GFX9 */
@@ -294,7 +294,7 @@
 #define       V_500_GDS			1 /* program SAS to 1 as well */
 #define       V_500_DATA		2
 #define       V_500_SRC_ADDR_TC_L2	3 /* new for CIK */
-#define     S_500_DST_SEL(x)		(((unsigned)(x) & 0x3) << 20)
+#define     S_500_DSL_SEL(x)		(((unsigned)(x) & 0x3) << 20)
 #define       V_500_DST_ADDR		0
 #define       V_500_GDS			1 /* program DAS to 1 as well */
 #define       V_500_NOWHERE		2 /* new for GFX9 */

src/amd/common/sid_tables.py

@@ -1,4 +1,3 @@
-from __future__ import print_function
 
 CopyRight = '''
 /*
@@ -65,8 +64,8 @@ class StringTable:
         """
         fragments = [
             '"%s\\0" /* %s */' % (
-                te[0].encode('unicode_escape').decode(),
-                ', '.join(str(idx) for idx in sorted(te[2]))
+                te[0].encode('string_escape'),
+                ', '.join(str(idx) for idx in te[2])
             )
             for te in self.table
         ]
@@ -334,10 +333,10 @@ def write_tables(asics, packets):
     strings_offsets = IntTable("int")
     fields = FieldTable()
 
-    print('/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */')
-    print()
-    print(CopyRight.strip())
-    print('''
+    print '/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */'
+    print
+    print CopyRight.strip()
+    print '''
 #ifndef SID_TABLES_H
 #define SID_TABLES_H
 
@@ -359,17 +358,17 @@ struct si_packet3 {
         unsigned name_offset;
         unsigned op;
 };
-''')
+'''
 
-    print('static const struct si_packet3 packet3_table[] = {')
+    print 'static const struct si_packet3 packet3_table[] = {'
     for pkt in packets:
-        print('\t{%s, %s},' % (strings.add(pkt[5:]), pkt))
-    print('};')
-    print()
+        print '\t{%s, %s},' % (strings.add(pkt[5:]), pkt)
+    print '};'
+    print
 
     regs = {}
     for asic in asics:
-        print('static const struct si_reg %s_reg_table[] = {' % (asic.name))
+        print 'static const struct si_reg %s_reg_table[] = {' % (asic.name)
         for reg in asic.registers:
             # Only output a register that was changed or added relative to
             # the previous generation
@@ -378,27 +377,27 @@ struct si_packet3 {
                 continue
 
             if len(reg.fields):
-                print('\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
-                    len(reg.fields), fields.add(reg.fields)))
+                print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
+                    len(reg.fields), fields.add(reg.fields))
             else:
-                print('\t{%s, %s},' % (strings.add(reg.name), reg.r_name))
+                print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name)
 
             regs[reg.r_name] = reg
-        print('};')
-        print()
+        print '};'
+        print
 
     fields.emit(sys.stdout, strings, strings_offsets)
 
-    print()
+    print
 
     strings.emit(sys.stdout, "sid_strings")
 
-    print()
+    print
 
     strings_offsets.emit(sys.stdout, "sid_strings_offsets")
 
-    print()
-    print('#endif')
+    print
+    print '#endif'
 
 
 def main():

src/amd/vulkan/.gitignore

@@ -2,7 +2,6 @@
 /radv_entrypoints.c
 /radv_entrypoints.h
 /radv_extensions.c
-/radv_extensions.h
 /radv_timestamp.h
 /dev_icd.json
 /vk_format_table.c

src/amd/vulkan/Android.mk

@@ -1,166 +0,0 @@
-# Copyright © 2018 Advanced Micro Devices, Inc.
-# Copyright © 2018 Mauro Rossi issor.oruam@gmail.com
-
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-# IN THE SOFTWARE.
-
-LOCAL_PATH := $(call my-dir)
-
-# get VULKAN_FILES and VULKAN_GENERATED_FILES
-include $(LOCAL_PATH)/Makefile.sources
-
-# The gallium includes are for the util/u_math.h include from main/macros.h
-
-RADV_COMMON_INCLUDES := \
-	$(MESA_TOP)/include \
-	$(MESA_TOP)/src/ \
-	$(MESA_TOP)/src/vulkan/wsi \
-	$(MESA_TOP)/src/vulkan/util \
-	$(MESA_TOP)/src/amd \
-	$(MESA_TOP)/src/amd/common \
-	$(MESA_TOP)/src/compiler \
-	$(MESA_TOP)/src/mapi \
-	$(MESA_TOP)/src/mesa \
-	$(MESA_TOP)/src/mesa/drivers/dri/common \
-	$(MESA_TOP)/src/gallium/auxiliary \
-	$(MESA_TOP)/src/gallium/include \
-	frameworks/native/vulkan/include
-
-RADV_SHARED_LIBRARIES := libdrm_amdgpu
-
-ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),)
-RADV_SHARED_LIBRARIES += libnativewindow
-endif
-
-#
-# libmesa_radv_common
-#
-
-include $(CLEAR_VARS)
-LOCAL_MODULE := libmesa_radv_common
-LOCAL_MODULE_CLASS := STATIC_LIBRARIES
-
-intermediates := $(call local-generated-sources-dir)
-
-LOCAL_SRC_FILES := \
-	$(VULKAN_FILES)
-
-LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare LLVMInitializeAMDGPU* functions
-
-$(call mesa-build-with-llvm)
-
-LOCAL_C_INCLUDES := \
-	$(RADV_COMMON_INCLUDES) \
-	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_amd_common,,) \
-	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_nir,,)/nir \
-	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_radv_common,,) \
-	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_util,,)/util
-
-LOCAL_WHOLE_STATIC_LIBRARIES := \
-	libmesa_vulkan_util
-
-LOCAL_GENERATED_SOURCES += $(intermediates)/radv_entrypoints.c
-LOCAL_GENERATED_SOURCES += $(intermediates)/radv_entrypoints.h
-LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.c
-LOCAL_GENERATED_SOURCES += $(intermediates)/radv_extensions.h
-LOCAL_GENERATED_SOURCES += $(intermediates)/vk_format_table.c
-
-RADV_ENTRYPOINTS_SCRIPT := $(MESA_TOP)/src/amd/vulkan/radv_entrypoints_gen.py
-RADV_EXTENSIONS_SCRIPT := $(MESA_TOP)/src/amd/vulkan/radv_extensions.py
-VK_FORMAT_TABLE_SCRIPT := $(MESA_TOP)/src/amd/vulkan/vk_format_table.py
-VK_FORMAT_PARSE_SCRIPT := $(MESA_TOP)/src/amd/vulkan/vk_format_parse.py
-
-vulkan_api_xml = $(MESA_TOP)/src/vulkan/registry/vk.xml
-vk_format_layout_csv = $(MESA_TOP)/src/amd/vulkan/vk_format_layout.csv
-
-$(intermediates)/radv_entrypoints.c: $(RADV_ENTRYPOINTS_SCRIPT) \
-					$(RADV_EXTENSIONS_SCRIPT) \
-					$(vulkan_api_xml)
-	@mkdir -p $(dir $@)
-	$(MESA_PYTHON2) $(RADV_ENTRYPOINTS_SCRIPT) \
-		--xml $(vulkan_api_xml) \
-		--outdir $(dir $@)
-
-$(intermediates)/radv_entrypoints.h: $(intermediates)/radv_entrypoints.c
-
-$(intermediates)/radv_extensions.c: $(RADV_EXTENSIONS_SCRIPT) $(vulkan_api_xml)
-	@mkdir -p $(dir $@)
-	$(MESA_PYTHON2) $(RADV_EXTENSIONS_SCRIPT) \
-		--xml $(vulkan_api_xml) \
-		--out-c $@ \
-		--out-h $(addsuffix .h,$(basename $@))
-
-$(intermediates)/radv_extensions.h: $(intermediates)/radv_extensions.c
-
-$(intermediates)/vk_format_table.c: $(VK_FORMAT_TABLE_SCRIPT) \
-					$(VK_FORMAT_PARSE_SCRIPT) \
-					$(vk_format_layout_csv)
-	@mkdir -p $(dir $@)
-	$(MESA_PYTHON2) $(VK_FORMAT_TABLE_SCRIPT) $(vk_format_layout_csv) > $@
-
-LOCAL_SHARED_LIBRARIES += $(RADV_SHARED_LIBRARIES)
-
-LOCAL_EXPORT_C_INCLUDE_DIRS := \
-	$(MESA_TOP)/src/amd/vulkan \
-	$(intermediates)
-
-include $(MESA_COMMON_MK)
-include $(BUILD_STATIC_LIBRARY)
-
-#
-# libvulkan_radeon
-#
-
-include $(CLEAR_VARS)
-
-LOCAL_MODULE := vulkan.radv
-LOCAL_MODULE_CLASS := SHARED_LIBRARIES
-LOCAL_PROPRIETARY_MODULE := true
-LOCAL_MODULE_RELATIVE_PATH := hw
-
-LOCAL_LDFLAGS += -Wl,--build-id=sha1
-
-LOCAL_SRC_FILES := \
-	$(VULKAN_ANDROID_FILES)
-
-LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare LLVMInitializeAMDGPU* functions
-
-$(call mesa-build-with-llvm)
-
-LOCAL_C_INCLUDES := \
-	$(RADV_COMMON_INCLUDES) \
-	$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_radv_common,,)
-
-LOCAL_EXPORT_C_INCLUDE_DIRS := \
-	$(MESA_TOP)/src/amd/vulkan \
-	$(intermediates)
-
-LOCAL_WHOLE_STATIC_LIBRARIES := \
-	libmesa_util \
-	libmesa_nir \
-	libmesa_glsl \
-	libmesa_compiler \
-	libmesa_amdgpu_addrlib \
-	libmesa_amd_common \
-	libmesa_radv_common
-
-LOCAL_SHARED_LIBRARIES += $(RADV_SHARED_LIBRARIES) libz libsync liblog
-
-include $(MESA_COMMON_MK)
-include $(BUILD_SHARED_LIBRARY)

src/amd/vulkan/Makefile.am

@@ -59,10 +59,6 @@ AM_CFLAGS = \
 	$(PTHREAD_CFLAGS) \
 	$(LLVM_CFLAGS)
 
-AM_CXXFLAGS = \
-	$(VISIBILITY_CXXFLAGS) \
-	$(LLVM_CXXFLAGS)
-
 VULKAN_SOURCES = \
 	$(VULKAN_GENERATED_FILES) \
 	$(VULKAN_FILES)
@@ -84,22 +80,6 @@ VULKAN_LIB_DEPS = \
 	$(DLOPEN_LIBS) \
 	-lm
 
-if HAVE_PLATFORM_DRM
-AM_CPPFLAGS += \
-	-DVK_USE_PLATFORM_DISPLAY_KHR
-
-VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
-endif
-
-if HAVE_XLIB_LEASE
-AM_CPPFLAGS += \
-	-DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
-	$(XCB_RANDR_CFLAGS) \
-	$(XLIB_RANDR_CFLAGS)
-
-VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
-endif
-
 if HAVE_PLATFORM_X11
 AM_CPPFLAGS += \
 	$(XCB_DRI3_CFLAGS) \
@@ -124,7 +104,7 @@ VULKAN_LIB_DEPS += \
 endif
 
 if HAVE_PLATFORM_ANDROID
-AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
+AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR
 AM_CFLAGS += $(ANDROID_CFLAGS)
 VULKAN_LIB_DEPS += $(ANDROID_LIBS)
 VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)

src/amd/vulkan/Makefile.sources

@@ -54,7 +54,6 @@ VULKAN_FILES := \
 	radv_meta_resolve_cs.c \
 	radv_meta_resolve_fs.c \
 	radv_nir_to_llvm.c \
-	radv_llvm_helper.cpp \
 	radv_pass.c \
 	radv_pipeline.c \
 	radv_pipeline_cache.c \
@@ -63,7 +62,6 @@ VULKAN_FILES := \
 	radv_shader.c \
 	radv_shader_info.c \
 	radv_shader.h \
-	radv_shader_helper.h \
 	radv_query.c \
 	radv_util.c \
 	radv_util.h \
@@ -81,9 +79,6 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
 	radv_wsi_x11.c
 
-VULKAN_WSI_DISPLAY_FILES := \
-	radv_wsi_display.c
-
 VULKAN_GENERATED_FILES := \
 	radv_entrypoints.c \
 	radv_entrypoints.h \

src/amd/vulkan/meson.build

@@ -67,7 +67,6 @@ libradv_files = files(
   'radv_descriptor_set.h',
   'radv_formats.c',
   'radv_image.c',
-  'radv_llvm_helper.cpp',
   'radv_meta.c',
   'radv_meta.h',
   'radv_meta_blit.c',
@@ -89,7 +88,6 @@ libradv_files = files(
   'radv_radeon_winsys.h',
   'radv_shader.c',
   'radv_shader.h',
-  'radv_shader_helper.h',
   'radv_shader_info.c',
   'radv_query.c',
   'radv_util.c',
@@ -117,16 +115,6 @@ if with_platform_wayland
   libradv_files += files('radv_wsi_wayland.c')
 endif
 
-if with_platform_drm
-  radv_flags += '-DVK_USE_PLATFORM_DISPLAY_KHR'
-  libradv_files += files('radv_wsi_display.c')
-endif
-
-if with_xlib_lease
-  radv_deps += [dep_xcb_xrandr, dep_xlib_xrandr]
-  radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
-endif
-
 libvulkan_radeon = shared_library(
   'vulkan_radeon',
   [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c],

src/amd/vulkan/radv_android.c

@@ -122,7 +122,7 @@ radv_image_from_gralloc(VkDevice device_h,
 		return result;
 
 	if (gralloc_info->handle->numFds != 1) {
-		return vk_errorf(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR,
+		return vk_errorf(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR,
 		                 "VkNativeBufferANDROID::handle::numFds is %d, "
 		                 "expected 1", gralloc_info->handle->numFds);
 	}
@@ -233,7 +233,7 @@ VkResult radv_GetSwapchainGrallocUsageANDROID(
 	result = radv_GetPhysicalDeviceImageFormatProperties2(phys_dev_h,
 	                                                      &image_format_info, &image_format_props);
 	if (result != VK_SUCCESS) {
-		return vk_errorf(device->instance, result,
+		return vk_errorf(result,
 		                 "radv_GetPhysicalDeviceImageFormatProperties2 failed "
 		                 "inside %s", __func__);
 	}
@@ -252,7 +252,7 @@ VkResult radv_GetSwapchainGrallocUsageANDROID(
 	 * gralloc swapchains.
 	 */
 	if (imageUsage != 0) {
-	return vk_errorf(device->instance, VK_ERROR_FORMAT_NOT_SUPPORTED,
+	return vk_errorf(VK_ERROR_FORMAT_NOT_SUPPORTED,
 	                "unsupported VkImageUsageFlags(0x%x) for gralloc "
 	                "swapchain", imageUsage);
 	}

src/amd/vulkan/radv_cs.h

@@ -31,7 +31,7 @@
 #include "sid.h"
 
 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
-                                      struct radeon_cmdbuf *cs,
+                                      struct radeon_winsys_cs *cs,
                                       unsigned needed)
 {
         if (cs->max_dw - cs->cdw < needed)
@@ -39,7 +39,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
         return cs->cdw + needed;
 }
 
-static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
+static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
         assert(reg < SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -48,13 +48,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned
         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
+static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
         radeon_set_config_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
-static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
+static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
         assert(reg >= SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -63,14 +63,14 @@ static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned
         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
+static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
         radeon_set_context_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
 
-static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
+static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 					      unsigned reg, unsigned idx,
 					      unsigned value)
 {
@@ -81,7 +81,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
 	radeon_emit(cs, value);
 }
 
-static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
+static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
 	assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 	assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -90,13 +90,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg,
 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
+static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
 	radeon_set_sh_reg_seq(cs, reg, 1);
 	radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
 	assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 	assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -105,13 +105,13 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned
 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
+static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 {
 	radeon_set_uconfig_reg_seq(cs, reg, 1);
 	radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
+static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
 					      unsigned reg, unsigned idx,
 					      unsigned value)
 {

src/amd/vulkan/radv_debug.c

@@ -80,7 +80,7 @@ radv_init_trace(struct radv_device *device)
 }
 
 static void
-radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
+radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
 {
 	const char *filename = getenv("RADV_TRACE_FILE");
 	FILE *f = fopen(filename, "w");
@@ -369,9 +369,11 @@ static void si_add_split_disasm(const char *disasm,
 }
 
 static void
-radv_dump_annotated_shader(struct radv_shader_variant *shader,
-			   gl_shader_stage stage, struct ac_wave_info *waves,
-			   unsigned num_waves, FILE *f)
+radv_dump_annotated_shader(struct radv_pipeline *pipeline,
+			   struct radv_shader_variant *shader,
+			   gl_shader_stage stage,
+			   struct ac_wave_info *waves, unsigned num_waves,
+			   FILE *f)
 {
 	uint64_t start_addr, end_addr;
 	unsigned i;
@@ -442,22 +444,28 @@ radv_dump_annotated_shader(struct radv_shader_variant *shader,
 
 static void
 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
-			    VkShaderStageFlagBits active_stages, FILE *f)
+			    struct radv_shader_variant *compute_shader,
+			    FILE *f)
 {
 	struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
 	unsigned num_waves = ac_get_wave_info(waves);
+	unsigned mask;
 
 	fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 		"\n\n", num_waves);
 
 	/* Dump annotated active graphics shaders. */
-	while (active_stages) {
-		int stage = u_bit_scan(&active_stages);
+	mask = pipeline->active_stages;
+	while (mask) {
+		int stage = u_bit_scan(&mask);
 
-		radv_dump_annotated_shader(pipeline->shaders[stage],
+		radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
 					   stage, waves, num_waves, f);
 	}
 
+	radv_dump_annotated_shader(pipeline, compute_shader,
+				   MESA_SHADER_COMPUTE, waves, num_waves, f);
+
 	/* Print waves executing shaders that are not currently bound. */
 	unsigned i;
 	bool found = false;
@@ -515,51 +523,48 @@ radv_dump_shader(struct radv_pipeline *pipeline,
 
 static void
 radv_dump_shaders(struct radv_pipeline *pipeline,
-		  VkShaderStageFlagBits active_stages, FILE *f)
+		  struct radv_shader_variant *compute_shader, FILE *f)
 {
+	unsigned mask;
+
 	/* Dump active graphics shaders. */
-	while (active_stages) {
-		int stage = u_bit_scan(&active_stages);
+	mask = pipeline->active_stages;
+	while (mask) {
+		int stage = u_bit_scan(&mask);
 
 		radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 	}
-}
 
-static void
-radv_dump_pipeline_state(struct radv_pipeline *pipeline,
-			 VkShaderStageFlagBits active_stages, FILE *f)
-{
-	radv_dump_shaders(pipeline, active_stages, f);
-	radv_dump_annotated_shaders(pipeline, active_stages, f);
-	radv_dump_descriptors(pipeline, f);
+	radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
 }
 
 static void
 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 			 struct radv_pipeline *compute_pipeline, FILE *f)
 {
-	VkShaderStageFlagBits active_stages;
+	struct radv_shader_variant *compute_shader =
+		compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
 
-	if (graphics_pipeline) {
-		active_stages = graphics_pipeline->active_stages;
-		radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
-	}
+	if (!graphics_pipeline)
+		return;
 
-	if (compute_pipeline) {
-		active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
-		radv_dump_pipeline_state(compute_pipeline, active_stages, f);
-	}
+	radv_dump_shaders(graphics_pipeline, compute_shader, f);
+	radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
+	radv_dump_descriptors(graphics_pipeline, f);
 }
 
 static void
 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 {
-	VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
-
 	if (!compute_pipeline)
 		return;
 
-	radv_dump_pipeline_state(compute_pipeline, active_stages, f);
+	radv_dump_shaders(compute_pipeline,
+			  compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
+	radv_dump_annotated_shaders(compute_pipeline,
+				    compute_pipeline->shaders[MESA_SHADER_COMPUTE],
+				    f);
+	radv_dump_descriptors(compute_pipeline, f);
 }
 
 static struct radv_pipeline *
@@ -638,9 +643,11 @@ radv_dump_device_name(struct radv_device *device, FILE *f)
 		snprintf(kernel_version, sizeof(kernel_version),
 			 " / %s", uname_data.release);
 
-	snprintf(llvm_string, sizeof(llvm_string),
-		 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
-		 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
+	if (HAVE_LLVM > 0) {
+		snprintf(llvm_string, sizeof(llvm_string),
+			 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
+			 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
+	}
 
 	fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
 		chip_name, device->physical_device->name,
@@ -660,7 +667,7 @@ radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 }
 
 void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 {
 	struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 	struct radv_device *device = queue->device;

src/amd/vulkan/radv_debug.h

@@ -44,12 +44,6 @@ enum {
 	RADV_DEBUG_NO_SISCHED        = 0x4000,
 	RADV_DEBUG_PREOPTIR          = 0x8000,
 	RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x10000,
-	RADV_DEBUG_NO_OUT_OF_ORDER   = 0x20000,
-	RADV_DEBUG_INFO              = 0x40000,
-	RADV_DEBUG_ERRORS            = 0x80000,
-	RADV_DEBUG_STARTUP           = 0x100000,
-	RADV_DEBUG_CHECKIR           = 0x200000,
-	RADV_DEBUG_NOTHREADLLVM      = 0x400000,
 };
 
 enum {
@@ -65,7 +59,7 @@ bool
 radv_init_trace(struct radv_device *device);
 
 void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs);
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs);
 
 void
 radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp);

src/amd/vulkan/radv_descriptor_set.c

@@ -95,7 +95,7 @@ VkResult radv_CreateDescriptorSetLayout(
 	set_layout = vk_alloc2(&device->alloc, pAllocator, size, 8,
 				 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (!set_layout)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	set_layout->flags = pCreateInfo->flags;
 
@@ -106,7 +106,7 @@ VkResult radv_CreateDescriptorSetLayout(
 	                                                                pCreateInfo->bindingCount);
 	if (!bindings) {
 		vk_free2(&device->alloc, pAllocator, set_layout);
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 	}
 
 	set_layout->binding_count = max_binding + 1;
@@ -322,7 +322,7 @@ void radv_GetDescriptorSetLayoutSupport(VkDevice device,
 
 /*
  * Pipeline layouts.  These have nothing to do with the pipeline.  They are
- * just multiple descriptor set layouts pasted together.
+ * just muttiple descriptor set layouts pasted together
  */
 
 VkResult radv_CreatePipelineLayout(
@@ -340,7 +340,7 @@ VkResult radv_CreatePipelineLayout(
 	layout = vk_alloc2(&device->alloc, pAllocator, sizeof(*layout), 8,
 			     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (layout == NULL)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	layout->num_sets = pCreateInfo->setLayoutCount;
 
@@ -412,7 +412,7 @@ radv_descriptor_set_create(struct radv_device *device,
 
 	if (pool->host_memory_base) {
 		if (pool->host_memory_end - pool->host_memory_ptr < mem_size)
-			return vk_error(device->instance, VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
+			return vk_error(VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
 
 		set = (struct radv_descriptor_set*)pool->host_memory_ptr;
 		pool->host_memory_ptr += mem_size;
@@ -421,7 +421,7 @@ radv_descriptor_set_create(struct radv_device *device,
 		                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 
 		if (!set)
-			return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+			return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 	}
 
 	memset(set, 0, mem_size);
@@ -437,7 +437,7 @@ radv_descriptor_set_create(struct radv_device *device,
 
 		if (!pool->host_memory_base && pool->entry_count == pool->max_entry_count) {
 			vk_free2(&device->alloc, NULL, set);
-			return vk_error(device->instance, VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
+			return vk_error(VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
 		}
 
 		/* try to allocate linearly first, so that we don't spend
@@ -466,7 +466,7 @@ radv_descriptor_set_create(struct radv_device *device,
 
 			if (pool->size - offset < layout_size) {
 				vk_free2(&device->alloc, NULL, set);
-				return vk_error(device->instance, VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
+				return vk_error(VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
 			}
 			set->bo = pool->bo;
 			set->mapped_ptr = (uint32_t*)(pool->mapped_ptr + offset);
@@ -478,7 +478,7 @@ radv_descriptor_set_create(struct radv_device *device,
 			pool->entries[index].set = set;
 			pool->entry_count++;
 		} else
-			return vk_error(device->instance, VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
+			return vk_error(VK_ERROR_OUT_OF_POOL_MEMORY_KHR);
 	}
 
 	if (layout->has_immutable_samplers) {
@@ -580,7 +580,7 @@ VkResult radv_CreateDescriptorPool(
 	pool = vk_alloc2(&device->alloc, pAllocator, size, 8,
 	                 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (!pool)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	memset(pool, 0, sizeof(*pool));
 
@@ -594,8 +594,7 @@ VkResult radv_CreateDescriptorPool(
 		pool->bo = device->ws->buffer_create(device->ws, bo_size, 32,
 						     RADEON_DOMAIN_VRAM,
 						     RADEON_FLAG_NO_INTERPROCESS_SHARING |
-						     RADEON_FLAG_READ_ONLY |
-						     RADEON_FLAG_32BIT);
+						     RADEON_FLAG_READ_ONLY);
 		pool->mapped_ptr = (uint8_t*)device->ws->buffer_map(pool->bo);
 	}
 	pool->size = bo_size;
@@ -721,7 +720,7 @@ static void write_texel_buffer_descriptor(struct radv_device *device,
 	memcpy(dst, buffer_view->state, 4 * 4);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo, 7);
 	else
 		*buffer_list = buffer_view->bo;
 }
@@ -751,7 +750,7 @@ static void write_buffer_descriptor(struct radv_device *device,
 		S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 7);
 	else
 		*buffer_list = buffer->bo;
 }
@@ -795,7 +794,7 @@ write_image_descriptor(struct radv_device *device,
 	memcpy(dst, descriptor, 16 * 4);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo, 7);
 	else
 		*buffer_list = iview->bo;
 }
@@ -996,7 +995,7 @@ VkResult radv_CreateDescriptorUpdateTemplate(VkDevice _device,
 
 	templ = vk_alloc2(&device->alloc, pAllocator, size, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (!templ)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	templ->entry_count = entry_count;
 	templ->bind_point = pCreateInfo->pipelineBindPoint;

src/amd/vulkan/radv_entrypoints_gen.py

@@ -116,7 +116,7 @@ struct string_map_entry {
    uint32_t num;
 };
 
-/* We use a big string constant to avoid lots of relocations from the entry
+/* We use a big string constant to avoid lots of reloctions from the entry
  * point table to lots of little strings. The entries in the entry point table
  * store the index into this big string.
  */
@@ -136,7 +136,7 @@ static const struct string_map_entry string_map_entries[] = {
 /* Hash table stats:
  * size ${len(strmap.sorted_strings)} entries
  * collisions entries:
-% for i in range(10):
+% for i in xrange(10):
  *     ${i}${'+' if i == 9 else ' '}     ${strmap.collisions[i]}
 % endfor
  */
@@ -430,7 +430,7 @@ def get_entrypoints(doc, entrypoints_to_defines, start_index):
             e_clone.name = e.name
             entrypoints[e.name] = e_clone
 
-    return [e for e in entrypoints.values() if e.enabled]
+    return [e for e in entrypoints.itervalues() if e.enabled]
 
 
 def get_entrypoints_defines(doc):
@@ -446,10 +446,7 @@ def get_entrypoints_defines(doc):
 
     for extension in doc.findall('./extensions/extension[@platform]'):
         platform = extension.attrib['platform']
-        ext = '_KHR'
-        if platform.upper() == 'XLIB_XRANDR':
-            ext = '_EXT'
-        define = 'VK_USE_PLATFORM_' + platform.upper() + ext
+        define = 'VK_USE_PLATFORM_' + platform.upper() + '_KHR'
 
         for entrypoint in extension.findall('./require/command'):
             fullname = entrypoint.attrib['name']

src/amd/vulkan/radv_extensions.py

@@ -51,14 +51,11 @@ class Extension:
 # and dEQP-VK.api.info.device fail due to the duplicated strings.
 EXTENSIONS = [
     Extension('VK_ANDROID_native_buffer',                 5, 'ANDROID && device->rad_info.has_syncobj_wait_for_submit'),
-    Extension('VK_KHR_16bit_storage',                     1, 'HAVE_LLVM >= 0x0700'),
     Extension('VK_KHR_bind_memory2',                      1, True),
-    Extension('VK_KHR_create_renderpass2',                1, True),
     Extension('VK_KHR_dedicated_allocation',              1, True),
     Extension('VK_KHR_descriptor_update_template',        1, True),
     Extension('VK_KHR_device_group',                      1, True),
     Extension('VK_KHR_device_group_creation',             1, True),
-    Extension('VK_KHR_draw_indirect_count',               1, True),
     Extension('VK_KHR_external_fence',                    1, 'device->rad_info.has_syncobj_wait_for_submit'),
     Extension('VK_KHR_external_fence_capabilities',       1, True),
     Extension('VK_KHR_external_fence_fd',                 1, 'device->rad_info.has_syncobj_wait_for_submit'),
@@ -68,7 +65,6 @@ EXTENSIONS = [
     Extension('VK_KHR_external_semaphore',                1, 'device->rad_info.has_syncobj'),
     Extension('VK_KHR_external_semaphore_capabilities',   1, True),
     Extension('VK_KHR_external_semaphore_fd',             1, 'device->rad_info.has_syncobj'),
-    Extension('VK_KHR_get_display_properties2',           1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
     Extension('VK_KHR_get_memory_requirements2',          1, True),
     Extension('VK_KHR_get_physical_device_properties2',   1, True),
     Extension('VK_KHR_get_surface_capabilities2',         1, 'RADV_HAS_SURFACE'),
@@ -89,12 +85,6 @@ EXTENSIONS = [
     Extension('VK_KHR_xcb_surface',                       6, 'VK_USE_PLATFORM_XCB_KHR'),
     Extension('VK_KHR_xlib_surface',                      6, 'VK_USE_PLATFORM_XLIB_KHR'),
     Extension('VK_KHR_multiview',                         1, True),
-    Extension('VK_KHR_display',                          23, 'VK_USE_PLATFORM_DISPLAY_KHR'),
-    Extension('VK_EXT_direct_mode_display',               1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
-    Extension('VK_EXT_acquire_xlib_display',              1, 'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
-    Extension('VK_EXT_conditional_rendering',             1, True),
-    Extension('VK_EXT_display_surface_counter',           1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
-    Extension('VK_EXT_display_control',                   1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
     Extension('VK_EXT_debug_report',                      9, True),
     Extension('VK_EXT_depth_range_unrestricted',          1, True),
     Extension('VK_EXT_descriptor_indexing',               2, True),
@@ -104,7 +94,6 @@ EXTENSIONS = [
     Extension('VK_EXT_global_priority',                   1, 'device->rad_info.has_ctx_priority'),
     Extension('VK_EXT_sampler_filter_minmax',             1, 'device->rad_info.chip_class >= CIK'),
     Extension('VK_EXT_shader_viewport_index_layer',       1, True),
-    Extension('VK_EXT_shader_stencil_export',             1, True),
     Extension('VK_EXT_vertex_attribute_divisor',          1, True),
     Extension('VK_AMD_draw_indirect_count',               1, True),
     Extension('VK_AMD_gcn_shader',                        1, True),
@@ -206,9 +195,9 @@ struct radv_device_extension_table {
    };
 };
 
-extern const VkExtensionProperties radv_instance_extensions[RADV_INSTANCE_EXTENSION_COUNT];
-extern const VkExtensionProperties radv_device_extensions[RADV_DEVICE_EXTENSION_COUNT];
-extern const struct radv_instance_extension_table radv_supported_instance_extensions;
+const VkExtensionProperties radv_instance_extensions[RADV_INSTANCE_EXTENSION_COUNT];
+const VkExtensionProperties radv_device_extensions[RADV_DEVICE_EXTENSION_COUNT];
+const struct radv_instance_extension_table radv_supported_instance_extensions;
 
 
 struct radv_physical_device;
@@ -224,12 +213,12 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID_KHR', 'WAYLAND_KHR', 'XCB_KHR', 'XLIB_KHR', 'DISPLAY_KHR', 'XLIB_XRANDR_EXT']:
-#ifdef VK_USE_PLATFORM_${platform}
-#   undef VK_USE_PLATFORM_${platform}
-#   define VK_USE_PLATFORM_${platform} true
+%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB']:
+#ifdef VK_USE_PLATFORM_${platform}_KHR
+#   undef VK_USE_PLATFORM_${platform}_KHR
+#   define VK_USE_PLATFORM_${platform}_KHR true
 #else
-#   define VK_USE_PLATFORM_${platform} false
+#   define VK_USE_PLATFORM_${platform}_KHR false
 #endif
 %endfor
 
@@ -243,9 +232,7 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 
 #define RADV_HAS_SURFACE (VK_USE_PLATFORM_WAYLAND_KHR || \\
                          VK_USE_PLATFORM_XCB_KHR || \\
-                         VK_USE_PLATFORM_XLIB_KHR || \\
-                         VK_USE_PLATFORM_DISPLAY_KHR)
-
+                         VK_USE_PLATFORM_XLIB_KHR)
 
 const VkExtensionProperties radv_instance_extensions[RADV_INSTANCE_EXTENSION_COUNT] = {
 %for ext in instance_extensions:

src/amd/vulkan/radv_formats.c

@@ -224,28 +224,6 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
 		}
 	}
 
-	if (desc->layout == VK_FORMAT_LAYOUT_ETC) {
-		switch (format) {
-		case VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK:
-		case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
-			return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
-		case VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK:
-		case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
-			return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
-		case VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK:
-		case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
-			return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
-		case VK_FORMAT_EAC_R11_UNORM_BLOCK:
-		case VK_FORMAT_EAC_R11_SNORM_BLOCK:
-			return V_008F14_IMG_DATA_FORMAT_ETC2_R;
-		case VK_FORMAT_EAC_R11G11_UNORM_BLOCK:
-		case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
-			return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
-		default:
-			break;
-		}
-	}
-
 	if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
 		return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
 	} else if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32) {
@@ -343,8 +321,10 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
 			return V_008F14_IMG_DATA_FORMAT_32;
 		case 2:
 			return V_008F14_IMG_DATA_FORMAT_32_32;
+#if 0 /* Not supported for render targets */
 		case 3:
 			return V_008F14_IMG_DATA_FORMAT_32_32_32;
+#endif
 		case 4:
 			return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
 		}
@@ -371,15 +351,10 @@ uint32_t radv_translate_tex_numformat(VkFormat format,
 				case VK_FORMAT_BC2_SRGB_BLOCK:
 				case VK_FORMAT_BC3_SRGB_BLOCK:
 				case VK_FORMAT_BC7_SRGB_BLOCK:
-				case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
-				case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
-				case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
 					return V_008F14_IMG_NUM_FORMAT_SRGB;
 				case VK_FORMAT_BC4_SNORM_BLOCK:
 				case VK_FORMAT_BC5_SNORM_BLOCK:
 			        case VK_FORMAT_BC6H_SFLOAT_BLOCK:
-				case VK_FORMAT_EAC_R11_SNORM_BLOCK:
-				case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
 					return V_008F14_IMG_NUM_FORMAT_SNORM;
 				default:
 					return V_008F14_IMG_NUM_FORMAT_UNORM;
@@ -611,15 +586,6 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
 		return;
 	}
 
-	if (desc->layout == VK_FORMAT_LAYOUT_ETC &&
-	    physical_device->rad_info.chip_class < GFX9 &&
-	    physical_device->rad_info.family != CHIP_STONEY) {
-		out_properties->linearTilingFeatures = linear;
-		out_properties->optimalTilingFeatures = tiled;
-		out_properties->bufferFeatures = buffer;
-		return;
-	}
-
 	if (radv_is_storage_image_format_supported(physical_device, format)) {
 		tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
 		linear |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
@@ -672,17 +638,13 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
 				tiled |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
 			}
 		}
-		if (tiled && !scaled) {
+		if (tiled && util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
 			tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
 			         VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
 		}
-
-		/* Tiled formatting does not support NPOT pixel sizes */
-		if (!util_is_power_of_two_or_zero(vk_format_get_blocksize(format)))
-			tiled = 0;
 	}
 
-	if (linear && !scaled) {
+	if (linear && util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
 		linear |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
 		          VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
 	}
@@ -916,87 +878,194 @@ bool radv_format_pack_clear_color(VkFormat format,
 				  uint32_t clear_vals[2],
 				  VkClearColorValue *value)
 {
+	uint8_t r = 0, g = 0, b = 0, a = 0;
 	const struct vk_format_description *desc = vk_format_description(format);
 
-	if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32) {
-		clear_vals[0] = float3_to_r11g11b10f(value->float32);
+	if (vk_format_get_component_bits(format, VK_FORMAT_COLORSPACE_RGB, 0) <= 8) {
+		if (desc->colorspace == VK_FORMAT_COLORSPACE_RGB) {
+			r = float_to_ubyte(value->float32[0]);
+			g = float_to_ubyte(value->float32[1]);
+			b = float_to_ubyte(value->float32[2]);
+			a = float_to_ubyte(value->float32[3]);
+		} else if (desc->colorspace == VK_FORMAT_COLORSPACE_SRGB) {
+			r = util_format_linear_float_to_srgb_8unorm(value->float32[0]);
+			g = util_format_linear_float_to_srgb_8unorm(value->float32[1]);
+			b = util_format_linear_float_to_srgb_8unorm(value->float32[2]);
+			a = float_to_ubyte(value->float32[3]);
+		}
+	}
+	switch (format) {
+	case VK_FORMAT_R8_UNORM:
+	case VK_FORMAT_R8_SRGB:
+		clear_vals[0] = r;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8_UNORM:
+	case VK_FORMAT_R8G8_SRGB:
+		clear_vals[0] = r | g << 8;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8B8A8_SRGB:
+	case VK_FORMAT_R8G8B8A8_UNORM:
+		clear_vals[0] = r | g << 8 | b << 16 | a << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_B8G8R8A8_SRGB:
+	case VK_FORMAT_B8G8R8A8_UNORM:
+		clear_vals[0] = b | g << 8 | r << 16 | a << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_A8B8G8R8_UNORM_PACK32:
+	case VK_FORMAT_A8B8G8R8_SRGB_PACK32:
+		clear_vals[0] = r | g << 8 | b << 16 | a << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8_UINT:
+		clear_vals[0] = value->uint32[0] & 0xff;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8_SINT:
+		clear_vals[0] = value->int32[0] & 0xff;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16_UINT:
+		clear_vals[0] = value->uint32[0] & 0xffff;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8_UINT:
+		clear_vals[0] = value->uint32[0] & 0xff;
+		clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8_SINT:
+		clear_vals[0] = value->int32[0] & 0xff;
+		clear_vals[0] |= (value->int32[1] & 0xff) << 8;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8B8A8_UINT:
+		clear_vals[0] = value->uint32[0] & 0xff;
+		clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
+		clear_vals[0] |= (value->uint32[2] & 0xff) << 16;
+		clear_vals[0] |= (value->uint32[3] & 0xff) << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R8G8B8A8_SINT:
+		clear_vals[0] = value->int32[0] & 0xff;
+		clear_vals[0] |= (value->int32[1] & 0xff) << 8;
+		clear_vals[0] |= (value->int32[2] & 0xff) << 16;
+		clear_vals[0] |= (value->int32[3] & 0xff) << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_A8B8G8R8_UINT_PACK32:
+		clear_vals[0] = value->uint32[0] & 0xff;
+		clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
+		clear_vals[0] |= (value->uint32[2] & 0xff) << 16;
+		clear_vals[0] |= (value->uint32[3] & 0xff) << 24;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16_UINT:
+		clear_vals[0] = value->uint32[0] & 0xffff;
+		clear_vals[0] |= (value->uint32[1] & 0xffff) << 16;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16B16A16_UINT:
+		clear_vals[0] = value->uint32[0] & 0xffff;
+		clear_vals[0] |= (value->uint32[1] & 0xffff) << 16;
+		clear_vals[1] = value->uint32[2] & 0xffff;
+		clear_vals[1] |= (value->uint32[3] & 0xffff) << 16;
+		break;
+	case VK_FORMAT_R32_UINT:
+		clear_vals[0] = value->uint32[0];
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R32G32_UINT:
+		clear_vals[0] = value->uint32[0];
+		clear_vals[1] = value->uint32[1];
+		break;
+	case VK_FORMAT_R32_SINT:
+		clear_vals[0] = value->int32[0];
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16_SFLOAT:
+		clear_vals[0] = util_float_to_half(value->float32[0]);
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16_SFLOAT:
+		clear_vals[0] = util_float_to_half(value->float32[0]);
+		clear_vals[0] |= (uint32_t)util_float_to_half(value->float32[1]) << 16;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16B16A16_SFLOAT:
+		clear_vals[0] = util_float_to_half(value->float32[0]);
+		clear_vals[0] |= (uint32_t)util_float_to_half(value->float32[1]) << 16;
+		clear_vals[1] = util_float_to_half(value->float32[2]);
+		clear_vals[1] |= (uint32_t)util_float_to_half(value->float32[3]) << 16;
+		break;
+	case VK_FORMAT_R16_UNORM:
+		clear_vals[0] = ((uint16_t)util_iround(CLAMP(value->float32[0], 0.0f, 1.0f) * 0xffff)) & 0xffff;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16_UNORM:
+		clear_vals[0] = ((uint16_t)util_iround(CLAMP(value->float32[0], 0.0f, 1.0f) * 0xffff)) & 0xffff;
+		clear_vals[0] |= ((uint16_t)util_iround(CLAMP(value->float32[1], 0.0f, 1.0f) * 0xffff)) << 16;
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R16G16B16A16_UNORM:
+		clear_vals[0] = ((uint16_t)util_iround(CLAMP(value->float32[0], 0.0f, 1.0f) * 0xffff)) & 0xffff;
+		clear_vals[0] |= ((uint16_t)util_iround(CLAMP(value->float32[1], 0.0f, 1.0f) * 0xffff)) << 16;
+		clear_vals[1] = ((uint16_t)util_iround(CLAMP(value->float32[2], 0.0f, 1.0f) * 0xffff)) & 0xffff;
+		clear_vals[1] |= ((uint16_t)util_iround(CLAMP(value->float32[3], 0.0f, 1.0f) * 0xffff)) << 16;
+		break;
+	case VK_FORMAT_R16G16B16A16_SNORM:
+		clear_vals[0] = ((uint16_t)util_iround(CLAMP(value->float32[0], -1.0f, 1.0f) * 0x7fff)) & 0xffff;
+		clear_vals[0] |= ((uint16_t)util_iround(CLAMP(value->float32[1], -1.0f, 1.0f) * 0x7fff)) << 16;
+		clear_vals[1] = ((uint16_t)util_iround(CLAMP(value->float32[2], -1.0f, 1.0f) * 0x7fff)) & 0xffff;
+		clear_vals[1] |= ((uint16_t)util_iround(CLAMP(value->float32[3], -1.0f, 1.0f) * 0x7fff)) << 16;
+		break;
+	case VK_FORMAT_A2B10G10R10_UNORM_PACK32:
+		clear_vals[0] = ((uint16_t)util_iround(CLAMP(value->float32[0], 0.0f, 1.0f) * 0x3ff)) & 0x3ff;
+		clear_vals[0] |= (((uint16_t)util_iround(CLAMP(value->float32[1], 0.0f, 1.0f) * 0x3ff)) & 0x3ff) << 10;
+		clear_vals[0] |= (((uint16_t)util_iround(CLAMP(value->float32[2], 0.0f, 1.0f) * 0x3ff)) & 0x3ff) << 20;
+		clear_vals[0] |= (((uint16_t)util_iround(CLAMP(value->float32[3], 0.0f, 1.0f) * 0x3)) & 0x3) << 30;
 		clear_vals[1] = 0;
 		return true;
-	}
-
-	if (desc->layout != VK_FORMAT_LAYOUT_PLAIN) {
-		fprintf(stderr, "failed to fast clear for non-plain format %d\n", format);
-		return false;
-	}
-
-	if (!util_is_power_of_two_or_zero(desc->block.bits)) {
-		fprintf(stderr, "failed to fast clear for NPOT format %d\n", format);
-		return false;
-	}
-
-	if (desc->block.bits > 64) {
-		/*
-		 * We have a 128 bits format, check if the first 3 components are the same.
-		 * Every elements has to be 32 bits since we don't support 64-bit formats,
-		 * and we can skip swizzling checks as alpha always comes last for these and
-		 * we do not care about the rest as they have to be the same.
-		 */
-		if (desc->channel[0].type == VK_FORMAT_TYPE_FLOAT) {
-			if (value->float32[0] != value->float32[1] ||
-			    value->float32[0] != value->float32[2])
-				return false;
-		} else {
-			if (value->uint32[0] != value->uint32[1] ||
-			    value->uint32[0] != value->uint32[2])
-				return false;
-		}
+	case VK_FORMAT_R32G32_SFLOAT:
+		clear_vals[0] = fui(value->float32[0]);
+		clear_vals[1] = fui(value->float32[1]);
+		break;
+	case VK_FORMAT_R32_SFLOAT:
+		clear_vals[1] = 0;
+		clear_vals[0] = fui(value->float32[0]);
+		break;
+	case VK_FORMAT_B10G11R11_UFLOAT_PACK32:
+		clear_vals[0] = float3_to_r11g11b10f(value->float32);
+		clear_vals[1] = 0;
+		break;
+	case VK_FORMAT_R32G32B32A32_SFLOAT:
+		if (value->float32[0] != value->float32[1] ||
+		    value->float32[0] != value->float32[2])
+			return false;
+		clear_vals[0] = fui(value->float32[0]);
+		clear_vals[1] = fui(value->float32[3]);
+		break;
+	case VK_FORMAT_R32G32B32A32_UINT:
+		if (value->uint32[0] != value->uint32[1] ||
+		    value->uint32[0] != value->uint32[2])
+			return false;
 		clear_vals[0] = value->uint32[0];
 		clear_vals[1] = value->uint32[3];
-		return true;
-	}
-	uint64_t clear_val = 0;
-
-	for (unsigned c = 0; c < 4; ++c) {
-		if (desc->swizzle[c] >= 4)
-			continue;
-
-		const struct vk_format_channel_description *channel = &desc->channel[desc->swizzle[c]];
-		assert(channel->size);
-
-		uint64_t v = 0;
-		if (channel->pure_integer) {
-			v = value->uint32[c]  & ((1ULL << channel->size) - 1);
-		} else if (channel->normalized) {
-			if (channel->type == VK_FORMAT_TYPE_UNSIGNED &&
-			    desc->swizzle[c] < 3 &&
-			    desc->colorspace == VK_FORMAT_COLORSPACE_SRGB) {
-				assert(channel->size == 8);
-
-				v = util_format_linear_float_to_srgb_8unorm(value->float32[c]);
-			} else if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
-				v = MAX2(MIN2(value->float32[c], 1.0f), 0.0f) * ((1ULL << channel->size) - 1);
-			} else  {
-				v = MAX2(MIN2(value->float32[c], 1.0f), -1.0f) * ((1ULL << (channel->size - 1)) - 1);
-			}
-		} else if (channel->type == VK_FORMAT_TYPE_FLOAT) {
-			if (channel->size == 32) {
-				memcpy(&v, &value->float32[c], 4);
-			} else if(channel->size == 16) {
-				v = util_float_to_half(value->float32[c]);
-			} else {
-				fprintf(stderr, "failed to fast clear for unhandled float size in format %d\n", format);
-				return false;
-			}
-		} else {
-			fprintf(stderr, "failed to fast clear for unhandled component type in format %d\n", format);
+		break;
+	case VK_FORMAT_R32G32B32A32_SINT:
+		if (value->int32[0] != value->int32[1] ||
+		    value->int32[0] != value->int32[2])
 			return false;
-		}
-		clear_val |= (v & ((1ULL << channel->size) - 1)) << channel->shift;
+		clear_vals[0] = value->int32[0];
+		clear_vals[1] = value->int32[3];
+		break;
+	default:
+		fprintf(stderr, "failed to fast clear %d\n", format);
+		return false;
 	}
-
-	clear_vals[0] = clear_val;
-	clear_vals[1] = clear_val >> 32;
-
 	return true;
 }
 
@@ -1256,7 +1325,7 @@ VkResult radv_GetPhysicalDeviceImageFormatProperties2(
 			 *    vkGetPhysicalDeviceImageFormatProperties2KHR returns
 			 *    VK_ERROR_FORMAT_NOT_SUPPORTED.
 			 */
-			result = vk_errorf(physical_device->instance, VK_ERROR_FORMAT_NOT_SUPPORTED,
+			result = vk_errorf(VK_ERROR_FORMAT_NOT_SUPPORTED,
 					   "unsupported VkExternalMemoryTypeFlagBitsKHR 0x%x",
 					   external_info->handleType);
 			goto fail;

src/amd/vulkan/radv_icd.py

@@ -44,4 +44,4 @@ if __name__ == '__main__':
     }
 
     with open(args.out, 'w') as f:
-        json.dump(json_data, f, indent = 4, sort_keys=True, separators=(',', ': '))
+        json.dump(json_data, f, indent = 4, sort_keys=True)

src/amd/vulkan/radv_image.c

@@ -110,8 +110,6 @@ radv_use_dcc_for_image(struct radv_device *device,
 {
 	bool dcc_compatible_formats;
 	bool blendable;
-	bool shareable = vk_find_struct_const(pCreateInfo->pNext,
-	                                      EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
 
 	/* DCC (Delta Color Compression) is only available for GFX8+. */
 	if (device->physical_device->rad_info.chip_class < VI)
@@ -120,11 +118,6 @@ radv_use_dcc_for_image(struct radv_device *device,
 	if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
 		return false;
 
-	/* FIXME: DCC is broken for shareable images starting with GFX9 */
-	if (device->physical_device->rad_info.chip_class >= GFX9 &&
-	    shareable)
-		return false;
-
 	/* TODO: Enable DCC for storage images. */
 	if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
 	    (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
@@ -421,7 +414,7 @@ static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
 		else
 			return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
 	default:
-		unreachable("illegal image type");
+		unreachable("illegale image type");
 	}
 }
 
@@ -541,7 +534,7 @@ si_make_texture_descriptor(struct radv_device *device,
 	if (device->physical_device->rad_info.chip_class >= GFX9) {
 		unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
 
-		/* Depth is the last accessible layer on Gfx9.
+		/* Depth is the the last accessible layer on Gfx9.
 		 * The hw doesn't need to know the total number of layers.
 		 */
 		if (type == V_008F1C_SQ_RSRC_IMG_3D)
@@ -626,7 +619,7 @@ si_make_texture_descriptor(struct radv_device *device,
 			S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
 			S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
 			S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
-			S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
+			S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
 		fmask_state[4] = 0;
 		fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
 		fmask_state[6] = 0;
@@ -733,20 +726,56 @@ radv_image_get_fmask_info(struct radv_device *device,
 			  unsigned nr_samples,
 			  struct radv_fmask_info *out)
 {
+	/* FMASK is allocated like an ordinary texture. */
+	struct radeon_surf fmask = {};
+	struct ac_surf_info info = image->info;
+	memset(out, 0, sizeof(*out));
+
 	if (device->physical_device->rad_info.chip_class >= GFX9) {
-		out->alignment = image->surface.fmask_alignment;
-		out->size = image->surface.fmask_size;
-		out->tile_swizzle = image->surface.fmask_tile_swizzle;
+		out->alignment = image->surface.u.gfx9.fmask_alignment;
+		out->size = image->surface.u.gfx9.fmask_size;
 		return;
 	}
 
-	out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
-	out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
-	out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
-	out->bank_height = image->surface.u.legacy.fmask.bankh;
-	out->tile_swizzle = image->surface.fmask_tile_swizzle;
-	out->alignment = image->surface.fmask_alignment;
-	out->size = image->surface.fmask_size;
+	fmask.blk_w = image->surface.blk_w;
+	fmask.blk_h = image->surface.blk_h;
+	info.samples = 1;
+	fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
+
+	if (!image->shareable)
+		info.surf_index = &device->fmask_mrt_offset_counter;
+
+	/* Force 2D tiling if it wasn't set. This may occur when creating
+	 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
+	 * destination buffer must have an FMASK too. */
+	fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
+	fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+
+	switch (nr_samples) {
+	case 2:
+	case 4:
+		fmask.bpe = 1;
+		break;
+	case 8:
+		fmask.bpe = 4;
+		break;
+	default:
+		return;
+	}
+
+	device->ws->surface_init(device->ws, &info, &fmask);
+	assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
+
+	out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
+	if (out->slice_tile_max)
+		out->slice_tile_max -= 1;
+
+	out->tile_mode_index = fmask.u.legacy.tiling_index[0];
+	out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
+	out->bank_height = fmask.u.legacy.bankh;
+	out->tile_swizzle = fmask.tile_swizzle;
+	out->alignment = MAX2(256, fmask.surf_alignment);
+	out->size = fmask.surf_size;
 
 	assert(!out->tile_swizzle || !image->shareable);
 }
@@ -772,8 +801,8 @@ radv_image_get_cmask_info(struct radv_device *device,
 	unsigned cl_width, cl_height;
 
 	if (device->physical_device->rad_info.chip_class >= GFX9) {
-		out->alignment = image->surface.cmask_alignment;
-		out->size = image->surface.cmask_size;
+		out->alignment = image->surface.u.gfx9.cmask_alignment;
+		out->size = image->surface.u.gfx9.cmask_size;
 		return;
 	}
 
@@ -930,14 +959,13 @@ radv_image_create(VkDevice _device,
 	image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
 			   VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (!image)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	image->type = pCreateInfo->imageType;
 	image->info.width = pCreateInfo->extent.width;
 	image->info.height = pCreateInfo->extent.height;
 	image->info.depth = pCreateInfo->extent.depth;
 	image->info.samples = pCreateInfo->samples;
-	image->info.storage_samples = pCreateInfo->samples;
 	image->info.array_size = pCreateInfo->arrayLayers;
 	image->info.levels = pCreateInfo->mipLevels;
 	image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
@@ -1015,7 +1043,7 @@ radv_image_create(VkDevice _device,
 		                                      0, RADEON_FLAG_VIRTUAL);
 		if (!image->bo) {
 			vk_free2(&device->alloc, alloc, image);
-			return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
+			return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
 		}
 	}
 
@@ -1330,7 +1358,7 @@ radv_CreateImageView(VkDevice _device,
 	view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
 			   VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (view == NULL)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	radv_image_view_init(view, device, pCreateInfo);
 
@@ -1378,7 +1406,7 @@ radv_CreateBufferView(VkDevice _device,
 	view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
 			   VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 	if (!view)
-		return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+		return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
 	radv_buffer_view_init(view, device, pCreateInfo);
 

src/amd/vulkan/radv_llvm_helper.cpp

@@ -1,140 +0,0 @@
-/*
- * Copyright © 2018 Red Hat.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-#include "ac_llvm_util.h"
-#include "ac_llvm_build.h"
-#include "radv_shader_helper.h"
-
-#include <list>
-class radv_llvm_per_thread_info {
-public:
-	radv_llvm_per_thread_info(enum radeon_family arg_family,
-				enum ac_target_machine_options arg_tm_options)
-		: family(arg_family), tm_options(arg_tm_options) {}
-
-	~radv_llvm_per_thread_info()
-	{
-		ac_destroy_llvm_passes(passes);
-		ac_destroy_llvm_compiler(&llvm_info);
-	}
-
-	bool init(void)
-	{
-		if (!ac_init_llvm_compiler(&llvm_info,
-					  true,
-					  family,
-					  tm_options))
-			return false;
-
-		passes = ac_create_llvm_passes(llvm_info.tm);
-		if (!passes)
-			return false;
-
-		return true;
-	}
-
-	bool compile_to_memory_buffer(LLVMModuleRef module,
-				      struct ac_shader_binary *binary)
-	{
-		return ac_compile_module_to_binary(passes, module, binary);
-	}
-
-	bool is_same(enum radeon_family arg_family,
-		     enum ac_target_machine_options arg_tm_options) {
-		if (arg_family == family &&
-		    arg_tm_options == tm_options)
-			return true;
-		return false;
-	}
-	struct ac_llvm_compiler llvm_info;
-private:
-	enum radeon_family family;
-	enum ac_target_machine_options tm_options;
-	struct ac_compiler_passes *passes;
-};
-
-/* we have to store a linked list per thread due to the possiblity of multiple gpus being required */
-static thread_local std::list<radv_llvm_per_thread_info> radv_llvm_per_thread_list;
-
-bool radv_compile_to_binary(struct ac_llvm_compiler *info,
-			    LLVMModuleRef module,
-			    struct ac_shader_binary *binary)
-{
-	radv_llvm_per_thread_info *thread_info = nullptr;
-
-	for (auto &I : radv_llvm_per_thread_list) {
-		if (I.llvm_info.tm == info->tm) {
-			thread_info = &I;
-			break;
-		}
-	}
-
-	if (!thread_info) {
-		struct ac_compiler_passes *passes = ac_create_llvm_passes(info->tm);
-		bool ret = ac_compile_module_to_binary(passes, module, binary);
-		ac_destroy_llvm_passes(passes);
-		return ret;
-	}
-
-	return thread_info->compile_to_memory_buffer(module, binary);
-}
-
-bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
-			     bool okay_to_leak_target_library_info,
-			     bool thread_compiler,
-			     enum radeon_family family,
-			     enum ac_target_machine_options tm_options)
-{
-	if (thread_compiler) {
-		for (auto &I : radv_llvm_per_thread_list) {
-			if (I.is_same(family, tm_options)) {
-				*info = I.llvm_info;
-				return true;
-			}
-		}
-
-		radv_llvm_per_thread_list.emplace_back(family, tm_options);
-		radv_llvm_per_thread_info &tinfo = radv_llvm_per_thread_list.back();
-
-		if (!tinfo.init()) {
-			radv_llvm_per_thread_list.pop_back();
-			return false;
-		}
-
-		*info = tinfo.llvm_info;
-		return true;
-	}
-
-	if (!ac_init_llvm_compiler(info,
-				   okay_to_leak_target_library_info,
-				   family,
-				   tm_options))
-		return false;
-	return true;
-}
-
-void radv_destroy_llvm_compiler(struct ac_llvm_compiler *info,
-				bool thread_compiler)
-{
-	if (!thread_compiler)
-		ac_destroy_llvm_compiler(info);
-}

src/amd/vulkan/radv_meta.c

@@ -80,9 +80,10 @@ radv_meta_save(struct radv_meta_saved_state *state,
 	}
 
 	if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
-		state->old_descriptor_set0 = descriptors_state->sets[0];
-		if (!state->old_descriptor_set0)
-			state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
+		if (descriptors_state->valid & (1 << 0))
+			state->old_descriptor_set0 = descriptors_state->sets[0];
+		else
+			state->old_descriptor_set0 = NULL;
 	}
 
 	if (state->flags & RADV_META_SAVE_CONSTANTS) {
@@ -514,20 +515,18 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 	nir_ssa_def *tmp;
 	nir_if *outer_if = NULL;
 
-	nir_ssa_def *input_img_deref = &nir_build_deref_var(b, input_img)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
 	tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
 	tex->op = nir_texop_txf_ms;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(img_coord);
 	tex->src[1].src_type = nir_tex_src_ms_index;
 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(input_img_deref);
 	tex->dest_type = nir_type_float;
 	tex->is_array = false;
 	tex->coord_components = 2;
+	tex->texture = nir_deref_var_create(tex, input_img);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(b, &tex->instr);
@@ -535,16 +534,16 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 	tmp = &tex->dest.ssa;
 
 	if (!is_integer && samples > 1) {
-		nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 2);
+		nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 1);
 		tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
 		tex_all_same->op = nir_texop_samples_identical;
 		tex_all_same->src[0].src_type = nir_tex_src_coord;
 		tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
-		tex_all_same->src[1].src_type = nir_tex_src_texture_deref;
-		tex_all_same->src[1].src = nir_src_for_ssa(input_img_deref);
 		tex_all_same->dest_type = nir_type_float;
 		tex_all_same->is_array = false;
 		tex_all_same->coord_components = 2;
+		tex_all_same->texture = nir_deref_var_create(tex_all_same, input_img);
+		tex_all_same->sampler = NULL;
 
 		nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
 		nir_builder_instr_insert(b, &tex_all_same->instr);
@@ -556,18 +555,18 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 
 		b->cursor = nir_after_cf_list(&if_stmt->then_list);
 		for (int i = 1; i < samples; i++) {
-			nir_tex_instr *tex_add = nir_tex_instr_create(b->shader, 3);
+			nir_tex_instr *tex_add = nir_tex_instr_create(b->shader, 2);
 			tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
 			tex_add->op = nir_texop_txf_ms;
 			tex_add->src[0].src_type = nir_tex_src_coord;
 			tex_add->src[0].src = nir_src_for_ssa(img_coord);
 			tex_add->src[1].src_type = nir_tex_src_ms_index;
 			tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(b, i));
-			tex_add->src[2].src_type = nir_tex_src_texture_deref;
-			tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
 			tex_add->dest_type = nir_type_float;
 			tex_add->is_array = false;
 			tex_add->coord_components = 2;
+			tex_add->texture = nir_deref_var_create(tex_add, input_img);
+			tex_add->sampler = NULL;
 
 			nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
 			nir_builder_instr_insert(b, &tex_add->instr);

src/amd/vulkan/radv_meta.h

@@ -199,6 +199,10 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
 				 uint32_t region_count,
 				 const VkImageResolve *regions);
 
+void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
+			       struct radv_image *image,
+			       struct radv_image *linear_image);
+
 uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 			  struct radv_image *image, uint32_t value);
 uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,

src/amd/vulkan/radv_meta_blit.c

@@ -131,20 +131,16 @@ build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
 	sampler->data.descriptor_set = 0;
 	sampler->data.binding = 0;
 
-	nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
 	tex->sampler_dim = tex_dim;
 	tex->op = nir_texop_tex;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(tex_pos);
-	tex->src[1].src_type = nir_tex_src_texture_deref;
-	tex->src[1].src = nir_src_for_ssa(tex_deref);
-	tex->src[2].src_type = nir_tex_src_sampler_deref;
-	tex->src[2].src = nir_src_for_ssa(tex_deref);
 	tex->dest_type = nir_type_float; /* TODO */
 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
 	tex->coord_components = tex_pos->num_components;
+	tex->texture = nir_deref_var_create(tex, sampler);
+	tex->sampler = nir_deref_var_create(tex, sampler);
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
@@ -189,20 +185,16 @@ build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
 	sampler->data.descriptor_set = 0;
 	sampler->data.binding = 0;
 
-	nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
 	tex->sampler_dim = tex_dim;
 	tex->op = nir_texop_tex;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(tex_pos);
-	tex->src[1].src_type = nir_tex_src_texture_deref;
-	tex->src[1].src = nir_src_for_ssa(tex_deref);
-	tex->src[2].src_type = nir_tex_src_sampler_deref;
-	tex->src[2].src = nir_src_for_ssa(tex_deref);
 	tex->dest_type = nir_type_float; /* TODO */
 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
 	tex->coord_components = tex_pos->num_components;
+	tex->texture = nir_deref_var_create(tex, sampler);
+	tex->sampler = nir_deref_var_create(tex, sampler);
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
@@ -247,20 +239,16 @@ build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
 	sampler->data.descriptor_set = 0;
 	sampler->data.binding = 0;
 
-	nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
 	tex->sampler_dim = tex_dim;
 	tex->op = nir_texop_tex;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(tex_pos);
-	tex->src[1].src_type = nir_tex_src_texture_deref;
-	tex->src[1].src = nir_src_for_ssa(tex_deref);
-	tex->src[2].src_type = nir_tex_src_sampler_deref;
-	tex->src[2].src = nir_src_for_ssa(tex_deref);
 	tex->dest_type = nir_type_float; /* TODO */
 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
 	tex->coord_components = tex_pos->num_components;
+	tex->texture = nir_deref_var_create(tex, sampler);
+	tex->sampler = nir_deref_var_create(tex, sampler);
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
@@ -520,7 +508,6 @@ void radv_CmdBlitImage(
 	RADV_FROM_HANDLE(radv_image, src_image, srcImage);
 	RADV_FROM_HANDLE(radv_image, dest_image, destImage);
 	struct radv_meta_saved_state saved_state;
-	bool old_predicating;
 
 	/* From the Vulkan 1.0 spec:
 	 *
@@ -535,12 +522,6 @@ void radv_CmdBlitImage(
 		       RADV_META_SAVE_CONSTANTS |
 		       RADV_META_SAVE_DESCRIPTORS);
 
-	/* VK_EXT_conditional_rendering says that blit commands should not be
-	 * affected by conditional rendering.
-	 */
-	old_predicating = cmd_buffer->state.predicating;
-	cmd_buffer->state.predicating = false;
-
 	for (unsigned r = 0; r < regionCount; r++) {
 		const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
 		const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
@@ -655,9 +636,6 @@ void radv_CmdBlitImage(
 		}
 	}
 
-	/* Restore conditional rendering. */
-	cmd_buffer->state.predicating = old_predicating;
-
 	radv_meta_restore(&saved_state, cmd_buffer);
 }
 

src/amd/vulkan/radv_meta_blit2d.c

@@ -485,25 +485,22 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
 		nir_ssa_dest_init(&sample_idx->instr, &sample_idx->dest, 1, 32, "sample_idx");
 		nir_builder_instr_insert(b, &sample_idx->instr);
 	}
-
-	nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b->shader, is_multisampled ? 4 : 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b->shader, is_multisampled ? 3 : 2);
 	tex->sampler_dim = dim;
 	tex->op = is_multisampled ? nir_texop_txf_ms : nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
 	tex->src[1].src_type = is_multisampled ? nir_tex_src_ms_index : nir_tex_src_lod;
 	tex->src[1].src = nir_src_for_ssa(is_multisampled ? &sample_idx->dest.ssa : nir_imm_int(b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(tex_deref);
 	if (is_multisampled) {
-		tex->src[3].src_type = nir_tex_src_lod;
-		tex->src[3].src = nir_src_for_ssa(nir_imm_int(b, 0));
+		tex->src[2].src_type = nir_tex_src_lod;
+		tex->src[2].src = nir_src_for_ssa(nir_imm_int(b, 0));
 	}
 	tex->dest_type = nir_type_uint;
 	tex->is_array = false;
 	tex->coord_components = is_3d ? 3 : 2;
+	tex->texture = nir_deref_var_create(tex, sampler);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(b, &tex->instr);
@@ -537,18 +534,16 @@ build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
 	pos_x = nir_iadd(b, pos_x, pos_y);
 	//pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
 
-	nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
+	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
 	tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
 	tex->op = nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(pos_x);
-	tex->src[1].src_type = nir_tex_src_texture_deref;
-	tex->src[1].src = nir_src_for_ssa(tex_deref);
 	tex->dest_type = nir_type_uint;
 	tex->is_array = false;
 	tex->coord_components = 1;
+	tex->texture = nir_deref_var_create(tex, sampler);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(b, &tex->instr);
@@ -608,7 +603,8 @@ build_nir_copy_fragment_shader(struct radv_device *device,
 	}
 
 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
-	nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
+	unsigned swiz[4] = { 0, 1 };
+	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
 
 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
 	nir_store_var(&b, color_out, color, 0xf);
@@ -641,7 +637,8 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,
 	}
 
 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
-	nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
+	unsigned swiz[4] = { 0, 1 };
+	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
 
 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
 	nir_store_var(&b, color_out, color, 0x1);
@@ -674,7 +671,8 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device,
 	}
 
 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
-	nir_ssa_def *tex_pos = nir_channels(&b, pos_int, 0x3);
+	unsigned swiz[4] = { 0, 1 };
+	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
 
 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
 	nir_store_var(&b, color_out, color, 0x1);

src/amd/vulkan/radv_meta_buffer.c

@@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev)
 	nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
 
 	nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
-	offset = nir_channel(&b, offset, 0);
+	offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
 
 	nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
 	                                                          nir_intrinsic_vulkan_resource_index);
@@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev)
 	nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
 
 	nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
-	offset = nir_channel(&b, offset, 0);
+	offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
 
 	nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
 	                                                          nir_intrinsic_vulkan_resource_index);
@@ -415,7 +415,7 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 	} else if (size) {
 		uint64_t va = radv_buffer_get_va(bo);
 		va += offset;
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo, 8);
 		si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
 	}
 
@@ -438,8 +438,8 @@ void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
 		src_va += src_offset;
 		dst_va += dst_offset;
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo);
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo, 8);
 
 		si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
 	}
@@ -472,13 +472,6 @@ void radv_CmdCopyBuffer(
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 	RADV_FROM_HANDLE(radv_buffer, src_buffer, srcBuffer);
 	RADV_FROM_HANDLE(radv_buffer, dest_buffer, destBuffer);
-	bool old_predicating;
-
-	/* VK_EXT_conditional_rendering says that copy commands should not be
-	 * affected by conditional rendering.
-	 */
-	old_predicating = cmd_buffer->state.predicating;
-	cmd_buffer->state.predicating = false;
 
 	for (unsigned r = 0; r < regionCount; r++) {
 		uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
@@ -488,9 +481,6 @@ void radv_CmdCopyBuffer(
 		radv_copy_buffer(cmd_buffer, src_buffer->bo, dest_buffer->bo,
 				 src_offset, dest_offset, copy_size);
 	}
-
-	/* Restore conditional rendering. */
-	cmd_buffer->state.predicating = old_predicating;
 }
 
 void radv_CmdUpdateBuffer(
@@ -516,7 +506,7 @@ void radv_CmdUpdateBuffer(
 	if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) {
 		si_emit_cache_flush(cmd_buffer);
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo, 8);
 
 		radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
 

src/amd/vulkan/radv_meta_bufimage.c

@@ -88,20 +88,18 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
 	nir_builder_instr_insert(&b, &stride->instr);
 
 	nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
-	nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
-
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
 	tex->sampler_dim = dim;
 	tex->op = nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(nir_channels(&b, img_coord, is_3d ? 0x7 : 0x3));
 	tex->src[1].src_type = nir_tex_src_lod;
 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(input_img_deref);
 	tex->dest_type = nir_type_float;
 	tex->is_array = false;
 	tex->coord_components = is_3d ? 3 : 2;
+	tex->texture = nir_deref_var_create(tex, input_img);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
@@ -115,11 +113,11 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
 	nir_ssa_def *coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
 
 	nir_ssa_def *outval = &tex->dest.ssa;
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(coord);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(outval);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(coord);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(outval);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;
@@ -322,30 +320,29 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
 	nir_ssa_def *buf_coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
 
 	nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
-	nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
 
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
 	tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
 	tex->op = nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(nir_channels(&b, buf_coord, 1));
 	tex->src[1].src_type = nir_tex_src_lod;
 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(input_img_deref);
 	tex->dest_type = nir_type_float;
 	tex->is_array = false;
 	tex->coord_components = 1;
+	tex->texture = nir_deref_var_create(tex, input_img);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
 
 	nir_ssa_def *outval = &tex->dest.ssa;
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(img_coord);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(outval);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(img_coord);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(outval);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;
@@ -535,32 +532,31 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
 	nir_builder_instr_insert(&b, &dst_offset->instr);
 
 	nir_ssa_def *src_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa);
-	nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
 
 	nir_ssa_def *dst_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
 
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
 	tex->sampler_dim = dim;
 	tex->op = nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, is_3d ? 0x7 : 0x3));
 	tex->src[1].src_type = nir_tex_src_lod;
 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(input_img_deref);
 	tex->dest_type = nir_type_float;
 	tex->is_array = false;
 	tex->coord_components = is_3d ? 3 : 2;
+	tex->texture = nir_deref_var_create(tex, input_img);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
 
 	nir_ssa_def *outval = &tex->dest.ssa;
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(dst_coord);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(outval);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(dst_coord);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(outval);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;
@@ -752,11 +748,11 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
 	comps[3] = nir_imm_int(&b, 0);
 	global_id = nir_vec(&b, comps, 4);
 
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(global_id);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(&clear_val->dest.ssa);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(global_id);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(&clear_val->dest.ssa);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;

src/amd/vulkan/radv_meta_clear.c

@@ -366,10 +366,10 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 
 	struct radv_subpass clear_subpass = {
 		.color_count = 1,
-		.color_attachments = (struct radv_subpass_attachment[]) {
+		.color_attachments = (VkAttachmentReference[]) {
 			subpass->color_attachments[clear_att->colorAttachment]
 		},
-		.depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
+		.depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
 	};
 
 	radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
@@ -645,8 +645,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 	if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 	                              subpass->depth_stencil_attachment.layout,
 	                              clear_rect, clear_value))
-		radv_update_ds_clear_metadata(cmd_buffer, iview->image,
-					      clear_value, aspects);
+		radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
 
 	radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 			.x = clear_rect->rect.offset.x,
@@ -745,7 +744,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
 				      iview->image->offset + iview->image->htile_offset,
 				      iview->image->surface.htile_size, clear_word);
 
-	radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
+	radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
 	if (post_flush) {
 		*post_flush |= flush_bits;
 	} else {
@@ -994,7 +993,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 	const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 	const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
 	VkClearColorValue clear_value = clear_att->clearValue.color;
-	uint32_t clear_color[2], flush_bits = 0;
+	uint32_t clear_color[2], flush_bits;
 	uint32_t cmask_clear_value;
 	bool ret;
 
@@ -1020,6 +1019,8 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 	if (iview->image->info.levels > 1)
 		goto fail;
 
+	if (iview->image->surface.is_linear)
+		goto fail;
 	if (!radv_image_extent_compare(iview->image, &iview->extent))
 		goto fail;
 
@@ -1089,7 +1090,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 		if (!can_avoid_fast_clear_elim)
 			need_decompress_pass = true;
 
-		flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
+		flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
 
 		radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
 						  need_decompress_pass);
@@ -1104,8 +1105,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
 		cmd_buffer->state.flush_bits |= flush_bits;
 	}
 
-	radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
-					 clear_color);
+	radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
 
 	return true;
 fail:

src/amd/vulkan/radv_meta_copy.c

@@ -72,7 +72,6 @@ vk_format_for_size(int bs)
 	case 2: return VK_FORMAT_R8G8_UINT;
 	case 4: return VK_FORMAT_R8G8B8A8_UINT;
 	case 8: return VK_FORMAT_R16G16B16A16_UINT;
-	case 12: return VK_FORMAT_R32G32B32_UINT;
 	case 16: return VK_FORMAT_R32G32B32A32_UINT;
 	default:
 		unreachable("Invalid format block size");
@@ -117,7 +116,6 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
 {
 	bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
 	struct radv_meta_saved_state saved_state;
-	bool old_predicating;
 
 	/* The Vulkan 1.0 spec says "dstImage must have a sample count equal to
 	 * VK_SAMPLE_COUNT_1_BIT."
@@ -130,12 +128,6 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
 		       RADV_META_SAVE_CONSTANTS |
 		       RADV_META_SAVE_DESCRIPTORS);
 
-	/* VK_EXT_conditional_rendering says that copy commands should not be
-	 * affected by conditional rendering.
-	 */
-	old_predicating = cmd_buffer->state.predicating;
-	cmd_buffer->state.predicating = false;
-
 	for (unsigned r = 0; r < regionCount; r++) {
 
 		/**
@@ -215,9 +207,6 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
 		}
 	}
 
-	/* Restore conditional rendering. */
-	cmd_buffer->state.predicating = old_predicating;
-
 	radv_meta_restore(&saved_state, cmd_buffer);
 }
 
@@ -246,19 +235,12 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
                           const VkBufferImageCopy* pRegions)
 {
 	struct radv_meta_saved_state saved_state;
-	bool old_predicating;
 
 	radv_meta_save(&saved_state, cmd_buffer,
 		       RADV_META_SAVE_COMPUTE_PIPELINE |
 		       RADV_META_SAVE_CONSTANTS |
 		       RADV_META_SAVE_DESCRIPTORS);
 
-	/* VK_EXT_conditional_rendering says that copy commands should not be
-	 * affected by conditional rendering.
-	 */
-	old_predicating = cmd_buffer->state.predicating;
-	cmd_buffer->state.predicating = false;
-
 	for (unsigned r = 0; r < regionCount; r++) {
 
 		/**
@@ -330,9 +312,6 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
 		}
 	}
 
-	/* Restore conditional rendering. */
-	cmd_buffer->state.predicating = old_predicating;
-
 	radv_meta_restore(&saved_state, cmd_buffer);
 }
 
@@ -364,7 +343,6 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
 {
 	bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
 	struct radv_meta_saved_state saved_state;
-	bool old_predicating;
 
 	/* From the Vulkan 1.0 spec:
 	 *
@@ -379,12 +357,6 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
 		       RADV_META_SAVE_CONSTANTS |
 		       RADV_META_SAVE_DESCRIPTORS);
 
-	/* VK_EXT_conditional_rendering says that copy commands should not be
-	 * affected by conditional rendering.
-	 */
-	old_predicating = cmd_buffer->state.predicating;
-	cmd_buffer->state.predicating = false;
-
 	for (unsigned r = 0; r < regionCount; r++) {
 		assert(pRegions[r].srcSubresource.aspectMask ==
 		       pRegions[r].dstSubresource.aspectMask);
@@ -492,9 +464,6 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
 		}
 	}
 
-	/* Restore conditional rendering. */
-	cmd_buffer->state.predicating = old_predicating;
-
 	radv_meta_restore(&saved_state, cmd_buffer);
 }
 
@@ -516,3 +485,24 @@ void radv_CmdCopyImage(
 			dest_image, destImageLayout,
 			regionCount, pRegions);
 }
+
+void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
+			       struct radv_image *image,
+			       struct radv_image *linear_image)
+{
+	struct VkImageCopy image_copy = { 0 };
+
+	image_copy.srcSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+	image_copy.srcSubresource.layerCount = 1;
+
+	image_copy.dstSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+	image_copy.dstSubresource.layerCount = 1;
+
+	image_copy.extent.width = image->info.width;
+	image_copy.extent.height = image->info.height;
+	image_copy.extent.depth = 1;
+
+	meta_copy_image(cmd_buffer, image, VK_IMAGE_LAYOUT_GENERAL, linear_image,
+			VK_IMAGE_LAYOUT_GENERAL,
+			1, &image_copy);
+}

src/amd/vulkan/radv_meta_fast_clear.c

@@ -66,20 +66,19 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
 						b.shader->info.cs.local_size[2], 0);
 
 	nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
-	nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
 
-	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
+	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
 	tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
 	tex->op = nir_texop_txf;
 	tex->src[0].src_type = nir_tex_src_coord;
 	tex->src[0].src = nir_src_for_ssa(nir_channels(&b, global_id, 3));
 	tex->src[1].src_type = nir_tex_src_lod;
 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
-	tex->src[2].src_type = nir_tex_src_texture_deref;
-	tex->src[2].src = nir_src_for_ssa(input_img_deref);
 	tex->dest_type = nir_type_float;
 	tex->is_array = false;
 	tex->coord_components = 2;
+	tex->texture = nir_deref_var_create(tex, input_img);
+	tex->sampler = NULL;
 
 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
 	nir_builder_instr_insert(&b, &tex->instr);
@@ -91,11 +90,11 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
 	nir_builder_instr_insert(&b, &bar->instr);
 
 	nir_ssa_def *outval = &tex->dest.ssa;
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(global_id);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(outval);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(global_id);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(outval);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;
@@ -571,7 +570,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
 		va += image->dcc_pred_offset;
 	}
 
-	si_emit_set_predication_state(cmd_buffer, true, va);
+	si_emit_set_predication_state(cmd_buffer, va);
 }
 
 /**
@@ -586,7 +585,6 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 	VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
 	VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 	uint32_t layer_count = radv_get_layerCount(image, subresourceRange);
-	bool old_predicating = false;
 	VkPipeline pipeline;
 
 	assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
@@ -603,9 +601,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
                pipeline = cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
 	}
 
-	if (radv_image_has_dcc(image)) {
-		old_predicating = cmd_buffer->state.predicating;
-
+	if (!decompress_dcc && radv_image_has_dcc(image)) {
 		radv_emit_set_predication_state_from_image(cmd_buffer, image, true);
 		cmd_buffer->state.predicating = true;
 	}
@@ -671,22 +667,9 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 					&cmd_buffer->pool->alloc);
 
 	}
-	if (radv_image_has_dcc(image)) {
-		cmd_buffer->state.predicating = old_predicating;
-
+	if (!decompress_dcc && radv_image_has_dcc(image)) {
+		cmd_buffer->state.predicating = false;
 		radv_emit_set_predication_state_from_image(cmd_buffer, image, false);
-
-		/* Clear the image's fast-clear eliminate predicate because
-		 * FMASK and DCC also imply a fast-clear eliminate.
-		 */
-		radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
-
-		if (cmd_buffer->state.predication_type != -1) {
-			/* Restore previous conditional rendering user state. */
-			si_emit_set_predication_state(cmd_buffer,
-						      cmd_buffer->state.predication_type,
-						      cmd_buffer->state.predication_va);
-		}
 	}
 	radv_meta_restore(&saved_state, cmd_buffer);
 }

src/amd/vulkan/radv_meta_resolve.c

@@ -613,8 +613,8 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
 		return;
 
 	for (uint32_t i = 0; i < subpass->color_count; ++i) {
-		struct radv_subpass_attachment src_att = subpass->color_attachments[i];
-		struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
+		VkAttachmentReference src_att = subpass->color_attachments[i];
+		VkAttachmentReference dest_att = subpass->resolve_attachments[i];
 
 		if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
 		    dest_att.attachment == VK_ATTACHMENT_UNUSED)
@@ -641,8 +641,8 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
 		       RADV_META_SAVE_GRAPHICS_PIPELINE);
 
 	for (uint32_t i = 0; i < subpass->color_count; ++i) {
-		struct radv_subpass_attachment src_att = subpass->color_attachments[i];
-		struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
+		VkAttachmentReference src_att = subpass->color_attachments[i];
+		VkAttachmentReference dest_att = subpass->resolve_attachments[i];
 
 		if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
 		    dest_att.attachment == VK_ATTACHMENT_UNUSED)
@@ -657,7 +657,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
 
 		struct radv_subpass resolve_subpass = {
 			.color_count = 2,
-			.color_attachments = (struct radv_subpass_attachment[]) { src_att, dest_att },
+			.color_attachments = (VkAttachmentReference[]) { src_att, dest_att },
 			.depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
 		};
 
@@ -684,8 +684,8 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
 	struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 
 	for (uint32_t i = 0; i < subpass->color_count; ++i) {
-		struct radv_subpass_attachment src_att = subpass->color_attachments[i];
-		struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
+		VkAttachmentReference src_att = subpass->color_attachments[i];
+		VkAttachmentReference dest_att = subpass->resolve_attachments[i];
 
 		if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
 		    dest_att.attachment == VK_ATTACHMENT_UNUSED)

src/amd/vulkan/radv_meta_resolve_cs.c

@@ -135,11 +135,11 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
 		outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
 
 	nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
-	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
-	store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
-	store->src[1] = nir_src_for_ssa(coord);
-	store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
-	store->src[3] = nir_src_for_ssa(outval);
+	nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store);
+	store->src[0] = nir_src_for_ssa(coord);
+	store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+	store->src[2] = nir_src_for_ssa(outval);
+	store->variables[0] = nir_deref_var_create(store, output_img);
 	nir_builder_instr_insert(&b, &store->instr);
 	return b.shader;
 }
@@ -473,15 +473,25 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
 	struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 	const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 	struct radv_meta_saved_state saved_state;
-	struct radv_subpass_barrier barrier;
-
-	/* Resolves happen before the end-of-subpass barriers get executed, so
-	 * we have to make the attachment shader-readable.
+	/* FINISHME(perf): Skip clears for resolve attachments.
+	 *
+	 * From the Vulkan 1.0 spec:
+	 *
+	 *    If the first use of an attachment in a render pass is as a resolve
+	 *    attachment, then the loadOp is effectively ignored as the resolve is
+	 *    guaranteed to overwrite all pixels in the render area.
 	 */
-	barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
-	barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
-	barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
-	radv_subpass_barrier(cmd_buffer, &barrier);
+
+	if (!subpass->has_resolve)
+		return;
+
+	/* Resolves happen before the end-of-subpass barriers get executed,
+	 * so we have to make the attachment shader-readable */
+	cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
+	                                RADV_CMD_FLAG_INV_GLOBAL_L2 |
+	                                RADV_CMD_FLAG_INV_VMEM_L1;
 
 	radv_decompress_resolve_subpass_src(cmd_buffer);
 
@@ -491,8 +501,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
 		       RADV_META_SAVE_DESCRIPTORS);
 
 	for (uint32_t i = 0; i < subpass->color_count; ++i) {
-		struct radv_subpass_attachment src_att = subpass->color_attachments[i];
-		struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
+		VkAttachmentReference src_att = subpass->color_attachments[i];
+		VkAttachmentReference dest_att = subpass->resolve_attachments[i];
 		struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
 		struct radv_image_view *dst_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
 		if (dest_att.attachment == VK_ATTACHMENT_UNUSED)

src/amd/vulkan/radv_meta_resolve_fs.c

@@ -580,25 +580,39 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
 	struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 	const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 	struct radv_meta_saved_state saved_state;
-	struct radv_subpass_barrier barrier;
 
-	/* Resolves happen before the end-of-subpass barriers get executed,
-	 * so we have to make the attachment shader-readable */
-	barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
-	barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
-	barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
-	radv_subpass_barrier(cmd_buffer, &barrier);
+	/* FINISHME(perf): Skip clears for resolve attachments.
+	 *
+	 * From the Vulkan 1.0 spec:
+	 *
+	 *    If the first use of an attachment in a render pass is as a resolve
+	 *    attachment, then the loadOp is effectively ignored as the resolve is
+	 *    guaranteed to overwrite all pixels in the render area.
+	 */
 
-	radv_decompress_resolve_subpass_src(cmd_buffer);
+	if (!subpass->has_resolve)
+		return;
 
 	radv_meta_save(&saved_state, cmd_buffer,
 		       RADV_META_SAVE_GRAPHICS_PIPELINE |
 		       RADV_META_SAVE_CONSTANTS |
 		       RADV_META_SAVE_DESCRIPTORS);
 
+	/* Resolves happen before the end-of-subpass barriers get executed,
+	 * so we have to make the attachment shader-readable */
+	cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_DB |
+	                                RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
+	                                RADV_CMD_FLAG_INV_GLOBAL_L2 |
+	                                RADV_CMD_FLAG_INV_VMEM_L1;
+
+	radv_decompress_resolve_subpass_src(cmd_buffer);
+
 	for (uint32_t i = 0; i < subpass->color_count; ++i) {
-		struct radv_subpass_attachment src_att = subpass->color_attachments[i];
-		struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
+		VkAttachmentReference src_att = subpass->color_attachments[i];
+		VkAttachmentReference dest_att = subpass->resolve_attachments[i];
 
 		if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
 		    dest_att.attachment == VK_ATTACHMENT_UNUSED)
@@ -609,7 +623,7 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
 
 		struct radv_subpass resolve_subpass = {
 			.color_count = 1,
-			.color_attachments = (struct radv_subpass_attachment[]) { dest_att },
+			.color_attachments = (VkAttachmentReference[]) { dest_att },
 			.depth_stencil_attachment = { .attachment = VK_ATTACHMENT_UNUSED },
 		};