docs: Add mesa 19.0.8 sha256 sums

docs: Add docs for 19.0.8
version: bump to 19.0.8
2019-06-26 13:42:45 -07:00 · 2019-06-26 13:08:54 -07:00 · 2019-06-26 09:43:56 -07:00 · 2019-06-26 09:42:49 -07:00 · 2019-06-24 16:21:34 -07:00 · 2019-06-24 14:56:04 -07:00
151 changed files with 1934 additions and 684 deletions
--- a/2
+++ b/2
@@ -1 +1 @@
-19.0.3
+19.0.8
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -14,4 +14,34 @@ b031c643491a92a5574c7a4bd659df33f2d89bb6
 5c30fffeec1732c21d600c036f95f8cdb1bb5487

 # This doesn't actually appliy to 19.0
-29179f58c6ba8099859ea25900214dbbd3814a92
+29179f58c6ba8099859ea25900214dbbd3814a92
+
+# This was superceeded by a manual backport from ken
+6981069fc805da1afc867ca3c905075d146d7ff9
+
+# This was manually backported
+0bc1942c9ddce4e796322a7561f06af5dec0decd
+
+# This doesn't need to be applied, it already seems to exist in stable.
+80dc78407d0d1e03ceddf8889b217e8fd113568d
+
+# This was backported manually
+4f18c43d1df64135e8968a7d4fbfd2c9918b76ae
+
+# These were de-nominated since they don't apply nicley
+88105375c978f9de82af8c654051e5aa16d61614
+c9358621276ae49162e58d4a16fe37abda6a347f
+
+# These are only for 19.1
+c3538ab5702ceeead284c2b5f9e700f3082c8135
+d2aa65eb1892f7b300ac24560f9dbda6b600b5a7
+78e35df52aa2f7d770f929a0866a0faa89c261a9
+0f1b070bad34c46c4bcc6c679fa533bf6b4b79e5
+ad2b4aa37806779bdfc15d704940136c3db21eb4
+9dc57eebd578b976b94c54d083377ba0920d43a8
+5820ac6756898a1bd30bde04555437a55c378726
+ffd2f948fee271cbbce93708fc508dab7cb5d14c
+
+# This was manually rebased and the script doesn't understand that for some
+# reason
+cb7c9b2a9352cc73a2d3becc0427c53c8baf153a
--- a/configure.ac
+++ b/configure.ac
@@ -2357,7 +2357,7 @@ if test "x$enable_xvmc" = xyes -o \
        "x$enable_omx_tizonia" = xyes -o \
        "x$enable_va" = xyes; then
    if echo $platforms | grep -q "x11"; then
-        PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED])
+        PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED libdrm >= $LIBDRM_REQUIRED])
    fi
    need_gallium_vl_winsys=yes
 fi
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -338,6 +338,9 @@ See src/mesa/state_tracker/st_debug.c for other options.
 for details.
 <li>SVGA_EXTRA_LOGGING - if set, enables extra logging to the vmware.log file,
 such as the OpenGL program's name and command line arguments.
+<li>SVGA_NO_LOGGING - if set, disables logging to the vmware.log file.
+This is useful when using Valgrind because it otherwise crashes when
+initializing the host log feature.
 <li>See the driver code for other, lesser-used variables.
 </ul>

--- a/docs/relnotes/19.0.3.html
+++ b/docs/relnotes/19.0.3.html
@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.

 <h2>SHA256 checksums</h2>
 <pre>
-TBD
+59543ec3c9f8c72990e77887f13d1678cb6739e5d5f56abc21ebf9e772389c5e  mesa-19.0.3.tar.gz
+f027244e38dc309a4c12db45ef79be81ab62c797a50a88d566e4edb6159fc4d5  mesa-19.0.3.tar.xz
 </pre>


--- a/docs/relnotes/19.0.4.html
+++ b/docs/relnotes/19.0.4.html
@@ -0,0 +1,243 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.4 Release Notes / May 9, 2019</h1>
+
+<p>
+Mesa 19.0.4 is a bug fix release which fixes bugs found since the 19.0.3 release.
+</p>
+<p>
+Mesa 19.0.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+de361c76bf7aae09219f571b9ae77a34864a1cd9f6ba24c845b18b3cd5e4b9a2  mesa-19.0.4.tar.gz
+39f9f32f448d77388ef817c6098d50eb0c1595815ce7e895dec09dd68774ce47  mesa-19.0.4.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>N/A</p>
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99781">Bug 99781</a> - Some Unity games fail assertion on startup in glXCreateContextAttribsARB</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100239">Bug 100239</a> - Incorrect rendering in CS:GO</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108540">Bug 108540</a> - vkAcquireNextImageKHR blocks when timeout=0 in Wayland</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110143">Bug 110143</a> - Doom 3: BFG Edition - Steam and GOG.com - white flickering screen</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110291">Bug 110291</a> - Vega 64 GPU hang running Space Engineers</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110355">Bug 110355</a> - radeonsi: GTK elements become invisible in some applications (GIMP, LibreOffice)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110573">Bug 110573</a> - Mesa vulkan-radeon 19.0.3 system freeze and visual artifacts (RADV)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110590">Bug 110590</a> - [Regression][Bisected] GTAⅣ under wine fails with GLXBadFBConfig</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110632">Bug 110632</a> - &quot;glx: Fix synthetic error generation in __glXSendError&quot; broke wine games on 32-bit</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Alejandro Piñeiro (1):</p>
+<ul>
+  <li>docs: document MESA_GLSL=errors keyword</li>
+</ul>
+
+<p>Andrii Simiklit (1):</p>
+<ul>
+  <li>egl: return correct error code for a case req ver &lt; 3 with forward-compatible</li>
+</ul>
+
+<p>Axel Davy (1):</p>
+<ul>
+  <li>st/nine: Fix D3DWindowBuffer_release for old wine nine support</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+  <li>radv: Disable VK_EXT_descriptor_indexing.</li>
+</ul>
+
+<p>Brian Paul (1):</p>
+<ul>
+  <li>svga: add SVGA_NO_LOGGING env var (v2)</li>
+</ul>
+
+<p>Caio Marcelo de Oliveira Filho (1):</p>
+<ul>
+  <li>spirv: Handle SpvOpDecorateId</li>
+</ul>
+
+<p>Charmaine Lee (1):</p>
+<ul>
+  <li>svga: move host logging to winsys</li>
+</ul>
+
+<p>Chuck Atkins (1):</p>
+<ul>
+  <li>meson: Fix missing glproto dependency for gallium-glx</li>
+</ul>
+
+<p>Daniel Stone (1):</p>
+<ul>
+  <li>vulkan/wsi/wayland: Respect non-blocking AcquireNextImage</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+  <li>r600: reset tex array override even when no view bound</li>
+  <li>util/bitset: fix bitset range mask calculations.</li>
+</ul>
+
+<p>Dylan Baker (7):</p>
+<ul>
+  <li>docs: Add SHA256 sums for mesa 19.0.3</li>
+  <li>cherry-ignore: Add a patch that was manually backported</li>
+  <li>cherry-ignore: Add more backported patches</li>
+  <li>cherry-ignore: Add another patch</li>
+  <li>cherry-ignore: Add more patches</li>
+  <li>meson: Force the use of config-tool for llvm</li>
+  <li>VERSION: bump for 19.0.4 release</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+  <li>vulkan/wsi: check if the display_fd given is master</li>
+  <li>vulkan/wsi: don't use DUMB_CLOSE for normal GEM handles</li>
+  <li>configure.ac: check for libdrm when using VL with X11</li>
+</ul>
+
+<p>Erik Faye-Lund (2):</p>
+<ul>
+  <li>softpipe: setup pixel_offset for all primitive types</li>
+  <li>draw: flush when setting stream-out targets</li>
+</ul>
+
+<p>Francisco Jerez (2):</p>
+<ul>
+  <li>intel/fs: Lower integer multiply correctly when destination stride equals 4.</li>
+  <li>intel/fs: Cap dst-aligned region stride to maximum representable hstride value.</li>
+</ul>
+
+<p>Hal Gentz (1):</p>
+<ul>
+  <li>glx: Fix synthetic error generation in __glXSendError</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+  <li>glsl: Silence may unused parameter warnings in glsl/ir.h</li>
+  <li>mesa: Add missing display list support for GL_FOG_COORDINATE_SOURCE</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+  <li>anv/descriptor_set: Destroy sets before pool finalization</li>
+</ul>
+
+<p>Jon Turney (1):</p>
+<ul>
+  <li>meson: Force '.so' extension for DRI drivers</li>
+</ul>
+
+<p>Juan A. Suarez Romero (2):</p>
+<ul>
+  <li>spirv: add missing SPV_EXT_descriptor_indexing capabilities</li>
+  <li>radv: enable descriptor indexing capabilities</li>
+</ul>
+
+<p>Kenneth Graunke (6):</p>
+<ul>
+  <li>glsl: Allow gl_nir_lower_samplers*() without a gl_shader_program</li>
+  <li>glsl: Don't look at sampler uniform storage for internal vars</li>
+  <li>i965: Ignore uniform storage for samplers or images, use binding info</li>
+  <li>i965: Fix BRW_MEMZONE_LOW_4G heap size.</li>
+  <li>i965: Force VMA alignment to be a multiple of the page size.</li>
+  <li>i965: leave the top 4Gb of the high heap VMA unused</li>
+</ul>
+
+<p>Lionel Landwerlin (4):</p>
+<ul>
+  <li>anv: store heap address bounds when initializing physical device</li>
+  <li>anv: leave the top 4Gb of the high heap VMA unused</li>
+  <li>anv: fix argument name for vkCmdEndQuery</li>
+  <li>anv: rework queries writes to ensure ordering memory writes</li>
+</ul>
+
+<p>Marek Olšák (2):</p>
+<ul>
+  <li>radeonsi/gfx9: set that window_rectangles always roll the context</li>
+  <li>radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+  <li>radeonsi: add si_debug_options for convenient adding/removing of options</li>
+</ul>
+
+<p>Rhys Perry (1):</p>
+<ul>
+  <li>radv: fix set_output_usage_mask() with composite and 64-bit types</li>
+</ul>
+
+<p>Ross Burton (1):</p>
+<ul>
+  <li>Revert "meson: drop GLESv1 .so version back to 1.0.0"</li>
+</ul>
+
+<p>Samuel Pitoiset (8):</p>
+<ul>
+  <li>radv: add missing VEGA20 chip in radv_get_device_name()</li>
+  <li>radv: do not need to force emit the TCS regs on Vega20</li>
+  <li>radv: fix color conversions for normalized uint/sint formats</li>
+  <li>radv: implement a workaround for VK_EXT_conditional_rendering</li>
+  <li>radv: set WD_SWITCH_ON_EOP=1 when drawing primitives from a stream output buffer</li>
+  <li>radv: only need to force emit the TCS regs on Vega10 and Raven1</li>
+  <li>radv: apply the indexing workaround for atomic buffer operations on GFX9</li>
+  <li>radv: fix setting the number of rectangles when it's dyanmic</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+  <li>anv: expose VK_EXT_queue_family_foreign on Android</li>
+</ul>
+
+<p>Timothy Arceri (4):</p>
+<ul>
+  <li>nir: fix nir_remove_unused_varyings()</li>
+  <li>util/drirc: add workarounds for bugs in Doom 3: BFG</li>
+  <li>radeonsi: add config entry for Counter-Strike Global Offensive</li>
+  <li>Revert "glx: Fix synthetic error generation in __glXSendError"</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.0.5.html
+++ b/docs/relnotes/19.0.5.html
@@ -0,0 +1,137 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.5 Release Notes / May 21, 2019</h1>
+
+<p>
+Mesa 19.0.5 is a bug fix release which fixes bugs found since the 19.0.4 release.
+</p>
+<p>
+Mesa 19.0.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+b6e6b78c23bec15d1e7887c78b7ad00ce395ea1b20ad8aab6ce441f55f724e70  mesa-19.0.5.tar.gz
+6aecb7f67c136768692fb3c33a54196186c6c4fcafab7973516a355e1a54f831  mesa-19.0.5.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>N/A</p>
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109659">Bug 109659</a> - Missing OpenGL symbols in OSMesa Gallium when building with meson</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110134">Bug 110134</a> - SIGSEGV while playing large hevc video in mpv</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110648">Bug 110648</a> - Dota2 will not open using vulkan since 19.0 series</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Caio Marcelo de Oliveira Filho (2):</p>
+<ul>
+  <li>nir: Fix nir_opt_idiv_const when negatives are involved</li>
+  <li>nir: Fix clone of nir_variable state slots</li>
+</ul>
+
+<p>Charmaine Lee (2):</p>
+<ul>
+  <li>st/mesa: purge framebuffers with current context after unbinding winsys buffers</li>
+  <li>mesa: unreference current winsys buffers when unbinding winsys buffers</li>
+</ul>
+
+<p>Dylan Baker (4):</p>
+<ul>
+  <li>docs: Add SHA256 sums for mesa 19.0.4</li>
+  <li>cherry-ignore: add patches for panfrost</li>
+  <li>cherry-ignore: Add more 19.1 patches</li>
+  <li>bump version to 19.0.5</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+  <li>meson: expose glapi through osmesa</li>
+</ul>
+
+<p>Gert Wollny (2):</p>
+<ul>
+  <li>softpipe/buffer: load only as many components as the the buffer resource type provides</li>
+  <li>Revert "softpipe/buffer: load only as many components as the the buffer resource type provides"</li>
+</ul>
+
+<p>Ian Romanick (1):</p>
+<ul>
+  <li>Revert "nir: add late opt to turn inot/b2f combos back to bcsel"</li>
+</ul>
+
+<p>Jason Ekstrand (3):</p>
+<ul>
+  <li>intel/fs/ra: Only add dest interference to sources that exist</li>
+  <li>intel/fs/ra: Stop adding RA interference to too many SENDS nodes</li>
+  <li>anv: Only consider minSampleShading when sampleShadingEnable is set</li>
+</ul>
+
+<p>Józef Kucia (1):</p>
+<ul>
+  <li>radv: clear vertex bindings while resetting command buffer</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>i965: Fix memory leaks in brw_upload_cs_work_groups_surface().</li>
+</ul>
+
+<p>Leo Liu (1):</p>
+<ul>
+  <li>winsys/amdgpu: add VCN JPEG to no user fence group</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>anv: Use corresponding type from the vector allocation</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+  <li>st/mesa: fix 2 crashes in st_tgsi_lower_yuv</li>
+</ul>
+
+<p>Nanley Chery (1):</p>
+<ul>
+  <li>anv: Fix some depth buffer sampling cases on ICL+</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+  <li>radv: add a workaround for Monster Hunter World and LLVM 7&amp;8</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.0.6.html
+++ b/docs/relnotes/19.0.6.html
@@ -0,0 +1,153 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.5 Release Notes / May 21, 2019</h1>
+
+<p>
+Mesa 19.0.6 is a bug fix release which fixes bugs found since the 19.0.5 release.
+</p>
+<p>
+Mesa 19.0.6 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+SHA256: ac8e9ea388ec5c69f5a690190edf8ede602afdbaeea62d49e108057737430ac7  mesa-19.0.6.tar.gz
+SHA256: 2db2f2fcaa4048b16e066fad76b8a93944f7d06d329972b0f5fd5ce692ce3d24  mesa-19.0.6.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>N/A</p>
+
+<h2>Bug fixes</h2>
+
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110721">Bug 110721</a> - graphics corruption on steam client with mesa 19.1.0 rc3 on polaris</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110761">Bug 110761</a> - Huge problems between Mesa and Electron engine apps</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110784">Bug 110784</a> - [regression][bisected] Reverting 'expose 0 shader binary formats for compat profiles for Qt' causes get_program_binary failures on Iris</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+
+<p>Alok Hota (2):</p>
+<ul>
+  <li>gallium/swr: Param defaults for unhandled PIPE_CAPs</li>
+  <li>gallium/aux: add PIPE_CAP_MAX_VARYINGS to u_screen</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+  <li>nir: Actually propagate progress in nir_opt_move_load_ubo.</li>
+</ul>
+
+<p>Chenglei Ren (1):</p>
+<ul>
+  <li>anv/android: fix missing dependencies issue during parallel build</li>
+</ul>
+
+<p>Christian Gmeiner (1):</p>
+<ul>
+  <li>etnaviv: use the correct uniform dirty bits</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+  <li>Revert "mesa: unreference current winsys buffers when unbinding winsys buffers"</li>
+</ul>
+
+<p>Deepak Rawat (1):</p>
+<ul>
+  <li>winsys/drm: Fix out of scope variable usage</li>
+</ul>
+
+<p>Dylan Baker (6):</p>
+<ul>
+  <li>docs: Add Sha256 sums for 19.0.5</li>
+  <li>cherry-ignore: Add a commit that was manually backported</li>
+  <li>cherry-ignore: add another 19.1 only patch</li>
+  <li>cherry-ignore: add another 19.1 only patch</li>
+  <li>gallium: wrap u_screen in extern "C" for c++</li>
+  <li>VERSION: bump to 19.0.6</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>egl/dri: flesh out and use dri2_create_drawable()</li>
+</ul>
+
+<p>Jan Zielinski (1):</p>
+<ul>
+  <li>swr/rast: fix 32-bit compilation on Linux</li>
+</ul>
+
+<p>Lionel Landwerlin (1):</p>
+<ul>
+  <li>vulkan: fix build dependency issue with generated files</li>
+</ul>
+
+<p>Marek Olšák (2):</p>
+<ul>
+  <li>u_blitter: don't fail mipmap generation for depth formats containing stencil</li>
+  <li>ac: fix a typo in ac_build_wg_scan_bottom</li>
+</ul>
+
+<p>Philipp Zabel (1):</p>
+<ul>
+  <li>etnaviv: fill missing offset in etna_resource_get_handle</li>
+</ul>
+
+<p>Rob Clark (3):</p>
+<ul>
+  <li>freedreno/ir3: dynamic UBO indexing vs 64b pointers</li>
+  <li>freedreno/ir3: set more barrier bits</li>
+  <li>freedreno/a6xx: fix GPU crash on small render targets</li>
+</ul>
+
+<p>Sagar Ghuge (1):</p>
+<ul>
+  <li>intel/compiler: Fix assertions in brw_alu3</li>
+</ul>
+
+<p>Samuel Pitoiset (2):</p>
+<ul>
+  <li>radv: allocate more space in the CS when emitting events</li>
+  <li>radv: do not use gfx fast depth clears for layered depth/stencil images</li>
+</ul>
+
+<p>Timothy Arceri (2):</p>
+<ul>
+  <li>Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"</li>
+  <li>st/glsl: make sure to propagate initialisers to driver storage</li>
+</ul>
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.0.7.html
+++ b/docs/relnotes/19.0.7.html
@@ -0,0 +1,150 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.6 Release Notes / June 24, 2019</h1>
+
+<p>
+Mesa 19.0.7 is a bug fix release which fixes bugs found since the 19.0.6 release.
+</p>
+<p>
+Mesa 19.0.7 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+81119f0cbbd1fbe7c0574e1e2690e0dae8868124d24c875f5fb76f165db3a54d  mesa-19.0.7.tar.gz
+d7bf3db2e442fe5eeb96144f8508d94f04aededdf37af477e644638d366b2b28  mesa-19.0.7.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>N/A</p>
+
+<h2>Bug fixes</h2>
+
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110302">Bug 110302</a> - [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110921">Bug 110921</a> - virgl on OpenGL 3.3 host regressed to OpenGL 2.1</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+
+<p>Bas Nieuwenhuizen (5):</p>
+<ul>
+  <li>radv: Prevent out of bound shift on 32-bit builds.</li>
+  <li>radv: Decompress DCC when the image format is not allowed for buffers.</li>
+  <li>radv: Fix vulkan build in meson.</li>
+  <li>anv: Fix vulkan build in meson.</li>
+  <li>meson: Allow building radeonsi with just the android platform.</li>
+</ul>
+
+<p>Charmaine Lee (1):</p>
+<ul>
+  <li>svga: Remove unnecessary check for the pre flush bit for setting vertex buffers</li>
+</ul>
+
+<p>Deepak Rawat (1):</p>
+<ul>
+  <li>winsys/svga/drm: Fix 32-bit RPCI send message</li>
+</ul>
+
+<p>Dylan Baker (3):</p>
+<ul>
+  <li>docs: Add SHA256 sums for 19.0.6</li>
+  <li>cherry-ignore: add additional 19.1 only patches</li>
+  <li>Bump version for 19.0.7 release</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+  <li>mapi: correctly handle the full offset table</li>
+</ul>
+
+<p>Gert Wollny (2):</p>
+<ul>
+  <li>virgl: Add a caps feature check version</li>
+  <li>virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts</li>
+</ul>
+
+<p>Haihao Xiang (1):</p>
+<ul>
+  <li>i965: support UYVY for external import only</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+  <li>nir/propagate_invariant: Don't add NULL vars to the hash table</li>
+  <li>anv: Set STATE_BASE_ADDRESS upper bounds on gen7</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>glsl: Fix out of bounds read in shader_cache_read_program_metadata</li>
+</ul>
+
+<p>Kevin Strasser (2):</p>
+<ul>
+  <li>gallium/winsys/kms: Fix dumb buffer bpp</li>
+  <li>st/mesa: Add rgbx handling for fp formats</li>
+</ul>
+
+<p>Lionel Landwerlin (2):</p>
+<ul>
+  <li>intel/perf: fix EuThreadsCount value in performance equations</li>
+  <li>intel/perf: improve dynamic loading config detection</li>
+</ul>
+
+<p>Mathias Fröhlich (1):</p>
+<ul>
+  <li>egl: Don't add hardware device if there is no render node v2.</li>
+</ul>
+
+<p>Nanley Chery (1):</p>
+<ul>
+  <li>anv/cmd_buffer: Initalize the clear color struct for CNL+</li>
+</ul>
+
+<p>Nataraj Deshpande (1):</p>
+<ul>
+  <li>anv: Fix check for isl_fmt in assert</li>
+</ul>
+
+<p>Samuel Pitoiset (5):</p>
+<ul>
+  <li>radv: fix alpha-to-coverage when there is unused color attachments</li>
+  <li>radv: fix setting CB_SHADER_MASK for dual source blending</li>
+  <li>radv: fix occlusion queries on VegaM</li>
+  <li>radv: fix VK_EXT_memory_budget if one heap isn't available</li>
+  <li>radv: fix FMASK expand with SRGB formats</li>
+</ul>
+
+
+
+</div>
+</body>
+</html>
--- a/docs/relnotes/19.0.8.html
+++ b/docs/relnotes/19.0.8.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 19.0.8 Release Notes / June 26, 2019</h1>
+
+<p>
+Mesa 19.0.8 is an emergency bug fix release which fixes a critical bug found in the 19.0.7 release.
+</p>
+<p>
+Mesa 19.0.8 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+1a3dc3f2af853c76aadb4a1e03c9ba420361c04a742d457a702b781671a96a57  mesa-19.0.8.tar.gz
+d017eb53a810c32dabeedf6ca2238ae1e897ce9090e470e9ce1d6c9e3f1b0862  mesa-19.0.8.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+
+<p>N/A</p>
+
+<h2>Bug fixes</h2>
+
+<p>None</p>
+
+<h2>Changes</h2>
+
+<p>Dylan Baker (2):</p>
+<ul>
+  <li>docs: Add SHA256 sums for 19.0.7</li>
+  <li>version: bump to 19.0.8</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+  <li>egl/x11: calloc dri2_surf so it's properly zeroed</li>
+</ul>
+
+</div>
+</body>
+</html>
--- a/docs/shading.html
+++ b/docs/shading.html
@@ -59,6 +59,7 @@ execution.  These are generally used for debugging.
 <li><b>nopfrag</b> - force fragment shader to be a simple shader that passes
    through the color attribute.
 <li><b>useprog</b> - log glUseProgram calls to stderr
+<li><b>errors</b> - GLSL compilation and link errors will be reported to stderr.
 </ul>
 <p>
 Example:  export MESA_GLSL=dump,nopt
--- a/meson.build
+++ b/meson.build
@@ -327,12 +327,12 @@ else
  with_egl = false
 endif

-if with_egl and not (with_platform_drm or with_platform_surfaceless)
+if with_egl and not (with_platform_drm or with_platform_surfaceless or with_platform_android)
  if with_gallium_radeonsi
-    error('RadeonSI requires drm or surfaceless platform when using EGL')
+    error('RadeonSI requires the drm, surfaceless or android platform when using EGL')
  endif
  if with_gallium_virgl
-    error('Virgl requires drm or surfaceless platform when using EGL')
+    error('Virgl requires the drm, surfaceless or android platform when using EGL')
  endif
 endif

@@ -1213,6 +1213,7 @@ if _llvm != 'false'
      with_gallium_opencl or _llvm == 'true'
    ),
    static : not _shared_llvm,
+    method : 'config-tool',
  )
  with_llvm = dep_llvm.found()
 endif
@@ -1387,12 +1388,14 @@ if with_platform_x11
      dep_xshmfence = dependency('xshmfence', version : '>= 1.1')
    endif
  endif
-  if with_glx == 'dri'
+  if with_glx == 'dri' or with_glx == 'gallium-xlib'
+    dep_glproto = dependency('glproto', version : '>= 1.4.14')
+  endif
+  if with_glx == 'dri' 
    if with_dri_platform == 'drm'
      dep_dri2proto = dependency('dri2proto', version : '>= 2.8')
      dep_xxf86vm = dependency('xxf86vm')
    endif
-    dep_glproto = dependency('glproto', version : '>= 1.4.14')
  endif
  if (with_egl or (
      with_gallium_vdpau or with_gallium_xvmc or with_gallium_xa or
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -3455,7 +3455,7 @@ ac_build_wg_scan_bottom(struct ac_llvm_context *ctx, struct ac_wg_scan *ws)

 	/* ws->result_reduce is already the correct value */
 	if (ws->enable_inclusive)
-		ws->result_inclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->src, ws->op);
+		ws->result_inclusive = ac_build_alu_op(ctx, ws->result_inclusive, ws->src, ws->op);
 	if (ws->enable_exclusive)
 		ws->result_exclusive = ac_build_alu_op(ctx, ws->result_exclusive, ws->extra, ws->op);
 }
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -151,13 +151,14 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
 	LLVMTargetRef target = ac_get_llvm_target(triple);

 	snprintf(features, sizeof(features),
-		 "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
+		 "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
 		 HAVE_LLVM >= 0x0800 ? "" : ",+vgpr-spilling",
 		 tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
 		 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 		 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
-		 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "");
-	
+		 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
+		 tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
+
 	LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 	                             target,
 	                             triple,
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -65,6 +65,7 @@ enum ac_target_machine_options {
 	AC_TM_CHECK_IR = (1 << 5),
 	AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
 	AC_TM_CREATE_LOW_OPT = (1 << 7),
+	AC_TM_NO_LOAD_STORE_OPT = (1 << 8),
 };

 enum ac_float_mode {
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2359,10 +2359,12 @@ static void get_image_coords(struct ac_nir_context *ctx,
 }

 static LLVMValueRef get_image_buffer_descriptor(struct ac_nir_context *ctx,
-                                                const nir_intrinsic_instr *instr, bool write)
+                                                const nir_intrinsic_instr *instr,
+						bool write, bool atomic)
 {
 	LLVMValueRef rsrc = get_image_descriptor(ctx, instr, AC_DESC_BUFFER, write);
-	if (ctx->abi->gfx9_stride_size_workaround) {
+	if (ctx->abi->gfx9_stride_size_workaround ||
+	    (ctx->abi->gfx9_stride_size_workaround_for_atomic && atomic)) {
 		LLVMValueRef elem_count = LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 2, 0), "");
 		LLVMValueRef stride = LLVMBuildExtractElement(ctx->ac.builder, rsrc, LLVMConstInt(ctx->ac.i32, 1, 0), "");
 		stride = LLVMBuildLShr(ctx->ac.builder, stride, LLVMConstInt(ctx->ac.i32, 16, 0), "");
@@ -2395,7 +2397,7 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
 		unsigned num_channels = util_last_bit(mask);
 		LLVMValueRef rsrc, vindex;

-		rsrc = get_image_buffer_descriptor(ctx, instr, false);
+		rsrc = get_image_buffer_descriptor(ctx, instr, false, false);
 		vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
 						 ctx->ac.i32_0, "");

@@ -2439,7 +2441,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
 	if (dim == GLSL_SAMPLER_DIM_BUF) {
 		char name[48];
 		const char *types[] = { "f32", "v2f32", "v4f32" };
-		LLVMValueRef rsrc = get_image_buffer_descriptor(ctx, instr, true);
+		LLVMValueRef rsrc = get_image_buffer_descriptor(ctx, instr, true, false);
 		LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[3]));
 		unsigned src_channels = ac_get_llvm_num_components(src);

@@ -2535,7 +2537,7 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
 	params[param_count++] = get_src(ctx, instr->src[3]);

 	if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
-		params[param_count++] = get_image_buffer_descriptor(ctx, instr, true);
+		params[param_count++] = get_image_buffer_descriptor(ctx, instr, true, true);
 		params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
 								ctx->ac.i32_0, ""); /* vindex */
 		params[param_count++] = ctx->ac.i32_0; /* voffset */
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -195,6 +195,7 @@ struct ac_shader_abi {
 	/* Whether to workaround GFX9 ignoring the stride for the buffer size if IDXEN=0
 	* and LLVM optimizes an indexed load with constant index to IDXEN=0. */
 	bool gfx9_stride_size_workaround;
+	bool gfx9_stride_size_workaround_for_atomic;
 };

 #endif /* AC_SHADER_ABI_H */
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -128,21 +128,26 @@ if with_xlib_lease
  radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
 endif

+if with_platform_android
+  radv_flags += [
+    '-DVK_USE_PLATFORM_ANDROID_KHR'
+  ]
+  libradv_files += files('radv_android.c')
+endif
+
 libvulkan_radeon = shared_library(
  'vulkan_radeon',
  [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c, sha1_h],
  include_directories : [
-    inc_common, inc_amd, inc_amd_common, inc_compiler, inc_vulkan_util,
-    inc_vulkan_wsi,
+    inc_common, inc_amd, inc_amd_common, inc_compiler, inc_vulkan_wsi,
  ],
  link_with : [
-    libamd_common, libamdgpu_addrlib, libvulkan_util, libvulkan_wsi,
-    libmesa_util,
+    libamd_common, libamdgpu_addrlib, libvulkan_wsi, libmesa_util,
  ],
  dependencies : [
    dep_llvm, dep_libdrm_amdgpu, dep_thread, dep_elf, dep_dl, dep_m,
    dep_valgrind, radv_deps,
-    idep_nir,
+    idep_nir, idep_vulkan_util,
  ],
  c_args : [c_vis_args, no_override_init_args, radv_flags],
  cpp_args : [cpp_vis_args, radv_flags],
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -301,7 +301,6 @@ radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 static VkResult
 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 {
-
 	cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);

 	list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
@@ -326,6 +325,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)

 	cmd_buffer->record_result = VK_SUCCESS;

+	memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
+
 	for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 		cmd_buffer->descriptors[i].dirty = 0;
 		cmd_buffer->descriptors[i].valid = 0;
@@ -565,8 +566,8 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,

 	for_each_bit(i, descriptors_state->valid) {
 		struct radv_descriptor_set *set = descriptors_state->sets[i];
-		data[i * 2] = (uintptr_t)set;
-		data[i * 2 + 1] = (uintptr_t)set >> 32;
+		data[i * 2] = (uint64_t)(uintptr_t)set;
+		data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
 	}

 	radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
@@ -2157,6 +2158,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
 	ia_multi_vgt_param =
 		si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
 					  draw_info->indirect,
+					  !!draw_info->strmout_buffer,
 					  draw_info->indirect ? 0 : draw_info->count);

 	if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
@@ -4734,7 +4736,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,

 	radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);

-	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
+	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 21);

 	/* Flags that only require a top-of-pipe event. */
 	VkPipelineStageFlags top_of_pipe_flags =
@@ -4844,8 +4846,11 @@ void radv_CmdBeginConditionalRenderingEXT(
 {
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 	RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
+	struct radeon_cmdbuf *cs = cmd_buffer->cs;
 	bool draw_visible = true;
-	uint64_t va;
+	uint64_t pred_value = 0;
+	uint64_t va, new_va;
+	unsigned pred_offset;

 	va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;

@@ -4861,13 +4866,51 @@ void radv_CmdBeginConditionalRenderingEXT(

 	si_emit_cache_flush(cmd_buffer);

+	/* From the Vulkan spec 1.1.107:
+	 *
+	 * "If the 32-bit value at offset in buffer memory is zero, then the
+	 *  rendering commands are discarded, otherwise they are executed as
+	 *  normal. If the value of the predicate in buffer memory changes while
+	 *  conditional rendering is active, the rendering commands may be
+	 *  discarded in an implementation-dependent way. Some implementations
+	 *  may latch the value of the predicate upon beginning conditional
+	 *  rendering while others may read it before every rendering command."
+	 *
+	 * But, the AMD hardware treats the predicate as a 64-bit value which
+	 * means we need a workaround in the driver. Luckily, it's not required
+	 * to support if the value changes when predication is active.
+	 *
+	 * The workaround is as follows:
+	 * 1) allocate a 64-value in the upload BO and initialize it to 0
+	 * 2) copy the 32-bit predicate value to the upload BO
+	 * 3) use the new allocated VA address for predication
+	 *
+	 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
+	 * in ME  (+ sync PFP) instead of PFP.
+	 */
+	radv_cmd_buffer_upload_data(cmd_buffer, 8, 16, &pred_value, &pred_offset);
+
+	new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;
+
+	radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+	radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
+			COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
+			COPY_DATA_WR_CONFIRM);
+	radeon_emit(cs, va);
+	radeon_emit(cs, va >> 32);
+	radeon_emit(cs, new_va);
+	radeon_emit(cs, new_va >> 32);
+
+	radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+	radeon_emit(cs, 0);
+
 	/* Enable predication for this command buffer. */
-	si_emit_set_predication_state(cmd_buffer, draw_visible, va);
+	si_emit_set_predication_state(cmd_buffer, draw_visible, new_va);
 	cmd_buffer->state.predicating = true;

 	/* Store conditional rendering user info. */
 	cmd_buffer->state.predication_type = draw_visible;
-	cmd_buffer->state.predication_va = va;
+	cmd_buffer->state.predication_va = new_va;
 }

 void radv_CmdEndConditionalRenderingEXT(
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -51,6 +51,7 @@ enum {
 	RADV_DEBUG_CHECKIR           = 0x200000,
 	RADV_DEBUG_NOTHREADLLVM      = 0x400000,
 	RADV_DEBUG_NOBINNING         = 0x800000,
+	RADV_DEBUG_NO_LOAD_STORE_OPT = 0x1000000,
 };

 enum {
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -111,6 +111,7 @@ radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
 	case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
 	case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
 	case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
+	case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
 	case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
 	case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
 	default: chip_string = "AMD RADV unknown"; break;
@@ -465,6 +466,7 @@ static const struct debug_control radv_debug_options[] = {
 	{"checkir", RADV_DEBUG_CHECKIR},
 	{"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
 	{"nobinning", RADV_DEBUG_NOBINNING},
+	{"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
 	{NULL, 0}
 };

@@ -510,6 +512,13 @@ radv_handle_per_app_options(struct radv_instance *instance,
 	} else if (!strcmp(name, "DOOM_VFR")) {
 		/* Work around a Doom VFR game bug */
 		instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
+	} else if (!strcmp(name, "MonsterHunterWorld.exe")) {
+		/* Workaround for a WaW hazard when LLVM moves/merges
+		 * load/store memory operations.
+		 * See https://reviews.llvm.org/D61313
+		 */
+		if (HAVE_LLVM < 0x900)
+			instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
 	}
 }

@@ -1380,40 +1389,46 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
 	 * Note that the application heap usages are not really accurate (eg.
 	 * in presence of shared buffers).
 	 */
-	if (vram_size) {
-		heap_usage = device->ws->query_value(device->ws,
-						     RADEON_ALLOCATED_VRAM);
+	for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
+		uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;

-		heap_budget = vram_size -
-			device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
-			heap_usage;
+		switch (device->mem_type_indices[i]) {
+		case RADV_MEM_TYPE_VRAM:
+			heap_usage = device->ws->query_value(device->ws,
+							     RADEON_ALLOCATED_VRAM);

-		memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
-		memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
-	}
+			heap_budget = vram_size -
+				device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
+				heap_usage;

-	if (visible_vram_size) {
-		heap_usage = device->ws->query_value(device->ws,
-						     RADEON_ALLOCATED_VRAM_VIS);
+			memoryBudget->heapBudget[heap_index] = heap_budget;
+			memoryBudget->heapUsage[heap_index] = heap_usage;
+			break;
+		case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
+			heap_usage = device->ws->query_value(device->ws,
+							     RADEON_ALLOCATED_VRAM_VIS);

-		heap_budget = visible_vram_size -
-			device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
-			heap_usage;
+			heap_budget = visible_vram_size -
+				device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
+				heap_usage;

-		memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
-		memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
-	}
+			memoryBudget->heapBudget[heap_index] = heap_budget;
+			memoryBudget->heapUsage[heap_index] = heap_usage;
+			break;
+		case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
+			heap_usage = device->ws->query_value(device->ws,
+							     RADEON_ALLOCATED_GTT);

-	if (gtt_size) {
-		heap_usage = device->ws->query_value(device->ws,
-						     RADEON_ALLOCATED_GTT);
+			heap_budget = gtt_size -
+				device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
+				heap_usage;

-		heap_budget = gtt_size -
-			device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
-			heap_usage;
-
-		memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
-		memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
+			memoryBudget->heapBudget[heap_index] = heap_budget;
+			memoryBudget->heapUsage[heap_index] = heap_usage;
+			break;
+		default:
+			break;
+		}
 	}

 	/* The heapBudget and heapUsage values must be zero for array elements
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -100,7 +100,7 @@ EXTENSIONS = [
    Extension('VK_EXT_display_control',                   1, 'VK_USE_PLATFORM_DISPLAY_KHR'),
    Extension('VK_EXT_debug_report',                      9, True),
    Extension('VK_EXT_depth_range_unrestricted',          1, True),
-    Extension('VK_EXT_descriptor_indexing',               2, True),
+    Extension('VK_EXT_descriptor_indexing',               2, False),
    Extension('VK_EXT_discard_rectangles',                1, True),
    Extension('VK_EXT_external_memory_dma_buf',           1, True),
    Extension('VK_EXT_external_memory_host',              1, 'device->rad_info.has_userptr'),
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -524,7 +524,7 @@ static bool radv_is_storage_image_format_supported(struct radv_physical_device *
 	}
 }

-static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
+bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
 {
 	const struct vk_format_description *desc = vk_format_description(format);
 	unsigned data_format, num_format;
@@ -536,7 +536,8 @@ static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
 	num_format = radv_translate_buffer_numformat(desc,
 						     vk_format_get_first_non_void_channel(format));

-	*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
+	if (scaled)
+		*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
 	return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID &&
 		num_format != ~0;
 }
@@ -990,10 +991,22 @@ bool radv_format_pack_clear_color(VkFormat format,
 				assert(channel->size == 8);

 				v = util_format_linear_float_to_srgb_8unorm(value->float32[c]);
-			} else if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
-				v = MAX2(MIN2(value->float32[c], 1.0f), 0.0f) * ((1ULL << channel->size) - 1);
-			} else  {
-				v = MAX2(MIN2(value->float32[c], 1.0f), -1.0f) * ((1ULL << (channel->size - 1)) - 1);
+			} else {
+				float f = MIN2(value->float32[c], 1.0f);
+
+				if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
+					f = MAX2(f, 0.0f) * ((1ULL << channel->size) - 1);
+				} else {
+					f = MAX2(f, -1.0f) * ((1ULL << (channel->size - 1)) - 1);
+				}
+
+				/* The hardware rounds before conversion. */
+				if (f > 0)
+					f += 0.5f;
+				else
+					f -= 0.5f;
+
+				v = (uint64_t)f;
 			}
 		} else if (channel->type == VK_FORMAT_TYPE_FLOAT) {
 			if (channel->size == 32) {
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -650,6 +650,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 	if (radv_image_has_htile(iview->image) &&
 	    iview->base_mip == 0 &&
 	    iview->base_layer == 0 &&
+	    iview->layer_count == iview->image->info.array_size &&
 	    radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 	    radv_image_extent_compare(iview->image, &iview->extent))
 		return true;
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -189,6 +189,24 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
 							layout,
 							&pRegions[r].imageSubresource);

+		if (!radv_is_buffer_format_supported(img_bsurf.format, NULL)) {
+			uint32_t queue_mask = radv_image_queue_family_mask(image,
+			                                                   cmd_buffer->queue_family_index,
+			                                                   cmd_buffer->queue_family_index);
+			MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
+			if (compressed) {
+				radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
+								.aspectMask = pRegions[r].imageSubresource.aspectMask,
+								.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
+								.levelCount = 1,
+								.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
+								.layerCount = pRegions[r].imageSubresource.layerCount,
+			                                });
+			}
+			img_bsurf.format = vk_format_for_size(vk_format_get_blocksize(img_bsurf.format));
+			img_bsurf.current_layout = VK_IMAGE_LAYOUT_GENERAL;
+		}
+
 		struct radv_meta_blit2d_buffer buf_bsurf = {
 			.bs = img_bsurf.bs,
 			.format = img_bsurf.format,
@@ -314,6 +332,24 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
 							layout,
 							&pRegions[r].imageSubresource);

+		if (!radv_is_buffer_format_supported(img_info.format, NULL)) {
+			uint32_t queue_mask = radv_image_queue_family_mask(image,
+			                                                   cmd_buffer->queue_family_index,
+			                                                   cmd_buffer->queue_family_index);
+			MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
+			if (compressed) {
+				radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
+								.aspectMask = pRegions[r].imageSubresource.aspectMask,
+								.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
+								.levelCount = 1,
+								.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
+								.layerCount = pRegions[r].imageSubresource.layerCount,
+			                                });
+			}
+			img_info.format = vk_format_for_size(vk_format_get_blocksize(img_info.format));
+			img_info.current_layout = VK_IMAGE_LAYOUT_GENERAL;
+		}
+
 		struct radv_meta_blit2d_buffer buf_info = {
 			.bs = img_info.bs,
 			.format = img_info.format,
--- a/src/amd/vulkan/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/radv_meta_fmask_expand.c
@@ -24,6 +24,7 @@

 #include "radv_meta.h"
 #include "radv_private.h"
+#include "vk_format.h"

 static nir_shader *
 build_fmask_expand_compute_shader(struct radv_device *device, int samples)
@@ -132,7 +133,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
 					     .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 					     .image = radv_image_to_handle(image),
 					     .viewType = radv_meta_get_view_type(image),
-					     .format = image->vk_format,
+					     .format = vk_format_no_srgb(image->vk_format),
 					     .subresourceRange = {
 						     .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 						     .baseMipLevel = 0,
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3497,10 +3497,17 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 	ctx.abi.clamp_shadow_reference = false;
 	ctx.abi.gfx9_stride_size_workaround = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x800;

+	/* Because the new raw/struct atomic intrinsics are buggy with LLVM 8,
+	 * we fallback to the old intrinsics for atomic buffer image operations
+	 * and thus we need to apply the indexing workaround...
+	 */
+	ctx.abi.gfx9_stride_size_workaround_for_atomic = ctx.ac.chip_class == GFX9 && HAVE_LLVM < 0x900;
+
 	if (shader_count >= 2)
 		ac_init_exec_full_mask(&ctx.ac);

-	if (ctx.ac.chip_class == GFX9 &&
+	if ((ctx.ac.family == CHIP_VEGA10 ||
+	     ctx.ac.family == CHIP_RAVEN) &&
 	    shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
 		ac_nir_fixup_ls_hs_input_vgprs(&ctx);

--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -524,7 +524,7 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
 		col_format |= cf << (4 * i);
 	}

-	if (!col_format && blend->need_src_alpha & (1 << 0)) {
+	if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
 		/* When a subpass doesn't have any color attachments, write the
 		 * alpha channel of MRT0 when alpha coverage is enabled because
 		 * the depth attachment needs it.
@@ -542,10 +542,13 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
 		}
 	}

-	blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
-
+	/* The output for dual source blending should have the same format as
+	 * the first output.
+	 */
 	if (blend->mrt0_is_dual_src)
 		col_format |= (col_format & 0xf) << 4;
+
+	blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
 	blend->spi_shader_col_format = col_format;
 }

@@ -1445,11 +1448,13 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,

 	const  VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
 			vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
-	if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
+	if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 		dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
-		typed_memcpy(dynamic->discard_rectangle.rectangles,
-		             discard_rectangle_info->pDiscardRectangles,
-		             discard_rectangle_info->discardRectangleCount);
+		if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
+			typed_memcpy(dynamic->discard_rectangle.rectangles,
+			             discard_rectangle_info->pDiscardRectangles,
+			             discard_rectangle_info->discardRectangleCount);
+		}
 	}

 	pipeline->dynamic_state.mask = states;
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1148,6 +1148,7 @@ void si_write_scissors(struct radeon_cmdbuf *cs, int first,
 		       const VkViewport *viewports, bool can_use_guardband);
 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 				   bool instanced_draw, bool indirect_draw,
+				   bool count_from_stream_output,
 				   uint32_t draw_vertex_count);
 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
 				enum chip_class chip_class,
@@ -1447,6 +1448,7 @@ uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *de
 					  int first_non_void);
 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
 					 int first_non_void);
+bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
 uint32_t radv_translate_colorformat(VkFormat format);
 uint32_t radv_translate_color_numformat(VkFormat format,
 					const struct vk_format_description *desc,
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -40,18 +40,6 @@
 static const int pipelinestat_block_size = 11 * 8;
 static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};

-static unsigned get_max_db(struct radv_device *device)
-{
-	unsigned num_db = device->physical_device->rad_info.num_render_backends;
-	MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
-
-	/* Otherwise we need to change the query reset procedure */
-	assert(rb_mask == ((1ull << num_db) - 1));
-
-	return num_db;
-}
-
-
 static nir_ssa_def *nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)
 {
 	return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));
@@ -108,12 +96,14 @@ build_occlusion_query_shader(struct radv_device *device) {
 	 * 	uint64_t dst_offset = dst_stride * global_id.x;
 	 * 	bool available = true;
 	 * 	for (int i = 0; i < db_count; ++i) {
-	 * 		uint64_t start = src_buf[src_offset + 16 * i];
-	 * 		uint64_t end = src_buf[src_offset + 16 * i + 8];
-	 * 		if ((start & (1ull << 63)) && (end & (1ull << 63)))
-	 * 			result += end - start;
-	 * 		else
-	 * 			available = false;
+	 *		if (enabled_rb_mask & (1 << i)) {
+	 *			uint64_t start = src_buf[src_offset + 16 * i];
+	 *			uint64_t end = src_buf[src_offset + 16 * i + 8];
+	 *			if ((start & (1ull << 63)) && (end & (1ull << 63)))
+	 *				result += end - start;
+	 *			else
+	 *				available = false;
+	 *		}
 	 * 	}
 	 * 	uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
 	 * 	if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
@@ -139,7 +129,8 @@ build_occlusion_query_shader(struct radv_device *device) {
 	nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
 	nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
 	nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");
-	unsigned db_count = get_max_db(device);
+	unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
+	unsigned db_count = device->physical_device->rad_info.num_render_backends;

 	nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");

@@ -185,6 +176,16 @@ build_occlusion_query_shader(struct radv_device *device) {
 	nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
 	radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));

+	nir_ssa_def *enabled_cond =
+		nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),
+			     nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));
+
+	nir_if *enabled_if = nir_if_create(b.shader);
+	enabled_if->condition = nir_src_for_ssa(nir_i2b(&b, enabled_cond));
+	nir_cf_node_insert(b.cursor, &enabled_if->cf_node);
+
+	b.cursor = nir_after_cf_list(&enabled_if->then_list);
+
 	nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
 	load_offset = nir_iadd(&b, input_base, load_offset);

@@ -1038,7 +1039,7 @@ VkResult radv_CreateQueryPool(

 	switch(pCreateInfo->queryType) {
 	case VK_QUERY_TYPE_OCCLUSION:
-		pool->stride = 16 * get_max_db(device);
+		pool->stride = 16 * device->physical_device->rad_info.num_render_backends;
 		break;
 	case VK_QUERY_TYPE_PIPELINE_STATISTICS:
 		pool->stride = pipelinestat_block_size * 2;
@@ -1152,12 +1153,17 @@ VkResult radv_GetQueryPoolResults(
 		}
 		case VK_QUERY_TYPE_OCCLUSION: {
 			volatile uint64_t const *src64 = (volatile uint64_t const *)src;
+			uint32_t db_count = device->physical_device->rad_info.num_render_backends;
+			uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
 			uint64_t sample_count = 0;
-			int db_count = get_max_db(device);
 			available = 1;

 			for (int i = 0; i < db_count; ++i) {
 				uint64_t start, end;
+
+				if (!(enabled_rb_mask & (1 << i)))
+					continue;
+
 				do {
 					start = src64[2 * i];
 					end = src64[2 * i + 1];
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -222,6 +222,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			.lower_ubo_ssbo_access_to_offsets = true,
 			.caps = {
 				.descriptor_array_dynamic_indexing = true,
+				.descriptor_array_non_uniform_indexing = true,
+				.descriptor_indexing = true,
 				.device_group = true,
 				.draw_parameters = true,
 				.float64 = true,
@@ -610,6 +612,8 @@ shader_variant_create(struct radv_device *device,
 		tm_options |= AC_TM_SISCHED;
 	if (options->check_ir)
 		tm_options |= AC_TM_CHECK_IR;
+	if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
+		tm_options |= AC_TM_NO_LOAD_STORE_OPT;

 	thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 	radv_init_llvm_once();
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -115,6 +115,15 @@ gather_intrinsic_load_deref_info(const nir_shader *nir,
 	}
 }

+static uint32_t
+widen_writemask(uint32_t wrmask)
+{
+	uint32_t new_wrmask = 0;
+	for(unsigned i = 0; i < 4; i++)
+		new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2);
+	return new_wrmask;
+}
+
 static void
 set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 		      uint8_t *output_usage_mask)
@@ -122,7 +131,7 @@ set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 	nir_deref_instr *deref_instr =
 		nir_instr_as_deref(instr->src[0].ssa->parent_instr);
 	nir_variable *var = nir_deref_instr_get_variable(deref_instr);
-	unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
+	unsigned attrib_count = glsl_count_attribute_slots(deref_instr->type, false);
 	unsigned idx = var->data.location;
 	unsigned comp = var->data.location_frac;
 	unsigned const_offset = 0;
@@ -130,15 +139,19 @@ set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 	get_deref_offset(deref_instr, &const_offset);

 	if (var->data.compact) {
+		assert(!glsl_type_is_64bit(deref_instr->type));
 		const_offset += comp;
 		output_usage_mask[idx + const_offset / 4] |= 1 << (const_offset % 4);
 		return;
 	}

-	for (unsigned i = 0; i < attrib_count; i++) {
+	uint32_t wrmask = nir_intrinsic_write_mask(instr);
+	if (glsl_type_is_64bit(deref_instr->type))
+		wrmask = widen_writemask(wrmask);
+
+	for (unsigned i = 0; i < attrib_count; i++)
 		output_usage_mask[idx + i + const_offset] |=
-			instr->const_index[0] << comp;
-	}
+			((wrmask >> (i * 4)) & 0xf) << comp;
 }

 static void
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -561,6 +561,7 @@ radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
 uint32_t
 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 			  bool instanced_draw, bool indirect_draw,
+			  bool count_from_stream_output,
 			  uint32_t draw_vertex_count)
 {
 	enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
@@ -622,6 +623,12 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 		    (instanced_draw || indirect_draw))
 			partial_vs_wave = true;

+		/* Hardware requirement when drawing primitives from a stream
+		 * output buffer.
+		 */
+		if (count_from_stream_output)
+			wd_switch_on_eop = true;
+
 		/* If the WD switch is false, the IA switch must be false too. */
 		assert(wd_switch_on_eop || !ia_switch_on_eop);
 	}
--- a/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c
+++ b/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c
@@ -147,10 +147,20 @@ lower_deref(nir_builder *b, struct lower_samplers_as_deref_state *state,

   remove_struct_derefs_prep(path.path, &name, &location, &type);

-   assert(location < state->shader_program->data->NumUniformStorage &&
-          state->shader_program->data->UniformStorage[location].opaque[stage].active);
+   if (state->shader_program && var->data.how_declared != nir_var_hidden) {
+      /* For GLSL programs, look up the bindings in the uniform storage. */
+      assert(location < state->shader_program->data->NumUniformStorage &&
+             state->shader_program->data->UniformStorage[location].opaque[stage].active);

-   binding = state->shader_program->data->UniformStorage[location].opaque[stage].index;
+      binding = state->shader_program->data->UniformStorage[location].opaque[stage].index;
+   } else {
+      /* For ARB programs, built-in shaders, or internally generated sampler
+       * variables in GLSL programs, assume that whoever created the shader
+       * set the bindings correctly already.
+       */
+      assert(var->data.explicit_binding);
+      binding = var->data.binding;
+   }

   if (var->type == type) {
      /* Fast path: We did not encounter any struct derefs. */
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -233,7 +233,7 @@ public:

   ir_rvalue *as_rvalue_to_saturate();

-   virtual bool is_lvalue(const struct _mesa_glsl_parse_state *state = NULL) const
+   virtual bool is_lvalue(const struct _mesa_glsl_parse_state * = NULL) const
   {
      return false;
   }
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -165,9 +165,8 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
   prog->FragDataIndexBindings->iterate(create_binding_str, &buf);
   ralloc_asprintf_append(&buf, "tf: %d ", prog->TransformFeedback.BufferMode);
   for (unsigned int i = 0; i < prog->TransformFeedback.NumVarying; i++) {
-      ralloc_asprintf_append(&buf, "%s:%d ",
-                             prog->TransformFeedback.VaryingNames[i],
-                             prog->TransformFeedback.BufferStride[i]);
+      ralloc_asprintf_append(&buf, "%s ",
+                             prog->TransformFeedback.VaryingNames[i]);
   }

   /* SSO has an effect on the linked program so include this when generating
--- a/src/compiler/nir/nir_clone.c
+++ b/src/compiler/nir/nir_clone.c
@@ -151,9 +151,11 @@ nir_variable_clone(const nir_variable *var, nir_shader *shader)
   nvar->name = ralloc_strdup(nvar, var->name);
   nvar->data = var->data;
   nvar->num_state_slots = var->num_state_slots;
-   nvar->state_slots = ralloc_array(nvar, nir_state_slot, var->num_state_slots);
-   memcpy(nvar->state_slots, var->state_slots,
-          var->num_state_slots * sizeof(nir_state_slot));
+   if (var->num_state_slots) {
+      nvar->state_slots = ralloc_array(nvar, nir_state_slot, var->num_state_slots);
+      memcpy(nvar->state_slots, var->state_slots,
+             var->num_state_slots * sizeof(nir_state_slot));
+   }
   if (var->constant_initializer) {
      nvar->constant_initializer =
         nir_constant_clone(var->constant_initializer, nvar);
--- a/src/compiler/nir/nir_linking_helpers.c
+++ b/src/compiler/nir/nir_linking_helpers.c
@@ -59,6 +59,15 @@ get_variable_io_mask(nir_variable *var, gl_shader_stage stage)
   return ((1ull << slots) - 1) << location;
 }

+static uint8_t
+get_num_components(nir_variable *var)
+{
+   if (glsl_type_is_struct(glsl_without_array(var->type)))
+      return 4;
+
+   return glsl_get_vector_elements(glsl_without_array(var->type));
+}
+
 static void
 tcs_add_output_reads(nir_shader *shader, uint64_t *read, uint64_t *patches_read)
 {
@@ -80,12 +89,14 @@ tcs_add_output_reads(nir_shader *shader, uint64_t *read, uint64_t *patches_read)
               continue;

            nir_variable *var = nir_deref_instr_get_variable(deref);
-            if (var->data.patch) {
-               patches_read[var->data.location_frac] |=
-                  get_variable_io_mask(var, shader->info.stage);
-            } else {
-               read[var->data.location_frac] |=
-                  get_variable_io_mask(var, shader->info.stage);
+            for (unsigned i = 0; i < get_num_components(var); i++) {
+               if (var->data.patch) {
+                  patches_read[var->data.location_frac + i] |=
+                     get_variable_io_mask(var, shader->info.stage);
+               } else {
+                  read[var->data.location_frac + i] |=
+                     get_variable_io_mask(var, shader->info.stage);
+               }
            }
         }
      }
@@ -161,22 +172,26 @@ nir_remove_unused_varyings(nir_shader *producer, nir_shader *consumer)
   uint64_t patches_read[4] = { 0 }, patches_written[4] = { 0 };

   nir_foreach_variable(var, &producer->outputs) {
-      if (var->data.patch) {
-         patches_written[var->data.location_frac] |=
-            get_variable_io_mask(var, producer->info.stage);
-      } else {
-         written[var->data.location_frac] |=
-            get_variable_io_mask(var, producer->info.stage);
+      for (unsigned i = 0; i < get_num_components(var); i++) {
+         if (var->data.patch) {
+            patches_written[var->data.location_frac + i] |=
+               get_variable_io_mask(var, producer->info.stage);
+         } else {
+            written[var->data.location_frac + i] |=
+               get_variable_io_mask(var, producer->info.stage);
+         }
      }
   }

   nir_foreach_variable(var, &consumer->inputs) {
-      if (var->data.patch) {
-         patches_read[var->data.location_frac] |=
-            get_variable_io_mask(var, consumer->info.stage);
-      } else {
-         read[var->data.location_frac] |=
-            get_variable_io_mask(var, consumer->info.stage);
+      for (unsigned i = 0; i < get_num_components(var); i++) {
+         if (var->data.patch) {
+            patches_read[var->data.location_frac + i] |=
+               get_variable_io_mask(var, consumer->info.stage);
+         } else {
+            read[var->data.location_frac + i] |=
+               get_variable_io_mask(var, consumer->info.stage);
+         }
      }
   }

--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -929,9 +929,6 @@ late_optimizations = [
   (('fdot4', a, b), ('fdot_replicated4', a, b), 'options->fdot_replicates'),
   (('fdph', a, b), ('fdph_replicated', a, b), 'options->fdot_replicates'),

-   (('b2f(is_used_more_than_once)', ('inot', 'a@1')), ('bcsel', a, 0.0, 1.0)),
-   (('fneg(is_used_more_than_once)', ('b2f', ('inot', 'a@1'))), ('bcsel', a, -0.0, -1.0)),
-
   # we do these late so that we don't get in the way of creating ffmas
   (('fmin', ('fadd(is_used_once)', '#c', a), ('fadd(is_used_once)', '#c', b)), ('fadd', c, ('fmin', a, b))),
   (('fmax', ('fadd(is_used_once)', '#c', a), ('fadd(is_used_once)', '#c', b)), ('fadd', c, ('fmax', a, b))),
--- a/src/compiler/nir/nir_opt_idiv_const.c
+++ b/src/compiler/nir/nir_opt_idiv_const.c
@@ -65,15 +65,17 @@ build_umod(nir_builder *b, nir_ssa_def *n, uint64_t d)
 static nir_ssa_def *
 build_idiv(nir_builder *b, nir_ssa_def *n, int64_t d)
 {
+   uint64_t abs_d = d < 0 ? -d : d;
+
   if (d == 0) {
      return nir_imm_intN_t(b, 0, n->bit_size);
   } else if (d == 1) {
      return n;
   } else if (d == -1) {
      return nir_ineg(b, n);
-   } else if (util_is_power_of_two_or_zero64(d)) {
-      uint64_t abs_d = d < 0 ? -d : d;
-      nir_ssa_def *uq = nir_ishr(b, n, nir_imm_int(b, util_logbase2_64(abs_d)));
+   } else if (util_is_power_of_two_or_zero64(abs_d)) {
+      nir_ssa_def *uq = nir_ushr(b, nir_iabs(b, n),
+                                    nir_imm_int(b, util_logbase2_64(abs_d)));
      nir_ssa_def *n_neg = nir_ilt(b, n, nir_imm_intN_t(b, 0, n->bit_size));
      nir_ssa_def *neg = d < 0 ? nir_inot(b, n_neg) : n_neg;
      return nir_bcsel(b, neg, nir_ineg(b, uq), uq);
--- a/src/compiler/nir/nir_opt_move_load_ubo.c
+++ b/src/compiler/nir/nir_opt_move_load_ubo.c
@@ -91,7 +91,7 @@ move_load_ubo(nir_block *block)
      }
   }

-   return false;
+   return progress;
 }

 bool
--- a/src/compiler/nir/nir_propagate_invariant.c
+++ b/src/compiler/nir/nir_propagate_invariant.c
@@ -65,12 +65,21 @@ add_cf_node(nir_cf_node *cf, struct set *invariants)
 static void
 add_var(nir_variable *var, struct set *invariants)
 {
-   _mesa_set_add(invariants, var);
+   /* Because we pass the result of nir_intrinsic_get_var directly to this
+    * function, it's possible for var to be NULL if, for instance, there's a
+    * cast somewhere in the chain.
+    */
+   if (var != NULL)
+      _mesa_set_add(invariants, var);
 }

 static bool
 var_is_invariant(nir_variable *var, struct set * invariants)
 {
+   /* Because we pass the result of nir_intrinsic_get_var directly to this
+    * function, it's possible for var to be NULL if, for instance, there's a
+    * cast somewhere in the chain.
+    */
   return var && (var->data.invariant || _mesa_set_search(invariants, var));
 }

--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -116,22 +116,6 @@ is_not_const(nir_alu_instr *instr, unsigned src, UNUSED unsigned num_components,
   return !nir_src_is_const(instr->src[src].src);
 }

-static inline bool
-is_used_more_than_once(nir_alu_instr *instr)
-{
-   bool zero_if_use = list_empty(&instr->dest.dest.ssa.if_uses);
-   bool zero_use = list_empty(&instr->dest.dest.ssa.uses);
-
-   if (zero_use && zero_if_use)
-      return false;
-   else if (zero_use && list_is_singular(&instr->dest.dest.ssa.if_uses))
-      return false;
-   else if (zero_if_use && list_is_singular(&instr->dest.dest.ssa.uses))
-      return false;
-
-   return true;
-}
-
 static inline bool
 is_used_once(nir_alu_instr *instr)
 {
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -36,6 +36,8 @@ struct spirv_supported_capabilities {
   bool address;
   bool atomic_storage;
   bool descriptor_array_dynamic_indexing;
+   bool descriptor_array_non_uniform_indexing;
+   bool descriptor_indexing;
   bool device_group;
   bool draw_parameters;
   bool float64;
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -494,6 +494,7 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
      break;

   case SpvOpDecorate:
+   case SpvOpDecorateId:
   case SpvOpMemberDecorate:
   case SpvOpDecorateStringGOOGLE:
   case SpvOpMemberDecorateStringGOOGLE:
@@ -503,6 +504,7 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
      struct vtn_decoration *dec = rzalloc(b, struct vtn_decoration);
      switch (opcode) {
      case SpvOpDecorate:
+      case SpvOpDecorateId:
      case SpvOpDecorateStringGOOGLE:
         dec->scope = VTN_DEC_DECORATION;
         break;
@@ -3699,12 +3701,26 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, SpvOp opcode,
         spv_check_supported(storage_8bit, cap);
         break;

+      case SpvCapabilityShaderNonUniformEXT:
+         spv_check_supported(descriptor_indexing, cap);
+         break;
+
      case SpvCapabilityInputAttachmentArrayDynamicIndexingEXT:
      case SpvCapabilityUniformTexelBufferArrayDynamicIndexingEXT:
      case SpvCapabilityStorageTexelBufferArrayDynamicIndexingEXT:
         spv_check_supported(descriptor_array_dynamic_indexing, cap);
         break;

+      case SpvCapabilityUniformBufferArrayNonUniformIndexingEXT:
+      case SpvCapabilitySampledImageArrayNonUniformIndexingEXT:
+      case SpvCapabilityStorageBufferArrayNonUniformIndexingEXT:
+      case SpvCapabilityStorageImageArrayNonUniformIndexingEXT:
+      case SpvCapabilityInputAttachmentArrayNonUniformIndexingEXT:
+      case SpvCapabilityUniformTexelBufferArrayNonUniformIndexingEXT:
+      case SpvCapabilityStorageTexelBufferArrayNonUniformIndexingEXT:
+         spv_check_supported(descriptor_array_non_uniform_indexing, cap);
+         break;
+
      case SpvCapabilityRuntimeDescriptorArrayEXT:
         spv_check_supported(runtime_descriptor_array, cap);
         break;
@@ -3760,6 +3776,7 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, SpvOp opcode,
   case SpvOpExecutionMode:
   case SpvOpDecorationGroup:
   case SpvOpDecorate:
+   case SpvOpDecorateId:
   case SpvOpMemberDecorate:
   case SpvOpGroupDecorate:
   case SpvOpGroupMemberDecorate:
@@ -3947,6 +3964,7 @@ vtn_handle_variable_or_type_instruction(struct vtn_builder *b, SpvOp opcode,
   case SpvOpMemberName:
   case SpvOpDecorationGroup:
   case SpvOpDecorate:
+   case SpvOpDecorateId:
   case SpvOpMemberDecorate:
   case SpvOpGroupDecorate:
   case SpvOpGroupMemberDecorate:
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -1433,6 +1433,37 @@ dri2_surf_update_fence_fd(_EGLContext *ctx,
   dri2_surface_set_out_fence_fd(surf, fence_fd);
 }

+EGLBoolean
+dri2_create_drawable(struct dri2_egl_display *dri2_dpy,
+                     const __DRIconfig *config,
+                     struct dri2_egl_surface *dri2_surf)
+{
+   __DRIcreateNewDrawableFunc createNewDrawable;
+   void *loaderPrivate = dri2_surf;
+
+   if (dri2_dpy->image_driver)
+      createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
+   else if (dri2_dpy->dri2)
+      createNewDrawable = dri2_dpy->dri2->createNewDrawable;
+   else if (dri2_dpy->swrast)
+      createNewDrawable = dri2_dpy->swrast->createNewDrawable;
+   else
+      return _eglError(EGL_BAD_ALLOC, "no createNewDrawable");
+
+   /* As always gbm is a bit special.. */
+#ifdef HAVE_DRM_PLATFORM
+   if (dri2_surf->gbm_surf)
+      loaderPrivate = dri2_surf->gbm_surf;
+#endif
+
+   dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen,
+                                                  config, loaderPrivate);
+   if (dri2_surf->dri_drawable == NULL)
+      return _eglError(EGL_BAD_ALLOC, "createNewDrawable");
+
+   return EGL_TRUE;
+}
+
 /**
 * Called via eglMakeCurrent(), drv->API.MakeCurrent().
 */
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -540,6 +540,11 @@ dri2_init_surface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
 void
 dri2_fini_surface(_EGLSurface *surf);

+EGLBoolean
+dri2_create_drawable(struct dri2_egl_display *dri2_dpy,
+                     const __DRIconfig *config,
+                     struct dri2_egl_surface *dri2_surf);
+
 static inline uint64_t
 combine_u32_into_u64(uint32_t hi, uint32_t lo)
 {
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -335,7 +335,6 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
 		    _EGLConfig *conf, void *native_window,
 		    const EGLint *attrib_list)
 {
-   __DRIcreateNewDrawableFunc createNewDrawable;
   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
   struct dri2_egl_config *dri2_conf = dri2_egl_config(conf);
   struct dri2_egl_surface *dri2_surf;
@@ -379,17 +378,8 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
      goto cleanup_surface;
   }

-   if (dri2_dpy->image_driver)
-      createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
-   else
-      createNewDrawable = dri2_dpy->dri2->createNewDrawable;
-
-   dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen, config,
-                                                  dri2_surf);
-   if (dri2_surf->dri_drawable == NULL) {
-      _eglError(EGL_BAD_ALLOC, "createNewDrawable");
+   if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
      goto cleanup_surface;
-   }

   if (window) {
      window->common.incRef(&window->common);
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -171,23 +171,8 @@ dri2_drm_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
   dri2_surf->base.Height = surf->base.height;
   surf->dri_private = dri2_surf;

-   if (dri2_dpy->dri2) {
-      dri2_surf->dri_drawable =
-         dri2_dpy->dri2->createNewDrawable(dri2_dpy->dri_screen, config,
-                                           dri2_surf->gbm_surf);
-
-   } else {
-      assert(dri2_dpy->swrast != NULL);
-
-      dri2_surf->dri_drawable =
-         dri2_dpy->swrast->createNewDrawable(dri2_dpy->dri_screen, config,
-                                             dri2_surf->gbm_surf);
-
-   }
-   if (dri2_surf->dri_drawable == NULL) {
-      _eglError(EGL_BAD_ALLOC, "createNewDrawable()");
+   if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
      goto cleanup_surf;
-   }

   return &dri2_surf->base;

--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -135,13 +135,8 @@ dri2_surfaceless_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
      goto cleanup_surface;
   }

-   dri2_surf->dri_drawable =
-      dri2_dpy->image_driver->createNewDrawable(dri2_dpy->dri_screen, config,
-                                                dri2_surf);
-   if (dri2_surf->dri_drawable == NULL) {
-      _eglError(EGL_BAD_ALLOC, "image->createNewDrawable");
+   if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
      goto cleanup_surface;
-    }

   if (conf->RedSize == 5)
      dri2_surf->visual = __DRI_IMAGE_FORMAT_RGB565;
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -272,7 +272,6 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
                              _EGLConfig *conf, void *native_window,
                              const EGLint *attrib_list)
 {
-   __DRIcreateNewDrawableFunc createNewDrawable;
   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
   struct dri2_egl_config *dri2_conf = dri2_egl_config(conf);
   struct wl_egl_window *window = native_window;
@@ -349,19 +348,8 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay *disp,
   if (dri2_dpy->flush)
      dri2_surf->wl_win->resize_callback = resize_callback;

-   if (dri2_dpy->image_driver)
-      createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
-   else if (dri2_dpy->dri2)
-      createNewDrawable = dri2_dpy->dri2->createNewDrawable;
-   else
-      createNewDrawable = dri2_dpy->swrast->createNewDrawable;
-
-   dri2_surf->dri_drawable = (*createNewDrawable)(dri2_dpy->dri_screen, config,
-                                                  dri2_surf);
-    if (dri2_surf->dri_drawable == NULL) {
-      _eglError(EGL_BAD_ALLOC, "createNewDrawable");
+   if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
       goto cleanup_surf_wrapper;
-    }

   dri2_surf->base.SwapInterval = dri2_dpy->default_swap_interval;

--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -261,7 +261,7 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,

   (void) drv;

-   dri2_surf = malloc(sizeof *dri2_surf);
+   dri2_surf = calloc(1, sizeof *dri2_surf);
   if (!dri2_surf) {
      _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
      return NULL;
@@ -289,21 +289,8 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
      goto cleanup_pixmap;
   }

-   if (dri2_dpy->dri2) {
-      dri2_surf->dri_drawable =
-         dri2_dpy->dri2->createNewDrawable(dri2_dpy->dri_screen, config,
-                                           dri2_surf);
-   } else {
-      assert(dri2_dpy->swrast);
-      dri2_surf->dri_drawable = 
-         dri2_dpy->swrast->createNewDrawable(dri2_dpy->dri_screen, config,
-                                             dri2_surf);
-   }
-
-   if (dri2_surf->dri_drawable == NULL) {
-      _eglError(EGL_BAD_ALLOC, "dri2->createNewDrawable");
+   if (!dri2_create_drawable(dri2_dpy, config, dri2_surf))
      goto cleanup_pixmap;
-   }

   if (type != EGL_PBUFFER_BIT) {
      cookie = xcb_get_geometry (dri2_dpy->conn, dri2_surf->drawable);
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -178,9 +178,12 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy,
          *     is supported for OpenGL contexts, and requesting a
          *     forward-compatible context for OpenGL versions less than 3.0
          *     will generate an error."
+          *
+          * Note: since the forward-compatible flag can be set more than one way,
+          *       the OpenGL version check is performed once, below.
          */
         if ((val & EGL_CONTEXT_OPENGL_FORWARD_COMPATIBLE_BIT_KHR) &&
-             (api != EGL_OPENGL_API || ctx->ClientMajorVersion < 3)) {
+              api != EGL_OPENGL_API) {
            err = EGL_BAD_ATTRIBUTE;
            break;
         }
--- a/src/egl/main/egldevice.c
+++ b/src/egl/main/egldevice.c
@@ -108,9 +108,9 @@ static int
 _eglAddDRMDevice(drmDevicePtr device, _EGLDevice **out_dev)
 {
   _EGLDevice *dev;
+   const int wanted_nodes = 1 << DRM_NODE_RENDER | 1 << DRM_NODE_PRIMARY;

-   if ((device->available_nodes & (1 << DRM_NODE_PRIMARY |
-                                   1 << DRM_NODE_RENDER)) == 0)
+   if ((device->available_nodes & wanted_nodes) != wanted_nodes)
      return -1;

   dev = _eglGlobal.DeviceList;
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -686,8 +686,8 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
 		base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
 		base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
 	} else {
-		base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
-		base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
+		base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
+		base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
 	}

 	/* note: on 32bit gpu's base_hi is ignored and DCE'd */
@@ -1511,6 +1511,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 		barrier->cat7.g = true;
 		barrier->cat7.r = true;
 		barrier->cat7.w = true;
+		barrier->cat7.l = true;
 		barrier->barrier_class = IR3_BARRIER_IMAGE_W |
 				IR3_BARRIER_BUFFER_W;
 		barrier->barrier_conflict =
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -950,6 +950,8 @@ draw_set_mapped_so_targets(struct draw_context *draw,
 {
   int i;

+   draw_do_flush( draw, DRAW_FLUSH_STATE_CHANGE );
+
   for (i = 0; i < num_targets; i++)
      draw->so.targets[i] = targets[i];
   for (i = num_targets; i < PIPE_MAX_SO_BUFFERS; i++)
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -2059,7 +2059,8 @@ void util_blitter_generate_mipmap(struct blitter_context *blitter,
      target = PIPE_TEXTURE_2D_ARRAY;

   assert(tex->nr_samples <= 1);
-   assert(!util_format_has_stencil(desc));
+   /* Disallow stencil formats without depth. */
+   assert(!util_format_has_stencil(desc) || util_format_has_depth(desc));

   is_depth = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS;

--- a/src/gallium/auxiliary/util/u_screen.c
+++ b/src/gallium/auxiliary/util/u_screen.c
@@ -337,6 +337,9 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
      return 1;

+   case PIPE_CAP_MAX_VARYINGS:
+      return 8;
+
   default:
      unreachable("bad PIPE_CAP_*");
   }
--- a/src/gallium/auxiliary/util/u_screen.h
+++ b/src/gallium/auxiliary/util/u_screen.h
@@ -24,6 +24,14 @@
 struct pipe_screen;
 enum pipe_cap;

+#ifdef __cplusplus
+extern "C" {
+#endif
+
 int
 u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
                                 enum pipe_cap param);
+
+#ifdef __cplusplus
+};
+#endif
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -592,12 +592,12 @@ etna_emit_state(struct etna_context *ctx)
   static const uint32_t uniform_dirty_bits =
      ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;

-   if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
+   if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
      etna_uniforms_write(
         ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX],
         ctx->shader_state.VS_UNIFORMS, &ctx->shader_state.vs_uniforms_size);

-   if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
+   if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
      etna_uniforms_write(
         ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT],
         ctx->shader_state.PS_UNIFORMS, &ctx->shader_state.ps_uniforms_size);
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -610,6 +610,7 @@ etna_resource_get_handle(struct pipe_screen *pscreen,
      rsc = etna_resource(rsc->external);

   handle->stride = rsc->levels[0].stride;
+   handle->offset = rsc->levels[0].offset;
   handle->modifier = layout_to_modifier(rsc->layout);

   if (handle->type == WINSYS_HANDLE_TYPE_SHARED) {
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -588,6 +588,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
 	blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
 	blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);

+	/* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
+	 * small render targets.  But since we align pitch to binw I think
+	 * we can get away avoiding GPU hangs a simpler way, by just rounding
+	 * up the blit scissor:
+	 */
+	blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
+
 	OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 	OUT_RING(ring,
 			 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1837,18 +1837,17 @@ static void r600_emit_sampler_states(struct r600_context *rctx,

 		/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
 		 * filtering between layers.
-		 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
 		 */
-		if (rview) {
-			enum pipe_texture_target target = rview->base.texture->target;
-			if (target == PIPE_TEXTURE_1D_ARRAY ||
-			    target == PIPE_TEXTURE_2D_ARRAY) {
-				rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
-				texinfo->is_array_sampler[i] = true;
-			} else {
-				rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
-				texinfo->is_array_sampler[i] = false;
-			}
+		enum pipe_texture_target target = PIPE_BUFFER;
+		if (rview)
+			target = rview->base.texture->target;
+		if (target == PIPE_TEXTURE_1D_ARRAY ||
+		    target == PIPE_TEXTURE_2D_ARRAY) {
+			rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
+			texinfo->is_array_sampler[i] = true;
+		} else {
+			rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
+			texinfo->is_array_sampler[i] = false;
 		}

 		radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -14,6 +14,7 @@ C_SOURCES := \
 	si_compute_blit.c \
 	si_cp_dma.c \
 	si_debug.c \
+	si_debug_options.h \
 	si_descriptors.c \
 	si_dma.c \
 	si_dma_cs.c \
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -11,6 +11,14 @@ DRI_CONF_SECTION_PERFORMANCE
 DRI_CONF_SECTION_END

 DRI_CONF_SECTION_DEBUG
-   DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
-   DRI_CONF_RADEONSI_ENABLE_NIR("false")
+
+//= BEGIN VERBATIM
+#define OPT_BOOL(name, dflt, description) \
+	DRI_CONF_OPT_BEGIN_B(radeonsi_##name, #dflt) \
+		DRI_CONF_DESC(en, description) \
+	DRI_CONF_OPT_END
+
+#include "radeonsi/si_debug_options.h"
+//= END VERBATIM
+
 DRI_CONF_SECTION_END
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -647,7 +647,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		 * This hack decreases back-to-back ClearDepth performance.
 		 */
 		if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
-		    sctx->screen->clear_db_cache_before_clear)
+		    sctx->screen->options.clear_db_cache_before_clear)
 			sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
 	}

--- a/src/gallium/drivers/radeonsi/si_debug_options.h
+++ b/src/gallium/drivers/radeonsi/si_debug_options.h
@@ -0,0 +1,4 @@
+OPT_BOOL(clear_db_cache_before_clear, false, "Clear DB cache before fast depth clear")
+OPT_BOOL(enable_nir, false, "Enable NIR")
+
+#undef OPT_BOOL
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -208,7 +208,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 				RADEON_SPARSE_PAGE_SIZE : 0;

 	case PIPE_CAP_PACKED_UNIFORMS:
-		if (sscreen->debug_flags & DBG(NIR))
+		if (sscreen->options.enable_nir)
 			return 1;
 		return 0;

@@ -423,11 +423,11 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
 	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 		return SI_NUM_IMAGES;
 	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
-		if (sscreen->debug_flags & DBG(NIR))
+		if (sscreen->options.enable_nir)
 			return 0;
 		return 32;
 	case PIPE_SHADER_CAP_PREFERRED_IR:
-		if (sscreen->debug_flags & DBG(NIR))
+		if (sscreen->options.enable_nir)
 			return PIPE_SHADER_IR_NIR;
 		return PIPE_SHADER_IR_TGSI;
 	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -61,7 +61,6 @@ static const struct debug_named_value debug_options[] = {

 	/* Shader compiler options (with no effect on the shader cache): */
 	{ "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
-	{ "nir", DBG(NIR), "Enable experimental NIR shaders" },
 	{ "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
 	{ "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },

@@ -807,8 +806,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
 	#define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) |	\
 			   DBG(SI_SCHED) |			\
 			   DBG(GISEL) |				\
-			   DBG(UNSAFE_MATH) |			\
-			   DBG(NIR))
+			   DBG(UNSAFE_MATH))
 	uint64_t shader_debug_flags = sscreen->debug_flags &
 		ALL_FLAGS;

@@ -816,7 +814,11 @@ static void si_disk_cache_create(struct si_screen *sscreen)
 	 * how 32-bit addresses are expanded to 64 bits.
 	 */
 	STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
-	shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
+	assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
+	shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
+
+	if (sscreen->options.enable_nir)
+		shader_debug_flags |= 1ull << 48;

 	sscreen->disk_shader_cache =
 		disk_cache_create(sscreen->info.name,
@@ -868,8 +870,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 		sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
 	if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
 		sscreen->debug_flags |= DBG(SI_SCHED);
-	if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
-		sscreen->debug_flags |= DBG(NIR);

 	if (sscreen->debug_flags & DBG(INFO))
 		ac_print_gpu_info(&sscreen->info);
@@ -1017,8 +1017,16 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 		driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
 	sscreen->commutative_blend_add =
 		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
-	sscreen->clear_db_cache_before_clear =
-		driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
+
+	{
+#define OPT_BOOL(name, dflt, description) \
+		sscreen->options.name = \
+			driQueryOptionb(config->options, "radeonsi_"#name);
+#include "si_debug_options.h"
+	}
+
+	sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
+					sscreen->info.family == CHIP_RAVEN;
 	sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
 					    sscreen->info.family <= CHIP_POLARIS12) ||
 					   sscreen->info.family == CHIP_VEGA10 ||
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -133,7 +133,6 @@ enum {

 	/* Shader compiler options (with no effect on the shader cache): */
 	DBG_CHECK_IR,
-	DBG_NIR,
 	DBG_MONOLITHIC_SHADERS,
 	DBG_NO_OPT_VARIANT,

@@ -445,7 +444,7 @@ struct si_screen {
 	bool				has_out_of_order_rast;
 	bool				assume_no_z_fights;
 	bool				commutative_blend_add;
-	bool				clear_db_cache_before_clear;
+	bool				has_gfx9_scissor_bug;
 	bool				has_msaa_sample_loc_bug;
 	bool				has_ls_vgpr_init_bug;
 	bool				has_dcc_constant_encode;
@@ -453,6 +452,11 @@ struct si_screen {
 	bool				dfsm_allowed;
 	bool				llvm_has_working_vgpr_indexing;

+	struct {
+#define OPT_BOOL(name, dflt, description) bool name:1;
+#include "si_debug_options.h"
+	} options;
+
 	/* Whether shaders are monolithic (1-part) or separate (3-part). */
 	bool				use_monolithic_shaders;
 	bool				record_llvm_ir;
@@ -1054,7 +1058,7 @@ struct si_context {
 	unsigned			num_resident_handles;
 	uint64_t			num_alloc_tex_transfer_bytes;
 	unsigned			last_tex_ps_draw_ratio; /* for query */
-	unsigned			context_roll_counter;
+	unsigned			context_roll;

 	/* Queries. */
 	/* Maintain the list of active queries for pausing between IBs. */
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -256,7 +256,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
 					    sx_blend_opt_control);
 	}
 	if (initial_cdw != cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 /*
@@ -792,7 +792,7 @@ static void si_emit_clip_regs(struct si_context *sctx)
 		S_028810_CLIP_DISABLE(window_space));

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 /*
@@ -1446,7 +1446,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
 				   SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 /*
@@ -3527,7 +3527,7 @@ static void si_emit_msaa_config(struct si_context *sctx)
 				   SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);

 	if (initial_cdw != cs->current.cdw) {
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;

 		/* GFX9: Flush DFSM when the AA mode changes. */
 		if (sctx->screen->dfsm_allowed) {
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -224,7 +224,8 @@ static inline unsigned si_atoms_that_always_roll_context(void)
 		SI_ATOM_BIT(scissors) |
 		SI_ATOM_BIT(viewports) |
 		SI_ATOM_BIT(stencil_ref) |
-		SI_ATOM_BIT(scratch_state));
+		SI_ATOM_BIT(scratch_state) |
+		SI_ATOM_BIT(window_rectangles));
 }

 struct si_shader_data {
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -321,7 +321,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
 				   S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
 				   S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 void si_emit_dpbb_state(struct si_context *sctx)
@@ -443,5 +443,5 @@ void si_emit_dpbb_state(struct si_context *sctx)
 				   S_028060_PUNCHOUT_MODE(punchout_mode) |
 				   S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -66,7 +66,7 @@ static unsigned si_conv_pipe_prim(unsigned mode)
 * The information about LDS and other non-compile-time parameters is then
 * written to userdata SGPRs.
 */
-static bool si_emit_derived_tess_state(struct si_context *sctx,
+static void si_emit_derived_tess_state(struct si_context *sctx,
 				       const struct pipe_draw_info *info,
 				       unsigned *num_patches)
 {
@@ -110,7 +110,7 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
 	    (!has_primid_instancing_bug ||
 	     (sctx->last_tess_uses_primid == tess_uses_primid))) {
 		*num_patches = sctx->last_num_patches;
-		return false;
+		return;
 	}

 	sctx->last_ls = ls_current;
@@ -305,9 +305,8 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
 					       ls_hs_config);
 		}
 		sctx->last_ls_hs_config = ls_hs_config;
-		return true; /* true if the context rolls */
+		sctx->context_roll = true;
 	}
-	return false;
 }

 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
@@ -541,7 +540,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 }

 /* rast_prim is the primitive type after GS. */
-static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
+static void si_emit_rasterizer_prim_state(struct si_context *sctx)
 {
 	struct radeon_cmdbuf *cs = sctx->gfx_cs;
 	enum pipe_prim_type rast_prim = sctx->current_rast_prim;
@@ -549,11 +548,11 @@ static bool si_emit_rasterizer_prim_state(struct si_context *sctx)

 	/* Skip this if not rendering lines. */
 	if (!util_prim_is_lines(rast_prim))
-		return false;
+		return;

 	if (rast_prim == sctx->last_rast_prim &&
 	    rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
-		return false;
+		return;

 	/* For lines, reset the stipple pattern at each primitive. Otherwise,
 	 * reset the stipple pattern at each packet (line strips, line loops).
@@ -564,7 +563,7 @@ static bool si_emit_rasterizer_prim_state(struct si_context *sctx)

 	sctx->last_rast_prim = rast_prim;
 	sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
-	return true; /* true if the context rolls */
+	sctx->context_roll = true;
 }

 static void si_emit_vs_state(struct si_context *sctx,
@@ -659,6 +658,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
 		radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
 				       info->restart_index);
 		sctx->last_restart_index = info->restart_index;
+		sctx->context_roll = true;
 	}
 }

@@ -896,6 +896,10 @@ static void si_emit_surface_sync(struct si_context *sctx,
 		radeon_emit(cs, 0);               /* CP_COHER_BASE */
 		radeon_emit(cs, 0x0000000A);      /* POLL_INTERVAL */
 	}
+
+	/* ACQUIRE_MEM has an implicit context roll if the current context
+	 * is busy. */
+	sctx->context_roll = true;
 }

 void si_emit_cache_flush(struct si_context *sctx)
@@ -1210,26 +1214,10 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
 			       unsigned skip_atom_mask)
 {
 	unsigned num_patches = 0;
-	/* Vega10/Raven scissor bug workaround. When any context register is
-	 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
-	 * registers must be written too.
-	 */
-	bool handle_scissor_bug = (sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
-				  !si_is_atom_dirty(sctx, &sctx->atoms.s.scissors);
-	bool context_roll = false; /* set correctly for GFX9 only */

-	context_roll |= si_emit_rasterizer_prim_state(sctx);
+	si_emit_rasterizer_prim_state(sctx);
 	if (sctx->tes_shader.cso)
-		context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
-
-	if (handle_scissor_bug &&
-	    (info->count_from_stream_output ||
-	     sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
-	     sctx->dirty_states & si_states_that_always_roll_context() ||
-	     si_prim_restart_index_changed(sctx, info)))
-		context_roll = true;
-
-	sctx->context_roll_counter = 0;
+		si_emit_derived_tess_state(sctx, info, &num_patches);

 	/* Emit state atoms. */
 	unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
@@ -1252,12 +1240,6 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
 	}
 	sctx->dirty_states = 0;

-	if (handle_scissor_bug &&
-	    (context_roll || sctx->context_roll_counter)) {
-		sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
-		sctx->atoms.s.scissors.emit(sctx);
-	}
-
 	/* Emit draw states. */
 	si_emit_vs_state(sctx, info);
 	si_emit_draw_registers(sctx, info, num_patches);
@@ -1456,6 +1438,22 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
 	if (!si_upload_vertex_buffer_descriptors(sctx))
 		return;

+	/* Vega10/Raven scissor bug workaround. When any context register is
+	 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
+	 * registers must be written too.
+	 */
+	bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
+	unsigned masked_atoms = 0;
+
+	if (has_gfx9_scissor_bug) {
+		masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
+
+		if (info->count_from_stream_output ||
+		    sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
+		    sctx->dirty_states & si_states_that_always_roll_context())
+			sctx->context_roll = true;
+	}
+
 	/* Use optimal packet order based on whether we need to sync the pipeline. */
 	if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
 				      SI_CONTEXT_FLUSH_AND_INV_DB |
@@ -1466,8 +1464,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
 		 * Then draw and prefetch at the end. This ensures that the time
 		 * the CUs are idle is very short.
 		 */
-		unsigned masked_atoms = 0;
-
 		if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
 			masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);

@@ -1481,6 +1477,13 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i

 		if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
 			sctx->atoms.s.render_cond.emit(sctx);
+
+		if (has_gfx9_scissor_bug &&
+		    (sctx->context_roll ||
+		     si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
+			sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+			sctx->atoms.s.scissors.emit(sctx);
+		}
 		sctx->dirty_atoms = 0;

 		si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
@@ -1505,7 +1508,16 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
 		if (!si_upload_graphics_shader_descriptors(sctx))
 			return;

-		si_emit_all_states(sctx, info, 0);
+		si_emit_all_states(sctx, info, masked_atoms);
+
+		if (has_gfx9_scissor_bug &&
+		    (sctx->context_roll ||
+		     si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
+			sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+			sctx->atoms.s.scissors.emit(sctx);
+		}
+		sctx->dirty_atoms = 0;
+
 		si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);

 		/* Prefetch the remaining shaders after the draw has been
@@ -1514,6 +1526,9 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
 			cik_emit_prefetch_L2(sctx, false);
 	}

+	/* Clear the context roll flag after the draw call. */
+	sctx->context_roll = false;
+
 	if (unlikely(sctx->current_saved_cs)) {
 		si_trace_emit(sctx);
 		si_log_draw_state(sctx, sctx->log);
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -576,7 +576,7 @@ static void si_emit_shader_es(struct si_context *sctx)
 					   shader->vgt_vertex_reuse_block_cntl);

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@@ -825,7 +825,7 @@ static void si_emit_shader_gs(struct si_context *sctx)
 	}

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
@@ -1002,7 +1002,7 @@ static void si_emit_shader_vs(struct si_context *sctx)
 					   shader->vgt_vertex_reuse_block_cntl);

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 /**
@@ -1194,7 +1194,7 @@ static void si_emit_shader_ps(struct si_context *sctx)
 				   shader->ctx_reg.ps.cb_shader_mask);

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 static void si_shader_ps(struct si_shader *shader)
@@ -2869,7 +2869,7 @@ static void si_emit_spi_map(struct si_context *sctx)
 				    sctx->tracked_regs.spi_ps_input_cntl, num_interp);

 	if (initial_cdw != sctx->gfx_cs->current.cdw)
-		sctx->context_roll_counter++;
+		sctx->context_roll = true;
 }

 /**
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -303,6 +303,7 @@ void si_emit_streamout_end(struct si_context *sctx)
 		 * buffer bound. This ensures that the primitives-emitted query
 		 * won't increment. */
 		radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
+		sctx->context_roll = true;

 		t[i]->buf_filled_size_valid = true;
 	}
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -283,7 +283,7 @@ static void si_emit_guardband(struct si_context *ctx)
 				   S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
 						       vp_as_scissor.quant_mode));
 	if (initial_cdw != ctx->gfx_cs->current.cdw)
-		ctx->context_roll_counter++;
+		ctx->context_roll = true;
 }

 static void si_emit_scissors(struct si_context *ctx)
--- a/src/gallium/drivers/softpipe/sp_setup.c
+++ b/src/gallium/drivers/softpipe/sp_setup.c
@@ -390,17 +390,6 @@ setup_sort_vertices(struct setup_context *setup,
 	 return FALSE;
   }

-
-   /* Prepare pixel offset for rasterisation:
-    *  - pixel center (0.5, 0.5) for GL, or
-    *  - assume (0.0, 0.0) for other APIs.
-    */
-   if (setup->softpipe->rasterizer->half_pixel_center) {
-      setup->pixel_offset = 0.5f;
-   } else {
-      setup->pixel_offset = 0.0f;
-   }
-
   return TRUE;
 }

@@ -1476,6 +1465,16 @@ sp_setup_prepare(struct setup_context *setup)
      }
   }

+   /* Prepare pixel offset for rasterisation:
+    *  - pixel center (0.5, 0.5) for GL, or
+    *  - assume (0.0, 0.0) for other APIs.
+    */
+   if (setup->softpipe->rasterizer->half_pixel_center) {
+      setup->pixel_offset = 0.5f;
+   } else {
+      setup->pixel_offset = 0.0f;
+   }
+
   setup->max_layer = max_layer;

   sp->quad.first->begin( sp->quad.first );
--- a/src/gallium/drivers/svga/Makefile.sources
+++ b/src/gallium/drivers/svga/Makefile.sources
@@ -15,8 +15,6 @@ C_SOURCES := \
 	svga_hw_reg.h \
 	svga_link.c \
 	svga_link.h \
-	svga_msg.c \
-	svga_msg.h \
 	svga_mksstats.h \
 	svga_pipe_blend.c \
 	svga_pipe_blit.c \
--- a/src/gallium/drivers/svga/meson.build
+++ b/src/gallium/drivers/svga/meson.build
@@ -27,7 +27,6 @@ files_svga = files(
  'svga_draw_elements.c',
  'svga_format.c',
  'svga_link.c',
-  'svga_msg.c',
  'svga_pipe_blend.c',
  'svga_pipe_blit.c',
  'svga_pipe_clear.c',
--- a/src/gallium/drivers/svga/svga_draw.c
+++ b/src/gallium/drivers/svga/svga_draw.c
@@ -619,11 +619,11 @@ draw_vgpu10(struct svga_hwtnl *hwtnl,
         vbuffer_attrs[i].sid = 0;
      }

-      /* If we haven't yet emitted a drawing command or if any
-       * vertex buffer state is changing, issue that state now.
+      /* If any of the vertex buffer state has changed, issue
+       * the SetVertexBuffers command. Otherwise, we will just
+       * need to rebind the resources.
       */
-      if (((hwtnl->cmd.swc->hints & SVGA_HINT_FLAG_CAN_PRE_FLUSH) == 0) ||
-          vbuf_count != svga->state.hw_draw.num_vbuffers ||
+      if (vbuf_count != svga->state.hw_draw.num_vbuffers ||
          !vertex_buffers_equal(vbuf_count,
                                vbuffer_attrs,
                                vbuffers,
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -37,7 +37,6 @@
 #include "svga_public.h"
 #include "svga_context.h"
 #include "svga_format.h"
-#include "svga_msg.h"
 #include "svga_screen.h"
 #include "svga_tgsi.h"
 #include "svga_resource_texture.h"
@@ -891,17 +890,18 @@ svga_get_driver_query_info(struct pipe_screen *screen,
 static void
 init_logging(struct pipe_screen *screen)
 {
+   struct svga_screen *svgascreen = svga_screen(screen);
   static const char *log_prefix = "Mesa: ";
   char host_log[1000];

   /* Log Version to Host */
   util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
-                 "%s%s", log_prefix, svga_get_name(screen));
-   svga_host_log(host_log);
+                 "%s%s\n", log_prefix, svga_get_name(screen));
+   svgascreen->sws->host_log(svgascreen->sws, host_log);

   util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
                 "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
-   svga_host_log(host_log);
+   svgascreen->sws->host_log(svgascreen->sws, host_log);

   /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
    * line (program name and arguments).
@@ -910,13 +910,23 @@ init_logging(struct pipe_screen *screen)
      char cmdline[1000];
      if (os_get_command_line(cmdline, sizeof(cmdline))) {
         util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
-                       "%s%s", log_prefix, cmdline);
-         svga_host_log(host_log);
+                       "%s%s\n", log_prefix, cmdline);
+         svgascreen->sws->host_log(svgascreen->sws, host_log);
      }
   }
 }


+/**
+ * no-op logging function to use when SVGA_NO_LOGGING is set.
+ */
+static void
+nop_host_log(struct svga_winsys_screen *sws, const char *message)
+{
+   /* nothing */
+}
+
+
 static void
 svga_destroy_screen( struct pipe_screen *screen )
 {
@@ -1134,7 +1144,11 @@ svga_screen_create(struct svga_winsys_screen *sws)

   svga_screen_cache_init(svgascreen);

-   init_logging(screen);
+   if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) {
+      svgascreen->sws->host_log = nop_host_log;
+   } else {
+      init_logging(screen);
+   }

   return screen;
 error2:
--- a/src/gallium/drivers/svga/svga_winsys.h
+++ b/src/gallium/drivers/svga/svga_winsys.h
@@ -753,6 +753,11 @@ struct svga_winsys_screen
   void
   (*stats_time_pop)();

+   /**
+    * Send a host log message
+    */
+   void
+   (*host_log)(struct svga_winsys_screen *sws, const char *message);

   /** Have VGPU v10 hardware? */
   boolean have_vgpu10;
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -565,68 +565,3 @@ using Vec4 = typename SIMD_T::Vec4;
 template <typename SIMD_T>
 using Mask = typename SIMD_T::Mask;

-template <typename SIMD_T>
-struct SIMDVecEqual
-{
-    INLINE bool operator()(Integer<SIMD_T> a, Integer<SIMD_T> b) const
-    {
-        Integer<SIMD_T> c = SIMD_T::xor_si(a, b);
-        return SIMD_T::testz_si(c, c);
-    }
-
-    INLINE bool operator()(Float<SIMD_T> a, Float<SIMD_T> b) const
-    {
-        return this->operator()(SIMD_T::castps_si(a), SIMD_T::castps_si(b));
-    }
-
-    INLINE bool operator()(Double<SIMD_T> a, Double<SIMD_T> b) const
-    {
-        return this->operator()(SIMD_T::castpd_si(a), SIMD_T::castpd_si(b));
-    }
-};
-
-template <typename SIMD_T>
-struct SIMDVecHash
-{
-    INLINE uint32_t operator()(Integer<SIMD_T> val) const
-    {
-#if defined(_WIN64) || !defined(_WIN32) // assume non-Windows is always 64-bit
-        static_assert(sizeof(void*) == 8, "This path only meant for 64-bit code");
-
-        uint64_t              crc32          = 0;
-        const uint64_t*       pData          = reinterpret_cast<const uint64_t*>(&val);
-        static const uint32_t loopIterations = sizeof(val) / sizeof(void*);
-        static_assert(loopIterations * sizeof(void*) == sizeof(val), "bad vector size");
-
-        for (uint32_t i = 0; i < loopIterations; ++i)
-        {
-            crc32 = _mm_crc32_u64(crc32, pData[i]);
-        }
-
-        return static_cast<uint32_t>(crc32);
-#else
-        static_assert(sizeof(void*) == 4, "This path only meant for 32-bit code");
-
-        uint32_t crc32 = 0;
-        const uint32_t* pData = reinterpret_cast<const uint32_t*>(&val);
-        static const uint32_t loopIterations = sizeof(val) / sizeof(void*);
-        static_assert(loopIterations * sizeof(void*) == sizeof(val), "bad vector size");
-
-        for (uint32_t i = 0; i < loopIterations; ++i)
-        {
-            crc32 = _mm_crc32_u32(crc32, pData[i]);
-        }
-
-        return crc32;
-#endif
-    };
-
-    INLINE uint32_t operator()(Float<SIMD_T> val) const
-    {
-        return operator()(SIMD_T::castps_si(val));
-    };
-    INLINE uint32_t operator()(Double<SIMD_T> val) const
-    {
-        return operator()(SIMD_T::castpd_si(val));
-    }
-};
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -36,6 +36,7 @@
 #include "util/u_cpu_detect.h"
 #include "util/u_format_s3tc.h"
 #include "util/u_string.h"
+#include "util/u_screen.h"

 #include "state_tracker/sw_winsys.h"

@@ -387,11 +388,9 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)

      return (int)(system_memory >> 20);
   }
+   default:
+      return u_pipe_screen_get_param_defaults(screen, param);
   }
-
-   /* should only get here on unhandled cases */
-   debug_printf("Unexpected PIPE_CAP %d query\n", param);
-   return 0;
 }

 static int
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -358,6 +358,7 @@ struct virgl_caps_v2 {
        uint32_t max_atomic_counter_buffers[6];
        uint32_t max_combined_atomic_counters;
        uint32_t max_combined_atomic_counter_buffers;
+        uint32_t host_feature_check_version;
 };

 union virgl_caps {
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -347,7 +347,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
   case PIPE_CAP_NATIVE_FENCE_FD:
      return vscreen->vws->supports_fences;
   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
-      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL;
+      return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
+            (vscreen->caps.caps.v2.host_feature_check_version < 1);
   default:
      return u_pipe_screen_get_param_defaults(screen, param);
   }
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -150,5 +150,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
   caps->caps.v2.max_image_samples = 0;
   caps->caps.v2.max_compute_work_group_invocations = 0;
   caps->caps.v2.max_compute_shared_memory_size = 0;
+   caps->caps.v2.host_feature_check_version = 0;
 }
 #endif
--- a/src/gallium/state_trackers/glx/xlib/meson.build
+++ b/src/gallium/state_trackers/glx/xlib/meson.build
@@ -23,5 +23,5 @@ libxlib = static_library(
  files('glx_api.c', 'glx_getproc.c', 'glx_usefont.c', 'xm_api.c', 'xm_st.c'),
  c_args : c_vis_args,
  include_directories : [inc_common, inc_mapi, inc_mesa],
-  dependencies : [dep_x11, dep_xext, dep_xcb],
+  dependencies : [dep_x11, dep_xext, dep_xcb, dep_glproto],
 )
--- a/src/gallium/state_trackers/nine/swapchain9.c
+++ b/src/gallium/state_trackers/nine/swapchain9.c
@@ -133,6 +133,13 @@ D3DWindowBuffer_release(struct NineSwapChain9 *This,
                        D3DWindowBuffer *present_handle)
 {
    int i;
+
+    /* IsBufferReleased API not available */
+    if (This->base.device->minor_version_num <= 2) {
+        ID3DPresent_DestroyD3DWindowBuffer(This->present, present_handle);
+        return;
+    }
+
    /* Add it to the 'pending release' list */
    for (i = 0; i < D3DPRESENT_BACK_BUFFERS_MAX_EX + 1; i++) {
        if (!This->present_handles_pending_release[i]) {
@@ -754,8 +761,11 @@ present( struct NineSwapChain9 *This,
    (void)target_depth;

    /* Can happen with old Wine (presentation can still succeed),
-     * or at window destruction. */
-    if (FAILED(hr) || target_width == 0 || target_height == 0) {
+     * or at window destruction.
+     * Also disable for very old wine as D3DWindowBuffer_release
+     * cannot do the DestroyD3DWindowBuffer workaround. */
+    if (FAILED(hr) || target_width == 0 || target_height == 0 ||
+        This->base.device->minor_version_num <= 2) {
        target_width = resource->width0;
        target_height = resource->height0;
    }
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -63,6 +63,7 @@ libgallium_dri = shared_library(
  # Will be deleted during installation, see install_megadrivers.py
  install : true,
  install_dir : dri_drivers_path,
+  name_suffix : 'so',
 )

 foreach d : [[with_gallium_kmsro, 'pl111_dri.so'],
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -43,9 +43,9 @@ libosmesa = shared_library(
    inc_gallium_drivers,
  ],
  link_depends : osmesa_link_deps,
-  link_whole : [libosmesa_st],
+  link_whole : [libosmesa_st, libglapi_static],
  link_with : [
-    libmesa_gallium, libgallium, libglapi_static, libws_null, osmesa_link_with,
+    libmesa_gallium, libgallium, libws_null, osmesa_link_with,
  ],
  dependencies : [
    dep_selinux, dep_thread, dep_clock, dep_unwind,
--- a/src/gallium/targets/va/meson.build
+++ b/src/gallium/targets/va/meson.build
@@ -52,6 +52,7 @@ libva_gallium = shared_library(
  # Will be deleted during installation, see install_megadrivers.py
  install : true,
  install_dir : va_drivers_path,
+  name_suffix : 'so',
 )

 foreach d : [[with_gallium_r600, 'r600'],
--- a/src/gallium/targets/vdpau/meson.build
+++ b/src/gallium/targets/vdpau/meson.build
@@ -58,6 +58,7 @@ libvdpau_gallium = shared_library(
  # Will be deleted during installation, see install_megadrivers.py
  install : true,
  install_dir : vdpau_drivers_path,
+  name_suffix : 'so',
 )
 foreach d : [[with_gallium_r300, 'r300'],
             [with_gallium_r600, 'r600'],
--- a/src/gallium/targets/xvmc/meson.build
+++ b/src/gallium/targets/xvmc/meson.build
@@ -50,6 +50,7 @@ libxvmc_gallium = shared_library(
  # Will be deleted during installation, see install_megadrivers.py
  install : true,
  install_dir : xvmc_drivers_path,
+  name_suffix : 'so',
 )

 foreach d : [[with_gallium_r600, 'r600'], [with_gallium_nouveau, 'nouveau']]
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -386,7 +386,8 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
-          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
+          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC &&
+          cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG;
 }

 static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs)
--- a/src/gallium/winsys/svga/drm/Makefile.sources
+++ b/src/gallium/winsys/svga/drm/Makefile.sources
@@ -8,6 +8,8 @@ C_SOURCES := \
 	vmw_fence.c \
 	vmw_fence.h \
 	vmwgfx_drm.h \
+	vmw_msg.c \
+	vmw_msg.h \
 	vmw_screen.c \
 	vmw_screen_dri.c \
 	vmw_screen.h \
--- a/src/gallium/winsys/svga/drm/meson.build
+++ b/src/gallium/winsys/svga/drm/meson.build
@@ -23,6 +23,7 @@ files_svgadrm = files(
  'vmw_buffer.c',
  'vmw_context.c',
  'vmw_fence.c',
+  'vmw_msg.c',
  'vmw_screen.c',
  'vmw_screen_dri.c',
  'vmw_screen_ioctl.c',
--- a/src/gallium/winsys/svga/drm/vmw_msg.c
+++ b/src/gallium/winsys/svga/drm/vmw_msg.c
@@ -29,7 +29,8 @@
 #include "util/u_memory.h"
 #include "util/u_string.h"
 #include "pipe/p_defines.h"
-#include "svga_msg.h"
+#include "svga_winsys.h"
+#include "vmw_msg.h"


 #define MESSAGE_STATUS_SUCCESS  0x0001
@@ -83,7 +84,7 @@
         port_num, magic,                  \
         ax, bx, cx, dx, si, di)           \
 ({                                         \
-   __asm__ volatile ("inl %%dx, %%eax;" :  \
+   __asm__ volatile ("inl %%dx, %%eax;" :      \
      "=a"(ax),                            \
      "=b"(bx),                            \
      "=c"(cx),                            \
@@ -128,7 +129,7 @@ typedef uint64_t VMW_REG;
         port_num, magic, bp,                     \
         ax, bx, cx, dx, si, di)                  \
 ({                                                \
-   __asm__ volatile ("push %%rbp;"                \
+   __asm__ volatile ("push %%rbp;"                    \
      "movq %12, %%rbp;"                          \
      "rep outsb;"                                \
      "pop %%rbp;" :                              \
@@ -152,7 +153,7 @@ typedef uint64_t VMW_REG;
         port_num, magic, bp,                     \
         ax, bx, cx, dx, si, di)                  \
 ({                                                \
-   __asm__ volatile ("push %%rbp;"                \
+   __asm__ volatile ("push %%rbp;"                    \
      "movq %12, %%rbp;"                          \
      "rep insb;"                                 \
      "pop %%rbp" :                               \
@@ -176,17 +177,23 @@ typedef uint64_t VMW_REG;

 typedef uint32_t VMW_REG;

-/* In the 32-bit version of this macro, we use "m" because there is no
- * more register left for bp
+/* In the 32-bit version of this macro, we store bp in a memory location
+ * because we've ran out of registers.
+ * Now we can't reference that memory location while we've modified
+ * %esp or %ebp, so we first push it on the stack, just before we push
+ * %ebp, and then when we need it we read it from the stack where we
+ * just pushed it.
 */
 #define VMW_PORT_HB_OUT(cmd, in_cx, in_si, in_di, \
         port_num, magic, bp,                     \
         ax, bx, cx, dx, si, di)                  \
 ({                                                \
-   __asm__ volatile ("push %%ebp;"                \
-      "mov %12, %%ebp;"                           \
+   __asm__ volatile ("push %12;"                  \
+      "push %%ebp;"                               \
+      "mov 0x04(%%esp), %%ebp;"                   \
      "rep outsb;"                                \
-      "pop %%ebp;" :                              \
+      "pop %%ebp;"                                \
+      "add $0x04, %%esp;" :                       \
      "=a"(ax),                                   \
      "=b"(bx),                                   \
      "=c"(cx),                                   \
@@ -208,10 +215,12 @@ typedef uint32_t VMW_REG;
         port_num, magic, bp,                     \
         ax, bx, cx, dx, si, di)                  \
 ({                                                \
-   __asm__ volatile ("push %%ebp;"                \
-      "mov %12, %%ebp;"                           \
+   __asm__ volatile ("push %12;"                  \
+      "push %%ebp;"                               \
+      "mov 0x04(%%esp), %%ebp;"                   \
      "rep insb;"                                 \
-      "pop %%ebp" :                               \
+      "pop %%ebp;"                                \
+      "add $0x04, %%esp;" :                       \
      "=a"(ax),                                   \
      "=b"(bx),                                   \
      "=c"(cx),                                   \
@@ -252,7 +261,7 @@ typedef uint32_t VMW_REG;
         (void) in_cx; (void) bp;                 \
         (void) ax; (void) bx; (void) cx;         \
         (void) dx; (void) si; (void) di;
-			
+

 #define VMW_PORT_HB_IN(cmd, in_cx, in_si, in_di,  \
         port_num, magic, bp,                     \
@@ -283,7 +292,7 @@ struct rpc_channel {


 /**
- * svga_open_channel
+ * vmw_open_channel
 *
 * @channel: RPC channel
 * @protocol:
@@ -291,7 +300,7 @@ struct rpc_channel {
 * Returns: PIPE_OK on success, PIPE_ERROR otherwise
 */
 static enum pipe_error
-svga_open_channel(struct rpc_channel *channel, unsigned protocol)
+vmw_open_channel(struct rpc_channel *channel, unsigned protocol)
 {
   VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si = 0, di = 0;

@@ -321,7 +330,7 @@ svga_open_channel(struct rpc_channel *channel, unsigned protocol)
 * Returns: PIPE_OK on success, PIPE_ERROR otherwises
 */
 static enum pipe_error
-svga_close_channel(struct rpc_channel *channel)
+vmw_close_channel(struct rpc_channel *channel)
 {
   VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si, di;

@@ -344,7 +353,7 @@ svga_close_channel(struct rpc_channel *channel)


 /**
- * svga_send_msg: Sends a message to the host
+ * vmw_send_msg: Sends a message to the host
 *
 * @channel: RPC channel
 * @logmsg: NULL terminated string
@@ -352,7 +361,7 @@ svga_close_channel(struct rpc_channel *channel)
 * Returns: PIPE_OK on success
 */
 static enum pipe_error
-svga_send_msg(struct rpc_channel *channel, const char *msg)
+vmw_send_msg(struct rpc_channel *channel, const char *msg)
 {
   VMW_REG ax = 0, bx = 0, cx = 0, dx = 0, si, di, bp;
   size_t msg_len = strlen(msg);
@@ -406,46 +415,45 @@ svga_send_msg(struct rpc_channel *channel, const char *msg)


 /**
- * svga_host_log: Sends a log message to the host
+ * vmw_svga_winsys_host_log: Sends a log message to the host
 *
 * @log: NULL terminated string
 *
- * Returns: PIPE_OK on success
 */
-enum pipe_error
-svga_host_log(const char *log)
+void
+vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log)
 {
   struct rpc_channel channel;
   char *msg;
   int msg_len;
-   enum pipe_error ret = PIPE_OK;
+   int ret;

 #ifdef MSG_NOT_IMPLEMENTED
-   return ret;
+   return;
 #endif

   if (!log)
-      return ret;
+      return;

   msg_len = strlen(log) + strlen("log ") + 1;
   msg = CALLOC(1, msg_len);
   if (msg == NULL) {
      debug_printf("Cannot allocate memory for log message\n");
-      return PIPE_ERROR_OUT_OF_MEMORY;
+      return;
   }

   util_sprintf(msg, "log %s", log);

-   if (svga_open_channel(&channel, RPCI_PROTOCOL_NUM) ||
-       svga_send_msg(&channel, msg) ||
-       svga_close_channel(&channel)) {
-      debug_printf("Failed to send log\n");
-
-      ret = PIPE_ERROR;
+   if (!(ret = vmw_open_channel(&channel, RPCI_PROTOCOL_NUM))) {
+      ret = vmw_send_msg(&channel, msg);
+      vmw_close_channel(&channel);
   }

+   if (ret)
+      debug_printf("Failed to send log\n");
+
   FREE(msg);

-   return ret;
+   return;
 }

--- a/src/gallium/winsys/svga/drm/vmw_msg.h
+++ b/src/gallium/winsys/svga/drm/vmw_msg.h
@@ -26,17 +26,16 @@
 * Author:
 *   Sinclair Yeh <syeh@vmware.com>
 */
-#ifndef _SVGA_MSG_H
-#define _SVGA_MSG_H
+#ifndef _VMW_MSG_H
+#define _VMW_MSG_H

 /**
- * svga_host_log: Sends a log message to the host
+ * vmw_host_log: Sends a log message to the host
 *
 * @log: NULL terminated string
 *
- * Returns: PIPE_OK on success
 */
-enum pipe_error svga_host_log(const char *log);
+void vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log);

 #endif

--- a/Show More
+++ b/Show More
@@ -1 +1 @@
 .0.3
 .0.8