Compare commits
35 Commits
mesa-19.0.
...
19.0
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3b7363f499 |
@@ -40,6 +40,7 @@ d2aa65eb1892f7b300ac24560f9dbda6b600b5a7
|
||||
ad2b4aa37806779bdfc15d704940136c3db21eb4
|
||||
9dc57eebd578b976b94c54d083377ba0920d43a8
|
||||
5820ac6756898a1bd30bde04555437a55c378726
|
||||
ffd2f948fee271cbbce93708fc508dab7cb5d14c
|
||||
|
||||
# This was manually rebased and the script doesn't understand that for some
|
||||
# reason
|
||||
|
||||
@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
|
||||
|
||||
<h2>SHA256 checksums</h2>
|
||||
<pre>
|
||||
TBD
|
||||
SHA256: ac8e9ea388ec5c69f5a690190edf8ede602afdbaeea62d49e108057737430ac7 mesa-19.0.6.tar.gz
|
||||
SHA256: 2db2f2fcaa4048b16e066fad76b8a93944f7d06d329972b0f5fd5ce692ce3d24 mesa-19.0.6.tar.xz
|
||||
</pre>
|
||||
|
||||
|
||||
|
||||
150
docs/relnotes/19.0.7.html
Normal file
150
docs/relnotes/19.0.7.html
Normal file
@@ -0,0 +1,150 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta http-equiv="content-type" content="text/html; charset=utf-8">
|
||||
<title>Mesa Release Notes</title>
|
||||
<link rel="stylesheet" type="text/css" href="../mesa.css">
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<div class="header">
|
||||
<h1>The Mesa 3D Graphics Library</h1>
|
||||
</div>
|
||||
|
||||
<iframe src="../contents.html"></iframe>
|
||||
<div class="content">
|
||||
|
||||
<h1>Mesa 19.0.6 Release Notes / June 24, 2019</h1>
|
||||
|
||||
<p>
|
||||
Mesa 19.0.7 is a bug fix release which fixes bugs found since the 19.0.6 release.
|
||||
</p>
|
||||
<p>
|
||||
Mesa 19.0.7 implements the OpenGL 4.5 API, but the version reported by
|
||||
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
|
||||
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
|
||||
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
|
||||
4.5 is <strong>only</strong> available if requested at context creation.
|
||||
Compatibility contexts may report a lower version depending on each driver.
|
||||
</p>
|
||||
|
||||
|
||||
<h2>SHA256 checksums</h2>
|
||||
<pre>
|
||||
81119f0cbbd1fbe7c0574e1e2690e0dae8868124d24c875f5fb76f165db3a54d mesa-19.0.7.tar.gz
|
||||
d7bf3db2e442fe5eeb96144f8508d94f04aededdf37af477e644638d366b2b28 mesa-19.0.7.tar.xz
|
||||
</pre>
|
||||
|
||||
|
||||
<h2>New features</h2>
|
||||
|
||||
<p>N/A</p>
|
||||
|
||||
<h2>Bug fixes</h2>
|
||||
|
||||
|
||||
<ul>
|
||||
|
||||
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110302">Bug 110302</a> - [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions</li>
|
||||
|
||||
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110921">Bug 110921</a> - virgl on OpenGL 3.3 host regressed to OpenGL 2.1</li>
|
||||
|
||||
</ul>
|
||||
|
||||
<h2>Changes</h2>
|
||||
|
||||
|
||||
<p>Bas Nieuwenhuizen (5):</p>
|
||||
<ul>
|
||||
<li>radv: Prevent out of bound shift on 32-bit builds.</li>
|
||||
<li>radv: Decompress DCC when the image format is not allowed for buffers.</li>
|
||||
<li>radv: Fix vulkan build in meson.</li>
|
||||
<li>anv: Fix vulkan build in meson.</li>
|
||||
<li>meson: Allow building radeonsi with just the android platform.</li>
|
||||
</ul>
|
||||
|
||||
<p>Charmaine Lee (1):</p>
|
||||
<ul>
|
||||
<li>svga: Remove unnecessary check for the pre flush bit for setting vertex buffers</li>
|
||||
</ul>
|
||||
|
||||
<p>Deepak Rawat (1):</p>
|
||||
<ul>
|
||||
<li>winsys/svga/drm: Fix 32-bit RPCI send message</li>
|
||||
</ul>
|
||||
|
||||
<p>Dylan Baker (3):</p>
|
||||
<ul>
|
||||
<li>docs: Add SHA256 sums for 19.0.6</li>
|
||||
<li>cherry-ignore: add additional 19.1 only patches</li>
|
||||
<li>Bump version for 19.0.7 release</li>
|
||||
</ul>
|
||||
|
||||
<p>Emil Velikov (1):</p>
|
||||
<ul>
|
||||
<li>mapi: correctly handle the full offset table</li>
|
||||
</ul>
|
||||
|
||||
<p>Gert Wollny (2):</p>
|
||||
<ul>
|
||||
<li>virgl: Add a caps feature check version</li>
|
||||
<li>virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts</li>
|
||||
</ul>
|
||||
|
||||
<p>Haihao Xiang (1):</p>
|
||||
<ul>
|
||||
<li>i965: support UYVY for external import only</li>
|
||||
</ul>
|
||||
|
||||
<p>Jason Ekstrand (2):</p>
|
||||
<ul>
|
||||
<li>nir/propagate_invariant: Don't add NULL vars to the hash table</li>
|
||||
<li>anv: Set STATE_BASE_ADDRESS upper bounds on gen7</li>
|
||||
</ul>
|
||||
|
||||
<p>Kenneth Graunke (1):</p>
|
||||
<ul>
|
||||
<li>glsl: Fix out of bounds read in shader_cache_read_program_metadata</li>
|
||||
</ul>
|
||||
|
||||
<p>Kevin Strasser (2):</p>
|
||||
<ul>
|
||||
<li>gallium/winsys/kms: Fix dumb buffer bpp</li>
|
||||
<li>st/mesa: Add rgbx handling for fp formats</li>
|
||||
</ul>
|
||||
|
||||
<p>Lionel Landwerlin (2):</p>
|
||||
<ul>
|
||||
<li>intel/perf: fix EuThreadsCount value in performance equations</li>
|
||||
<li>intel/perf: improve dynamic loading config detection</li>
|
||||
</ul>
|
||||
|
||||
<p>Mathias Fröhlich (1):</p>
|
||||
<ul>
|
||||
<li>egl: Don't add hardware device if there is no render node v2.</li>
|
||||
</ul>
|
||||
|
||||
<p>Nanley Chery (1):</p>
|
||||
<ul>
|
||||
<li>anv/cmd_buffer: Initalize the clear color struct for CNL+</li>
|
||||
</ul>
|
||||
|
||||
<p>Nataraj Deshpande (1):</p>
|
||||
<ul>
|
||||
<li>anv: Fix check for isl_fmt in assert</li>
|
||||
</ul>
|
||||
|
||||
<p>Samuel Pitoiset (5):</p>
|
||||
<ul>
|
||||
<li>radv: fix alpha-to-coverage when there is unused color attachments</li>
|
||||
<li>radv: fix setting CB_SHADER_MASK for dual source blending</li>
|
||||
<li>radv: fix occlusion queries on VegaM</li>
|
||||
<li>radv: fix VK_EXT_memory_budget if one heap isn't available</li>
|
||||
<li>radv: fix FMASK expand with SRGB formats</li>
|
||||
</ul>
|
||||
|
||||
|
||||
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
62
docs/relnotes/19.0.8.html
Normal file
62
docs/relnotes/19.0.8.html
Normal file
@@ -0,0 +1,62 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta http-equiv="content-type" content="text/html; charset=utf-8">
|
||||
<title>Mesa Release Notes</title>
|
||||
<link rel="stylesheet" type="text/css" href="../mesa.css">
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<div class="header">
|
||||
<h1>The Mesa 3D Graphics Library</h1>
|
||||
</div>
|
||||
|
||||
<iframe src="../contents.html"></iframe>
|
||||
<div class="content">
|
||||
|
||||
<h1>Mesa 19.0.8 Release Notes / June 26, 2019</h1>
|
||||
|
||||
<p>
|
||||
Mesa 19.0.8 is an emergency bug fix release which fixes a critical bug found in the 19.0.7 release.
|
||||
</p>
|
||||
<p>
|
||||
Mesa 19.0.8 implements the OpenGL 4.5 API, but the version reported by
|
||||
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
|
||||
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
|
||||
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
|
||||
4.5 is <strong>only</strong> available if requested at context creation.
|
||||
Compatibility contexts may report a lower version depending on each driver.
|
||||
</p>
|
||||
|
||||
|
||||
<h2>SHA256 checksums</h2>
|
||||
<pre>
|
||||
1a3dc3f2af853c76aadb4a1e03c9ba420361c04a742d457a702b781671a96a57 mesa-19.0.8.tar.gz
|
||||
d017eb53a810c32dabeedf6ca2238ae1e897ce9090e470e9ce1d6c9e3f1b0862 mesa-19.0.8.tar.xz
|
||||
</pre>
|
||||
|
||||
|
||||
<h2>New features</h2>
|
||||
|
||||
<p>N/A</p>
|
||||
|
||||
<h2>Bug fixes</h2>
|
||||
|
||||
<p>None</p>
|
||||
|
||||
<h2>Changes</h2>
|
||||
|
||||
<p>Dylan Baker (2):</p>
|
||||
<ul>
|
||||
<li>docs: Add SHA256 sums for 19.0.7</li>
|
||||
<li>version: bump to 19.0.8</li>
|
||||
</ul>
|
||||
|
||||
<p>Kenneth Graunke (1):</p>
|
||||
<ul>
|
||||
<li>egl/x11: calloc dri2_surf so it's properly zeroed</li>
|
||||
</ul>
|
||||
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
@@ -327,12 +327,12 @@ else
|
||||
with_egl = false
|
||||
endif
|
||||
|
||||
if with_egl and not (with_platform_drm or with_platform_surfaceless)
|
||||
if with_egl and not (with_platform_drm or with_platform_surfaceless or with_platform_android)
|
||||
if with_gallium_radeonsi
|
||||
error('RadeonSI requires drm or surfaceless platform when using EGL')
|
||||
error('RadeonSI requires the drm, surfaceless or android platform when using EGL')
|
||||
endif
|
||||
if with_gallium_virgl
|
||||
error('Virgl requires drm or surfaceless platform when using EGL')
|
||||
error('Virgl requires the drm, surfaceless or android platform when using EGL')
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
@@ -128,6 +128,13 @@ if with_xlib_lease
|
||||
radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
|
||||
endif
|
||||
|
||||
if with_platform_android
|
||||
radv_flags += [
|
||||
'-DVK_USE_PLATFORM_ANDROID_KHR'
|
||||
]
|
||||
libradv_files += files('radv_android.c')
|
||||
endif
|
||||
|
||||
libvulkan_radeon = shared_library(
|
||||
'vulkan_radeon',
|
||||
[libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c, sha1_h],
|
||||
|
||||
@@ -566,8 +566,8 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
|
||||
|
||||
for_each_bit(i, descriptors_state->valid) {
|
||||
struct radv_descriptor_set *set = descriptors_state->sets[i];
|
||||
data[i * 2] = (uintptr_t)set;
|
||||
data[i * 2 + 1] = (uintptr_t)set >> 32;
|
||||
data[i * 2] = (uint64_t)(uintptr_t)set;
|
||||
data[i * 2 + 1] = (uint64_t)(uintptr_t)set >> 32;
|
||||
}
|
||||
|
||||
radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
|
||||
|
||||
@@ -1389,40 +1389,46 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
|
||||
* Note that the application heap usages are not really accurate (eg.
|
||||
* in presence of shared buffers).
|
||||
*/
|
||||
if (vram_size) {
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_VRAM);
|
||||
for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
|
||||
uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
|
||||
|
||||
heap_budget = vram_size -
|
||||
device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
|
||||
heap_usage;
|
||||
switch (device->mem_type_indices[i]) {
|
||||
case RADV_MEM_TYPE_VRAM:
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_VRAM);
|
||||
|
||||
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
|
||||
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
|
||||
}
|
||||
heap_budget = vram_size -
|
||||
device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
|
||||
heap_usage;
|
||||
|
||||
if (visible_vram_size) {
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_VRAM_VIS);
|
||||
memoryBudget->heapBudget[heap_index] = heap_budget;
|
||||
memoryBudget->heapUsage[heap_index] = heap_usage;
|
||||
break;
|
||||
case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_VRAM_VIS);
|
||||
|
||||
heap_budget = visible_vram_size -
|
||||
device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
|
||||
heap_usage;
|
||||
heap_budget = visible_vram_size -
|
||||
device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
|
||||
heap_usage;
|
||||
|
||||
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
|
||||
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
|
||||
}
|
||||
memoryBudget->heapBudget[heap_index] = heap_budget;
|
||||
memoryBudget->heapUsage[heap_index] = heap_usage;
|
||||
break;
|
||||
case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_GTT);
|
||||
|
||||
if (gtt_size) {
|
||||
heap_usage = device->ws->query_value(device->ws,
|
||||
RADEON_ALLOCATED_GTT);
|
||||
heap_budget = gtt_size -
|
||||
device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
|
||||
heap_usage;
|
||||
|
||||
heap_budget = gtt_size -
|
||||
device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
|
||||
heap_usage;
|
||||
|
||||
memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
|
||||
memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
|
||||
memoryBudget->heapBudget[heap_index] = heap_budget;
|
||||
memoryBudget->heapUsage[heap_index] = heap_usage;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* The heapBudget and heapUsage values must be zero for array elements
|
||||
|
||||
@@ -524,7 +524,7 @@ static bool radv_is_storage_image_format_supported(struct radv_physical_device *
|
||||
}
|
||||
}
|
||||
|
||||
static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
|
||||
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
|
||||
{
|
||||
const struct vk_format_description *desc = vk_format_description(format);
|
||||
unsigned data_format, num_format;
|
||||
@@ -536,7 +536,8 @@ static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
|
||||
num_format = radv_translate_buffer_numformat(desc,
|
||||
vk_format_get_first_non_void_channel(format));
|
||||
|
||||
*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
|
||||
if (scaled)
|
||||
*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
|
||||
return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID &&
|
||||
num_format != ~0;
|
||||
}
|
||||
|
||||
@@ -189,6 +189,24 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
|
||||
layout,
|
||||
&pRegions[r].imageSubresource);
|
||||
|
||||
if (!radv_is_buffer_format_supported(img_bsurf.format, NULL)) {
|
||||
uint32_t queue_mask = radv_image_queue_family_mask(image,
|
||||
cmd_buffer->queue_family_index,
|
||||
cmd_buffer->queue_family_index);
|
||||
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
|
||||
if (compressed) {
|
||||
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
|
||||
.aspectMask = pRegions[r].imageSubresource.aspectMask,
|
||||
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
|
||||
.levelCount = 1,
|
||||
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
|
||||
.layerCount = pRegions[r].imageSubresource.layerCount,
|
||||
});
|
||||
}
|
||||
img_bsurf.format = vk_format_for_size(vk_format_get_blocksize(img_bsurf.format));
|
||||
img_bsurf.current_layout = VK_IMAGE_LAYOUT_GENERAL;
|
||||
}
|
||||
|
||||
struct radv_meta_blit2d_buffer buf_bsurf = {
|
||||
.bs = img_bsurf.bs,
|
||||
.format = img_bsurf.format,
|
||||
@@ -314,6 +332,24 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
|
||||
layout,
|
||||
&pRegions[r].imageSubresource);
|
||||
|
||||
if (!radv_is_buffer_format_supported(img_info.format, NULL)) {
|
||||
uint32_t queue_mask = radv_image_queue_family_mask(image,
|
||||
cmd_buffer->queue_family_index,
|
||||
cmd_buffer->queue_family_index);
|
||||
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
|
||||
if (compressed) {
|
||||
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
|
||||
.aspectMask = pRegions[r].imageSubresource.aspectMask,
|
||||
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
|
||||
.levelCount = 1,
|
||||
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
|
||||
.layerCount = pRegions[r].imageSubresource.layerCount,
|
||||
});
|
||||
}
|
||||
img_info.format = vk_format_for_size(vk_format_get_blocksize(img_info.format));
|
||||
img_info.current_layout = VK_IMAGE_LAYOUT_GENERAL;
|
||||
}
|
||||
|
||||
struct radv_meta_blit2d_buffer buf_info = {
|
||||
.bs = img_info.bs,
|
||||
.format = img_info.format,
|
||||
|
||||
@@ -24,6 +24,7 @@
|
||||
|
||||
#include "radv_meta.h"
|
||||
#include "radv_private.h"
|
||||
#include "vk_format.h"
|
||||
|
||||
static nir_shader *
|
||||
build_fmask_expand_compute_shader(struct radv_device *device, int samples)
|
||||
@@ -132,7 +133,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
|
||||
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
||||
.image = radv_image_to_handle(image),
|
||||
.viewType = radv_meta_get_view_type(image),
|
||||
.format = image->vk_format,
|
||||
.format = vk_format_no_srgb(image->vk_format),
|
||||
.subresourceRange = {
|
||||
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
||||
.baseMipLevel = 0,
|
||||
|
||||
@@ -524,7 +524,7 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
|
||||
col_format |= cf << (4 * i);
|
||||
}
|
||||
|
||||
if (!col_format && blend->need_src_alpha & (1 << 0)) {
|
||||
if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
|
||||
/* When a subpass doesn't have any color attachments, write the
|
||||
* alpha channel of MRT0 when alpha coverage is enabled because
|
||||
* the depth attachment needs it.
|
||||
@@ -542,10 +542,13 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
|
||||
}
|
||||
}
|
||||
|
||||
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
|
||||
|
||||
/* The output for dual source blending should have the same format as
|
||||
* the first output.
|
||||
*/
|
||||
if (blend->mrt0_is_dual_src)
|
||||
col_format |= (col_format & 0xf) << 4;
|
||||
|
||||
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
|
||||
blend->spi_shader_col_format = col_format;
|
||||
}
|
||||
|
||||
|
||||
@@ -1448,6 +1448,7 @@ uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *de
|
||||
int first_non_void);
|
||||
uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
|
||||
int first_non_void);
|
||||
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
|
||||
uint32_t radv_translate_colorformat(VkFormat format);
|
||||
uint32_t radv_translate_color_numformat(VkFormat format,
|
||||
const struct vk_format_description *desc,
|
||||
|
||||
@@ -40,18 +40,6 @@
|
||||
static const int pipelinestat_block_size = 11 * 8;
|
||||
static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
|
||||
|
||||
static unsigned get_max_db(struct radv_device *device)
|
||||
{
|
||||
unsigned num_db = device->physical_device->rad_info.num_render_backends;
|
||||
MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
|
||||
|
||||
/* Otherwise we need to change the query reset procedure */
|
||||
assert(rb_mask == ((1ull << num_db) - 1));
|
||||
|
||||
return num_db;
|
||||
}
|
||||
|
||||
|
||||
static nir_ssa_def *nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)
|
||||
{
|
||||
return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));
|
||||
@@ -108,12 +96,14 @@ build_occlusion_query_shader(struct radv_device *device) {
|
||||
* uint64_t dst_offset = dst_stride * global_id.x;
|
||||
* bool available = true;
|
||||
* for (int i = 0; i < db_count; ++i) {
|
||||
* uint64_t start = src_buf[src_offset + 16 * i];
|
||||
* uint64_t end = src_buf[src_offset + 16 * i + 8];
|
||||
* if ((start & (1ull << 63)) && (end & (1ull << 63)))
|
||||
* result += end - start;
|
||||
* else
|
||||
* available = false;
|
||||
* if (enabled_rb_mask & (1 << i)) {
|
||||
* uint64_t start = src_buf[src_offset + 16 * i];
|
||||
* uint64_t end = src_buf[src_offset + 16 * i + 8];
|
||||
* if ((start & (1ull << 63)) && (end & (1ull << 63)))
|
||||
* result += end - start;
|
||||
* else
|
||||
* available = false;
|
||||
* }
|
||||
* }
|
||||
* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
|
||||
* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
|
||||
@@ -139,7 +129,8 @@ build_occlusion_query_shader(struct radv_device *device) {
|
||||
nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
|
||||
nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
|
||||
nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");
|
||||
unsigned db_count = get_max_db(device);
|
||||
unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
|
||||
unsigned db_count = device->physical_device->rad_info.num_render_backends;
|
||||
|
||||
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
|
||||
|
||||
@@ -185,6 +176,16 @@ build_occlusion_query_shader(struct radv_device *device) {
|
||||
nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
|
||||
radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
|
||||
|
||||
nir_ssa_def *enabled_cond =
|
||||
nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),
|
||||
nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));
|
||||
|
||||
nir_if *enabled_if = nir_if_create(b.shader);
|
||||
enabled_if->condition = nir_src_for_ssa(nir_i2b(&b, enabled_cond));
|
||||
nir_cf_node_insert(b.cursor, &enabled_if->cf_node);
|
||||
|
||||
b.cursor = nir_after_cf_list(&enabled_if->then_list);
|
||||
|
||||
nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
|
||||
load_offset = nir_iadd(&b, input_base, load_offset);
|
||||
|
||||
@@ -1038,7 +1039,7 @@ VkResult radv_CreateQueryPool(
|
||||
|
||||
switch(pCreateInfo->queryType) {
|
||||
case VK_QUERY_TYPE_OCCLUSION:
|
||||
pool->stride = 16 * get_max_db(device);
|
||||
pool->stride = 16 * device->physical_device->rad_info.num_render_backends;
|
||||
break;
|
||||
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
|
||||
pool->stride = pipelinestat_block_size * 2;
|
||||
@@ -1152,12 +1153,17 @@ VkResult radv_GetQueryPoolResults(
|
||||
}
|
||||
case VK_QUERY_TYPE_OCCLUSION: {
|
||||
volatile uint64_t const *src64 = (volatile uint64_t const *)src;
|
||||
uint32_t db_count = device->physical_device->rad_info.num_render_backends;
|
||||
uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
|
||||
uint64_t sample_count = 0;
|
||||
int db_count = get_max_db(device);
|
||||
available = 1;
|
||||
|
||||
for (int i = 0; i < db_count; ++i) {
|
||||
uint64_t start, end;
|
||||
|
||||
if (!(enabled_rb_mask & (1 << i)))
|
||||
continue;
|
||||
|
||||
do {
|
||||
start = src64[2 * i];
|
||||
end = src64[2 * i + 1];
|
||||
|
||||
@@ -165,9 +165,8 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
|
||||
prog->FragDataIndexBindings->iterate(create_binding_str, &buf);
|
||||
ralloc_asprintf_append(&buf, "tf: %d ", prog->TransformFeedback.BufferMode);
|
||||
for (unsigned int i = 0; i < prog->TransformFeedback.NumVarying; i++) {
|
||||
ralloc_asprintf_append(&buf, "%s:%d ",
|
||||
prog->TransformFeedback.VaryingNames[i],
|
||||
prog->TransformFeedback.BufferStride[i]);
|
||||
ralloc_asprintf_append(&buf, "%s ",
|
||||
prog->TransformFeedback.VaryingNames[i]);
|
||||
}
|
||||
|
||||
/* SSO has an effect on the linked program so include this when generating
|
||||
|
||||
@@ -65,12 +65,21 @@ add_cf_node(nir_cf_node *cf, struct set *invariants)
|
||||
static void
|
||||
add_var(nir_variable *var, struct set *invariants)
|
||||
{
|
||||
_mesa_set_add(invariants, var);
|
||||
/* Because we pass the result of nir_intrinsic_get_var directly to this
|
||||
* function, it's possible for var to be NULL if, for instance, there's a
|
||||
* cast somewhere in the chain.
|
||||
*/
|
||||
if (var != NULL)
|
||||
_mesa_set_add(invariants, var);
|
||||
}
|
||||
|
||||
static bool
|
||||
var_is_invariant(nir_variable *var, struct set * invariants)
|
||||
{
|
||||
/* Because we pass the result of nir_intrinsic_get_var directly to this
|
||||
* function, it's possible for var to be NULL if, for instance, there's a
|
||||
* cast somewhere in the chain.
|
||||
*/
|
||||
return var && (var->data.invariant || _mesa_set_search(invariants, var));
|
||||
}
|
||||
|
||||
|
||||
@@ -261,7 +261,7 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
|
||||
|
||||
(void) drv;
|
||||
|
||||
dri2_surf = malloc(sizeof *dri2_surf);
|
||||
dri2_surf = calloc(1, sizeof *dri2_surf);
|
||||
if (!dri2_surf) {
|
||||
_eglError(EGL_BAD_ALLOC, "dri2_create_surface");
|
||||
return NULL;
|
||||
|
||||
@@ -108,9 +108,9 @@ static int
|
||||
_eglAddDRMDevice(drmDevicePtr device, _EGLDevice **out_dev)
|
||||
{
|
||||
_EGLDevice *dev;
|
||||
const int wanted_nodes = 1 << DRM_NODE_RENDER | 1 << DRM_NODE_PRIMARY;
|
||||
|
||||
if ((device->available_nodes & (1 << DRM_NODE_PRIMARY |
|
||||
1 << DRM_NODE_RENDER)) == 0)
|
||||
if ((device->available_nodes & wanted_nodes) != wanted_nodes)
|
||||
return -1;
|
||||
|
||||
dev = _eglGlobal.DeviceList;
|
||||
|
||||
@@ -619,11 +619,11 @@ draw_vgpu10(struct svga_hwtnl *hwtnl,
|
||||
vbuffer_attrs[i].sid = 0;
|
||||
}
|
||||
|
||||
/* If we haven't yet emitted a drawing command or if any
|
||||
* vertex buffer state is changing, issue that state now.
|
||||
/* If any of the vertex buffer state has changed, issue
|
||||
* the SetVertexBuffers command. Otherwise, we will just
|
||||
* need to rebind the resources.
|
||||
*/
|
||||
if (((hwtnl->cmd.swc->hints & SVGA_HINT_FLAG_CAN_PRE_FLUSH) == 0) ||
|
||||
vbuf_count != svga->state.hw_draw.num_vbuffers ||
|
||||
if (vbuf_count != svga->state.hw_draw.num_vbuffers ||
|
||||
!vertex_buffers_equal(vbuf_count,
|
||||
vbuffer_attrs,
|
||||
vbuffers,
|
||||
|
||||
@@ -358,6 +358,7 @@ struct virgl_caps_v2 {
|
||||
uint32_t max_atomic_counter_buffers[6];
|
||||
uint32_t max_combined_atomic_counters;
|
||||
uint32_t max_combined_atomic_counter_buffers;
|
||||
uint32_t host_feature_check_version;
|
||||
};
|
||||
|
||||
union virgl_caps {
|
||||
|
||||
@@ -347,7 +347,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
|
||||
case PIPE_CAP_NATIVE_FENCE_FD:
|
||||
return vscreen->vws->supports_fences;
|
||||
case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
|
||||
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL;
|
||||
return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
|
||||
(vscreen->caps.caps.v2.host_feature_check_version < 1);
|
||||
default:
|
||||
return u_pipe_screen_get_param_defaults(screen, param);
|
||||
}
|
||||
|
||||
@@ -150,5 +150,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
|
||||
caps->caps.v2.max_image_samples = 0;
|
||||
caps->caps.v2.max_compute_work_group_invocations = 0;
|
||||
caps->caps.v2.max_compute_shared_memory_size = 0;
|
||||
caps->caps.v2.host_feature_check_version = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -177,17 +177,23 @@ typedef uint64_t VMW_REG;
|
||||
|
||||
typedef uint32_t VMW_REG;
|
||||
|
||||
/* In the 32-bit version of this macro, we use "m" because there is no
|
||||
* more register left for bp
|
||||
/* In the 32-bit version of this macro, we store bp in a memory location
|
||||
* because we've ran out of registers.
|
||||
* Now we can't reference that memory location while we've modified
|
||||
* %esp or %ebp, so we first push it on the stack, just before we push
|
||||
* %ebp, and then when we need it we read it from the stack where we
|
||||
* just pushed it.
|
||||
*/
|
||||
#define VMW_PORT_HB_OUT(cmd, in_cx, in_si, in_di, \
|
||||
port_num, magic, bp, \
|
||||
ax, bx, cx, dx, si, di) \
|
||||
({ \
|
||||
__asm__ volatile ("push %%ebp;" \
|
||||
"mov %12, %%ebp;" \
|
||||
__asm__ volatile ("push %12;" \
|
||||
"push %%ebp;" \
|
||||
"mov 0x04(%%esp), %%ebp;" \
|
||||
"rep outsb;" \
|
||||
"pop %%ebp;" : \
|
||||
"pop %%ebp;" \
|
||||
"add $0x04, %%esp;" : \
|
||||
"=a"(ax), \
|
||||
"=b"(bx), \
|
||||
"=c"(cx), \
|
||||
@@ -209,10 +215,12 @@ typedef uint32_t VMW_REG;
|
||||
port_num, magic, bp, \
|
||||
ax, bx, cx, dx, si, di) \
|
||||
({ \
|
||||
__asm__ volatile ("push %%ebp;" \
|
||||
"mov %12, %%ebp;" \
|
||||
__asm__ volatile ("push %12;" \
|
||||
"push %%ebp;" \
|
||||
"mov 0x04(%%esp), %%ebp;" \
|
||||
"rep insb;" \
|
||||
"pop %%ebp" : \
|
||||
"pop %%ebp;" \
|
||||
"add $0x04, %%esp;" : \
|
||||
"=a"(ax), \
|
||||
"=b"(bx), \
|
||||
"=c"(cx), \
|
||||
@@ -418,6 +426,7 @@ vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log)
|
||||
struct rpc_channel channel;
|
||||
char *msg;
|
||||
int msg_len;
|
||||
int ret;
|
||||
|
||||
#ifdef MSG_NOT_IMPLEMENTED
|
||||
return;
|
||||
@@ -435,12 +444,14 @@ vmw_svga_winsys_host_log(struct svga_winsys_screen *sws, const char *log)
|
||||
|
||||
util_sprintf(msg, "log %s", log);
|
||||
|
||||
if (vmw_open_channel(&channel, RPCI_PROTOCOL_NUM) ||
|
||||
vmw_send_msg(&channel, msg) ||
|
||||
vmw_close_channel(&channel)) {
|
||||
debug_printf("Failed to send log\n");
|
||||
if (!(ret = vmw_open_channel(&channel, RPCI_PROTOCOL_NUM))) {
|
||||
ret = vmw_send_msg(&channel, msg);
|
||||
vmw_close_channel(&channel);
|
||||
}
|
||||
|
||||
if (ret)
|
||||
debug_printf("Failed to send log\n");
|
||||
|
||||
FREE(msg);
|
||||
|
||||
return;
|
||||
|
||||
@@ -182,7 +182,7 @@ kms_sw_displaytarget_create(struct sw_winsys *ws,
|
||||
kms_sw_dt->format = format;
|
||||
|
||||
memset(&create_req, 0, sizeof(create_req));
|
||||
create_req.bpp = 32;
|
||||
create_req.bpp = util_format_get_blocksizebits(format);
|
||||
create_req.width = width;
|
||||
create_req.height = height;
|
||||
ret = drmIoctl(kms_sw->fd, DRM_IOCTL_MODE_CREATE_DUMB, &create_req);
|
||||
|
||||
@@ -751,7 +751,7 @@ resolve_ahw_image(struct anv_device *device,
|
||||
vk_format,
|
||||
VK_IMAGE_ASPECT_COLOR_BIT,
|
||||
vk_tiling);
|
||||
assert(format != ISL_FORMAT_UNSUPPORTED);
|
||||
assert(isl_fmt != ISL_FORMAT_UNSUPPORTED);
|
||||
|
||||
/* Handle RGB(X)->RGBA fallback. */
|
||||
switch (desc.format) {
|
||||
|
||||
@@ -122,6 +122,23 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
|
||||
sba.IndirectObjectBufferSizeModifyEnable = true;
|
||||
sba.InstructionBufferSize = 0xfffff;
|
||||
sba.InstructionBuffersizeModifyEnable = true;
|
||||
# else
|
||||
/* On gen7, we have upper bounds instead. According to the docs,
|
||||
* setting an upper bound of zero means that no bounds checking is
|
||||
* performed so, in theory, we should be able to leave them zero.
|
||||
* However, border color is broken and the GPU bounds-checks anyway.
|
||||
* To avoid this and other potential problems, we may as well set it
|
||||
* for everything.
|
||||
*/
|
||||
sba.GeneralStateAccessUpperBound =
|
||||
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
|
||||
sba.GeneralStateAccessUpperBoundModifyEnable = true;
|
||||
sba.DynamicStateAccessUpperBound =
|
||||
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
|
||||
sba.DynamicStateAccessUpperBoundModifyEnable = true;
|
||||
sba.InstructionAccessUpperBound =
|
||||
(struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
|
||||
sba.InstructionAccessUpperBoundModifyEnable = true;
|
||||
# endif
|
||||
# if (GEN_GEN >= 9)
|
||||
sba.BindlessSurfaceStateBaseAddress = (struct anv_address) { NULL, 0 };
|
||||
@@ -828,27 +845,21 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
|
||||
set_image_fast_clear_state(cmd_buffer, image, aspect,
|
||||
ANV_FAST_CLEAR_NONE);
|
||||
|
||||
/* The fast clear value dword(s) will be copied into a surface state object.
|
||||
* Ensure that the restrictions of the fields in the dword(s) are followed.
|
||||
*
|
||||
* CCS buffers on SKL+ can have any value set for the clear colors.
|
||||
*/
|
||||
if (image->samples == 1 && GEN_GEN >= 9)
|
||||
return;
|
||||
|
||||
/* Other combinations of auxiliary buffers and platforms require specific
|
||||
* values in the clear value dword(s).
|
||||
/* Initialize the struct fields that are accessed for fast-clears so that
|
||||
* the HW restrictions on the field values are satisfied.
|
||||
*/
|
||||
struct anv_address addr =
|
||||
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
|
||||
|
||||
if (GEN_GEN >= 9) {
|
||||
for (unsigned i = 0; i < 4; i++) {
|
||||
const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
|
||||
const unsigned num_dwords = GEN_GEN >= 10 ?
|
||||
isl_dev->ss.clear_color_state_size / 4 :
|
||||
isl_dev->ss.clear_value_size / 4;
|
||||
for (unsigned i = 0; i < num_dwords; i++) {
|
||||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
|
||||
sdi.Address = addr;
|
||||
sdi.Address.offset += i * 4;
|
||||
/* MCS buffers on SKL+ can only have 1/0 clear colors. */
|
||||
assert(image->samples > 1);
|
||||
sdi.ImmediateData = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -112,7 +112,6 @@ endforeach
|
||||
|
||||
libanv_files = files(
|
||||
'anv_allocator.c',
|
||||
'anv_android_stubs.c',
|
||||
'anv_android.h',
|
||||
'anv_batch_chain.c',
|
||||
'anv_blorp.c',
|
||||
@@ -178,6 +177,13 @@ if with_xlib_lease
|
||||
anv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
|
||||
endif
|
||||
|
||||
if with_platform_android
|
||||
anv_flags += '-DVK_USE_PLATFORM_ANDROID_KHR'
|
||||
libanv_files += files('anv_android.c')
|
||||
else
|
||||
libanv_files += files('anv_android_stubs.c')
|
||||
endif
|
||||
|
||||
libanv_common = static_library(
|
||||
'anv_common',
|
||||
[
|
||||
|
||||
@@ -49,7 +49,7 @@ def parse_GL_API( file_name, factory = None ):
|
||||
# that are not part of the ABI.
|
||||
|
||||
for func in api.functionIterateByCategory():
|
||||
if func.assign_offset:
|
||||
if func.assign_offset and func.offset < 0:
|
||||
func.offset = api.next_offset;
|
||||
api.next_offset += 1
|
||||
|
||||
@@ -683,8 +683,12 @@ class gl_function( gl_item ):
|
||||
|
||||
if name in static_data.offsets and static_data.offsets[name] <= static_data.MAX_OFFSETS:
|
||||
self.offset = static_data.offsets[name]
|
||||
elif name in static_data.offsets and static_data.offsets[name] > static_data.MAX_OFFSETS:
|
||||
self.offset = static_data.offsets[name]
|
||||
self.assign_offset = True
|
||||
else:
|
||||
self.offset = -1
|
||||
if self.exec_flavor != "skip":
|
||||
raise RuntimeError("Entry-point %s is missing offset in static_data.py. Add one at the bottom of the list." % (name))
|
||||
self.assign_offset = self.exec_flavor != "skip" or name in static_data.unused_functions
|
||||
|
||||
if not self.name:
|
||||
|
||||
@@ -29,7 +29,7 @@ MAX_OFFSETS = 407
|
||||
"""Table of functions that have ABI-mandated offsets in the dispatch table.
|
||||
|
||||
The first MAX_OFFSETS entries are required by indirect GLX. The rest are
|
||||
required to preserve the glapi <> drivers ABI. This is to be addressed shortly.
|
||||
required to preserve the glapi <> GL/GLES ABI. This is to be addressed shortly.
|
||||
|
||||
This list will never change."""
|
||||
offsets = {
|
||||
|
||||
@@ -1848,23 +1848,10 @@ static bool
|
||||
kernel_has_dynamic_config_support(struct brw_context *brw)
|
||||
{
|
||||
__DRIscreen *screen = brw->screen->driScrnPriv;
|
||||
uint64_t invalid_config_id = UINT64_MAX;
|
||||
|
||||
hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
|
||||
struct brw_perf_query_info *query = entry->data;
|
||||
char config_path[280];
|
||||
uint64_t config_id;
|
||||
|
||||
snprintf(config_path, sizeof(config_path), "%s/metrics/%s/id",
|
||||
brw->perfquery.sysfs_dev_dir, query->guid);
|
||||
|
||||
/* Look for the test config, which we know we can't replace. */
|
||||
if (read_file_uint64(config_path, &config_id) && config_id == 1) {
|
||||
return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
|
||||
&config_id) < 0 && errno == ENOENT;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
|
||||
&invalid_config_id) < 0 && errno == ENOENT;
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -1990,8 +1977,7 @@ compute_topology_builtins(struct brw_context *brw)
|
||||
for (int i = 0; i < sizeof(devinfo->eu_masks); i++)
|
||||
brw->perfquery.sys_vars.n_eus += util_bitcount(devinfo->eu_masks[i]);
|
||||
|
||||
brw->perfquery.sys_vars.eu_threads_count =
|
||||
brw->perfquery.sys_vars.n_eus * devinfo->num_thread_per_eu;
|
||||
brw->perfquery.sys_vars.eu_threads_count = devinfo->num_thread_per_eu;
|
||||
|
||||
/* At the moment the subslice mask builtin has groups of 3bits for each
|
||||
* slice.
|
||||
|
||||
@@ -1363,7 +1363,8 @@ intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
|
||||
for (i = 0; i < num_mods && i < max; i++) {
|
||||
if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
|
||||
f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
|
||||
f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
|
||||
f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
|
||||
f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
|
||||
external_only[i] = GL_TRUE;
|
||||
}
|
||||
else {
|
||||
|
||||
@@ -414,9 +414,15 @@ st_new_renderbuffer_fb(enum pipe_format format, unsigned samples, boolean sw)
|
||||
case PIPE_FORMAT_R32G32B32A32_FLOAT:
|
||||
strb->Base.InternalFormat = GL_RGBA32F;
|
||||
break;
|
||||
case PIPE_FORMAT_R32G32B32X32_FLOAT:
|
||||
strb->Base.InternalFormat = GL_RGB32F;
|
||||
break;
|
||||
case PIPE_FORMAT_R16G16B16A16_FLOAT:
|
||||
strb->Base.InternalFormat = GL_RGBA16F;
|
||||
break;
|
||||
case PIPE_FORMAT_R16G16B16X16_FLOAT:
|
||||
strb->Base.InternalFormat = GL_RGB16F;
|
||||
break;
|
||||
default:
|
||||
_mesa_problem(NULL,
|
||||
"Unexpected format %s in st_new_renderbuffer_fb",
|
||||
|
||||
Reference in New Issue
Block a user