docs: Add 8.0.5 release notes

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
mesa: Bump version number to 8.0.5
2012-10-24 22:10:00 +02:00 · 2012-10-24 21:11:11 +02:00 · 2012-10-24 11:41:07 -07:00 · 2012-10-24 11:41:07 -07:00 · 2012-10-24 11:41:07 -07:00 · 2012-10-24 11:41:07 -07:00
140 changed files with 1928 additions and 509 deletions
--- a/2
+++ b/2
@@ -184,7 +184,7 @@ ultrix-gcc:

 # Rules for making release tarballs

-PACKAGE_VERSION=8.0.3
+PACKAGE_VERSION=8.0.5
 PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
 PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)

--- a/bin/get-pick-list.sh
+++ b/bin/get-pick-list.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+# Script for generating a list of candidates for cherry-picking to a stable branch
+
+# Grep for commits with "cherry picked from commit" in the commit message.
+git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
+	grep "cherry picked from commit" |\
+	sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
+
+# Grep for commits that were marked as a candidate for the stable tree.
+git log --reverse --pretty=%H -i --grep='^[[:space:]]*NOTE: This is a candidate' HEAD..origin/master |\
+while read sha
+do
+	# Check to see whether the patch is on the ignore list.
+	if [ -f .git/cherry-ignore ] ; then
+		if grep -q ^$sha .git/cherry-ignore ; then
+			continue
+		fi
+	fi
+
+	# Check to see if it has already been picked over.
+	if grep -q ^$sha already_picked ; then
+		continue
+	fi
+
+	git log -n1 --pretty=oneline $sha | cat
+done
+
+rm -f already_picked
--- a/bin/shortlog_mesa.sh
+++ b/bin/shortlog_mesa.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+# This script is used to generate the list of changes that
+# appears in the release notes files, with HTML formatting.
+
+
+typeset -i in_log=0
+
+git shortlog $* | while read l
+do
+    if [ $in_log -eq 0 ]; then
+	echo '<p>'$l'</p>'
+	echo '<ul>'
+	in_log=1
+    elif echo "$l" | egrep -q '^$' ; then
+	echo '</ul>'
+	echo
+	in_log=0
+    else
+        mesg=$(echo $l | sed 's/ (cherry picked from commit [0-9a-f]\+)//;s/\&/&amp;/g;s/</\&lt;/g;s/>/\&gt;/g')
+	echo '  <li>'${mesg}'</li>'
+    fi
+done
--- a/configs/default
+++ b/configs/default
@@ -10,7 +10,7 @@ CONFIG_NAME = default
 # Version info
 MESA_MAJOR=8
 MESA_MINOR=0
-MESA_TINY=3
+MESA_TINY=5
 MESA_VERSION = $(MESA_MAJOR).$(MESA_MINOR).$(MESA_TINY)

 # external projects.  This should be useless now that we use libdrm.
--- a/docs/relnotes-8.0.3.html
+++ b/docs/relnotes-8.0.3.html
@@ -28,7 +28,9 @@ for DRI hardware acceleration.

 <h2>MD5 checksums</h2>
 <pre>
-TBD.
+b7210a6d6e4584bd852ab29294ce717e  MesaLib-8.0.3.tar.gz
+cc5ee15e306b8c15da6a478923797171  MesaLib-8.0.3.tar.bz2
+32773634a0f7e70a680505a81426eccf  MesaLib-8.0.3.zip
 </pre>

 <h2>New features</h2>
--- a/docs/relnotes-8.0.4.html
+++ b/docs/relnotes-8.0.4.html
@@ -0,0 +1,201 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<h1>Mesa 8.0.4 Release Notes / July 10, 2012</h1>
+
+<p>
+Mesa 8.0.4 is a bug fix release which fixes bugs found since the 8.0.2 release.
+</p>
+<p>
+Mesa 8.0.4 implements the OpenGL 3.0 API, but the version reported by
+glGetString(GL_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.0.
+</p>
+<p>
+See the <a href="install.html">Compiling/Installing page</a> for prerequisites
+for DRI hardware acceleration.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+02b96082d2f1ad72e7385f4022afafb9  MesaLib-8.0.4.tar.gz
+d546f988adfdf986cff45b1efa2d8a46  MesaLib-8.0.4.tar.bz2
+1f0fdabe6e8019d4de6c16e20e74d163  MesaLib-8.0.4.zip
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45967">Bug 45967</a> - piglit getteximage-invalid-format-for-packed-type regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47742">Bug 47742</a> - [softpipe] piglit fbo-generatemipmap-array regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=48141">Bug 48141</a> - [vmwgfx] src/gallium/auxiliary/util/u_inlines.h:256:pipe_buffer_map_range: Assertion `offset + length &lt;= buffer-&gt;width0' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=48472">Bug 48472</a> - GPU Lockup while running demo (rzr - the scene is dead) in wine</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=50033">Bug 50033</a> - src/mesa/state_tracker/st_cb_fbo.c:379:st_render_texture: Assertion `strb-&gt;rtt_level &lt;= strb-&gt;texture-&gt;last_level' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=50621">Bug 50621</a> - Mesa fails its test suite with a buffer overflow.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=50298">Bug 50298</a> - [ILK IVB bisected]Ogles2conform GL/sin/sin_float_vert_xvary.test regressed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=51574">Bug 51574</a> - ir_loop_jump constructor assigns member variable to itself</li>
+
+<!-- <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=">Bug </a> - </li> -->
+
+</ul>
+
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-8.0.3..mesa-8.0.4
+</pre>
+
+<p>Andreas Betz (1):</p>
+<ul>
+  <li>vega: fix 565 color unpacking bug</li>
+</ul>
+
+<p>Antoine Labour (2):</p>
+<ul>
+  <li>meta: Cleanup the resources we allocate.</li>
+  <li>mesa: Free uniforms correclty.</li>
+</ul>
+
+<p>Brian Paul (22):</p>
+<ul>
+  <li>docs: add link to 8.0.3 release notes</li>
+  <li>mesa: fix Z32_FLOAT -&gt; uint conversion functions</li>
+  <li>draw: fix primitive restart bug by using the index buffer offset</li>
+  <li>st/mesa: fix glDrawPixels(GL_DEPTH_COMPONENT) color output</li>
+  <li>svga: fix synchronization bug between sampler views and surfaces</li>
+  <li>mesa: new _mesa_error_check_format_and_type() function</li>
+  <li>mesa: add missing GL_UNSIGNED_INT_10F_11F_11F_REV case</li>
+  <li>mesa: fix missing return value in getteximage_error_check()</li>
+  <li>st/mesa: pass GL_MAP_INVALIDATE_RANGE_BIT to gallium drivers</li>
+  <li>svga: add 0.5 in float-&gt;int conversion of sample min/max lod</li>
+  <li>svga: fix min/max lod clamping</li>
+  <li>svga: change PIPE_CAPF_MAX_TEXTURE_LOD_BIAS from 16.0 to 15.0</li>
+  <li>st/mesa: add fallback pipe formats for (compressed) R, RG formats</li>
+  <li>st/mesa: copy num_immediates field when copying the immediates array</li>
+  <li>svga: move svga_texture() casts/calls in svga_surface_copy()</li>
+  <li>svga: reset vertex buffer offset in svga_release_user_upl_buffers()</li>
+  <li>st/mesa: don't set PIPE_BIND_DISPLAY_TARGET for user-created renderbuffers</li>
+  <li>st/mesa: use private pipe_sampler_view in decompress_with_blit()</li>
+  <li>st/mesa: add null pointer check in st_texture_image_map()</li>
+  <li>st/mesa: fix mipmap image size computation w.r.t. texture arrays</li>
+  <li>draw: fix missing immediates bug in polygon stipple code</li>
+  <li>st/mesa: fix max_offset computation for base vertex</li>
+</ul>
+
+<p>Christoph Bumiller (1):</p>
+<ul>
+  <li>nv50: handle NEG,ABS modifiers for short RCP encoding</li>
+</ul>
+
+<p>Dylan Noblesmith (1):</p>
+<ul>
+  <li>mesa: require GL_MAX_SAMPLES &gt;= 4 for GL 3.0</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+  <li>i965/vs: Fix texelFetchOffset()</li>
+</ul>
+
+<p>Ian Romanick (5):</p>
+<ul>
+  <li>docs: Add 8.0.3 release md5sums</li>
+  <li>glx/tests: Fix off-by-one error in allocating extension string buffer</li>
+  <li>glsl: Remove spurious printf messages</li>
+  <li>glsl: Fix pi/2 constant in acos built-in function</li>
+  <li>mesa: Bump version number to 8.0.4</li>
+</ul>
+
+<p>José Fonseca (2):</p>
+<ul>
+  <li>mesa: Avoid void acinclude.m4 Android.common.mk Android.mk autogen.sh bin common.py configs configure.ac docs doxygen include Makefile scons SConstruct src tests arithmetic.</li>
+  <li>draw: Ensure that prepare is always run after LLVM garbagge collection.</li>
+</ul>
+
+<p>Kenneth Graunke (15):</p>
+<ul>
+  <li>mesa: Check for a negative "size" parameter in glCopyBufferSubData().</li>
+  <li>i965: Fix brw_swap_cmod() for LE/GE comparisons.</li>
+  <li>glsl: Remove unused ir_loop_jump::loop pointer.</li>
+  <li>ralloc: Fix ralloc_parent() of memory allocated out of the NULL context.</li>
+  <li>mesa: Restore depth texture state on glPopAttrib(GL_TEXTURE_BIT).</li>
+  <li>glsl/builtins: Fix textureGrad() for Array samplers.</li>
+  <li>mesa: Unbind ARB_copy_buffer and transform feedback buffers on delete.</li>
+  <li>mesa: Support BindBuffer{Base,Offset,Range} with a buffer of 0.</li>
+  <li>mesa: Unbind ARB_transform_feedback2 binding points on Delete too.</li>
+  <li>meta: Fix GL_RENDERBUFFER binding in decompress_texture_image().</li>
+  <li>i965/fs: Fix texelFetchOffset() on pre-Gen7.</li>
+  <li>i965/vs: Fix texelFetchOffset() on pre-Gen7.</li>
+  <li>i965/fs: Fix user-defined FS outputs with less than four components.</li>
+  <li>glsl: Hook up loop_variable_state destructor to plug a memory leak.</li>
+  <li>glsl: Don't trust loop analysis in the presence of function calls.</li>
+</ul>
+
+<p>Kurt Roeckx (1):</p>
+<ul>
+  <li>i830: Fix crash for GL_STENCIL_TEST in i830Enable()</li>
+</ul>
+
+<p>Lukas Rössler (1):</p>
+<ul>
+  <li>glu: fix two Clang warnings</li>
+</ul>
+
+<p>Marek Olšák (2):</p>
+<ul>
+  <li>mesa: allow exposing GL3 without EXT_texture_integer</li>
+  <li>st/mesa: don't do srgb-&gt;linear conversion in decompress_with_blit</li>
+</ul>
+
+<p>Paul Seidler (1):</p>
+<ul>
+  <li>tests: include mesa headers</li>
+</ul>
+
+<p>Stéphane Marchesin (3):</p>
+<ul>
+  <li>glx: Handle a null reply in QueryVersion.</li>
+  <li>i915g: Don't invert signalled/unsignalled fences</li>
+  <li>i915g: Don't avoid flushing when we have a pending fence.</li>
+</ul>
+
+<p>Thomas Gstädtner (1):</p>
+<ul>
+  <li>gallium/targets: pass ldflags parameter to MKLIB</li>
+</ul>
+
+<p>Vadim Girlin (2):</p>
+<ul>
+  <li>st/mesa: set stObj-&gt;lastLevel in guess_and_alloc_texture</li>
+  <li>r600g: check gpr count limit</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+  <li>st/mesa: Fix uninitialized members in glsl_to_tgsi_visitor constructor.</li>
+</ul>
+
+</body>
+</html>
--- a/docs/relnotes-8.0.5.html
+++ b/docs/relnotes-8.0.5.html
@@ -0,0 +1,252 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<h1>Mesa 8.0.5 Release Notes / October 24, 2012</h1>
+
+<p>
+Mesa 8.0.5 is a bug fix release which fixes bugs found since the 8.0.4 release.
+</p>
+<p>
+Mesa 8.0.5 implements the OpenGL 3.0 API, but the version reported by
+glGetString(GL_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.0.
+</p>
+<p>
+See the <a href="install.html">Compiling/Installing page</a> for prerequisites
+for DRI hardware acceleration.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+TBD
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44912">Bug 44912</a> - [bisected] WebGL conformance/textures/texture-mips tests fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=46644">Bug 46644</a> - Sandybridge Mobile: ARBfp TXP with coords from fragment.color doesn't apply W divide</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=46784">Bug 46784</a> - MAD using multiply written register fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47375">Bug 47375</a> - Blender crash on startup after upgrade to mesa 8.0.1</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=48120">Bug 48120</a> - GL_EXT_texture_sRGB_decode still broken</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=48628">Bug 48628</a> - [bisected ILK]Oglc fogexp(basic.allCases) regressed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=49772">Bug 49772</a> - [SNB]Oglc depth-stencil(basic.read.ds) regressed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=52129">Bug 52129</a> - [Bisected ILK]Piglit spec_ARB_shader_texture_lod_execution_glsl-fs-shadow2DGradARB-01  regressed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=52382">Bug 52382</a> - [ivb gt1] Severe image corruption and GPU Hang, too many PS threads</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=52563">Bug 52563</a> - build failure - struct radeon_renderbuffer has no member named Base</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53311">Bug 53311</a> - [Bisected IVB]Oglc transform_feedback(advanced.transformFeedback.points) Invalid argument</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53314">Bug 53314</a> - [llvmpipe] src/gallium/drivers/llvmpipe/lp_texture.c:920:llvmpipe_get_texture_tile_layout: Assertion `x &lt; lpr-&gt;tiles_per_row[level]' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53316">Bug 53316</a> - [llvmpipe] src/gallium/drivers/llvmpipe/lp_texture.c:601:llvmpipe_get_transfer: Assertion `resource' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53317">Bug 53317</a> - [llvmpipe] SIGSEGV src/gallium/auxiliary/gallivm/lp_bld_sample.c:99</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53318">Bug 53318</a> - [softpipe] sp_state_shader.c:194:softpipe_delete_fs_state: Assertion `var != softpipe-&gt;fs_variant' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53319">Bug 53319</a> - [softpipe] sp_texture.c:322:softpipe_get_transfer: Assertion `level &lt;= resource-&gt;last_level' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53618">Bug 53618</a> - [Bisected i915]Piglit glx_GLX_ARB_create_context_NULL_attribute_list Aborted</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54183">Bug 54183</a> - [Bisected ILK regression]many piglit/oglc/ogles2 cases Segmentation fault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54193">Bug 54193</a> - output_components uninitialized in fs_visitor::emit_fb_writes()</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=54301">Bug 54301</a> - [Bisected ILK regression]Piglit glx_GLX_ARB_create_context_forward-compatible_flag_with_3.0 Segmentation fault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=56211">Bug 56211</a> - src/mesa/state_tracker/st_cb_texture.c:1123:copy_image_data_to_texture: Assertion `u_minify(stImage-&gt;pt-&gt;height0, src_level) == stImage-&gt;base.Height' failed.</li>
+
+<!-- <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=">Bug </a> - </li> -->
+
+</ul>
+
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+  git log mesa-8.0.4..mesa-8.0.5
+</pre>
+
+<p>Alex Deucher (3):</p>
+<ul>
+  <li>r600g: 8.0.x support for Trinity</li>
+  <li>r600g: add new Sumo, Palm, BTC pci ids</li>
+  <li>r600g: add additional evergreen pci ids</li>
+</ul>
+
+<p>Andreas Boll (4):</p>
+<ul>
+  <li>docs/relnotes-8.0.4: fix html markup</li>
+  <li>mesa: fix html in shortlog_mesa.sh script</li>
+  <li>mesa: add get-pick-list.sh script into bin/</li>
+  <li>mesa: Bump version number to 8.0.5</li>
+</ul>
+
+<p>Brian Paul (18):</p>
+<ul>
+  <li>mesa: use _mesa_is_user_fbo() and _mesa_is_winsys_fbo() functions</li>
+  <li>intel: use _mesa_is_winsys/user_fbo() helpers</li>
+  <li>st/egl: fix uninitialized pointer bug</li>
+  <li>mesa: added Ian's shortlog_mesa.sh script in bin/</li>
+  <li>mesa: loosen small matrix determinant check</li>
+  <li>xlib: add X error handler around XGetImage() call</li>
+  <li>radeon: set swrast_renderbuffer::ColorType field when mapping renderbuffers</li>
+  <li>svga: fix invalid memory reference in needs_to_create_zero()</li>
+  <li>meta: fix glDrawPixels fallback test, stencil drawing</li>
+  <li>radeon: fix Base/base typo</li>
+  <li>st/mesa: fix glCopyTexSubImage crash</li>
+  <li>gallivm: fix crash in lp_sampler_static_state()</li>
+  <li>st/mesa: fix renderbuffer validation bug</li>
+  <li>softpipe: fix softpipe_delete_fs_state() failed assertion</li>
+  <li>mesa: raise GL_INVALID_OPERATION in glGenerateMipmap for missing base image</li>
+  <li>st/mesa: s/CALLOC/calloc/ to fix allocation bug</li>
+  <li>mesa: do internal format error checking for glTexStorage()</li>
+  <li>mesa: fix incorrect error for glCompressedSubTexImage</li>
+</ul>
+
+<p>Chad Versace (3):</p>
+<ul>
+  <li>mesa: Don't advertise GLES extensions in GL contexts</li>
+  <li>i830: Fix stack corruption</li>
+  <li>swrast: Fix implicit declaration warnings</li>
+</ul>
+
+<p>Chris Forbes (1):</p>
+<ul>
+  <li>mesa: fix dropped &amp;&amp; in glGetStringi()</li>
+</ul>
+
+<p>Christoph Bumiller (1):</p>
+<ul>
+  <li>st/mesa: call update_renderbuffer_surface for sRGB renderbuffers, too</li>
+</ul>
+
+<p>Eric Anholt (9):</p>
+<ul>
+  <li>i965/gen7: Reduce GT1 WM thread count according to updated BSpec.</li>
+  <li>i965/fs: Invalidate live intervals in passes that remove an instruction.</li>
+  <li>i965: Fix bug in the old FS backend's projtex() calculation.</li>
+  <li>i965: Add support for GL_SKIP_DECODE_EXT on other SRGB formats.</li>
+  <li>i965/vs: Convert EdgeFlagPointer values appropriately for the VS on gen4.</li>
+  <li>i965: Fix accumulator_contains() test to also reject swizzles of the dst.</li>
+  <li>mesa: Fix glPopAttrib() behavior on GL_FRAMEBUFFER_SRGB.</li>
+  <li>mesa: In conditional rendering fallback, check the query status.</li>
+  <li>i965: Drop the confusing saturate argument to math instruction setup.</li>
+</ul>
+
+<p>Ian Romanick (8):</p>
+<ul>
+  <li>docs: Add 8.0.4 release md5sums</li>
+  <li>Revert "i965: Avoid unnecessary recompiles for shaders that don't use dFdy()."</li>
+  <li>i965: Fix regression in depth texture rendering on pre-SNB</li>
+  <li>dri2: Fix bug in attribute handling for non-desktop OpenGL contexts</li>
+  <li>mesa: Generate an error when glCopyTexImage border is invalid</li>
+  <li>mesa/es: Validate glTexImage border in Mesa code rather than the ES wrapper</li>
+  <li>mesa: Allow glGetTexParameter of GL_TEXTURE_SRGB_DECODE_EXT</li>
+  <li>dri_util: Use calloc to allocate __DRIcontext</li>
+</ul>
+
+<p>Jonas Maebe (1):</p>
+<ul>
+  <li>darwin: do not create double-buffered offscreen pixel formats</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+  <li>intel: move error on create context to proper path</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+  <li>mesa: disable MSVC global optimization in pack.c</li>
+</ul>
+
+<p>Kenneth Graunke (8):</p>
+<ul>
+  <li>mesa: Use GLdouble for depthMax in final unpack conversions.</li>
+  <li>i965/fs: Initialize output_components[] by filling it with zeros.</li>
+  <li>mesa: Prevent repeated glDeleteShader() from blowing away our refcounts.</li>
+  <li>i965: Support MESA_FORMAT_SIGNED_RGBA_16.</li>
+  <li>glsl: Fix #pragma invariant(all) language version check.</li>
+  <li>i965/vs: Don't clobber sampler message MRFs with subexpressions.</li>
+  <li>intel: Move finish_batch() call before MI_BATCH_BUFFER_END and padding.</li>
+  <li>i965/fs: Don't use brw-&gt;fragment_program in calculate_urb_setup().</li>
+</ul>
+
+<p>Maarten Lankhorst (1):</p>
+<ul>
+  <li>winsys/radeon: Remove unnecessary pipe_thread_destroy in radeon_drm_cs_destroy</li>
+</ul>
+
+<p>Marek Olšák (6):</p>
+<ul>
+  <li>mesa: remove assertions that do not allow compressed 2D_ARRAY textures</li>
+  <li>r300g: fix colormask with non-BGRA formats</li>
+  <li>r600g: fix RSQ of negative value on Cayman</li>
+  <li>r600g: fix EXP on Cayman</li>
+  <li>r600g: fix instance divisor on Cayman</li>
+  <li>gallium/u_blit: set dst format from pipe_resource, not pipe_surface</li>
+</ul>
+
+<p>Michel Dänzer (2):</p>
+<ul>
+  <li>st/mesa: Fix source miptree level for copying data to finalized miptree.</li>
+  <li>st/mesa: Fix assertions for copying texture image to finalized miptree.</li>
+</ul>
+
+<p>Niels Ole Salscheider (1):</p>
+<ul>
+  <li>st/mesa: index can be negative in the PROGRAM_CONSTANT case</li>
+</ul>
+
+<p>Paul Berry (5):</p>
+<ul>
+  <li>i965: Compute dFdy() correctly for FBOs.</li>
+  <li>mesa: Add UsesDFdy to struct gl_fragment_program.</li>
+  <li>i965: Avoid unnecessary recompiles for shaders that don't use dFdy().</li>
+  <li>i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.</li>
+  <li>i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.</li>
+</ul>
+
+<p>Stéphane Marchesin (1):</p>
+<ul>
+  <li>glsl/linker: Avoid buffer over-run in parcel_out_uniform_storage::visit_field</li>
+</ul>
+
+<p>Tapani Pälli (2):</p>
+<ul>
+  <li>xmlconfig: use __progname when building for Android</li>
+  <li>android: do not expose single buffered eglconfigs</li>
+</ul>
+
+<p>Vadim Girlin (1):</p>
+<ul>
+  <li>winsys/radeon: fix relocs caching</li>
+</ul>
+
+</body>
+</html>
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -13,6 +13,8 @@ The release notes summarize what's new or changed in each Mesa release.
 </p>

 <UL>
+<LI><A HREF="relnotes-8.0.4.html">8.0.4 release notes</A>
+<LI><A HREF="relnotes-8.0.3.html">8.0.3 release notes</A>
 <LI><A HREF="relnotes-8.0.2.html">8.0.2 release notes</A>
 <LI><A HREF="relnotes-8.0.1.html">8.0.1 release notes</A>
 <LI><A HREF="relnotes-8.0.html">8.0 release notes</A>
--- a/include/pci_ids/r600_pci_ids.h
+++ b/include/pci_ids/r600_pci_ids.h
@@ -157,6 +157,7 @@ CHIPSET(0x68FE, CEDAR_68FE, CEDAR)

 CHIPSET(0x68C0, REDWOOD_68C0, REDWOOD)
 CHIPSET(0x68C1, REDWOOD_68C1, REDWOOD)
+CHIPSET(0x68C7, REDWOOD_68C7, REDWOOD)
 CHIPSET(0x68C8, REDWOOD_68C8, REDWOOD)
 CHIPSET(0x68C9, REDWOOD_68C9, REDWOOD)
 CHIPSET(0x68D8, REDWOOD_68D8, REDWOOD)
@@ -179,6 +180,8 @@ CHIPSET(0x6880, CYPRESS_6880, CYPRESS)
 CHIPSET(0x6888, CYPRESS_6888, CYPRESS)
 CHIPSET(0x6889, CYPRESS_6889, CYPRESS)
 CHIPSET(0x688A, CYPRESS_688A, CYPRESS)
+CHIPSET(0x688C, CYPRESS_688C, CYPRESS)
+CHIPSET(0x688D, CYPRESS_688D, CYPRESS)
 CHIPSET(0x6898, CYPRESS_6898, CYPRESS)
 CHIPSET(0x6899, CYPRESS_6899, CYPRESS)
 CHIPSET(0x689B, CYPRESS_689B, CYPRESS)
@@ -195,6 +198,7 @@ CHIPSET(0x9806, PALM_9806, PALM)
 CHIPSET(0x9807, PALM_9807, PALM)
 CHIPSET(0x9808, PALM_9808, PALM)
 CHIPSET(0x9809, PALM_9809, PALM)
+CHIPSET(0x980A, PALM_980A, PALM)

 CHIPSET(0x9640, SUMO_9640,  SUMO)
 CHIPSET(0x9641, SUMO_9641,  SUMO)
@@ -204,6 +208,7 @@ CHIPSET(0x9644, SUMO2_9644, SUMO2)
 CHIPSET(0x9645, SUMO2_9645, SUMO2)
 CHIPSET(0x9647, SUMO_9647,  SUMO)
 CHIPSET(0x9648, SUMO_9648,  SUMO)
+CHIPSET(0x9649, SUMO_9649,  SUMO)
 CHIPSET(0x964a, SUMO_964A,  SUMO)
 CHIPSET(0x964b, SUMO_964B,  SUMO)
 CHIPSET(0x964c, SUMO_964C,  SUMO)
@@ -239,6 +244,7 @@ CHIPSET(0x6729, BARTS_6729, BARTS)
 CHIPSET(0x6738, BARTS_6738, BARTS)
 CHIPSET(0x6739, BARTS_6739, BARTS)
 CHIPSET(0x673E, BARTS_673E, BARTS)
+
 CHIPSET(0x6740, TURKS_6740, TURKS)
 CHIPSET(0x6741, TURKS_6741, TURKS)
 CHIPSET(0x6742, TURKS_6742, TURKS)
@@ -249,6 +255,7 @@ CHIPSET(0x6746, TURKS_6746, TURKS)
 CHIPSET(0x6747, TURKS_6747, TURKS)
 CHIPSET(0x6748, TURKS_6748, TURKS)
 CHIPSET(0x6749, TURKS_6749, TURKS)
+CHIPSET(0x674A, TURKS_674A, TURKS)
 CHIPSET(0x6750, TURKS_6750, TURKS)
 CHIPSET(0x6751, TURKS_6751, TURKS)
 CHIPSET(0x6758, TURKS_6758, TURKS)
@@ -275,7 +282,33 @@ CHIPSET(0x6766, CAICOS_6766, CAICOS)
 CHIPSET(0x6767, CAICOS_6767, CAICOS)
 CHIPSET(0x6768, CAICOS_6768, CAICOS)
 CHIPSET(0x6770, CAICOS_6770, CAICOS)
+CHIPSET(0x6771, CAICOS_6771, CAICOS)
 CHIPSET(0x6772, CAICOS_6772, CAICOS)
 CHIPSET(0x6778, CAICOS_6778, CAICOS)
 CHIPSET(0x6779, CAICOS_6779, CAICOS)
 CHIPSET(0x677B, CAICOS_677B, CAICOS)
+
+CHIPSET(0x9900, ARUBA_9900, ARUBA)
+CHIPSET(0x9901, ARUBA_9901, ARUBA)
+CHIPSET(0x9903, ARUBA_9903, ARUBA)
+CHIPSET(0x9904, ARUBA_9904, ARUBA)
+CHIPSET(0x9905, ARUBA_9905, ARUBA)
+CHIPSET(0x9906, ARUBA_9906, ARUBA)
+CHIPSET(0x9907, ARUBA_9907, ARUBA)
+CHIPSET(0x9908, ARUBA_9908, ARUBA)
+CHIPSET(0x9909, ARUBA_9909, ARUBA)
+CHIPSET(0x990A, ARUBA_990A, ARUBA)
+CHIPSET(0x990F, ARUBA_990F, ARUBA)
+CHIPSET(0x9910, ARUBA_9910, ARUBA)
+CHIPSET(0x9913, ARUBA_9913, ARUBA)
+CHIPSET(0x9917, ARUBA_9917, ARUBA)
+CHIPSET(0x9918, ARUBA_9918, ARUBA)
+CHIPSET(0x9919, ARUBA_9919, ARUBA)
+CHIPSET(0x9990, ARUBA_9990, ARUBA)
+CHIPSET(0x9991, ARUBA_9991, ARUBA)
+CHIPSET(0x9992, ARUBA_9992, ARUBA)
+CHIPSET(0x9993, ARUBA_9993, ARUBA)
+CHIPSET(0x9994, ARUBA_9994, ARUBA)
+CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
+CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
+CHIPSET(0x99A4, ARUBA_99A4, ARUBA)
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -498,6 +498,14 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay *dpy)
      for (j = 0; dri2_dpy->driver_configs[j]; j++) {
         const EGLint surface_type = EGL_WINDOW_BIT | EGL_PBUFFER_BIT;
         struct dri2_egl_config *dri2_conf;
+         unsigned int double_buffered = 0;
+
+         dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[j],
+            __DRI_ATTRIB_DOUBLE_BUFFER, &double_buffered);
+
+         /* support only double buffered configs */
+         if (!double_buffered)
+            continue;

         dri2_conf = dri2_add_config(dpy, dri2_dpy->driver_configs[j],
               count + 1, visuals[i].size, surface_type, NULL,
@@ -523,17 +531,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay *dpy)
      /* there is no front buffer so no OpenGL */
      dri2_conf->base.RenderableType &= ~EGL_OPENGL_BIT;
      dri2_conf->base.Conformant &= ~EGL_OPENGL_BIT;
-
-      /*
-       * We want to make sure GL_DRAW_BUFFER for windows or pbuffers is always
-       * GL_BACK.  For EGL configs that do not have a double DRI config, clear
-       * the surface type.
-       *
-       * This is just to be on the safe side.  dri2_add_config never sets
-       * EGL_WINDOW_BIT or EGL_PBUFFER_BIT for such configs.
-       */
-      if (!dri2_conf->dri_double_config)
-         dri2_conf->base.SurfaceType = 0;
   }

   return (count != 0);
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_llvm.c
@@ -65,8 +65,13 @@ static void
 draw_llvm_garbage_collect_callback(void *cb_data)
 {
   struct draw_llvm *llvm = (struct draw_llvm *) cb_data;
+   struct draw_context *draw = llvm->draw;
   struct draw_llvm_variant_list_item *li;

+   /* Ensure prepare will be run and shaders recompiled */
+   assert(!draw->suspend_flushing);
+   draw_do_flush(draw, DRAW_FLUSH_STATE_CHANGE);
+
   /* free all shader variants */
   li = first_elem(&llvm->vs_variants_list);
   while (!at_end(&llvm->vs_variants_list, li)) {
--- a/src/gallium/auxiliary/draw/draw_pipe_pstipple.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_pstipple.c
@@ -165,11 +165,16 @@ pstip_transform_decl(struct tgsi_transform_context *ctx,
 }


+/**
+ * TGSI immediate declaration transform callback.
+ * We're just counting the number of immediates here.
+ */
 static void
 pstip_transform_immed(struct tgsi_transform_context *ctx,
                      struct tgsi_full_immediate *immed)
 {
   struct pstip_transform_context *pctx = (struct pstip_transform_context *) ctx;
+   ctx->emit_immediate(ctx, immed); /* emit to output shader */
   pctx->numImmed++;
 }

--- a/src/gallium/auxiliary/draw/draw_pt.c
+++ b/src/gallium/auxiliary/draw/draw_pt.c
@@ -329,25 +329,28 @@ draw_pt_arrays_restart(struct draw_context *draw,

   if (draw->pt.user.elts) {
      /* indexed prims (draw_elements) */
+      const char *elts =
+         (const char *) draw->pt.user.elts + draw->pt.index_buffer.offset;
+
      cur_start = start;
      cur_count = 0;

      switch (draw->pt.user.eltSize) {
      case 1:
         {
-            const ubyte *elt_ub = (const ubyte *) draw->pt.user.elts;
+            const ubyte *elt_ub = (const ubyte *) elts;
            PRIM_RESTART_LOOP(elt_ub);
         }
         break;
      case 2:
         {
-            const ushort *elt_us = (const ushort *) draw->pt.user.elts;
+            const ushort *elt_us = (const ushort *) elts;
            PRIM_RESTART_LOOP(elt_us);
         }
         break;
      case 4:
         {
-            const uint *elt_ui = (const uint *) draw->pt.user.elts;
+            const uint *elt_ui = (const uint *) elts;
            PRIM_RESTART_LOOP(elt_ui);
         }
         break;
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -99,15 +99,14 @@ lp_sampler_static_state(struct lp_sampler_static_state *state,
                        const struct pipe_sampler_view *view,
                        const struct pipe_sampler_state *sampler)
 {
-   const struct pipe_resource *texture = view->texture;
+   const struct pipe_resource *texture;

   memset(state, 0, sizeof *state);

-   if(!texture)
+   if (!sampler || !view || !view->texture)
      return;

-   if(!sampler)
-      return;
+   texture = view->texture;

   /*
    * We don't copy sampler state over unless it is actually enabled, to avoid
--- a/src/gallium/auxiliary/util/u_blit.c
+++ b/src/gallium/auxiliary/util/u_blit.c
@@ -370,7 +370,7 @@ util_blit_pixels_writemask(struct blit_state *ctx,
                      dstX0, dstY0, dstX1, dstY1);

   src_format = util_format_linear(src_tex->format);
-   dst_format = util_format_linear(dst->format);
+   dst_format = util_format_linear(dst->texture->format);

   /*
    * Check for simple case:  no format conversion, no flipping, no stretching,
--- a/src/gallium/drivers/i915/i915_flush.c
+++ b/src/gallium/drivers/i915/i915_flush.c
@@ -45,7 +45,10 @@ static void i915_flush_pipe( struct pipe_context *pipe,

   draw_flush(i915->draw);

-   if (i915->batch->map == i915->batch->ptr) {
+   /* Only shortcut this if we have no fence, otherwise we must flush the
+    * empty batchbuffer to get our fence back.
+    */
+   if (!fence && i915->batch && (i915->batch->map == i915->batch->ptr)) {
      return;
   }

--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -368,7 +368,7 @@ i915_fence_signalled(struct pipe_screen *screen,
 {
   struct i915_screen *is = i915_screen(screen);

-   return is->iws->fence_signalled(is->iws, fence) == 0;
+   return is->iws->fence_signalled(is->iws, fence) == 1;
 }

 static boolean
@@ -378,7 +378,7 @@ i915_fence_finish(struct pipe_screen *screen,
 {
   struct i915_screen *is = i915_screen(screen);

-   return is->iws->fence_finish(is->iws, fence) == 0;
+   return is->iws->fence_finish(is->iws, fence) == 1;
 }


--- a/src/gallium/drivers/nv50/nv50_pc_emit.c
+++ b/src/gallium/drivers/nv50/nv50_pc_emit.c
@@ -865,8 +865,10 @@ emit_flop(struct nv_pc *pc, struct nv_instruction *i)
   assert(SFILE(i, 0) == NV_FILE_GPR);

   if (!i->is_long) {
+      assert(i->opcode == NV_OP_RCP);
      emit_form_MUL(pc, i);
-      assert(i->opcode == NV_OP_RCP && !src0->mod);
+      if (src0->mod & NV_MOD_NEG) pc->emit[0] |= 0x00400000;
+      if (src0->mod & NV_MOD_ABS) pc->emit[0] |= 0x00008000;
      return;
   }

--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -42,6 +42,16 @@ struct r300_fragment_shader;
 struct r300_vertex_shader;
 struct r300_stencilref_context;

+enum colormask_swizzle {
+    COLORMASK_BGRA,
+    COLORMASK_RGBA,
+    COLORMASK_RRRR,
+    COLORMASK_AAAA,
+    COLORMASK_GRRG,
+    COLORMASK_ARRA,
+    COLORMASK_NUM_SWIZZLES
+};
+
 struct r300_atom {
    /* Name, for debugging. */
    const char* name;
@@ -67,7 +77,7 @@ struct r300_aa_state {
 struct r300_blend_state {
    struct pipe_blend_state state;

-    uint32_t cb_clamp[8];
+    uint32_t cb_clamp[COLORMASK_NUM_SWIZZLES][8];
    uint32_t cb_noclamp[8];
    uint32_t cb_no_readwrite[8];
 };
@@ -321,6 +331,8 @@ struct r300_surface {

    /* Whether the CBZB clear is allowed on the surface. */
    boolean cbzb_allowed;
+
+    unsigned colormask_swizzle;
 };

 struct r300_texture_desc {
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -45,10 +45,12 @@ void r300_emit_blend_state(struct r300_context* r300,
    CS_LOCALS(r300);

    if (fb->nr_cbufs) {
-        if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT)
+        if (fb->cbufs[0]->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
            WRITE_CS_TABLE(blend->cb_noclamp, size);
-        else
-            WRITE_CS_TABLE(blend->cb_clamp, size);
+        } else {
+            unsigned swz = r300_surface(fb->cbufs[0])->colormask_swizzle;
+            WRITE_CS_TABLE(blend->cb_clamp[swz], size);
+        }
    } else {
        WRITE_CS_TABLE(blend->cb_no_readwrite, size);
    }
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -169,15 +169,52 @@ static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA
            dstA == PIPE_BLENDFACTOR_ONE);
 }

+/* The hardware colormask is clunky a must be swizzled depending on the format.
+ * This was figured out by trial-and-error. */
 static unsigned bgra_cmask(unsigned mask)
 {
-    /* Gallium uses RGBA color ordering while R300 expects BGRA. */
-
    return ((mask & PIPE_MASK_R) << 2) |
           ((mask & PIPE_MASK_B) >> 2) |
           (mask & (PIPE_MASK_G | PIPE_MASK_A));
 }

+static unsigned rgba_cmask(unsigned mask)
+{
+    return mask & PIPE_MASK_RGBA;
+}
+
+static unsigned rrrr_cmask(unsigned mask)
+{
+    return (mask & PIPE_MASK_R) |
+           ((mask & PIPE_MASK_R) << 1) |
+           ((mask & PIPE_MASK_R) << 2) |
+           ((mask & PIPE_MASK_R) << 3);
+}
+
+static unsigned aaaa_cmask(unsigned mask)
+{
+    return ((mask & PIPE_MASK_A) >> 3) |
+           ((mask & PIPE_MASK_A) >> 2) |
+           ((mask & PIPE_MASK_A) >> 1) |
+           (mask & PIPE_MASK_A);
+}
+
+static unsigned grrg_cmask(unsigned mask)
+{
+    return ((mask & PIPE_MASK_R) << 1) |
+           ((mask & PIPE_MASK_R) << 2) |
+           ((mask & PIPE_MASK_G) >> 1) |
+           ((mask & PIPE_MASK_G) << 2);
+}
+
+static unsigned arra_cmask(unsigned mask)
+{
+    return ((mask & PIPE_MASK_R) << 1) |
+           ((mask & PIPE_MASK_R) << 2) |
+           ((mask & PIPE_MASK_A) >> 3) |
+           (mask & PIPE_MASK_A);
+}
+
 /* Create a new blend state based on the CSO blend state.
 *
 * This encompasses alpha blending, logic/raster ops, and blend dithering. */
@@ -190,9 +227,9 @@ static void* r300_create_blend_state(struct pipe_context* pipe,
    uint32_t blend_control_noclamp = 0;    /* R300_RB3D_CBLEND: 0x4e04 */
    uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */
    uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */
-    uint32_t color_channel_mask = 0;  /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */
    uint32_t rop = 0;                 /* R300_RB3D_ROPCNTL: 0x4e18 */
    uint32_t dither = 0;              /* R300_RB3D_DITHER_CTL: 0x4e50 */
+    int i;
    CB_LOCALS;

    blend->state = *state;
@@ -331,20 +368,6 @@ static void* r300_create_blend_state(struct pipe_context* pipe,
                (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT;
    }

-    /* Color channel masks for all MRTs. */
-    color_channel_mask = bgra_cmask(state->rt[0].colormask);
-    if (r300screen->caps.is_r500 && state->independent_blend_enable) {
-        if (state->rt[1].blend_enable) {
-            color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4;
-        }
-        if (state->rt[2].blend_enable) {
-            color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8;
-        }
-        if (state->rt[3].blend_enable) {
-            color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12;
-        }
-    }
-
    /* Neither fglrx nor classic r300 ever set this, regardless of dithering
     * state. Since it's an optional implementation detail, we can leave it
     * out and never dither.
@@ -358,14 +381,27 @@ static void* r300_create_blend_state(struct pipe_context* pipe,
    */

    /* Build a command buffer. */
-    BEGIN_CB(blend->cb_clamp, 8);
-    OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
-    OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
-    OUT_CB(blend_control);
-    OUT_CB(alpha_blend_control);
-    OUT_CB(color_channel_mask);
-    OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
-    END_CB;
+    {
+        unsigned (*func[COLORMASK_NUM_SWIZZLES])(unsigned) = {
+            bgra_cmask,
+            rgba_cmask,
+            rrrr_cmask,
+            aaaa_cmask,
+            grrg_cmask,
+            arra_cmask
+        };
+
+        for (i = 0; i < COLORMASK_NUM_SWIZZLES; i++) {
+            BEGIN_CB(blend->cb_clamp[i], 8);
+            OUT_CB_REG(R300_RB3D_ROPCNTL, rop);
+            OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
+            OUT_CB(blend_control);
+            OUT_CB(alpha_blend_control);
+            OUT_CB(func[i](state->rt[0].colormask));
+            OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
+            END_CB;
+        }
+    }

    /* Build a command buffer. */
    BEGIN_CB(blend->cb_noclamp, 8);
@@ -373,7 +409,7 @@ static void* r300_create_blend_state(struct pipe_context* pipe,
    OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3);
    OUT_CB(blend_control_noclamp);
    OUT_CB(alpha_blend_control_noclamp);
-    OUT_CB(color_channel_mask);
+    OUT_CB(rgba_cmask(state->rt[0].colormask));
    OUT_CB_REG(R300_RB3D_DITHER_CTL, dither);
    END_CB;

--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -704,10 +704,87 @@ static uint32_t r300_translate_out_fmt(enum pipe_format format)
    }
 }

+static uint32_t r300_translate_colormask_swizzle(enum pipe_format format)
+{
+    switch (format) {
+    case PIPE_FORMAT_A8_UNORM:
+    case PIPE_FORMAT_A8_SNORM:
+    case PIPE_FORMAT_A16_UNORM:
+    case PIPE_FORMAT_A16_SNORM:
+    case PIPE_FORMAT_A16_FLOAT:
+    case PIPE_FORMAT_A32_FLOAT:
+        return COLORMASK_AAAA;
+
+    case PIPE_FORMAT_I8_UNORM:
+    case PIPE_FORMAT_I8_SNORM:
+    case PIPE_FORMAT_L8_UNORM:
+    case PIPE_FORMAT_L8_SNORM:
+    case PIPE_FORMAT_R8_UNORM:
+    case PIPE_FORMAT_R8_SNORM:
+    case PIPE_FORMAT_R32_FLOAT:
+    case PIPE_FORMAT_L32_FLOAT:
+    case PIPE_FORMAT_I32_FLOAT:
+        return COLORMASK_RRRR;
+
+    case PIPE_FORMAT_L8A8_SNORM:
+    case PIPE_FORMAT_L8A8_UNORM:
+    case PIPE_FORMAT_L16A16_UNORM:
+    case PIPE_FORMAT_L16A16_SNORM:
+    case PIPE_FORMAT_L16A16_FLOAT:
+    case PIPE_FORMAT_L32A32_FLOAT:
+        return COLORMASK_ARRA;
+
+    case PIPE_FORMAT_R8G8_SNORM:
+    case PIPE_FORMAT_R8G8_UNORM:
+    case PIPE_FORMAT_R16G16_UNORM:
+    case PIPE_FORMAT_R16G16_SNORM:
+    case PIPE_FORMAT_R16G16_FLOAT:
+    case PIPE_FORMAT_R32G32_FLOAT:
+        return COLORMASK_GRRG;
+
+    case PIPE_FORMAT_B5G6R5_UNORM:
+    case PIPE_FORMAT_B5G5R5A1_UNORM:
+    case PIPE_FORMAT_B5G5R5X1_UNORM:
+    case PIPE_FORMAT_B4G4R4A4_UNORM:
+    case PIPE_FORMAT_B4G4R4X4_UNORM:
+    case PIPE_FORMAT_B8G8R8A8_UNORM:
+    /*case PIPE_FORMAT_B8G8R8A8_SNORM:*/
+    case PIPE_FORMAT_B8G8R8X8_UNORM:
+    /*case PIPE_FORMAT_B8G8R8X8_SNORM:*/
+    case PIPE_FORMAT_B10G10R10A2_UNORM:
+        return COLORMASK_BGRA;
+
+    case PIPE_FORMAT_R8G8B8X8_UNORM:
+    /*case PIPE_FORMAT_R8G8B8X8_SNORM:*/
+    case PIPE_FORMAT_R8G8B8A8_UNORM:
+    case PIPE_FORMAT_R8G8B8A8_SNORM:
+    case PIPE_FORMAT_R10G10B10A2_UNORM:
+    case PIPE_FORMAT_R10G10B10X2_SNORM:
+    case PIPE_FORMAT_R16_UNORM:
+    case PIPE_FORMAT_R16G16B16A16_UNORM:
+    case PIPE_FORMAT_R16_SNORM:
+    case PIPE_FORMAT_R16G16B16A16_SNORM:
+    case PIPE_FORMAT_R16_FLOAT:
+    case PIPE_FORMAT_R16G16B16A16_FLOAT:
+    case PIPE_FORMAT_R32G32B32A32_FLOAT:
+    case PIPE_FORMAT_L16_UNORM:
+    case PIPE_FORMAT_L16_SNORM:
+    case PIPE_FORMAT_L16_FLOAT:
+    case PIPE_FORMAT_I16_UNORM:
+    case PIPE_FORMAT_I16_SNORM:
+    case PIPE_FORMAT_I16_FLOAT:
+        return COLORMASK_RGBA;
+
+    default:
+        return ~0; /* Unsupported. */
+    }
+}
+
 boolean r300_is_colorbuffer_format_supported(enum pipe_format format)
 {
    return r300_translate_colorformat(format) != ~0 &&
-           r300_translate_out_fmt(format) != ~0;
+           r300_translate_out_fmt(format) != ~0 &&
+           r300_translate_colormask_swizzle(format) != ~0;
 }

 boolean r300_is_zs_format_supported(enum pipe_format format)
@@ -827,6 +904,8 @@ static void r300_texture_setup_fb_state(struct r300_surface *surf)
                R300_COLOR_TILE(tex->tex.macrotile[level]) |
                R300_COLOR_MICROTILE(tex->tex.microtile);
        surf->format = r300_translate_out_fmt(surf->base.format);
+        surf->colormask_swizzle =
+            r300_translate_colormask_swizzle(surf->base.format);
    }
 }

--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -930,7 +930,7 @@ int evergreen_context_init(struct r600_context *ctx, struct r600_screen *screen)
 	}

 	/* add blocks */
-	if (ctx->screen->family == CHIP_CAYMAN)
+	if (ctx->screen->family >= CHIP_CAYMAN)
 		r = r600_context_add_block(ctx, cayman_config_reg_list,
 					   Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	else
@@ -938,7 +938,7 @@ int evergreen_context_init(struct r600_context *ctx, struct r600_screen *screen)
 					   Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	if (r)
 		goto out_err;
-	if (ctx->screen->family == CHIP_CAYMAN)
+	if (ctx->screen->family >= CHIP_CAYMAN)
 		r = r600_context_add_block(ctx, cayman_context_reg_list,
 					   Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 	else
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -66,6 +66,7 @@ enum radeon_family {
 	CHIP_TURKS,
 	CHIP_CAICOS,
 	CHIP_CAYMAN,
+	CHIP_ARUBA,
 	CHIP_LAST,
 };

--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2689,7 +2689,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 	unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
 	unsigned format, num_format, format_comp, endian;
 	u32 *bytecode;
-	int i, r;
+	int i, j, r;

 	/* Vertex element offsets need special handling. If the offset is
 	 * bigger than what we can put in the fetch instruction we need to
@@ -2708,24 +2708,40 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru

 	for (i = 0; i < ve->count; i++) {
 		if (elements[i].instance_divisor > 1) {
-			struct r600_bytecode_alu alu;
-
-			memset(&alu, 0, sizeof(alu));
-			alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
-			alu.src[0].sel = 0;
-			alu.src[0].chan = 3;
-
-			alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
-			alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
-
-			alu.dst.sel = i + 1;
-			alu.dst.chan = 3;
-			alu.dst.write = 1;
-			alu.last = 1;
-
-			if ((r = r600_bytecode_add_alu(&bc, &alu))) {
-				r600_bytecode_clear(&bc);
-				return r;
+			if (rctx->chip_class == CAYMAN) {
+				for (j = 0; j < 4; j++) {
+					struct r600_bytecode_alu alu;
+					memset(&alu, 0, sizeof(alu));
+					alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+					alu.src[0].sel = 0;
+					alu.src[0].chan = 3;
+					alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+					alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
+					alu.dst.sel = i + 1;
+					alu.dst.chan = j;
+					alu.dst.write = j == 3;
+					alu.last = j == 3;
+					if ((r = r600_bytecode_add_alu(&bc, &alu))) {
+						r600_bytecode_clear(&bc);
+						return r;
+					}
+				}
+			} else {
+				struct r600_bytecode_alu alu;
+				memset(&alu, 0, sizeof(alu));
+				alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
+				alu.src[0].sel = 0;
+				alu.src[0].chan = 3;
+				alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+				alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
+				alu.dst.sel = i + 1;
+				alu.dst.chan = 3;
+				alu.dst.write = 1;
+				alu.last = 1;
+				if ((r = r600_bytecode_add_alu(&bc, &alu))) {
+					r600_bytecode_clear(&bc);
+					return r;
+				}
 			}
 		}
 	}
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -333,6 +333,7 @@ static const char *r600_get_family_name(enum radeon_family family)
 	case CHIP_TURKS: return "AMD TURKS";
 	case CHIP_CAICOS: return "AMD CAICOS";
 	case CHIP_CAYMAN: return "AMD CAYMAN";
+	case CHIP_ARUBA: return "AMD ARUBA";
 	default: return "AMD unknown";
 	}
 }
@@ -777,7 +778,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 	}

 	/* setup class */
-	if (rscreen->family == CHIP_CAYMAN) {
+	if (rscreen->family >= CHIP_CAYMAN) {
 		rscreen->chip_class = CAYMAN;
 	} else if (rscreen->family >= CHIP_CEDAR) {
 		rscreen->chip_class = EVERGREEN;
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1277,6 +1277,14 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 	if (ctx.bc->chip_class == CAYMAN)
 		cm_bytecode_add_cf_end(ctx.bc);

+	/* check GPR limit - we have 124 = 128 - 4
+	 * (4 are reserved as alu clause temporary registers) */
+	if (ctx.bc->ngpr > 124) {
+		R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
+		r = -ENOMEM;
+		goto out_err;
+	}
+
 	free(ctx.literals);
 	tgsi_parse_free(&ctx.parse);
 	return 0;
@@ -1453,6 +1461,11 @@ static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
 		alu.inst = ctx->inst_info->r600_opcode;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 			r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
+
+			/* RSQ should take the absolute value of src */
+			if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
+				r600_bytecode_src_set_abs(&alu.src[j]);
+			}
 		}
 		tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 		alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
@@ -2856,10 +2869,8 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)

 				alu.dst.sel = ctx->temp_reg;
 				alu.dst.chan = i;
-				if (i == 0)
-					alu.dst.write = 1;
-				if (i == 2)
-					alu.last = 1;
+				alu.dst.write = i == 0;
+				alu.last = i == 2;
 				r = r600_bytecode_add_alu(ctx->bc, &alu);
 				if (r)
 					return r;
--- a/src/gallium/drivers/softpipe/sp_state_shader.c
+++ b/src/gallium/drivers/softpipe/sp_state_shader.c
@@ -158,8 +158,10 @@ softpipe_bind_fs_state(struct pipe_context *pipe, void *fs)

   softpipe->fs = fs;

-   if (fs == NULL)
-      softpipe->fs_variant = NULL;
+   /* This depends on the current fragment shader and must always be
+    * re-validated before use.
+    */
+   softpipe->fs_variant = NULL;

   if (state)
      draw_bind_fragment_shader(softpipe->draw,
--- a/src/gallium/drivers/svga/svga_pipe_blit.c
+++ b/src/gallium/drivers/svga/svga_pipe_blit.c
@@ -44,8 +44,7 @@ static void svga_surface_copy(struct pipe_context *pipe,
                              const struct pipe_box *src_box)
 {
   struct svga_context *svga = svga_context(pipe);
-   struct svga_texture *stex = svga_texture(src_tex);
-   struct svga_texture *dtex = svga_texture(dst_tex);
+   struct svga_texture *stex, *dtex;
 /*   struct pipe_screen *screen = pipe->screen;
   SVGA3dCopyBox *box;
   enum pipe_error ret;
@@ -63,6 +62,9 @@ static void svga_surface_copy(struct pipe_context *pipe,
      return;
   }

+   stex = svga_texture(src_tex);
+   dtex = svga_texture(dst_tex);
+
 #if 0
   srcsurf = screen->get_tex_surface(screen, src_tex,
                                     src_level, src_box->z, src_box->z,
--- a/src/gallium/drivers/svga/svga_pipe_draw.c
+++ b/src/gallium/drivers/svga/svga_pipe_draw.c
@@ -201,6 +201,17 @@ svga_release_user_upl_buffers(struct svga_context *svga)
      if (vb->buffer && svga_buffer_is_user_buffer(vb->buffer)) {
         struct svga_buffer *buffer = svga_buffer(vb->buffer);

+         /* The buffer_offset is relative to the uploaded buffer.
+          * Since we're discarding that buffer we need to reset this offset
+          * so it's not inadvertantly applied to a subsequent draw.
+          *
+          * XXX a root problem here is that the svga->curr.vb[] information
+          * is getting set both by gallium API calls and by code in
+          * svga_upload_user_buffers().  We should instead have two copies
+          * of the vertex buffer information and choose between as needed.
+          */
+         vb->buffer_offset = 0;
+
         buffer->uploaded.start = ~0;
         buffer->uploaded.end = 0;
         if (buffer->uploaded.buffer)
--- a/src/gallium/drivers/svga/svga_pipe_sampler.c
+++ b/src/gallium/drivers/svga/svga_pipe_sampler.c
@@ -125,8 +125,8 @@ svga_create_sampler_state(struct pipe_context *pipe,
    *    - min/max LOD clamping
    */
   cso->min_lod = 0;
-   cso->view_min_lod = MAX2(sampler->min_lod, 0);
-   cso->view_max_lod = MAX2(sampler->max_lod, 0);
+   cso->view_min_lod = MAX2((int) (sampler->min_lod + 0.5), 0);
+   cso->view_max_lod = MAX2((int) (sampler->max_lod + 0.5), 0);

   /* Use min_mipmap */
   if (svga->debug.use_min_mipmap) {
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -120,7 +120,7 @@ svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
      return result.u;

   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
-      return 16.0;
+      return 15.0;

   default:
      return 0;
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -82,12 +82,14 @@ update_tss_binding(struct svga_context *svga,
      const struct svga_sampler_state *s = svga->curr.sampler[i];
      struct svga_hw_view_state *view = &svga->state.hw_draw.views[i];
      struct pipe_resource *texture = NULL;
+      struct pipe_sampler_view *sv = svga->curr.sampler_views[i];

      /* get min max lod */
-      if (svga->curr.sampler_views[i]) {
-         min_lod = MAX2(s->view_min_lod, 0);
-         max_lod = MIN2(s->view_max_lod, svga->curr.sampler_views[i]->texture->last_level);
-         texture = svga->curr.sampler_views[i]->texture;
+      if (sv) {
+         min_lod = MAX2(0, (s->view_min_lod + sv->u.tex.first_level));
+         max_lod = MIN2(s->view_max_lod, sv->texture->last_level);
+         max_lod += sv->u.tex.first_level;
+         texture = sv->texture;
      } else {
         min_lod = 0;
         max_lod = 0;
--- a/src/gallium/drivers/svga/svga_surface.c
+++ b/src/gallium/drivers/svga/svga_surface.c
@@ -320,6 +320,11 @@ svga_mark_surface_dirty(struct pipe_surface *surf)
      else {
         /* this will happen later in svga_propagate_surface */
      }
+
+      /* Increment the view_age and texture age for this surface's slice
+       * so that any sampler views into the texture are re-validated too.
+       */
+      tex->view_age[surf->u.tex.first_layer] = ++(tex->age);
   }
 }

--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -2994,6 +2994,11 @@ needs_to_create_zero( struct svga_shader_emitter *emit )
             emit->key.fkey.tex[i].swizzle_a > PIPE_SWIZZLE_ALPHA)
            return TRUE;
      }
+
+      for (i = 0; i < emit->key.fkey.num_textures; i++) {
+         if (emit->key.fkey.tex[i].compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
+            return TRUE;
+      }
   }

   if (emit->unit == PIPE_SHADER_VERTEX) {
@@ -3017,11 +3022,6 @@ needs_to_create_zero( struct svga_shader_emitter *emit )
       emit->info.opcode_count[TGSI_OPCODE_KILP] >= 1)
      return TRUE;

-   for (i = 0; i < emit->key.fkey.num_textures; i++) {
-      if (emit->key.fkey.tex[i].compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
-         return TRUE;
-   }
-
   return FALSE;
 }

--- a/src/gallium/state_trackers/egl/x11/native_ximage.c
+++ b/src/gallium/state_trackers/egl/x11/native_ximage.c
@@ -455,7 +455,7 @@ ximage_display_copy_to_pixmap(struct native_display *ndpy,
   if (src->bind & PIPE_BIND_DISPLAY_TARGET) {
      struct ximage_display *xdpy = ximage_display(ndpy);
      enum pipe_format fmt = get_pixmap_format(&xdpy->base, pix);
-      const struct ximage_config *xconf;
+      const struct ximage_config *xconf = NULL;
      struct xlib_drawable xdraw;
      int i;

--- a/src/gallium/state_trackers/vega/vg_translate.c
+++ b/src/gallium/state_trackers/vega/vg_translate.c
@@ -526,8 +526,8 @@ void _vega_unpack_float_span_rgba(struct vg_context *ctx,
      src += offset;
      for (i = 0; i < n; ++i) {
         VGfloat clr[4];
-         clr[0] = ((*src >> 10) & 31)/31.;
-         clr[1] = ((*src >>  5) & 95)/95.;
+         clr[0] = ((*src >> 11) & 31)/31.;
+         clr[1] = ((*src >>  5) & 63)/63.;
         clr[2] = ((*src >>  0) & 31)/31.;
         clr[3] = 1.f;

--- a/src/gallium/targets/Makefile.xorg
+++ b/src/gallium/targets/Makefile.xorg
@@ -46,7 +46,7 @@ endif
 default: depend $(TOP)/$(LIB_DIR)/gallium $(LIBNAME) $(LIBNAME_STAGING)

 $(LIBNAME): $(OBJECTS) Makefile ../Makefile.xorg $(LIBS) $(DRIVER_PIPES) $(GALLIUM_AUXILIARIES)
-	$(MKLIB) -linker '$(LD)' -noprefix -o $@ $(LDFLAGS) $(OBJECTS) $(DRIVER_PIPES) $(GALLIUM_AUXILIARIES) $(DRIVER_LINKS)
+	$(MKLIB) -linker '$(LD)' -noprefix -o $@ -ldflags '$(LDFLAGS)' $(OBJECTS) $(DRIVER_PIPES) $(GALLIUM_AUXILIARIES) $(DRIVER_LINKS)

 depend: $(C_SOURCES) $(CPP_SOURCES) $(ASM_SOURCES) $(SYMLINKS) $(GENERATED_SOURCES)
 	rm -f depend
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -198,9 +198,10 @@ int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
    unsigned hash = bo->handle & (sizeof(csc->is_handle_added)-1);

    if (csc->is_handle_added[hash]) {
-        reloc = csc->relocs_hashlist[hash];
+        i = csc->reloc_indices_hashlist[hash];
+        reloc = &csc->relocs[i];
        if (reloc->handle == bo->handle) {
-            return csc->reloc_indices_hashlist[hash];
+            return i;
        }

        /* Hash collision, look for the BO in the list of relocs linearly. */
@@ -217,7 +218,6 @@ int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
                 *         AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
                 * will collide here: ^ and here:   ^,
                 * meaning that we should get very few collisions in the end. */
-                csc->relocs_hashlist[hash] = reloc;
                csc->reloc_indices_hashlist[hash] = i;
                /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
                return i;
@@ -241,10 +241,11 @@ static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
    enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;

    if (csc->is_handle_added[hash]) {
-        reloc = csc->relocs_hashlist[hash];
+        i = csc->reloc_indices_hashlist[hash];
+        reloc = &csc->relocs[i];
        if (reloc->handle == bo->handle) {
            update_reloc_domains(reloc, rd, wd, added_domains);
-            return csc->reloc_indices_hashlist[hash];
+            return i;
        }

        /* Hash collision, look for the BO in the list of relocs linearly. */
@@ -254,7 +255,6 @@ static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
            if (reloc->handle == bo->handle) {
                update_reloc_domains(reloc, rd, wd, added_domains);

-                csc->relocs_hashlist[hash] = reloc;
                csc->reloc_indices_hashlist[hash] = i;
                /*printf("write_reloc collision, hash: %i, handle: %i\n", hash, bo->handle);*/
                return i;
@@ -287,7 +287,6 @@ static unsigned radeon_add_reloc(struct radeon_cs_context *csc,
    reloc->flags = 0;

    csc->is_handle_added[hash] = TRUE;
-    csc->relocs_hashlist[hash] = reloc;
    csc->reloc_indices_hashlist[hash] = csc->crelocs;

    csc->chunks[1].length_dw += RELOC_DWORDS;
@@ -472,7 +471,6 @@ static void radeon_drm_cs_destroy(struct radeon_winsys_cs *rcs)
        pipe_semaphore_signal(&cs->flush_queued);
        pipe_semaphore_wait(&cs->flush_completed);
        pipe_thread_wait(cs->thread);
-        pipe_thread_destroy(cs->thread);
    }
    pipe_semaphore_destroy(&cs->flush_queued);
    pipe_semaphore_destroy(&cs->flush_completed);
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -48,7 +48,6 @@ struct radeon_cs_context {

    /* 0 = BO not added, 1 = BO added */
    char                        is_handle_added[256];
-    struct drm_radeon_cs_reloc  *relocs_hashlist[256];
    unsigned                    reloc_indices_hashlist[256];

    unsigned used_vram;
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -3735,13 +3735,10 @@ ast_case_label::hir(exec_list *instructions,
      instructions->push_tail(set_fallthru_on_test);
   } else { /* default case */
      if (state->switch_state.previous_default) {
-	 printf("a\n");
 	 YYLTYPE loc = this->get_location();
 	 _mesa_glsl_error(& loc, state,
 			  "multiple default labels in one switch");

-	 printf("b\n");
-
 	 loc = state->switch_state.previous_default->get_location();
 	 _mesa_glsl_error(& loc, state,
 			  "this is the first default label");
--- a/src/glsl/builtins/ir/acos.ir
+++ b/src/glsl/builtins/ir/acos.ir
@@ -2,21 +2,21 @@
   (signature float
     (parameters
       (declare (in) float x))
-     ((return (expression float - (constant float (1.5707963))
+     ((return (expression float - (constant float (1.5707964))
                                  (call asin ((var_ref x)))))))
   (signature vec2
     (parameters
       (declare (in) vec2 x))
-     ((return (expression vec2 - (constant float (1.5707963))
+     ((return (expression vec2 - (constant float (1.5707964))
                                 (call asin ((var_ref x)))))))
   (signature vec3
     (parameters
       (declare (in) vec3 x))
-     ((return (expression vec3 - (constant float (1.5707963))
+     ((return (expression vec3 - (constant float (1.5707964))
                                 (call asin ((var_ref x)))))))
   (signature vec4
     (parameters
       (declare (in) vec4 x))
-     ((return (expression vec4 - (constant float (1.5707963))
+     ((return (expression vec4 - (constant float (1.5707964))
                                 (call asin ((var_ref x)))))))
 ))
--- a/src/glsl/builtins/tools/texture_builtins.py
+++ b/src/glsl/builtins/tools/texture_builtins.py
@@ -54,7 +54,7 @@ def get_txs_dim(sampler_type):
 def generate_sigs(g, tex_inst, sampler_type, variant = 0, unused_fields = 0):
    coord_dim = get_coord_dim(sampler_type)
    extra_dim = get_extra_dim(sampler_type, variant & Proj, unused_fields)
-    offset_dim = get_sampler_dim(sampler_type)
+    sampler_dim = get_sampler_dim(sampler_type)

    if variant & Single:
        return_type = "float"
@@ -74,12 +74,12 @@ def generate_sigs(g, tex_inst, sampler_type, variant = 0, unused_fields = 0):
    elif tex_inst == "txf" or tex_inst == "txs":
        print "\n       (declare (in) int lod)",
    elif tex_inst == "txd":
-        grad_type = vec_type("", coord_dim)
+        grad_type = vec_type("", sampler_dim)
        print "\n       (declare (in) " + grad_type + " dPdx)",
        print "\n       (declare (in) " + grad_type + " dPdy)",

    if variant & Offset:
-        print "\n       (declare (const_in) " + vec_type("i", offset_dim) + " offset)",
+        print "\n       (declare (const_in) " + vec_type("i", sampler_dim) + " offset)",
    if tex_inst == "txb":
        print "\n       (declare (in) float bias)",

--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -292,7 +292,7 @@ pragma_statement:
 	| PRAGMA_OPTIMIZE_OFF EOL
 	| PRAGMA_INVARIANT_ALL EOL
 	{
-	   if (state->language_version < 120) {
+	   if (state->language_version == 110) {
 	      _mesa_glsl_warning(& @1, state,
 				 "pragma `invariant(all)' not supported in %s",
 				 state->version_string);
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1158,7 +1158,6 @@ public:
   {
      this->ir_type = ir_type_loop_jump;
      this->mode = mode;
-      this->loop = loop;
   }

   virtual ir_loop_jump *clone(void *mem_ctx, struct hash_table *) const;
@@ -1182,9 +1181,6 @@ public:

   /** Mode selector for the jump instruction. */
   enum jump_mode mode;
-private:
-   /** Loop containing this break instruction. */
-   ir_loop *loop;
 };

 /**
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cpp
@@ -275,7 +275,7 @@ private:
 	 const gl_texture_index target = base_type->sampler_index();
 	 const unsigned shadow = base_type->sampler_shadow;
 	 for (unsigned i = this->uniforms[id].sampler
-		 ; i < this->next_sampler
+		 ; i < MIN2(this->next_sampler, MAX_SAMPLERS)
 		 ; i++) {
 	    this->targets[i] = target;
 	    this->shader_samplers_used |= 1U << i;
--- a/src/glsl/loop_analysis.cpp
+++ b/src/glsl/loop_analysis.cpp
@@ -110,6 +110,8 @@ public:
   virtual ir_visitor_status visit(ir_loop_jump *);
   virtual ir_visitor_status visit(ir_dereference_variable *);

+   virtual ir_visitor_status visit_enter(ir_call *);
+
   virtual ir_visitor_status visit_enter(ir_loop *);
   virtual ir_visitor_status visit_leave(ir_loop *);
   virtual ir_visitor_status visit_enter(ir_assignment *);
@@ -152,6 +154,21 @@ loop_analysis::visit(ir_loop_jump *ir)
 }


+ir_visitor_status
+loop_analysis::visit_enter(ir_call *ir)
+{
+   /* If we're not somewhere inside a loop, there's nothing to do. */
+   if (this->state.is_empty())
+      return visit_continue;
+
+   loop_variable_state *const ls =
+      (loop_variable_state *) this->state.get_head();
+
+   ls->contains_calls = true;
+   return visit_continue_with_parent;
+}
+
+
 ir_visitor_status
 loop_analysis::visit(ir_dereference_variable *ir)
 {
@@ -209,6 +226,17 @@ loop_analysis::visit_leave(ir_loop *ir)
   loop_variable_state *const ls =
      (loop_variable_state *) this->state.pop_head();

+   /* Function calls may contain side effects.  These could alter any of our
+    * variables in ways that cannot be known, and may even terminate shader
+    * execution (say, calling discard in the fragment shader).  So we can't
+    * rely on any of our analysis about assignments to variables.
+    *
+    * We could perform some conservative analysis (prove there's no statically
+    * possible assignment, etc.) but it isn't worth it for now; function
+    * inlining will allow us to unroll loops anyway.
+    */
+   if (ls->contains_calls)
+      return visit_continue;

   foreach_list(node, &ir->body_instructions) {
      /* Skip over declarations at the start of a loop.
--- a/src/glsl/loop_analysis.h
+++ b/src/glsl/loop_analysis.h
@@ -122,10 +122,16 @@ public:
    */
   unsigned num_loop_jumps;

+   /**
+    * Whether this loop contains any function calls.
+    */
+   bool contains_calls;
+
   loop_variable_state()
   {
      this->max_iterations = -1;
      this->num_loop_jumps = 0;
+      this->contains_calls = false;
      this->var_hash = hash_table_ctor(0, hash_table_pointer_hash,
 				       hash_table_pointer_compare);
   }
@@ -134,6 +140,23 @@ public:
   {
      hash_table_dtor(this->var_hash);
   }
+
+   static void* operator new(size_t size, void *ctx)
+   {
+      void *lvs = ralloc_size(ctx, size);
+      assert(lvs != NULL);
+
+      ralloc_set_destructor(lvs, (void (*)(void*)) destructor);
+
+      return lvs;
+   }
+
+private:
+   static void
+   destructor(loop_variable_state *lvs)
+   {
+      lvs->~loop_variable_state();
+   }
 };


--- a/src/glsl/ralloc.c
+++ b/src/glsl/ralloc.c
@@ -278,7 +278,7 @@ ralloc_parent(const void *ptr)
      return NULL;

   info = get_header(ptr);
-   return PTR_FROM_HEADER(info->parent);
+   return info->parent ? PTR_FROM_HEADER(info->parent) : NULL;
 }

 static void *autofree_context = NULL;
--- a/src/glu/sgi/libnurbs/internals/mapdesc.cc
+++ b/src/glu/sgi/libnurbs/internals/mapdesc.cc
@@ -90,7 +90,7 @@ Mapdesc::setBboxsize( INREAL *mat )
 void
 Mapdesc::identify( REAL dest[MAXCOORDS][MAXCOORDS] )
 {
-    memset( dest, 0, sizeof( dest ) );
+    memset( dest, 0, sizeof( REAL ) * MAXCOORDS * MAXCOORDS );
    for( int i=0; i != hcoords; i++ )
 	dest[i][i] = 1.0;
 }
--- a/src/glu/sgi/libnurbs/internals/nurbstess.cc
+++ b/src/glu/sgi/libnurbs/internals/nurbstess.cc
@@ -505,7 +505,7 @@ NurbsTessellator::do_pwlcurve( O_pwlcurve *o_pwlcurve )
 	o_pwlcurve->owner = currentCurve;
    }

-    if( (inCurve == 2) ) 
+    if( inCurve == 2 ) 
 	endcurve();
 }

--- a/src/glx/apple/apple_visual.c
+++ b/src/glx/apple/apple_visual.c
@@ -116,7 +116,7 @@ apple_visual_create_pfobj(CGLPixelFormatObj * pfobj, const struct glx_config * m
      *uses_stereo = false;
   }

-   if (mode->doubleBufferMode) {
+   if (!offscreen && mode->doubleBufferMode) {
      attr[numattr++] = kCGLPFADoubleBuffer;
      *double_buffered = true;
   }
--- a/src/glx/glxext.c
+++ b/src/glx/glxext.c
@@ -293,6 +293,9 @@ QueryVersion(Display * dpy, int opcode, int *major, int *minor)
                                                                       GLX_MINOR_VERSION),
                                                                      NULL);

+   if (!reply)
+     return GL_FALSE;
+
   if (reply->major_version != GLX_MAJOR_VERSION) {
      free(reply);
      return GL_FALSE;
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -315,6 +315,10 @@ struct gl_meta_state
   struct drawtex_state DrawTex;  /**< For _mesa_meta_DrawTex() */
 };

+static void meta_glsl_blit_cleanup(struct gl_context *ctx, struct blit_state *blit);
+static void cleanup_temp_texture(struct gl_context *ctx, struct temp_texture *tex);
+static void meta_glsl_clear_cleanup(struct gl_context *ctx, struct clear_state *clear);
+
 static GLuint
 compile_shader_with_debug(struct gl_context *ctx, GLenum target, const GLcharARB *source)
 {
@@ -331,12 +335,16 @@ compile_shader_with_debug(struct gl_context *ctx, GLenum target, const GLcharARB
      return shader;

   _mesa_GetShaderiv(shader, GL_INFO_LOG_LENGTH, &size);
-   if (size == 0)
+   if (size == 0) {
+      _mesa_DeleteObjectARB(shader);
      return 0;
+   }

   info = malloc(size);
-   if (!info)
+   if (!info) {
+      _mesa_DeleteObjectARB(shader);
      return 0;
+   }

   _mesa_GetProgramInfoLog(shader, size, NULL, info);
   _mesa_problem(ctx,
@@ -345,6 +353,7 @@ compile_shader_with_debug(struct gl_context *ctx, GLenum target, const GLcharARB
 		 info, source);

   free(info);
+   _mesa_DeleteObjectARB(shader);

   return 0;
 }
@@ -397,10 +406,15 @@ _mesa_meta_init(struct gl_context *ctx)
 void
 _mesa_meta_free(struct gl_context *ctx)
 {
-   /* Note: Any textures, VBOs, etc, that we allocate should get
-    * freed by the normal context destruction code.  But this would be
-    * the place to free other meta data someday.
-    */
+   GET_CURRENT_CONTEXT(old_context);
+   _mesa_make_current(ctx, NULL, NULL);
+   meta_glsl_blit_cleanup(ctx, &ctx->Meta->Blit);
+   meta_glsl_clear_cleanup(ctx, &ctx->Meta->Clear);
+   cleanup_temp_texture(ctx, &ctx->Meta->TempTex);
+   if (old_context)
+      _mesa_make_current(old_context, old_context->WinSysDrawBuffer, old_context->WinSysReadBuffer);
+   else
+      _mesa_make_current(NULL, NULL, NULL);
   free(ctx->Meta);
   ctx->Meta = NULL;
 }
@@ -1056,6 +1070,15 @@ init_temp_texture(struct gl_context *ctx, struct temp_texture *tex)
   _mesa_GenTextures(1, &tex->TexObj);
 }

+static void
+cleanup_temp_texture(struct gl_context *ctx, struct temp_texture *tex)
+{
+   if (!tex->TexObj)
+     return;
+   _mesa_DeleteTextures(1, &tex->TexObj);
+   tex->TexObj = 0;
+}
+

 /**
 * Return pointer to temp_texture info for non-bitmap ops.
@@ -1592,6 +1615,21 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
   }
 }

+static void
+meta_glsl_blit_cleanup(struct gl_context *ctx, struct blit_state *blit)
+{
+   if (blit->ArrayObj) {
+      _mesa_DeleteVertexArraysAPPLE(1, &blit->ArrayObj);
+      blit->ArrayObj = 0;
+      _mesa_DeleteBuffersARB(1, &blit->VBO);
+      blit->VBO = 0;
+   }
+   if (blit->DepthFP) {
+      _mesa_DeletePrograms(1, &blit->DepthFP);
+      blit->DepthFP = 0;
+   }
+}
+

 /**
 * Meta implementation of ctx->Driver.Clear() in terms of polygon rendering.
@@ -1774,7 +1812,9 @@ meta_glsl_clear_init(struct gl_context *ctx, struct clear_state *clear)

   clear->ShaderProg = _mesa_CreateProgramObjectARB();
   _mesa_AttachShader(clear->ShaderProg, fs);
+   _mesa_DeleteObjectARB(fs);
   _mesa_AttachShader(clear->ShaderProg, vs);
+   _mesa_DeleteObjectARB(vs);
   _mesa_BindAttribLocationARB(clear->ShaderProg, 0, "position");
   _mesa_LinkProgramARB(clear->ShaderProg);

@@ -1787,7 +1827,9 @@ meta_glsl_clear_init(struct gl_context *ctx, struct clear_state *clear)

      clear->IntegerShaderProg = _mesa_CreateProgramObjectARB();
      _mesa_AttachShader(clear->IntegerShaderProg, fs);
+      _mesa_DeleteObjectARB(fs);
      _mesa_AttachShader(clear->IntegerShaderProg, vs);
+      _mesa_DeleteObjectARB(vs);
      _mesa_BindAttribLocationARB(clear->IntegerShaderProg, 0, "position");

      /* Note that user-defined out attributes get automatically assigned
@@ -1802,6 +1844,24 @@ meta_glsl_clear_init(struct gl_context *ctx, struct clear_state *clear)
   }
 }

+static void
+meta_glsl_clear_cleanup(struct gl_context *ctx, struct clear_state *clear)
+{
+   if (clear->ArrayObj == 0)
+      return;
+   _mesa_DeleteVertexArraysAPPLE(1, &clear->ArrayObj);
+   clear->ArrayObj = 0;
+   _mesa_DeleteBuffersARB(1, &clear->VBO);
+   clear->VBO = 0;
+   _mesa_DeleteObjectARB(clear->ShaderProg);
+   clear->ShaderProg = 0;
+
+   if (clear->IntegerShaderProg) {
+      _mesa_DeleteObjectARB(clear->IntegerShaderProg);
+      clear->IntegerShaderProg = 0;
+   }
+}
+
 /**
 * Meta implementation of ctx->Driver.Clear() in terms of polygon rendering.
 */
@@ -2193,8 +2253,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
    * Determine if we can do the glDrawPixels with texture mapping.
    */
   fallback = GL_FALSE;
-   if (ctx->_ImageTransferState ||
-       ctx->Fog.Enabled) {
+   if (ctx->Fog.Enabled) {
      fallback = GL_TRUE;
   }

@@ -2229,6 +2288,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
         texIntFormat = GL_ALPHA;
         metaExtraSave = (MESA_META_COLOR_MASK |
                          MESA_META_DEPTH_TEST |
+                          MESA_META_PIXEL_TRANSFER |
                          MESA_META_SHADER |
                          MESA_META_STENCIL_TEST);
      }
@@ -3256,6 +3316,7 @@ decompress_texture_image(struct gl_context *ctx,
   };
   struct vertex verts[4];
   GLuint fboDrawSave, fboReadSave;
+   GLuint rbSave;

   if (slice > 0) {
      assert(target == GL_TEXTURE_3D ||
@@ -3272,6 +3333,7 @@ decompress_texture_image(struct gl_context *ctx,
   /* save fbo bindings (not saved by _mesa_meta_begin()) */
   fboDrawSave = ctx->DrawBuffer->Name;
   fboReadSave = ctx->ReadBuffer->Name;
+   rbSave = ctx->CurrentRenderbuffer ? ctx->CurrentRenderbuffer->Name : 0;

   _mesa_meta_begin(ctx, MESA_META_ALL & ~MESA_META_PIXEL_STORE);

@@ -3292,6 +3354,7 @@ decompress_texture_image(struct gl_context *ctx,

   /* alloc dest surface */
   if (width > decompress->Width || height > decompress->Height) {
+      _mesa_BindRenderbufferEXT(GL_RENDERBUFFER_EXT, decompress->RBO);
      _mesa_RenderbufferStorageEXT(GL_RENDERBUFFER_EXT, GL_RGBA,
                                   width, height);
      decompress->Width = width;
@@ -3424,6 +3487,7 @@ decompress_texture_image(struct gl_context *ctx,
      _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER_EXT, fboDrawSave);
      _mesa_BindFramebufferEXT(GL_READ_FRAMEBUFFER_EXT, fboReadSave);
   }
+   _mesa_BindRenderbufferEXT(GL_RENDERBUFFER_EXT, rbSave);
 }


--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -173,12 +173,6 @@ dri2CreateContextAttribs(__DRIscreen *screen, int api,
 	return NULL;
    }

-    if (mesa_api != API_OPENGL && num_attribs != 0) {
-	*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
-	assert(!"Should not get here.");
-	return NULL;
-    }
-
    for (unsigned i = 0; i < num_attribs; i++) {
 	switch (attribs[i * 2]) {
 	case __DRI_CTX_ATTRIB_MAJOR_VERSION:
@@ -200,6 +194,23 @@ dri2CreateContextAttribs(__DRIscreen *screen, int api,
 	}
    }

+    /* The EGL_KHR_create_context spec says:
+     *
+     *     "Flags are only defined for OpenGL context creation, and specifying
+     *     a flags value other than zero for other types of contexts,
+     *     including OpenGL ES contexts, will generate an error."
+     *
+     * The GLX_EXT_create_context_es2_profile specification doesn't say
+     * anything specific about this case.  However, none of the known flags
+     * have any meaning in an ES context, so this seems safe.
+     */
+    if (mesa_api != __DRI_API_OPENGL
+        && mesa_api != __DRI_API_OPENGL_CORE
+        && flags != 0) {
+	*error = __DRI_CTX_ERROR_BAD_FLAG;
+	return NULL;
+    }
+
    /* There are no forward-compatible contexts before OpenGL 3.0.  The
     * GLX_ARB_create_context spec says:
     *
@@ -221,7 +232,7 @@ dri2CreateContextAttribs(__DRIscreen *screen, int api,
 	return NULL;
    }

-    context = malloc(sizeof *context);
+    context = calloc(1, sizeof *context);
    if (!context) {
 	*error = __DRI_CTX_ERROR_NO_MEMORY;
 	return NULL;
--- a/src/mesa/drivers/dri/common/xmlconfig.c
+++ b/src/mesa/drivers/dri/common/xmlconfig.c
@@ -86,7 +86,7 @@ static const char *__getProgramName () {
 #endif

 #if !defined(GET_PROGRAM_NAME)
-#    if defined(__OpenBSD__) || defined(NetBSD) || defined(__UCLIBC__)
+#    if defined(__OpenBSD__) || defined(NetBSD) || defined(__UCLIBC__) || defined(ANDROID)
 /* This is a hack. It's said to work on OpenBSD, NetBSD and GNU.
 * Rogelio M.Serrano Jr. reported it's also working with UCLIBC. It's
 * used as a last resort, if there is no documented facility available. */
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -30,6 +30,7 @@
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
+#include "main/fbobject.h"
 #include "main/dd.h"
 #include "main/state.h"

@@ -545,7 +546,7 @@ i830Scissor(struct gl_context * ctx, GLint x, GLint y, GLsizei w, GLsizei h)

   DBG("%s %d,%d %dx%d\n", __FUNCTION__, x, y, w, h);

-   if (ctx->DrawBuffer->Name == 0) {
+   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      x1 = x;
      y1 = ctx->DrawBuffer->Height - (y + h);
      x2 = x + w - 1;
@@ -861,7 +862,7 @@ i830Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
         if (ctx->DrawBuffer) {
            struct intel_renderbuffer *irbStencil
               = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
-            hw_stencil = (irbStencil && irbStencil->mt->region);
+            hw_stencil = (irbStencil && irbStencil->mt);
         }
         if (hw_stencil) {
            I830_STATECHANGE(i830, I830_UPLOAD_CTX);
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -128,7 +128,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
   GLubyte border[4];
   GLuint dst_x, dst_y;

-   memset(state, 0, sizeof(state));
+   memset(state, 0, sizeof(*state));

   /*We need to refcount these. */

--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -30,6 +30,7 @@
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
+#include "main/fbobject.h"
 #include "main/dd.h"
 #include "main/state.h"
 #include "tnl/tnl.h"
@@ -400,7 +401,7 @@ intelCalcViewport(struct gl_context * ctx)
 {
   struct intel_context *intel = intel_context(ctx);

-   if (ctx->DrawBuffer->Name == 0) {
+   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      _math_matrix_viewport(&intel->ViewportMatrix,
 			    ctx->Viewport.X,
 			    ctx->DrawBuffer->Height - ctx->Viewport.Y,
@@ -518,7 +519,7 @@ i915Scissor(struct gl_context * ctx, GLint x, GLint y, GLsizei w, GLsizei h)

   DBG("%s %d,%d %dx%d\n", __FUNCTION__, x, y, w, h);

-   if (ctx->DrawBuffer->Name == 0) {
+   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      x1 = x;
      y1 = ctx->DrawBuffer->Height - (y + h);
      x2 = x + w - 1;
@@ -577,7 +578,7 @@ i915CullFaceFrontFace(struct gl_context * ctx, GLenum unused)
   else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
      mode = S4_CULLMODE_CW;

-      if (ctx->DrawBuffer && ctx->DrawBuffer->Name != 0)
+      if (ctx->DrawBuffer && _mesa_is_user_fbo(ctx->DrawBuffer))
         mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
      if (ctx->Polygon.CullFaceMode == GL_FRONT)
         mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -240,7 +240,7 @@ brwCreateContext(int api,
   /* WM maximum threads is number of EUs times number of threads per EU. */
   if (intel->gen >= 7) {
      if (intel->gt == 1) {
-	 brw->max_wm_threads = 86;
+	 brw->max_wm_threads = 48;
 	 brw->max_vs_threads = 36;
 	 brw->max_gs_threads = 36;
 	 brw->urb.size = 128;
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -692,6 +692,16 @@ static void brw_emit_vertices(struct brw_context *brw)
      uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
      uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;

+      /* The gen4 driver expects edgeflag to come in as a float, and passes
+       * that float on to the tests in the clipper.  Mesa's current vertex
+       * attribute value for EdgeFlag is stored as a float, which works out.
+       * glEdgeFlagPointer, on the other hand, gives us an unnormalized
+       * integer ubyte.  Just rewrite that to convert to a float.
+       */
+      if (input->attrib == VERT_ATTRIB_EDGEFLAG &&
+          format == BRW_SURFACEFORMAT_R8_UINT)
+         format = BRW_SURFACEFORMAT_R8_SSCALED;
+
      switch (input->glarray->Size) {
      case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
      case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -47,13 +47,13 @@ brw_swap_cmod(uint32_t cmod)
   case BRW_CONDITIONAL_NZ:
      return cmod;
   case BRW_CONDITIONAL_G:
-      return BRW_CONDITIONAL_LE;
-   case BRW_CONDITIONAL_GE:
      return BRW_CONDITIONAL_L;
+   case BRW_CONDITIONAL_GE:
+      return BRW_CONDITIONAL_LE;
   case BRW_CONDITIONAL_L:
-      return BRW_CONDITIONAL_GE;
-   case BRW_CONDITIONAL_LE:
      return BRW_CONDITIONAL_G;
+   case BRW_CONDITIONAL_LE:
+      return BRW_CONDITIONAL_GE;
   default:
      return ~0;
   }
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -974,7 +974,6 @@ void brw_SAMPLE(struct brw_compile *p,
 void brw_math_16( struct brw_compile *p,
 		  struct brw_reg dest,
 		  GLuint function,
-		  GLuint saturate,
 		  GLuint msg_reg_nr,
 		  struct brw_reg src,
 		  GLuint precision );
@@ -982,7 +981,6 @@ void brw_math_16( struct brw_compile *p,
 void brw_math( struct brw_compile *p,
 	       struct brw_reg dest,
 	       GLuint function,
-	       GLuint saturate,
 	       GLuint msg_reg_nr,
 	       struct brw_reg src,
 	       GLuint data_type,
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -429,7 +429,6 @@ static void brw_set_math_message( struct brw_compile *p,
 				  GLuint function,
 				  GLuint integer_type,
 				  bool low_precision,
-				  bool saturate,
 				  GLuint dataType )
 {
   struct brw_context *brw = p->brw;
@@ -461,22 +460,24 @@ static void brw_set_math_message( struct brw_compile *p,
      break;
   }

+
   brw_set_message_descriptor(p, insn, BRW_SFID_MATH,
 			      msg_length, response_length, false, false);
   if (intel->gen == 5) {
      insn->bits3.math_gen5.function = function;
      insn->bits3.math_gen5.int_type = integer_type;
      insn->bits3.math_gen5.precision = low_precision;
-      insn->bits3.math_gen5.saturate = saturate;
+      insn->bits3.math_gen5.saturate = insn->header.saturate;
      insn->bits3.math_gen5.data_type = dataType;
      insn->bits3.math_gen5.snapshot = 0;
   } else {
      insn->bits3.math.function = function;
      insn->bits3.math.int_type = integer_type;
      insn->bits3.math.precision = low_precision;
-      insn->bits3.math.saturate = saturate;
+      insn->bits3.math.saturate = insn->header.saturate;
      insn->bits3.math.data_type = dataType;
   }
+   insn->header.saturate = 0;
 }


@@ -1567,7 +1568,6 @@ void brw_WAIT (struct brw_compile *p)
 void brw_math( struct brw_compile *p,
 	       struct brw_reg dest,
 	       GLuint function,
-	       GLuint saturate,
 	       GLuint msg_reg_nr,
 	       struct brw_reg src,
 	       GLuint data_type,
@@ -1603,7 +1603,6 @@ void brw_math( struct brw_compile *p,
       * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
       */
      insn->header.destreg__conditionalmod = function;
-      insn->header.saturate = saturate;

      brw_set_dest(p, insn, dest);
      brw_set_src0(p, insn, src);
@@ -1624,7 +1623,6 @@ void brw_math( struct brw_compile *p,
 			   function,
 			   src.type == BRW_REGISTER_TYPE_D,
 			   precision,
-			   saturate,
 			   data_type);
   }
 }
@@ -1689,7 +1687,6 @@ void brw_math2(struct brw_compile *p,
 void brw_math_16( struct brw_compile *p,
 		  struct brw_reg dest,
 		  GLuint function,
-		  GLuint saturate,
 		  GLuint msg_reg_nr,
 		  struct brw_reg src,
 		  GLuint precision )
@@ -1704,7 +1701,6 @@ void brw_math_16( struct brw_compile *p,
       * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
       */
      insn->header.destreg__conditionalmod = function;
-      insn->header.saturate = saturate;

      /* Source modifiers are ignored for extended math instructions. */
      assert(!src.negate);
@@ -1732,7 +1728,6 @@ void brw_math_16( struct brw_compile *p,
 			function,
 			BRW_MATH_INTEGER_UNSIGNED,
 			precision,
-			saturate,
 			BRW_MATH_DATA_VECTOR);

   /* Second instruction:
@@ -1748,7 +1743,6 @@ void brw_math_16( struct brw_compile *p,
 			function,
 			BRW_MATH_INTEGER_UNSIGNED,
 			precision,
-			saturate,
 			BRW_MATH_DATA_VECTOR);

   brw_pop_insn_state(p);
--- a/src/mesa/drivers/dri/i965/brw_eu_util.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_util.c
@@ -42,7 +42,6 @@ void brw_math_invert( struct brw_compile *p,
   brw_math( p, 
 	     dst,
 	     BRW_MATH_FUNCTION_INV, 
-	     BRW_MATH_SATURATE_NONE,
 	     0,
 	     src,
 	     BRW_MATH_PRECISION_FULL, 
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -35,6 +35,7 @@ extern "C" {
 #include "main/macros.h"
 #include "main/shaderobj.h"
 #include "main/uniforms.h"
+#include "main/fbobject.h"
 #include "program/prog_parameter.h"
 #include "program/prog_print.h"
 #include "program/register_allocate.h"
@@ -717,7 +718,7 @@ fs_visitor::calculate_urb_setup()
       *
       * See compile_sf_prog() for more info.
       */
-      if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
+      if (fp->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
         urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
   }

@@ -1595,6 +1596,9 @@ fs_visitor::compute_to_mrf()
      }
   }

+   if (progress)
+      live_intervals_valid = false;
+
   return progress;
 }

@@ -1671,6 +1675,9 @@ fs_visitor::remove_duplicate_mrf_writes()
      }
   }

+   if (progress)
+      live_intervals_valid = false;
+
   return progress;
 }

@@ -1877,6 +1884,13 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
   struct brw_context *brw = brw_context(ctx);
   struct brw_wm_prog_key key;

+   /* As a temporary measure we assume that all programs use dFdy() (and hence
+    * need to be compiled differently depending on whether we're rendering to
+    * an FBO).  FIXME: set this bool correctly based on the contents of the
+    * program.
+    */
+   bool program_uses_dfdy = true;
+
   if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
      return true;

@@ -1921,7 +1935,10 @@ brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)

   if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
      key.drawable_height = ctx->DrawBuffer->Height;
-      key.render_to_fbo = ctx->DrawBuffer->Name != 0;
+   }
+
+   if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
+      key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   }

   key.nr_color_regions = 1;
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -410,6 +410,7 @@ public:

      this->frag_depth = NULL;
      memset(this->outputs, 0, sizeof(this->outputs));
+      memset(this->output_components, 0, sizeof(this->output_components));
      this->first_non_payload_grf = 0;
      this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;

@@ -542,7 +543,8 @@ public:
 			   struct brw_reg src);
   void generate_discard(fs_inst *inst);
   void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
-   void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+                     bool negate_value);
   void generate_spill(fs_inst *inst, struct brw_reg src);
   void generate_unspill(fs_inst *inst, struct brw_reg dst);
   void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst);
@@ -617,6 +619,7 @@ public:
   struct hash_table *variable_ht;
   ir_variable *frag_depth;
   fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
+   unsigned output_components[BRW_MAX_DRAW_BUFFERS];
   int first_non_payload_grf;
   int max_grf;
   int urb_setup[FRAG_ATTRIB_MAX];
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -194,8 +194,6 @@ fs_visitor::generate_math1_gen7(fs_inst *inst,
   assert(inst->mlen == 0);
   brw_math(p, dst,
 	    brw_math_function(inst->opcode),
-	    inst->saturate ? BRW_MATH_SATURATE_SATURATE
-			   : BRW_MATH_SATURATE_NONE,
 	    0, src0,
 	    BRW_MATH_DATA_VECTOR,
 	    BRW_MATH_PRECISION_FULL);
@@ -223,8 +221,6 @@ fs_visitor::generate_math1_gen6(fs_inst *inst,
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_math(p, dst,
 	    op,
-	    inst->saturate ? BRW_MATH_SATURATE_SATURATE :
-	    BRW_MATH_SATURATE_NONE,
 	    0, src0,
 	    BRW_MATH_DATA_VECTOR,
 	    BRW_MATH_PRECISION_FULL);
@@ -233,8 +229,6 @@ fs_visitor::generate_math1_gen6(fs_inst *inst,
      brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
      brw_math(p, sechalf(dst),
 	       op,
-	       inst->saturate ? BRW_MATH_SATURATE_SATURATE :
-	       BRW_MATH_SATURATE_NONE,
 	       0, sechalf(src0),
 	       BRW_MATH_DATA_VECTOR,
 	       BRW_MATH_PRECISION_FULL);
@@ -274,8 +268,6 @@ fs_visitor::generate_math_gen4(fs_inst *inst,
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_math(p, dst,
 	    op,
-	    inst->saturate ? BRW_MATH_SATURATE_SATURATE :
-	    BRW_MATH_SATURATE_NONE,
 	    inst->base_mrf, src,
 	    BRW_MATH_DATA_VECTOR,
 	    BRW_MATH_PRECISION_FULL);
@@ -284,8 +276,6 @@ fs_visitor::generate_math_gen4(fs_inst *inst,
      brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
      brw_math(p, sechalf(dst),
 	       op,
-	       inst->saturate ? BRW_MATH_SATURATE_SATURATE :
-	       BRW_MATH_SATURATE_NONE,
 	       inst->base_mrf + 1, sechalf(src),
 	       BRW_MATH_DATA_VECTOR,
 	       BRW_MATH_PRECISION_FULL);
@@ -475,8 +465,13 @@ fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
   brw_ADD(p, dst, src0, negate(src1));
 }

+/* The negate_value boolean is used to negate the derivative computation for
+ * FBOs, since they place the origin at the upper left instead of the lower
+ * left.
+ */
 void
-fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
+fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+                         bool negate_value)
 {
   struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
 				 BRW_REGISTER_TYPE_F,
@@ -490,7 +485,10 @@ fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
 				 BRW_WIDTH_4,
 				 BRW_HORIZONTAL_STRIDE_0,
 				 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
-   brw_ADD(p, dst, src0, negate(src1));
+   if (negate_value)
+      brw_ADD(p, dst, src1, negate(src0));
+   else
+      brw_ADD(p, dst, src0, negate(src1));
 }

 void
@@ -913,7 +911,7 @@ fs_visitor::generate_code()
 	 generate_ddx(inst, dst, src[0]);
 	 break;
      case FS_OPCODE_DDY:
-	 generate_ddy(inst, dst, src[0]);
+	 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
 	 break;

      case FS_OPCODE_SPILL:
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -76,6 +76,7 @@ fs_visitor::visit(ir_variable *ir)
 	 /* Writing gl_FragColor outputs to all color regions. */
 	 for (int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
 	    this->outputs[i] = *reg;
+	    this->output_components[i] = 4;
 	 }
      } else if (ir->location == FRAG_RESULT_DEPTH) {
 	 this->frag_depth = ir;
@@ -84,11 +85,16 @@ fs_visitor::visit(ir_variable *ir)
 	 assert(ir->location >= FRAG_RESULT_DATA0 &&
 		ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);

+	 int vector_elements =
+	    ir->type->is_array() ? ir->type->fields.array->vector_elements
+				 : ir->type->vector_elements;
+
 	 /* General color output. */
 	 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
 	    int output = ir->location - FRAG_RESULT_DATA0 + i;
 	    this->outputs[output] = *reg;
-	    this->outputs[output].reg_offset += 4 * i;
+	    this->outputs[output].reg_offset += vector_elements * i;
+	    this->output_components[output] = vector_elements;
 	 }
      }
   } else if (ir->mode == ir_var_uniform) {
@@ -820,20 +826,36 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   const int vector_elements =
      ir->coordinate ? ir->coordinate->type->vector_elements : 0;

-   if (ir->offset) {
-      /* The offsets set up by the ir_texture visitor are in the
-       * m1 header, so we can't go headerless.
+   if (ir->offset != NULL && ir->op == ir_txf) {
+      /* It appears that the ld instruction used for txf does its
+       * address bounds check before adding in the offset.  To work
+       * around this, just add the integer offset to the integer texel
+       * coordinate, and don't put the offset in the header.
       */
-      header_present = true;
-      mlen++;
-      base_mrf--;
-   }
+      ir_constant *offset = ir->offset->as_constant();
+      for (int i = 0; i < vector_elements; i++) {
+	 emit(BRW_OPCODE_ADD,
+	      fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
+	      coordinate,
+	      offset->value.i[i]);
+	 coordinate.reg_offset++;
+      }
+   } else {
+      if (ir->offset) {
+	 /* The offsets set up by the ir_texture visitor are in the
+	  * m1 header, so we can't go headerless.
+	  */
+	 header_present = true;
+	 mlen++;
+	 base_mrf--;
+      }

-   for (int i = 0; i < vector_elements; i++) {
-      emit(BRW_OPCODE_MOV,
-	   fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
-	   coordinate);
-      coordinate.reg_offset++;
+      for (int i = 0; i < vector_elements; i++) {
+	 emit(BRW_OPCODE_MOV,
+	      fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
+	      coordinate);
+	 coordinate.reg_offset++;
+      }
   }
   mlen += vector_elements * reg_width;

@@ -2027,7 +2049,7 @@ fs_visitor::emit_fb_writes()
      this->current_annotation = ralloc_asprintf(this->mem_ctx,
 						 "FB write target %d",
 						 target);
-      for (int i = 0; i < 4; i++)
+      for (unsigned i = 0; i < this->output_components[target]; i++)
 	 emit_color_write(target, i, color_mrf);

      fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -40,6 +40,8 @@
 #include "brw_state.h"
 #include "brw_defines.h"

+#include "main/fbobject.h"
+
 /* Constant single cliprect for framebuffer object or DRI2 drawing */
 static void upload_drawing_rect(struct brw_context *brw)
 {
@@ -376,6 +378,26 @@ static void emit_depthbuffer(struct brw_context *brw)
      assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
      assert(!hiz_region || region->tiling == I915_TILING_Y);

+      /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+       * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
+       * Coordinate Offset X/Y":
+       *
+       *   "The 3 LSBs of both offsets must be zero to ensure correct
+       *   alignment"
+       *
+       * We have no guarantee that tile_x and tile_y are correctly aligned,
+       * since they are determined by the mipmap layout, which is only aligned
+       * to multiples of 4.
+       *
+       * So, to avoid hanging the GPU, just smash the low order 3 bits of
+       * tile_x and tile_y to 0.  This is a temporary workaround until we come
+       * up with a better solution.
+       */
+      if (intel->gen >= 6) {
+	 tile_x &= ~7;
+	 tile_y &= ~7;
+      }
+
      BEGIN_BATCH(len);
      OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
      OUT_BATCH(((region->pitch * region->cpp) - 1) |
@@ -506,7 +528,7 @@ static void upload_polygon_stipple(struct brw_context *brw)
    * to a FBO (i.e. any named frame buffer object), we *don't*
    * need to invert - we already match the layout.
    */
-   if (ctx->DrawBuffer->Name == 0) {
+   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      for (i = 0; i < 32; i++)
 	  OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
   }
@@ -549,15 +571,13 @@ static void upload_polygon_stipple_offset(struct brw_context *brw)

   /* _NEW_BUFFERS
    *
-    * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
-    * we have to invert the Y axis in order to match the OpenGL
-    * pixel coordinate system, and our offset must be matched
-    * to the window position.  If we're drawing to a FBO
-    * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
-    * system works just fine, and there's no window system to
-    * worry about.
+    * If we're drawing to a system window we have to invert the Y axis
+    * in order to match the OpenGL pixel coordinate system, and our
+    * offset must be matched to the window position.  If we're drawing
+    * to a user-created FBO then our native pixel coordinate system
+    * works just fine, and there's no window system to worry about.
    */
-   if (brw->intel.ctx.DrawBuffer->Name == 0)
+   if (_mesa_is_winsys_fbo(brw->intel.ctx.DrawBuffer))
      OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
   else
      OUT_BATCH(0);
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -32,7 +32,9 @@

 #include "main/glheader.h"
 #include "main/macros.h"
+#include "main/mtypes.h"
 #include "main/enums.h"
+#include "main/fbobject.h"

 #include "intel_batchbuffer.h"

@@ -136,7 +138,7 @@ brw_upload_sf_prog(struct brw_context *brw)
   struct gl_context *ctx = &brw->intel.ctx;
   struct brw_sf_prog_key key;
   /* _NEW_BUFFERS */
-   bool render_to_fbo = ctx->DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);

   memset(&key, 0, sizeof(key));

--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -314,7 +314,6 @@ static void invert_det( struct brw_sf_compile *c)
   brw_math(&c->func, 
 	    c->inv_det, 
 	    BRW_MATH_FUNCTION_INV,
-	    BRW_MATH_SATURATE_NONE,
 	    0, 
 	    c->det,
 	    BRW_MATH_DATA_SCALAR,
@@ -599,7 +598,6 @@ void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
 	 brw_math(&c->func,
 		  c->tmp,
 		  BRW_MATH_FUNCTION_INV,
-		  BRW_MATH_SATURATE_NONE,
 		  0,
 		  c->dx0,
 		  BRW_MATH_DATA_SCALAR,
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -31,10 +31,12 @@
   


+#include "main/mtypes.h"
+#include "main/macros.h"
+#include "main/fbobject.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
-#include "main/macros.h"
 #include "brw_sf.h"

 static void upload_sf_vp(struct brw_context *brw)
@@ -44,7 +46,7 @@ static void upload_sf_vp(struct brw_context *brw)
   const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
   struct brw_sf_viewport *sfv;
   GLfloat y_scale, y_bias;
-   const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   const GLfloat *v = ctx->Viewport._WindowMap.m;

   sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
@@ -142,7 +144,7 @@ static void upload_sf_unit( struct brw_context *brw )
   struct brw_sf_unit_state *sf;
   drm_intel_bo *bo = intel->batch.bo;
   int chipset_max_threads;
-   bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);

   sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
 			sizeof(*sf), 64, &brw->sf.state_offset);
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -262,7 +262,6 @@ vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
   brw_math(p,
 	    dst,
 	    brw_math_function(inst->opcode),
-	    BRW_MATH_SATURATE_NONE,
 	    inst->base_mrf,
 	    src,
 	    BRW_MATH_DATA_VECTOR,
@@ -291,7 +290,6 @@ vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
   brw_math(p,
 	    dst,
 	    brw_math_function(inst->opcode),
-	    BRW_MATH_SATURATE_NONE,
 	    inst->base_mrf,
 	    src,
 	    BRW_MATH_DATA_SCALAR,
@@ -355,7 +353,6 @@ vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
   brw_math(p,
 	    dst,
 	    brw_math_function(inst->opcode),
-	    BRW_MATH_SATURATE_NONE,
 	    inst->base_mrf,
 	    op0,
 	    BRW_MATH_DATA_VECTOR,
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1793,6 +1793,42 @@ vec4_visitor::visit(ir_texture *ir)
   /* Should be lowered by do_lower_texture_projection */
   assert(!ir->projector);

+   /* Generate code to compute all the subexpression trees.  This has to be
+    * done before loading any values into MRFs for the sampler message since
+    * generating these values may involve SEND messages that need the MRFs.
+    */
+   src_reg coordinate;
+   if (ir->coordinate) {
+      ir->coordinate->accept(this);
+      coordinate = this->result;
+   }
+
+   src_reg shadow_comparitor;
+   if (ir->shadow_comparitor) {
+      ir->shadow_comparitor->accept(this);
+      shadow_comparitor = this->result;
+   }
+
+   src_reg lod, dPdx, dPdy;
+   switch (ir->op) {
+   case ir_txf:
+   case ir_txl:
+   case ir_txs:
+      ir->lod_info.lod->accept(this);
+      lod = this->result;
+      break;
+   case ir_txd:
+      ir->lod_info.grad.dPdx->accept(this);
+      dPdx = this->result;
+
+      ir->lod_info.grad.dPdy->accept(this);
+      dPdy = this->result;
+      break;
+   case ir_tex:
+   case ir_txb:
+      break;
+   }
+
   vec4_instruction *inst = NULL;
   switch (ir->op) {
   case ir_tex:
@@ -1820,17 +1856,16 @@ vec4_visitor::visit(ir_texture *ir)
   inst->dst = dst_reg(this, ir->type);
   inst->shadow_compare = ir->shadow_comparitor != NULL;

-   if (ir->offset != NULL)
+   if (ir->offset != NULL && ir->op != ir_txf)
      inst->texture_offset = brw_texture_offset(ir->offset->as_constant());

   /* MRF for the first parameter */
   int param_base = inst->base_mrf + inst->header_present;

   if (ir->op == ir_txs) {
-      ir->lod_info.lod->accept(this);
      int writemask = intel->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
      emit(MOV(dst_reg(MRF, param_base, ir->lod_info.lod->type, writemask),
-	   this->result));
+	   lod));
   } else {
      int i, coord_mask = 0, zero_mask = 0;
      /* Load the coordinate */
@@ -1840,17 +1875,35 @@ vec4_visitor::visit(ir_texture *ir)
      for (; i < 4; i++)
 	 zero_mask |= (1 << i);

-      ir->coordinate->accept(this);
-      emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, coord_mask),
-	       this->result));
+      if (ir->offset && ir->op == ir_txf) {
+	 /* It appears that the ld instruction used for txf does its
+	  * address bounds check before adding in the offset.  To work
+	  * around this, just add the integer offset to the integer
+	  * texel coordinate, and don't put the offset in the header.
+	  */
+	 ir_constant *offset = ir->offset->as_constant();
+	 assert(offset);
+
+	 for (int j = 0; j < ir->coordinate->type->vector_elements; j++) {
+	    src_reg src = coordinate;
+	    src.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(src.swizzle, j),
+				       BRW_GET_SWZ(src.swizzle, j),
+				       BRW_GET_SWZ(src.swizzle, j),
+				       BRW_GET_SWZ(src.swizzle, j));
+	    emit(ADD(dst_reg(MRF, param_base, ir->coordinate->type, 1 << j),
+		     src, offset->value.i[j]));
+	 }
+      } else {
+	 emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, coord_mask),
+		  coordinate));
+      }
      emit(MOV(dst_reg(MRF, param_base, ir->coordinate->type, zero_mask),
 	       src_reg(0)));
      /* Load the shadow comparitor */
      if (ir->shadow_comparitor) {
-	 ir->shadow_comparitor->accept(this);
 	 emit(MOV(dst_reg(MRF, param_base + 1, ir->shadow_comparitor->type,
 			  WRITEMASK_X),
-		  this->result));
+		  shadow_comparitor));
 	 inst->mlen++;
      }

@@ -1870,21 +1923,13 @@ vec4_visitor::visit(ir_texture *ir)
 	    mrf = param_base;
 	    writemask = WRITEMASK_Z;
 	 }
-	 ir->lod_info.lod->accept(this);
-	 emit(MOV(dst_reg(MRF, mrf, ir->lod_info.lod->type, writemask),
-		  this->result));
+	 emit(MOV(dst_reg(MRF, mrf, ir->lod_info.lod->type, writemask), lod));
      } else if (ir->op == ir_txf) {
-	 ir->lod_info.lod->accept(this);
 	 emit(MOV(dst_reg(MRF, param_base, ir->lod_info.lod->type, WRITEMASK_W),
-		  this->result));
+		  lod));
      } else if (ir->op == ir_txd) {
 	 const glsl_type *type = ir->lod_info.grad.dPdx->type;

-	 ir->lod_info.grad.dPdx->accept(this);
-	 src_reg dPdx = this->result;
-	 ir->lod_info.grad.dPdy->accept(this);
-	 src_reg dPdy = this->result;
-
 	 if (intel->gen >= 5) {
 	    dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
 	    dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_constval.c
@@ -143,14 +143,12 @@ static void calc_sizes( struct tracker *t )
   /* Examine vertex program output sizes to set the size_masks[] info
    * which describes the fragment program input sizes.
    */
-   for (vertRes = VERT_RESULT_TEX0; vertRes < VERT_RESULT_MAX; vertRes++) {
+   for (vertRes = 0; vertRes < VERT_RESULT_MAX; vertRes++) {

      /* map vertex program output index to fragment program input index */
      GLint fragAttrib = _mesa_vert_result_to_frag_attrib(vertRes);
      if (fragAttrib < 0)
         continue;
-      assert(fragAttrib >= FRAG_ATTRIB_TEX0);
-      assert(fragAttrib <= FRAG_ATTRIB_MAX);

      switch (get_output_size(t, vertRes)) {
      case 4: t->size_masks[4-1] |= 1 << fragAttrib;
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -677,7 +677,6 @@ static void emit_math1_gen4(struct brw_vs_compile *c,
   brw_math(p, 
 	    tmp,
 	    function,
-	    BRW_MATH_SATURATE_NONE,
 	    2,
 	    arg0,
 	    BRW_MATH_DATA_SCALAR,
@@ -712,7 +711,6 @@ emit_math1_gen6(struct brw_vs_compile *c,
   brw_math(p,
 	    tmp_dst,
 	    function,
-	    BRW_MATH_SATURATE_NONE,
 	    2,
 	    tmp_src,
 	    BRW_MATH_DATA_SCALAR,
@@ -764,7 +762,6 @@ static void emit_math2_gen4( struct brw_vs_compile *c,
   brw_math(p, 
 	    tmp,
 	    function,
-	    BRW_MATH_SATURATE_NONE,
 	    2,
 	    arg0,
 	    BRW_MATH_DATA_SCALAR,
@@ -1753,7 +1750,7 @@ accumulator_contains(struct brw_vs_compile *c, struct brw_reg val)
   if (val.address_mode != BRW_ADDRESS_DIRECT)
      return false;

-   if (val.negate || val.abs)
+   if (val.negate || val.abs || val.dw1.bits.swizzle != BRW_SWIZZLE_XYZW)
      return false;

   switch (prev_insn->header.opcode) {
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -33,6 +33,7 @@
 #include "brw_wm.h"
 #include "brw_state.h"
 #include "main/formats.h"
+#include "main/fbobject.h"
 #include "main/samplerobj.h"
 #include "program/prog_parameter.h"

@@ -417,6 +418,13 @@ static void brw_wm_populate_key( struct brw_context *brw,
   GLuint line_aa;
   GLuint i;

+   /* As a temporary measure we assume that all programs use dFdy() (and hence
+    * need to be compiled differently depending on whether we're rendering to
+    * an FBO).  FIXME: set this bool correctly based on the contents of the
+    * program.
+    */
+   bool program_uses_dfdy = true;
+
   memset(key, 0, sizeof(*key));

   /* Build the index for table lookup
@@ -515,7 +523,10 @@ static void brw_wm_populate_key( struct brw_context *brw,
    */
   if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
      key->drawable_height = ctx->DrawBuffer->Height;
-      key->render_to_fbo = ctx->DrawBuffer->Name != 0;
+   }
+
+   if ((fp->program.Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
+      key->render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   }

   /* _NEW_BUFFERS */
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -346,7 +346,8 @@ void emit_ddxy(struct brw_compile *p,
 	       const struct brw_reg *dst,
 	       GLuint mask,
 	       bool is_ddx,
-	       const struct brw_reg *arg0);
+	       const struct brw_reg *arg0,
+	       bool negate_value);
 void emit_delta_xy(struct brw_compile *p,
 		   const struct brw_reg *dst,
 		   GLuint mask,
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -297,13 +297,11 @@ void emit_pixel_w(struct brw_wm_compile *c,
      if (c->dispatch_width == 16) {
 	 brw_math_16(p, dst[3],
 		     BRW_MATH_FUNCTION_INV,
-		     BRW_MATH_SATURATE_NONE,
 		     2, src,
 		     BRW_MATH_PRECISION_FULL);
      } else {
 	 brw_math(p, dst[3],
 		  BRW_MATH_FUNCTION_INV,
-		  BRW_MATH_SATURATE_NONE,
 		  2, src,
 		  BRW_MATH_DATA_VECTOR,
 		  BRW_MATH_PRECISION_FULL);
@@ -457,12 +455,16 @@ void emit_frontfacing(struct brw_compile *p,
 * between each other.  We could probably do it like ddx and swizzle the right
 * order later, but bail for now and just produce
 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
+ *
+ * The negate_value boolean is used to negate the d/dy computation for FBOs,
+ * since they place the origin at the upper left instead of the lower left.
 */
 void emit_ddxy(struct brw_compile *p,
 	       const struct brw_reg *dst,
 	       GLuint mask,
 	       bool is_ddx,
-	       const struct brw_reg *arg0)
+	       const struct brw_reg *arg0,
+               bool negate_value)
 {
   int i;
   struct brw_reg src0, src1;
@@ -498,7 +500,10 @@ void emit_ddxy(struct brw_compile *p,
 			   BRW_HORIZONTAL_STRIDE_0,
 			   BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
 	 }
-	 brw_ADD(p, dst[i], src0, negate(src1));
+         if (negate_value)
+            brw_ADD(p, dst[i], src1, negate(src0));
+         else
+            brw_ADD(p, dst[i], src0, negate(src1));
      }
   }
   if (mask & SATURATE)
@@ -883,9 +888,6 @@ void emit_math1(struct brw_wm_compile *c,
   struct brw_compile *p = &c->func;
   struct intel_context *intel = &p->brw->intel;
   int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1;
-   GLuint saturate = ((mask & SATURATE) ?
-		      BRW_MATH_SATURATE_SATURATE :
-		      BRW_MATH_SATURATE_NONE);
   struct brw_reg src;

   if (!(mask & WRITEMASK_XYZW))
@@ -911,11 +913,11 @@ void emit_math1(struct brw_wm_compile *c,
   /* Send two messages to perform all 16 operations:
    */
   brw_push_insn_state(p);
+   brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
   brw_set_compression_control(p, BRW_COMPRESSION_NONE);
   brw_math(p,
 	    dst[dst_chan],
 	    function,
-	    saturate,
 	    2,
 	    src,
 	    BRW_MATH_DATA_VECTOR,
@@ -926,7 +928,6 @@ void emit_math1(struct brw_wm_compile *c,
      brw_math(p,
 	       offset(dst[dst_chan],1),
 	       function,
-	       saturate,
 	       3,
 	       sechalf(src),
 	       BRW_MATH_DATA_VECTOR,
@@ -998,10 +999,6 @@ void emit_math2(struct brw_wm_compile *c,
 		   sechalf(src1));
      }
   } else {
-      GLuint saturate = ((mask & SATURATE) ?
-			 BRW_MATH_SATURATE_SATURATE :
-			 BRW_MATH_SATURATE_NONE);
-
      brw_set_compression_control(p, BRW_COMPRESSION_NONE);
      brw_MOV(p, brw_message_reg(3), arg1[0]);
      if (c->dispatch_width == 16) {
@@ -1009,11 +1006,11 @@ void emit_math2(struct brw_wm_compile *c,
 	 brw_MOV(p, brw_message_reg(5), sechalf(arg1[0]));
      }

+      brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
      brw_set_compression_control(p, BRW_COMPRESSION_NONE);
      brw_math(p,
 	       dst[dst_chan],
 	       function,
-	       saturate,
 	       2,
 	       arg0[0],
 	       BRW_MATH_DATA_VECTOR,
@@ -1026,7 +1023,6 @@ void emit_math2(struct brw_wm_compile *c,
 	 brw_math(p,
 		  offset(dst[dst_chan],1),
 		  function,
-		  saturate,
 		  4,
 		  sechalf(arg0[0]),
 		  BRW_MATH_DATA_VECTOR,
@@ -1739,11 +1735,11 @@ void brw_wm_emit( struct brw_wm_compile *c )
 	 break;

      case OPCODE_DDX:
-	 emit_ddxy(p, dst, dst_flags, true, args[0]);
+	 emit_ddxy(p, dst, dst_flags, true, args[0], false);
 	 break;

      case OPCODE_DDY:
-	 emit_ddxy(p, dst, dst_flags, false, args[0]);
+	 emit_ddxy(p, dst, dst_flags, false, args[0], c->key.render_to_fbo);
 	 break;

      case OPCODE_DP2:
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -428,7 +428,7 @@ brw_format_for_mesa_format(gl_format mesa_format)
      [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
      [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
      [MESA_FORMAT_SIGNED_RGB_16] = 0,
-      [MESA_FORMAT_SIGNED_RGBA_16] = 0,
+      [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
      [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,

      [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
@@ -583,6 +583,9 @@ translate_tex_format(gl_format mesa_format,
 		     GLenum depth_mode,
 		     GLenum srgb_decode)
 {
+   if (srgb_decode == GL_SKIP_DECODE_EXT)
+      mesa_format = _mesa_get_srgb_format_linear(mesa_format);
+
   switch( mesa_format ) {

   case MESA_FORMAT_Z16:
@@ -598,14 +601,6 @@ translate_tex_format(gl_format mesa_format,
   case MESA_FORMAT_Z32_FLOAT_X24S8:
      return BRW_SURFACEFORMAT_R32G32_FLOAT;

-   case MESA_FORMAT_SARGB8:
-   case MESA_FORMAT_SLA8:
-   case MESA_FORMAT_SL8:
-      if (srgb_decode == GL_DECODE_EXT)
-	 return brw_format_for_mesa_format(mesa_format);
-      else if (srgb_decode == GL_SKIP_DECODE_EXT)
-	 return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
-
   case MESA_FORMAT_RGBA8888_REV:
      /* This format is not renderable? */
      return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -489,6 +489,24 @@ gen6_hiz_exec(struct intel_context *intel,
         offset = intel_renderbuffer_tile_offsets(&rb, &tile_x, &tile_y);
      }

+      /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+       * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
+       * Coordinate Offset X/Y":
+       *
+       *   "The 3 LSBs of both offsets must be zero to ensure correct
+       *   alignment"
+       *
+       * We have no guarantee that tile_x and tile_y are correctly aligned,
+       * since they are determined by the mipmap layout, which is only aligned
+       * to multiples of 4.
+       *
+       * So, to avoid hanging the GPU, just smash the low order 3 bits of
+       * tile_x and tile_y to 0.  This is a temporary workaround until we come
+       * up with a better solution.
+       */
+      tile_x &= ~7;
+      tile_y &= ~7;
+
      uint32_t format;
      switch (mt->format) {
      case MESA_FORMAT_Z16:       format = BRW_DEPTHFORMAT_D16_UNORM; break;
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -29,13 +29,14 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"

 static void
 gen6_upload_scissor_state(struct brw_context *brw)
 {
   struct intel_context *intel = &brw->intel;
   struct gl_context *ctx = &intel->ctx;
-   const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   struct gen6_scissor_rect *scissor;
   uint32_t scissor_state_offset;

--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -30,6 +30,7 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "main/macros.h"
+#include "main/fbobject.h"
 #include "intel_batchbuffer.h"

 /**
@@ -123,7 +124,7 @@ upload_sf_state(struct brw_context *brw)
   uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
   int i;
   /* _NEW_BUFFER */
-   bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
   int attr = 0, input_index = 0;
   int urb_entry_read_offset = 1;
   float point_size;
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -29,6 +29,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"

 /* The clip VP defines the guardband region where expensive clipping is skipped
 * and fragments are allowed to be generated and clipped out cheaply by the SF.
@@ -70,7 +71,7 @@ gen6_upload_sf_vp(struct brw_context *brw)
   const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
   struct brw_sf_viewport *sfv;
   GLfloat y_scale, y_bias;
-   const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   const GLfloat *v = ctx->Viewport._WindowMap.m;

   sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
--- a/src/mesa/drivers/dri/i965/gen7_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_clip_state.c
@@ -26,6 +26,7 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"

 static void
 upload_clip_state(struct brw_context *brw)
@@ -40,7 +41,7 @@ upload_clip_state(struct brw_context *brw)
   const struct gl_fragment_program *fprog = brw->fragment_program;

   /* _NEW_BUFFERS */
-   bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);

   if (brw_fprog_uses_noperspective(fprog)) {
      nonperspective_barycentric_enable_flag =
--- a/src/mesa/drivers/dri/i965/gen7_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen7_hiz.c
@@ -349,6 +349,24 @@ gen7_hiz_exec(struct intel_context *intel,
         offset = intel_renderbuffer_tile_offsets(&rb, &tile_x, &tile_y);
      }

+      /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+       * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
+       * Coordinate Offset X/Y":
+       *
+       *   "The 3 LSBs of both offsets must be zero to ensure correct
+       *   alignment"
+       *
+       * We have no guarantee that tile_x and tile_y are correctly aligned,
+       * since they are determined by the mipmap layout, which is only aligned
+       * to multiples of 4.
+       *
+       * So, to avoid hanging the GPU, just smash the low order 3 bits of
+       * tile_x and tile_y to 0.  This is a temporary workaround until we come
+       * up with a better solution.
+       */
+      tile_x &= ~7;
+      tile_y &= ~7;
+
      intel_emit_depth_stall_flushes(intel);

      BEGIN_BATCH(7);
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -93,6 +93,24 @@ static void emit_depthbuffer(struct brw_context *brw)

      offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);

+      /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
+       * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
+       * Coordinate Offset X/Y":
+       *
+       *   "The 3 LSBs of both offsets must be zero to ensure correct
+       *   alignment"
+       *
+       * We have no guarantee that tile_x and tile_y are correctly aligned,
+       * since they are determined by the mipmap layout, which is only aligned
+       * to multiples of 4.
+       *
+       * So, to avoid hanging the GPU, just smash the low order 3 bits of
+       * tile_x and tile_y to 0.  This is a temporary workaround until we come
+       * up with a better solution.
+       */
+      tile_x &= ~7;
+      tile_y &= ~7;
+
      assert(region->tiling == I915_TILING_Y);

      /* _NEW_DEPTH, _NEW_STENCIL */
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -26,6 +26,7 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "main/macros.h"
+#include "main/fbobject.h"
 #include "intel_batchbuffer.h"

 static void
@@ -49,7 +50,7 @@ upload_sbe_state(struct brw_context *brw)
   bool userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
   uint16_t attr_overrides[FRAG_ATTRIB_MAX];
   /* _NEW_BUFFERS */
-   bool render_to_fbo = ctx->DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   uint32_t point_sprite_origin;

   brw_compute_vue_map(&vue_map, intel, userclip_active, vs_outputs_written);
@@ -163,7 +164,7 @@ upload_sf_state(struct brw_context *brw)
   uint32_t dw1, dw2, dw3;
   float point_size;
   /* _NEW_BUFFERS */
-   bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
+   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);

   dw1 = GEN6_SF_STATISTICS_ENABLE |
         GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
--- a/src/mesa/drivers/dri/i965/gen7_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_viewport_state.c
@@ -25,6 +25,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"

 static void
 gen7_upload_sf_clip_viewport(struct brw_context *brw)
@@ -33,7 +34,7 @@ gen7_upload_sf_clip_viewport(struct brw_context *brw)
   struct gl_context *ctx = &intel->ctx;
   const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
   GLfloat y_scale, y_bias;
-   const bool render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
   const GLfloat *v = ctx->Viewport._WindowMap.m;
   struct gen7_sf_clip_viewport *vp;

--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -192,6 +192,9 @@ _intel_batchbuffer_flush(struct intel_context *intel,

   intel->batch.reserved_space = 0;

+   if (intel->vtbl.finish_batch)
+      intel->vtbl.finish_batch(intel);
+
   /* Mark the end of the buffer. */
   intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
   if (intel->batch.used & 1) {
@@ -199,9 +202,6 @@ _intel_batchbuffer_flush(struct intel_context *intel,
      intel_batchbuffer_emit_dword(intel, MI_NOOP);
   }

-   if (intel->vtbl.finish_batch)
-      intel->vtbl.finish_batch(intel);
-
   intel_upload_finish(intel);

   /* Check that we didn't just wrap our batchbuffer at a bad time. */
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -30,6 +30,7 @@
 #include "intel_fbo.h"
 #include "intel_mipmap_tree.h"

+#include "main/fbobject.h"
 #include "main/framebuffer.h"
 #include "main/renderbuffer.h"

@@ -82,7 +83,7 @@ intel_check_front_buffer_rendering(struct intel_context *intel)
 static void
 intelDrawBuffer(struct gl_context * ctx, GLenum mode)
 {
-   if ((ctx->DrawBuffer != NULL) && (ctx->DrawBuffer->Name == 0)) {
+   if (ctx->DrawBuffer && _mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      struct intel_context *const intel = intel_context(ctx);
      const bool was_front_buffer_rendering =
 	intel->is_front_buffer_rendering;
@@ -105,7 +106,7 @@ intelDrawBuffer(struct gl_context * ctx, GLenum mode)
 static void
 intelReadBuffer(struct gl_context * ctx, GLenum mode)
 {
-   if ((ctx->DrawBuffer != NULL) && (ctx->DrawBuffer->Name == 0)) {
+   if (ctx->DrawBuffer && _mesa_is_winsys_fbo(ctx->DrawBuffer)) {
      struct intel_context *const intel = intel_context(ctx);
      const bool was_front_buffer_reading =
 	intel->is_front_buffer_reading;
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -206,7 +206,7 @@ intel_flush_front(struct gl_context *ctx)
    __DRIcontext *driContext = intel->driContext;
    __DRIscreen *const screen = intel->intelScreen->driScrnPriv;

-   if ((ctx->DrawBuffer->Name == 0) && intel->front_buffer_dirty) {
+    if (_mesa_is_winsys_fbo(ctx->DrawBuffer) && intel->front_buffer_dirty) {
      if (screen->dri2.loader &&
          (screen->dri2.loader->base.version >= 2)
 	  && (screen->dri2.loader->flushFrontBuffer != NULL) &&
@@ -445,7 +445,7 @@ intel_viewport(struct gl_context *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
    if (intel->saved_viewport)
 	intel->saved_viewport(ctx, x, y, w, h);

-    if (ctx->DrawBuffer->Name == 0) {
+    if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
       dri2InvalidateDrawable(driContext->driDrawablePriv);
       dri2InvalidateDrawable(driContext->driReadablePriv);
    }
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -29,6 +29,7 @@
 #include "main/enums.h"
 #include "main/mtypes.h"
 #include "main/macros.h"
+#include "main/fbobject.h"
 #include "main/image.h"
 #include "main/bufferobj.h"
 #include "main/readpix.h"
@@ -116,7 +117,7 @@ do_blit_readpixels(struct gl_context * ctx,
      return false;
   }
   else {
-      if (ctx->ReadBuffer->Name == 0)
+      if (_mesa_is_winsys_fbo(ctx->ReadBuffer))
 	 rowLength = -rowLength;
   }

@@ -145,7 +146,7 @@ do_blit_readpixels(struct gl_context * ctx,
 				       all ? INTEL_WRITE_FULL :
 				       INTEL_WRITE_PART);

-   if (ctx->ReadBuffer->Name == 0)
+   if (_mesa_is_winsys_fbo(ctx->ReadBuffer))
      y = ctx->ReadBuffer->Height - (y + height);

   if (!intelEmitCopyBlit(intel,
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -556,10 +556,10 @@ intelCreateContext(gl_api api,
      if (ctx->VersionMajor > major_version
 	  || (ctx->VersionMajor == major_version
 	      && ctx->VersionMinor >= minor_version)) {
-	 *error = __DRI_CTX_ERROR_BAD_VERSION;
 	 return true;
      }

+      *error = __DRI_CTX_ERROR_BAD_VERSION;
      intelDestroyContext(driContextPriv);
   } else {
      *error = __DRI_CTX_ERROR_NO_MEMORY;
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -66,6 +66,8 @@ radeon_renderbuffer_map(struct gl_context *ctx, struct gl_renderbuffer *rb)

 	rrb->base.Map = map;
 	rrb->base.RowStride = stride;
+	/* No floating point color buffers, use GLubytes */
+	rrb->base.ColorType = GL_UNSIGNED_BYTE;
 }

 static void
--- a/src/mesa/drivers/x11/xm_buffer.c
+++ b/src/mesa/drivers/x11/xm_buffer.c
@@ -446,14 +446,43 @@ xmesa_MapRenderbuffer(struct gl_context *ctx,
      }
      else {
         /* this must be a pixmap/window renderbuffer */
+         int (*old_handler)(XMesaDisplay *, XErrorEvent *);
         int y2 = rb->Height - y - h;

         assert(xrb->pixmap);

+         /* Install error handler for XGetImage() in case the the window
+          * isn't mapped.  If we fail we'll create a temporary XImage.
+          */
+         mesaXErrorFlag = 0;
+         old_handler = XSetErrorHandler(mesaHandleXError);
+
         /* read pixel data out of the pixmap/window into an XImage */
         ximage = XGetImage(xrb->Parent->display,
                            xrb->pixmap, x, y2, w, h,
                            AllPlanes, ZPixmap);
+
+         XSetErrorHandler(old_handler);
+
+         if (mesaXErrorFlag) {
+            /* create new, temporary XImage */
+            int bytes_per_line =
+               _mesa_format_row_stride(xrb->Base.Base.Format,
+                                       xrb->Base.Base.Width);
+            char *image = (char *) malloc(bytes_per_line *
+                                          xrb->Base.Base.Height);
+            ximage = XCreateImage(xrb->Parent->display,
+                                  xrb->Parent->xm_visual->visinfo->visual,
+                                  xrb->Parent->xm_visual->visinfo->depth,
+                                  ZPixmap, /* format */
+                                  0, /* offset */
+                                  image, /* data */
+                                  xrb->Base.Base.Width,
+                                  xrb->Base.Base.Height,
+                                  8, /* pad */
+                                  bytes_per_line);
+         }
+
         if (!ximage) {
            *mapOut = NULL;
            *rowStrideOut = 0;
--- a/src/mesa/main/APIspec.xml
+++ b/src/mesa/main/APIspec.xml
@@ -440,10 +440,6 @@
 		</desc>
 	</desc>

-	<desc name="border" error="GL_INVALID_VALUE">
-		<value name="0"/>
-	</desc>
-
 	<desc name="format">
 		<value name="GL_ALPHA"/>

@@ -1918,10 +1914,6 @@
 		<value name="GL_LUMINANCE"/>
 		<value name="GL_LUMINANCE_ALPHA"/>
 	</desc>
-
-	<desc name="border" error="GL_INVALID_VALUE">
-		<value name="0"/>
-	</desc>
 </template>

 <template name="CopyTexSubImage2D">
--- a/src/mesa/main/attrib.c
+++ b/src/mesa/main/attrib.c
@@ -135,6 +135,9 @@ struct gl_enable_attrib
   /* GL_ARB_point_sprite / GL_NV_point_sprite */
   GLboolean PointSprite;
   GLboolean FragmentShaderATI;
+
+   /* GL_ARB_framebuffer_sRGB / GL_EXT_framebuffer_sRGB */
+   GLboolean sRGBEnabled;
 };


@@ -322,6 +325,9 @@ _mesa_PushAttrib(GLbitfield mask)
      attr->VertexProgramPointSize = ctx->VertexProgram.PointSizeEnabled;
      attr->VertexProgramTwoSide = ctx->VertexProgram.TwoSideEnabled;
      save_attrib_data(&head, GL_ENABLE_BIT, attr);
+
+      /* GL_ARB_framebuffer_sRGB / GL_EXT_framebuffer_sRGB */
+      attr->sRGBEnabled = ctx->Color.sRGBEnabled;
   }

   if (mask & GL_EVAL_BIT) {
@@ -617,6 +623,10 @@ pop_enable_group(struct gl_context *ctx, const struct gl_enable_attrib *enable)
                   enable->VertexProgramTwoSide,
                   GL_VERTEX_PROGRAM_TWO_SIDE_ARB);

+   /* GL_ARB_framebuffer_sRGB / GL_EXT_framebuffer_sRGB */
+   TEST_AND_UPDATE(ctx->Color.sRGBEnabled, enable->sRGBEnabled,
+                   GL_FRAMEBUFFER_SRGB);
+
   /* texture unit enables */
   for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
      const GLbitfield enabled = enable->Texture[i];
@@ -799,6 +809,14 @@ pop_texture_group(struct gl_context *ctx, struct texture_state *texstate)
            _mesa_TexParameterf(target, GL_TEXTURE_COMPARE_FAIL_VALUE_ARB,
                                samp->CompareFailValue);
         }
+         if (ctx->Extensions.ARB_shadow) {
+            _mesa_TexParameteri(target, GL_TEXTURE_COMPARE_MODE,
+                                samp->CompareMode);
+            _mesa_TexParameteri(target, GL_TEXTURE_COMPARE_FUNC,
+                                samp->CompareFunc);
+         }
+         if (ctx->Extensions.ARB_depth_texture)
+            _mesa_TexParameteri(target, GL_DEPTH_TEXTURE_MODE, samp->DepthMode);
      }

      /* remove saved references to the texture objects */
@@ -973,6 +991,9 @@ _mesa_PopAttrib(void)
               _mesa_set_enable(ctx, GL_DITHER, color->DitherFlag);
               _mesa_ClampColorARB(GL_CLAMP_FRAGMENT_COLOR_ARB, color->ClampFragmentColor);
               _mesa_ClampColorARB(GL_CLAMP_READ_COLOR_ARB, color->ClampReadColor);
+
+               /* GL_ARB_framebuffer_sRGB / GL_EXT_framebuffer_sRGB */
+               _mesa_set_enable(ctx, GL_FRAMEBUFFER_SRGB, color->sRGBEnabled);
            }
            break;
         case GL_CURRENT_BIT:
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -42,6 +42,7 @@
 #include "mfeatures.h"
 #include "mtypes.h"
 #include "texobj.h"
+#include "transformfeedback.h"


 /* Debug flags */
@@ -524,7 +525,7 @@ _mesa_copy_buffer_subdata(struct gl_context *ctx,
                          GLintptr readOffset, GLintptr writeOffset,
                          GLsizeiptr size)
 {
-   void *srcPtr, *dstPtr;
+   GLubyte *srcPtr, *dstPtr;

   /* the buffers should not be mapped */
   assert(!_mesa_bufferobj_mapped(src));
@@ -791,6 +792,24 @@ _mesa_DeleteBuffersARB(GLsizei n, const GLuint *ids)
            _mesa_BindBufferARB( GL_ELEMENT_ARRAY_BUFFER_ARB, 0 );
         }

+         /* unbind ARB_copy_buffer binding points */
+         if (ctx->CopyReadBuffer == bufObj) {
+            _mesa_BindBufferARB( GL_COPY_READ_BUFFER, 0 );
+         }
+         if (ctx->CopyWriteBuffer == bufObj) {
+            _mesa_BindBufferARB( GL_COPY_WRITE_BUFFER, 0 );
+         }
+
+         /* unbind transform feedback binding points */
+         if (ctx->TransformFeedback.CurrentBuffer == bufObj) {
+            _mesa_BindBufferARB( GL_TRANSFORM_FEEDBACK_BUFFER, 0 );
+         }
+         for (j = 0; j < MAX_FEEDBACK_ATTRIBS; j++) {
+            if (ctx->TransformFeedback.CurrentObject->Buffers[j] == bufObj) {
+               _mesa_BindBufferBase( GL_TRANSFORM_FEEDBACK_BUFFER, j, 0 );
+            }
+         }
+
         /* unbind any pixel pack/unpack pointers bound to this buffer */
         if (ctx->Pack.BufferObj == bufObj) {
            _mesa_BindBufferARB( GL_PIXEL_PACK_BUFFER_EXT, 0 );
@@ -1311,6 +1330,12 @@ _mesa_CopyBufferSubData(GLenum readTarget, GLenum writeTarget,
      return;
   }

+   if (size < 0) {
+      _mesa_error(ctx, GL_INVALID_VALUE,
+                  "glCopyBufferSubData(writeOffset = %d)", (int) size);
+      return;
+   }
+
   if (readOffset + size > src->Size) {
      _mesa_error(ctx, GL_INVALID_VALUE,
                  "glCopyBuffserSubData(readOffset + size = %d)",
--- a/Show More
+++ b/Show More