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explicit-s
...
mesa-18.1.
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08e8556f54 | ||
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d6a312e288 | ||
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d844b2a656 | ||
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a829747276 | ||
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ff1ecebb1d |
@@ -21,7 +21,7 @@ env:
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- LIBXCB_VERSION=libxcb-1.13
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- LIBXSHMFENCE_VERSION=libxshmfence-1.2
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- LIBVDPAU_VERSION=libvdpau-1.1
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- LIBVA_VERSION=libva-1.6.2
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- LIBVA_VERSION=libva-1.7.0
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- LIBWAYLAND_VERSION=wayland-1.11.1
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- WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
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- PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
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|
@@ -16,7 +16,7 @@ latest_branchpoint=`git merge-base origin/master HEAD`
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git log --reverse --pretty=%H $latest_branchpoint > already_landed
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# ... and the ones cherry-picked.
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git log --reverse --grep="cherry picked from commit" $latest_branchpoint..HEAD |\
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git log --reverse --pretty=medium --grep="cherry picked from commit" $latest_branchpoint..HEAD |\
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grep "cherry picked from commit" |\
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sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
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@@ -38,7 +38,7 @@ do
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# Place every "fixes:" tag on its own line and join with the next word
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# on its line or a later one.
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fixes=`git show -s $sha | tr -d "\n" | sed -e 's/fixes:[[:space:]]*/\nfixes:/Ig' | grep "fixes:" | sed -e 's/\(fixes:[a-zA-Z0-9]*\).*$/\1/'`
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fixes=`git show --pretty=medium -s $sha | tr -d "\n" | sed -e 's/fixes:[[:space:]]*/\nfixes:/Ig' | grep "fixes:" | sed -e 's/\(fixes:[a-zA-Z0-9]*\).*$/\1/'`
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# For each one try to extract the tag
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fixes_count=`echo "$fixes" | wc -l`
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@@ -12,7 +12,7 @@
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latest_branchpoint=`git merge-base origin/master HEAD`
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# Grep for commits with "cherry picked from commit" in the commit message.
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git log --reverse --grep="cherry picked from commit" $latest_branchpoint..HEAD |\
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git log --reverse --pretty=medium --grep="cherry picked from commit" $latest_branchpoint..HEAD |\
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grep "cherry picked from commit" |\
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sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked
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@@ -1,6 +1,6 @@
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#!/usr/bin/env python
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# encoding=utf-8
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# Copyright © 2017 Intel Corporation
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# Copyright © 2017-2018 Intel Corporation
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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@@ -35,7 +35,11 @@ def main():
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parser.add_argument('drivers', nargs='+')
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args = parser.parse_args()
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to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), args.libdir)
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if os.path.isabs(args.libdir):
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to = os.path.join(os.environ.get('DESTDIR', '/'), args.libdir[1:])
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else:
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to = os.path.join(os.environ['MESON_INSTALL_DESTDIR_PREFIX'], args.libdir)
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master = os.path.join(to, os.path.basename(args.megadriver))
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if not os.path.exists(to):
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|
@@ -86,7 +86,7 @@ DRI2PROTO_REQUIRED=2.8
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GLPROTO_REQUIRED=1.4.14
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LIBOMXIL_BELLAGIO_REQUIRED=0.0
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LIBOMXIL_TIZONIA_REQUIRED=0.10.0
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LIBVA_REQUIRED=0.38.0
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LIBVA_REQUIRED=0.39.0
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VDPAU_REQUIRED=1.1
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WAYLAND_REQUIRED=1.11
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WAYLAND_PROTOCOLS_REQUIRED=1.8
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|
@@ -584,7 +584,7 @@ endif
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with_gallium_va = _va == 'true'
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dep_va = null_dep
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if with_gallium_va
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dep_va = dependency('libva', version : '>= 0.38.0')
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dep_va = dependency('libva', version : '>= 0.39.0')
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dep_va_headers = declare_dependency(
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compile_args : run_command(prog_pkgconfig, ['libva', '--cflags']).stdout().split()
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)
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|
@@ -1521,6 +1521,20 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
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LLVMValueRef addr;
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unsigned num_addr = 0;
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if (a->opcode == ac_image_get_lod) {
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switch (a->dim) {
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case ac_image_1darray:
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num_coords = 1;
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break;
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case ac_image_2darray:
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case ac_image_cube:
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num_coords = 2;
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break;
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default:
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break;
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}
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}
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if (a->offset)
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args[num_addr++] = ac_to_integer(ctx, a->offset);
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if (a->bias)
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@@ -1307,6 +1307,14 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
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}
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}
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/* Fixup for GFX9 which allocates 1D textures as 2D. */
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if (instr->op == nir_texop_lod && ctx->ac.chip_class >= GFX9) {
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if ((args->dim == ac_image_2darray ||
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args->dim == ac_image_2d) && !args->coords[1]) {
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args->coords[1] = ctx->ac.i32_0;
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}
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}
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args->attributes = AC_FUNC_ATTR_READNONE;
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return ac_build_image_opcode(&ctx->ac, args);
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}
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@@ -3397,6 +3405,13 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
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}
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/* Texture coordinates fixups */
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if (instr->coord_components > 1 &&
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instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
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instr->is_array &&
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instr->op != nir_texop_txf) {
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args.coords[1] = apply_round_slice(&ctx->ac, args.coords[1]);
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}
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if (instr->coord_components > 2 &&
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(instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
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instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
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|
@@ -463,15 +463,6 @@ VkResult radv_CreateInstance(
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client_version = VK_MAKE_VERSION(1, 0, 0);
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}
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if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
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client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
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return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
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"Client requested version %d.%d.%d",
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VK_VERSION_MAJOR(client_version),
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VK_VERSION_MINOR(client_version),
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VK_VERSION_PATCH(client_version));
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}
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instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
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if (!instance)
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@@ -205,7 +205,7 @@ radv_entrypoint_is_enabled(int index, uint32_t core_version,
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% if not e.device_command:
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if (device) return false;
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% endif
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% if e.name == 'vkCreateInstance' or e.name == 'vkEnumerateInstanceExtensionProperties' or e.name == 'vkEnumerateInstanceLayerProperties':
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% if e.name == 'vkCreateInstance' or e.name == 'vkEnumerateInstanceExtensionProperties' or e.name == 'vkEnumerateInstanceLayerProperties' or e.name == 'vkEnumerateInstanceVersion':
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return !device;
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% elif e.core_version:
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return instance && ${e.core_version.c_vk_version()} <= core_version;
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@@ -133,12 +133,12 @@ radv_use_dcc_for_image(struct radv_device *device,
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if (create_info->scanout)
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return false;
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/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet. */
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if (pCreateInfo->samples > 2)
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return false;
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/* TODO: Enable DCC for MSAA textures. */
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if (!device->physical_device->dcc_msaa_allowed)
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/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
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* 2x can be enabled with an option.
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*/
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if (pCreateInfo->samples > 2 ||
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(pCreateInfo->samples == 2 &&
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!device->physical_device->dcc_msaa_allowed))
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return false;
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/* Determine if the formats are DCC compatible. */
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@@ -968,7 +968,7 @@ radv_image_create(VkDevice _device,
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image->info.samples = pCreateInfo->samples;
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image->info.array_size = pCreateInfo->arrayLayers;
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image->info.levels = pCreateInfo->mipLevels;
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image->info.num_channels = 4; /* TODO: set this correctly */
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image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
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image->vk_format = pCreateInfo->format;
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image->tiling = pCreateInfo->tiling;
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@@ -100,7 +100,8 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
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struct radv_meta_blit2d_buffer *src_buf,
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struct blit2d_src_temps *tmp,
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enum blit2d_src_type src_type, VkFormat depth_format,
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VkImageAspectFlagBits aspects)
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VkImageAspectFlagBits aspects,
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uint32_t log2_samples)
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{
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struct radv_device *device = cmd_buffer->device;
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@@ -108,7 +109,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
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create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
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radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
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device->meta_state.blit2d.p_layouts[src_type],
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device->meta_state.blit2d[log2_samples].p_layouts[src_type],
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0, /* set */
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1, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]) {
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@@ -123,7 +124,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
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});
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.blit2d.p_layouts[src_type],
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device->meta_state.blit2d[log2_samples].p_layouts[src_type],
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VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
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&src_buf->pitch);
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} else {
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@@ -131,12 +132,12 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
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if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.blit2d.p_layouts[src_type],
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device->meta_state.blit2d[log2_samples].p_layouts[src_type],
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VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
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&src_img->layer);
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radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
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device->meta_state.blit2d.p_layouts[src_type],
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device->meta_state.blit2d[log2_samples].p_layouts[src_type],
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0, /* set */
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1, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]) {
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@@ -190,10 +191,11 @@ blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
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static void
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bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
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enum blit2d_src_type src_type, unsigned fs_key)
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enum blit2d_src_type src_type, unsigned fs_key,
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uint32_t log2_samples)
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{
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VkPipeline pipeline =
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cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
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cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
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@@ -201,10 +203,11 @@ bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
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static void
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bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
|
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enum blit2d_src_type src_type)
|
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enum blit2d_src_type src_type,
|
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uint32_t log2_samples)
|
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{
|
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VkPipeline pipeline =
|
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cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
|
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cmd_buffer->device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type];
|
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|
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
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VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
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@@ -212,10 +215,11 @@ bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
|
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|
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static void
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bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
|
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enum blit2d_src_type src_type)
|
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enum blit2d_src_type src_type,
|
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uint32_t log2_samples)
|
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{
|
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VkPipeline pipeline =
|
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cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
|
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cmd_buffer->device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type];
|
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|
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
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VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
|
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@@ -227,7 +231,8 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
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struct radv_meta_blit2d_buffer *src_buf,
|
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struct radv_meta_blit2d_surf *dst,
|
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unsigned num_rects,
|
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struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
|
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struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type,
|
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uint32_t log2_samples)
|
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{
|
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struct radv_device *device = cmd_buffer->device;
|
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|
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@@ -241,7 +246,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
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else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
|
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depth_format = vk_format_depth_only(dst->image->vk_format);
|
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struct blit2d_src_temps src_temps;
|
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blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, aspect_mask);
|
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blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, aspect_mask, log2_samples);
|
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|
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struct blit2d_dst_temps dst_temps;
|
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blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
|
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@@ -255,7 +260,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
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};
|
||||
|
||||
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
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device->meta_state.blit2d.p_layouts[src_type],
|
||||
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
|
||||
vertex_push_constants);
|
||||
|
||||
@@ -266,7 +271,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
||||
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
&(VkRenderPassBeginInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
|
||||
.renderPass = device->meta_state.blit2d.render_passes[fs_key][dst_layout],
|
||||
.renderPass = device->meta_state.blit2d_render_passes[fs_key][dst_layout],
|
||||
.framebuffer = dst_temps.fb,
|
||||
.renderArea = {
|
||||
.offset = { rects[r].dst_x, rects[r].dst_y, },
|
||||
@@ -277,13 +282,13 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
||||
}, VK_SUBPASS_CONTENTS_INLINE);
|
||||
|
||||
|
||||
bind_pipeline(cmd_buffer, src_type, fs_key);
|
||||
bind_pipeline(cmd_buffer, src_type, fs_key, log2_samples);
|
||||
} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
|
||||
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
|
||||
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
&(VkRenderPassBeginInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
|
||||
.renderPass = device->meta_state.blit2d.depth_only_rp[ds_layout],
|
||||
.renderPass = device->meta_state.blit2d_depth_only_rp[ds_layout],
|
||||
.framebuffer = dst_temps.fb,
|
||||
.renderArea = {
|
||||
.offset = { rects[r].dst_x, rects[r].dst_y, },
|
||||
@@ -294,14 +299,14 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
||||
}, VK_SUBPASS_CONTENTS_INLINE);
|
||||
|
||||
|
||||
bind_depth_pipeline(cmd_buffer, src_type);
|
||||
bind_depth_pipeline(cmd_buffer, src_type, log2_samples);
|
||||
|
||||
} else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
|
||||
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
|
||||
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
&(VkRenderPassBeginInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
|
||||
.renderPass = device->meta_state.blit2d.stencil_only_rp[ds_layout],
|
||||
.renderPass = device->meta_state.blit2d_stencil_only_rp[ds_layout],
|
||||
.framebuffer = dst_temps.fb,
|
||||
.renderArea = {
|
||||
.offset = { rects[r].dst_x, rects[r].dst_y, },
|
||||
@@ -312,7 +317,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
||||
}, VK_SUBPASS_CONTENTS_INLINE);
|
||||
|
||||
|
||||
bind_stencil_pipeline(cmd_buffer, src_type);
|
||||
bind_stencil_pipeline(cmd_buffer, src_type, log2_samples);
|
||||
} else
|
||||
unreachable("Processing blit2d with multiple aspects.");
|
||||
|
||||
@@ -332,7 +337,24 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
|
||||
|
||||
|
||||
|
||||
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
||||
if (log2_samples > 0) {
|
||||
for (uint32_t sample = 0; sample < src_img->image->info.samples; sample++) {
|
||||
uint32_t sample_mask = 1 << sample;
|
||||
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
VK_SHADER_STAGE_FRAGMENT_BIT, 20, 4,
|
||||
&sample);
|
||||
|
||||
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
||||
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
VK_SHADER_STAGE_FRAGMENT_BIT, 24, 4,
|
||||
&sample_mask);
|
||||
|
||||
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
||||
}
|
||||
}
|
||||
else
|
||||
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
||||
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
|
||||
|
||||
/* At the point where we emit the draw call, all data from the
|
||||
@@ -358,7 +380,8 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
|
||||
enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
|
||||
use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
|
||||
radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
|
||||
num_rects, rects, src_type);
|
||||
num_rects, rects, src_type,
|
||||
src_img ? util_logbase2(src_img->image->info.samples) : 0);
|
||||
}
|
||||
|
||||
static nir_shader *
|
||||
@@ -421,13 +444,14 @@ build_nir_vertex_shader(void)
|
||||
|
||||
typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
|
||||
struct radv_device *,
|
||||
nir_ssa_def *, bool);
|
||||
nir_ssa_def *, bool, bool);
|
||||
|
||||
static nir_ssa_def *
|
||||
build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
|
||||
nir_ssa_def *tex_pos, bool is_3d)
|
||||
nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
|
||||
{
|
||||
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
|
||||
enum glsl_sampler_dim dim =
|
||||
is_3d ? GLSL_SAMPLER_DIM_3D : is_multisampled ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
|
||||
const struct glsl_type *sampler_type =
|
||||
glsl_sampler_type(dim, false, false, GLSL_TYPE_UINT);
|
||||
nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
|
||||
@@ -436,6 +460,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
|
||||
sampler->data.binding = 0;
|
||||
|
||||
nir_ssa_def *tex_pos_3d = NULL;
|
||||
nir_intrinsic_instr *sample_idx = NULL;
|
||||
if (is_3d) {
|
||||
nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
|
||||
nir_intrinsic_set_base(layer, 16);
|
||||
@@ -451,13 +476,26 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
|
||||
chans[2] = &layer->dest.ssa;
|
||||
tex_pos_3d = nir_vec(b, chans, 3);
|
||||
}
|
||||
nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
|
||||
if (is_multisampled) {
|
||||
sample_idx = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
|
||||
nir_intrinsic_set_base(sample_idx, 20);
|
||||
nir_intrinsic_set_range(sample_idx, 4);
|
||||
sample_idx->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
|
||||
sample_idx->num_components = 1;
|
||||
nir_ssa_dest_init(&sample_idx->instr, &sample_idx->dest, 1, 32, "sample_idx");
|
||||
nir_builder_instr_insert(b, &sample_idx->instr);
|
||||
}
|
||||
nir_tex_instr *tex = nir_tex_instr_create(b->shader, is_multisampled ? 3 : 2);
|
||||
tex->sampler_dim = dim;
|
||||
tex->op = nir_texop_txf;
|
||||
tex->op = is_multisampled ? nir_texop_txf_ms : nir_texop_txf;
|
||||
tex->src[0].src_type = nir_tex_src_coord;
|
||||
tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
|
||||
tex->src[1].src_type = nir_tex_src_lod;
|
||||
tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
|
||||
tex->src[1].src_type = is_multisampled ? nir_tex_src_ms_index : nir_tex_src_lod;
|
||||
tex->src[1].src = nir_src_for_ssa(is_multisampled ? &sample_idx->dest.ssa : nir_imm_int(b, 0));
|
||||
if (is_multisampled) {
|
||||
tex->src[2].src_type = nir_tex_src_lod;
|
||||
tex->src[2].src = nir_src_for_ssa(nir_imm_int(b, 0));
|
||||
}
|
||||
tex->dest_type = nir_type_uint;
|
||||
tex->is_array = false;
|
||||
tex->coord_components = is_3d ? 3 : 2;
|
||||
@@ -473,7 +511,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
|
||||
|
||||
static nir_ssa_def *
|
||||
build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
|
||||
nir_ssa_def *tex_pos, bool is_3d)
|
||||
nir_ssa_def *tex_pos, bool is_3d, bool is_multisampled)
|
||||
{
|
||||
const struct glsl_type *sampler_type =
|
||||
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
|
||||
@@ -519,9 +557,31 @@ static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
|
||||
.vertexAttributeDescriptionCount = 0,
|
||||
};
|
||||
|
||||
static void
|
||||
build_nir_store_sample_mask(struct nir_builder *b)
|
||||
{
|
||||
nir_intrinsic_instr *sample_mask = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
|
||||
nir_intrinsic_set_base(sample_mask, 24);
|
||||
nir_intrinsic_set_range(sample_mask, 4);
|
||||
sample_mask->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
|
||||
sample_mask->num_components = 1;
|
||||
nir_ssa_dest_init(&sample_mask->instr, &sample_mask->dest, 1, 32, "sample_mask");
|
||||
nir_builder_instr_insert(b, &sample_mask->instr);
|
||||
|
||||
const struct glsl_type *sample_mask_out_type = glsl_uint_type();
|
||||
|
||||
nir_variable *sample_mask_out =
|
||||
nir_variable_create(b->shader, nir_var_shader_out,
|
||||
sample_mask_out_type, "sample_mask_out");
|
||||
sample_mask_out->data.location = FRAG_RESULT_SAMPLE_MASK;
|
||||
|
||||
nir_store_var(b, sample_mask_out, &sample_mask->dest.ssa, 0x1);
|
||||
}
|
||||
|
||||
static nir_shader *
|
||||
build_nir_copy_fragment_shader(struct radv_device *device,
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d)
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d,
|
||||
bool is_multisampled)
|
||||
{
|
||||
const struct glsl_type *vec4 = glsl_vec4_type();
|
||||
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
|
||||
@@ -538,11 +598,15 @@ build_nir_copy_fragment_shader(struct radv_device *device,
|
||||
vec4, "f_color");
|
||||
color_out->data.location = FRAG_RESULT_DATA0;
|
||||
|
||||
if (is_multisampled) {
|
||||
build_nir_store_sample_mask(&b);
|
||||
}
|
||||
|
||||
nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
|
||||
unsigned swiz[4] = { 0, 1 };
|
||||
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
|
||||
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
|
||||
nir_store_var(&b, color_out, color, 0xf);
|
||||
|
||||
return b.shader;
|
||||
@@ -550,7 +614,8 @@ build_nir_copy_fragment_shader(struct radv_device *device,
|
||||
|
||||
static nir_shader *
|
||||
build_nir_copy_fragment_shader_depth(struct radv_device *device,
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d)
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d,
|
||||
bool is_multisampled)
|
||||
{
|
||||
const struct glsl_type *vec4 = glsl_vec4_type();
|
||||
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
|
||||
@@ -567,11 +632,15 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,
|
||||
vec4, "f_color");
|
||||
color_out->data.location = FRAG_RESULT_DEPTH;
|
||||
|
||||
if (is_multisampled) {
|
||||
build_nir_store_sample_mask(&b);
|
||||
}
|
||||
|
||||
nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
|
||||
unsigned swiz[4] = { 0, 1 };
|
||||
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
|
||||
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
|
||||
nir_store_var(&b, color_out, color, 0x1);
|
||||
|
||||
return b.shader;
|
||||
@@ -579,7 +648,8 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,
|
||||
|
||||
static nir_shader *
|
||||
build_nir_copy_fragment_shader_stencil(struct radv_device *device,
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d)
|
||||
texel_fetch_build_func txf_func, const char* name, bool is_3d,
|
||||
bool is_multisampled)
|
||||
{
|
||||
const struct glsl_type *vec4 = glsl_vec4_type();
|
||||
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
|
||||
@@ -596,11 +666,15 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device,
|
||||
vec4, "f_color");
|
||||
color_out->data.location = FRAG_RESULT_STENCIL;
|
||||
|
||||
if (is_multisampled) {
|
||||
build_nir_store_sample_mask(&b);
|
||||
}
|
||||
|
||||
nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
|
||||
unsigned swiz[4] = { 0, 1 };
|
||||
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
|
||||
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
|
||||
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d, is_multisampled);
|
||||
nir_store_var(&b, color_out, color, 0x1);
|
||||
|
||||
return b.shader;
|
||||
@@ -614,45 +688,48 @@ radv_device_finish_meta_blit2d_state(struct radv_device *device)
|
||||
for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
||||
for (unsigned k = 0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
|
||||
radv_DestroyRenderPass(radv_device_to_handle(device),
|
||||
state->blit2d.render_passes[j][k],
|
||||
&state->alloc);
|
||||
state->blit2d_render_passes[j][k],
|
||||
&state->alloc);
|
||||
}
|
||||
}
|
||||
|
||||
for (enum radv_blit_ds_layout j = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; j < RADV_BLIT_DS_LAYOUT_COUNT; j++) {
|
||||
radv_DestroyRenderPass(radv_device_to_handle(device),
|
||||
state->blit2d.depth_only_rp[j], &state->alloc);
|
||||
state->blit2d_depth_only_rp[j], &state->alloc);
|
||||
radv_DestroyRenderPass(radv_device_to_handle(device),
|
||||
state->blit2d.stencil_only_rp[j], &state->alloc);
|
||||
state->blit2d_stencil_only_rp[j], &state->alloc);
|
||||
}
|
||||
|
||||
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
|
||||
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
||||
state->blit2d.p_layouts[src],
|
||||
&state->alloc);
|
||||
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
||||
state->blit2d.ds_layouts[src],
|
||||
&state->alloc);
|
||||
for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; ++log2_samples) {
|
||||
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
|
||||
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
||||
state->blit2d[log2_samples].p_layouts[src],
|
||||
&state->alloc);
|
||||
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
||||
state->blit2d[log2_samples].ds_layouts[src],
|
||||
&state->alloc);
|
||||
|
||||
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->blit2d[log2_samples].pipelines[src][j],
|
||||
&state->alloc);
|
||||
}
|
||||
|
||||
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->blit2d.pipelines[src][j],
|
||||
state->blit2d[log2_samples].depth_only_pipeline[src],
|
||||
&state->alloc);
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->blit2d[log2_samples].stencil_only_pipeline[src],
|
||||
&state->alloc);
|
||||
}
|
||||
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->blit2d.depth_only_pipeline[src],
|
||||
&state->alloc);
|
||||
radv_DestroyPipeline(radv_device_to_handle(device),
|
||||
state->blit2d.stencil_only_pipeline[src],
|
||||
&state->alloc);
|
||||
}
|
||||
}
|
||||
|
||||
static VkResult
|
||||
blit2d_init_color_pipeline(struct radv_device *device,
|
||||
enum blit2d_src_type src_type,
|
||||
VkFormat format)
|
||||
VkFormat format,
|
||||
uint32_t log2_samples)
|
||||
{
|
||||
VkResult result;
|
||||
unsigned fs_key = radv_format_meta_fs_key(format);
|
||||
@@ -681,7 +758,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
struct radv_shader_module fs = { .nir = NULL };
|
||||
|
||||
|
||||
fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
|
||||
fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
|
||||
vi_create_info = &normal_vi_create_info;
|
||||
|
||||
struct radv_shader_module vs = {
|
||||
@@ -705,7 +782,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
};
|
||||
|
||||
for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
|
||||
if (!device->meta_state.blit2d.render_passes[fs_key][dst_layout]) {
|
||||
if (!device->meta_state.blit2d_render_passes[fs_key][dst_layout]) {
|
||||
VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
|
||||
|
||||
result = radv_CreateRenderPass(radv_device_to_handle(device),
|
||||
@@ -737,7 +814,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
.pPreserveAttachments = (uint32_t[]) { 0 },
|
||||
},
|
||||
.dependencyCount = 0,
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key][dst_layout]);
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -765,7 +842,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
},
|
||||
.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
|
||||
.rasterizationSamples = 1,
|
||||
.rasterizationSamples = 1 << log2_samples,
|
||||
.sampleShadingEnable = false,
|
||||
.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
|
||||
},
|
||||
@@ -796,8 +873,8 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
},
|
||||
},
|
||||
.flags = 0,
|
||||
.layout = device->meta_state.blit2d.p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d.render_passes[fs_key][0],
|
||||
.layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d_render_passes[fs_key][0],
|
||||
.subpass = 0,
|
||||
};
|
||||
|
||||
@@ -809,7 +886,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
||||
&vk_pipeline_info, &radv_pipeline_info,
|
||||
&device->meta_state.alloc,
|
||||
&device->meta_state.blit2d.pipelines[src_type][fs_key]);
|
||||
&device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key]);
|
||||
|
||||
|
||||
ralloc_free(vs.nir);
|
||||
@@ -820,7 +897,8 @@ blit2d_init_color_pipeline(struct radv_device *device,
|
||||
|
||||
static VkResult
|
||||
blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
enum blit2d_src_type src_type)
|
||||
enum blit2d_src_type src_type,
|
||||
uint32_t log2_samples)
|
||||
{
|
||||
VkResult result;
|
||||
const char *name;
|
||||
@@ -847,7 +925,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
|
||||
struct radv_shader_module fs = { .nir = NULL };
|
||||
|
||||
fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
|
||||
fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
|
||||
vi_create_info = &normal_vi_create_info;
|
||||
|
||||
struct radv_shader_module vs = {
|
||||
@@ -871,7 +949,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
};
|
||||
|
||||
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
|
||||
if (!device->meta_state.blit2d.depth_only_rp[ds_layout]) {
|
||||
if (!device->meta_state.blit2d_depth_only_rp[ds_layout]) {
|
||||
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
|
||||
result = radv_CreateRenderPass(radv_device_to_handle(device),
|
||||
&(VkRenderPassCreateInfo) {
|
||||
@@ -899,7 +977,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
.pPreserveAttachments = (uint32_t[]) { 0 },
|
||||
},
|
||||
.dependencyCount = 0,
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp[ds_layout]);
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d_depth_only_rp[ds_layout]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -927,7 +1005,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
},
|
||||
.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
|
||||
.rasterizationSamples = 1,
|
||||
.rasterizationSamples = 1 << log2_samples,
|
||||
.sampleShadingEnable = false,
|
||||
.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
|
||||
},
|
||||
@@ -958,8 +1036,8 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
},
|
||||
},
|
||||
.flags = 0,
|
||||
.layout = device->meta_state.blit2d.p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d.depth_only_rp[0],
|
||||
.layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d_depth_only_rp[0],
|
||||
.subpass = 0,
|
||||
};
|
||||
|
||||
@@ -971,7 +1049,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
||||
&vk_pipeline_info, &radv_pipeline_info,
|
||||
&device->meta_state.alloc,
|
||||
&device->meta_state.blit2d.depth_only_pipeline[src_type]);
|
||||
&device->meta_state.blit2d[log2_samples].depth_only_pipeline[src_type]);
|
||||
|
||||
|
||||
ralloc_free(vs.nir);
|
||||
@@ -982,7 +1060,8 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
|
||||
|
||||
static VkResult
|
||||
blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
enum blit2d_src_type src_type)
|
||||
enum blit2d_src_type src_type,
|
||||
uint32_t log2_samples)
|
||||
{
|
||||
VkResult result;
|
||||
const char *name;
|
||||
@@ -1009,7 +1088,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
|
||||
struct radv_shader_module fs = { .nir = NULL };
|
||||
|
||||
fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
|
||||
fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D, log2_samples > 0);
|
||||
vi_create_info = &normal_vi_create_info;
|
||||
|
||||
struct radv_shader_module vs = {
|
||||
@@ -1033,7 +1112,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
};
|
||||
|
||||
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
|
||||
if (!device->meta_state.blit2d.stencil_only_rp[ds_layout]) {
|
||||
if (!device->meta_state.blit2d_stencil_only_rp[ds_layout]) {
|
||||
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
|
||||
result = radv_CreateRenderPass(radv_device_to_handle(device),
|
||||
&(VkRenderPassCreateInfo) {
|
||||
@@ -1061,7 +1140,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
.pPreserveAttachments = (uint32_t[]) { 0 },
|
||||
},
|
||||
.dependencyCount = 0,
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp[ds_layout]);
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d_stencil_only_rp[ds_layout]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1089,7 +1168,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
},
|
||||
.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
|
||||
.rasterizationSamples = 1,
|
||||
.rasterizationSamples = 1 << log2_samples,
|
||||
.sampleShadingEnable = false,
|
||||
.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
|
||||
},
|
||||
@@ -1136,8 +1215,8 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
},
|
||||
},
|
||||
.flags = 0,
|
||||
.layout = device->meta_state.blit2d.p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d.stencil_only_rp[0],
|
||||
.layout = device->meta_state.blit2d[log2_samples].p_layouts[src_type],
|
||||
.renderPass = device->meta_state.blit2d_stencil_only_rp[0],
|
||||
.subpass = 0,
|
||||
};
|
||||
|
||||
@@ -1149,7 +1228,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
|
||||
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
||||
&vk_pipeline_info, &radv_pipeline_info,
|
||||
&device->meta_state.alloc,
|
||||
&device->meta_state.blit2d.stencil_only_pipeline[src_type]);
|
||||
&device->meta_state.blit2d[log2_samples].stencil_only_pipeline[src_type]);
|
||||
|
||||
|
||||
ralloc_free(vs.nir);
|
||||
@@ -1175,15 +1254,16 @@ static VkFormat pipeline_formats[] = {
|
||||
|
||||
static VkResult
|
||||
meta_blit2d_create_pipe_layout(struct radv_device *device,
|
||||
int idx)
|
||||
int idx,
|
||||
uint32_t log2_samples)
|
||||
{
|
||||
VkResult result;
|
||||
VkDescriptorType desc_type = (idx == BLIT2D_SRC_TYPE_BUFFER) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER : VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE;
|
||||
const VkPushConstantRange push_constant_ranges[] = {
|
||||
{VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
|
||||
{VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
|
||||
{VK_SHADER_STAGE_FRAGMENT_BIT, 16, 12},
|
||||
};
|
||||
int num_push_constant_range = (idx != BLIT2D_SRC_TYPE_IMAGE) ? 2 : 1;
|
||||
int num_push_constant_range = (idx != BLIT2D_SRC_TYPE_IMAGE || log2_samples > 0) ? 2 : 1;
|
||||
|
||||
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
|
||||
&(VkDescriptorSetLayoutCreateInfo) {
|
||||
@@ -1199,7 +1279,7 @@ meta_blit2d_create_pipe_layout(struct radv_device *device,
|
||||
.pImmutableSamplers = NULL
|
||||
},
|
||||
}
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[idx]);
|
||||
}, &device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].ds_layouts[idx]);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
@@ -1207,11 +1287,11 @@ meta_blit2d_create_pipe_layout(struct radv_device *device,
|
||||
&(VkPipelineLayoutCreateInfo) {
|
||||
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
||||
.setLayoutCount = 1,
|
||||
.pSetLayouts = &device->meta_state.blit2d.ds_layouts[idx],
|
||||
.pSetLayouts = &device->meta_state.blit2d[log2_samples].ds_layouts[idx],
|
||||
.pushConstantRangeCount = num_push_constant_range,
|
||||
.pPushConstantRanges = push_constant_ranges,
|
||||
},
|
||||
&device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[idx]);
|
||||
&device->meta_state.alloc, &device->meta_state.blit2d[log2_samples].p_layouts[idx]);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
return VK_SUCCESS;
|
||||
@@ -1225,27 +1305,33 @@ radv_device_init_meta_blit2d_state(struct radv_device *device)
|
||||
VkResult result;
|
||||
bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
|
||||
|
||||
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
|
||||
if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
|
||||
continue;
|
||||
for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; log2_samples++) {
|
||||
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
|
||||
if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
|
||||
continue;
|
||||
|
||||
result = meta_blit2d_create_pipe_layout(device, src);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
/* Don't need to handle copies between buffers and multisample images. */
|
||||
if (src == BLIT2D_SRC_TYPE_BUFFER && log2_samples > 0)
|
||||
continue;
|
||||
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
|
||||
result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
|
||||
result = meta_blit2d_create_pipe_layout(device, src, log2_samples);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
|
||||
result = blit2d_init_color_pipeline(device, src, pipeline_formats[j], log2_samples);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
result = blit2d_init_depth_only_pipeline(device, src, log2_samples);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
result = blit2d_init_stencil_only_pipeline(device, src, log2_samples);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
result = blit2d_init_depth_only_pipeline(device, src);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
|
||||
result = blit2d_init_stencil_only_pipeline(device, src);
|
||||
if (result != VK_SUCCESS)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return VK_SUCCESS;
|
||||
|
@@ -87,8 +87,8 @@ VkResult radv_CreateRenderPass(
|
||||
subpass_attachment_count +=
|
||||
desc->inputAttachmentCount +
|
||||
desc->colorAttachmentCount +
|
||||
/* Count colorAttachmentCount again for resolve_attachments */
|
||||
desc->colorAttachmentCount;
|
||||
(desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
|
||||
(desc->pDepthStencilAttachment != NULL);
|
||||
}
|
||||
|
||||
if (subpass_attachment_count) {
|
||||
|
@@ -465,18 +465,18 @@ struct radv_meta_state {
|
||||
} blit;
|
||||
|
||||
struct {
|
||||
VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
|
||||
VkPipelineLayout p_layouts[5];
|
||||
VkDescriptorSetLayout ds_layouts[5];
|
||||
VkPipeline pipelines[5][NUM_META_FS_KEYS];
|
||||
|
||||
VkPipelineLayout p_layouts[3];
|
||||
VkDescriptorSetLayout ds_layouts[3];
|
||||
VkPipeline pipelines[3][NUM_META_FS_KEYS];
|
||||
VkPipeline depth_only_pipeline[5];
|
||||
|
||||
VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
|
||||
VkPipeline depth_only_pipeline[3];
|
||||
VkPipeline stencil_only_pipeline[5];
|
||||
} blit2d[1 + MAX_SAMPLES_LOG2];
|
||||
|
||||
VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
|
||||
VkPipeline stencil_only_pipeline[3];
|
||||
} blit2d;
|
||||
VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
|
||||
VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
|
||||
VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
|
||||
|
||||
struct {
|
||||
VkPipelineLayout img_p_layout;
|
||||
|
@@ -488,4 +488,11 @@ vk_to_non_srgb_format(VkFormat format)
|
||||
}
|
||||
}
|
||||
|
||||
static inline unsigned
|
||||
vk_format_get_nr_components(VkFormat format)
|
||||
{
|
||||
const struct vk_format_description *desc = vk_format_description(format);
|
||||
return desc->nr_channels;
|
||||
}
|
||||
|
||||
#endif /* VK_FORMAT_H */
|
||||
|
@@ -501,6 +501,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
|
||||
bo->size = result.alloc_size;
|
||||
bo->is_shared = true;
|
||||
bo->ws = ws;
|
||||
bo->ref_count = 1;
|
||||
radv_amdgpu_add_buffer_to_global_list(bo);
|
||||
return (struct radeon_winsys_bo *)bo;
|
||||
error_va_map:
|
||||
|
@@ -78,7 +78,8 @@ def _valgrind(glcpp, filename):
|
||||
extra_args = parse_test_file(filename, nl_format='\n')
|
||||
|
||||
try:
|
||||
_, tmpfile = tempfile.mkstemp()
|
||||
fd, tmpfile = tempfile.mkstemp()
|
||||
os.close(fd)
|
||||
with open(filename, 'rb') as f:
|
||||
proc = subprocess.Popen(
|
||||
['valgrind', '--error-exitcode=31', '--log-file', tmpfile, glcpp] + extra_args,
|
||||
@@ -135,7 +136,8 @@ def _replace_test(args, replace):
|
||||
total += 1
|
||||
testfile = os.path.join(args.testdir, filename)
|
||||
try:
|
||||
_, tmpfile = tempfile.mkstemp()
|
||||
fd, tmpfile = tempfile.mkstemp()
|
||||
os.close(fd)
|
||||
with io.open(testfile, 'rt') as f:
|
||||
contents = f.read()
|
||||
with io.open(tmpfile, 'wt') as f:
|
||||
|
@@ -37,6 +37,8 @@ struct lower_returns_state {
|
||||
* needs to be predicated on the return flag variable.
|
||||
*/
|
||||
bool has_predicated_return;
|
||||
|
||||
bool removed_unreachable_code;
|
||||
};
|
||||
|
||||
static bool lower_returns_in_cf_list(struct exec_list *cf_list,
|
||||
@@ -162,8 +164,9 @@ lower_returns_in_block(nir_block *block, struct lower_returns_state *state)
|
||||
*/
|
||||
return false;
|
||||
} else {
|
||||
state->removed_unreachable_code = true;
|
||||
nir_cf_delete(&list);
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -262,9 +265,11 @@ nir_lower_returns_impl(nir_function_impl *impl)
|
||||
state.loop = NULL;
|
||||
state.return_flag = NULL;
|
||||
state.has_predicated_return = false;
|
||||
state.removed_unreachable_code = false;
|
||||
nir_builder_init(&state.builder, impl);
|
||||
|
||||
bool progress = lower_returns_in_cf_list(&impl->body, &state);
|
||||
progress = progress || state.removed_unreachable_code;
|
||||
|
||||
if (progress) {
|
||||
nir_metadata_preserve(impl, nir_metadata_none);
|
||||
|
@@ -1419,11 +1419,11 @@ apply_var_decoration(struct vtn_builder *b, nir_variable *nir_var,
|
||||
case SpvBuiltInTessLevelInner:
|
||||
nir_var->data.compact = true;
|
||||
break;
|
||||
case SpvBuiltInSamplePosition:
|
||||
nir_var->data.origin_upper_left = b->origin_upper_left;
|
||||
/* fallthrough */
|
||||
case SpvBuiltInFragCoord:
|
||||
nir_var->data.pixel_center_integer = b->pixel_center_integer;
|
||||
/* fallthrough */
|
||||
case SpvBuiltInSamplePosition:
|
||||
nir_var->data.origin_upper_left = b->origin_upper_left;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
@@ -864,19 +864,22 @@ dri2_x11_swap_buffers_msc(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw,
|
||||
if (draw->Type == EGL_PIXMAP_BIT || draw->Type == EGL_PBUFFER_BIT)
|
||||
return 0;
|
||||
|
||||
if (draw->SwapBehavior == EGL_BUFFER_PRESERVED || !dri2_dpy->swap_available)
|
||||
return dri2_copy_region(drv, disp, draw, dri2_surf->region) ? 0 : -1;
|
||||
if (draw->SwapBehavior == EGL_BUFFER_PRESERVED || !dri2_dpy->swap_available) {
|
||||
swap_count = dri2_copy_region(drv, disp, draw, dri2_surf->region) ? 0 : -1;
|
||||
} else {
|
||||
dri2_flush_drawable_for_swapbuffers(disp, draw);
|
||||
|
||||
dri2_flush_drawable_for_swapbuffers(disp, draw);
|
||||
cookie = xcb_dri2_swap_buffers_unchecked(dri2_dpy->conn,
|
||||
dri2_surf->drawable, msc_hi,
|
||||
msc_lo, divisor_hi, divisor_lo,
|
||||
remainder_hi, remainder_lo);
|
||||
|
||||
cookie = xcb_dri2_swap_buffers_unchecked(dri2_dpy->conn, dri2_surf->drawable,
|
||||
msc_hi, msc_lo, divisor_hi, divisor_lo, remainder_hi, remainder_lo);
|
||||
reply = xcb_dri2_swap_buffers_reply(dri2_dpy->conn, cookie, NULL);
|
||||
|
||||
reply = xcb_dri2_swap_buffers_reply(dri2_dpy->conn, cookie, NULL);
|
||||
|
||||
if (reply) {
|
||||
swap_count = (((int64_t)reply->swap_hi) << 32) | reply->swap_lo;
|
||||
free(reply);
|
||||
if (reply) {
|
||||
swap_count = (((int64_t)reply->swap_hi) << 32) | reply->swap_lo;
|
||||
free(reply);
|
||||
}
|
||||
}
|
||||
|
||||
/* Since we aren't watching for the server's invalidate events like we're
|
||||
|
@@ -138,8 +138,7 @@ u_transfer_helper_resource_destroy(struct pipe_screen *pscreen,
|
||||
if (helper->vtbl->get_stencil) {
|
||||
struct pipe_resource *stencil = helper->vtbl->get_stencil(prsc);
|
||||
|
||||
if (stencil)
|
||||
helper->vtbl->resource_destroy(pscreen, stencil);
|
||||
pipe_resource_reference(&stencil, NULL);
|
||||
}
|
||||
|
||||
helper->vtbl->resource_destroy(pscreen, prsc);
|
||||
|
@@ -477,12 +477,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
|
||||
|
||||
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
||||
/* TODO: Indirect indexing of GS inputs is unimplemented. */
|
||||
return shader != PIPE_SHADER_GEOMETRY &&
|
||||
(sscreen->llvm_has_working_vgpr_indexing ||
|
||||
/* TCS and TES load inputs directly from LDS or
|
||||
* offchip memory, so indirect indexing is trivial. */
|
||||
shader == PIPE_SHADER_TESS_CTRL ||
|
||||
shader == PIPE_SHADER_TESS_EVAL);
|
||||
if (shader == PIPE_SHADER_GEOMETRY)
|
||||
return 0;
|
||||
|
||||
if (shader == PIPE_SHADER_VERTEX &&
|
||||
!sscreen->llvm_has_working_vgpr_indexing)
|
||||
return 0;
|
||||
|
||||
/* TCS and TES load inputs directly from LDS or offchip
|
||||
* memory, so indirect indexing is always supported.
|
||||
* PS has to support indirect indexing, because we can't
|
||||
* lower that to TEMPs for INTERP instructions.
|
||||
*/
|
||||
return 1;
|
||||
|
||||
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
||||
return sscreen->llvm_has_working_vgpr_indexing ||
|
||||
|
@@ -353,7 +353,7 @@ OMX_ERRORTYPE enc_LoadImage_common(vid_enc_PrivateType * priv, OMX_VIDEO_PORTDEF
|
||||
blit.src.resource = inp->resource;
|
||||
blit.src.format = inp->resource->format;
|
||||
|
||||
blit.src.box.x = 0;
|
||||
blit.src.box.x = -1;
|
||||
blit.src.box.y = def->nFrameHeight;
|
||||
blit.src.box.width = def->nFrameWidth;
|
||||
blit.src.box.height = def->nFrameHeight / 2 ;
|
||||
@@ -367,11 +367,11 @@ OMX_ERRORTYPE enc_LoadImage_common(vid_enc_PrivateType * priv, OMX_VIDEO_PORTDEF
|
||||
blit.dst.box.depth = 1;
|
||||
blit.filter = PIPE_TEX_FILTER_NEAREST;
|
||||
|
||||
blit.mask = PIPE_MASK_G;
|
||||
blit.mask = PIPE_MASK_R;
|
||||
priv->s_pipe->blit(priv->s_pipe, &blit);
|
||||
|
||||
blit.src.box.x = 1;
|
||||
blit.mask = PIPE_MASK_R;
|
||||
blit.src.box.x = 0;
|
||||
blit.mask = PIPE_MASK_G;
|
||||
priv->s_pipe->blit(priv->s_pipe, &blit);
|
||||
priv->s_pipe->flush(priv->s_pipe, NULL, 0);
|
||||
|
||||
|
@@ -21,10 +21,9 @@
|
||||
libgraw_xlib = shared_library(
|
||||
'graw_xlib',
|
||||
['graw_xlib.c'],
|
||||
c_args : ['-DGALLIUM_TRACE', '-DGALLIUM_RBUG'],
|
||||
include_directories : [inc_common, inc_gallium_drivers, inc_gallium_winsys],
|
||||
link_with : [
|
||||
libgraw_util, libtrace, librbug, libmesa_util, libgallium, libws_xlib
|
||||
libgraw_util, libmesa_util, libgallium, libws_xlib
|
||||
],
|
||||
dependencies : [dep_thread, driver_swrast],
|
||||
version : '1.0',
|
||||
|
@@ -842,6 +842,8 @@ fs_inst::size_read(int arg) const
|
||||
case SHADER_OPCODE_TYPED_ATOMIC:
|
||||
case SHADER_OPCODE_TYPED_SURFACE_READ:
|
||||
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
|
||||
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
|
||||
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
|
||||
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
|
||||
case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
|
||||
case SHADER_OPCODE_BYTE_SCATTERED_READ:
|
||||
|
@@ -334,6 +334,31 @@ public:
|
||||
opcode != BRW_OPCODE_IF &&
|
||||
opcode != BRW_OPCODE_WHILE));
|
||||
}
|
||||
|
||||
bool reads_g0_implicitly() const
|
||||
{
|
||||
switch (opcode) {
|
||||
case SHADER_OPCODE_TEX:
|
||||
case SHADER_OPCODE_TXL:
|
||||
case SHADER_OPCODE_TXD:
|
||||
case SHADER_OPCODE_TXF:
|
||||
case SHADER_OPCODE_TXF_CMS_W:
|
||||
case SHADER_OPCODE_TXF_CMS:
|
||||
case SHADER_OPCODE_TXF_MCS:
|
||||
case SHADER_OPCODE_TXS:
|
||||
case SHADER_OPCODE_TG4:
|
||||
case SHADER_OPCODE_TG4_OFFSET:
|
||||
case SHADER_OPCODE_SAMPLEINFO:
|
||||
case VS_OPCODE_PULL_CONSTANT_LOAD:
|
||||
case GS_OPCODE_SET_PRIMITIVE_ID:
|
||||
case GS_OPCODE_GET_INSTANCE_ID:
|
||||
case SHADER_OPCODE_GEN4_SCRATCH_READ:
|
||||
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
|
@@ -705,7 +705,7 @@ static inline struct brw_reg
|
||||
brw_imm_w(int16_t w)
|
||||
{
|
||||
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
|
||||
imm.d = w | (w << 16);
|
||||
imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16;
|
||||
return imm;
|
||||
}
|
||||
|
||||
|
@@ -1267,6 +1267,9 @@ vec4_instruction_scheduler::calculate_deps()
|
||||
}
|
||||
}
|
||||
|
||||
if (inst->reads_g0_implicitly())
|
||||
add_dep(last_fixed_grf_write, n);
|
||||
|
||||
if (!inst->is_send_from_grf()) {
|
||||
for (int i = 0; i < inst->mlen; i++) {
|
||||
/* It looks like the MRF regs are released in the send
|
||||
|
@@ -580,9 +580,11 @@ brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
||||
reg->d = -reg->d;
|
||||
return true;
|
||||
case BRW_REGISTER_TYPE_W:
|
||||
case BRW_REGISTER_TYPE_UW:
|
||||
reg->d = -(int16_t)reg->ud;
|
||||
case BRW_REGISTER_TYPE_UW: {
|
||||
uint16_t value = -(int16_t)reg->ud;
|
||||
reg->ud = value | (uint32_t)value << 16;
|
||||
return true;
|
||||
}
|
||||
case BRW_REGISTER_TYPE_F:
|
||||
reg->f = -reg->f;
|
||||
return true;
|
||||
@@ -618,9 +620,11 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
||||
case BRW_REGISTER_TYPE_D:
|
||||
reg->d = abs(reg->d);
|
||||
return true;
|
||||
case BRW_REGISTER_TYPE_W:
|
||||
reg->d = abs((int16_t)reg->ud);
|
||||
case BRW_REGISTER_TYPE_W: {
|
||||
uint16_t value = abs((int16_t)reg->ud);
|
||||
reg->ud = value | (uint32_t)value << 16;
|
||||
return true;
|
||||
}
|
||||
case BRW_REGISTER_TYPE_F:
|
||||
reg->f = fabsf(reg->f);
|
||||
return true;
|
||||
|
@@ -508,12 +508,12 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct anv_block_state *state)
|
||||
assert(center_bo_offset >= back_used);
|
||||
|
||||
/* Make sure we don't shrink the back end of the pool */
|
||||
if (center_bo_offset < pool->back_state.end)
|
||||
center_bo_offset = pool->back_state.end;
|
||||
if (center_bo_offset < back_required)
|
||||
center_bo_offset = back_required;
|
||||
|
||||
/* Make sure that we don't shrink the front end of the pool */
|
||||
if (size - center_bo_offset < pool->state.end)
|
||||
center_bo_offset = size - pool->state.end;
|
||||
if (size - center_bo_offset < front_required)
|
||||
center_bo_offset = size - front_required;
|
||||
}
|
||||
|
||||
assert(center_bo_offset % PAGE_SIZE == 0);
|
||||
|
@@ -1179,6 +1179,7 @@ PFN_vkVoidFunction anv_GetInstanceProcAddr(
|
||||
|
||||
LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
|
||||
LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceLayerProperties);
|
||||
LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceVersion);
|
||||
LOOKUP_ANV_ENTRYPOINT(CreateInstance);
|
||||
|
||||
#undef LOOKUP_ANV_ENTRYPOINT
|
||||
|
@@ -927,7 +927,7 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims,
|
||||
!_mesa_is_srgb_format(gl_format);
|
||||
struct brw_context *brw = (struct brw_context*) ctx;
|
||||
const struct gen_device_info *devinfo = &brw->screen->devinfo;
|
||||
if (devinfo->gen == 9 && is_linear_astc)
|
||||
if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
|
||||
flush_astc_denorms(ctx, dims, texImage,
|
||||
xoffset, yoffset, zoffset,
|
||||
width, height, depth);
|
||||
|
@@ -732,6 +732,6 @@ endif
|
||||
if with_glx == 'xlib'
|
||||
subdir('drivers/x11')
|
||||
endif
|
||||
if with_tests
|
||||
if with_tests and dri_drivers != []
|
||||
subdir('main/tests')
|
||||
endif
|
||||
|
@@ -82,7 +82,9 @@ if with_gallium
|
||||
subdir('gallium')
|
||||
# This has to be here since it requires libgallium, and subdir cannot
|
||||
# contain ..
|
||||
subdir('mesa/state_tracker/tests')
|
||||
if with_tests
|
||||
subdir('mesa/state_tracker/tests')
|
||||
endif
|
||||
endif
|
||||
|
||||
# This must be after at least mesa, glx, and gallium, since libgl will be
|
||||
|
@@ -311,6 +311,7 @@ util_queue_init(struct util_queue *queue,
|
||||
goto fail;
|
||||
|
||||
(void) mtx_init(&queue->lock, mtx_plain);
|
||||
(void) mtx_init(&queue->finish_lock, mtx_plain);
|
||||
|
||||
queue->num_queued = 0;
|
||||
cnd_init(&queue->has_queued_cond);
|
||||
@@ -398,6 +399,7 @@ util_queue_destroy(struct util_queue *queue)
|
||||
|
||||
cnd_destroy(&queue->has_space_cond);
|
||||
cnd_destroy(&queue->has_queued_cond);
|
||||
mtx_destroy(&queue->finish_lock);
|
||||
mtx_destroy(&queue->lock);
|
||||
free(queue->jobs);
|
||||
free(queue->threads);
|
||||
@@ -529,6 +531,12 @@ util_queue_finish(struct util_queue *queue)
|
||||
|
||||
util_barrier_init(&barrier, queue->num_threads);
|
||||
|
||||
/* If 2 threads were adding jobs for 2 different barries at the same time,
|
||||
* a deadlock would happen, because 1 barrier requires that all threads
|
||||
* wait for it exclusively.
|
||||
*/
|
||||
mtx_lock(&queue->finish_lock);
|
||||
|
||||
for (unsigned i = 0; i < queue->num_threads; ++i) {
|
||||
util_queue_fence_init(&fences[i]);
|
||||
util_queue_add_job(queue, &barrier, &fences[i], util_queue_finish_execute, NULL);
|
||||
@@ -538,6 +546,7 @@ util_queue_finish(struct util_queue *queue)
|
||||
util_queue_fence_wait(&fences[i]);
|
||||
util_queue_fence_destroy(&fences[i]);
|
||||
}
|
||||
mtx_unlock(&queue->finish_lock);
|
||||
|
||||
util_barrier_destroy(&barrier);
|
||||
|
||||
|
@@ -200,6 +200,7 @@ struct util_queue_job {
|
||||
/* Put this into your context. */
|
||||
struct util_queue {
|
||||
const char *name;
|
||||
mtx_t finish_lock; /* only for util_queue_finish */
|
||||
mtx_t lock;
|
||||
cnd_t has_queued_cond;
|
||||
cnd_t has_space_cond;
|
||||
|
Reference in New Issue
Block a user