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19 Commits

Author SHA1 Message Date
Dylan Baker
131f12d49f Version: Bump for rc2 2019-02-05 11:49:03 -08:00
Emil Velikov
f8f68c41a1 anv: wire up the state_pool_padding test
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 927ba12b53 ("anv/tests: Adding test for the state_pool padding.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com><Paste>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit 8943eb8f03)
2019-02-05 11:41:54 -08:00
Michel Dänzer
15e2fc16e9 loader/dri3: Use strlen instead of sizeof for creating VRR property atom
sizeof counts the terminating null character as well, so that also
contributed to the ID computed for the X11 atom. But the convention is
for only the non-null characters to contribute to the atom ID.

Fixes: 2e12fe425f "loader/dri3: Enable adaptive_sync via
                     _VARIABLE_REFRESH property"
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit c0a540f320)
2019-02-05 11:41:48 -08:00
Marek Olšák
3f5099180d radeonsi: fix crashing performance counters (division by zero)
Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c"
(cherry picked from commit 742d6cdb42)
2019-02-05 09:05:51 -08:00
Danylo Piliaiev
9667d89fe6 anv: Fix VK_EXT_transform_feedback working with varyings packed in PSIZ
Transform feedback did not set correct SO_DECL.ComponentMask for
varyings packed in VARYING_SLOT_PSIZ:
 gl_Layer         - VARYING_SLOT_LAYER    in VARYING_SLOT_PSIZ.y
 gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
 gl_PointSize     - VARYING_SLOT_PSIZ     in VARYING_SLOT_PSIZ.w

Fixes: 36ee2fd61c "anv: Implement the basic form of VK_EXT_transform_feedback"

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 64d3b148fe)
2019-02-04 09:16:37 -08:00
Jason Ekstrand
c6649ca94d intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions.  If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.

Fixes: 232ed89802 "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b4f0d062cd)
2019-02-04 09:16:21 -08:00
Neha Bhende
89f84f98e0 st/mesa: Fix topogun-1.06-orc-84k-resize.trace crash
We need to initialize all fields in rs->prim explicitly while
creating new rastpos stage.

Fixes: bac8534267 ("st/mesa: allow glDrawElements to work with GL_SELECT
feedback")

v2: Initializing all fields in rs->prim as per Ilia.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 69d736b17a)
2019-02-01 09:19:29 -08:00
Ernestas Kulik
c824f8031c v3d: Fix leak in resource setup error path
Reported by Coverity: in the case of unsupported modifier request, the
code does not jump to the “fail” label to destroy the acquired resource.

CID: 1435704
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes: 45bb8f2957 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
(cherry picked from commit 90458bef54)
2019-01-31 11:12:29 -08:00
Eric Anholt
7fdb08375f v3d: Fix image_load_store clamping of signed integer stores.
This was copy-and-paste fail, that oddly showed up in the CTS's
reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i
to rgba8i or reinterprets to other signed int formats.

Fixes: 6281f26f06 ("v3d: Add support for shader_image_load_store.")
(cherry picked from commit ab4d5775b0)
2019-01-31 11:09:28 -08:00
Eric Anholt
535cc4f1d5 mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.
One of the CTS cases tries to invalidate just stencil of packed
depth/stencil, and we incorrectly lost the depth contents.

Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil
Fixes: 0c42b5f3cb ("mesa: wire up InvalidateFramebuffer")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

(cherry picked from commit db2ae51121)
2019-01-31 11:09:05 -08:00
Rob Clark
7f91ae20b9 freedreno: more fixing release tarball
Fixes: aa0fed10d3 freedreno: move ir3 to common location
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit 39cfdf9930)
2019-01-31 11:08:53 -08:00
Rob Clark
0a72505a9e freedreno: fix release tarball
Fixes: b4476138d5 freedreno: move drm to common location
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit e252656d14)
2019-01-31 11:08:11 -08:00
Samuel Pitoiset
31d0079a20 radv/winsys: fix hash when adding internal buffers
This fixes serious stuttering in Shadow Of The Tomb Raider.

Fixes: 50fd253bd6 ("radv/winsys: Add priority handling during submit.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 9c762c01c8)
2019-01-31 11:07:40 -08:00
Ernestas Kulik
4d1dd3b0cd vc4: Fix leak in HW queries error path
Reported by Coverity: in the case where there exist hardware and
non-hardware queries, the code does not jump to err_free_query and leaks
the query.

CID: 1430194
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Fixes: 9ea90ffb98 ("broadcom/vc4: Add support for HW perfmon")
(cherry picked from commit f6e49d5ad0)
2019-01-31 11:07:26 -08:00
Emil Velikov
45d1aa2f6c vc4: Declare the last cpu pointer as being modified in NEON asm.
Earlier commit addressed 7 of the 8 instances available.

v2: Rebase patch back to master (by anholt)

Cc: Carsten Haitzler (Rasterman) <raster@rasterman.com>
Cc: Eric Anholt <eric@anholt.net>
Fixes: 300d3ae8b1 ("vc4: Declare the cpu pointers as being modified in NEON asm.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 385843ac3c)
2019-01-31 10:59:58 -08:00
Dylan Baker
2fddad9e3f VERSION: bump to 19.0.0-rc1 2019-01-30 14:10:12 -08:00
Dylan Baker
2b603ee4f1 android,autotools,i965: Fix location of float64_glsl.h
Android.mk and autotools disagree about where generated files should
go, which wasn't a problem until we wanted to build a dist
tarball. This corrects the problme by changing the output and include
paths to be the same on android and autotools (meson already has the
correct include path).

Fixes: 7d7b30835c
       ("automake: Fix path to generated source")
2019-01-30 14:10:12 -08:00
Dylan Baker
e7f6a5d17f automake: Add --enable-autotools to distcheck flags
Fixes: e68777c87c
       ("autotools: Deprecate the use of autotools")
2019-01-30 09:45:14 -08:00
Dylan Baker
1f5f12687f configure: Bump SWR LLVM requirement to 7
It is currently impossible to build a dist tarball that works when SWR
requires LLVM 6. To generate the tarball we'd need to configure with
LLVM 6, which is fine. But to build the dist check we need LLVM 7, as
RadeonSI and RadV require that version. Unfortunately the headers
genererated with LLVM 6 don't compile with LLVM 7, the API has changed
between the two versions.

I weighed a couple of options here. One would be to ship an
unbootstrapped tarball generated with meson. This would fix the issue
by not bootstrapping, so whatever version of LLVM used would work
because the SWR headers would be generated at compile
time. Unfortunately this would involve some heavy modifications to the
infastructure used to upload the tarballs, and I've decided not to
persue this.
2019-01-30 09:27:14 -08:00
20 changed files with 78 additions and 25 deletions

View File

@@ -22,6 +22,7 @@
SUBDIRS = src
AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-autotools \
--enable-dri \
--enable-dri3 \
--enable-egl \

View File

@@ -1 +1 @@
19.0.0-devel
19.0.0-rc2

View File

@@ -122,7 +122,7 @@ LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=7.0.0
LLVM_REQUIRED_RADV=7.0.0
LLVM_REQUIRED_SWR=6.0.0
LLVM_REQUIRED_SWR=7.0.0
dnl Check for progs
AC_PROG_CPP
@@ -2845,8 +2845,8 @@ if test -n "$with_gallium_drivers"; then
fi
# XXX: Keep in sync with LLVM_REQUIRED_SWR
AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x6.0.0 -a \
"x$LLVM_VERSION" != x6.0.1)
AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x7.0.0 -a \
"x$LLVM_VERSION" != x7.0.1)
if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"

View File

@@ -543,7 +543,7 @@ static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
cs->handles[cs->num_buffers].bo_handle = bo;
cs->handles[cs->num_buffers].bo_priority = priority;
hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
cs->buffer_hash_table[hash] = cs->num_buffers;
++cs->num_buffers;

View File

@@ -159,9 +159,8 @@ v3d_store_utile(void *gpu, uint32_t gpu_stride,
* d0-d7.
*/
"vstm %[gpu], {q0, q1, q2, q3}\n"
:
: [cpu] "+r"(cpu)
: [gpu] "r"(gpu),
[cpu] "r"(cpu),
[cpu_stride] "r"(cpu_stride)
: "q0", "q1", "q2", "q3");
return;

View File

@@ -156,7 +156,7 @@ pack_sint(nir_builder *b, nir_ssa_def *color, const unsigned *bits,
int num_components)
{
color = nir_channels(b, color, (1 << num_components) - 1);
color = nir_format_clamp_uint(b, color, bits);
color = nir_format_clamp_sint(b, color, bits);
return pack_bits(b, color, bits, num_components, true);
}

View File

@@ -104,6 +104,6 @@ $(intermediates)/glsl/ir_expression_operation_strings.h: $(LOCAL_PATH)/glsl/ir_e
@mkdir -p $(dir $@)
$(hide) $(MESA_PYTHON2) $< strings > $@
$(intermediates)/compiler/glsl/float64_glsl.h: $(LOCAL_PATH)/glsl/xxd.py
$(intermediates)/glsl/float64_glsl.h: $(LOCAL_PATH)/glsl/xxd.py
@mkdir -p $(dir $@)
$(hide) $(MESA_PYTHON2) $< $(MESA_TOP)/src/compiler/glsl/float64.glsl $@ -n float64_source > $@

View File

@@ -45,6 +45,7 @@ TESTS =
BUILT_SOURCES =
CLEANFILES =
EXTRA_DIST = \
meson.build \
drm/meson.build \
ir3/ir3_nir_trig.py \
ir3/meson.build

View File

@@ -23,4 +23,6 @@ libfreedreno_la_SOURCES = \
$(a6xx_SOURCES) \
$(ir3_SOURCES)
EXTRA_DIST = meson.build
EXTRA_DIST = \
ir3/ir3_cmdline.c \
meson.build

View File

@@ -1333,7 +1333,7 @@ void si_init_perfcounters(struct si_screen *screen)
for (i = 0; i < num_blocks; ++i) {
struct si_pc_block *block = &pc->blocks[i];
block->b = &blocks[i];
block->num_instances = block->b->instances;
block->num_instances = MAX2(1, block->b->instances);
if (!strcmp(block->b->b->name, "CB") ||
!strcmp(block->b->b->name, "DB"))

View File

@@ -780,7 +780,7 @@ v3d_resource_create_with_modifiers(struct pipe_screen *pscreen,
rsc->tiled = false;
} else {
fprintf(stderr, "Unsupported modifier requested\n");
return NULL;
goto fail;
}
rsc->internal_format = prsc->format;

View File

@@ -132,7 +132,7 @@ vc4_create_batch_query(struct pipe_context *pctx, unsigned num_queries,
/* We can't mix HW and non-HW queries. */
if (nhwqueries && nhwqueries != num_queries)
return NULL;
goto err_free_query;
if (!nhwqueries)
return (struct pipe_query *)query;

View File

@@ -253,6 +253,7 @@ VULKAN_TESTS = \
vulkan/tests/block_pool_no_free \
vulkan/tests/state_pool_no_free \
vulkan/tests/state_pool_free_list_only \
vulkan/tests/state_pool_padding \
vulkan/tests/state_pool
VULKAN_TEST_LDADD = \
@@ -274,6 +275,10 @@ vulkan_tests_state_pool_free_list_only_CFLAGS = $(VULKAN_CFLAGS)
vulkan_tests_state_pool_free_list_only_CPPFLAGS = $(VULKAN_CPPFLAGS)
vulkan_tests_state_pool_free_list_only_LDADD = $(VULKAN_TEST_LDADD)
vulkan_tests_state_pool_padding_CFLAGS = $(VULKAN_CFLAGS)
vulkan_tests_state_pool_padding_CPPFLAGS = $(VULKAN_CPPFLAGS)
vulkan_tests_state_pool_padding_LDADD = $(VULKAN_TEST_LDADD)
vulkan_tests_state_pool_CFLAGS = $(VULKAN_CFLAGS)
vulkan_tests_state_pool_CPPFLAGS = $(VULKAN_CPPFLAGS)
vulkan_tests_state_pool_LDADD = $(VULKAN_TEST_LDADD)

View File

@@ -667,15 +667,14 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
* messages adding a node interference to the grf127_send_hack_node.
* This node has a fixed asignment to grf127.
*
* We don't apply it to SIMD16 because previous code avoids any register
* overlap between sources and destination.
* We don't apply it to SIMD16 instructions because previous code avoids
* any register overlap between sources and destination.
*/
ra_set_node_reg(g, grf127_send_hack_node, 127);
if (dispatch_width == 8) {
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->is_send_from_grf() && inst->dst.file == VGRF)
ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
}
foreach_block_and_inst(block, fs_inst, inst, cfg) {
if (inst->exec_size < 16 && inst->is_send_from_grf() &&
inst->dst.file == VGRF)
ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
}
if (spilled_any_registers) {

View File

@@ -1211,13 +1211,30 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline,
hole_dwords -= 4;
}
int varying = output->location;
uint8_t component_mask = output->component_mask;
/* VARYING_SLOT_PSIZ contains three scalar fields packed together:
* - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
* - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
* - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
*/
if (varying == VARYING_SLOT_LAYER) {
varying = VARYING_SLOT_PSIZ;
component_mask = 1 << 1; // SO_DECL_COMPMASK_Y
} else if (varying == VARYING_SLOT_VIEWPORT) {
varying = VARYING_SLOT_PSIZ;
component_mask = 1 << 2; // SO_DECL_COMPMASK_Z
} else if (varying == VARYING_SLOT_PSIZ) {
component_mask = 1 << 3; // SO_DECL_COMPMASK_W
}
next_offset[buffer] = output->offset +
__builtin_popcount(output->component_mask) * 4;
__builtin_popcount(component_mask) * 4;
so_decl[stream][decls[stream]++] = (struct GENX(SO_DECL)) {
.OutputBufferSlot = buffer,
.RegisterIndex = vue_map->varying_to_slot[output->location],
.ComponentMask = output->component_mask,
.RegisterIndex = vue_map->varying_to_slot[varying],
.ComponentMask = component_mask,
};
}

View File

@@ -111,7 +111,7 @@ set_adaptive_sync_property(xcb_connection_t *conn, xcb_drawable_t drawable,
xcb_intern_atom_reply_t* reply;
xcb_void_cookie_t check;
cookie = xcb_intern_atom(conn, 0, sizeof(name), name);
cookie = xcb_intern_atom(conn, 0, strlen(name), name);
reply = xcb_intern_atom_reply(conn, cookie, NULL);
if (reply == NULL)
return;

View File

@@ -34,6 +34,8 @@ AM_CFLAGS = \
-I$(top_builddir)/src/util \
-I$(top_srcdir)/src/mesa/drivers/dri/common \
-I$(top_srcdir)/src/gtest/include \
-I$(top_builddir)/src/compiler \
-I$(top_srcdir)/src/compiler \
-I$(top_builddir)/src/compiler/glsl \
-I$(top_builddir)/src/compiler/nir \
-I$(top_srcdir)/src/compiler/nir \

View File

@@ -42,7 +42,7 @@
#include "compiler/glsl/ir.h"
#include "compiler/glsl/program.h"
#include "compiler/glsl/glsl_to_nir.h"
#include "compiler/glsl/float64_glsl.h"
#include "glsl/float64_glsl.h"
#include "brw_program.h"
#include "brw_context.h"

View File

@@ -4691,6 +4691,29 @@ discard_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb,
if (!att)
continue;
/* If we're asked to invalidate just depth or just stencil, but the
* attachment is packed depth/stencil, then we can only use
* Driver.DiscardFramebuffer if the attachments list includes both depth
* and stencil and they both point at the same renderbuffer.
*/
if ((attachments[i] == GL_DEPTH_ATTACHMENT ||
attachments[i] == GL_STENCIL_ATTACHMENT) &&
(!att->Renderbuffer ||
att->Renderbuffer->_BaseFormat == GL_DEPTH_STENCIL)) {
GLenum other_format = (attachments[i] == GL_DEPTH_ATTACHMENT ?
GL_STENCIL_ATTACHMENT : GL_DEPTH_ATTACHMENT);
bool has_both = false;
for (int j = 0; j < numAttachments; j++) {
if (attachments[j] == other_format)
has_both = true;
break;
}
if (fb->Attachment[BUFFER_DEPTH].Renderbuffer !=
fb->Attachment[BUFFER_STENCIL].Renderbuffer || !has_both)
continue;
}
ctx->Driver.DiscardFramebuffer(ctx, fb, att);
}
}

View File

@@ -208,6 +208,10 @@ new_draw_rastpos_stage(struct gl_context *ctx, struct draw_context *draw)
rs->prim.end = 1;
rs->prim.start = 0;
rs->prim.count = 1;
rs->prim.pad = 0;
rs->prim.num_instances = 1;
rs->prim.base_instance = 0;
rs->prim.is_indirect = 0;
return rs;
}